24AA52-/ST_技术文档

24AA52/24LCS52

2K 2.2V I²C^™Serial EEPROM with Software Write-Protect

Features:

Description:

• Single supply with operation down to 1.8V

• Low-power CMOS technology:

The Microchip Technology Inc. 24AA52/24LCS52

(24XXX52*) is a 2 Kbit Electrically Erasable PROM

capable of operation across a broad voltage range

(1.8V to 5.5V). This device has a software write-protect

feature for the lower half of the array, as well as an

external pin that can be used to write-protect the entire

array. The software write-protect feature is enabled by

sending the device a special command. Once this

feature has been enabled, it cannot be reversed. In

addition to the software protect feature, there is a WP

pin that can be used to write-protect the entire array,

regardless of whether the software write-protect

register has been written or not. This allows the system

designer to protect none, half, or all of the array,

depending on the application. The device is organized

as one block of 256 x 8-bit memory with a 2-wire serial

interface. Low-voltage design permits operation down

to 1.8V, with standby and active currents of only 1 μA

and 1 mA, respectively. The 24XXX52 also has a page

write capability for up to 16 bytes of data. The 24XXX52

is available in the standard 8-pin PDIP, surface mount

SOIC, TSSOP, MSOP and DFN packages.

- 1 mA active current, typical

- 1 μA standby current, typical (I-temp)

• Organized as 1 block of 256 bytes (256 x 8)

• Software write protection for lower 128 bytes

• Hardware write protection for entire array

• 2-wire serial interface bus, I²C™ compatible

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (24AA52) and 400 kHz (24LCS52)

compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 16 bytes

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, MSOP and DFN

packages

• Pb-free finishes available

Block Diagram

• Available for extended temperature ranges:

- Industrial (I): -40°C to +85°C

WP

A0 A1 A2

HV Generator

Device Selection Table

Software write

protected area

(00h-7Fh)

I/O

Control

Logic

Memory

Control

Logic

Part

VCC

Max Clock

Frequency

Temp

Ranges

XDEC

Number

Range

400 kHz⁽¹⁾

400 kHz

I

Standard

Array

24AA52

1.8-5.5

2.2-5.5

SDA SCL

24LCS52

Note 1: 100 kHz for VCC <2.2V

VCC

VSS

Write-Protect

Circuitry

YDEC

Package Types

PDIP/SOIC/TSSOP/MSOP/DFN

Sense Amp.

R/W Control

A0

A1

1

2

3

4

8

VCC

1

VCC

WP

A0

A1

8

7

6

5

7

6

5

WP

2

3

4

SCL

SDA

A2

SCL

SDA

VSS

*24XXX52 is used in this document as a generic part number

for the 24AA52/24LCS52 devices.

DS21166J-page 1

24AA52/24LCS52

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. These are stress ratings only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC SPECIFICATIONS

VCC = +1.8V to +5.5V

Industrial (I): TA = -40°C to +85°C

DC CHARACTERISTICS

Param.

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

D1

VIH

A0, A1, A2, SCL, SDA

and WP pins

—

D2

D3

D4

—

High-level input voltage

Low-level input voltage

0.7 VCC

—

0.3 VCC

—

V

VIL

0.2 VCC for VCC < 2.5V

VHYS

Hysteresis of Schmitt

Trigger inputs

0.05 VCC

(Note)

D5

D6

D7

D8

VOL

ILI

Low-level output voltage

Input leakage current

Output leakage current

—

0.40

±1

V

IOL = 3.0 mA, VCC = 2.5V

VIN = VSS or VCC

μA

pF

ILO

±1

VOUT = VSS or VCC

CIN,

Pin capacitance

10

VCC = 5.0V (Note)

COUT

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

D9

ICC write Operating current

ICC read

—

1.0

3.0

1.0

mA

μA

VCC = 5.5V, SCL = 400 kHz

—

D10

D11

0.20

ICCS

Standby current

—

0.36

—

1.0

—

Industrial

SDA = SCL = VCC

A0, A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

DS21166J-page 2

24AA52/24LCS52

TABLE 1-2:

AC SPECIFICATIONS

VCC = +1.8V to +5.5V

Industrial (I): TA = -40°C to +85°C

AC CHARACTERISTICS

Param.

Symbol

No.

Characteristic

Clock frequency

Min

Typ

Max

Units

Conditions

1

FCLK

THIGH

TLOW

TR

—

400

100

kHz 2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

2

Clock high time

Clock low time

600

4000

—

ns

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

3

1300

4700

—

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

4

SDA and SCL rise time

(Note 1)

—

300

1000

5

TF

SDA and SCL fall time

—

300

(Note 1)

6

THD:STA Start condition hold time

600

4000

—

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

7

TSU:STA Start condition setup

time

600

4700

—

8

THD:DAT Data input hold time

0

—

(Note 2)

9

TSU:DAT Data input setup time

100

250

—

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

10

11

12

TSU:STO Stop condition setup

time

600

4000

—

TAA

Output valid from clock

(Note 2)

—

900

3500

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

TBUF

Bus free time: Time the

bus must be free before

a new transmission can

start

1300

4700

—

2.2V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V (24AA52)

13

14

TOF

TSP

Output fall time from VIH 20 + 0.1 CB

—

250

ns

2.2V ≤ VCC ≤ 5.5V

minimum to VIL

maximum

—

1.8V ≤ VCC < 2.5V (24AA52)

Input filter spike

suppression

—

50

(Note 1 and Note 3)

(SDA and SCL pins)

15

16

TWC

—

Write cycle time

(byte or page)

—

5

ms

—

Endurance

1M

—

cycles 25°C, VCC = 5.0V, Block

mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site

at www.microchip.com.

DS21166J-page 3

24AA52/24LCS52

FIGURE 1-1:

BUS TIMING DATA

5

4

2

3

SCL

7

8

9

10

6

SDA

IN

14

12

11

SDA

OUT

FIGURE 1-2:

BUS TIMING START/STOP

D4

SCL

SDA

6

7

10

Start

Stop

DS21166J-page 4

24AA52/24LCS52

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24XXX52 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data, as a receiver. The bus has to be

controlled by a master device, which generates the

Serial Clock (SCL), controls the bus access and gener-

ates the Start and Stop conditions, while the 24XXX52

works as slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoretically, unlimited; although only the last sixteen

will be stored when doing a write operation. When an

overwrite does occur, it will replace data in a first-in,

first-out (FIFO) fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

3.5

Acknowledge

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Each receiving device, when addressed, is obliged to

generate an Acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse, which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note: The 24XXX52 does not generate any

Acknowledge

bits

if

an

internal

programming cycle is in progress.

3.1

Bus Not Busy (A)

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end-of-

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XXX52) will leave the data

line high to enable the master to generate the Stop

condition.

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS21166J-page 5

24AA52/24LCS52

After receiving another Acknowledge signal from the

24XXX52, the master device will transmit the data word

to be written into the addressed memory location. The

24XXX52 acknowledges again and the master gener-

ates a Stop condition. This initiates the internal write

cycle, which means that during this time, the 24XXX52

will not generate Acknowledge signals (Figure 4-1). If

an attempt is made to write to the array when the soft-

ware or hardware write protection has been enabled,

the device will acknowledge the command, but no data

will be written. The write cycle time must be observed

even if the write protection is enabled.

3.6

Device Addressing

A control byte is the first byte received following the

Start condition from the master device. The first part of

the control byte consists of a 4-bit control code which is

set to ‘1010’ for normal read and write operations and

‘0110’ for writing to the write-protect register. The

control byte is followed by three Chip Select bits (A2,

A1, A0). The Chip Select bits allow the use of up to

eight 24XXX52 devices on the same bus and are used

to determine which device is accessed. The Chip

Select bits in the control byte must correspond to the

logic levels on the corresponding A2, A1 and A0 pins

for the device to respond. The device will not acknowl-

edge if you attempt a Read command with the control

code set to ‘0110’.

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XXX52 in the same way

as in a byte write. Instead of generating a Stop condi-

tion, the master transmits up to 15 additional data bytes

to the 24XXX52, which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a Stop condition. Upon

receipt of each word, the four lower order Address

Pointer bits are internally incremented by one. The

higher order four bits of the word address remain

constant. If the master should transmit more than 16

bytes prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received, an

internal write cycle will begin (Figure 4-2). If an attempt

is made to write to the array when the hardware write

protection has been enabled, the device will acknowl-

edge the command, but no data will be written. The

write cycle time must be observed even if the write

protection is enabled.

The eighth bit of slave address determines if the master

device wants to read or write to the 24XXX52

(Figure 3-2). When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected.

Control

Code

Chip

Select

Operation

Read

R/W

1010

A2 A1 A0

1

0

Write

Set Write-Protect

Register

0110

A2 A1 A0

0

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

Start

Read/Write

Slave Address

R/W A

Note: Page write operations are limited to writing

bytes within

a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer multi-

ples of the page buffer size (or ‘page size’)

and end at addresses that are integer mul-

tiples of [page size – 1]. If a Page Write

command attempts to write across a phys-

ical page boundary, the result is that the

data wraps around to the beginning of the

current page (overwriting data previously

stored there), instead of being written to

the next page, as might be expected. It is

therefore necessary for the application

software to prevent page write operations

that would attempt to cross a page

boundary.

1

0

1

0

A2

A1

A0

OR

0

4.0

4.1

WRITE OPERATIONS

Byte Write

Following the Start signal from the master, the device

code(4 bits), the Chip Select bits (3 bits) and the R/W

bit, which is a logic low, are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow,

once it has generated an Acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the Address Pointer of the 24XXX52.

DS21166J-page 6

24AA52/24LCS52

FIGURE 4-1:

BYTE WRITE

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Word

Address

Data

SDA Line

S

P

A

C

K

A

C

K

A

C

K

Bus Activity

FIGURE 4-2:

PAGE WRITE

S

T

Bus Activity

Master

Control

Byte

Word

Address (n)

A

R

T

S

O

P

Data (n)

Data (n + 1)

Data (n + 15)

SDA Line

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

DS21166J-page 7

24AA52/24LCS52

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 5-1 for flow

diagram.

FIGURE 5-1:

ACKNOWLEDGE

POLLING FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

No

Yes

DS21166J-page 8

24AA52/24LCS52

6.0

WRITE PROTECTION

The 24XXX52 has a software write-protect feature that

allows the lower half of the array (addresses 00h-7Fh)

to be permanently write-protected, as well as a WP pin

that can be used to protect the entire array.

6.1

Software Write-Protect

The software write-protect feature is invoked by writing

to the write-protect register. This is done by sending a

command similar to a normal Write command. As shown

in Figure 6-1, the write-protect register is written by

sending a Write command with the slave address set to

‘0110’ instead of ‘1010’ and the address bits and data

bits are “don’t cares.” Once the software write-protect

register has been written, the device will not

acknowledge the ‘0110’ control byte.

FIGURE 6-1:

SETTING WRITE-PROTECT REGISTER

S

T

A

R

T

S

Bus Activity

Master

Control

Byte

Word

Address

T

Data

O

P

SDA Line

S

0

1

0

P

A

C

K

A

C

K

A

C

K

Bus Activity

6.2

Resetting the Software

Write-Protect Fuse

It is possible to reset the software write-protect feature

on the 24XXX52. This is done by sending a command

similar to setting the software write-protect command,

except the command is sent before the regular control

byte and is ‘1001’ . The full command will be shown in

Figure 6-2. In order for the command to work, a voltage

of Vcc + 5.5V must be applied to the WP pin and must

be sustained for 1μS before the command is given. The

customer should also allow for a 5 ms delay after the

Stop bit for TWC.

DS21166J-page 9

24AA52/24LCS52

FIGURE 6-2:

RESETTING WRITE-PROTECT FUSE (RWPF)

WP = VHH = VCC + 5.5V

S

T

A

R

T

1μs

TWC

S

T

O

P

RWPF

Command

Word

Address (0x09)

Control

Byte

Bus Activity

Master

Data (0xFF)

1 0 0 1 0 0 0 S 1 0 1 0 0 0 0 0

0 0 0 0 1 0 0 1

1 1 1 1 1 1 1 1

P

SDA Line

A

C

K

A

C

K

A

C

K

Bus Activity

Note:

Clock = 100 kHz, VDD = 1.8V to 5.5V

6.3

Hardware Write-Protect

The WP pin can be tied to VCC or VSS. If tied to VCC, the

entire array will be write-protected, regardless of

whether the software write-protect register has been

written or not. If the WP pin is set to VCC, it will prevent

the software write-protect register from being written. If

the WP is tied to VSS, write protection is determined by

the status of the software write-protect register for

addresses 00h-7Fh. Addresses 80h-FFh are solely

protected by the WP pin level.

DS21166J-page 10

24AA52/24LCS52

7.3

Sequential Read

7.0

READ OPERATION

Sequential reads are initiated in the same way as a

random read, with the exception that after the 24XXX52

transmits the first data byte, the master issues an

acknowledge, as opposed to a Stop condition in a

random read. This directs the 24XXX52 to transmit the

next sequentially addressed 8-bit word (Figure 7-3).

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

7.1

Current Address Read

To provide sequential reads, the 24XXX52 contains an

internal Address Pointer, which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

The 24XXX52 contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by ‘1’. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n+1. Upon receipt of

the slave address with R/W bit set to ‘1’, the 24XXX52

issues an acknowledge and transmits the 8-bit data

word. The master will not acknowledge the transfer, but

does generate a Stop condition and the 24XXX52

discontinues transmission (Figure 7-1).

7.4

Contiguous Addressing Across

Multiple Devices

The Chip Select bits (A2, A1, A0) can be used to

expand the contiguous address space for up to 16K bits

by adding up to eight 24XXX52 devices on the same

bus. In this case, software can use A0 of the control

byte as address bit A8; A1 as address bit A9, and A2

as address bit A10. It is not possible to sequentially

read across device boundaries.

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is done by sending the word address to the

24XXX52 as part of a write operation. Once the word

address is sent, the master generates a Start condition

following the acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. The master then issues the control byte again, but

with the R/W bit set to a ‘1’. The 24XXX52 then issues

an acknowledge and transmits the 8-bit data word. The

master will not acknowledge the transfer, but does

7.5

Noise Protection and Brown-Out

The 24XXX52 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

generate

a

Stop condition and the 24XXX52

discontinues transmission (Figure 7-2).

FIGURE 7-1:

CURRENT ADDRESS READ

S

T

A

R

Bus Activity

Master

Control

Byte

S

T

Data (n)

O

P

T

SDA Line

S

P

A

C

K

N

O

Bus Activity

A

C

K

DS21166J-page 11

24AA52/24LCS52

FIGURE 7-2:

RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Word

Address (n)

Control

Byte

Data (n)

S

P

S

SDA Line

A

C

K

A

C

K

A

C

K

N

O

Bus Activity

A

C

K

FIGURE 7-3:

SEQUENTIAL READ

S

T

O

P

Bus Activity

Master

Control

Byte

Data (n)

Data (n + 1)

Data (n + 2)

Data (n + X)

SDA Line

P

A

C

K

A

C

K

A

C

K

A

C

K

N

O

Bus Activity

A

C

K

DS21166J-page 12

24AA52/24LCS52

8.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 8-1.

TABLE 8-1:

Symbol

PIN FUNCTION TABLE

PDIP

SOIC

TSSOP

MSOP

DFN

Description

Chip Address Input

A0

A1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Chip Address Input

Ground

A2

VSS

SDA

SCL

WP

VCC

Serial Address/Data I/O

Serial Clock

Write-Protect Input

+1.8V to 5.5V Power Supply

8.1

A0, A1, A2

8.3

Serial Clock (SCL)

The levels on these inputs are compared with the

corresponding bits in the slave address. The chip is

selected if the compare is true.

This input is used to synchronize the data transfer to

and from the device.

8.4

Write-Protect (WP)

Up to eight 24XXX52 devices may be connected to the

same bus by using different Chip Select bit

combinations. These inputs must be connected to

either VSS or VCC.

This is the hardware write-protect pin. It can be tied to

VCC or VSS. If tied to VCC, the hardware write protection

is enabled. If the WP pin is tied to VSS, the hardware

write protection is disabled.

8.2

Serial Address/Data Input/Output

(SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal. Therefore, the SDA bus requires a pull-

up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

DS21166J-page 13

24AA52/24LCS52

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24AA52

XXXXXXXX

TXXXXNNN

e

3

I/P

3EC

YYWW

0510

8-Lead SOIC (150 mil)

Example:

24LCS52I

XXXXXXXT

e

3

XXXXYYWW

SN

0510

NNN

3EC

Example:

8-Lead TSSOP

S52

I510

3EC

XXXX

TYWW

NNN

Example:

8-Lead MSOP

XXXXXT

4S52I

5103EC

YWWNNN

8-Lead 2x3 DFN

Example:

2M4

510

3E

XXX

YWW

NN

1st Line Marking Codes

MSOP

Part Number

TSSOP

DFN

24AA52

A52

S52

4A52I

4S52I

2M1

2M4

24LCS52

DS21166J-page 14

24AA52/24LCS52

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

Note:

For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note:

Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

DS21166J-page 15

24AA52/24LCS52

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

DS21166J-page 16

24AA52/24LCS52

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050

.061

.056

.007

.237

.154

.193

.015

.025

4

1.27

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

Overall Height

A

.053

.069

1.35

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.32

0.10

5.79

3.71

4.80

0.25

0.48

0

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21166J-page 17

24AA52/24LCS52

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

A1

A2

φ

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

3.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.035

.004

.251

.173

.118

.024

4

.037

.006

.256

.177

.122

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

3.00

0.60

4

§

.002

.246

.169

.114

.020

0

Overall Width

6.25

4.30

2.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

DS21166J-page 18

24AA52/24LCS52

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E

E1

p

D

2

B

n

1

α

A2

A

c

φ

A1

(F)

L

β

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.026 BSC

0.65 BSC

Overall Height

A

A2

A1

E

-

.043

-

1.10

Molded Package Thickness

Standoff

.030

.033

.037

0.75

0.00

0.85

-

0.95

0.15

.000

-

.006

Overall Width

.193 TYP.

4.90 BSC

Molded Package Width

Overall Length

Foot Length

E1

D

.118 BSC

3.00 BSC

L

.016

.024

.037 REF

.031

0.40

0.60

0.95 REF

0.80

Footprint (Reference)

Foot Angle

F

φ

c

0°

.003

.009

5°

-

8°

.009

.016

15°

0°

0.08

0.22

5°

-

8°

0.23

0.40

15°

Lead Thickness

Lead Width

.006

B

α

β

.012

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

-

5°

15°

5°

15°

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-187

Drawing No. C04-111

DS21166J-page 19

24AA52/24LCS52

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

D

b

p

n

L

K

E

E2

EXPOSED

METAL

PAD

(NOTE 2)

2

1

PIN 1

ID INDEX

AREA

DETAIL

D2

ALTERNATE

CONTACT

(

NOTE 1)

BOTTOM VIEW

CONFIGURATION

TOP VIEW

EXPOSED

TIE BAR

A

A1

(

NOTE 3)

A3

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

MIN

MAX

MIN

NOM

MAX

n

e

Number of Pins

Pitch

8

.020 BSC

.035

0.50 BSC

Overall Height

Standoff

A

A1

A3

D

.031

.000

.039

0.80

0.90

0.02

0.20 REF.

1.00

.001

.008 REF.

.002

0.00

0.05

Contact Thickness

Overall Length

Overall Width

.079 BSC

.118 BSC

2.00 BSC

3.00 BSC

E

Exposed Pad Length

Exposed Pad Width

Contact Length §

D2

E2

L

.051

.059

.012

.008

–

.069

.075

.020

1.30**

1.50**

0.30

–

1.75

1.90

0.50

.016

0.40

Contact-to-Exposed Pad

Contact Width

§

K

–

0.20

–

b

.010

.012

0.20

0.25

0.30

*

Controlling Parameter

** Not within JEDEC parameters

Significant Characteristic

Notes:

§

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Exposed pad may vary according to die attach paddle size.

3. Package may have one or more exposed tie bars at ends.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent MO-229 VCED-2

Revised 09-12-05

DWG No. C04-123

DS21166J-page 20

24AA52/24LCS52

APPENDIX A: REVISION HISTORY

Revision G

Added 2.2V to document; Revised Features section to

include Standard and Pb-free finishes.

Corrections to Section 1.0, Electrical Characteristics;

Product ID System, added lead finish info.

Revision H

Added Reset Software Write-Protect feature.

Added 2x3 DFN package option.

Revision J

Revised Sections 6.3 and 8.4. Revised DFN Package

Drawing.

DS21166J-page 21

24AA52/24LCS52

NOTES:

DS21166J-page 22

24AA52/24LCS52

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS21166J-page 23

24AA52/24LCS52

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

24AA52/24LCS52

DS21166J

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21166J-page 24

24AA52/24LCS52

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

X

Examples:

Temperature Package Lead Finish

Range

a) 24AA52-I/P: Industrial Temperature,

1.8V, PDIP package

b) 24AA52-I/SN: Industrial Temperature,

1.8V, SOIC package

2

Device:

24AA52:

24AA52T:

=

1.8V, 2 Kbit I C Serial EEPROM

2

c) 24AA52T-I/MS: Tape and Reel, Industrial

Temperature, 1.8V, MSOP package

1.8V, 2 Kbit I C Serial EEPROM

(Tape and Reel)

2

24LCS52:

=

2.2V, 2 Kbit I C Serial EEPROM

d) 24LCS52-I/P: Industrial Temperature,

2.2V, PDIP package

2

24LCS52T: = 2.2V, 2 Kbit I C Serial EEPROM

(Tape and Reel)

e) 24LCS52-I/MC: Industrial Temperature,

2.2V, DFN package

f)

24LCS52T-I/MS: Tape and Reel,

Industrial Temperature, 2.2V, MSOP

package

Temperature

Range:

I

=

-40°C to +85°C

Package:

P

=

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (150 mil body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

Plastic Micro Small Outline (MSOP), 8-lead

Micro Lead Frame (2x3 mm body), 8-lead

SN

ST

MS

MC

Lead Finish Blank =

Pb-free – Matte Tin (see Note 1)

G

=

Pb-free – Matte Tin only

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

DS21166J-page25

24AA52/24LCS52

NOTES:

DS21166J-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and Zena are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21166J-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

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Tel: 61-2-9868-6733

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Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

10/31/05

DS21166J-page 28


型号：	24AA52-/ST
厂家：	MICROCHIP
描述：	2K 2.2V I2C⑩ Serial EEPROM with Software Write-Protect 2K 2.2V I2C⑩串行EEPROM用软件写保护可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总28页 (文件大小：439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24AA52-/ST [MICROCHIP]

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24AA52-/STG

24AA52-I/MC

24AA52-I/MCG

24AA52-I/MS

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24AA52-I/P

24AA52-I/PG

24AA52-I/PRVA

24AA52-I/SN

24AA52-I/SNG

24AA52-I/SNRVA

24AA52-I/ST