24CO25-P [MICROCHIP]
2K 2.5V I 2 C ⑩ Serial EEPROM; 2K 2.5V的I 2 C ⑩串行EEPROM
| 型号： | 24CO25-P |
| 厂家： | 
MICROCHIP |
| 描述： | 2K 2.5V I 2 C ⑩ Serial EEPROM |
| 文件： | 总12页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
24LC024/24LC025
2 ™
2K 2.5V I C Serial EEPROM
FEATURES
PACKAGE TYPES
PDIP/SOIC
• Single supply with operation from 2.5 to 5.5V
• Low power CMOS technology
- 1 mA active current typical
A0
1
8
Vcc
- 10 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (256 x 8)
• Hardware write protection for entire array
(24LC024)
A1
A2
2
3
7
6
WP*
SCL
• 2-wire serial interface bus, I2C compatible
• 100kHz and 400kHz compatibility
• Page-write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 3.5 ms typical write cycle time for page write
• Address lines allow up to eight devices on bus
• 10,000,000 erase/write cycles guaranteed
• ESD protection > 4,000V
Vss
4
5
SDA
TSSOP
• Data retention > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
1
8
A0
A1
VCC
2
3
4
7
6
5
WP*
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
A2
VSS
SCL
SDA
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
DESCRIPTION
The Microchip Technology Inc. 24LC024/24LC025 is a
2K bit Serial Electrically Erasable PROM with a voltage
range of 2.5V to 5.5V. The device is organized as a
single block of 256 x 8-bit memory with a 2-wire serial
interface. Low current design permits operation with
typical standby and active currents of only 10 µA and 1
mA respectively.The device has a page-write capability
for up to 16 bytes of data. Functional address lines
allow the connection of up to eight 24LC024/24LC025
devices on the same bus for up to 16K bits of contigu-
ous EEPROM memory. The device is available in the
standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP
packages.
BLOCK DIAGRAM
WP*
A0 A1 A2
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
SDA
SCL
VCC
VSS
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 1
24LC024/24LC025
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
VSS
SDA
SCL
VCC
Ground
Serial Data
VCC........................................................................ 7.0V
All inputs and outputs w.r.t. VSS......-0.6V to VCC +1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins ......................................≥ 4 kV
Serial Clock
+2.5V to 5.5V Power Supply
A0, A1, A2 Chip Selects
WP
NC
Hardware Write Protect (24LC024)
No internal connection
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device.This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
All parameters apply across the speci- VCC = +2.5V to +5.5V
fied operating ranges unless otherwise Commercial (C):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
noted.
Industrial (I):
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High level input voltage
VIH
VIL
0.7 VCC
0.05 VCC
V
V
V
V
Low level input voltage
0.3 VCC
—
Hysteresis of Schmitt trigger inputs
Low level output voltage
VHYS
VOL
(Note)
0.40
IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current
ILI
ILO
-10
-10
—
10
10
10
µA
µA
pF
VIN = 0.1V to 5.5V, WP = Vss
VOUT = 0.1V to 5.5V
Output leakage current
Pin capacitance (all inputs/outputs)
CIN, COUT
VCC = 5.0V (Note)
Tamb = 25°C, f = 1 MHz
ICC Read
ICC Write
ICCS
—
—
—
1
3
mA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
Operating current
Standby current
50
VCC = 5.5V, SDA = SCL = VCC
A0, A1, A2 = Vss
Note: This parameter is periodically sampled and not 100% tested.
DS21210A-page 2
Preliminary
1997 Microchip Technology Inc.
24LC024/24LC025
TABLE 1-3:
AC CHARACTERISTICS
All parameters apply across the specified operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted.
Commercial (C):
Industrial (I):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
STD MODE FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
—
—
250
50
20 +0.1
250
50
ns
ns
(Note 1), C ≤ 100 pF
B
C
B
Input filter spike suppression
(SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
—
10
—
—
10
—
ms Byte or Page mode
10M
10M
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C = total capacitance of one bus line in pF.
B
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: BUS TIMING DATA
THIGH
TF
TR
SCL
TSU:STA
TLOW
THD:DAT
TSU:DAT
TSU:STO
SDA
IN
THD:STA
TSP
TBUF
TAA
SDA
OUT
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 3
24LC024/24LC025
2.0
PIN DESCRIPTIONS
3.0
FUNCTIONAL DESCRIPTION
The 24LC024/24LC025 supports a bi-directional 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24LC024/24LC025 works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.
2.1
SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24LC024/24LC025 devices may be con-
nected to the same bus by using different chip select bit
combinations. These inputs must be connected to
either VCC or VSS.
2.4
WP (24LC024 only)
This is the hardware write protect pin. It must be tied to
VCC or VSS. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled. Note that the WP pin is
available only on the 24LC024.This pin is not internally
connected on the 24LC025.
2.5
Noise Protection
The 24LC024/24LC025 employs a VCC threshold
detector circuit which disables the internal erase/write
logic if the VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
DS21210A-page 4
Preliminary
1997 Microchip Technology Inc.
24LC024/24LC025
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus not Busy (A)
4.5
Acknowledge
Both data and clock lines remain HIGH.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
Note: The 24LC024/24LC025 does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
4.3
Stop Data Transfer (C)
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 5
24LC024/24LC025
FIGURE 5-1: CONTROL BYTE FORMAT
5.0
DEVICE ADDRESSING
Read/Write Bit
A control byte is the first byte received following the
start condition from the master device (Figure 5-1).The
control byte consists of a four bit control code; for the
24LC024/24LC025 this is set as 1010 binary for read
and write operations. The next three bits of the control
byte are the chip select bits (A2, A1, A0). The chip
select bits allow the use of up to eight 24LC024/
24LC025 devices on the same bus and are used to
select which device is accessed. The chip select bits in
the control byte must correspond to the logic levels on
the corresponding A2, A1, and A0 pins for the device to
respond. These bits are in effect the three most signifi-
cant bits of the word address.
Chip Select
Control Code
Bits
S
1
0
1
0
A2 A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. Following the start condition, the 24LC024/
24LC025 monitors the SDA bus checking the control
byte being transmitted. Upon receiving a 1010 code
and appropriate chip select bits, the slave device out-
puts an acknowledge signal on the SDA line. Depend-
ing on the state of the R/W bit, the 24LC024/24LC025
will select a read or write operation.
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by add-
ing up to eight 24LC024/24LC025 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
across device boundaries.
DS21210A-page 6
Preliminary
1997 Microchip Technology Inc.
24LC024/24LC025
6.2
Page Write
6.0
WRITE OPERATIONS
The write control byte, word address and the first data
byte are transmitted to the 24LC024/24LC025 in the
same way as in a byte write. But instead of generating
a stop condition, the master transmits up to 15 addi-
tional data bytes to the 24LC024/24LC025 which are
temporarily stored in the on-chip page buffer and will be
written into the memory after the master has transmit-
ted a stop condition. After the receipt of each word, the
four lower order address pointer bits are internally
incremented by one. The higher order four bits of the
word address remains constant. If the master should
transmit more than 16 bytes prior to generating the stop
condition, the address counter will roll over and the pre-
viously received data will be overwritten. As with the
byte write operation, once the stop condition is received
an internal write cycle will begin (Figure 6-2). If an
attempt is made to write to the protected portion of the
array when the hardware write protection has been
enabled, the device will acknowledge the command but
no data will be written. The write cycle time must be
observed even if the write protection is enabled.
6.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24LC024/
24LC025. After receiving another acknowledge signal
from the 24LC024/24LC025 the master device will
transmit the data word to be written into the addressed
memory location. The 24LC024/24LC025 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC024/24LC025 will not generate
acknowledge signals (Figure 6-1). If an attempt is made
to write to the protected portion of the array when the
hardware write protection (24LC024 only) has been
enabled, the device will acknowledge the command but
no data will be written. The write cycle time must be
observed even if the write protection is enabled.
6.3
WRITE PROTECTION
The WP pin (available on 24LC024 only) must be tied
to VCC or VSS. If tied to VCC, the entire array will be write
protected. If the WP pin is tied to VSS, then write oper-
ations to all address locations are allowed.
FIGURE 6-1: BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2: PAGE WRITE
S
T
S
T
O
P
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n +1
DATA n + 15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 7
24LC024/24LC025
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately.This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
DS21210A-page 8
Preliminary
1997 Microchip Technology Inc.
24LC024/24LC025
condition following the acknowledge. This terminates
the write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24LC024/
24LC025 will then issue an acknowledge and transmits
the eight bit data word. The master will not acknowl-
edge the transfer but does generate a stop condition
and the 24LC024/24LC025 discontinues transmission
(Figure 8-2). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one.There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24LC024/24LC025 contains an address counter
that maintains the address of the last word accessed,
internally incremented by one. Therefore, if the previ-
ous read access was to address n, the next current
address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to one, the 24LC024/24LC025 issues an
acknowledge and transmits the eight bit data word.The
master will not acknowledge the transfer but does gen-
erate a stop condition and the 24LC024/24LC025 dis-
continues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC024/24LC025
transmits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a ran-
dom read. This directs the 24LC024/24LC025 to trans-
mit the next sequentially addressed 8-bit word
(Figure 8-3).
8.2
Random Read
To provide sequential reads the 24LC024/24LC025
contains an internal address pointer which is incre-
mented by one at the completion of each operation.
This address pointer allows the entire memory contents
to be serially read during one operation. The internal
address pointer will automatically roll over from address
0FFh to address 000h.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set.This is done by sending the word address to the
24LC024/24LC025 as part of a write operation. After
the word address is sent, the master generates a start
FIGURE 8-1: CURRENT ADDRESS READ
S
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
A
R
T
SDA LINE
P
S
A
C
K
N
O
BUS ACTIVITY
DATA
A
C
K
FIGURE 8-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
S
P
S
SDA LINE
N
O
A
C
K
A
C
K
A
C
K
DATA (n)
A
C
K
BUS ACTIVITY
FIGURE 8-3: SEQUENTIAL READ
S
T
BUS ACTIVITY
CONTROL
DATA n
DATA n + 1
DATA n + 2
DATA n + X
MASTER
SDA LINE
O
P
BYTE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 9
24LC024/24LC025
NOTES:
DS21210A-page 10
Preliminary
1997 Microchip Technology Inc.
24LC024/24LC025
24LC024/24LC025 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24LC024/24LC025
—
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = TSSOP, 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = –40°C to +85°C
2
24LC024
2K I C Serial EEPROM with WP
2
24LC024T
2K I C Serial EEPROM with WP pin
(Tape and Reel)
Device:
2
24LC025
2K I C Serial EEPROM
2
24LC025T
2K I C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office.
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 11
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Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Italy
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, PRC 200335
Arizona Microchip Technology SRL
Centro Direzionale Colleone
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
Tel: 86-21-6275-5700
Fax: 86 21-6275-5060
Singapore
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#10-03 Prime Centre
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
5/8/97
Tel: 714-263-1888 Fax: 714-263-1338
Tel: 886 2-717-7175 Fax: 886-2-545-0139
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
M
All rights reserved. © 1997, Microchip Technology Incorporated, USA. 6/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or
warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21210A-page 12
Preliminary
1997 Microchip Technology Inc.
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