24FC16_技术文档

24AA16

2

16K 1.8V I C Serial EEPROM

PACKAGE TYPES

PDIP

FEATURES

• Single supply with operation down to 1.8V

• Low power CMOS technology

A0

1

8

7

VCC

WP

- 1 mA active current typical

A1

2

- 10 µA standby current typical at 5.5V

- 3 µA standby current typical at 1.8V

• Organized as 8 blocks of 256 bytes (8 x 256 x 8)

• 2-wire serial interface bus, I²C compatible

A2

3

4

6

5

SCL

SDA

VSS

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

8-lead

SOIC

1

8

7

A0

A1

VCC

2

3

4

WP

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

6

5

A2

SCL

SDA

VSS

• ESD protection > 4,000V

• 10,000,000 erase/write cycles guaranteed

• Data retention > 200 years

14-lead SOIC

14

1

2

3

4

5

6

7

• 8-pin DIP, 8-lead or 14-lead SOIC packages

• Available for extended temperature ranges

NC

A0

13

12

11

V

CC

- Commercial (C):

- Industrial (I):

0˚C to +70°C

-40°C to +85°C

WP

NC

A1

NC

DESCRIPTION

10

9

SCL

SDA

NC

A2

The Microchip Technology Inc. 24AA16 is a 1.8 volt 16K

bit Electrically Erasable PROM. The device is orga-

nized as eight blocks of 256 x 8-bit memory with a 2-

wire serial interface. Low voltage design permits oper-

ation down to 1.8 volts with standby and active currents

of only 3 µA and 1 mA, respectively. The 24AA16 also

has a page-write capability for up to 16 bytes of data.

The 24AA16 is available in the standard 8-pin DIP and

both 8-lead and 14-lead surface mount SOIC pack-

ages.

V

SS

8

NC

BLOCK DIAGRAM

WP

HV GENERATOR

I/O

MEMORY

CONTROL

LOGIC

EEPROM

ARRAY

CONTROL

LOGIC

XDEC

PAGE LATCHES

SDA

SCL

YDEC

VCC

VSS

SENSE AMP

R/W CONTROL

I²C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

DS21054E-page 1

This document was created with FrameMaker 4 0 4

24AA16

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

VSS

SDA

Ground

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS .................-0.6V to VCC +1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied ................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins..................................................≥ 4 kV

Serial Address/Data I/O

Serial Clock

SCL

WP

Write Protect Input

+1.8V to 5.5V Power Supply

No Internal Connection

VCC

A0, A1, A2

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability

TABLE 1-2:

DC CHARACTERISTICS

VCC = 1.8V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Industrial (I):

Tamb = -40°C to +85°C

Parameter

Symbol

Min

Typ

Max Units Conditions

WP, SCL and SDA pins:

High level input voltage

VIH

VIL

.7 VCC

—

.3 VCC

—

V

Low level input voltage

Hysteresis of Schmitt trigger inputs

Low level output voltage

Input leakage current

VHYS

VOL

ILI

.05 VCC

—

V

(Note)

.40

10

V

I^OL= 3.0 mA, V^CC= 1.8V

V^IN= .1V to V^CC

V^OUT= .1V to V^CC

-10

µA

Output leakage current

ILO

-10

10

Pin capacitance

(all inputs/outputs

CIN,

COUT

—

10

pF VCC = 5.0V (Note 1)

Tamb = 25˚C, FCLK = 1 MHz

Operating current

ICC Write

—

0.5

—

3

—

1

mA VCC = 5.5V, SCL = 400 kHz

mA VCC = 1.8V, SCL = 100 kHz

mA VCC = 5.5V, SCL = 400 kHz

mA VCC = 1.8V, SCL = 100 kHz

ICC Read

0.05

—

Standby current

ICCS

—

3

100

30

—

µA VCC = 5.5V, SDA=SCL=VCC

µA VCC = 3.0V, SDA=SCL=VCC

µA VCC = 1.8V, SDA=SCL=VCC

Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

THD:STA

TSU:STA

TSU:STO

SDA

START

STOP

DS21054E-page 2

1996 Microchip Technology Inc.

24AA16

TABLE 1-3:

AC CHARACTERISTICS

STANDARD

MODE

VCC = 4.5-5.5V

FAST MODE

Parameter

Symbol

Units

Remarks

Min

Max

Min

Max

Clock frequency

FCLK

THIGH

TLOW

TR

—

4000

4700

—

100

—

600

1300

—

400

—

kHz

ns

Clock high time

Clock low time

—

ns

SDA and SCL rise time

SDA and SCL fall time

1000

300

—

300

—

ns

(Note 1)

TF

—

ns

START condition hold

time

THD:STA

4000

600

ns

After this period the ﬁrst

clock pulse is generated

START condition setup

time

TSU:STA

4700

—

600

—

ns

Only relevant for repeated

START condition

Data input hold time

Data input setup time

THD:DAT

TSU:DAT

TSU:STO

0

—

0

—

ns

250

4000

100

600

STOP condition setup

time

Output valid from clock

Bus free time

TAA

—

3500

—

900

—

ns

(Note 2)

TBUF

4700

1300

Time the bus must be free

before a new transmission

can start

Output fall time from V^IH

min to VIL max

TOF

TSP

—

250

50

20 +0.1

CB

250

50

ns

(Note 1), CB ≤ 100 pF

Input ﬁlter spike suppres-

sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

Endurance

TWR

—

10

—

10

—

ms

Byte or Page mode

10M

cycles 25°C, Vcc = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. C^B= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions

3: The combined T^SPand V^HYS=speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T^Ispeciﬁcation for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TR

TF

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

IN

TSP

TBUF

TAA

THD:STA

SDA

OUT

1996 Microchip Technology Inc.

DS21054E-page 3

24AA16

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24AA16 supports a Bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is deﬁned as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access, and generates the

START and STOP conditions, while the 24AA16 works

as slave. Both, master and slave can operate as trans-

mitter or receiver but the master device determines

which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a ﬁrst in ﬁrst

out fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

Note: The 24AA16 does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

DS21054E-page 4

1996 Microchip Technology Inc.

24AA16

3.6

Device Addressing

4.0

WRITE OPERATION

A control byte is the ﬁrst byte received following the start

condition from the master device. The control byte con-

sists of a 4-bit control code, for the 24AA16 this is set as

1010 binary for read and write operations. The next three

bits of the control byte are the block select bits (B2, B1,

B0). They are used by the master device to select which

of the eight 256 word blocks of memory are to be

accessed. These bits are in effect the three most signiﬁ-

cant bits of the word address. It should be noted that the

protocol limits the size of the memory to eight blocks of

256 words, therefore the protocol can support only one

24AA16 per system.

4.1

Byte Write

Following the start condition from the master, the

device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore the next byte transmitted by

the master is the word address and will be written into

the address pointer of the 24AA16. After receiving

another acknowledge signal from the 24AA16 the mas-

ter device will transmit the data word to be written into

the addressed memory location. The 24AA16 acknowl-

edges again and the master generates a stop condi-

tion. This initiates the internal write cycle, and during

this time the 24AA16 will not generate acknowledge

signals (Figure 4-1).

The last bit of the control byte deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the 24AA16 monitors the

SDA bus checking the device type identiﬁer being

transmitted, upon a 1010 code the slave device outputs

an acknowledge signal on the SDA line. Depending on

the state of the R/W bit, the 24AA16 will select a read

or write operation.

4.2

Page Write

Control

Code

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24AA16 in the same way as

in a byte write. But instead of generating a stop condi-

tion the master transmits up to sixteen data bytes to the

24AA16 which are temporarily stored in the on-chip

page buffer and will be written into the memory after the

master has transmitted a stop condition. After the

receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

Operation

Block Select

R/W

Read

Write

1010

Block Address

1

0

FIGURE 3-2: CONTROL BYTE

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

A

1

0

1

0

B2

B1

B0

X = Don’t care

FIGURE 4-1: BYTE WRITE

S

T

A

R

T

S

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS

T

DATA

O

P

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

FIGURE 4-2: PAGE WRITE

S

T

O

P

T

BUS ACTIVITY

MASTER

A

R

T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 1

DATA n + 15

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

1996 Microchip Technology Inc.

DS21054E-page 5

24AA16

5.0

ACKNOWLEDGE POLLING

7.0

READ OPERATION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.1

Current Address Read

The 24AA16 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address n, the

next current address read operation would access data

from address n + 1. Upon receipt of the slave address

with R/W bit set to one, the 24AA16 issues an acknowl-

edge and transmits the 8-bit data word. The master will

not acknowledge the transfer but does generate a stop

condition and the 24AA16 discontinues transmission

(Figure 7-1).

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

7.2

Random Read

Send Stop

Condition to

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set. This is done by sending the word address to the

24AA16 as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24AA16 will then

issue an acknowledge and transmits the eight bit data

word. The master will not acknowledge the transfer but

does generate a stop condition and the 24AA16 discon-

tinues transmission (Figure 7-2).

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

NO

Acknowledge

7.3

Sequential Read

(ACK = 0)?

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24AA16 transmits the

ﬁrst data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the 24AA16 to transmit the next sequentially

addressed 8-bit word (Figure 7-3).

YES

6.0

WRITE PROTECTION

To provide sequential reads the 24AA16 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

The 24AA16 can be used as a serial ROM when the

WP pin is connected to VCC. Programming will be inhib-

ited and the entire memory will be write-protected.

7.4

Noise Protection

The 24AA16 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

DS21054E-page 6

1996 Microchip Technology Inc.

24AA16

FIGURE 7-1: CURRENT ADDRESS READ

S

T

O

P

S

T

A

R

T

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

SDA LINE

S

P

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-2: RANDOM READ

S

T

O

P

S

T

A

R

T

S

T

A

R

T

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

S

P

S

SDA LINE

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-3: SEQUENTIAL READ

S

T

O

P

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

SDA LINE

P

A

C

K

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

8.3

WP

8.0

PIN DESCRIPTIONS

This pin must be connected to either VSS or VCC.

8.1

SDA Serial Address/Data Input/Output

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400

kHz) from 24LC04B/08B.

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations

are not affected.

This feature allows the user to use the 24AA16 as a

serial ROM when WP is enabled (tied to VCC).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

8.4

A0, A1, A2

These pins are not used by the 24AA16. They may be

left ﬂoating or tied to either VSS or VCC.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

1996 Microchip Technology Inc.

DS21054E-page 7

24AA16

NOTE:

DS21054E-page 8

1996 Microchip Technology Inc.

24AA16

NOTES:

1996 Microchip Technology Inc.

DS21054E-page 9

24AA16

NOTES:

DS21054E-page 10

1996 Microchip Technology Inc.

24AA16

24AA16 Product Identiﬁcation System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

24AA16

-

/P

Package:

P = Plastic DIP (300 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Temperature

Range:

Blank = 0°C to +70°C

I = -40°C to +85°C

2

Device:

24AA16

24AA16T

1.8K, 16K I C Serial EEPROM

2

1.8K, 16K I C Serial EEPROM (Tape and Reel)

1996 Microchip Technology Inc

DS21054E-page 11

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9/3/96

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Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-

sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement

of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-

rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and

DS21054E-page 12

1996 Microchip Technology Inc.


型号：	24FC16
厂家：	MICROCHIP
描述：	The Microchip Technology Inc. 24FC16 is a 16Kb I2C™ compatible Serial EEPROM. The device is organi 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：79K)
中文：	中文翻译
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24FC16 [MICROCHIP]

相关型号：

24FC16-I/MS

24FC16-I/SN

24FC16/P

24FC16/SN

24FC16H

24FC16HT-I/OT

24FC16HT-I/SN

24FC16I/P

24FC16I/SN

24FC16T-E/MS

24FC16T-E/MUY

24FC16T-E/OT