24LC04BH_技术文档

24AA04H/24LC04BH

4K I²C^™Serial EEPROM with Half-Array Write-Protect

Device Selection Table

Description:

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

The Microchip Technology Inc. 24AA04H/24LC04BH

(24XX04H*) is an 4 Kbit Electrically Erasable PROM.

The device is organized as two blocks of 256 x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.7V, with standby

and active currents of only 1 μA and 1 mA,

24AA04H

1.7-5.5

2.5-5.5

400 kHz⁽¹⁾

400 kHz

I

24LC04BH

I, E

Note 1: 100 kHz for VCC <2.5V

respectively. The 24XX04H also has a page write

capability for up to 16 bytes of data. The 24XX04H is

available in the standard 8-pin PDIP, surface mount

SOIC, TSSOP, 2x3 TDFN and MSOP packages, and

is also available in the 5-lead SOT-23 package. All

packages are Pb-free and RoHS compliant.

Features:

• Single Supply with Operation Down to 1.7V for

24AA04H Devices, 2.5V for 24LC04BH Devices

• Low-Power CMOS Technology:

- Read current 1 mA, max.

Block Diagram

- Standby current 1 μA, max.

• 2-Wire Serial Interface, I²C™ Compatible

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• Page Write Time 3 ms, typical

HV

Generator

WP

I/O

Control

Logic

Memory

Control

Logic

EEPROM

Array

XDEC

• Self-Timed Erase/Write Cycle

Page

Latches

• 16-Byte Page Write Buffer

• Hardware Write-Protect for Half-Array (100h-1FFh)

• ESD Protection >4,000V

I/O

SCL

YDEC

• More than 1 Million Erase/Write Cycles

• Data Retention >200 years

SDA

Sense Amp.

R/W Control

VCC

VSS

• Factory Programming available

• Packages include 8-lead PDIP, SOIC, TSSOP,

TDFN, MSOP and 5-lead SOT-23

Package Types

• Pb-Free and RoHS Compliant

• Temperature Ranges:

SOIC, TSSOP

PDIP, MSOP

- Industrial (I):

-40°C to +85°C

A0

1

8

VCC

1

8

7

A0

A1

A2

VCC

WP

- Automotive (E): -40°C to +125°C

2

3

4

A1

A2

2

3

7

6

WP

SCL

6

5

SCL

SDA

VSS

4

5

SDA VSS

SOT-23-5

TDFN

A0

1

VCC

WP

8

7

6

5

WP

Vcc

1

5

4

SCL

2

3

4

A1

SCL

SDA

2

3

Vss

A2

VSS

SDA

Note:

Pins A0, A1 and A2 are not used by the 24XX04. (No

internal connections).

*24XX04H is used in this document as a generic part

number for the 24AA04H/24LC04BH devices.

DS22119A-page 1

24AA04H/24LC04BH

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

VCC = +1.7V to +5.5V

DC CHARACTERISTICS

Industrial (I):

TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

Symbol

No.

Characteristic

Min.

Typ.

Max.

Units

Conditions

D1

D2

D3

D4

VIH

—

WP, SCL and SDA pins

High-level input voltage

Low-level input voltage

—

V

—

0.7 VCC

—

VIL

0.3 VCC

—

V

—

VHYS

Hysteresis of Schmitt

Trigger inputs

0.05 VCC

V

(Note)

D5

D6

D7

D8

VOL

ILI

Low-level output voltage

Input leakage current

Output leakage current

—

0.40

±1

V

IOL = 3.0 mA, VCC = 2.5V

VIN = VSS or VCC

μA

pF

ILO

±1

VOUT = VSS or VCC

CIN,

Pin capacitance

10

VCC = 5.0V (Note)

COUT

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

D9

ICC write Operating current

—

0.1

3

1

mA

VCC = 5.5V, SCL = 400 kHz

—

D10

D11

ICC read

0.05

ICCS

Standby current

—

0.01

—

1

5

μA

Industrial

Automotive

SDA = SCL = VCC

WP = VSS

Note:

This parameter is periodically sampled and not 100% tested.

DS22119A-page 2

24AA04H/24LC04BH

TABLE 1-2:

AC CHARACTERISTICS

Industrial (I):

Automotive (E):

TA = -40°C to +85°C, VCC = +1.7V to +5.5V

TA = -40°C to +125°C, VCC = +2.5V to +5.5V

AC CHARACTERISTICS

Param.

Symbol

No.

Characteristic

Clock Frequency

Min.

Max. Units Conditions

1

2

3

4

FCLK

THIGH

TLOW

TR

—

400

100

kHz 2.5V ≤ VCC ≤ 5.5V

kHz 1.7V ≤ VCC < 2.5V (24AA04H)

Clock High Time

Clock Low Time

600

4000

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

1300

4700

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

SDA and SCL Rise Time

(Note 1)

—

300

1000

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

5

6

TF

SDA and SCL Fall Time

—

300

ns

(Note 1)

THD:STA Start Condition Hold Time

600

4000

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

7

TSU:STA Start Condition Setup Time

600

4700

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

8

9

THD:DAT Data Input Hold Time

TSU:DAT Data Input Setup Time

0

—

ns

(Note 2)

100

250

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

10

11

12

13

14

TSU:STO Stop Condition Setup Time

600

4000

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

TSU:WP

THD:WP

TAA

WP Setup Time

WP Hold Time

600

4000

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

1300

4700

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

Output Valid from Clock

—

900

3500

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

(Note 2)

TBUF

Bus free time: Time the bus

must be free before a new

transmission can start

1300

4700

—

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

15

16

17

18

TOF

TSP

TWC

—

Output Fall Time from VIH

Minimum to VIL Maximum

—

250

ns

2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA04H)

Input Filter Spike Suppression

(SDA and SCL pins)

—

50

ns

(Notes 1 and 3)

Write Cycle Time (byte or

page)

—

5

ms

—

Endurance

1M

—

cycles 25°C, (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at

www.microchip.com.

DS22119A-page 3

24AA04H/24LC04BH

FIGURE 1-1: BUS TIMING DATA

5

4

D4

2

SCL

7

3

10

8

9

SDA

IN

6

16

14

12

13

SDA

OUT

(protected)

WP

11

(unprotected)

DS22119A-page 4

24AA04H/24LC04BH

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24XX04H supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX04H works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last sixteen

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a first-in first-

out (FIFO) fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

3.5

Acknowledge

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note:

The 24XX04H does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus Not Busy (A)

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX04H) will leave the data

line high to enable the master to generate the Stop

condition.

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS22119A-page 5

24AA04H/24LC04BH

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

3.6

Device Addressing

A control byte is the first byte received following the

Start condition from the master device (Figure 3-2).

The control byte consists of a four-bit control code. For

the 24XX04H, this is set as ‘1010’ binary for read and

write operations. The next three bits of the control byte

are the block-select bits (B2, B1, B0). B2 and B1 are a

“don’t care” for the 24XX04H. B0 is used by the master

device to select which of the two 256 word-blocks of

memory are to be accessed. These bits are in effect the

three Most Significant bits of the word address.

Read/Write Bit

Block

Select

Bits

Control Code

S

1

0

1

0

x

B0 R/W ACK

Slave Address

The last bit of the control byte defines the operation to

be performed. When set to ‘1’ a read operation is

selected. When set to ‘0’ a write operation is selected.

Following the Start condition, the 24XX04H monitors

the SDA bus, checking the device type identifier being

transmitted and, upon receiving a ‘1010’ code, the

slave device outputs an Acknowledge signal on the

SDA line. Depending on the state of the R/W bit, the

24XX04H will select a read or write operation.

Acknowledge Bit

Start Bit

x = “don’t care”

Control

Code

Operation

Block Select

R/W

Read

Write

Block Address

1010

1

0

DS22119A-page 6

24AA04H/24LC04BH

4.2

Page Write

4.0

4.1

WRITE OPERATION

Byte Write

The write control byte, word address and the first data

byte are transmitted to the 24XX04H in the same way

as in a byte write. However, instead of generating a

Stop condition, the master transmits up to 16 data bytes

to the 24XX04H, which are temporarily stored in the on-

chip page buffer and will be written into memory once

the master has transmitted a Stop condition. Upon

receipt of each word, the four lower-order Address

Pointer bits are internally incremented by ‘1’. The

higher-order 5 bits of the word address remain

constant. If the master should transmit more than 16

words prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received an

internal write cycle will begin (Figure 4-2).

Following the Start condition from the master, the

device code (4 bits), the block address (3 bits) and the

R/W bit, which is a logic-low, is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow once it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte transmit-

ted by the master is the word address and will be

written into the Address Pointer of the 24XX04H. After

receiving another Acknowledge signal from the

24XX04H, the master device will transmit the data word

to be written into the addressed memory location. The

24XX04H acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and, during this time, the 24XX04H will not

generate Acknowledge signals (Figure 4-1).

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page-size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

FIGURE 4-1: BYTE WRITE

S

T

A

R

T

Bus Activity

Master

Control

Byte

Word

Address

O

P

Data

0

1 0 1

X X B0 0

SDA Line

S

P

A

C

K

A

C

K

A

C

K

Bus Activity

Block

Select

Bits

x= “don’t care”

FIGURE 4-2: PAGE WRITE

S

T

A

R

T

Bus Activity

Master

Control

Byte

Word

Address (n)

O

P

Data (n)

Data (n + 1)

Data (n + 15)

B0

0

SDA Line

0

10 X X

1

S

P

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

C

Block

Select

Bits

K

x= “don’t care”

DS22119A-page 7

24AA04H/24LC04BH

5.0

ACKNOWLEDGE POLLING

6.0

WRITE PROTECTION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally-timed write cycle and ACK polling

can then be initiated immediately. This involves the

master sending a Start condition followed by the control

byte for a Write command (R/W = 0). If the device is still

busy with the write cycle, no ACK will be returned. If the

cycle is complete, the device will return the ACK and

the master can then proceed with the next Read or

Write command. See Figure 5-1 for a flow diagram of

this operation.

The WP pin allows the user to write-protect half of the

array (100h-1FFh) when the pin is tied to VCC. If the pin

is tied to VSS the write protection is disabled.

FIGURE 5-1:

ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

No

Yes

DS22119A-page 8

24AA04H/24LC04BH

7.3

Sequential Read

7.0

READ OPERATION

Sequential reads are initiated in the same way as a

random read, except that once the 24XX04H transmits

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

directs the 24XX04H to transmit the next sequentially-

addressed 8-bit word (Figure 7-3).

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

7.1

Current Address Read

To provide sequential reads, the 24XX04H contains an

internal Address Pointer that is incremented by one

upon completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

The 24XX04H contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous access

(either a read or write operation) was to address n, the

next current address read operation would access data

from address n + 1. Upon receipt of the slave address

with R/W bit set to ‘1’, the 24XX04H issues an acknowl-

edge and transmits the 8-bit data word. The master will

not acknowledge the transfer, but does generate a Stop

condition and the 24XX04H discontinues transmission

(Figure 7-1).

7.4

Noise Protection

The 24XX04H employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is accomplished by sending the word

address to the 24XX04H as part of a write operation.

Once the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. The master then issues

the control byte again, but with the R/W bit set to a ‘1’.

The 24XX04H will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition and the 24XX04H will discontinue transmis-

sion (Figure 7-2).

FIGURE 7-1:

CURRENT ADDRESS READ

S

Bus Activity

Master

T

A

R

Control

Byte

S

T

Data (n)

O

P

T

x

B0

0

SDA Line

1 0 1

1

S

P

A

C

K

N

o

Bus Activity

Block

Select

Bits

A

C

K

x= “don’t care”

DS22119A-page 9

24AA04H/24LC04BH

FIGURE 7-2:

RANDOM READ

S

T

A

R

T

A

R

T

S

T

Bus Activity

Master

Control

Byte

Word

Address (n)

Control

Byte

Data (n)

O

P

x

B0

010

x B0

1

0

101

0 x

S

P

S

SDA Line

A

C

K

A

C

K

A

C

K

N

o

Block

Select

Bits

Block

Select

Bits

Bus Activity

A

C

K

x= “don’t care”

FIGURE 7-3:

Bus Activity

SEQUENTIAL READ

S

T

Control

Byte

O

P

Data (n)

Data (n + 1)

Data (n + 2)

Data (n + X)

Master

1

P

SDA Line

A

C

K

A

C

K

N

o

C

Bus Activity

K

A

C

K

DS22119A-page 10

24AA04H/24LC04BH

8.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 8-1.

TABLE 8-1:

Name

PIN FUNCTION TABLE

PDIP

SOIC

TSSOP

TDFN

MSOP

SOT-23

Description

Not Connected

A0

A1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

—

2

Not Connected

A2

Not Connected

VSS

SDA

SCL

WP

VCC

Ground

3

Serial Address/Data I/O

Serial Clock

1

5

Write-Protect Input

+1.7V to 5.5V Power Supply

4

8.1

Serial Address/Data Input/Output

(SDA)

8.3

Write-Protect (WP)

The WP pin must be connected to either VSS or VCC.

SDA is a bidirectional pin used to transfer addresses

and data into and out of the device. Since it is an open-

drain terminal, the SDA bus requires a pull-up resistor

to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).

If tied to VSS, normal memory operation is enabled

(read/write the entire memory 000h-1FFh).

If tied to VCC, write operations are inhibited, half of the

memory will be write-protected (100h-1FFh). Read

operations are not affected.

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating Start and Stop conditions.

8.4

A0, A1, A2

The A0, A1 and A2 pins are not used by the 24XX04H.

They may be left floating or tied to either VSS or VCC.

8.2

Serial Clock (SCL)

The SCL input is used to synchronize the data transfer

to and from the device.

DS22119A-page 11

24AA04H/24LC04BH

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

Example:

8-Lead PDIP (300 mil)

24LC04BH

I/P 13F

XXXXXXXX

T/XXXNNN

e

3

0827

YYWW

Example:

24L04BHI

8-Lead SOIC (3.90 mm)

XXXXXXXX

T/XXYYWW

e

3

SN

0827

13F

NNN

Example:

4L4H

8-Lead TSSOP

XXXX

TYWW

NNN

I827

13F

Example:

8-Lead MSOP

XXXXXT

4L4BHI

82713F

YWWNNN

Example:

5-Lead SOT-23

XXNN

3QNN

8-Lead 2x3 TDFN

Example:

XXX

YWW

NN

AE4

827

13

DS22119A-page 12

24AA04H/24LC04BH

1st Line Marking

MSOP

E-Temp

SOT-23

TDFN

Part No.

TSSOP

I-Temp

E-Temp

I-Temp

E-Temp

24AA04H

4A4H

4L4H

4A4HI

—

3MNN

3QNN

—

AE1

AE4

—

24LC04BH

4L4BHI

4L4BHE

3RNN

AE5

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

Note:

For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

DS22119A-page 13

24AA04H/24LC04BH

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DS22119A-page 14

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

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DS22119A-page 15

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

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DS22119A-page 16

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ()ꢋꢐꢆ )"ꢋꢐ*ꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ (ꢒꢆMꢆ+%+ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ( !ꢇꢚ

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ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ

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ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕ<?1

DS22119A-page 17

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ,ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ, ꢒꢆꢙ, !ꢇꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

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ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

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DS22119A-page 18

24AA04H/24LC04BH

.ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆ("ꢄꢐꢉꢋꢉꢊꢗ"ꢆꢑ!(ꢒꢆꢙ !(ꢁ/ꢓꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

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ꢛꢗꢊꢃꢉꢜ

ꢀꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢎꢜꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ

ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ

1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢛꢀ1

DS22119A-page 19

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ0ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/1ꢓ1ꢔ%2.ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ0ꢛꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

DS22119A-page 20

24AA04H/24LC04BH

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ0ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/1ꢓ1ꢔ%2.ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ0ꢛꢚ

ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

DS22119A-page 21

24AA04H/24LC04BH

APPENDIX A: REVISION HISTORY

Revision A (11/2008)

Original release.

DS22119A-page 22

24AA04H/24LC04BH

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS22119A-page 23

24AA04H/24LC04BH

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

24AA04H/24LC04BH

DS22119A

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS22119A-page 24

24AA04H/24LC04BH

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

a) 24AA04H-I/P: Industrial Temperature,1.7V,

PDIP package

Temperature Package

Range

b) 24AA04H-I/SN: Industrial Tempera-

ture,1.7V, SOIC package

2

Device:

24AA04H:

=

1.7V, 4 Kbit I C Serial EEPROM

c) 24AA04HT-I/OT: Industrial Temperature,

1.7V, SOT-23 package, Tape and Reel

2

24AA04HT: = 1.7V, 4 Kbit I C Serial EEPROM

(Tape and Reel)

24LC04BH: = 2.5V, 4 Kbit I C Serial EEPROM

2

24LC04BHT:= 2.5V, 4 Kbit I C Serial EEPROM

d) 24LC04BH-I/P: Industrial Temperature,

2.5V, PDIP package

(Tape and Reel)

e) 24LC04BH-E/SN: Automotive Temp.,2.5V

SOIC package

Temperature

Range:

I

E

=

-40°C to +85°C

-40°C to +125°C

f)

24LC04BHT-I/OT: Industrial Temperature,

2.5V, SOT-23 package, Tape and Reel

Package:

P

=

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

Plastic Dual Flat (TDFN), No lead package,

2x3 mm body, 8-lead

SN

ST

MNY

(1)

MS

OT

=

Plastic Micro Small Outline (MSOP), 8-lead

SOT-23, 5-lead (Tape and Reel only)

Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.

DS22119A-page 25

24AA04H/24LC04BH

NOTES:

DS22119A-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

32

PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22119A-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS22119A-page 28


型号：	24LC04BH
厂家：	MICROCHIP
描述：	4K I2C™ Serial EEPROM with Half-Array Write-Protect 4K I2C ™串行EEPROM，带有半阵列写保护可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总28页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24LC04BH [MICROCHIP]

相关型号：

24LC04BH-E/MNY

24LC04BH-E/MS

24LC04BH-E/OT

24LC04BH-E/P

24LC04BH-E/SN

24LC04BH-E/ST

24LC04BH-I/MNY

24LC04BH-I/MS

24LC04BH-I/OT

24LC04BH-I/P

24LC04BH-I/SN

24LC04BH-I/ST