24LC164T-I/PQTP [MICROCHIP]
16K 2.5V Cascadable I2C⑩ Serial EEPROM; 16K 2.5V级联I2C⑩串行EEPROM
| 型号： | 24LC164T-I/PQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 16K 2.5V Cascadable I2C⑩ Serial EEPROM |
| 文件： | 总16页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete Device
24LC164
16K 2.5V Cascadable I2C™ Serial EEPROM
FEATURES
PACKAGE TYPES
• Single supply with operation down to 2.5V
• Low power CMOS technology
PDIP
A0
A1
1
2
8
7
VCC
WP
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
A2
3
4
6
5
SCL
SDA
• Organized as eight blocks of 256 bytes
(8 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
VSS
• Functional address inputs for cascading up to
8 devices
• Schmitt trigger, filtered inputs for noise
suppression
SOIC
1
2
8
7
A0
A1
VCC
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
WP
3
4
6
5
A2
SCL
SDA
VSS
• Factory programming (QTP) available
• ESD protection > 4,000V
BLOCK DIAGRAM
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
WP
A2 A1 A0
• 8-pin DIP, 8-lead SOIC packages
HV GENERATOR
• Available temperature ranges:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
EEPROM ARRAY
(8 x 256 x 8)
XDEC
PAGE LATCHES
DESCRIPTION
The Microchip Technology Inc. 24LC164 is a cascad-
able 16 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with standby
and active currents of only 5 µA and 1 mA respectively.
The 24LC164 also has a page-write capability for up to
16 bytes of data. The 24LC164 is available in the stan-
dard 8-pin DIP and 8-lead surface mount SOIC pack-
ages.
SDA
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
The three select pins, A0, A1 and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128 Kbits total system
EEPROM.
I2C is a trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS21093I-page 1
24LC164
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
VSS
SDA
Ground
1.1
Maximum Ratings*
Serial Address/Data I/O
Serial Clock
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.3V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins..................................................≥ 4 kV
SCL
WP
Write Protect Input
+2.5V to 5.5V Power Supply
Chip Address Inputs
VCC
A0, A1, A2
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C):
VCC = +2.5V to +5.5V
TAMB = 0°C to +70°C
TAMB = -40°C to +85°C
Industrial (I):
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
VIH
VIL
.7 VCC
—
—
.3 VCC
—
V
V
V
—
—
Hysteresis of Schmitt trigger
inputs
VHYS
.05 VCC
(Note)
Low level output voltage
Input leakage current
VOL
ILI
—
-10
-10
—
.40
10
10
10
V
IOL = 3.0 mA, VCC = 2.5V
VIN = 0.1V to VCC
µA
µΑ
pF
Output leakage current
ILO
VOUT = 0.1V to VCC
Pin capacitance
CIN, COUT
VCC = 5.0V (Note)
(all inputs/outputs)
TAMB = 25°C, FCLK = 1MHz
Operating current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V, SCL = 400 kHz
Standby current
ICCS
—
—
30
100
µΑ
µΑ
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
A0 = A1 = A2 = WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
STOP
START
DS21093I-page 2
2004 Microchip Technology Inc.
24LC164
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
VCC = 4.5V - 5.5V
FAST MODE
Parameter
Symbol
Min.
Max.
Min.
Max.
Units
Remarks
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
—
—
—
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
—
250
4000
—
100
600
—
—
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH min
to VIL max
TOF
TSP
—
—
250
50
20 + 0.1
Cb
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
TWR
—
—
10
—
—
10
—
ms
Byte or Page mode
1M
1M
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website at
www.microchip.com.
FIGURE 1-2:
BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
SDA
OUT
2004 Microchip Technology Inc.
DS21093I-page 3
24LC164
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The 24LC164 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter and if receiving
data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC164 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
3.5
Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit..
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Note: The 24LC164 does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
3.1
Bus not Busy (A)
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC164) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS21093I-page 4
2004 Microchip Technology Inc.
24LC164
3.6
Device Addressing
4.0
4.1
WRITE OPERATION
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC164. After
receiving another acknowledge signal from the
24LC164, the master device will transmit the data word
to be written into the addressed memory location. The
24LC164 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle. During this time the 24LC164 will not generate
acknowledge signals (Figure 4-1).
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one, a read operation is
selected. When set to ‘0’ a write operation is selected.
Following the start condition, the 24LC164 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC164 will select a read
or write operation.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC164 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 16 data bytes to the
24LC164 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Operation Control Code
Block Select R/W
Read
Write
1
1
A2 A1 A0 Block Address
1
0
A2 A1 A0 Block Address
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
READ/WRITE
START
SLAVE ADDRESS
R/W
A
1
A2
A1
A0
B2
B1
B0
MSB
LSB
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
2004 Microchip Technology Inc.
DS21093I-page 5
24LC164
FIGURE 4-1:
BYTE WRITE
S
BUS ACTIVITY
MASTER
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
2
A
1
A
0
B
2
B
1
B
0
SDA LINE
S
P
1
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 4-2:
PAGE WRITE
S
T
A
R
T
BUS ACTIVITY
MASTER
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 1)
DATA (n + 15)
A A A B B B
2 1 0 2 1 0
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS21093I-page 6
2004 Microchip Technology Inc.
24LC164
5.0
ACKNOWLEDGE POLLING
7.0
READ OPERATION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC164 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to ‘1’, the 24LC164 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a stop
condition and the 24LC164 discontinues transmission
(Figure 7-1).
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC164 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC164 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC164 dis-
continues transmission (Figure 7-2).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
Yes
Next
Operation
To provide sequential reads the 24LC164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
6.0
WRITE PROTECTION
The 24LC164 can be used as a serial ROM when the
WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
7.4
Noise Protection
The 24LC164 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
2004 Microchip Technology Inc.
DS21093I-page 7
24LC164
FIGURE 7-1:
CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
BUS ACTIVITY
MASTER
DATA (n)
S
1 A2A1A0B2B1B0
P
SDA LINE
N
O
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 7-2:
RANDOM READ
S
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
A
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
BYTE
R
T
S 1 A2A1A0B2B1B0
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
DATA (n)
BYTE
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
8.3
WP
8.0
8.1
PIN DESCRIPTIONS
This pin must be connected to either VSS or VCC.
SDA Serial Address/Data Input/
Output
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to VCC (typical 10kΩ for 100 kHz, 2kΩ for
400 kHz).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to VCC).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
Note: The level on A1 is compared to the
inverse of the slave address.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either VSS or
VCC.
DS21093I-page 8
2004 Microchip Technology Inc.
24LC164
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example
24LC164
XXXXXXXX
XXXXXNNN
XXXXXNNN
YYWW
0025
8-Lead SOIC (150 mil)
Example
24LC164
XXXX0025
XXXXXXXX
XXXXYYWW
NNN
NNN
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2004 Microchip Technology Inc.
DS21093I-page 9
24LC164
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21093I-page 10
2004 Microchip Technology Inc.
24LC164
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2004 Microchip Technology Inc.
DS21093I-page 11
24LC164
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
DS21093I-page 12
2004 Microchip Technology Inc.
24LC164
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS21093I
Device:
24LC164
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
2004 Microchip Technology Inc.
DS21093I-page 13
24LC164
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
24LC164–/P Commercial Temp,
PDIP package
b)
24LC164–/SN Commercial Temp.,
SOIC package
Device
24LC164: VDD range 2.5V to 5.5V
24LC164T: (Tape and Reel)
Temperature Range
Package
-
I
=
=
0°C to +70°C
-40°C to +85°C
P
SN
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
Pattern
QTP, SQTP or Special Requirements. Blank for standard
devices.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21093I-page 14
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21093I-page 15
WORLDWIDE SALES AND SERVICE
China - Beijing
Singapore
AMERICAS
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Italy
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Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
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Tel: 31-416-690399
Toronto
6285 Northam Drive, Suite 108
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Tel: 905-673-0699
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3-17-2, Shin Yokohama, Kohoku-ku,
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
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ASIA/PACIFIC
Australia
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United Kingdom
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Korea
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Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
2004 Microchip Technology Inc.
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