24LC174T-I/SN [MICROCHIP]
2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SOIC-8;
| 型号： | 24LC174T-I/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete Device
24LC174
2 ™
16K 2.5V Cascadable I C Serial EEPROM with OTP Security Page
FEATURES
PACKAGE TYPES
• Single supply with operation down to 2.5V
• 16 bytes OTP Secure Memory
• Low power CMOS technology
PDIP
A0
A1
1
2
6
7
VCC
WP
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as eight blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I2C compatible
• Functional address inputs for cascading up to 8
devices
A2
3
4
8
9
SCL
SDA
VSS
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
8-lead
SOIC
1
6
A0
A1
VCC
2
3
4
7
8
9
WP
A2
SCL
SDA
VSS
• 1,000,000 Erase/Write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead SOIC packages
• Available temperature ranges:
BLOCK DIAGRAM
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40° to +85°
A0 A1
A2
WP
HV GENERATOR
DESCRIPTION
I/O
MEMORY
CONTROL
LOGIC
EEPROM ARRAY
(8 x 256 x 8)
The Microchip Technology Inc. 24LC174 is a cascad-
able 16K bit Electrically Erasable PROM. The device is
organized as eight blocks of 256 x 8-bit memory with a
2-wire serial interface and provides a specially
addressed OTP (one-time programmable) 16 byte
security block. Low voltage design permits operation
down to 2.5 volts with standby and active currents of
only 5 µA and 1 mA respectively. The 24LC174 also
has a page-write capability for up to 16 bytes of data.
The 24LC174 is available in the standard 8-pin DIP and
8-lead surface mount SOIC packages.
CONTROL
LOGIC
XDEC
PAGE LATCHES
SDA
SCL
YDEC
V
CC
SS
SENSE AMP
R/W CONTROL
V
The three select pins, A0, A1, and A2, function as chip
select inputs and allow up to eight devices to share a
common bus, for up to 128K bits total system
EEPROM.
I2C is a trademark of Philips Corporation.
2004 Microchip Technology Inc.
DS21101H-page 1
24LC174
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
VSS
SDA
Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................-0.3V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins..................................................≥ 4 kV
Serial Address/Data I/O
Serial Clock
SCL
WP
Write Protect Input
+2.5V to 5.5V Power Supply
Chip Address Inputs
VCC
A0, A1, A2
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Max
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
VIH
VIL
VHYS
VOL
.7 VCC
—
.05 VCC
—
—
.3 VCC
—
V
V
V
V
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
(Note)
.40
IOL = 3.0 mA, VCC = 2.5V
Input leakage current
ILI
ILO
-10
-10
—
10
10
10
µA
µA
pF
VIN = .1V to VCC
Output leakage current
VOUT = .1V to VCC
Pin capacitance (all inputs/outputs)
CIN, COUT
VCC = 5.0V (Note1),
Tamb = 25°C, FCLK = 1 MHz
Operating current
Standby current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V, SCL = 400 kHz
ICCS
—
—
30
100
µA
µA
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note:This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
START
STOP
DS21101H-page 2
2004 Microchip Technology Inc.
24LC174
TABLE 1-3:
AC CHARACTERISTICS
Vcc= 4.5 - 5.5V
Fast Mode
Standard Mode
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
TF
—
—
ns
(Note 1)
THD:STA
4000
600
ns
After this period the first clock
pulse is generated
START condition setup
time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
—
0
—
—
ns
ns
ns
ns
ns
250
4000
—
100
600
—
STOP condition setup time TSU:STO
—
—
Output valid from clock
Bus free time
TAA
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission can
start
Output fall time from VIH
min to VIL max
TOF
TSP
—
—
250
50
20 +0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
TWR
—
—
10
—
—
10
—
ms
Byte or Page mode
1M
1M
cycles 25°C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
SDA
OUT
2004 Microchip Technology Inc.
DS21101H-page 3
24LC174
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The 24LC174 supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC174
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Note: The 24LC174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC174) will leave the data line
HIGH to enable the master to generate the STOP con-
dition.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS21101H-page 4
2004 Microchip Technology Inc.
24LC174
3.6
Device Addressing and Operation
4.0
WRITE OPERATION
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC174. After
receiving another acknowledge signal from the
24LC174 the master device will transmit the data word
to be written into the addressed memory location. The
24LC174 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24LC174 will not gener-
ate acknowledge signals (Figure 4-1).
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC174 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24LC174 will select a read
or write operation.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC174 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to 16 data bytes to the
24LC174 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 7.3).
Operation Control Code Block Select R/W
Read
Write
1
1
A2 A1 A0 Block Address
A2 A1 A0 Block Address
1
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
A2
A1
A0
B2
B1
B0
MSB
LSB
Note: Page write operations are limited to writing
bytes within
a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples
of the page buffer size (or ‘page size’) and
end at addresses that are integer multiples
of [page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
2004 Microchip Technology Inc.
DS21101H-page 5
24LC174
FIGURE 4-1: BYTE WRITE
S
T
A
R
T
S
T
O
P
WORD
ADDRESS
CONTROL
BYTE
BUS ACTIVITY:
MASTER
DATA
SDA LINE
S
1
A2 A1 A0 B2 B1 B0
P
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
FIGURE 4-2: PAGE WRITE
S
T
A
R
T
S
T
O
P
WORD
ADDRESS (n)
CONTROL
BYTE
BUS ACTIVITY:
MASTER
DATA n
DATA n + 1
DATA n + 15
SDA LINE
S
A2 A1 A0 B2 B1 B0
P
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
6.0
WRITE PROTECTION
The 24LC174 can be used as a serial ROM when the
WP pin is connected to Vcc. Programming will be inhib-
ited and the entire memory will be write-protected.
DS21101H-page 6
2004 Microchip Technology Inc.
24LC174
7.3
Sequential Read
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random
read, and sequential read.
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC174 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC174 to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
7.1
Current Address Read
To provide sequential reads the 24LC174 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
The 24LC174 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the 24LC174 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the 24LC174 discontinues
transmission (Figure 8-1).
7.4
Noise Protection
The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC174 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC174 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC174 dis-
continues transmission (Figure 8-2).
2004 Microchip Technology Inc.
DS21101H-page 7
24LC174
8.5
Security Access Control
8.0
PIN DESCRIPTIONS
The security row is enabled by sending the control
sequence with the I2C slave address of 0110. Bit 0 of
the control byte must be set to a one for a READ
OPERATION or a zero for the OTP WRITE OPERA-
TION. The SECURITY ACCESS DATA is always read
starting at byte 0 for N bytes up to and including byte
15. (See Figure 8-3).
8.1
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.6
Security Access Write
The S.A.W. data is written to the device using a normal
page write following the proper control access
sequence. Upon receiving the final stop bit, the internal
write sequence will commence. At the completion of
the internal write sequence a fuse will be set disabling
the write function for the 16 byte security page.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.7
Security Access Read
8.3
WP
The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).
8.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC174 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Note: The level on A1 is compared to the inverse
of the slave address.
Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either VSS or
VCC.
DS21101H-page 8
2004 Microchip Technology Inc.
24LC174
FIGURE 8-1: CURRENT ADDRESS READ
S
T
S
T
O
P
BUS ACTIVITY
A
CONTROL
BYTE
MASTER
R
DATA n
T
S
1
A2 A1 A0 B2 B1 B0
SDA LINE
P
N
O
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 8-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
O
DATA (n)
P
1 A2A1A0B2B1B0
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-4: SECURITY CONTROL BYTE ALLOCATION
Block
START
READ/WRITE
Operation
Control Code
R/W
SLAVE ADDRESS
R/W
A
Select
Read
Write
0110
0110
000
000
1
0
0
1
1
0
0
0
0
MSB
LSB
2004 Microchip Technology Inc.
DS21101H-page 9
24LC174
FIGURE 8-5: SECURITY PAGE READ
S
T
S
T
A
R
T
CONTROL
A
WORD
ADDRESS (n)
CONTROL
BYTE
DATA 0
BYTE
R
T
BUS MASTER
ACTIVITY
SDA LINE
S 0 1 1 0
0
S 0 1 1 0
1
R/W
R/W
A
A
C
K
A
A
C
K
BUS ACTIVITY
C
K
C
K
S
T
O
P
BUS ACTIVITY
MASTER
DATA 1
DATA 2
DATA 3
DATA 15
SDA LINE
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 8-6: SECURITY PAGE WRITE
S
T
A
R
T
S
CONTROL
BYTE
WORD
ADDRESS (n)
T
DATA (n)
DATA n + 1
DATA n + 15
BUS MASTER
ACTIVITY
O
P
SDA LINE
S 0 1 1 0
0
P
R/W
N
O
A
A
C
K
A
C
K
A
C
K
C
K
BUS ACTIVITY
A
C
K
DS21101H-page 10
2004 Microchip Technology Inc.
24LC174
24LC174 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24LC174
–
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
24LC174
24LC174T
16K I2C Serial EEPROM
Device:
16K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21101H-page 11
24LC174
NOTES:
DS21101H-page 12
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21101H-page 13
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Italy
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Fax: 650-961-0286
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Netherlands
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Toronto
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ASIA/PACIFIC
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United Kingdom
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Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
2004 Microchip Technology Inc.
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