24LC21/PROC [MICROCHIP]
128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, MS-001, DIP-8;
| 型号： | 24LC21/PROC |
| 厂家： | 
MICROCHIP |
| 描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, MS-001, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not recommended for new designs –
Please use 24LCS21A.
24LC21
1K 2.5V Dual Mode I2C™ Serial EEPROM
Features:
Package Types
PDIP
• Single supply with operation down to 2.5V
™
™
• Completely implements DDC1 /DDC2 interface
for monitor identification
NC
NC
1
2
8
7
VCC
• Low-power CMOS technology:
- 1 mA active current typical
VCLK
- 10 A standby current typical at 5.5V
NC
3
4
6
5
SCL
SDA
2
™
• 2-wire serial interface bus, I C compatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
VSS
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
SOIC
1
2
8
7
NC
NC
VCC
• 8-pin PDIP and SOIC package
VCLK
• Available for extended temperature ranges
Commercial (C):
Industrial (I):
0°C to +70°C
-40°C to +85°C
3
4
5
5
NC
SCL
SDA
VSS
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial and industrial temperature ranges.
Block Diagram
VCLK
HV Generator
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
Page Latches
SDA SCL
YDEC
VCC
VSS
Sense Amp
R/W Control
1994-2012 Microchip Technology Inc.
DS21095K-page 1
24LC21
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V
DC CHARACTERISTICS
Parameter
Commercial (C): TA = 0°C to +70°C
Industrial
(I): TA = -40°C to +85°C
Symbol
Min
Max
Units
Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage
VIH
VIL
.7 VCC
—
—
.3 VCC
V
V
—
—
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
VIH
VIL
2.0
—
.8
.2 VCC
V
V
VCC 2.7V (Note 1)
VCC < 2.7V (Note 1)
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
VHYS
VOL1
.05 VCC
—
—
.4
V
V
(Note 1)
IOL = 3 mA, VCC = 2.5V (Note 1)
IOL = 6 mA, VCC = 2.5V
VIN = .1V to VCC
Low-level output voltage
VOL2
—
.6
V
Input leakage current
ILI
-10
-10
—
10
10
10
A
A
pF
Output leakage current
ILO
VOUT = .1V to VCC
Pin capacitance (all inputs/outputs)
CIN, COUT
VCC = 5.0V (Note1),
TA = 25C, FCLK = 1 MHz
Operating current
Standby current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V, SCL = 400 kHz
ICCS
—
—
30
100
A
A
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: VLCK must be grounded.
DS21095K-page 2
1994-2012 Microchip Technology Inc.
24LC21
TABLE 1-2:
AC CHARACTERISTICS
Vcc= 4.5 - 5.5V
Fast Mode
Standard Mode
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
—
Clock high time
—
Clock low time
—
—
ns
—
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first clock
pulse is generated
Start condition setup time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
Start condition
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
—
250
4000
—
100
600
—
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min. to VIL max.
TOF
TSP
—
—
—
250
50
20 + .1
CB
250
50
ns
ns
(Note 1), CB 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
(Note 3)
Write cycle time
TWR
10
—
10
ms
Byte or Page mode
Transmit-only Mode Parameters
Output valid from VCLK
VCLK high time
TVAA
TVHIGH
TVLOW
TVHZ
—
4000
4700
—
2000
—
—
600
1300
—
1000
—
ns
ns
ns
ns
ns
—
—
—
—
—
VCLK low time
—
—
Mode transition time
500
—
500
—
Transmit-only power-up
time
TVPU
0
0
Endurance
—
1M
—
1M
—
cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
™
application, please consult the Total Endurance Model which can be obtained from Microchip’s web site
at: www.microchip.com
1994-2012 Microchip Technology Inc.
DS21095K-page 3
24LC21
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.0
FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-only
mode and the Bidirectional mode. There is a separate
two-wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.2
Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-only mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
2.1
Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two-wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
FIGURE 2-1:
TRANSMIT-ONLY MODE
SCL
TVAA
TVAA
SDA
Null Bit
Bit 1 (LSB)
Bit 1 (MSB)
Bit 7
VCLK
TVHIGH
TVLOW
FIGURE 2-2:
DEVICE INITIALIZATION
VCC
SCL
TVAA
TVAA
High-impedance for 9 clock cycles
TVPU
Bit 8
Bit 7
SDA
VCLK
1
2
8
9
10
11
DS21095K-page 4
1994-2012 Microchip Technology Inc.
24LC21
3.1
Bidirectional Mode Bus
Characteristics
3.0
BIDIRECTIONAL MODE
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is disregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the Start and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines Start condition. All
commands must be preceded by a Start condition.
START DATA TRANSFER (B)
a
3.1.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines Stop condition. All
operations must be ended with a Stop condition.
STOP DATA TRANSFER (C)
a
FIGURE 3-1:
MODE TRANSITION
Transmit-only mode
Bidirectional mode
SCL
TVHZ
SDA
VCLK
FIGURE 3-2:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Stop
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
1994-2012 Microchip Technology Inc.
DS21095K-page 5
24LC21
3.1.4
DATA VALID (D)
3.1.5
ACKNOWLEDGE
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Note:
The 24LC21 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3:
BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
Start
Stop
FIGURE 3-4:
BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
DS21095K-page 6
1994-2012 Microchip Technology Inc.
24LC21
3.1.6
SLAVE ADDRESS
4.0
4.1
WRITE OPERATION
Byte Write
After generating a Start condition, the bus master trans-
mits the slave address consisting of a 7-bit device code
‘1010’ for the 24LC21, followed by three “don’t care”
bits.
Following the Start signal from the master, the slave
address (4 bits), the “don’t care” bits (3 bits) and the
R/W bit which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word
address and will be written into the address pointer of
the 24LC21. After receiving another Acknowledge
signal from the 24LC21 the master device will transmit
the data word to be written into the addressed mem-
ory location. The 24LC21 acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle, and during this time the
24LC21 will not generate Acknowledge signals
(Figure 4-1).
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC21 (Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
Operation Control Code
Chip Select R/W
Read
Write
1010
1010
xxx
xxx
1
0
FIGURE 3-5:
CONTROL BYTE
ALLOCATION
Start
Read/Write
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
SLAVE ADDRESS
R/W
A
4.2
Page Write
1
0
1
0
x
x
x
The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to eight data bytes to the
24LC21, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
1994-2012 Microchip Technology Inc.
DS21095K-page 7
24LC21
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
Note:
Page write operations are limited to writing
bytes within single physical page,
a
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size - 1]. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
FIGURE 4-1:
BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
Control
Byte
Word
Address
Data
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
VCLK
FIGURE 4-2:
BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
Control
Byte
Word
Address
Data
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
VCLK
DS21095K-page 8
1994-2012 Microchip Technology Inc.
24LC21
FIGURE 4-3:
PAGE WRITE
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
Control
Byte
Word
Address
O
Data (n)
Data (n + 1)
Data (n + 15)
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
VCLK
1994-2012 Microchip Technology Inc.
DS21095K-page 9
24LC21
5.0
ACKNOWLEDGE POLLING
6.0
WRITE PROTECTION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
When using the 24LC21 in the Bidirectional mode, the
VCLK pin operates as the write-protect control pin.
Setting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to VSS would allow the
24LC21 to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit-only mode.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS21095K-page 10
1994-2012 Microchip Technology Inc.
24LC21
7.3
Sequential Read
7.0
READ OPERATION
Sequential reads are initiated in the same way as a
random read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
To provide sequential reads the 24LC21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
The 24LC21 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24LC21
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-1).
7.4
Noise Protection
The 24LC21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC21 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate
a
Stop condition and the 24LC21
discontinues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
Control
Byte
Data (n)
SDA LINE
S
P
N
O
A
C
K
BUS ACTIVITY
A
C
K
1994-2012 Microchip Technology Inc.
DS21095K-page 11
24LC21
FIGURE 7-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address
Control
Byte
BUS ACTIVITY
MASTER
Data (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
Data (n + X)
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS21095K-page 12
1994-2012 Microchip Technology Inc.
24LC21
8.2
SCL
8.0
PIN DESCRIPTIONS
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit-only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-only mode.
TABLE 8-1:
Name
PIN FUNCTION TABLE
Function
VSS
SDA
SCL
VCLK
VCC
NC
Ground
Serial Address/Data I/O
Serial Clock (Bidirectional mode)
Serial Clock (Transmit-only mode)
+2.5V to 5.5V Power Supply
No Connection
8.3
VCLK
This pin is the clock input for the Transmit-only mode.
In the Transmit-only mode, each bit is clocked out on
the rising edge of this signal. In the Bidirectional mode,
a high logic level is required on this pin to enable write
capability.
8.1
SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bidirectional
mode. In the Transmit-only mode, which only allows
data to be read from the device, data is also transferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10K for 100 kHz, 2K for 400 kHz).
For normal data transfer in the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
1994-2012 Microchip Technology Inc.
DS21095K-page 13
24LC21
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP
Example
24LC21
XXXXXXXX
XXXXXNNN
YYWW
017
0410
Example
8-Lead SOIC (.150”)
24LC21
/SN0410
017
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21095K-page 14
1994-2012 Microchip Technology Inc.
24LC21
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
A1
B1
B
p
eB
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
1994-2012 Microchip Technology Inc.
DS21095K-page 15
24LC21
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
45
c
A2
A
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
8
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.053
.061
.056
.007
.237
.154
.193
.015
.025
4
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21095K-page 16
1994-2012 Microchip Technology Inc.
24LC21
APPENDIX A: REVISION HISTORY
Revision J
Added note to page 1 header (Not recommended for
new designs).
Added Section 9.0: Package Marking Information.
Added On-line Support page.
Updated document format.
Revision K
Added a note to each package outline drawing.
1994-2012 Microchip Technology Inc.
DS21095K-page 17
24LC21
NOTES:
DS21095K-page 18
1994-2012 Microchip Technology Inc.
24LC21
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1994-2012 Microchip Technology Inc.
DS21095K-page 19
24LC21
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
Technical Publications Manager
Reader Response
Total Pages Sent ________
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Literature Number: DS21095K
Application (optional):
Would you like a reply?
Y
N
Device: 24LC21
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21095K-page 20
1994-2012 Microchip Technology Inc.
24LC21
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Temperature
Range
Package
Pattern
2
™
Device
24LC21: Dual Mode I C Serial EEPROM
2
™
24LC21T: Dual Mode I C Serial EEPROM (Tape and Reel)
Temperature Range Blank
I
=
=
0C to +70C
-40C to +85C
Package
P
SN
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1994-2012 Microchip Technology Inc.
DS21095K-page 21
24LC21
NOTES:
DS21095K-page 22
1994-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1994-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620767306
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
1994-2012 Microchip Technology Inc.
DS21095K-page 23
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
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Fax: 91-80-3090-4123
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Fax: 45-4485-2829
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Tel: 630-285-0071
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Tel: 86-571-2819-3187
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Tel: 86-21-5407-5533
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Tel: 86-24-2334-2829
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Tel: 86-755-8203-2660
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Tel: 886-7-213-7828
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Tel: 949-462-9523
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Tel: 86-27-5980-5300
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Tel: 886-2-2508-8600
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Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
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Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
10/26/12
DS21095K-page 24
1994-2012 Microchip Technology Inc.
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