24LC65T-I/SM204_技术文档

24AA65/24LC65/24C65

64K I²C^™Smart Serial^™EEPROM

Device Selection Table

Part Number

VCC Range

Page Size

Temp. Ranges

Packages

24AA65

24LC65

24C65

1.8-6.0V

2.5-6.0V

4.5-6.0V

64 Bytes

C

P, SM

C, I

C, I, E

Features:

Description:

• Voltage Operating Range: 1.8V to 6.0V

- Peak write current 3 mA at 6.0V

- Maximum read current 150 μA at 6.0V

- Standby current 1 μA, typical

The Microchip Technology Inc. 24AA65/24LC65/

24C65 (24XX65)* is a “smart” 8K x 8 Serial Electrically

Erasable PROM. This device has been developed for

advanced, low-power applications such as personal

communications, and provides the systems designer

with flexibility through the use of many new user-pro-

grammable features. The 24XX65 offers a relocatable

4K bit block of ultra-high-endurance memory for data

that changes frequently. The remainder of the array, or

60K bits, is rated at 1,000,000 erase/write (E/W) cycles

ensured. The 24XX65 features an input cache for fast

write loads with a capacity of eight pages, or 64 bytes.

This device also features programmable security

options for E/W protection of critical data and/or code

of up to fifteen 4K blocks. Functional address lines

allow the connection of up to eight 24XX65’s on the

same bus for up to 512K bits contiguous EEPROM

memory. Advanced CMOS technology makes this

device ideal for low-power nonvolatile code and data

applications. The 24XX65 is available in the standard

8-pin plastic DIP and 8-pin surface mount SOIJ

package.

• Industry Standard Two-Wire Bus Protocol I²C™

Compatible

• 8-Byte Page, or Byte modes Available

• 2 ms Typical Write Cycle Time, Byte or Page

• 64-Byte Input Cache for Fast Write Loads

• Up to 8 devices may be connected to the same

bus for up to 512K bits total memory

• Including 100 kHz (1.8V ≤ Vcc < 4.5V) and 400

kHz (4.5V ≤ VCC ≤ 6.0V) Compatibility

• Programmable Block Security Options

• Programmable Endurance Options

• Schmitt Trigger, Filtered Inputs for Noise

Suppression

• Output Slope Control to Eliminate Ground Bounce

• Self-Timed Erase and Write Cycles

• Power-on/off Data Protection Circuitry

• Endurance:

Package Types

- 10,000,000 E/W cycles for a High Endurance

Block

PDIP

A0

A1

1

2

8

7

VCC

- 1,000,000 E/W cycles for a Standard

Endurance Block

NC

• Electrostatic Discharge Protection > 4000V

• Data Retention > 200 years

A2

3

4

6

5

SCL

SDA

VSS

• 8-pin PDIP/SOIJ Packages

•

Temperature Ranges

SOIJ

- Industrial (I)

- Automotive (E)

-40°C to +85°C

-40°C to +125°C

1

2

8

7

A0

V

CC

• Pb-Free and RoHS Compliant

A1

A2

NC

3

4

6

5

SCL

SDA

VSS

*24XX65 is used in this document as a generic part

number for the 24AA65/24LC65/24C65 devices.

DS21073K-page 1

24AA65/24LC65/24C65

Block Diagram

Pin Function Table

A0 A1 A2

Name

Function

HV Generator

A0, A1, A2

VSS

User Configurable Chip Selects

Ground

I/O

Control

Logic

Memory

Control

Logic

EEPROM

Array

SDA

Serial Address/Data/I/O

Serial Clock

XDEC

SCL

Page Latches

VCC

+1.8V to 6.0V Power Supply

No Internal Connection

NC

I/O

SCL

Cache

YDEC

SDA

VCC

VSS

Sense Amp.

R/W Control

DS21073K-page 2

24AA65/24LC65/24C65

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

VCC = +1.8V to +6.0V

Commercial

Industrial

Automotive

(C): TA =

(I): TA =

(E): TA =

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

DC CHARACTERISTICS

Parameter

Sym

Min

Max

Units

Conditions

A0, A1, A2, SCL and SDA pins:

High-level input voltage

VIH

VIL

.7 VCC

—

.05 VCC

—

.3 VCC

—

V

Low-level input voltage

Hysteresis of Schmitt Trigger inputs VHYS

Low-level output voltage

(Note 1)

IOL = 3.0 mA

VOL

.40

Input leakage current

ILI

—

±1

10

μA

pF

VIN = .1V to VCC

VOUT = .1V to VCC

Output leakage current

ILO

Pin capacitance

CIN, COUT

VCC = 5.0V (Note 1)

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

Operating current

ICC Write

ICC Read

—

3

150

mA

μA

VCC = 6.0V, SCL = 400 kHz

Standby current

ICCS

—

5

μA

VCC = 5.0V, SCL = SDA = VCC

A0, A1, A2 = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1:

BUS TIMING START/STOP

VHYS

SCL

THD:STA

TSU:STA

TSU:STO

SDA

Start

Stop

DS21073K-page 3

24AA65/24LC65/24C65

TABLE 1-2:

AC CHARACTERISTICS

VCC = 1.8V-6.0V VCC = 4.5-6.0V

STD. Mode FAST Mode

Parameter

Symbol

Units

Remarks

Min

Max

Min

Max

Clock frequency

FCLK

THIGH

TLOW

TR

—

4000

4700

—

100

—

600

1300

—

400

—

kHz

ns

Clock high time

Clock low time

—

ns

SDA and SCL rise time

SDA and SCL fall time

Start condition setup time

1000

300

—

300

—

ns

(Note 1)

TF

—

ns

(Note 1)

THD:STA 4000

600

ns

After this period the first

clock pulse is generated

Start condition setup time

TSU:STA

4700

—

600

—

ns

Only relevant for

repeated Start condition

Data input hold time

Data input setup time

Stop condition setup time

Output valid from clock

Bus free time

THD:DAT

TSU:DAT

TSU:STO

TAA

0

—

0

—

ns

250

4000

—

100

600

—

3500

—

900

—

(Note 2)

TBUF

4700

1300

Time the bus must be

free before a new

transmission can start

Output fall time from VIH min to TOF

VIL max

—

50

—

250

—

5

20 + 0.1

CB

250

—

5

ns

(Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

TSP

50

(Note 3)

Write cycle time

TWR

—

ms/page (Note 4)

Endurance

High Endurance Block

Rest of Array

10M

1M

—

10M

1M

—

cycles 25°C, (Note 5)

Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.

FIGURE 1-2:

BUS TIMING DATA

TF

TR

THIGH

TLOW

THD:STA

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

SDA

IN

TSP

TBUF

TAA

SDA

OUT

DS21073K-page 4

24AA65/24LC65/24C65

3.3

Stop Data Transfer (C)

2.0

FUNCTIONAL DESCRIPTION

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

The 24XX65 supports a bidirectional two-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus must be controlled

by a master device which generates the serial clock

(SCL), controls the bus access and generates the Start

and Stop conditions, while the 24XX65 works as slave.

Both master and slave can operate as transmitter or

receiver, but the master device determines which mode

is activated.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

3.0

BUS CHARACTERISTICS

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note:

The 24XX65 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain high.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX65) must leave the data line high to enable

the master to generate the Stop condition.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

To Change

DS21073K-page 5

24AA65/24LC65/24C65

3.6

Device Addressing

4.0

4.1

WRITE OPERATION

Byte Write

A control byte is the first byte received following the

Start condition from the master device. The control byte

consists of a four-bit control code, for the 24XX65 this

is set as ‘1010’ binary for read and write operations.

The next three bits of the control byte are the device

select bits (A2, A1, A0). They are used by the master

device to select which of the eight devices are to be

accessed. These bits are in effect the three Most

Significant bits of the word address. The last bit of the

control byte defines the operation to be performed.

When set to a one a read operation is selected, when

set to a zero a write operation is selected. The next two

bytes received define the address of the first data byte

(Figure 4-1). Because only A12..A0 are used, the

upper three address bits must be zeros. The Most

Significant bit of the Most Significant Byte is transferred

first. Following the Start condition, the 24XX65

monitors the SDA bus checking the device type

identifier being transmitted. Upon receiving a ‘1010’

code and appropriate device select bits, the slave

device (24XX65) outputs an Acknowledge signal on the

SDA line. Depending upon the state of the R/W bit, the

24XX65 will select a read or write operation.

Following the Start condition from the master, the con-

trol code (four bits), the device select (three bits), and

the R/W bit which is a logic low, is placed onto the bus

by the master transmitter. This indicates to the

addressed slave receiver (24XX65) that a byte with a

word address will follow after it has generated an

Acknowledge bit during the ninth clock cycle. There-

fore, the next byte transmitted by the master is the

high-order byte of the word address and will be written

into the Address Pointer of the 24XX65. The next byte

is the Least Significant Address Byte. After receiving

another Acknowledge signal from the 24XX65, the

master device will transmit the data word to be written

into the addressed memory location. The 24XX65

acknowledges again and the master generates a Stop

condition. This initiates the internal write cycle, and

during this time the 24XX65 will not generate

Acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX65 in the same way as

in a byte write. But instead of generating a Stop

condition, the master transmits up to eight pages of

eight data bytes each (64 bytes total), which are

temporarily stored in the on-chip page cache of the

24XX65. They will be written from the cache into the

EEPROM array after the master has transmitted a Stop

condition. After the receipt of each word, the six lower

order Address Pointer bits are internally incremented by

one. The higher order seven bits of the word address

remain constant. If the master should transmit more

than eight bytes prior to generating the Stop condition

(writing across a page boundary), the address counter

(lower three bits) will roll over and the pointer will be

incremented to point to the next line in the cache. This

can continue to occur up to eight times or until the cache

is full, at which time a Stop condition should be

generated by the master. If a Stop condition is not

received, the cache pointer will roll over to the first line

(byte 0) of the cache, and any further data received will

overwrite previously captured data. The Stop condition

can be sent at any time during the transfer. As with the

byte write operation, once the Stop condition is received

an internal write cycle will begin. The 64-byte cache will

continue to capture data until a Stop condition occurs or

the operation is aborted (Figure 4-2).

Operation Control Code Device Select R/W

Read

Write

1010

Device Address

DeviceAddress

1

0

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

A

1

0

1

0

A2

A1

A0

DS21073K-page 6

24AA65/24LC65/24C65

FIGURE 4-1:

BYTE WRITE

S

T

A

R

T

S

Bus Activity

Master

Word

Address (0)

Word

Address (1)

T

Control

Byte

Data

O

P

0 0 0

S

SDA Line

P

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

FIGURE 4-2:

PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2)

S

T

A

R

T

S

T

O

P

Word

Address (1)

Word

Address (0)

Control

Byte

Bus

Activity

Master

Data n

Data n + 7

S

P

SDA Line

0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Bus

Activity:

FIGURE 4-3:

CURRENT ADDRESS READ

S

T

S

T

Bus Activity

Control

Byte

A

R

T

Data n

Master

O

P

SDA Line

S

P

A

C

K

N

O

Bus Activity

A

C

K

DS21073K-page 7

24AA65/24LC65/24C65

FIGURE 4-4:

RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

Word

Address (1)

Control

Byte

Word

Address (0)

Control

Byte

Data n

0 0 0

P

SDA Line

S

N

O

A

C

K

A

C

K

A

C

K

A

C

K

Bus

Activity

A

C

K

FIGURE 4-5:

SEQUENTIAL READ

S

T

O

P

Bus Activity

Master

Control

Data n

Byte

Data n + 1

Data n + 2

Data n + X

SDA Line

P

A

C

K

A

C

K

A

C

K

N

O

C

Bus Activity

K

A

C

K

DS21073K-page 8

24AA65/24LC65/24C65

5.4

Contiguous Addressing Across

Multiple Devices

5.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read

and sequential read.

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX65's on the same bus.

In this case, software can use A0 of the control byte as

address bit A13, A1 as address bit A14 and A2 as

address bit A15.

5.1

Current Address Read

The 24XX65 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address n (n is

any legal address), the next current address read

operation would access data from address n + 1. Upon

receipt of the slave address with R/W bit set to one, the

24XX65 issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the transfer but does generate a Stop condition and the

24XX65 discontinues transmission (Figure 4-3).

5.5

Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operation even on a noisy bus. All I/O lines incorporate

Schmitt Triggers for 400 kHz (Fast mode) compatibility.

5.6

High Endurance Block

The location of the high endurance block within the

memory map is programmed by setting the leading bit

7 (S/HE) of the configuration byte to ‘0’. The upper bits

of the address loaded in this command will determine

which 4K block within the memory map will be set to

high endurance. This block will be capable of

10,000,000 erase/write cycles typical (Figure 8-1).

5.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24XX65 as part of a write operation (R/W bit set to ‘0’).

After the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. Then the master issues

the control byte again, but with the R/W bit set to a one.

The 24XX65 will then issue an acknowledge and

transmit the eight-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition which causes the 24XX65 to discontinue

transmission (Figure 4-4).

The high endurance block will retain its value as the

high endurance block even if it resides within the

security block range. The high endurance setting

always takes precedence to the security setting.

Note:

The high endurance block cannot be

changed after the security option has been

set with a length greater than zero. If the

H.E. block is not programmed by the user,

the default location is the highest block of

memory which starts at location 0x1E00

and ends at 0x1FFF.

5.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX65 transmits the

first data byte, the master issues an acknowledge as

opposed to the Stop condition used in a random read.

This acknowledge directs the 24XX65 to transmit the

next sequentially addressed 8-bit word (Figure 4-5).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge, but will

generate a Stop condition.

To provide sequential reads the 24XX65 contains an

internal Address Pointer which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

DS21073K-page 9

24AA65/24LC65/24C65

acknowledge the second, and then send a Stop bit to

end the sequence. The upper four bits of both of these

bytes will always be read as ‘1’s. The lower four bits of

the first byte contains the starting secure block. The

lower four bits of the second byte contains the number

of secure blocks. The default starting secure block is

fifteen and the default number of secure blocks is zero

(Figure 8-1).

5.7

Security Options

The 24XX65 has a sophisticated mechanism for write

protecting portions of the array. This write-protect

function is programmable and allows the user to protect

0-15 contiguous 4K blocks. The user sets the security

option by sending to the device the starting block

number for the protected region and the number of

blocks to be protected. All parts will come from the

factory in the default configuration with the starting

block number set to 15 and the number of protected

blocks set to zero. THE SECURITY OPTION CAN BE

SET ONLY ONCE WITH A LENGTH GREATER THAN

ZERO.

6.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 6-1 for flow

diagram.

To invoke the security option, a Write command is sent

to the device with the leading bit (bit 7) of the first

address byte set to a ‘1’ (Figure 8-1). Bits 1-4 of the first

address byte define the starting block number for the

protected region.

For example, if the starting block number is to be set to

5, the first address byte would be 1XX0101X. Bits 0, 5

and 6 of the first address byte are disregarded by the

device and can be either high or low. The device will

acknowledge after the first address byte. A byte of

“don’t care” bits is then sent by the master, with the

device acknowledging afterwards. The third byte sent

to the device has bit 7 (S/HE) set high and bit 6 (R) set

low. Bits 4 and 5 are “don’t cares” and bits 0-3 define

the number of blocks to be write-protected. For exam-

ple, if three blocks are to be protected, the third byte

would be 10XX0011. After the third byte is sent to the

device, it will acknowledge and a Stop bit is then sent

by the master to complete the command.

FIGURE 6-1:

ACKNOWLEDGE

POLLING FLOW

Send

Write Command

If one of the security blocks coincides with the high

endurance block, the high endurance setting will take

precedence. Also, if the range of the security blocks

encompass the high endurance block when the secu-

rity option is set, the security block range will be set

accordingly, but the high endurance block will continue

to retain the high endurance setting. As a result, the

memory blocks preceding the high endurance block will

be set as secure sections.

Send Stop

Condition to

Initiate Write Cycle

Send Start

During a normal write sequence, if an attempt is made

to write to a protected address, no data will be written

and the device will not report an error or abort the

command. If a Write command is attempted across a

secure boundary, unprotected addresses will be written

and protected addresses will not.

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

NO

5.8

Security Configuration Read

The status of the secure portion of memory can be read

by using the same technique as programming this

option except the read bit (bit 6) of the configuration

byte is set to a one. After the configuration byte is sent,

the device will acknowledge and then send two bytes of

data to the master just as in a normal read sequence.

The master must acknowledge the first byte and not

YES

DS21073K-page 10

24AA65/24LC65/24C65

fully loaded cache of 64 bytes. Since the cache started

loading at byte 2, the last two bytes loaded into the

cache will ‘roll over' and be loaded into the first two

bytes of page 0 (of the cache). When the Stop bit is

sent, page 0 of the cache is written to page 3 of the

array. The remaining pages in the cache are then

loaded sequentially to the array. A write cycle is

executed after each page is written. If a partially loaded

page in the cache remains when the Stop bit is sent,

only the bytes that have been loaded will be written to

the array.

7.0

PAGE CACHE AND ARRAY

MAPPING

The cache is a 64-byte (8 pages x 8 bytes) FIFO buffer.

The cache allows the loading of up to 64 bytes of data

before the write cycle is actually begun, effectively

providing a 64-byte burst write at the maximum bus

rate. Whenever a Write command is initiated, the cache

starts loading and will continue to load until a Stop bit is

received to start the internal write cycle. The total

length of the write cycle will depend on how many

pages are loaded into the cache before the Stop bit is

given. Maximum cycle time for each page is 5 ms. Even

if a page is only partially loaded, it will still require the

same cycle time as a full page. If more than 64 bytes of

data are loaded before the Stop bit is given, the

Address Pointer will ‘wrap around’ to the beginning of

cache page 0 and existing bytes in the cache will be

overwritten. The device will not respond to any

commands while the write cycle is in progress.

7.3

Power Management

The design incorporates a power Standby mode when

not in use and automatically powers off after the normal

termination of any operation when a Stop bit is received

and all internal functions are complete. This includes

any error conditions (i.e., not receiving an Acknowl-

edge or Stop condition per the two-wire bus specifica-

tion). The device also incorporates VDD monitor

circuitry to prevent inadvertent writes (data corruption)

during low voltage conditions. The VDD monitor circuitry

is powered off when the device is in Standby mode in

order to further reduce power consumption.

7.1

Cache Write Starting at a Page

Boundary

If a Write command begins at a page boundary

(address bits A2, A1 and A0 are zero), then all data

loaded into the cache will be written to the array in

sequential addresses. This includes writing across a

4K block boundary. In the example shown below,

(Figure 8-2) a Write command is initiated starting at

byte 0 of page 3 with a fully loaded cache (64 bytes).

The first byte in the cache is written to byte 0 of page 3

(of the array), with the remaining pages in the cache

written to sequential pages in the array. A write cycle is

executed after each page is written. Since the write

begins at page 3 and 8 pages are loaded into the

cache, the last 3 pages of the cache are written to the

next row in the array.

8.0

8.1

PIN DESCRIPTIONS

A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24XX65 for multiple

device operation and conform to the two-wire bus

standard. The levels applied to these pins define the

address block occupied by the device in the address

map. A particular device is selected by transmitting the

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-2 and Figure 8-1).

8.2

SDA Serial Address/Data Input/

Output

7.2

Cache Write Starting at a

Non-Page Boundary

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for 400

kHz).

When a Write command is initiated that does not begin

at a page boundary (i.e., address bits A2, A1 and A0

are not all zero), it is important to note how the data is

loaded into the cache, and how the data in the cache is

written to the array. When a Write command begins, the

first byte loaded into the cache is always loaded into

page 0. The byte within page 0 of the cache where the

load begins is determined by the three Least Significant

Address bits (A2, A1, A0) that were sent as part of the

Write command. If the Write command does not start at

byte 0 of a page and the cache is fully loaded, then the

last byte(s) loaded into the cache will roll around to

page 0 of the cache and fill the remaining empty bytes.

If more than 64 bytes of data are loaded into the cache,

data already loaded will be overwritten. In the example

shown in Figure 8-3, a Write command has been

initiated starting at byte 2 of page 3 in the array with a

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

8.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

DS21073K-page 11

24AA65/24LC65/24C65

FIGURE 8-1:

CONTROL SEQUENCE BIT ASSIGNMENTS

Control Byte

Address Byte 1

Address Byte 0

Configuration Byte

A

7

A

0

A A

A

0

A

A A A A

B B B B

2

3 1 0

X

R X

1

0

1

0

S

0

•

R/W

2

1

12 1110 9

8

S/HE

Slave Device

Address Select

Bits

Block

Count

Security Read

Acknowledge

from

No

ACK

S

Master

S

t

Acknowledges from Device

t

a

r

Data from Device

o

p

R

t

A

C

K

A

C

K

A

C

K

A

C

K

A A

A

0

B

2

N N N N

1

B

3

B B

C

K

X X X X X

X X X X X X X

X

X X X

1

0

1

0

1

X X

X

1

X

1

2

1

3

2

1 0

1

0

S/HE

Starting Block

Number

Number of

Blocks to

Protect

Security Write

S

t

Acknowledges from Device

a

r

o

p

t

R

0

A

C

K

A

C

K

A

C

K

A

C

K

A A

A

0

N N N N

X

B B B

B

0

X

X X X X X X X

1

0

1

0

1

X X

X

1

X

2

1

2

3 1 0

3

2

1

S/HE

Starting Block

Number

Number of

Blocks to

Protect

No

High Endurance Block Read

ACK

S

t

S

t

a

r

t

Acknowledges from Device

o

p

Data from Device

R

1

A

C

K

A

C

K

A

C

K

A

C

K

A A

A

0

B

2

B

3

B B

0

X X X X X

X X X X X X X

X

X X X

1

0

1

0

1

X X

X

0

X

1

2

1

S/HE

High Endurance

Block Number

High Endurance Block Write

S

t

Acknowledges from Device

a

r

o

p

t

R

0

A

C

K

A

C

K

A

C

K

A

C

K

A A

A

0

B B B

B

0

X

X X X X X X X

X

0 0 0

0

1

0

1

0

1

X X

X

0

X

2

1

3

2

1

S/HE

High Endurance

Block Number

DS21073K-page 12

24AA65/24LC65/24C65

FIGURE 8-2:

CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

1

Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0.

2 64 bytes of data are loaded into cache.

cache page 0

cache cache

byte 0 byte 1

cache cache page 1 cache page 2

byte 7 bytes 8-15 bytes 16-23

cache page 7

bytes 56-63

• • •

3

Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

4

Remaining pages in cache are written

to sequential pages in array.

Write cycle is executed after every page is written.

array row n

page 0 page 1 page 2 byte 0 byte 1

• • • byte 7 page 4 • • • page 7

array row n + 1

page 0 page 1 page 2

page 3 page 4 • • • page 7

5

Last page in cache written to page 2 in next row.

FIGURE 8-3:

CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY

1

Write command initiated; 64 bytes of data

loaded into cache starting at byte 2 of page 0.

2

Last 2 bytes loaded 'roll over'

to beginning.

3

Last 2 bytes

loaded into

cache cache cache

byte 0 byte 1 byte 2

cache cache page 1 cache page 2

byte 7 bytes 8-15 bytes 16-23

cache page 7

bytes 56-63

page 0 of cache.

• • •

4

Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

5

Remaining bytes in cache are

written sequentially to array.

Write cycle is executed after every page is written.

array

page 0 page 1 page 2

• • •

page 4 • • • page 7

byte 0 byte 1 byte 2 byte 3 byte 4

page 3

byte 7

row n

array

row

n + 1

6

Last 3 pages in cache written to next row in array.

DS21073K-page 13

24AA65/24LC65/24C65

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24LC65

I/P017

XXXXXXXX

T/XXXNNN

YYWW

0310

8-Lead SOIJ (5.28 mm)

Example:

XXXXXXXX

T/XXXXXX

YYWWNNN

24LC65

I/SM

0110017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

DS21073K-page 14

24AA65/24LC65/24C65

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DS21073K-page 15

24AA65/24LC65/24C65

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DS21073K-page 16

24AA65/24LC65/24C65

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS21073K-page 17

24AA65/24LC65/24C65

APPENDIX A: REVISION HISTORY

Revision J

Corrections to Section 1.0, Electrical Characteristics.

Revision K (07/2008)

Revised Temperature ranges; Ambient temperature;

Revised Package Drawings; Replaced On-line

Support; Revised Product ID System.

DS21073K-page 18

24AA65/24LC65/24C65

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS21073K-page 19

24AA65/24LC65/24C65

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

24AA65/24LC65/24C65

DS21073K

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21073K-page 20

24AA65/24LC65/24C65

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a) 24LC65T-I/SM: 64 Kbit Smart Serial,

Tape and Reel, 5.28 mm SOIJ package,

Industrial temperature, 2.5V

b) 24LC65-I/P: 64 Kbit Smart Serial,

Industrial temperature, PDIP package,

2.5V

Device:

24AA65 - 64K I²C 1.8V Serial EEPROM (100 kHz)

24AA65T - 64K I²C 1.8V Serial EEPROM (100 kHz)

24LC65 - 64K I²C Serial EEPROM (100 kHz/400 kHz)

24LC65T - 64K I²C Serial EEPROM (Tape and Reel)

24C65 - 64K I²C 4.5V Serial EEPROM (400 kHz)

24C65T - 64K I²C 4.5V Serial EEPROM (Tape and Reel)

c) 24AA65T-/SM: 64 Kbit Smart Serial,

Tape and Reel, 5.28 mm SOIJ package,

Commercial temperature, 1.8V

d) 24C65-E/P: 64 Kbit Smart Serial,

Automotive temperature, PDIP, 5V

Temperature

Range:

I

E

=

-40°C to +85°C

-40°C to +125°C

Package:

P

SM

=

Plastic DIP (300 mil Body)

Plastic SOIJ (5.28 mm Body, EIAJ standard)

DS21073K-page 21

24AA65/24LC65/24C65

NOTES:

DS21073K-page 22

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC and SmartShunt are registered trademarks

of Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

32

PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21073K-page 23

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS21073K-page 24


型号：	24LC65T-I/SM204
厂家：	MICROCHIP
描述：	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
文件：	总24页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24LC65T-I/SM204 [MICROCHIP]

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