25AA040AT-I/MS_技术文档

25AA040A/25LC040A

4K SPI Bus Serial EEPROM

Device Selection Table

Part Number

VCC Range

Page Size

Temp. Ranges

Packages

25AA040A

25LC040A

1.8-5.5V

2.5-5.5V

16 Bytes

I

P, MS, SN, ST, MC, OT

I, E

Features:

Description:

• Max. Clock 10 MHz

The Microchip Technology Inc. 25XX040A* is a 4 Kbit

Serial Electrically Erasable Programmable Read-Only

Memory (EEPROM). The memory is accessed via a

simple Serial Peripheral Interface (SPI) compatible

serial bus. The bus signals required are a clock input

(SCK) plus separate data in (SI) and data out (SO)

lines. Access to the device is controlled through a Chip

Select (CS) input.

• Low-Power CMOS Technology:

- Max. Write Current: 5 mA at 5.5V, 10 MHz

- Read Current: 5 mA at 5.5V, 10 MHz

- Standby Current: 5 μA at 5.5V

• 512 x 8-Bit Organization

• Write Page mode (up to 16 bytes)

• Sequential Read

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

• Self-timed Erase and Write Cycles (5 ms max.)

• Block Write Protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection:

The 25XX040A is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packages including 8-lead MSOP, 8-lead TSSOP

and rotated TSSOP, 8-lead 2x3 DFN, and 6-lead

SOT-23.

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High Reliability:

- Endurance: 1,000,000 Erase/Write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

Package Types (not to scale)

PDIP/SOIC

TSSOP/MSOP

(ST, MS)

(P, SN)

• Temperature Ranges Supported:

CS

SO

WP

VCC

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CS

SO

WP

V

CC

- Industrial (I):

- Automotive (E):

-40°C to +85°C

-40°C to +125°C

HOLD

SCK

SI

HOLD

SCK

SI

VSS

• Pb-free Packages Available

VSS

DFN

(MC)

Pin Function Table

SOT-23

(OT)

Name

Function

Chip Select Input

1

2

3

6

5

4

V

CC

SCK

1

8

V

DD

CS

SO

2

3

4

7

6

5

HOLD

SCK

SI

VSS

CS

SO

CS

SO

SI

WP

Serial Data Output

Write-Protect

Ground

VSS

WP

VSS

SI

X-Rotated TSSOP

(X/ST)

Serial Data Input

Serial Clock Input

Hold Input

1

2

3

4

8

HOLD

SCK

SI

7

6

5

VCC

SCK

HOLD

VCC

CS

SO

VSS

WP

Supply Voltage

*25XX040A is used in this document as a generic part number for the

25AA040A and the 25LC040A.

DS21827D-page 1

25AA040A/25LC040A

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Industrial (I):

Automotive (E):

TA = -40°C to +85°C

TA = -40°C to +125°C

VCC = 1.8V to 5.5V

VCC = 2.5V to 5.5V

DC CHARACTERISTICS

Param.

No.

Sym.

Characteristic

Min.

Max.

VCC +1

Units

Test Conditions

D001

VIH1

High-level Input

Voltage

0.7 VCC

V

D002

D003

D004

D005

D006

VIL1

VIL2

VOL

VOH

Low-level Input

Voltage

-0.3

0.3 VCC

0.2 VCC

0.4

V

VCC ≥ 2.7V (Note 1)

VCC < 2.7V (Note 1)

IOL = 2.1 mA

Low-level Output

Voltage

—

0.2

IOL = 1.0 mA, VCC = 2.5V

IOH = -400 μA

High-level Output

Voltage

VCC -0.5

—

D007

D008

D009

ILI

Input Leakage

Current

—

±1

7

μA

pF

CS = VCC, VIN = VSS or VCC

CS = VCC, VOUT = VSS or VCC

ILO

CINT

Output Leakage

Current

Internal Capacitance

(all inputs and

outputs)

TA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note 1)

D010

ICC Read

—

5

mA

VCC = 5.5V; FCLK = 10.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 5.0 MHz;

SO = Open

Operating Current

Standby Current

2.5

D011

D012

ICC Write

ICCS

—

5

3

mA

VCC = 5.5V

VCC = 2.5V

—

5

μA

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, TA = +125°C

CS = VCC = 2.5V, Inputs tied to VCC or

VSS, TA = +85°C

—

1

Note 1: This parameter is periodically sampled and not 100% tested.

DS21827D-page 2

25AA040A/25LC040A

TABLE 1-2:

AC CHARACTERISTICS

Industrial (I):

Automotive (E): TA = -40°C to +125°C

TA = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Param.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

No.

1

2

3

FCLK Clock Frequency

—

10

5

3

MHz 4.5V ≤ VCC < 5.5V

MHz 2.5V ≤ VCC < 4.5V

MHz 1.8V ≤ VCC < 2.5V

TCSS CS Setup Time

TCSH CS Hold Time

TCSD CS Disable Time

50

100

150

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

100

200

250

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

4

5

50

—

ns

—

Tsu

Data Setup Time

10

20

30

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

6

THD

Data Hold Time

20

40

50

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

7

8

9

TR

TF

CLK Rise Time

CLK Fall Time

Clock High Time

—

100

ns

(Note 1)

THI

50

100

150

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

10

TLO

Clock Low Time

50

100

150

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

11

12

13

TCLD Clock Delay Time

TCLE Clock Enable Time

50

—

ns

—

TV

Output Valid from Clock

Low

—

50

100

160

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

14

15

THO

TDIS

Output Hold Time

0

—

ns

(Note 1)

Output Disable Time

—

40

80

160

ns

4.5V ≤ VCC < 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

16

THS

HOLD Setup Time

20

40

80

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

DS21827D-page 3

25AA040A/25LC040A

TABLE 1-2:

AC CHARACTERISTICS (CONTINUED)

Industrial (I):

Automotive (E): TA = -40°C to +125°C

TA = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Param.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

No.

17

THH

HOLD Hold Time

20

40

80

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

18

19

THZ

THV

HOLD Low to Output

High-Z

30

60

160

—

ns

4.5V ≤ VCC < 5.5V (Note 1)

2.5V ≤ VCC < 4.5V (Note 1)

1.8V ≤ VCC < 2.5V (Note 1)

HOLD High to Output

Valid

30

60

160

—

ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

20

21

TWC

—

Internal Write Cycle Time

(byte or page)

—

5

ms

(NOTE 3)

Endurance

1M

—

E/W (NOTE 2)

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site:

www.microchip.com.

3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle

is complete.

TABLE 1-3:

AC Waveform:

VLO = 0.2V

AC TEST CONDITIONS

—

VHI = VCC - 0.2V

(Note 1)

(Note 2)

—

VHI = 4.0V

CL = 100 pF

Timing Measurement Reference Level

Input

0.5 VCC

Output

Note 1: For VCC ≤ 4.0V

2: For VCC ≥ 4.0V

DS21827D-page 4

25AA040A/25LC040A

FIGURE 1-1:

HOLD TIMING

CS

17

16

SCK

SO

18

19

High-impedance

n

n + 2

n + 1

n

n - 1

5

Don’t Care

n

n + 2

n + 1

n

n - 1

SI

HOLD

FIGURE 1-2:

SERIAL INPUT TIMING

4

CS

12

11

2

7

3

8

Mode 1,1

Mode 0,0

SCK

SI

5

6

MSB in

LSB in

High-impedance

SO

FIGURE 1-3:

SERIAL OUTPUT TIMING

CS

3

9

10

Mode 1,1

SCK

Mode 0,0

13

15

ISB out

14

MSB out

SO

SI

Don’t Care

DS21827D-page 5

25AA040A/25LC040A

If the write operation is initiated immediately after the

WREN instruction without CS driven high, data will not

be written to the array since the write enable latch was

not properly set.

2.0

2.1

FUNCTIONAL DESCRIPTION

Principles of Operation

The 25XX040A is

a 512-byte Serial EEPROM

After setting the write enable latch, the user may

proceed by driving CS low, issuing a WRITEinstruction,

followed by the remainder of the address, and then the

data to be written. Keep in mind that the Most

Significant address bit (A8) is included in the instruction

byte for the 25XX040A. Up to 16 bytes of data can be

sent to the device before a write cycle is necessary.

The only restriction is that all of the bytes must reside

in the same page. Additionally, a page address begins

with XXXX 0000 and ends with XXXX 1111. If the

internal address counter reaches XXXX 1111 and

clock signals continue to be applied to the chip, the

address counter will roll back to the first address of the

page and over-write any data that previously existed in

those locations.

designed to interface directly with the Serial Peripheral

Interface (SPI) port of many of today’s popular

microcontroller families, including Microchip’s PIC^®

microcontrollers. It may also interface with microcon-

trollers that do not have a built-in SPI port by using dis-

crete I/O lines programmed properly in firmware to

match the SPI protocol.

The 25XX040A contains an 8-bit instruction register.

The device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses and data are transferred MSb first, LSb last.

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’) and, end at addresses that are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25XX040A in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

2.2

Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25XX040A

followed by a 9-bit address. The MSb (A8) is sent to the

slave during the instruction sequence. See Figure 2-1

for more details.

After the correct READinstruction and address are sent,

the data stored in the memory at the selected address

is shifted out on the SO pin. Data stored in the memory

at the next address can be read sequentially by

continuing to provide clock pulses to the slave. The

internal Address Pointer is automatically incremented

to the next higher address after each byte of data is

shifted out. When the highest address is reached

(1FFh), the address counter rolls over to address 000h

allowing the read cycle to be continued indefinitely. The

read operation is terminated by raising the CS pin

(Figure 2-1).

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the n^thdata byte has been clocked in. If CS is driven

high at any other time, the write operation will not be

completed. Refer to Figure 2-2 and Figure 2-3 for more

detailed illustrations on the byte write sequence and

the page write sequence, respectively. While the write

is in progress, the STATUS register may be read to

check the status of the WPEN, WIP, WEL, BP1 and

BP0 bits (Figure 2-6). Attempting to read a memory

array location will not be possible during a write cycle.

Polling the WIP bit in the STATUS register is recom-

mended in order to determine if a write cycle is in

progress. When the write cycle is completed, the write

enable latch is reset.

2.3

Write Sequence

Prior to any attempt to write data to the 25XX040A, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX040A. After all eight bits of the instruction are

transmitted, CS must be driven high to set the write

enable latch.

DS21827D-page 6

25AA040A/25LC040A

BLOCK DIAGRAM

STATUS

Register

HV Generator

EEPROM

Array

Memory

Control

Logic

X

I/O Control

Logic

Dec

Page Latches

Y Decoder

SI

SO

CS

SCK

Sense Amp.

R/W Control

HOLD

WP

VCC

VSS

TABLE 2-1:

INSTRUCTION SET

Instruction Name

READ

Instruction Format

Description

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Reset the write enable latch (disable write operations)

Set the write enable latch (enable write operations)

Read STATUS register

0000 A₈011

0000 A₈010

0000 x100

0000 x110

0000 x101

0000 x001

WRITE

WRDI

WREN

RDSR

WRSR

Write STATUS register

Note:

A₈is the 9^thaddress bit, which is used to address the entire 512 byte array.

x= don’t care.

FIGURE 2-1:

READ SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9 10 11

17

18

20

19 21 22 23

12

15 16

13 14

SCK

Instruction+Address MSb

A₈

Lower Address Byte

1 A₇A₆A₅A₄

A₂A₁A₀

0

1

A₃

SI

Data Out

High-impedance

7

6

5

4

3

2

1

0

SO

DS21827D-page 7

25AA040A/25LC040A

FIGURE 2-2:

BYTE WRITE SEQUENCE

CS

Twc

12

13

0

1

2

3

4

5

6

7

8

9

10 11

14 15 16 17 18

20 21 22 23

19

SCK

Instruction+Address MSb

A₈

Lower Address Byte

A₃

A₁

Data Byte

0

1

0

A₆A₅

A₂

A₀

7

6

5

4

3

2

1

0

A₄

A₇

SI

High-impedance

SO

FIGURE 2-3:

PAGE WRITE SEQUENCE

CS

12

13

0

1

2

3

4

5

6

7

8

9

10 11

14 15 16 17 18

20 21 22 23

19

SCK

Lower Address Byte

A₃

A₁

Instruction+Address MSb

A₈

Data Byte 1

5

0

1

0

A₆A₅

A₂

A₀

7

6

4

3

2

1

0

A₄

A₇

SI

CS

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCK

SI

Data Byte 2

Data Byte 3

Data Byte n (16 max.)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DS21827D-page 8

25AA040A/25LC040A

The following is a list of conditions under which the

write enable latch will be reset:

2.4

Write Enable (WREN) and Write

Disable (WRDI)

• Power-up

The 25XX040A contains a write enable latch. See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WRENinstruction will set the

latch, and the WRDIwill reset the latch.

• WRDIinstruction successfully executed

• WRSRinstruction successfully executed

• WRITEinstruction successfully executed

• WP pin is brought low

FIGURE 2-4:

WRITE ENABLE SEQUENCE (WREN)

CS

SCK

SI

0

1

2

3

4

5

6

7

0

1

0

High-impedance

SO

FIGURE 2-5:

WRITE DISABLE SEQUENCE (WRDI)

CS

0

1

2

3

4

5

6

7

SCK

0

1

0

1

0

SI

High-impedance

SO

DS21827D-page 9

25AA040A/25LC040A

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 2-4 and Figure 2-5.

2.5

Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. See Figure 2-6 for the

RDSRtiming sequence. The STATUS register may be

read at any time, even during a write cycle. The

STATUS register is formatted as follows:

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSRinstruction, which

is shown in Figure 2-7. These bits are nonvolatile and

are described in more detail in Table 2-3.

TABLE 2-2:

STATUS REGISTER

7

–

X

6

–

X

5

–

X

4

–

X

3

2

1

0

W/R W/R

R

BP1 BP0 WEL WIP

W/R = writable/readable. R = read-only.

The Write-In-Process (WIP) bit indicates whether the

25XX040A is busy with a write operation. When set to

a ‘1’, a write is in progress, when set to a ‘0’, no write

is in progress. This bit is read-only.

FIGURE 2-6:

READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

SI

Instruction

0

1

0

1

Data from STATUS Register

High-impedance

7

6

5

4

3

2

1

0

SO

DS21827D-page 10

25AA040A/25LC040A

TABLE 2-3:

BP1

ARRAY PROTECTION

2.6

Write Status Register Instruction

(WRSR)

Array Addresses

Write-Protected

BP0

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS regis-

ter as shown in Table 2-2. See Figure 2-7 for the WRSR

timing sequence. Four levels of protection for the array

are selectable by writing to the appropriate bits in the

STATUS register. The user has the ability to write-protect

none, one, two or all four of the segments of the array as

shown in Table 2-3.

none

0

1

upper 1/4

(180h-1FFh)

upper 1/2

(100h-1FFh)

1

0

1

all

(000h-1FFh)

FIGURE 2-7:

WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

15

0

SCK

SI

Instruction

Data to STATUS Register

7

6

5

4

3

2

0

1

High-impedance

SO

Note:

An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register

sequence.

DS21827D-page 11

25AA040A/25LC040A

2.7

Data Protection

2.8

Power-On State

The following protection has been implemented to

prevent inadvertent writes to the array:

The 25XX040A powers on in the following state:

• The device is in low-power Standby mode

(CS= 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

• CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

TABLE 2-4:

WRITE-PROTECT FUNCTIONALITY MATRIX

WP

(pin 3)

WEL

(SR bit 1)

Protected Blocks

Unprotected Blocks

STATUS Register

Protected

Writable

Protected

Writable

0 (low)

1 (high)

x

0

1

1 (high)

x = don’t care

DS21827D-page 12

25AA040A/25LC040A

3.4

Serial Input (SI)

3.0

PIN DESCRIPTIONS

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

PDIP, SOIC,

MSOP,

TSSOP,

DFN

3.5

Serial Clock (SCK)

Rotated SOT-

Name

Function

TSSOP

23

The SCK is used to synchronize the communication

between a master and the 25XX040A. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

CS

SO

1

2

3

4

5

6

7

8

3

4

5

6

7

8

1

2

5

4

Chip Select Input

Serial Data Output

Write-Protect Pin

Ground

WP

—

2

3.6

Hold (HOLD)

VSS

SI

3

Serial Data Input

Serial Clock Input

Hold Input

The HOLD pin is used to suspend transmission to the

25XX040A while in the middle of a serial sequence

without having to retransmit the entire sequence again.

It must be held high any time this function is not being

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25XX040A must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paused and transitions on these pins will be ignored. To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

SCK

HOLD

VCC

1

—

6

Supply Voltage

3.1

Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

3.2

Serial Output (SO)

The SO pin is used to transfer data out of the

25XX040A. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

3.3

Write-Protect (WP)

The WP pin is a hardware write-protect input pin.

When it is low, all writes to the array or STATUS

registers are disabled, but any other operations

function normally. When WP is high, all functions,

including nonvolatile writes, operate normally. At any

time, when WP is low, the write enable reset latch will

be reset and programming will be inhibited. However,

if a write cycle is already in progress, WP going low will

not change or disable the write cycle. See Table 2-4 for

the Write-Protect Functionality Matrix.

DS21827D-page 13

25AA040A/25LC040A

4.0

4.1

PACKAGING INFORMATION

Package Marking Information

Example:

8-Lead PDIP

25AA040A

I/P 1L7

XXXXXXXX

T/XXXNNN

e

3

0627

YYWW

Example:

8-Lead SOIC

25AA04AI

XXXXXXXT

SN

0627

1L7

XXXXYYWW

e

3

NNN

Example:

8-Lead TSSOP

5A4A

I627

1L7

XXXX

TYWW

NNN

8-Lead MSOP (150 mil)

Example:

5L4AI

6271L7

XXXXXT

YWWNNN

1st Line Marking Codes

Part Number

DFN

I Temp.

TSSOP

Standard Rotated

MSOP

SOT-23

I Temp. E Temp.

E Temp.

—

32NN

5A4A

5L4A

A4AX

L4AX

5A4AT

421

424

25AA040A

25LC040A

5L4AT 35NN

36NN

425

Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21827D-page 14

25AA040A/25LC040A

Package Marking Information (continued)

8-Lead 2X3 DFN

Example:

XXX

YWW

NN

421

627

L7

6-Lead SOT-23

Example:

32L7

XXNN

DS21827D-page 15

25AA040A/25LC040A

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS21827D-page 16

25AA040A/25LC040A

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff

A2

A1

E

1.25

0.10

–

§

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

4.90 BSC

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057B

DS21827D-page 17

25AA040A/25LC040A

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

b

e

c

φ

A

A2

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.20

1.05

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.80

0.05

1.00

–

Overall Width

6.40 BSC

Molded Package Width

Molded Package Length

Foot Length

E1

D

4.30

2.90

0.45

4.40

4.50

3.10

0.75

3.00

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

c

0.09

0.20

0.30

Lead Width

b

0.19

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-086B

DS21827D-page 18

25AA040A/25LC040A

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

b

1

e

c

φ

A2

A

L

L1

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.10

0.95

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.75

0.00

0.85

–

4.90 BSC

3.00 BSC

0.60

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

L

0.40

0.80

Footprint

L1

φ

0.95 REF

–

Foot Angle

0°

8°

Lead Thickness

c

0.08

–

0.23

0.40

Lead Width

b

0.22

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-111B

DS21827D-page 19

25AA040A/25LC040A

8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

b

N

L

K

E2

E

EXPOSED PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

NOTE 2

A3

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

0.50 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

D

0.02

Contact Thickness

Overall Length

Overall Width

0.20 REF

2.00 BSC

3.00 BSC

–

E

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

Contact-to-Exposed Pad

D2

E2

b

1.30

1.50

0.18

0.30

0.20

1.75

1.90

0.30

0.50

–

0.25

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-123B

DS21827D-page 20

25AA040A/25LC040A

6-Lead Plastic Small Outline Transistor (CH) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

b

4

N

E

E1

PIN 1 ID BY

LASER MARK

1

2

3

e

e1

D

c

A

φ

A2

L

A1

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

6

0.95 BSC

Outside Lead Pitch

Overall Height

e1

A

1.90 BSC

0.90

0.89

0.00

2.20

1.30

2.70

0.10

0.35

0°

–

1.45

1.30

0.15

3.20

1.80

3.10

0.60

0.80

30°

Molded Package Thickness

Standoff

A2

A1

E

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

L

Footprint

L1

φ

Foot Angle

Lead Thickness

Lead Width

c

0.08

0.20

0.26

0.51

b

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-028B

DS21827D-page 21

25AA040A/25LC040A

APPENDIX A: REVISION HISTORY

Revision B

Corrections to Section 1.0, Electrical Characteristics.

Revision C

Added Packages SOT-23, DFN and X-rotated TSSOP;

Revised AC Char., Params. 9, 10; Revised Package

Legend.

Revision D

Removed Preliminary status; Replaced package

drawings (Rev. AP); Revise Table 1-1, Param. D004,

D007, D008; Revise Table 1-2, Param. 7, 8, 9 ,10.

DS21827D-page 22

25AA040A/25LC040A

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS21827D-page 23

25AA040A/25LC040A

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

25AA040A/25LC040A

DS21827D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21827D-page 24

25AA040A/25LC040A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

Tape & Reel

Temperature Package

a)

25AA040A-I/MS = 4k-bit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., MSOP

package

b)

25AA040AT-I/SN = 4k-bit, 16-byte page, 1.8V

Serial EEPROM, Industrial temp., Tape & Reel,

SOIC package

Device:

25AA040A

25LC040A

4k-bit, 1.8V, 16 Byte Page, SPI Serial EEPROM

4k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM

c)

d)

e)

f)

25LC040AT-I/SN = 4k-bit, 16-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

SOIC package

25AA040AX 4k-bit, 1.8V, 16 Byte Page, SPI Serial EEPROM,

in alternate pinout (ST only)

25LC040AX 4k-bit, 2.5V, 16 Byte Page, SPI EEPROM, in

alternate pinout (ST only)

25LC040AT-I/ST = 4k-bit, 16-byte page, 2.5V

Serial EEPROM, Industrial temp., Tape & Reel,

TSSOP package

Tape & Reel:

Blank

T

=

Standard packaging

Tape & Reel

25LC040AT-E/SN = 4k-bit, 16-byte page, 2.5V

Serial EEPROM, Extended temp., Tape & Reel,

SOIC package

Temperature

Range:

I

E

=

-40°C to+85°C

-40°C to+125°C

25LC040AX-E/ST = 4k-bit, 16-byte page, 2.5V

Serial EEPROM, Extended temp., rotated

pinout, TSSOP package

Package:

MS

P

SN

ST

MC

OT

=

Plastic MSOP (Micro Small Outline), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mml body), 8-lead

TSSOP, 8-lead

2x3 DFN, 8-lead

SOT-23, 6-lead (Tape and Reel only)

DS21827D-page 25

25AA040A/25LC040A

NOTES:

DS21827D-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21827D-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21827D-page 28


型号：	25AA040AT-I/MS
厂家：	MICROCHIP
描述：	4K SPI Bus Serial EEPROM 4K SPI总线串行EEPROM 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件：	总28页 (文件大小：554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

25AA040AT-I/MS [MICROCHIP]

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