25AA1024-I/S16K_技术文档

25AA1024

1 Mbit SPI Bus Serial EEPROM

Device Selection Table

Part Number

25AA1024

VCC Range

Page Size

Temp. Ranges

Packages

1.8-5.5V

256 Byte

I

P, SM, MF

Features

Description

• 20 MHz Maximum Clock Speed

• Byte and Page-level Write Operations:

- 256 byte page

- 6 ms maximum write cycle time

- No page or sector erase required

• Low-Power CMOS Technology:

- Maximum Write current: 7 mA at 5.5V

- Maximum Read current: 10 mA at 5.5V,

20 MHz

- Standby current: 1 µA at 2.5V, 85°C

(Deep Power-down)

The Microchip Technology Inc. 25AA1024 is a

1024 Kbit serial EEPROM memory with byte-level and

page-level serial EEPROM functions. It also features

Page, Sector and Chip erase functions typically

associated with Flash-based products. These functions

are not required for byte or page write operations. The

memory is accessed via a simple Serial Peripheral

Interface (SPI) compatible serial bus. The bus signals

required are a clock input (SCK) plus separate data in

(SI) and data out (SO) lines. Access to the device is

controlled by a Chip Select (CS) input.

• Electronic Signature for Device ID

• Self-Timed Erase and Write Cycles:

- Page Erase (6 ms maximum)

- Sector Erase (10 ms maximum)

- Chip Erase (10 ms maximum)

• Sector Write Protection (32K byte/sector):

- Protect none, 1/4, 1/2 or all of array

• Built-in Write Protection:

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused,

transitions on its inputs will be ignored, with the

exception of Chip Select, allowing the host to service

higher priority interrupts.

The 25AA1024 is available in standard packages

including 8-lead PDIP and SOIJ, and advanced 8-lead

DFN package. All devices are RoHS compliant.

- Power-on/off data protection circuitry

- Write enable latch

Package Types (not to scale)

- Write-protect pin

• High Reliability:

- Endurance: 1M erase/write cycles

- Data Retention: >200 years

- ESD Protection: 4000V

• Temperature Ranges Supported:

- Industrial (I):-40°C to +85°C

• RoHS Compliant

DFN

PDIP/SOIJ

(MF)

(P, SM)

1

2

3

4

CS

SO

8

7

6

5

VCC

HOLD

SCK

SI

CS

SO

VCC

1

2

3

4

8

7

6

5

HOLD

WP

VSS

WP

VSS

SCK

SI

Pin Function Table

Name

Function

CS

Chip Select Input

SO

WP

VSS

SI

Serial Data Output

Write-Protect

Ground

Serial Data Input

Serial Clock Input

Hold Input

SCK

HOLD

VCC

Supply Voltage

 2007-2015 Microchip Technology Inc.

DS20001836J-page 1

25AA1024

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Industrial (I)*:

Industrial (I):

* Limited industrial temperature range.

TA = 0°C to +85°C

TA = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

DC CHARACTERISTICS

Param.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

No.

D001

VIH1

High-level Input

Voltage

0.7 VCC

VCC +1

V

D002

D003

D004

D005

D006

VIL1

VIL2

VOL

VOH

Low-level Input

Voltage

-0.3

0.3 VCC

0.2 VCC

0.4

V

VCC≥ 2.7V

VCC < 2.7V

Low-level Output

Voltage

—

IOL = 2.1 mA

—

0.2

IOL = 1.0 mA, VCC < 2.5V

IOH = -400 µA

High-level Output

Voltage

VCC -0.2

—

D007

D008

D009

ILI

ILO

Input Leakage

Current

CS = VCC, VIN = VSS or VCC

CS = VCC, VOUT = VSS or VCC

—

±1

7

µA

pF

Output Leakage

Current

CINT

Internal Capacitance

(all inputs and

outputs)

TA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

D010

ICCREAD

—

10

5

mA

VCC = 5.5V; FCLK = 20.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 10.0 MHz;

SO = Open

Operating Current

Standby Current

D011

ICCWRITE

ICCS

—

7

5

mA

A

VCC = 5.5V

VCC = 2.5V

D012

D013

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, 85°C

12

ICCSPD Deep Power-down

Current

CS = VCC = 2.5V, Inputs tied to VCC or

VSS, 85°C

—

1

µA

Note:

This parameter is periodically sampled and not 100% tested.

DS20001836J-page 2

 2007-2015 Microchip Technology Inc.

25AA1024

TABLE 1-2:

AC CHARACTERISTICS

Industrial (I)*:

Industrial (I):

TA = 0°C to +85°C

TA = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

AC CHARACTERISTICS

*Limited industrial temperature range.

Param.

Sym.

No.

Characteristic

Min.

Max.

Units

Conditions

1

2

3

FCLK

TCSS

TCSH

Clock Frequency

CS Setup Time

CS Hold Time

—

20

10

2

MHz 4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

MHz

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

25

50

—

ns

2.0 ≤ VCC < 2.5

250

1.8 ≤ VCC < 2.0, 0°C to +85°C

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

50

—

ns

100

500

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

(Note 3)

4

5

TCSD

TSU

CS Disable Time

Data Setup Time

50

5

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

10

50

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

6

THD

Data Hold Time

10

20

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

100

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

7

8

9

TR

TF

CLK Rise Time

CLK Fall Time

Clock High Time

—

20

—

ns

(Note 1)

THI

25

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

50

ns

250

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

10

TLO

Clock Low Time

25

50

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

250

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

11

12

13

TCLD

TCLE

TV

Clock Delay Time

Clock Enable Time

50

—

ns

Output Valid from Clock

Low

25

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

50

250

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance

estimates in a specific application, please consult the Total Endurance™ Model which can be obtained

from Microchip’s web site at www.microchip.com.

3: Includes THI time.

 2007-2015 Microchip Technology Inc.

DS20001836J-page 3

25AA1024

TABLE 1-2:

AC CHARACTERISTICS (CONTINUED)

Industrial (I)*:

Industrial (I):

TA = 0°C to +85°C

TA = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

AC CHARACTERISTICS

*Limited industrial temperature range.

Param.

Sym.

No.

Characteristic

Min.

Max.

Units

Conditions

14

15

THO

TDIS

Output Hold Time

0

—

25

ns

(Note 1)

Output Disable Time

—

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

50

2.0 ≤ VCC < 2.5

250

1.8 ≤ VCC < 2.0, 0°C to +85°C

(Note 1)

16

17

18

THS

THH

THZ

HOLD Setup Time

HOLD Hold Time

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

10

20

—

ns

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

100

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

10

20

—

ns

2.0 ≤ VCC < 2.5

1.8 ≤ VCC < 2.0, 0°C to +85°C

100

HOLD Low to Output

High Z

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

15

30

—

ns

2.0 ≤ VCC < 2.5

150

1.8 ≤ VCC < 2.0, 0°C to +85°C

(Note 1)

19

THV

HOLD High to Output

Valid

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

15

30

—

ns

2.0 ≤ VCC < 2.5

150

1.8 ≤ VCC < 2.0, 0°C to +85°C

20

21

TREL

TPD

CS High to Standby mode

VCC = 1.8V to 5.5V

—

100

µs

CS High to Deep

Power-down

22

23

24

TCE

TSE

Chip Erase Cycle Time

Sector Erase Cycle Time

Internal Write Cycle Time

—

10

6

ms

VCC = 1.8V to 5.5V

TWC

Byte or Page mode and Page

Erase

25

—

Endurance

1M

—

E/W Page mode, 25°C, 5.5V (Note 2)

cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance

estimates in a specific application, please consult the Total Endurance™ Model which can be obtained

from Microchip’s web site at www.microchip.com.

3: Includes THI time.

DS20001836J-page 4

 2007-2015 Microchip Technology Inc.

25AA1024

TABLE 1-3:

AC Waveform

VLO = 0.2V

AC TEST CONDITIONS

—

VHI = VCC - 0.2V

(Note 1)

(Note 2)

—

VHI = 4.0V

CL = 30 pF

Timing Measurement Reference Level

Input

0.5 VCC

Output

Note 1: For VCC  4.0V

2: For VCC > 4.0V

FIGURE 1-1: HOLD TIMING

CS

17

18

17

16

SCK

19

High-Impedance

Don’t Care

n

SO

n + 2

n + 1

n

n - 1

5

n

n + 1

n

n - 1

SI

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

4

CS

12

11

2

7

3

Mode 1,1

8

Mode 0,0

SCK

5

6

SI

MSB in

LSB in

High-Impedance

SO

 2007-2015 Microchip Technology Inc.

DS20001836J-page 5

25AA1024

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

3

9

10

Mode 1,1

Mode 0,0

SCK

13

15

14

MSB out

LSB out

SO

SI

Don’t Care

DS20001836J-page 6

 2007-2015 Microchip Technology Inc.

25AA1024

2.0

2.1

FUNCTIONAL DESCRIPTION

Principles of Operation

BLOCK DIAGRAM

STATUS

Register

HV Generator

The 25AA1024 is a 131,072 byte Serial EEPROM

designed to interface directly with the Serial Peripheral

Interface (SPI) port of many of today’s popular

microcontroller families, including Microchip’s PIC^®

microcontrollers. It may also interface with

microcontrollers that do not have a built-in SPI port by

using discrete I/O lines programmed properly in

firmware to match the SPI protocol.

EEPROM

Array

Memory

Control

Logic

X

I/O Control

Logic

Dec

Page Latches

The 25AA1024 contains an 8-bit instruction register.

The device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

SI

SO

Y Decoder

CS

SCK

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses and data are transferred MSB first, LSB last.

Sense Amp.

R/W Control

HOLD

WP

VCC

VSS

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25AA1024 in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

TABLE 2-1:

INSTRUCTION SET

Instruction Name

Instruction Format

Description

READ

WRITE

WREN

WRDI

RDSR

WRSR

PE

0000 0011

0000 0010

0000 0110

0000 0100

0000 0101

0000 0001

0100 0010

1101 1000

1100 0111

1010 1011

1011 1001

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Set the write enable latch (enable write operations)

Reset the write enable latch (disable write operations)

Read STATUS register

Write STATUS register

Page Erase – erase one page in memory array

Sector Erase – erase one sector in memory array

Chip Erase – erase all sectors in memory array

Release from Deep Power-down and Read Electronic Signature

Deep Power-Down mode

SE

CE

RDID

DPD

 2007-2015 Microchip Technology Inc.

DS20001836J-page 7

25AA1024

The data stored in the memory at the next address can

be read sequentially by continuing to provide clock

pulses. The internal Address Pointer is automatically

incremented to the next higher address after each byte

of data is shifted out. When the highest address is

reached (1FFFFh), the address counter rolls over to

address, 00000h, allowing the read cycle to be

continued indefinitely. The read operation is terminated

by raising the CS pin (Figure 2-1).

Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25AA1024

followed by the 24-bit address, with seven MSBs of the

address being “don’t care” bits. After the correct READ

instruction and address are sent, the data stored in the

memory at the selected address is shifted out on the

SO pin.

FIGURE 2-1:

READ SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

Instruction

24-bit Address

23 22 21 20

0

1

2

1

0

SI

Data Out

High-Impedance

7

6

5

4

3

2

1

0

SO

DS20001836J-page 8

 2007-2015 Microchip Technology Inc.

25AA1024

2.2

Write Sequence

Note:

Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’), and end at addresses that

are integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

Prior to any attempt to write data to the 25AA1024, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25AA1024. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set.

A write sequence includes an automatic, self-timed

erase cycle. It is not required to erase any portion of the

memory prior to issuing a Write command.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITE

instruction, followed by the 24-bit address, with seven

MSBs of the address being “don’t care” bits, and then

the data to be written. Up to 256 bytes of data can be

sent to the device before a write cycle is necessary.

The only restriction is that all of the bytes must reside

in the same page.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the n^thdata byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the STATUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

Note:

When doing a write of less than 256 bytes

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle, for this reason

endurance is specified per page.

FIGURE 2-2:

BYTE WRITE SEQUENCE

CS

TWC

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

Instruction

24-bit Address

23 22 21 20

Data Byte

0

1

0

2

1

0

7

6

5

4

3

2

1

0

High-Impedance

SO

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DS20001836J-page 9

25AA1024

FIGURE 2-3:

PAGE WRITE SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9

10 11

29 30 31 32 33 34 35 36 37 38 39

Data Byte 1

SCK

Instruction

24-bit Address

0

1

0 23 22 21 20

2

1

0

7

6

5

4

3

2

1

0

SI

CS

40 41 42 43 44 45 46 47

Data Byte 2

49 50 51 52 53 54 55

Data Byte 3

48

7

SCK

SI

Data Byte n (256 max.)

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DS20001836J-page 10

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25AA1024

The following is a list of conditions under which the

write enable latch will be reset:

2.3

Write Enable (WREN) and Write

Disable (WRDI)

• Power-up

The 25AA1024 contains a write enable latch. See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WRENinstruction will set the

latch, and the WRDIwill reset the latch.

• WRDIinstruction successfully executed

• WRSRinstruction successfully executed

• WRITEinstruction successfully executed

• PEinstruction successfully executed

• SEinstruction successfully executed

• CEinstruction successfully executed

FIGURE 2-4:

WRITE ENABLE SEQUENCE (WREN)

CS

0

1

2

3

4

5

6

7

SCK

SI

0

1

0

High-Impedance

SO

FIGURE 2-5:

WRITE DISABLE SEQUENCE (WRDI)

CS

0

1

2

3

4

5

6

7

SCK

0

1

0

1

0

SI

High-Impedance

SO

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DS20001836J-page 11

25AA1024

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 2-4 and Figure 2-5.

2.4

Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. The STATUS register

may be read at any time, even during a write cycle. The

STATUS register is formatted as follows:

TABLE 2-2:

STATUS REGISTER

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSRinstruction. These

bits are nonvolatile and are shown in Table 2-3.

7

6

–

X

5

–

X

4

–

X

3

2

1

0

W/R

W/R W/R

R

WPEN

BP1 BP0 WEL WIP

See Figure 2-6 for the RDSRtiming sequence.

W/R = writable/readable. R = read-only.

The Write-In-Process (WIP) bit indicates whether the

25AA1024 is busy with a write operation. When set to

a ‘1’, a write is in progress, when set to a ‘0’, no write

is in progress. This bit is read-only.

FIGURE 2-6:

READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

SI

Instruction

0

1

0

1

Data from STATUS register

High-Impedance

7

6

5

4

3

2

1

0

SO

DS20001836J-page 12

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25AA1024

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the

2.5

Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS

register, as shown in Table 2-2. The user is able to

select one of four levels of protection for the array by

writing to the appropriate bits in the STATUS register.

The array is divided up into four segments. The user

has the ability to write-protect none, one, two, or all four

of the segments of the array. The partitioning is

controlled, as shown in Table 2-3.

programmable

hardware

write-protect

feature.

Hardware write protection is enabled when the WP pin

is low and the WPEN bit is high. Hardware write

protection is disabled when either the WP pin is high or

the WPEN bit is low. When the chip is hardware

write-protected, only writes to nonvolatile bits in the

STATUS register are disabled. See Table 2-4 for a

matrix of functionality on the WPEN bit.

See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3:

ARRAY PROTECTION

Array Addresses

Write-Protected

Array Addresses

Unprotected

BP1

BP0

0

none

All (Sectors 0, 1, 2 & 3)

(00000h-1FFFFh)

0

1

Upper 1/4 (Sector 3)

(18000h-1FFFFh)

Lower 3/4 (Sectors 0, 1 & 2)

(00000h-17FFFh)

0

1

Upper 1/2 (Sectors 2 & 3)

(10000h-1FFFFh)

Lower 1/2 (Sectors 0 & 1)

(00000h-0FFFFh)

All (Sectors 0, 1, 2 & 3)

(00000h-1FFFFh)

none

FIGURE 2-7:

WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

15

0

SCK

SI

Instruction

Data to STATUS register

7

6

5

4

3

2

0

1

High-Impedance

SO

 2007-2015 Microchip Technology Inc.

DS20001836J-page 13

25AA1024

2.6

Data Protection

2.7

Power-On State

The following protection has been implemented to

prevent inadvertent writes to the array:

The 25AA1024 powers on in the following state:

• The device is in low-power Standby mode

(CS= 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

• CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

TABLE 2-4:

WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1)

WPEN

(SR bit 7)

WP

(pin 3)

Protected Blocks

Unprotected Blocks

STATUS Register

0

x

0

1

x

Protected

Writable

Protected

Writable

Protected

Writable

1

x

1

0 (low)

1 (high)

1

x = don’t care

DS20001836J-page 14

 2007-2015 Microchip Technology Inc.

25AA1024

2.8

PAGE ERASE

The Page Erase function will erase all bits (FFh) inside

the given page. A Write Enable (WREN) instruction

must be given prior to attempting a Page Erase. This

is done by setting CS low and then clocking out the

proper instruction into the 25AA1024. After all eight

bits of the instruction are transmitted, the CS must be

brought high to set the write enable latch.

CS must then be driven high after the last bit if the

address or the Page Erase will not execute. Once the

CS is driven high, the self-timed Page Erase cycle is

started. The WIP bit in the STATUS register can be

read to determine when the Page Erase cycle is

complete.

If a Page Erase function is given to an address that

has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The Page Erase function is entered by driving CS low,

followed by the instruction code (Figure 2-8), and

three address bytes. Any address inside the page to

be erased is a valid address.

FIGURE 2-8:

PAGE ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31

Instruction

24-bit Address

23 22 21 20

0

1

0

1

0

2

1

0

High-Impedance

SO

 2007-2015 Microchip Technology Inc.

DS20001836J-page 15

25AA1024

2.9

SECTOR ERASE

The Sector Erase function will erase all bits (FFh)

inside the given sector. A Write Enable (WREN)

instruction must be given prior to executing a Sector

Erase. This is done by setting CS low and then

clocking out the proper instruction into the 25AA1024.

After all eight bits of the instruction are transmitted, the

CS must be brought high to set the write enable latch.

CS must then be driven high after the last bit if the

address or the Sector Erase will not execute. Once the

CS is driven high, the self-timed Sector Erase cycle is

started. The WIP bit in the STATUS register can be

read to determine when the Sector Erase cycle is

complete.

If a SECTOR ERASEinstruction is given to an address

that has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The Sector Erase function is entered by driving CS

low, followed by the instruction code (Figure 2-9), and

three address bytes. Any address inside the sector to

be erased is a valid address.

See Table 2-3 for Sector Addressing.

FIGURE 2-9:

SECTOR ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31

Instruction

24-bit Address

23 22 21 20

1

0

1

0

2

1

0

High-Impedance

SO

DS20001836J-page 16

 2007-2015 Microchip Technology Inc.

25AA1024

2.10 CHIP ERASE

The Chip Erase function will erase all bits (FFh) in the

array. A Write Enable (WREN) instruction must be given

prior to executing a Chip Erase. This is done by setting

CS low and then clocking out the proper instruction

into the 25AA1024. After all eight bits of the instruction

are transmitted, the CS must be brought high to set

the write enable latch.

The CS pin must be driven high after the eighth bit of

the instruction code has been given or the Chip Erase

function will not be executed. Once the CS pin is

driven high, the self-timed Chip Erase function begins.

While the device is executing the Chip Erase function

the WIP bit in the STATUS register can be read to

determine when the Chip Erase function is complete.

The Chip Erase function is entered by driving the CS

low, followed by the instruction code (Figure 2-10)

onto the SI line.

The Chip Erase function is ignored if either of the

Block Protect bits (BP0, BP1) are not 0, meaning ¼,

½, or all of the array is protected.

FIGURE 2-10:

CHIP ERASE SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

SI

High-Impedance

SO

 2007-2015 Microchip Technology Inc.

DS20001836J-page 17

25AA1024

2.11 DEEP POWER-DOWN MODE

Deep Power-Down mode of the 25AA1024 is its

lowest power consumption state. The device will not

respond to any of the Read or Write commands while

in Deep Power-Down mode, and therefore it can be

used as an additional software write protection feature.

All instructions given during Deep Power-Down mode

are ignored except the Read Electronic Signature

Command (RDID). The RDID command will release

the device from Deep Power-down and outputs the

electronic signature on the SO pin, and then returns

the device to Standby mode after delay (TREL).

The Deep Power-Down mode is entered by driving CS

low, followed by the instruction code (Figure 2-11) onto

the SI line, followed by driving CS high.

Deep Power-Down mode automatically releases at

device power-down. Once power is restored to the

device, it will power-up in the Standby mode.

If the CS pin is not driven high after the eighth bit of the

instruction code has been given, the device will not

execute Deep Power-down. Once the CS line is driven

high, there is a delay (TDP) before the current settles

to its lowest consumption.

FIGURE 2-11:

DEEP POWER-DOWN SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

0

1

SI

High-Impedance

SO

DS20001836J-page 18

 2007-2015 Microchip Technology Inc.

25AA1024

Release from Deep Power-Down mode and Read

Electronic Signature is entered by driving CS low,

followed by the RDID instruction code (Figure 2-12)

and then a dummy address of 24 bits (A23-A0). After

the last bit of the dummy address is clocked in, the

8-bit electronic signature is clocked out on the SO

pin.

2.12 RELEASE FROM DEEP

POWER-DOWN AND READ

ELECTRONIC SIGNATURE

Once the device has entered Deep Power-Down

mode, all instructions are ignored except the release

from Deep Power-down and Read Electronic

Signature command. This command can also be used

when the device is not in Deep Power-down, to read

the electronic signature out on the SO pin unless

another command is being executed such as Erase,

Program or Write STATUS register.

After the signature has been read out at least once,

the sequence can be terminated by driving CS high.

After a delay of TREL, the device will then return to

Standby mode and will wait to be selected so it can be

given new instructions. If additional clock cycles are

sent after the electronic signature has been read once,

it will continue to output the signature on the SO line

until the sequence is terminated.

FIGURE 2-12:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

TREL

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

Instruction

24-bit Address

23 22 21 20

1

0

1

0

1

0

1

2

1

0

Electronic Signature Out

High-Impedance

7

6

5

4

3

2

1

0

SO

0

1

0

1

0

1

Manufacturers ID 0x29

Driving CS high after the 8-bit RDID command, but before the electronic signature has been transmitted, will still

ensure the device will be taken out of Deep Power-Down mode, as shown in Figure 2-13.

FIGURE 2-13:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

TREL

0

1

2

3

4

5

6

7

SCK

SI

Instruction

1

0

1

0

1

0

1

High-Impedance

SO

 2007-2015 Microchip Technology Inc.

DS20001836J-page 19

25AA1024

The WP pin function is blocked when the WPEN bit in

the STATUS register is low. This allows the user to

install the 25AA1024 in a system with WP pin grounded

and still be able to write to the STATUS register. The

WP pin functions will be enabled when the WPEN bit is

set high.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

Name

PIN FUNCTION TABLE

Pin Number

Function

3.4

Serial Input (SI)

Chip Select Input

CS

SO

1

2

3

4

5

6

7

8

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

Serial Data Output

Write-Protect Pin

Ground

WP

VSS

SI

3.5

Serial Clock (SCK)

Serial Data Input

Serial Clock Input

Hold Input

The SCK is used to synchronize the communication

between a master and the 25AA1024. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

SCK

HOLD

VCC

Supply Voltage

3.1

Chip Select (CS)

3.6

Hold (HOLD)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After

power-up, a low level on CS is required prior to any

sequence being initiated.

The HOLD pin is used to suspend transmission to the

25AA1024 while in the middle of a serial sequence

without having to retransmit the entire sequence again.

It must be held high any time this function is not being

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK

high-to-low transition. The 25AA1024 must remain

selected during this sequence. The SI, SCK and SO

pins are in a high-impedance state during the time the

device is paused and transitions on these pins will be

ignored. To resume serial communication, HOLD must

be brought high while the SCK pin is low, otherwise

serial communication will not resume. Pulling the

HOLD line low at any time will tri-state the SO line.

3.2

Serial Output (SO)

The SO pin is used to transfer data out of the

25AA1024. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

3.3

Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the

STATUS register to prohibit writes to the nonvolatile

bits in the STATUS register. When WP is low and

WPEN is high, writing to the nonvolatile bits in the

STATUS register is disabled. All other operations

function normally. When WP is high, all functions,

including writes to the nonvolatile bits in the STATUS

register, operate normally. If the WPEN bit is set, WP

low during a STATUS register write sequence will

disable writing to the STATUS register. If an internal

write cycle has already begun, WP going low will have

no effect on the write.

DS20001836J-page 20

 2007-2015 Microchip Technology Inc.

25AA1024

4.0

4.1

PACKAGING INFORMATION

Package Marking Information

8-Lead DFN

Example:

XXXXXXX

T/XXXXX

YYWW

5AA1024

e

3

I/MF

1509

NNN

1L7

8-Lead PDIP

Example:

XXXXXXXX

T/XXXNNN

25AA1024

I/P

1L7

e

3

YYWW

1509

8-Lead SOIJ

Example:

XXXXXXXX

T/XXXXXX

YYWWNNN

25AA1024

I/SM

e

3

15091L7

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

JEDEC^®designator for Matte Tin (Sn)

e

3

Note: For very small packages with no room for the JEDEC^®designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2007-2015 Microchip Technology Inc.

DS20001836J-page 21

25AA1024

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DS20001836J-page 22

 2007-2015 Microchip Technology Inc.

25AA1024

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ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢏꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢏꢅꢐꢈꢉꢅꢓꢔꢕ,ꢅ-ꢀꢖꢁ.ꢕꢁ

/ꢔ01 /ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢗꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢘ,21 ꢘꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢐ"ꢉꢐꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

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 2007-2015 Microchip Technology Inc.

DS20001836J-page 23

25AA1024

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DS20001836J-page 24

 2007-2015 Microchip Technology Inc.

25AA1024

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

N

B

E1

NOTE 1

1

2

TOP VIEW

E

A2

A

C

PLANE

L

c

A1

e

eB

8X b1

8X b

.010

C

SIDE VIEW

END VIEW

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

 2007-2015 Microchip Technology Inc.

DS20001836J-page 25

25AA1024

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

DATUM A

b

e

2

e

2

e

Units

Dimension Limits

INCHES

NOM

8

.100 BSC

-

MIN

MAX

Number of Pins

Pitch

N

e

A

Top to Seating Plane

-

.210

.195

-

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

A2

A1

E

E1

D

L

c

b1

b

eB

.115

.015

.290

.240

.348

.115

.008

.040

.014

-

.130

-

.310

.250

.365

.130

.010

.060

.018

-

.325

.280

.400

.150

.015

.070

.022

.430

Lower Lead Width

Overall Row Spacing

§

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

DS20001836J-page 26

 2007-2015 Microchip Technology Inc.

25AA1024

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2007-2015 Microchip Technology Inc.

DS20001836J-page 27

25AA1024

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20001836J-page 28

 2007-2015 Microchip Technology Inc.

25AA1024

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2007-2015 Microchip Technology Inc.

DS20001836J-page 29

25AA1024

APPENDIX A: REVISION HISTORY

Revision C (02/2007)

Revised Features Section (Self-timed Erase and Write

Cycles); Revised Table 1-1 (parameters D012 and

D13); Table 1-2 (parameters 20-24); Revised Package

Marking Information; Replaced Package Drawings;

Revised Product ID System Section (SM package);

Changed PICmicro to PIC.

Revision D (07/2007)

Revised Features; Revised Tables 1-1 and 1-2 (added

Industrial temp. and revised parameters 22-23);

Replaced Package Drawings (Rev. AP); Revised

Product ID System; Changed Flash to EEPROM.

Revision E (10/2007)

Removed 25LC1024 part number; New data sheet

created for 25LC1024 (DS22064); Revised Tables;

Updates throughout.

Revision F (05/2008)

Modified parameter D006 in Table 1-1; Revised

Package Marking Information; Replaced Package

Drawings.

Revision G (01/2010)

Added 8-Lead (MF) DFN-S Land Pattern; Replaced

8-Lead (SM) SOIJ Land Pattern.

Revision H (05/2010)

Revised Table 1-2, Param. No 25 Conditions; Revised

Section 2.2; Added note.

Revision J (04/2015)

Corrected Features section; Revised Table 1-2,

updated ‘Conditions’; Revised Figure 2-12, added

parameter TREL; Revised Section 2-12, clarified

condition for existing Deep Power-Down mode.

DS20001836J-page 30

 2007-2015 Microchip Technology Inc.

25AA1024

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our web site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://www.microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

 2007-2015 Microchip Technology Inc.

DS20001836J-page 31

25AA1024

NOTES:

DS20001836J-page 32

 2007-2015 Microchip Technology Inc.

25AA1024

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

X

/XX

[X]

PART NO.

Device

Examples:

a)

25AA1024T-I/SM = 1 Mbit, 1.8V Serial

Temperature Package

Range

Tape and Reel

Option

EEPROM, Industrial temp., Tape & Reel, SOIJ

package

b)

25AA1024T-I/MF = 1 Mbit, 1.8V Serial

EEPROM, Industrial temp., Tape & Reel, DFN

package

Device:

25AA1024

1 Mbit, 1.8V, 256-Byte Page SPI Serial EEPROM

Tape

Option:

&

Reel Blank

=

Standard packaging (tube)

Tape & Reel

T

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Temperature

Range:

I

=

-40C to+85C

Package:

MF

P

SM

=

Micro Lead Frame (6 x 5 mm body), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIJ (5.28 mm), 8-lead

 2007-2015 Microchip Technology Inc.

DS20001836J-page 33

25AA1024

NOTES:

DS20001836J-page 34

 2007-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,

MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-63277-265-7

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2007-2015 Microchip Technology Inc.

DS20001836J-page 35

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Dusseldorf

Tel: 49-2129-3766400

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Austin, TX

Tel: 512-257-3370

Germany - Pforzheim

Tel: 49-7231-424750

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Tel: 86-769-8702-9880

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Cleveland

Korea - Seoul

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Poland - Warsaw

Tel: 48-22-3325737

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Sweden - Stockholm

Tel: 46-8-5090-4654

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Detroit

Novi, MI

Tel: 248-848-4000

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Houston, TX

Tel: 281-894-5983

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Taiwan - Kaohsiung

Tel: 886-7-213-7828

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

New York, NY

Tel: 631-435-6000

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

San Jose, CA

Tel: 408-735-9110

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

01/27/15

DS20001836J-page 36

 2007-2015 Microchip Technology Inc.


型号：	25AA1024-I/S16K
厂家：	MICROCHIP
描述：	1024k, 128K X 8 , 1.8V SER EE, DIE in WAFFLE PK, -40C to +85C, Die-Waffle, WPAC
文件：	总36页 (文件大小：485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

25AA1024-I/S16K [MICROCHIP]

相关型号：

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25AA1024-I/SM16KVAO

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25AA1024I/MF

25AA1024I/P

25AA1024I/SM

25AA1024T-E/MF

25AA1024T-E/P

25AA1024T-E/SM

25AA1024T-I/MF

25AA1024T-I/MFG

25AA1024T-I/P