25AA128-I/WF16K [MICROCHIP]
128K, 16K X 8, 1.8V SER EE, WAFER ON FRAME, -40C to +85C, Wafer-Frame, WFRAME;
| 型号： | 25AA128-I/WF16K |
| 厂家： | 
MICROCHIP |
| 描述： | 128K, 16K X 8, 1.8V SER EE, WAFER ON FRAME, -40C to +85C, Wafer-Frame, WFRAME 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总32页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25AA128/25LC128
128K SPI Bus Serial EEPROM
Device Selection Table
Part Number
25AA128
VCC Range
Page Size
Temp. Ranges
Packages
1.8V-5.5V
2.5V-5.5V
64 Byte
64 Byte
I
MF, P, SN, SM, ST
MF, P, SN, SM, ST
25LC128
I, E
Features
Pin Function Table
Name
Function
Chip Select Input
Serial Data Output
• Maximum Clock: 10 MHz
• Low-Power CMOS Technology:
CS
SO
- Write current (maximum): 5 mA at 5.5V,
10 MHz
WP
Write-Protect
Ground
- Read current: 5 mA at 5.5V, 10 MHz
- Standby current: 5 µA at 5.5V
• 16,384 x 8-Bit Organization
• 64-Byte Page
VSS
SI
Serial Data Input
Serial Clock Input
Hold Input
SCK
HOLD
VCC
• Self-Timed Erase and Write Cycles
(5 ms maximum)
Supply Voltage
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
Description
The Microchip Technology Inc. 25XX128(1) is a
128 Kbit Serial Electrically Erasable PROM. The mem-
ory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a Chip Select (CS) input.
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• RoHS Compliant
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
• Temperature Ranges;
- Industrial (I):
- Extended (E):
-40C to +85C
-40°C to +125°C
Note 1: 25XX128 is used in this document as a
generic part number for the 25AA128/
25LC128 devices.
• Automotive AEC-Q100 Qualified
Packages
• 8-Lead DFN, 8-Lead PDIP, 8-Lead SOIC,
8-Lead SOIJ and 8-Lead TSSOP
8-Lead DFN
8-Lead PDIP/SOIC/SOIJ
8-Lead TSSOP
(Top View)
8-Lead X-Rotated TSSOP
(Top View)
(Top View)
(Top View)
CS
SO
WP
VSS
1
8
VCC
1
2
8
VCC
CS
SO
HOLD
VCC
CS
CS
SO
WP
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VCC
SCK
SI
VSS
WP
2
7
7
6
5
HOLD
SCK
SI
HOLD
SCK
HOLD
3
6
WP 3
VSS
SCK
SI
4
SO
4
5
SI
VSS
2003-2019 Microchip Technology Inc.
DS20001831F-page 1
25AA128/25LC128
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Extended (E):
TA = -40°C to +85°C
TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
D1
D2
D3
D4
D5
D6
D7
D8
D9
VIH
VIL1
VIL2
VOL
VOL
VOH
ILI
High-Level Input Voltage
Low-Level Input Voltage
0.7 VCC
VCC+1
V
V
-0.3
-0.3
—
0.3 VCC
0.2 VCC
0.4
VCC2.7V
VCC < 2.7V
IOL = 2.1 mA
V
Low-Level Output Voltage
V
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
IOH = -400 µA
High-Level Output Voltage VCC -0.5
—
V
Input Leakage Current
Output Leakage Current
—
—
—
±1
µA
µA
pF
CS = VCC, VIN = VSS or VCC
CS = VCC, VOUT = VSS or VCC
ILO
±1
CINT
Internal Capacitance
7
TA = 25°C, CLK = 1.0 MHz,
(all inputs and outputs)
VCC = 5.0V (Note)
D10
ICC Read Operating Current
—
—
5
mA
mA
VCC = 5.5V, FCLK = 10.0 MHz,
SO = Open
2.5
VCC = 2.5V, FCLK = 5.0 MHz
SO = Open
D11
D12
ICC Write Operating Current
—
—
—
5
3
5
mA
mA
µA
VCC = 5.5V
VCC = 2.5V
ICCS
Standby Current
CS = VCC = 5.5V, Inputs tied to VCC
or VSS, 125°C
—
1
µA
CS = VCC = 5.5V, Inputs tied to VCC
or VSS, 85°C
Note:
This parameter is periodically sampled and not 100% tested.
2003-2019 Microchip Technology Inc.
DS20001831F-page 2
25AA128/25LC128
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Extended (E):
TA = -40°C to +85°C
TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Clock Frequency
Min.
Max.
Units
Conditions
1
2
3
FCLK
TCSS
TCSH
—
—
10
5
MHz 4.5V Vcc 5.5V
MHz 2.5V Vcc 4.5V
MHz 1.8V Vcc 2.5V
—
3
CS Setup Time
CS Hold Time
50
100
150
100
200
250
50
10
20
30
20
40
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
—
—
—
—
—
—
—
—
50
100
160
—
40
80
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4
5
TCSD
TSU
CS Disable Time
Data Setup Time
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
Note 1
6
THD
Data Hold Time
7
8
9
TR
TF
CLK Rise Time
CLK Fall Time
Clock High Time
—
Note 1
THI
50
100
150
50
100
150
50
50
—
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
10
TLO
Clock Low Time
11
12
13
TCLD
TCLE
TV
Clock Delay Time
Clock Enable Time
Output Valid from Clock
Low
4.5V Vcc 5.5V
—
2.5V Vcc 4.5V
—
1.8V Vcc 2.5V
14
15
THO
TDIS
Output Hold Time
0
Note 1
Output Disable Time
—
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
—
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website:
www.microchip.com.
2003-2019 Microchip Technology Inc.
DS20001831F-page 3
25AA128/25LC128
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I):
Extended (E):
TA = -40°C to +85°C
TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Conditions
16
17
18
19
THS
THH
THZ
THV
TWC
HOLD Setup Time
20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
4.5V Vcc 5.5V
40
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
Note 2
80
—
HOLD Hold Time
20
—
40
—
80
—
HOLD Low to Output
High-Z
—
30
60
160
30
60
160
5
—
—
HOLD High to Output
Valid
—
—
—
20
21
Internal Write Cycle Time
Endurance
—
1,000,000
—
E/W Page mode, 25°C, VCC = 5.5V
Cycles (Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website:
www.microchip.com.
TABLE 1-1:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
Note 1
VHI = 4.0V
Note 2
CL = 50 pF
Timing Measurement Reference Level
Input
0.5 VCC
0.5 VCC
Output
Note 1: For VCC 4.0V
2: For VCC > 4.0V
2003-2019 Microchip Technology Inc.
DS20001831F-page 4
25AA128/25LC128
FIGURE 1-1: HOLD TIMING
CS
17
17
16
16
SCK
18
19
High-Impedance
n
SO
n + 2
n + 2
n + 1
n
n - 1
5
Don’t Care
n
n + 1
n
n - 1
SI
HOLD
FIGURE 1-2: SERIAL INPUT TIMING
4
CS
12
11
2
7
3
8
Mode 1,1
Mode 0,0
SCK
SI
5
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
3
9
10
Mode 1,1
Mode 0,0
SCK
13
15
LSB out
14
MSB out
SO
SI
Don’t Care
2003-2019 Microchip Technology Inc.
DS20001831F-page 5
25AA128/25LC128
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
DFN(1) PDIP SOIC SOIJ TSSOP X-Rotated TSSOP
Function
Chip Select Input
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
SO
Serial Data Output
Write-Protect Pin
Ground
WP
VSS
SI
Serial Data Input
Serial Clock Input
Hold Input
SCK
HOLD
VCC
Supply Voltage
Note 1: The exposed pad on the DFN package can be connected to VSS or left floating.
The WP pin functions will be enabled when the WPEN
bit is set high.
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX128. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.2
Serial Output (SO)
2.6
Hold (HOLD)
The SO pin is used to transfer data out of the 25XX128.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
The HOLD pin is used to suspend transmission to the
25XX128 while in the middle of a serial sequence with-
out having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX128 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
2.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will dis-
able writing to the STATUS register. If an internal write
cycle has already begun, WP going low will have no
effect on the write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX128 in a system with WP pin grounded
and still be able to write to the STATUS register.
2003-2019 Microchip Technology Inc.
DS20001831F-page 6
25AA128/25LC128
3.3
Write Sequence
3.0
3.1
FUNCTIONAL DESCRIPTION
Principles of Operation
Prior to any attempt to write data to the 25AA128/
25LC128, the write enable latch must be set by issuing
the WREN instruction (Figure 3-4). This is done by set-
ting CS low and then clocking out the proper instruction
into the 25AA128/25LC128. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch. If the write operation
is initiated immediately after the WREN instruction with-
out CS being brought high, the data will not be written
to the array because the write enable latch will not have
been properly set.
The 25AA128/25LC128 is a 16,384 byte Serial
EEPROM designed to interface directly with the Serial
Peripheral Interface (SPI) port of many of today’s pop-
ular microcontroller families, including Microchip’s
PIC® microcontrollers. It may also interface with micro-
controllers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25AA128/25LC128 contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low and the HOLD pin must be high for
the entire operation.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the 16-bit address, with two
MSBs of the address being “don’t care” bits, and then
the data to be written. Up to 64 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA128/25LC128 in
‘HOLD’ mode. After releasing the HOLD pin, operation
will resume from the point when the HOLD was
asserted.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA128/
25LC128 followed by the 16-bit address, with two
MSBs of the address being “don’t care” bits. After the
correct READinstruction and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO pin. The data stored in the memory at the
next address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (3FFFh), the address counter rolls
over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 3-1).
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the Write-in-Process
(WIP) bit (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
2003-2019 Microchip Technology Inc.
DS20001831F-page 7
25AA128/25LC128
BLOCK DIAGRAM
STATUS
Register
HV Generator
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
Dec
Page Latches
Y Decoder
SI
SO
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 3-1:
INSTRUCTION SET
Instruction Name
READ
Instruction Format
Description
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read STATUS register
0000 0011
0000 0010
0000 0100
0000 0110
0000 0101
0000 0001
WRITE
WRDI
WREN
RDSR
WRSR
Write STATUS register
FIGURE 3-1: READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16-bit Address
1 15 14 13 12
0
0
0
0
0
0
1
2
1
0
Data Out
High-Impedance
7
6
5
4
3
2
1
0
SO
2003-2019 Microchip Technology Inc.
DS20001831F-page 8
25AA128/25LC128
FIGURE 3-2: BYTE WRITE SEQUENCE
CS
Twc
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Instruction
16-bit Address
15 14 13 12
Data Byte
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 3-3: PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
Data Byte 1
SCK
SI
Instruction
16-bit Address
0
0
0
0
0
0
1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte n (64 max)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2003-2019 Microchip Technology Inc.
DS20001831F-page 9
25AA128/25LC128
The following is a list of conditions under which the
write enable latch will be reset:
3.4
Write Enable (WREN) and Write
Disable (WRDI)
• Power-up
The 25AA128/25LC128 contains a write enable latch.
See Table 3-2 for the write-protect functionality matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
1
0
0
SI
High-Impedance
SO
2003-2019 Microchip Technology Inc.
DS20001831F-page 10
25AA128/25LC128
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
3.5
Read STATUS Register Instruction
(RDSR)
The Read STATUS Register instruction (RDSR)
provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as follows:
TABLE 3-2:
STATUS REGISTER
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 3-1.
7
6
–
X
5
–
X
4
–
X
3
2
1
0
W/R
W/R W/R
R
R
WPEN
Note:
BP1 BP0 WEL WIP
See Figure 3-6 for the RDSR timing sequence.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25AA128/25LC128 is busy with a write operation.
When set to a ‘1’, a write is in progress, when set to
a ‘0’, no write is in progress. This bit is read-only.
FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
0
0
0
0
0
1
0
1
SI
Data from STATUS Register
High-Impedance
7
6
5
4
3
2
1
0
SO
Note:
Bits 7-1 of the STATUS register are undetermined during a write cycle.
2003-2019 Microchip Technology Inc.
DS20001831F-page 11
25AA128/25LC128
3.6
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two, or all four
of the segments of the array. The partitioning is con-
trolled as shown in Table 3-1.
TABLE 3-1:
ARRAY PROTECTION
Array Addresses
Write-Protected
BP1
BP0
none
0
0
0
1
upper 1/4
(3000h-3FFFh)
upper 1/2
(2000h-3FFFh)
1
1
0
1
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 3-2 for a matrix of functionality
on the WPEN bit.
all
(0000h-3FFFh)
See Figure 3-7 for the WRSR timing sequence.
FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
0
SCK
Instruction
Data to STATUS Register
7
6
5
4
3
2
0
0
0
0
0
0
0
1
SI
High-Impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
2003-2019 Microchip Technology Inc.
DS20001831F-page 12
25AA128/25LC128
3.7
Data Protection
3.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25AA128/25LC128 powers on in the following
state:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 3-2:
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
0
1
1
1
x
0
1
1
x
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
x
0 (low)
1 (high)
Note:
x = don’t care
2003-2019 Microchip Technology Inc.
DS20001831F-page 13
25AA128/25LC128
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN-S
Example
XXXXXXX
T/XXXXX
YYWW
25LC128
I/MF
1934
13F
e
3
NNN
8-Lead PDIP (300 mil)
Example
25AA128
XXXXXXX
T/XXXNNN
3
I/P
e
13F
1934
YYWW
8-Lead SOIC (3.90 mm)
Example
25LC128I
XXXXXXXX
XXXYYWW
NNN
SN
1934
13F
e
3
8-Lead SOIJ (5.28 mm)
Example
25LC128
XXXXXXXX
T/XXXXXXX
YYWWNNN
e
3
I/SM
193413F
8-Lead TSSOP
Example
XXXX
TYYW
NNN
5LD
I934
13F
st
1
Line Marking Codes
SOIC
Part
No.
DFN
PDIP
SOIJ
TSSOP
I-Temp. E-Temp.
I-Temp.
25AA128
E-Temp.
I-Temp.
E-Temp.
I-Temp. E-Temp. I-Temp. E-Temp.
(1)
(1)
25AA128 25AA128
—
—
25AA128T
25AA128T
25AA128
—
5AD
—
—
(2)
5ADX
(1)
(1)
25LC128 25LC128 25LC128 25LC128 25LC128 25LC128T
25LC128T
25AA128 25AA128
5LD
5LD
(3)
(3)
5LDX
5LDX
Note 1: T = Temperature grade (I, E)
2: For 25AA128X
3: For 25LC128X
2003-2019 Microchip Technology Inc.
DS20001831F-page 14
25AA128/25LC128
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
e
3
* Standard OTP marking consists of Microchip part number, year code, week code and
traceability code.
Note: For very small packages with no room for the JEDEC® designator
e
3
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2019 Microchip Technology Inc.
DS20001831F-page 15
25AA128/25LC128
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2003-2019 Microchip Technology Inc.
DS20001831F-page 16
25AA128/25LC128
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2003-2019 Microchip Technology Inc.
DS20001831F-page 17
25AA128/25LC128
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
2003-2019 Microchip Technology Inc.
DS20001831F-page 18
25AA128/25LC128
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
2003-2019 Microchip Technology Inc.
DS20001831F-page 19
25AA128/25LC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
2003-2019 Microchip Technology Inc.
DS20001831F-page 20
25AA128/25LC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
E1
D
3.90 BSC
4.90 BSC
Chamfer (Optional)
Foot Length
h
L
0.25
0.40
-
-
0.50
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
b
0.25
0.51
15°
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
2003-2019 Microchip Technology Inc.
DS20001831F-page 21
25AA128/25LC128
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
2003-2019 Microchip Technology Inc.
DS20001831F-page 22
25AA128/25LC128
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2019 Microchip Technology Inc.
DS20001831F-page 23
25AA128/25LC128
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2019 Microchip Technology Inc.
DS20001831F-page 24
25AA128/25LC128
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2019 Microchip Technology Inc.
DS20001831F-page 25
25AA128/25LC128
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
0.65 BSC
Overall Height
Molded Package Thickness
Standoff
A
–
0.80
0.05
–
1.00
–
1.20
1.05
0.15
A2
A1
E
Overall Width
6.40 BSC
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
4.30
2.90
0.45
4.40
3.00
0.60
4.50
3.10
0.75
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
φ
1.00 REF
0°
0.09
0.19
–
–
–
8°
c
b
0.20
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
2003-2019 Microchip Technology Inc.
DS20001831F-page 26
25AA128/25LC128
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2019 Microchip Technology Inc.
DS20001831F-page 27
25AA128/25LC128
APPENDIX A: REVISION HISTORY
Revision F (08/2019)
Updated content throughout for clarification.
Update 8L PDIP Package Drawing.
Revision E (07/2011)
Added SOIJ (SM) package.
Revision D (06/2009)
Added X-Rotated TSSOP to package types; Revised
Table 1-2, Param. 21; Revised Table 3-1; Revised
TSSOP Line Marking table; Added SOIC Land Pattern;
Revised Product ID section.
Revision C (05/2007)
Removed Preliminary status; Revised Table 1-2, Para.
7 and 8; Revised Table 1-3, CL; Revised trademarks;
Replaced Package drawings (Rev. AP); Replaced On-
Line Support; Revised Product ID section.
Revision B (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Revision A(09/2003)
Initial release of this document.
2003-2019 Microchip Technology Inc.
DS20001831F-page 28
25AA128/25LC128
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.
2003-2019 Microchip Technology Inc.
DS20001831F-page 29
25AA128/25LC128
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
(1)
-X
/XX
[X]
PART NO.
Device
a) 25AA128T-I/SN: Tape and Reel, Industrial
Temp., 1.8V, SOIC package.
Temperature Package
Range
Tape and Reel
Option
b) 25AA128T-I/ST: Tape and Reel, Industrial
Temp.,
1.8V,
TSSOP
package.
Device:
25AA128:
25LC128:
25AA128X:
128-Kbit, 1.8V,SPI Serial EEPROM
128-Kbit, 2.5V, SPI Serial EEPROM
128-Kbit, 1.8V, SPI Serial EEPROM in
alternate pinout (ST only)
128-Kbit, 2.5V, SPI Serial EEPROM in
alternate pinout (ST only)
c) 25LC128-I/P:
Industrial Temp., 2.5V, PDIP
package.
d) 25LC128T-E/MF: Tape and Reel, Extended
Temp., 2.5V, DFN package.
25LC128X:
e) 25LC128XT-I/ST: Tape and Reel, Industrial
Temp., 2.5V, Rotated pinout,
TSSOP package.
Tape and Reel Blank = Standard packaging (tube or tray)
(1)
Option:
T
= Tape and Reel
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
MF
P
=
=
=
=
=
Plastic Dual Flat, No Lead Package –
5x6x0.85 mm Body, 8-lead (DFN-S)
Plastic Dual In-Line – 300 mil Body, 8-lead
(PDIP)
Plastic Small Outline - Narrow, 3.90 mm
Body, 8-lead (SOIC)
Plastic Small Outline - Medium, 5.28 mm
Body, 8-lead (SOIJ)
Plastic Thin Shrink Small Outline – 4.4 mm,
8-lead (TSSOP)
Note 1: Tape and Reel identifier only appears
in the catalog part number description.
This identifier is used for ordering pur-
poses and is not printed on the device
package. Check with your Microchip
Sales Office for package availability
with the Tape and Reel option.
SN
SM
ST
2: Contact Microchip for Automotive
grade ordering part numbers.
2003-2019 Microchip Technology Inc.
DS20001831F-page 30
25AA128/25LC128
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2019, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
ISBN: 978-1-5224-4947-8
2003-2019 Microchip Technology Inc.
DS20001831F-page 31
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2003-2019 Microchip Technology Inc.
DS20001831F-page 32
05/14/19
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