25AA160T-E/P [MICROCHIP]
16K SPI Bus Serial EEPROM; 16K SPI总线串行EEPROM
| 型号： | 25AA160T-E/P |
| 厂家： | 
MICROCHIP |
| 描述： | 16K SPI Bus Serial EEPROM |
| 文件： | 总22页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not recommended for new designs –
Please use 25AA160A/B or 25LC160A/B.
25AA160/25LC160/25C160
16K SPI™ Bus Serial EEPROM
Device Selection Table
Description:
The Microchip Technology Inc. 25AA160/25LC160/
25C160 (25XX160*) are 16 Kbit Serial Electrically
Erasable PROMs. The memory is accessed via a
simple Serial Peripheral Interface™ (SPI™) compati-
ble serial bus. The bus signals required are a clock
input (SCK) plus separate data in (SI) and data out
(SO) lines. Access to the device is controlled through a
Chip Select (CS) input.
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
25AA160
25LC160
25C160
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
I
I
I,E
Features:
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
• Low-power CMOS technology:
- Write current: 3 mA maximum
- Read current: 500 µA typical
- Standby current: 500 nA typical
• 2048 x 8-bit organization
• 16 byte page
Package Types
• Write cycle time: 5 ms max.
• Self-timed erase and write cycles
• Block write protection:
PDIP/SOIC
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
WP
VSS
- Write-protect pin
• Sequential read
Block Diagram
• High reliability:
Status
Register
HV Generator
- Endurance: 1 M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP and SOIC packages
• Temperature ranges supported:
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
- Industrial (I):
-40°C to +85°C
Dec
- Automotive (E) (25C160):
-40°C to +125°C
Page Latches
Y Decoder
SI
SO
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
*25XX160 is used in this document as a generic part number
for the 25AA160/25LC160/25C160 devices.
SPI™ is a trademark of Motorola Inc.
2004 Microchip Technology Inc.
DS21231D-page 1
25AA160/25LC160/25C160
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins......................................................................................................................................... 4 KV
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability.
1.1
DC Characteristics
Industrial (I):
TA = -40°C to +85°C VCC = 1.8V to 5.5V
DC CHARACTERISTICS
Param.
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C160 only)
Sym.
Characteristics
Min.
Max.
Units
Conditions
VCC ≥ 2.7V (Note)
No.
D1
VIH1
High-level input
voltage
2.0
0.7 VCC
-0.3
VCC+1
VCC+1
0.8
V
V
V
V
V
V
V
D2
D3
D4
D5
D6
D7
VIH2
VIL1
VIL2
VOL
VOL
VOH
VCC< 2.7V (Note)
VCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
IOL = 2.1 mA
Low-level input
voltage
-0.3
0.3 VCC
0.4
Low -level output
voltage
—
—
0.2
IOL = 1.0 mA, VCC < 2.5V
IOH = -400 µA
High-level output
voltage
VCC -0.5
—
D8
D9
ILI
Input leakage current
-10
-10
10
10
µA
µA
CS = VCC, VIN = VSS TO VCC
CS = VCC, VOUT = VSS TO VCC
ILO
Output leakage
current
D10
D11
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
ICC Read
—
—
1
500
mA
µA
VCC = 5.5V; FCLK = 3.0 MHz;
SO = Open
Operating Current
VCC = 2.5V; FCLK = 2.0 MHz;
SO = Open
D12
D13
ICC Write
ICCS
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
Standby Current
—
—
5
1
µA
µA
CS = VCC = 5.5V, Inputs tied to VCC or
VSS
CS = VCC = 2.5V, Inputs tied to VCC or
VSS
Note:
This parameter is periodically sampled and not 100% tested.
DS21231D-page 2
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
1.2
AC Characteristics
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
VCC = 4.5V to 5.5V (25C160 only)
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Clock Frequency
Min.
Max.
Units
Conditions
1
2
3
FCLK
TCSS
TCSH
—
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Setup Time
CS Hold Time
100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
4
5
TCSD
TSU
CS Disable Time
Data Setup Time
500
—
ns
—
30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
6
THD
Data Hold Time
50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
7
8
9
TR
TF
CLK Rise Time
CLK Fall Time
Clock High Time
—
—
2
2
µs
µs
(Note 1)
(Note 1)
THI
150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
10
TLO
Clock Low Time
150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
11
12
13
TCLD
TCLE
TV
Clock Delay Time
Clock Enable Time
50
50
—
—
ns
ns
—
—
Output Valid from Clock
Low
—
—
—
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
14
15
THO
TDIS
Output Hold Time
0
—
ns
(Note 1)
Output Disable Time
—
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
16
17
18
19
THS
THH
THZ
THV
HOLD Setup Time
HOLD Hold Time
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Low to Output High-
Z
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
HOLD High to Output Valid
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
20
21
TWC
—
Internal Write Cycle Time
Endurance
—
5
ms
—
1 M
—
E/W
(Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
™
consult the Total Endurance Model which can be obtained from Microchip’s web site at: www.microchip.com.
2004 Microchip Technology Inc.
DS21231D-page 3
25AA160/25LC160/25C160
FIGURE 1-1:
HOLD TIMING
CS
17
16
16
17
SCK
SO
18
19
High-impedance
don’t care
n
n+2
n+2
n+1
n
n-1
5
n
n+1
n
n-1
SI
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
12
2
11
7
3
8
Mode 1,1
Mode 0,0
SCK
SI
5
6
MSB in
LSB in
High-impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
3
9
10
Mode 1,1
Mode 0,0
SCK
13
15
ISB out
14
MSB out
SO
SI
don’t care
DS21231D-page 4
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
FIGURE 1-4:
AC TEST CIRCUIT
1.3
AC Test Conditions
VCC
AC Waveform:
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
(Note 2)
2.25 KΩ
1.8 KΩ
VHI = 4.0V
Timing Measurement Reference Level
Input
SO
0.5 VCC
0.5 VCC
100 pF
Output
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
2004 Microchip Technology Inc.
DS21231D-page 5
25AA160/25LC160/25C160
2.4
Serial Input (SI)
2.0
PIN DESCRIPTIONS
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name PDIP
SOIC
Description
2.5
Serial Clock (SCK)
Chip Select Input
CS
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
The SCK is used to synchronize the communication
between a master and the 25XX160. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
SO
Serial Data Output
Write-Protect Pin
Ground
WP
VSS
SI
Serial Data Input
Serial Clock Input
Hold Input
SCK
HOLD
Vcc
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX160 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX160 must remain selected
during this sequence. The SI, SCK, and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial commu-
nication will not resume. Lowering the HOLD line at any
time will tri-state the SO line.
Supply Voltage
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already initi-
ated or in progress will be completed, regardless of the
CS input signal. If CS is brought high during a program
cycle, the device will go into Standby mode as soon as
the programming cycle is complete. When the device is
deselected, SO goes to the high-impedance state,
allowing multiple parts to share the same SPI bus. A
low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25XX160.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the nonvolatile bits in the Status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP going low will have no effect on the write.
The WP pin function is blocked when the WPEN bit in
the Status register is low. This allows the user to install
the 25XX160 in a system with WP pin grounded and
still be able to write to the Status register. The WP pin
functions will be enabled when the WPEN bit is set
high.
DS21231D-page 6
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
3.3
Write Sequence
3.0
3.1
FUNCTIONAL DESCRIPTION
Principles of Operation
Prior to any attempt to write data to the 25XX160, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX160. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.
The 25XX160 are 2048 byte Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC16C6X/7X
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using dis-
crete I/O lines programmed properly with the software.
The 25XX160 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation. The WP pin must be held high to allow
writing to the memory array.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITEinstruc-
tion, followed by the 16-bit address, with the five MSBs
of the address being "don’t care" bits, and then the data
to be written. Up to 16 bytes of data can be sent to the
25XX160 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with xxxxxxxx
xxxx0000and ends with xxxxxxxxxxxx1111.
If the internal address counter reaches xxxx xxxx
xxxx1111and the clock continues, the counter will
roll back to the first address of the page and overwrite
any data in the page that may have been written.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX160 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX160
followed by the 16-bit address, with the five MSBs of
the address being "don’t care" bits. After the correct
READinstruction and address are sent, the data stored
in the memory at the selected address is shifted out on
the SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (07FFh), the address counter rolls
over to address 0000h allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 3-1).
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
WRITE
WRDI
WREN
RDSR
WRSR
0000 0011
0000 0010
0000 0100
0000 0110
0000 0101
0000 0001
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status register
Write Status register
2004 Microchip Technology Inc.
DS21231D-page 7
25AA160/25LC160/25C160
FIGURE 3-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
instruction
16-bit address
1 15 14 13 12
0
0
0
0
0
0
1
2
1
0
SI
data out
High-impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-2:
BYTE WRITE SEQUENCE
CS
Twc
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
data byte
SCK
SI
instruction
16-bit address
15 14 13 12
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
High-impedance
SO
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
data byte 1
SCK
instruction
16-bit address
0
0
0
0
0
0
1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39
data byte 2
41 42 43 44 45 46 47
data byte 3
40
7
SCK
SI
data byte n (16 max)
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DS21231D-page 8
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
The following is a list of conditions under which the
write enable latch will be reset:
3.4
Write Enable (WREN) and Write
Disable (WRDI)
• Power-up
The 25XX160 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WRENinstruction will set the
latch, and the WRDIwill reset the latch.
• WRDIinstruction successfully executed
• WRSRinstruction successfully executed
• WRITEinstruction successfully executed
FIGURE 3-4:
WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
1
1
0
SI
High-impedance
SO
FIGURE 3-5:
WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
0
1
0
SI
High-impedance
SO
2004 Microchip Technology Inc.
DS21231D-page 9
25AA160/25LC160/25C160
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
register. This bit is read-only.
3.5
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
7
6
5
4
3
2
1
0
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSRinstruction. These
bits are nonvolatile.
WPEN
X
X
X
BP1
BP0
WEL
WIP
The Write-In-Process (WIP) bit indicates whether the
25XX160 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
See Figure 3-6 for the RDSR timing sequence.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15
SCK
SI
instruction
0
0
0
0
0
1
0
1
data from Status register
High-impedance
7
6
5
4
3
2
1
0
SO
TABLE 3-2:
BP1
ARRAY PROTECTION
3.6
Write Status Register (WRSR)
Array Addresses
Write-Protected
The Write Status register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
BP0
0
0
0
1
none
upper 1/4
(0600h - 07FFh)
1
1
0
1
upper 1/2
(0400h - 07FFh)
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
all
(0000h - 07FFh)
See Figure 3-7 for the WRSR timing sequence.
DS21231D-page 10
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
0
SCK
SI
instruction
data to Status register
7
6
5
4
3
2
0
0
0
0
0
0
0
1
High-impedance
SO
3.7
Data Protection
3.8
Power On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25XX160 powers on in the following state:
• The device is in low power Standby mode (CS=1)
• The write enable latch is reset
• The write enable latch is reset on power-up
• A WRITE ENABLEinstruction must be issued to
set the write enable latch
• SO is in high-impedance state
• A low level on CS is required to enter active state
• After a byte write, page write, or Status register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 3-3:
WPEN
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
X
0
1
X
X
X
0
1
1
1
Protected
Writable
Low
High
Protected
Writable
Protected
Writable
Protected
Writable
2004 Microchip Technology Inc.
DS21231D-page 11
25AA160/25LC160/25C160
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
25LC160
I/PNNN
YYWW
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
25C160
XXXXYYWW
I/SNYYWW
NNN
NNN
Legend: XX...X Customer specific information*
YYear code (last digit of calendar year)
YYYear code (last 2 digits of calendar year)
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line thus limiting the number of available
characters for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS21231D-page 12
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
1
n
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2004 Microchip Technology Inc.
DS21231D-page 13
25AA160/25LC160/25C160
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21231D-page 14
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
APPENDIX A: REVISION HISTORY
Revision D
Added note to page 1 header (Not recommended for
new designs).
Updated document format.
2004 Microchip Technology Inc.
DS21231D-page 15
25AA160/25LC160/25C160
NOTES:
DS21231D-page 16
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2004 Microchip Technology Inc.
DS21231D-page 17
25AA160/25LC160/25C160
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
25AA160/25LC160/25C160
DS21231D
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21231D-page 18
2004 Microchip Technology Inc.
25AA160/25LC160/25C160
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a) 25AA160-I/P: Industrial Temp.,
PDIP package
b) 25AA160-I/SN: Industrial Temp.,
SOIC package
Device
25AA160: 16 Kbit 1.8V SPI Serial EEPROM
25AA160T: 16 Kbit 1.8V SPI Serial EEPROM (Tape and Reel)
25LC160: 16 Kbit 2.5V SPI Serial EEPROM
c) 25LC160-I/SN: Industrial Temp.,
SOIC package
25LC160T: 16 Kbit 2.5V SPI Serial EEPROM (Tape and Reel)
25C160: 16 Kbit 5.0V SPI Serial EEPROM
25C160T: 16 Kbit 5.0V SPI Serial EEPROM (Tape and Reel)
d) 25LC160T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
e) 25C160-E/P: Extended Temp.,
PDIP package
f)
25C160-E/SN: Extended Temp.,
SOIC package
Temperature Range
Package
I
E
=
=
-40°C to +85°C
-40°C to +125°C
P
SN
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21231D-page 19
25AA160/25LC160/25C160
NOTES:
DS21231D-page 20
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21231D-page 21
WORLDWIDE SALES AND SERVICE
China - Beijing
Singapore
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: www.microchip.com
Unit 706B
200 Middle Road
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No. 6 Chaoyangmen Bei Str.
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Tel: 86-10-85282100
Fax: 86-10-85282104
#07-02 Prime Centre
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Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4816
Fax: 886-7-536-4817
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
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Tel: 86-28-86766200
Atlanta
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Tel: 770-640-0034
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Taiwan
Taiwan Branch
Fax: 86-28-86766599
Boston
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Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
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Tel: 91-80-22290061 Fax: 91-80-22290062
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Fax: 650-961-0286
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Netherlands
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Toronto
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ASIA/PACIFIC
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United Kingdom
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Korea
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Fax: 44-118-921-5820
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
DS21231D-page 22
2004 Microchip Technology Inc.
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