25AA512T-E/P_技术文档

25AA512/25LC512

512 Kbit SPI Bus Serial EEPROM

Device Selection Table

Part Number

VCC Range

Page Size

Temp. Ranges

Packages

25LC512

25AA512

2.5-5.5V

1.8-5.5V

128 Byte

I,E

I

P, SN, SM, MF

Features:

Description:

• 20 MHz max. Clock Speed

• Byte and Page-level Write Operations

- 128-byte page

The Microchip Technology Inc. 25AA512/25LC512

(25XX512^*) is a 512 Kbit serial EEPROM memory with

byte-level and page-level serial EEPROM functions. It

also features Page, Sector and Chip erase functions

typically associated with Flash-based products. These

functions are not required for byte or page write opera-

tions. The memory is accessed via a simple Serial

Peripheral Interface (SPI) compatible serial bus. The

bus signals required are a clock input (SCK) plus sepa-

rate data in (SI) and data out (SO) lines. Access to the

device is controlled by a Chip Select (CS) input.

- 5 ms max.

- No page or sector erase required

• Low-Power CMOS Technology

- Max. Write Current: 5 mA at 5.5V, 20 MHz

- Read Current: 10 mA at 5.5V, 20 MHz

- Standby Current: 1μA at 2.5V (Deep power-

down)

• Electronic Signature for Device ID

• Self-Timed Erase and Write cycles

- Page Erase (5 ms, typical)

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

- Sector Erase (10 ms/sector, typical)

- Bulk Erase (10 ms, typical)

• Sector Write Protection (16K byte/sector)

- Protect none, 1/4, 1/2 or all of array

The 25XX512 is available in standard packages includ-

ing 8-lead PDIP, SOIC, and advanced 8-lead DFN

package. All packages are Pb-free and RoHS

compliant.

• Built-In Write Protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High Reliability

- Endurance: 1 Million erase/write cycles

Package Types (not to scale)

• Temperature Ranges Supported;

DFN

PDIP/SOIC/SOIJ

(P, SN, SM)

- Industrial (I):

- Automotive (E):

-40°C to +85°C

-40°C to +125°C

(MF)

1

2

3

4

CS

SO

8

7

6

5

VCC

HOLD

SCK

SI

• Pb-free and RoHS Compliant

CS

SO

WP

VCC

1

2

3

4

8

7

6

5

HOLD

SCK

SI

Pin Function Table

WP

VSS

Name

Function

V

SS

CS

SO

Chip Select Input

Serial Data Output

WP

VSS

SI

Write-Protect

Ground

Serial Data Input

Serial Clock Input

SCK

HOLD

VCC

Hold Input

Supply Voltage

*25XX512 is used in this document as a generic part number

for the 25AA512, 25LC512 devices.

Preliminary

DS22021B-page 1

25AA512/25LC512

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Industrial (I):

Automotive (E):

TA = 0°C to +85°C

TA = -40°C to +85°C

TA = -40°C to +125°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

VCC = 2.5V to 5.5V

DC CHARACTERISTICS

Param.

Sym.

Characteristic

Min.

Max.

VCC +1

Units

Test Conditions

No.

D001

VIH1

High-level input

voltage

.7 VCC

V

D002

D003

D004

D005

D006

VIL1

VIL2

VOL

VOH

Low-level input

voltage

-0.3

0.3 VCC

0.2 VCC

0.4

V

VCC ≥ 2.7V

VCC < 2.7V

Low-level output

voltage

—

IOL = 2.1 mA

—

0.2

IOL = 1.0 mA, VCC < 2.5V

IOH = -400 μA

High-level output

voltage

VCC -0.5

—

D007

D008

ILI

Input leakage current

—

±1

μA

CS = VCC, VIN = VSS TO VCC

CS = VCC, VOUT = VSS TO VCC

ILO

Output leakage

current

D009

D010

CINT

Internal capacitance

(all inputs and

outputs)

—

7

pF

TA = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

ICC Read

—

10

5

mA

VCC = 5.5V; FCLK = 20.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 10.0 MHz;

SO = Open

Operating current

D011

D012

ICC Write

ICCS

—

7

5

mA

VCC = 5.5V

VCC = 2.5V

—

20

μA

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, 125°C

Standby current

10

μA

CS = VCC = 5.5V, Inputs tied to VCC or

VSS, 85°C

D13

ICCSPD

Deep power-down

current

—

2

1

μA

CS = VCC = 2.5V, Inputs tied to VCC or

VSS, 125°C

CS = VCC = 2.5V, Inputs tied to VCC or

VSS, 85°C

Note:

This parameter is periodically sampled and not 100% tested.

DS22021B-page 2

Preliminary

25AA512/25LC512

TABLE 1-2:

AC CHARACTERISTICS

Industrial (I):

Automotive (E):

TA = 0°C to +85°C

TA = -40°C to +85°C

TA = -40°C to +125°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Param.

Sym.

No.

Characteristic

Clock frequency

Min.

Max.

Units

Conditions

1

2

3

FCLK

TCSS

TCSH

—

20

10

2

MHz 4.5 ≤ VCC ≤ 5.5

MHz 2.5 ≤ VCC < 4.5

MHz 1.8 ≤ VCC < 2.5

CS setup time

CS hold time

25

50

250

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

50

100

500

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

(Note 3)

4

5

TCSD

Tsu

CS disable time

Data setup time

50

—

ns

5

10

50

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

6

THD

Data hold time

10

20

100

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

7

8

9

TR

TF

CLK rise time

CLK fall time

Clock high time

—

20

ns

(Note 1)

THI

25

50

250

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

10

TLO

Clock low time

25

50

250

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

11

12

13

TCLD

TCLE

TV

Clock delay time

50

—

ns

Clock enable time

Output valid from clock low

—

25

50

250

ns

4.5 ≤ VCC ≤ 5.5

2.8 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

14

15

THO

TDIS

Output hold time

0

—

ns

(Note 1)

Output disable time

—

25

50

250

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

(Note 1)

16

17

THS

THH

HOLD setup time

HOLD hold time

10

20

100

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

10

20

100

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance

estimates in a specific application, please consult the Total Endurance™ Model which can be obtained

from our web site at www.microchip.com.

3: Includes THI time.

Preliminary

DS22021B-page 3

25AA512/25LC512

TABLE 1-2:

AC CHARACTERISTICS (CONTINUED)

Industrial (I):

Automotive (E):

TA = 0°C to +85°C

TA = -40°C to +85°C

TA = -40°C to +125°C

VCC = 1.8V to 5.5V

VCC = 2.0V to 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Param.

Sym.

No.

Characteristic

Min.

Max.

Units

Conditions

18

THZ

HOLD low to output

High-Z

15

30

150

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

(Note 1)

19

THV

HOLD high to output valid

15

30

150

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ VCC < 4.5

1.8 ≤ VCC < 2.5

20

21

TREL

TPD

CS High to Standby mode

—

100

μs

VCC = 1.8V to 5.5V

CS High to Deep power-

down

22

23

24

TCE

TSE

TWC

Chip erase cycle time

Sector erase cycle time

Internal write cycle time

—

10

5

ms

VCC = 1.8V to 5.5V

Byte or Page mode and Page

Erase

25

—

Endurance

1M

—

E/W (Note 2) Per Page

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance

estimates in a specific application, please consult the Total Endurance™ Model which can be obtained

from our web site at www.microchip.com.

3: Includes THI time.

TABLE 1-3:

AC TEST CONDITIONS

AC Waveform:

VLO = 0.2V

—

VHI = VCC - 0.2V

(Note 1)

(Note 2)

—

VHI = 4.0V

CL = 30 pF

Timing Measurement Reference Level

Input

0.5 VCC

Output

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

DS22021B-page 4

Preliminary

25AA512/25LC512

FIGURE 1-1: HOLD TIMING

CS

16

17

16

17

16

17

18

16

17

SCK

SO

18

n

19

High-Impedance

Don’t Care

High-Impedance

Don’t Care

n + 1

n

n - 1

n - 2

5

n + 1

n

n - 1

SI

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

4

CS

12

11

2

7

3

8

Mode 1,1

Mode 0,0

SCK

SI

5

6

MSB in

LSB in

High-Impedance

SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

3

9

10

Mode 1,1

Mode 0,0

SCK

13

15

LSB out

14

MSB out

SO

SI

Don’t Care

Preliminary

DS22021B-page 5

25AA512/25LC512

2.0

2.1

FUNCTIONAL DESCRIPTION

Principles of Operation

BLOCK DIAGRAM

The 25XX512 is a 65,536 byte Serial EEPROM

designed to interface directly with the Serial Periph-

eral Interface (SPI) port of many of today’s popular

microcontroller families, including Microchip’s PIC^®

microcontrollers. It may also interface with microcon-

trollers that do not have a built-in SPI port by using

discrete I/O lines programmed properly in firmware to

match the SPI protocol.

STATUS

Register

HV Generator

EEPROM

Array

Memory

Control

Logic

X

I/O Control

Logic

Dec

The 25XX512 contains an 8-bit instruction register. The

device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

Page Latches

Y Decoder

SI

SO

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB first, LSB

last.

CS

SCK

Sense Amp.

R/W Control

HOLD

WP

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25XX512 in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

VCC

VSS

TABLE 2-1:

INSTRUCTION SET

Instruction Name

Instruction Format

Description

READ

WRITE

WREN

WRDI

RDSR

WRSR

PE

0000 0011

0000 0010

0000 0110

0000 0100

0000 0101

0000 0001

0100 0010

1101 1000

1100 0111

1010 1011

1011 1001

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Set the write enable latch (enable write operations)

Reset the write enable latch (disable write operations)

Read STATUS register

Write STATUS register

Page Erase – erase one page in memory array

Sector Erase – erase one sector in memory array

Chip Erase – erase all sectors in memory array

Release from Deep power-down and read electronic signature

Deep Power-Down mode

SE

CE

RDID

DPD

DS22021B-page 6

Preliminary

25AA512/25LC512

provide clock pulses. The internal Address Pointer is

automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address is reached (FFFFh), the address counter rolls

over to address 0000h allowing the read cycle to be

continued indefinitely. The READ instruction is

terminated by raising the CS pin (Figure 2-1).

Read Sequence

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the 25XX512 fol-

lowed by the 16-bit address. After the correct READ

instruction and address are sent, the data stored in the

memory at the selected address is shifted out on the

SO pin. The data stored in the memory at the next

address can be read sequentially by continuing to

FIGURE 2-1:

READ SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9 10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

Instruction

16-bit Address

15 14 13 12

0

1

2

1

0

SI

Data Out

High-Impedance

7

6

5

4

3

2

1

0

SO

Preliminary

DS22021B-page 7

25AA512/25LC512

.

2.2

Write Sequence

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’), and end at addresses that are

integer multiples of page size – 1. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

Prior to any attempt to write data to the 25XX512, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX512. After all eight bits of the instruction are trans-

mitted, the CS must be brought high to set the write

enable latch. If the write operation is initiated immedi-

ately after the WREN instruction without CS being

brought high, the data will not be written to the array

because the write enable latch will not have been

properly set.

A write sequence includes an automatic, self timed

erase cycle. It is not required to erase any portion of the

memory prior to issuing a WRITEinstruction.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITEinstruc-

tion, followed by the 16-bit address, and then the data

to be written. Up to 128 bytes of data can be sent to the

device before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page. When doing a write of less than 128 bytes

the data in the rest of the page is refreshed along with

the data bytes being written. This will force the entire

page to endure a write cycle, for this reason endurance

is specified per page

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the n^thdata byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence, respectively.

While the write is in progress, the STATUS register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

FIGURE 2-2:

BYTE WRITE SEQUENCE

CS

Twc

0

1

2

3

4

5

6

7

8

9 10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

SI

Instruction

16-bit Address

15 14 13 12

Data Byte

0

1

0

2

1

0

7

6

5

4

3

2

1

0

High-Impedance

SO

DS22021B-page 8

Preliminary

25AA512/25LC512

FIGURE 2-3:

PAGE WRITE SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9

10 11

21 22 23 24 25 26 27 28 29 30 31

Data Byte 1

SCK

Instruction

16-bit Address

0

1

0 15 14 13 12

2

1

0

7

6

5

4

3

2

1

0

SI

CS

32 33 34 35 36 37 38 39

Data Byte 2

41 42 43 44 45 46 47

Data Byte 3

40

7

SCK

SI

Data Byte n (128 max)

7

6

5

4

3

2

1

0

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Preliminary

DS22021B-page 9

25AA512/25LC512

• Power-up

2.3

Write Enable (WREN) and Write

Disable (WRDI)

• WRDIinstruction successfully executed

• WRSRinstruction successfully executed

• WRITEinstruction successfully executed

• PEinstruction successfully executed

• SEinstruction successfully executed

• CEinstruction successfully executed

The 25XX512 contains a write enable latch.

See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WRENinstruction will set the

latch, and the WRDIwill reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

FIGURE 2-4:

WRITE ENABLE SEQUENCE (WREN)

CS

SCK

SI

0

1

2

3

4

5

6

7

0

1

0

High-Impedance

SO

FIGURE 2-5:

WRITE DISABLE SEQUENCE (WRDI)

CS

0

1

2

3

4

5

6

7

SCK

0

1

0

1

0

SI

High-Impedance

SO

DS22021B-page 10

Preliminary

25AA512/25LC512

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the STATUS register. These commands are shown

in Figure 2-4 and Figure 2-5.

2.4

Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the STATUS register. The STATUS register

may be read at any time, even during a write cycle. The

STATUS register is formatted as follows:

TABLE 2-2:

STATUS REGISTER

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSRinstruction. These

bits are nonvolatile, and are shown in Table 2-3.

7

6

–

X

5

–

X

4

–

X

3

2

1

0

W/R

W/R W/R

R

WPEN

BP1 BP0 WEL WIP

See Figure 2-6 for the RDSRtiming sequence.

W/R = writable/readable. R = read-only.

The Write-In-Process (WIP) bit indicates whether the

25XX512 is busy with a write operation. When set to a

‘1’, a write is in progress, when set to a ‘0’, no write is

in progress. This bit is read-only.

FIGURE 2-6:

READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

SI

Instruction

0

1

0

1

Data from STATUS Register

High-Impedance

7

6

5

4

3

2

1

0

SO

Preliminary

DS22021B-page 11

25AA512/25LC512

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the STATUS register control the

programmable hardware write-protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pin is high or the WPEN

bit is low. When the chip is hardware write-protected,

only writes to nonvolatile bits in the STATUS register

are disabled. See Table 2-4 for a matrix of functionality

on the WPEN bit.

2.5

Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the STATUS

register as shown in Table 2-2. The user is able to

select one of four levels of protection for the array by

writing to the appropriate bits in the STATUS register.

The array is divided up into four segments. The user

has the ability to write-protect none, one, two or all four

of the segments of the array. The partitioning is

controlled as shown in Table 2-3.

See Figure 2-7 for the WRSRtiming sequence.

TABLE 2-3:

ARRAY PROTECTION

Array Addresses

Write-Protected

Array Addresses

Unprotected

BP1

BP0

none

All (Sectors 0, 1, 2 & 3)

(0000h-FFFFh)

0

Upper 1/4 (Sector 3)

(C000h-FFFFh)

Lower 3/4 (Sectors 0, 1 & 2)

(0000h-BFFFh)

0

1

Upper 1/2 (Sectors 2 & 3)

(8000h-FFFFh)

Lower 1/2 (Sectors 0 & 1)

(0000h-7FFFh)

0

1

All (Sectors 0, 1, 2 & 3)

(0000h-FFFFh)

none

FIGURE 2-7:

WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

15

0

SCK

SI

Instruction

Data to STATUS Register

7

6

5

4

3

2

0

1

High-Impedance

SO

DS22021B-page 12

Preliminary

25AA512/25LC512

2.6

Data Protection

2.7

Power-On State

The following protection has been implemented to

prevent inadvertent writes to the array:

The 25XX512 powers on in the following state:

• The device is in low-power Standby mode

(CS=1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

• CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

TABLE 2-4:

WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1)

WPEN

(SR bit 7)

WP

(pin 3)

Protected Blocks

Unprotected Blocks

STATUS Register

Protected

Writable

Protected

Writable

Protected

Writable

0

x

0

1

x

1

x

1

0 (low)

1 (high)

1

x = don’t care

Preliminary

DS22021B-page 13

25AA512/25LC512

2.8

PAGE ERASE

The PAGE ERASE instruction will erase all bits (FFh)

inside the given page. A Write Enable (WREN) instruc-

tion must be given prior to attempting a PAGE ERASE.

This is done by setting CS low and then clocking out

the proper instruction into the 25XX512. After all eight

bits of the instruction are transmitted, the CS must be

brought high to set the write enable latch.

CS must then be driven high after the last bit of the

address or the PAGE ERASE will not execute. Once

the CS is driven high the self-timed PAGE ERASE

cycle is started. The WIP bit in the STATUS register

can be read to determine when the PAGE ERASEcycle

is complete.

If a PAGE ERASE instruction is given to an address

that has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The PAGE ERASEinstruction is entered by driving CS

low, followed by the instruction code (Figure 2-8) and

two address bytes. Any address inside the page to be

erased is a valid address.

FIGURE 2-8:

PAGE ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

21 22 23

Instruction

16-bit Address

15 14 13 12

0

1

0

1

0

2

1

0

High-Impedance

SO

DS22021B-page 14

Preliminary

25AA512/25LC512

2.9

SECTOR ERASE

The SECTOR ERASE instruction will erase all bits

(FFh) inside the given sector. A Write Enable (WREN)

instruction must be given prior to attempting a SECTOR

ERASE. This is done by setting CS low and then clock-

ing out the proper instruction into the 25XX512. After

all eight bits of the instruction are transmitted, the CS

must be brought high to set the write enable latch.

CS must then be driven high after the last bit of the

address or the SECTOR ERASEwill not execute. Once

the CS is driven high the self-timed SECTOR ERASE

cycle is started. The WIP bit in the STATUS register

can be read to determine when the SECTOR ERASE

cycle is complete.

If a SECTOR ERASEinstruction is given to an address

that has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The SECTOR ERASE instruction is entered by driving

CS low, followed by the instruction code (Figure 2-9)

and two address bytes. Any address inside the sector

to be erased is a valid address.

See Table 2-3 for Sector Addressing.

FIGURE 2-9:

SECTOR ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

21 22 23

Instruction

16-bit Address

15 14 13 12

1

0

1

0

2

1

0

High-Impedance

SO

Preliminary

DS22021B-page 15

25AA512/25LC512

2.10 CHIP ERASE

The CHIP ERASEinstruction will erase all bits (FFh) in

the array. A Write Enable (WREN) instruction must be

given prior to executing a CHIP ERASE. This is done

by setting CS low and then clocking out the proper

instruction into the 25XX512. After all eight bits of the

instruction are transmitted, the CS must be brought

high to set the write enable latch.

The CS pin must be driven high after the eighth bit of

the instruction code has been given or the CHIP

ERASE instruction will not be executed. Once the CS

pin is driven high the self-timed CHIP ERASEinstruc-

tion begins. While the device is executing the CHIP

ERASEinstruction the WIP bit in the STATUS register

can be read to determine when the CHIP ERASE

instruction is complete.

The CHIP ERASEinstruction is entered by driving the

CS low, followed by the instruction code (Figure 2-10)

onto the SI line.

The CHIP ERASEinstruction is ignored if either of the

Block Protect bits (BP0, BP1) are not 0, meaning ¼,

½, or all of the array is protected.

FIGURE 2-10:

CHIP ERASE SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

SI

High-Impedance

SO

DS22021B-page 16

Preliminary

25AA512/25LC512

2.11 DEEP POWER-DOWN MODE

Deep Power-Down mode of the 25XX512 is its lowest

power consumption state. The device will not respond

to any of the Read or Write commands while in Deep

Power-Down mode, and therefore it can be used as an

additional software write protection feature.

All instructions given during Deep Power-Down mode

are ignored except the Read Electronic Signature

command (RDID). The RDID command will release

the device from Deep power-down and outputs the

electronic signature on the SO pin, and then returns

the device to Standby mode after delay (T_REL

)

The Deep Power-Down mode is entered by driving CS

low, followed by the instruction code (Figure 2-11) onto

the SI line, followed by driving CS high.

Deep Power-Down mode automatically releases at

device power-down. Once power is restored to the

device it will power-up in the Standby mode.

If the CS pin is not driven high after the eighth bit of the

instruction code has been given, the device will not

execute Deep power-down. Once the CS line is driven

high there is a delay (T_DP) before the current settles to

its lowest consumption.

FIGURE 2-11:

DEEP POWER-DOWN SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

0

1

SI

High-Impedance

SO

Preliminary

DS22021B-page 17

25AA512/25LC512

Release from Deep Power-Down mode and Read

Electronic Signature is entered by driving CS low,

followed by the RDID instruction code (Figure 2-12)

and then a dummy address of 16 bits (A15-A0). After

the last bit of the dummy address is clock in, the 8-bit

Electronic Signature is clocked out on the SO pin.

2.12 RELEASE FROM DEEP POWER-

DOWN AND READ ELECTRONIC

SIGNATURE

Once the device has entered Deep Power-Down

mode all instructions are ignored except the Release

from Deep Power-down and Read Electronic Signa-

ture command. This command can also be used when

the device is not in Deep power-down to read the

electronic signature out on the SO pin unless another

command is being executed such as Erase, Program

or Write Status Register.

After the signature has been read out at least once,

the sequence can be terminated by driving CS high.

The device will then return to Standby mode and will

wait to be selected so it can be given new instructions.

If additional clock cycles are sent after the electronic

signature has been read once, it will continue to output

the signature on the SO line until the sequence is

terminated.

FIGURE 2-12:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

0

1

2

3

4

5

6

7

8

9 10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

Instruction

16-bit Address

15 14 13 12

1

0

1

0

1

0

1

2

1

0

SI

Electronic Signature Out

High-Impedance

7

6

5

4

3

2

1

0

SO

0

1

0

1

0

1

Manufacturer’s ID = 0x29

Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure

the device will be taken out of Deep Power-Down mode. However, there is a delay T_RELthat occurs before the device

returns to Standby mode (I_CCS), as shown in Figure 2-13.

FIGURE 2-13:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

T_REL

0

1

2

3

4

5

6

7

SCK

SI

Instruction

1

0

1

0

1

0

1

High-Impedance

SO

DS22021B-page 18

Preliminary

25AA512/25LC512

The WP pin function is blocked when the WPEN bit in

the STATUS register is low. This allows the user to

install the 25XX512 in a system with WP pin grounded

and still be able to write to the STATUS register. The

WP pin functions will be enabled when the WPEN bit is

set high.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

Name

PIN FUNCTION TABLE

Pin Number

Function

3.4

Serial Input (SI)

CS

SO

1

2

3

4

5

6

7

8

Chip Select Input

Serial Data Output

Write-Protect Pin

Ground

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

WP

VSS

SI

3.5

Serial Clock (SCK)

Serial Data Input

Serial Clock Input

Hold Input

The SCK is used to synchronize the communication

between a master and the 25XX512. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

SCK

HOLD

VCC

Supply Voltage

3.1

Chip Select (CS)

3.6

Hold (HOLD)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

The HOLD pin is used to suspend transmission to the

25LC512 while in the middle of a serial sequence with-

out having to re-transmit the entire sequence over

again. It must be held high any time this function is not

being used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence.

The HOLD pin should be brought low while SCK is low,

otherwise the HOLD function will not be invoked until

the next SCK high-to-low transition. The 25LC512 must

remain selected during this sequence. The SI and SCK

levels are “don’t cares” during the time the device is

paused and any transitions on these pins will be

ignored. To resume serial communication, HOLD

should be brought high while the SCK pin is low, other-

wise serial communication will not be resumed until the

next SCK high-to-low transition.

3.2

Serial Output (SO)

The SO pin is used to transfer data out of the 25XX512.

During a read cycle, data is shifted out on this pin after

the falling edge of the serial clock.

3.3

Write-Protect (WP)

The SO line will tri-state immediately upon a high-to-

low transition of the HOLD pin, and will begin outputting

again immediately upon a subsequent low-to-high

transition of the HOLD pin, independent of the state of

SCK.

This pin is used in conjunction with the WPEN bit in the

STATUS register to prohibit writes to the nonvolatile

bits in the STATUS register. When WP is low and

WPEN is high, writing to the nonvolatile bits in the

STATUS register is disabled. All other operations

function normally. When WP is high, all functions,

including writes to the nonvolatile bits in the STATUS

register, operate normally. If the WPEN bit is set, WP

low during a STATUS register write sequence will

disable writing to the STATUS register. If an internal

write cycle has already begun, WP going low will have

no effect on the write.

Preliminary

DS22021B-page 19

25AA512/25LC512

4.0

4.1

PACKAGING INFORMATION

Package Marking Information

8-Lead DFN

Example:

XXXXXXX

T/XXXXX

YYWW

25LC512

I/MF

0728

1L7

e

3

NNN

Example:

25AA512

8-Lead PDIP

XXXXXXXX

T/XXXNNN

I/P

1L7

e

3

0728

YYWW

Example:

8-Lead SOIC

25LC512I

XXXXXXXT

e

3

SN 0728

XXXXYYWW

1L7

NNN

Example:

25LC512

8-Lead SOIJ

XXXXXXXX

T/XXXXXX

YYWWNNN

I/SM

07281L7

e3

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

Note:

For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard marking consists of Microchip part number, year code, week code, traceability code (facility

code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please

check with your Microchip Sales Office.

DS22021B-page 20

Preliminary

25AA512/25LC512

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

L

b

N

K

E

E2

EXPOSED PAD

NOTE 1

1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

A3

A1

NOTE 2

Units

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

1.27 BSC

0.85

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

D

0.01

Contact Thickness

Overall Length

Overall Width

0.20 REF

5.00 BSC

6.00 BSC

4.00

E

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

Contact-to-Exposed Pad

D2

E2

b

3.90

2.20

0.35

0.50

0.20

4.10

2.40

0.48

0.75

–

2.30

0.40

L

0.60

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-122B

Preliminary

DS22021B-page 21

25AA512/25LC512

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS22021B-page 22

Preliminary

25AA512/25LC512

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff

A2

A1

E

1.25

0.10

–

§

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

4.90 BSC

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057B

Preliminary

DS22021B-page 23

25AA512/25LC512

8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

1

2

e

b

α

c

φ

A2

A

β

A1

L

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

1.77

1.75

0.05

7.62

5.11

5.13

0.51

0°

–

2.03

1.98

0.25

8.26

5.38

5.33

0.76

8°

Molded Package Thickness

Standoff §

A2

A1

E

Overall Width

Molded Package Width

Overall Length

E1

D

L

Foot Length

Foot Angle

φ

c

Lead Thickness

Lead Width

0.15

0.36

–

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

–

15°

Notes:

1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

Microchip Technology Drawing C04-056B

DS22021B-page 24

Preliminary

25AA512/25LC512

APPENDIX A: REVISION HISTORY

Revision A

Original release.

Revision B (06/2007)

Revised Device Selection Table; Revised Features

section; Revised Table 1-1 DC Characteristics;

Revised Table 1-2 AC Characteristics; Replaced Pack-

age Drawings (Rev. AP); Revised Package Marking

(SOIC, SOIJ); Revised Product ID section.

Preliminary

DS22021B-page 25

25AA512/25LC512

NOTES:

DS22021B-page 26

Preliminary

25AA512/25LC512

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS22021B-page 27

25AA512/25LC512

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

25AA512/25LC512

DS22021B

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS22021B-page 28

Preliminary

25AA512/25LC512

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

X

–

Examples:

Tape & Reel

Package

Temp Range

a)

25AA512-I/SN = 512 Kbit, 1.8V Serial

EEPROM, Industrial temp., SOIC package

b)

25AA512T-I/SM = 512 Kbit, 1.8V Serial

EEPROM, Industrial temp., Tape & Reel, SOIJ

package

Device:

25AA512

25LC512

512 Kbit, 1.8V, 128-Byte Page SPI Serial EEPROM

512 Kbit, 2.5V, 128-Byte Page SPI Serial EEPROM

c)

25AA512T-I/MF = 512 Kbit, 1.8V Serial

EEPROM, Industrial temp., Tape & Reel, DFN

package

Tape & Reel:

Blank

T

=

Standard packaging (tube)

Tape & Reel

d)

e)

f)

25LC512-I/SM = 512 Kbit, 2.5V Serial

EEPROM, Industrial temp., SOIJ package

Temperature

Range:

I

E

=

-40°C to+85°C

-40°C to+125°C

25LC512-I/P = 512 Kbit, 2.5V Serial EEPROM,

Industrial temp., P-DIP package

25LC512T-E/MF

= 512 Kbit, 2.5V Serial

Package:

MF

P

SN

=

Micro Lead Frame (6 x 5 mm body), 8-lead

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

EEPROM, Extended temp., Tape & Reel, DFN

package

Preliminary

DS22021B-page 29

25AA512/25LC512

NOTES:

DS22021B-page 30

Preliminary

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Preliminary

DS22021B-page 31

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS22021B-page 32

Preliminary


型号：	25AA512T-E/P
厂家：	MICROCHIP
描述：	512 Kbit SPI Bus Serial EEPROM 512 Kbit的SPI总线串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总32页 (文件大小：602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

25AA512T-E/P [MICROCHIP]

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