首页 > 存储 > EEPROM > 25C160TE/SN

25C160TE/SN

更新时间：2024-10-29 12:58:29

品牌：MICROCHIP

描述：2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8

PDF下载

中文翻译

PCB计价

概述
规格参数
数据手册

如果您发现信息不准确，欢迎纠错

25C160TE/SN 概述

2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8 EEPROM

25C160TE/SN 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.15
最大时钟频率 (fCLK)：	3 MHz	数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
内存密度：	16384 bit	内存集成电路类型：	EEPROM
内存宽度：	8	湿度敏感等级：	1
功能数量：	1	端子数量：	8
字数：	2048 words	字数代码：	2000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	2KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
串行总线类型：	SPI	最大待机电流：	0.000001 A
子类别：	EEPROMs	最大压摆率：	0.005 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3.91 mm
最长写入周期时间 (tWC)：	5 ms	写保护：	HARDWARE/SOFTWARE
Base Number Matches：	1

25C160TE/SN 数据手册

通过下载25C160TE/SN数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载

25C080/160

8K/16K 5.0V SPI Bus Serial EEPROM

FEATURES

PACKAGE TYPES

• SPI modes 0,0 and 1,1

• 3 MHz Clock Rate

• Single 5V supply

PDIP

VCC

• Low Power CMOS Technology

- Max Write Current: 5 mA

- Read Current: 1.0 mA

- Standby Current: 1 µA typical

• Organization

HOLD

VSS

SCK

- 1024 x 8 for 25C080

- 2048 x 8 for 25C160

• 16 Byte Page

• Self-timed ERASE and WRITE Cycles

• Sequential Read

• Block Write Protection

- Protect none, 1/4, 1/2, or all of Array

• Built-in Write Protection

- Power On/Off Data Protection Circuitry

- Write Latch

SOIC

VCC

HOLD

- Write Protect Pin

• High Reliability

VSS

SCK

- Endurance: 10M cycles (guaranteed)

- Data Retention: >200 years

- ESD protection: >4000 V

• 8-pin PDIP/SOIC Packages

• Temperature ranges supported

- Commercial (C):

- Industrial (I):

- Automotive (E):

0°C to +70°C

-40°C to +85°C

-40˚C to +125˚C

BLOCK DIAGRAM

Status

HV Generator

DESCRIPTION

The Microchip Technology Inc. 25C080/160 are 8K and

16K bit Serial Electrically Erasable PROMs. The mem-

ory is accessed via a simple Serial Peripheral Interface

(SPI) compatible serial bus. The bus signals required

are a clock input (SCK) plus separate data in (SI) and

data out (SO) lines. Access to the device is controlled

through a chip select (CS) input, allowing any number

of devices to share the same bus.

EEPROM

Array

Memory

Control

Logic

I/O Control

Logic

Dec

Page Latches

Y Decoder

There are two other inputs that provide the end user

with additional ﬂexibility. Communication to the device

can be paused via the hold pin (HOLD). While the

device is paused, transitions on its inputs will be

ignored, with the exception of chip select, allowing the

host to service higher priority interrupts. Also write

operations to the Status Register can be disabled via

the write protect pin (WP).

SCK

HOLD

Sense Amp.

R/W Control

Vcc

Vss

SPI is a trademark of Motorola.

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 1

This document was created with FrameMaker 4 0 4

25C080/160

FIGURE 1-1: AC TEST CIRCUIT

1.0

ELECTRICAL

CHARACTERISTICS

Vcc

1.1

Maximum Ratings*

2.25 K

VCC........................................................................ 7.0V

All inputs and outputs w.r.t. VSS......-0.6V to VCC +1.0V

Storage temperature .............................-65˚C to 150˚C

Ambient temperature under bias...........-65˚C to 125˚C

Soldering temperature of leads (10 seconds) ...+300˚C

ESD protection on all pins...................................... 4kV

1.8 K

100 pF

*Stresses above those listed under ‘Maximum ratings’ may

cause permanent damage to the device.This is a stress rating

only and functional operation of the device at those or any

other conditions above those indicated in the operational list-

ings of this speciﬁcation is not implied. Exposure to maximum

rating conditions for extended period of time may affect device

reliability

1.2

AC Test Conditions

AC Waveform:

VLO = 0.2V

VHI = Vcc - 0.2V

VHI = 4.0V

(Note 1)

(Note 2)

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

Timing Measurement Reference Level

Chip Select Input

Serial Data Output

Serial Data Input

Serial Clock Input

Write Protect Pin

Ground

Input

0.5 VCC

Output

SCK

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

VSS

VCC

HOLD

Supply Voltage

Hold Input

TABLE 1-2:

DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.

VCC = 4.5V to 5.5V

Commercial (C): Tamb = 0°C to +70°C

Industrial (I):

Tamb = -40°C to +85°C

Automotive (E): Tamb = -40˚C to +125˚C

Parameter

Symbol

Min

Max

Units

Test Conditions

High level input voltage

Low level input voltage

Low level output voltage

High level output voltage

Input leakage current

Output leakage current

VIH1

VIL1

VOL

VOH

ILI

2.0

-0.3

VCC+1

0.8

0.4

—

IOL=2.1 mA

VCC-0.5

-10

IOH=-400 µA

µA

CS=VIH, VIN=Vss to VCC

ILO

-10

CS=VIH, V

=Vss to VCC

OUT

Internal Capacitance

(all inputs and outputs)

CINT

—

Tamb=25˚C, FCLK=3.0 MHz,

VCC=5.5V (Note)

Operating Current

ICC write

—

VCC=5.5V

ICC READ

—

500

µA

VCC=5.5V; 3 MHz

VCC=5.5V; 2 MHz

Standby Current

ICCS

—

µA

CS=VCC=5.5V; Vin=0V or VCC

Note:

This parameter is periodically sampled and not 100% tested.

DS21147F-page 2

Preliminary

1996 Microchip Technology Inc.

25C080/160

FIGURE 1-2: SERIAL INPUT TIMING

t_CSD

t_CLD

t_R

t_CSS

t_F

t_CSH

SCK

t_SU

t_HD

MSB in

LSB in

high impedance

FIGURE 1-3: SERIAL OUTPUT TIMING

t_CSH

t_HI

t_LO

SCK

t_V

t_DIS

LSB out

t_HO

MSB out

don’t care

FIGURE 1-4: HOLD TIMING

t_HH

t_HS

t_HH

SCK

t_HZ

t_HV

high impedance

don’t care

t_SU

n+2

n+1

n-1

n+1

n-1

HOLD

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 3

25C080/160

TABLE 1-3:

AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted.

VCC = 4.5V to 5.5V

Commercial (C): Tamb = 0° to +70°C

Industrial (I):

Tamb = -40° to +85°C

Automotive (E): Tamb = -40˚C to +125˚C

Symbol

Parameter

Clock Frequency

Min

Max

Units

Test Conditions

fSCK

tCSS

tCSH

tCSD

tSU

tHD

—

100

250

—

MHz

µs

CS Setup Time

CS Hold Time

CS Disable Time

Data Setup Time

Data Hold Time

CLK Rise Time

CLK Fall Time

—

(Note 1)

—

tHI

Clock High Time

Clock Low Time

Clock Delay Time

150

—

150

tLO

tCLD

Output Valid from

Clock Low

—

tHO

tDIS

tHS

tHH

tHZ

tHV

tWC

—

Output Hold Time

—

200

—

Output Disable Time

HOLD Setup Time

—

(Note 1)

100

—

HOLD Hold Time

HOLD Low to Output High-Z

HOLD High to Output Valid

Internal Write Cycle Time

Endurance

(Note 1)

(Note 2)

10M

—

E/W Cycles 25°C, Vcc = 5.0V, Block Mode

(Note 3)

Note 1: This parameter is periodically sampled and not 100% tested.

2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write

cycle is complete.

3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS21147F-page 4

Preliminary

1996 Microchip Technology Inc.

25C080/160

the WREN or WRDI commands regardless of the state

of write protection on the status register.This bit is read

only.

2.0

PRINCIPLES OF OPERATION

The 25C080/160 is an 1024/2048 byte EEPROM

designed to interface directly with the Serial Peripheral

Interface (SPI) port of many of today’s popular micro-

controller families, including Microchip’s midrange

PIC16CXX microcontrollers. It may also interface with

microcontrollers that do not have a built-in SPI port by

using discrete I/O lines programmed properly with soft-

ware.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write protected. These bits

are set by the user issuing the WRSR instruction.

These bits are non-volatile.

The Write Protect Enable (WPEN) bit is a non-volatile

bit that is available as an enable bit for the WP pin. The

Write Protect (WP) pin and the Write Protect Enable

(WPEN) bit in the status register control the program-

mable hardware write protect feature. Hardware write

protection is enabled when WP pin is low and the

WPEN bit is high. Hardware write protection is disabled

when either the WP pin is high or the WPEN bit is low.

When the chip is hardware write protected, only writes

to non-volatile bits in the status register are disabled.

See Table 2-2 for matrix of functionality on the WPEN

bit and Figure 2-1 for a ﬂowchart of Table 2-2. See

Figure 3-5 for RDSR timing sequence.

The 25C080/160 contains an 8-bit instruction register.

The part is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation. If the WPEN bit in the status register is set,

the WP pin must be held high to allow writing to the non-

volatile bits in the status register.

Table 2-1 contains a list of the possible instruction bytes

and format for device operation. All instructions,

addresses and data are transferred MSB ﬁrst, LSB last.

Data is sampled on the ﬁrst rising edge of SCK after CS

goes low. If the clock line is shared with other peripheral

devices on the SPI bus, the user can assert the HOLD

input and place the 25C080/160 in ‘HOLD’ mode. After

releasing the HOLD pin, operation will resume from the

point when the HOLD was asserted.

TABLE 2-1:

INSTRUCTION SET

Instruction Instruction

Description

Name

Format

WREN

0000 0110 Set the write enable latch

(enable write operations)

0000 0100 Reset the write enable

latch (disable write opera-

tions)

WRDI

2.1

Write Enable (WREN) and Write

Disable (WRDI)

RDSR

WRSR

0000 0101 Read status register

0000 0001 Write status register (write

protect enable and block

write protection bits)

0000 0011 Read data from memory

array beginning at

The 25C080/160 contains a write enable latch. This

latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.The following is

a list of conditions under which the write enable latch

will be reset:

READ

selected address

0000 0010 Write data to memory

array beginning at

• Power-up

WRITE

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

selected address

2.2

Read Status Register (RDSR)

The RDSR instruction provides access to the status

even during a write cycle. The status register is format-

ted as follows:

WPEN

BP1

BP0

WEL

WIP

The Write-In-Process (WIP) bit indicates whether the

25C080/160 is busy with a write operation.When set to

a ‘1’ a write is in progress, when set to a ‘0’ no write is

in progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When set to a ‘1’ the latch

allows writes to the array and status register, when set

to a ‘0’ the latch prohibits writes to the array and status

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 5

25C080/160

TABLE 2-2:

WRITE PROTECT FUNCTIONALITY MATRIX

WPEN

WEL

Protected Blocks

Unprotected Blocks

Status Register

Low

High

Protected

Writable

Protected

Writable

Protected

Writable

Protected

Writable

Protected

Writable

FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART

CS Returns High

Write

to Status

Reg?

Write

To other

Commands

to array?

Yes

WEL = 1?

Yes

WEL = 1?

Yes

Write to the

Unprotected Block

WP is low?

Yes

Do not write to

Array

WPEN = 1?

Yes

Write to

Status Register

Do not write to

Status Register

From other

Commands

Continue

DS21147F-page 6

Preliminary

1996 Microchip Technology Inc.

25C080/160

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set.

2.3

Write Status Register (WRSR)

The WRSR instruction allows the user to select one of

four protection options for the array by writing to the

appropriate bits in the status register. The array is

divided up into four segments. The user has the ability

to write protect none, one, two, or all four of the seg-

ments of the array.The partitioning is controlled as illus-

trated in table below. See Figure 3-6 for WRSR timing

sequence.

Once the write enable latch is set, the user may pro-

ceed by setting the CS low, issuing a write instruction,

followed by the 16-bit address, with the ﬁve (25C160) or

six (25C080) MSBs of the address being don’t care bits,

and then the data to be written. Up to 16 bytes of data

can be sent to the 25C080/160 before a write cycle is

necessary. The only restriction is that all of the bytes

must reside in the same page. A page address begins

with XXXX XXXX XXXX 0000 and ends with XXXX

XXXX XXXX 1111. If the internal address counter

reaches XXXX XXXX XXXX 1111 and the clock contin-

ues, the counter will roll back to the ﬁrst address of the

page and overwrite any data in the page that may have

been written.

TABLE 2-3:

BP1

ARRAY PROTECTION

Array Addresses

Write Protected

BP0

none

upper 1/4

300h-3FFh for 25C080

600h-7FFh for 25C160

upper 1/2

200h-3FFh for 25C080

400h-7FFh for 25C160

all

For the data to be actually written to the array, the CS

must be brought high after the least signiﬁcant bit (D0)

of the n data byte has been clocked in. If CSis brought

high at any other time, the write operation will not be

completed. See Figure 3-3 and Figure 3-4 for more

detailed illustrations on the byte write sequence and the

page write sequence, respectively.

000h-3FFh for 25C080

000h-7FFh for 25C160

3.0

DEVICE OPERATION

While the write is in progress, the status register may

be read to check the status of the WPEN, WIP, WEL,

BP1, and BP0 bits. A read attempt of a memory array

location will not be possible during a write cycle. When

a write cycle is completed, the write enable latch is

reset

3.1

Clock and Data Timing

Data input on the SI pin is latched on the rising edge of

SCK. Data is output on the SO pin after the falling edge

of SCK.

3.4

Data Protection

3.2

Read Sequence

The following protection has been implemented to pre-

vent inadvertent writes to the array:

The part is selected by pulling CS low. The 8-bit read

instruction is transmitted to the 25C080/160 followed by

the 16-bit address, with the ﬁve (25C160) or six

(25C080) MSBs of the address being don’t care bits.

After the correct read instruction and address are sent,

the data stored in the memory at the selected address

is shifted out on the SO pin. The data stored in the

memory at the next address can be read sequentially

by continuing to provide clock pulses. The internal

address pointer is automatically incremented to the

next higher address after each byte of data is shifted

out. When the highest address is reached ($3FF for

25C080, $7FF for 25C160) the address counter rolls

over to address $000 allowing the read cycle to be con-

tinued indeﬁnitely. The read operation is terminated by

setting CS high (see Figure 3-1).

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set

the write enable latch.

• After a successful byte write, page write, or status

• CS must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle

is ignored and programming is continued.

3.5

Power On State

The 25C080/160 powers on in the following state:

• The device is in low power standby mode (CS=1).

• The write enable latch is reset.

3.3

Write Sequence

• SO is in high impedance state.

• A low level on CS is required to enter active state.

Prior to any attempt to write data to the 25C080/160,

the write enable latch must be set by issuing the WREN

instruction (Figure 3-2). This is done by setting CS low

and then clocking the proper instruction into the

25C080/160. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 7

25C080/160

FIGURE 3-1: READ SEQUENCE

10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

instruction

16 bit address

1 15 14 13 12

data out

high impedance

FIGURE 3-2: WRITE ENABLE SEQUENCE

SCK

high impedance

FIGURE 3-3: WRITE SEQUENCE

9 10 11

21 22 23 24 25 26 27 28 29 30 31

data byte

SCK

instruction

16 bit address

15 14 13 12

high impedance

DS21147F-page 8

Preliminary

1996 Microchip Technology Inc.

25C080/160

FIGURE 3-4: PAGE WRITE SEQUENCE

9 10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

instruction

16 bit address

0 15 14 13 12

data byte 1

32 33 34 35 36 37 38 39

data byte 2

41 42 43 44 45 46 47

data byte 3

SCK

data byte n (16 max)

FIGURE 3-5: READ STATUS REGISTER SEQUENCE

10 11 12 13 14 15

SCK

instruction

data from status register

high impedance

FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE

10 11 12 13 14 15

SCK

instruction

data to status register

high impedance

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 9

25C080/160

4.5

Write Protect (WP)

4.0

PIN DESCRIPTIONS

This pin is used in conjunction with the WPEN bit in the

status register to prohibit writes to the non-volatile bits

in the status register. When WP is low and WPEN is

high, writing to the non-volatile bits in the status register

is disabled. All other operations function normally.

When WP is high, all functions, including writes to the

non-volatile bits in the status register operate normally.

If the WPEN bit is set WP low during a status register

write sequence will disable writing to the status register.

If an internal write cycle has already begun, WP going

low will have no effect on the write.

4.1

Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into standby mode.

However, a programming cycle which is already in

progress will be completed, regardless of the CS input

signal. If CS is brought high during a program cycle, the

device will go into standby mode as soon as the pro-

gramming cycle is complete. As soon as the device is

deselected, SO goes to the high impedance state,

allowing multiple parts to share the same SPI bus. A

low to high transition on CS after a valid write sequence

is what initiates an internal write cycle. After power-up,

a low level on CS is required prior to any sequence

being initiated.

The WP pin function is blocked when the WPEN bit in

the status register is low. This allows the user to install

the 25C080/160 in a system with WP pin grounded and

still be able to write to the status register. The WP pin

functions will be enabled when the WPEN bit is set

high.

4.2

Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses, and data to be written

to the memory. Input is latched on the rising edge of the

serial clock.

4.6

Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25C080/160 while in the middle of a serial sequence

without having to re-transmit the entire sequence over

at a later time. It should be held high any time this func-

tion is not being used. Once the device is selected and

a serial sequence is underway, the HOLD pin may be

pulled low to pause further serial communication with-

out resetting the serial sequence. The HOLD pin must

be brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high to

low transition. The 25C080/160 must remain selected

during this sequence. The SI, SCK, and SO pins are in

a high impedance state during the time the part is

paused and transitions on these pins will be ignored.To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial commu-

nication will not resume.

It is possible for the SI pin and the SO pin to be tied

together. With SI and SO tied together, two way com-

munication of data can occur using only one microcon-

troller I/O line.

4.3

Serial Output (SO)

The SO pin is used to transfer data serially out of the

25C080/160. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

It is possible for the SI pin and the SO pin to be tied

together. With SI and SO tied together, two way com-

munication of data can occur using only one microcon-

troller I/O line.

4.4

Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25C080/160. Instructions,

addresses, or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

DS21147F-page 10

Preliminary

1996 Microchip Technology Inc.

25C080/160

25C080/160 Product Identiﬁcation System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

25C080/160

–

Package:

P = Plastic DIP (300 mil body), 8 lead

SN = Plastic SOIC (150 mil body), 8 lead

Temperature

Range:

Blank = 0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Device:

SPI Bus Serial EEPROM

25C080/160

25C080T/160T

SPI Bus Serial EEPROM (Tape and Reel)

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce (see next page)

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

1996 Microchip Technology Inc.

Preliminary

DS21147F-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

Corporate Ofﬁce

ASIA/PACIFIC

Hong Kong

EUROPE

United Kingdom

Microchip Technology Inc.

Microchip Technology

RM 3801B, Tower Two

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T. Hong Kong

Tel: 852 2 401 1200 Fax: 852 2 401 3431

India

Microchip Technology

No. 6, Legacy, Convent Road

Bangalore 560 025 India

Tel: 91 80 526 3148 Fax: 91 80 559 9840

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire SL8 5AJ

Tel: 44 1628 850303 Fax: 44 1628 850178

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602 786-7200 Fax: 602 786-7277

Technical Support: 602 786-7627

Web: http://www.microchip.com

France

Atlanta

Arizona Microchip Technology SARL

Zone Industrielle de la Bonde

2 Rue du Buisson aux Fraises

91300 Massy - France

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770 640-0034 Fax: 770 640-0307

Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Boston

Korea

Germany

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508 480-9990 Fax: 508 480-8575

Microchip Technology

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Shanghai

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Muenchen, Germany

Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Chicago

Italy

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 708 285-0071 Fax: 708 285-0075

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 972 991-7177 Fax: 972 991-8588

Dayton

Microchip Technology Inc.

Suite 150

Arizona Microchip Technology SRL

Centro Direzionale Colleone Pas Taurus 1

Viale Colleoni 1

20041 Agrate Brianza

Milan Italy

Microchip Technology

Unit 406 of Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hongiao District

Shanghai, Peoples Republic of China

Tel: 86 21 6275 5700

Fax: 011 86 21 6275 5060

Singapore

Microchip Technology

200 Middle Road

#10-03 Prime Centre

Singapore 188980

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan, R.O.C

Microchip Technology

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

Tel: 39 39 6899939 Fax: 39 39 689 9883

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Two Prestige Place

Miamisburg, OH 45342

Tel: 513 291-1654 Fax: 513 291-9175

Tel: 81 45 471 6166 Fax: 81 45 471 6122

11/7/96

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 714 263-1888 Fax: 714 263-1338

NewYork

Microchip Technology Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 436-7950 Fax: 408 436-7955

Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada

Tel: 905 405-6279 Fax: 905 405-6253

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-

sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement

of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-

rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.The Microchip logo and

DS21147F-page 12

Preliminary

1996 Microchip Technology Inc.

25C160TE/SN 相关器件

型号	制造商	描述	价格	文档
25C160TESN	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8	获取价格
25C160TI/SN	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8	获取价格
25C160TIOT	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO5, SOT-23, 5 PIN	获取价格
25C160TISN	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8	获取价格
25C160TOT	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO5, SOT-23, 5 PIN	获取价格
25C160TSN	MICROCHIP	暂无描述	获取价格
25C160TST	MICROCHIP	2K X 8 SPI BUS SERIAL EEPROM, PDSO8, TSSOP-8	获取价格
25C22X58SC	ALTECH	Electric Fuse,	获取价格
25C256	CATALYST	128K/256K-Bit SPI Serial CMOS E2PROM	获取价格
25C320	MICROCHIP	32K 5.0V SPI Bus Serial EEPROM	获取价格