25LC040-E/SN [MICROCHIP]
4K SPI ⑩ Bus Serial EEPROM; 4K SPI总线⑩串行EEPROM型号: | 25LC040-E/SN |
厂家: | MICROCHIP |
描述: | 4K SPI ⑩ Bus Serial EEPROM |
文件: | 总22页 (文件大小:402K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Not recommended for new designs –
Please use 25AA040A or 25LC040A.
25AA040/25LC040/25C040
4K SPI Bus Serial EEPROM
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
25AA040
25LC040
25C040
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
I
I
Package Types
I,E
PDIP
CS
1
8
VCC
Features:
SO
2
3
7
6
HOLD
SCK
• Low-power CMOS technology:
- Write current: 3 mA, typical
- Read current: 500 μA, typical
- Standby current: 500 nA, typical
• 512 x 8-bit organization
• 16 byte page
WP
VSS
4
5
SI
SOIC
CS
1
8
VCC
SO
2
3
7
6
HOLD
SCK
• Write cycle time: 5 ms max.
• Self-timed Erase and Write cycles
• Block write protection:
WP
VSS
4
5
SI
TSSOP
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
1
2
8
HOLD
VCC
SCK
SI
7
6
5
3
4
CS
SO
VSS
WP
- Write-protect pin
• Sequential read
• High reliability:
Block Diagram
- Endurance: 1M cycles
STATUS
Register
HV Generator
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
- Industrial (I):
- Automotive (E) (25C040):
-40°C to +85°C
EEPROM
Array
Memory
Control
Logic
-40°C to +125°C
I/O Control
Logic
XDEC
Description:
Page
Latches
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040*) is a 4 Kbit serial Electrically
Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices.
© 2006 Microchip Technology Inc.
DS21204E-page 1
25AA040/25LC040/25C040
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
ESD protection on all pins......................................................................................................................................... 4 KV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
VCC ≥ 2.7V (Note)
D001
D002
D003
D004
D005
D006
D007
VIH1
High-level input
voltage
2.0
0.7 VCC
-0.3
VCC+1
VCC+1
0.8
V
V
V
V
V
V
V
VIH2
VIL1
VIL2
VOL
VOL
VOH
VCC< 2.7V (Note)
VCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
IOL = 2.1 mA
Low-level input
voltage
-0.3
0.3 VCC
0.4
Low-level output
voltage
—
—
0.2
IOL = 1.0 mA, VCC < 2.5V
IOH =-400 μA
High-level output
voltage
VCC -0.5
—
D008
D009
ILI
Input leakage current
—
—
±1
±1
μA
μA
CS = VCC, VIN = VSS TO VCC
CS = VCC, VOUT = VSS TO VCC
ILO
Output leakage
current
D010
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
D011
D012
D013
ICC Read Operating Current
—
—
1
500
mA
μA
VCC = 5.5V; FCLK = 3.0 MHz; SO = Open
VCC = 2.5V; FCLK = 2.0 MHz; SO = Open
ICC Write
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
ICCS
Standby Current
—
—
5
1
μA
μA
CS = VCC = 5.5V, Inputs tied to VCC or
VSS
CS = VCC = 2.5V, Inputs tied to VCC or
VSS
Note:
This parameter is periodically sampled and not 100% tested.
DS21204E-page 2
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
VCC = 4.5V to 5.5V (25C040 only)
AC CHARACTERISTICS
Param
Sym.
No.
Characteristic
Min.
Max.
Units
Test Conditions
1
2
3
FCLK
TCSS
TCSH
Clock Frequency
—
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
CS Setup Time
CS Hold Time
100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
4
5
TCSD
TSU
CS Disable Time
Data Setup Time
500
—
ns
—
30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
6
THD
Data Hold Time
50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
7
8
9
TR
TF
CLK Rise Time
CLK Fall Time
Clock High Time
—
—
2
2
μs
μs
(Note 1)
(Note 1)
THI
150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
10
TLO
Clock Low Time
150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
11
12
13
TCLD
TCLE
TV
Clock Delay Time
50
50
—
—
ns
ns
—
—
Clock Enable Time
Output Valid from Clock Low
—
—
—
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
14
15
THO
TDIS
Output Hold Time
0
—
ns
(Note 1)
Output Disable Time
—
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
16
17
18
19
THS
THH
THZ
THV
HOLD Setup Time
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Hold Time
100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
HOLD Low to Output High-Z
HOLD High to Output Valid
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
20
21
TWC
—
Internal Write Cycle Time
Endurance
—
5
ms
—
1M
—
E/W
(Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.
© 2006 Microchip Technology Inc.
DS21204E-page 3
25AA040/25LC040/25C040
FIGURE 1-1:
HOLD TIMING
CS
17
17
16
16
SCK
SO
18
19
High-impedance
n
n + 2
n + 1
n
n - 1
5
Don’t Care
n
n + 2
n + 1
n
n - 1
SI
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
12
11
2
7
3
8
Mode 1,1
Mode 0,0
SCK
SI
5
6
MSB in
LSB in
High-impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
3
9
10
Mode 1,1
Mode 0,0
SCK
13
15
ISB out
14
MSB out
SO
SI
Don’t Care
DS21204E-page 4
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
TABLE 1-3:
AC Waveform:
VLO = 0.2V
AC TEST CONDITIONS
FIGURE 1-4:
AC TEST CIRCUIT AC
VCC
—
VHI = VCC - 0.2V
(Note 1)
(Note 2)
2.25 KΩ
1.8 KΩ
VHI = 4.0V
Timing Measurement Reference Level
Input
SO
0.5 VCC
0.5 VCC
100 pF
Output
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
© 2006 Microchip Technology Inc.
DS21204E-page 5
25AA040/25LC040/25C040
2.4
Serial Input (SI)
2.0
PIN DESCRIPTIONS
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.5
Serial Clock (SCK)
Name
PDIP
SOIC
TSSOP
Description
The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
CS
SO
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
Chip Select Input
Serial Data Output
Write-Protect Pin
Ground
WP
VSS
SI
Serial Data Input
Serial Clock Input
Hold Input
2.6
Hold (HOLD)
SCK
HOLD
VCC
The HOLD pin is used to suspend transmission to the
25XX040 while in the middle of a serial sequence
without having to retransmit the entire sequence again
at a later time. It must be held high any time this func-
tion is not being used. Once the device is selected and
a serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication
without resetting the serial sequence. The HOLD pin
must be brought low while SCK is low, otherwise the
HOLD function will not be invoked until the next SCK
high-to-low transition. The 25XX040 must remain
selected during this sequence. The SI, SCK and SO
pins are in a high-impedance state during the time the
part is paused and transitions on these pins will be
ignored. To resume serial communication, HOLD must
be brought high while the SCK pin is low, otherwise
serial communication will not resume. Lowering the
HOLD line at any time will tri-state the SO line.
Supply Voltage
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes into the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25XX040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
Write-Protect (WP)
This pin is a hardware write-protect input pin. When
WP is low, all writes to the array or STATUS register
are disabled, but any other operation functions
normally. When WP is high, all functions, including
nonvolatile writes operate normally. WP going low at
any time will reset the write enable latch and inhibit
programming, except when an internal write has
already begun. If an internal write cycle has already
begun, WP going low will have no effect on the write.
See Table 3-3 for Write-Protect Functionality Matrix.
DS21204E-page 6
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
3.3
Write Sequence
3.0
3.1
FUNCTIONAL DESCRIPTION
Principles of Operation
Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX040. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire operation.
The WP pin must be held high to allow writing to the
memory array.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the address, and then the data
to be written. Keep in mind that the Most Significant
address bit (A8) is included in the instruction byte. Up
to 16 bytes of data can be sent to the 25XX040 before
a write cycle is necessary. The only restriction is that all
of the bytes must reside in the same page. A page
address begins with XXXX0000and ends with XXXX
1111. If the internal address counter reaches XXXX
1111and the clock continues, the counter will roll back
to the first address of the page and overwrite any data
in the page that may have been written.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The Most
Significant address bit (A8) is located in the instruction
byte. All instructions, addresses, and data are
transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX040 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit READ
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin. The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal Address Pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 3-1).
TABLE 3-1:
INSTRUCTION SET
Instruction Name
READ
Instruction Format
Description
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read STATUS register
0000 A8011
0000 A8010
0000 0100
0000 0110
0000 0101
0000 0001
WRITE
WRDI
WREN
RDSR
WRSR
Write STATUS register
Note:
A8 is the 9th address bit necessary to fully address 512 bytes.
© 2006 Microchip Technology Inc.
DS21204E-page 7
25AA040/25LC040/25C040
FIGURE 3-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
Instruction
A8
Lower Address Byte
0
0
0
0
0
1
1
A7
6
5
4
3
2
1
A0
Don’t Care
Data Out
High-impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-2:
BYTE WRITE SEQUENCE
CS
TWC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Data Byte
Instruction
A8
Lower Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
A7
6
5
4
3
2
1
A0
SI
High-impedance
SO
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
SCK
Instruction
A8
Lower Address Byte
Data Byte 1
3
0
0
0
0
0
1
0
A7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
SI
CS
25 26 27 28 29 30 31 32
Data Byte 2
34 35 36 37 38 39 40
Data Byte 3
33
7
SCK
SI
Data Byte n (16 max)
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DS21204E-page 8
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
The following is a list of conditions under which the
write enable latch will be reset:
3.4
Write Enable (WREN) and Write
Disable (WRDI)
• Power-up
The 25XX040 contains a write enable latch.
See
• WRDIinstruction successfully executed
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WRENinstruction will set the
latch, and the WRDIwill reset the latch.
• WRSRinstruction successfully executed
• WRITEinstruction successfully executed
• WP line is low
FIGURE 3-4:
WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
High-impedance
SO
FIGURE 3-5:
WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-impedance
SO
© 2006 Microchip Technology Inc.
DS21204E-page 9
25AA040/25LC040/25C040
3.5
Read Status Register (RDSR)
3.6
Write Status Register (WRSR)
The RDSRinstruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The WRSRinstruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
illustrated in Table 3-2.
7
6
5
4
3
2
1
0
X
X
X
X
BP1
BP0
WEL
WIP
The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
See Figure 3-7 for WRSRtiming sequence.
TABLE 3-2:
BP1
ARRAY PROTECTION
Array Addresses
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘0’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the
STATUS register. This bit is read-only.
BP0
Write-Protected
none
0
0
0
1
upper 1/4
(0180h-01FFh)
upper 1/2
(0100h-01FFh)
1
1
0
1
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSRinstruction. These
bits are nonvolatile.
all
(0000h-01FFh)
See Figure 3-6 for RDSRtiming sequence.
FIGURE 3-6:
READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
Instruction
0
0
0
0
0
1
0
1
Data from STATUS register
High-impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-7:
WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Data to STATUS register
SCK
SI
Instruction
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
High-impedance
SO
DS21204E-page 10
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
3.7
Data Protection
3.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25XX040 powers on in the following state:
• The device is in low-power Standby mode
• The write enable latch is reset on power-up
(CS= 1)
• A write enable instruction must be issued to set
the write enable latch
• The write enable latch is reset
• SO is in high-impedance state
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• A low level on CS is required to enter active state
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
• The write enable latch is reset when the WP pin is
low
TABLE 3-3:
WP
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
Protected Blocks
Protected
Unprotected Blocks
Protected
STATUS Register
Protected
Low
X
0
1
High
Protected
Protected
Protected
High
Protected
Writable
Writable
© 2006 Microchip Technology Inc.
DS21204E-page 11
25AA040/25LC040/25C040
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
25AA040
I/P 1L7
XXXXXXXX
XXXXXNNN
e
3
0601
YYWW
8-Lead SOIC (150 mil)
Example:
25AA040I/
XXXXXXXX
e
3
XXXXYYWW
SN
0601
NNN
1L7
Example:
8-Lead TSSOP
XXXX
YYWW
5A4X
0601
NNN
1L7
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS21204E-page 12
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please
see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.170
3.56
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.130
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
DS21204E-page 13
25AA040/25LC040/25C040
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please
see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
2
1
B
n
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21204E-page 14
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please
see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
e
D
2
1
n
b
α
c
ϕ
A
β
A2
L
A1
Units
Dimension Limits
MILLIMETERS*
INCHES
NOM
MIN
MAX
MIN
NOM
8
0.65 BSC
MAX
Number of Pins
Pitch
n
e
A
8
.026 BSC
Overall Height
–
–
1.20
–
–
.047
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Molded Package Length
Foot Length
A2
A1
E
E1
D
L
0.80
0.05
1.00
1.05
0.15
.031
.002
.039
.041
.006
–
6.40 BSC
4.40
–
.252 BSC
.173
4.30
2.90
0.45
0°
4.50
3.10
0.75
8°
.169
.114
.018
0°
.177
.122
.030
8°
3.00
0.60
.118
.024
Foot Angle
ϕ
–
–
Lead Thickness
Lead Width
c
b
0.09
0.19
–
–
0.20
0.30
.004
.007
–
–
.008
.012
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12° REF
12° REF
12° REF
12° REF
*Controlling Parameter
Notes:
1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
Drawing No. C04-086
Revised 7-25-06
© 2006 Microchip Technology Inc.
DS21204E-page 15
25AA040/25LC040/25C040
APPENDIX A: REVISION HISTORY
Revision D
Corrections to Section 1.0, Electrical Characteristics.
Revision E (8/2006)
Added note to page 1 header (Not recommended for
new designs). Added note to package drawings.
Updated document format
DS21204E-page 16
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2006 Microchip Technology Inc.
DS21204E-page 17
25AA040/25LC040/25C040
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
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Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
25AA040/25LC040/25C040
DS21204E
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21204E-page 18
© 2006 Microchip Technology Inc.
25AA040/25LC040/25C040
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
XXX
a) 25AA040-I/P: Industrial Temp.,
PDIP package
Temperature
Range
Package
Pattern
b) 25AA040-I/SN: Industrial Temp.,
SOIC package
c) 25AA040T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
d) 25AA040X-I/ST: Alternate Pinout,
Industrial Temp., TSSOP package
e) 25AA040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
Device:
25AA040: 4096-bit 1.8V SPI Serial EEPROM
25AA040T: 4096-bit 1.8V SPI Serial EEPROM
(Tape and Reel)
25XX040X: 4096-bit 1.8V SPI Serial EEPROM
in alternate pinout (ST only)
25AA040XT:4096-bit 1.8V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
25LC040: 4096-bit 2.5V SPI Serial EEPROM
25LC040T: 4096-bit 2.5V SPI Serial EEPROM
(Tape and Reel)
25LC040X: 4096-bit 2.5V SPI Serial EEPROM
in alternate pinout (ST only)
25LC040XT:4096-bit 2.5V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
f)
25LC040-I/P: Industrial Temp.,
PDIP package
g) 25LC040-I/SN: Industrial Temp.,
SOIC package
h) 25LC040T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
i)
25LC040X-I/ST: Alternate Pinout,
Industrial Temp., TSSOP package
25LC040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
j)
25C040:
4096-bit 5.0V SPI Serial EEPROM
25C040T: 4096-bit 5.0V SPI Serial EEPROM
(Tape and Reel)
25C040X: 4096-bit 5.0V SPI Serial EEPROM
in alternate pinout (ST only)
k) 25C040-I/P: Industrial Temp.,
PDIP package
25C040XT: 4096-bit 5.0V SPI Serial EEPROM
in alternate pinout Tape and Reel
(ST only)
l)
25C040-I/SN: Industrial Temp.,
SOIC package
m) 25C040T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
n) 25C040X-I/ST: Alternate Pinout,
Industrial Temp., TSSOP package
o) 25C040XT-I/ST: Alternate Pinout, Tape
and Reel, Industrial Temp., TSSOP
package
Temperature
Range:
I
E
=
=
-40 °C to+85 °C
-40 °C to+125 °C
Package:
P
SN
ST
=
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
Plastic TSSOP (4.4 mm body), 8-lead
p) 25C040-E/P: Extended Temp.,
PDIP package
q) 25C040-E/SN: Extended Temp.,
SOIC package
r)
25C040T-E/SN: Tape and Reel,
Extended Temp., SOIC package
s) 25C040X-E/ST: Alternate Pinout,
Extended Temp., TSSOP package
t)
25C040XT-E/ST: Alternate Pinout, Tape
and Reel, Extended Temp., TSSOP pack-
age
© 2006 Microchip Technology Inc.
DS21204E-page 19
25AA040/25LC040/25C040
NOTES:
DS21204E-page 20
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21204E-page 21
WORLDWIDE SALES AND SERVICE
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Corporate Office
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08/29/06
DS21204E-page 22
© 2006 Microchip Technology Inc.
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