25LC320XT-E/STG [MICROCHIP]
4K X 8 SPI BUS SERIAL EEPROM, PDSO8, 4.40 MM, PLASTIC, TSSOP-8;
| 型号： | 25LC320XT-E/STG |
| 厂家： | 
MICROCHIP |
| 描述： | 4K X 8 SPI BUS SERIAL EEPROM, PDSO8, 4.40 MM, PLASTIC, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25LC320
32K 2.5V SPI Bus Serial EEPROM
FEATURES
PACKAGE TYPES
DIP/SOIC
• SPI modes 0,0 and 1,1
• 3.0 MHz Clock Rate
• Single supply with Programming Operation down
to 2.5V
• Low Power CMOS Technology
- Max Write Current: 5.0 mA
- Read Current: 1 mA at 5.5V, 3 Mhz
- Standby Current: 1 µA typical
• 4096 x 8 Organization
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
WP
VSS
SCK
SI
• 32-Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
TSSOP
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
- Power On/Off Data Protection Circuitry
- Write Enable Latch
- Write Protect Pin
• High Reliability
BLOCK DIAGRAM
- Endurance: 1M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000V
• 8-pin PDIP/SOIC, 14-pin TSSOP
• Temperature ranges supported
Status
Register
HV Generator
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
DESCRIPTION
Dec
The Microchip Technology Inc. 25LC320 is a 32K-bit
serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
Page Latches
Y Decoder
WP
SI
SO
CS
SCK
HOLD
Sense Amp.
R/W Control
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with exception of chip select, allowing the host
to service higher priority interrupts. Also write opera-
tions to the Status Register can be disabled via the
write protect pin (WP).
Vcc
Vss
SPI is a trademark of Motorola.
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 1
25LC320
FIGURE 1-1: AC TEST CIRCUIT
1.0
ELECTRICAL
Vcc
CHARACTERISTICS
*
1.1
Maximum Ratings
2.25 K
VCC........................................................................ 7.0V
All inputs and outputs w.r.t. VSS.......-0.6V to V +1.0V
SO
CC
Storage temperature ............................ -65°C to 150°C
Ambient temperature under bias.......... -65°C to 125°C
Soldering temperature of leads
1.8 K
100 pF
(10 seconds) .................................................... +300°C
ESD protection on all pins..................................... 4 kV
*Notice: Stresses above those listed under ‘Maximum ratings’
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended period of time may affect device reliability
1.2
AC Test Conditions
AC Waveform:
VLO = 0.2V
VHI = Vcc - 0.2V
VHI = 4.0V
(Note 1)
(Note 2)
TABLE 1-1:
PIN FUNCTION TABLE
Timing Measurement Reference Level
Name
Function
Input
Output
0.5 VCC
0.5 VCC
CS
SO
Chip Select Input
Serial Data Output
Serial Data Input
Serial Clock Input
Write Protect Pin
Ground
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
SI
SCK
WP
VSS
VCC
HOLD
NC
Supply Voltage
Hold Input
No Connect
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 2.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Max
Units
Test Conditions
High level input voltage
VIH1
2.0
VCC+1
V
VCC ≥ 2.7V
VIH2
VIL1
VIL2
VOL
VOH
ILI
0.7 VCC
-0.3
VCC+1
0.8
V
VCC< 2.7V
Low level input voltage
V
VCC ≥ 2.7V
-0.3
0.3 VCC
0.4
V
VCC< 2.7V
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
—
V
IOL=2.1 mA
VCC-0.5
-10
—
V
IOH=-400 µA
CS=VIH, VIN=GND to VCC
10
µA
µA
ILO
-10
10
CS=VIH, V
=GND to VCC
OUT
Internal Capacitance
CINT
—
7
pF
Tamb=25°C, FCLK= 1.0 MHz,
(all inputs and outputs)
VCC=5.5V (Note)
Operating Current
ICC write
ICC read
ICCS
—
—
5
3
mA
mA
VCC=5.5V; SO=Open
VCC=2.5V; SO=Open
—
—
1
500
mA
µA
VCC=5.5V; SO=Open, FCLK=3.0 MHz
VCC=2.5V; SO=Open, FCLK=2.0 MHz
Standby Current
—
5
2
µA
µA
CS=VCC=5.5V; VIN=Gnd or VCC
CS=VCC=2.5V; VIN=Gnd or VCC
Note:
This parameter is periodically sampled and not 100% tested.
DS21158B-page 2
Preliminary
1996 Microchip Technology Inc.
25LC320
FIGURE 1-2: SERIAL INPUT TIMING
tCSD
CS
tCLD
tR
tCSS
tF
tCSH
SCK
tSU
tHD
SI
msb in
lsb in
high impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
tCSH
tHI
tLO
SCK
tV
tDIS
tHO
msb out
lsb out
SO
SI
don’t care
FIGURE 1-4: HOLD TIMING
CS
tHH
tHS
tHS
tHH
SCK
tHZ
tHV
high impedance
don’t care
n
SO
n+2
n+2
n+1
n
n-1
tSU
n
n+1
n
n-1
SI
HOLD
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 3
25LC320
TABLE 1-3:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = 2.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Symbol
fSCK
Tamb = -40°C to +85°C
Parameter
Min
Max
Units
Test Conditions
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
Clock Frequency
—
—
3
2
MHz
MHz
tCSS
tCSH
tCSD
tSU
CS Setup Time
CS Hold Time
100
250
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
100
250
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
CS Disable Time
Data Setup Time
Data Hold Time
250
500
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
30
50
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
tHD
50
100
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
tR
tF
CLK Rise Time
CLK Fall Time
Clock High Time
—
—
2
2
µs
µs
(Note 1)
(Note 1)
tHI
150
250
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
tLO
Clock Low Time
150
250
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
tCLD
tV
Clock Delay Time
50
—
ns
Output Valid from
Clock Low
—
—
150
250
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
tHO
tDIS
Output Hold Time
0
—
ns
Output Disable Time
—
—
200
250
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
tHS
tHH
tHZ
tHV
HOLD Setup Time
100
100
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
HOLD Hold Time
100
100
—
—
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
HOLD Low to Output High-Z
HOLD High to Output Valid
100
150
—
—
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
100
150
—
—
ns
ns
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
tWC
—
Internal Write Cycle Time
Endurance
—
5
ms
(Note 2)
1M
—
E/W Cycles 25°C, Vcc = 5.0V, Block Mode
(Note 3)
Note 1: This parameter is periodically sampled and not 100% tested.
2: tWC begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write
cycle is complete.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS21158B-page 4
Preliminary
1996 Microchip Technology Inc.
25LC320
2.2
Read Status Register (RDSR)
2.0
PRINCIPLES OF OPERATION
The 25LC320 is a 4096 byte EEPROM designed to
interface directly with the serial peripheral interface
(SPI ) port of many of today’s popular microcontroller
families, including Microchip’s midrange PIC16CXX
microcontrollers. It may also interface with microcontrol-
lers that do not have a built-in SPI port by using dis-
crete I/O lines programmed properly with software.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
WIP
The Write-In-Process (WIP) bit indicates whether the
25LC320 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.
The 25LC320 contains an 8-bit instruction register.The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. If the WPEN bit in the Sta-
tus Register is set, the WP pin must be held high to
allow writing to the non-volatile bits in the status regis-
ter.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
the WREN or WRDI commands regardless of the state
of write protection on the status register.This bit is read
only.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the
HOLD input and place the 25LC320 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
2.1
Write Enable (WREN) and Write
Disable (WRDI)
The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the
programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
low and the WPEN bit is high. Hardware write
protection is disabled when either the WP pin is high or
the WPEN bit is low. When the chip is hardware write
protected, only writes to non-volatile bits in the status
register are disabled. See Table 2-2 for matrix of
functionality on the WPEN bit and Figure 2-1 for a
flowchart of Table 2-2. See Figure 3-5 for RDSR timing
sequence.
The 25LC320 contains a write enable latch. This latch
must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.The following is
a list of conditions under which the write enable latch
will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
TABLE 2-1:
INSTRUCTION SET
Instruction Name Instruction Format
Description
WREN
WRDI
RDSR
WRSR
READ
WRITE
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
Write status register (write protect enable and block write protection bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
TABLE 2-2:
WRITE PROTECT FUNCTIONALITY MATRIX
WPEN
WP
WEL
Protected Blocks
Unprotected Blocks
Status Register
0
0
1
1
X
X
X
X
Low
Low
High
High
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 5
25LC320
FIGURE 2-1: WRITE TO STATUS REGISTER AND/OR ARRAY FLOWCHART
CS Returns High
Write
to Status
Reg?
No
No
No
No
Write
To other
Commands
to array?
Yes
Yes
WEL = 1?
Yes
WEL = 1?
Yes
Write to the
Unprotected Block
No
No
WP is low?
Yes
Do not write to
Array
WPEN = 1?
Yes
Write to
Status Register
Do not write to
Status Register
From other
Commands
Continue
2.3
Write Status Register (WRSR)
TABLE 2-3:
BP1
ARRAY PROTECTION
The WRSR instruction allows the user to select one of
four protection options for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array.The partitioning is controlled as illus-
trated in Table 2-3.
Array Addresses
Write Protected
BP0
0
0
0
1
none
upper 1/4
0C00h - 0FFFh
1
1
0
1
upper 1/2
0800h - 0FFFh
See Figure 3-6 for WRSR timing sequence.
all
0000h - 0FFFh
DS21158B-page 6
Preliminary
1996 Microchip Technology Inc.
25LC320
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n data byte has been clocked in. If CSis brought
3.0
DEVICE OPERATION
th
3.1
Clock and Data Timing
high at any other time, the write operation will not be
completed. Refer to Figure 3-3 and Figure 3-4 for more
detailed illustrations on the byte write sequence and the
page write sequence respectively.
Data input on the SI pin is latched on the rising edge of
SCK. Data is output on the SO pin after the falling edge
of SCK.
While the write is in progress, the status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits. A read attempt of a memory array
location will not be possible during a write cycle. When
a write cycle is completed, the write enable latch is
reset.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25LC320 followed by
the 16-bit address, with the four MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (0FFFh) the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by setting
CS high (Figure 3-1).
3.4
Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
the write enable latch.
• After a successful byte write, page write, or status
register write, the write enable latch is reset.
• CS must be set high after the proper number of
clock cycles to start an internal write cycle.
• Access to the array during an internal write cycle
is ignored and programming is continued.
3.3
Write Sequence
Prior to any attempt to write data to the 25LC320, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-2). This is done by setting CS low
and then clocking the proper instruction into the
25LC320. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
3.5
Power On State
The 25LC320 powers on in the following state:
• The device is in low power standby mode.
• The write enable latch is reset.
• SO is in high impedance state.
• A low level on CS is required to enter active state.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the 16-bit address, with the four MSBs of
the address being don’t care bits, and then the data to
be written. Up to 32 bytes of data can be sent to the
25LC320 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXXX XXXX
XXX0 0000 and ends with XXXX XXXX XXX1 1111. If
the internal address counter reaches XXXX XXXX
XXX1 1111 and the clock continues, the counter will roll
back to the first address of the page and overwrite any
data in the page that may have been written.
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 7
25LC320
FIGURE 3-1: READ SEQUENCE
CS
0
0
1
0
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
instruction
16 bit address
0
0
0
0
1
1
15 14 13 12
2
1
0
data out
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-2: WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
high impedance
SO
FIGURE 3-3: WRITE SEQUENCE
CS
T
wc
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
data byte
SCK
SI
instruction
16 bit address
15 14 13 12
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
high impedance
SO
DS21158B-page 8
Preliminary
1996 Microchip Technology Inc.
25LC320
FIGURE 3-4: PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
instruction
16-bit address
0 15 14 13 12
data byte 1
0
0
0
0
0
0
1
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39
data byte 2
41 42 43 44 45 46 47
data byte 3
40
SCK
SI
data byte n (32 max)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FIGURE 3-5: READ STATUS REGISTER SEQUENCE
CS
0
0
1
0
2
3
4
5
1
6
0
7
8
9 10 11 12 13 14 15
SCK
SI
instruction
0
0
0
1
data from status register
high impedance
7
6
5
4
3
2
1
0
SO
FIGURE 3-6: WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
SI
instruction
data to status register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
high impedance
SO
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 9
25LC320
The WP pin function is blocked when the WPEN bit in
the status register is low. This allows the user to install
the 25LC320 in a system with WPpin grounded and still
be able to write to the status register. The WP pin
functions will be enabled when the WPEN bit is
set high.
4.0
PIN DESCRIPTIONS
4.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already in
progress will be completed, regardless of the CS input
signal. If CS is brought high during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is complete. As soon as the device is
deselected, SO goes to the high impedance state,
allowing multiple parts to share the same SPI bus. A
low to high transition on CS after a valid write sequence
is what initiates an internal write cycle. After power-up,
a low level on CS is required prior to any sequence
being initiated.
4.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25LC320 while in the middle of a serial sequence with-
out having to re-transmit entire sequence over at a later
time. It should be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLDpin may be pulled low
to pause further serial communication without resetting
the serial sequence. The HOLD pin must be brought
low while SCK is low, otherwise the HOLD function will
not be evoked until the next SCK high to low transition.
The 25LC320 must remain selected during this
sequence. The SI, SCK, and SO pins are in a high
impedance state during the time the part is paused and
transitions on these pins will be ignored. To resume
serial communication, HOLD must be brought high
while the SCK pin is low, otherwise serial communica-
tion will not resume.
4.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data to be written
to the memory. Input is latched on the rising edge of the
serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two way
communication of data can occur using only one
microcontroller I/O line.
4.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25LC320.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
It is possible for the SI pin and the SO pin to be tied
together. With SI and SO tied together, two-way
communication of data can occur using only one
microcontroller I/O line.
4.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25LC320. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
4.5
Write Protect (WP)
This pin is used in conjunction with the WPEN bit in the
status register to prohibit writes to the non-volatile bits
in the status register. When WP is low and WPEN is
high, writing to the non-volatile bits in the status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
non-volatile bits in the status register operate normally.
WP going low during a status register write sequence
will disable writing to the status register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
DS21158B-page 10
Preliminary
1996 Microchip Technology Inc.
25LC320
25LC320 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
25LC320
-
/P
Package:
P = PDIP (300 mil Body), 8-lead
SN = SOIC (150 mil Body), 8-lead
ST = TSSOP (4.4 mm Body), 14-lead
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
Device:
32K SPI Bus Serial EEPROM
25LC320
32K SPI Bus Serial EEPROM (Tape and Reel)
25LC320T
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see next page)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1996 Microchip Technology Inc.
Preliminary
DS21158B-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
ASIA/PACIFIC
Hong Kong
EUROPE
United Kingdom
Microchip Technology Inc.
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
France
Atlanta
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Boston
Korea
Germany
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Shanghai
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Chicago
Italy
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Microchip Technology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan, R.O.C
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Tel: 81 45 471 6166 Fax: 81 45 471 6122
11/7/96
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 11/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21158B-page 12
Preliminary
1996 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明