34AA04T-I/ST_技术文档

34AA04

4K I²C^™Serial EEPROM with Software Write-Protect

Device Selection Table

Description

The Microchip Technology Inc. 34AA04 is a 4 Kbit

Electrically Erasable PROM which utilizes the I²C serial

interface and is capable of operation across a broad

voltage range (1.7V to 3.6V). This device is JEDEC

JC42.4 (EE1004-v) Serial Presence Detect (SPD)

compliant and includes reversible software write

protection for each of four independent 128 x 8-bit

blocks. The device features a page write capability of

up to 16 bytes of data. Address pins allow up to eight

devices on the same bus.

Part

Number

VCC

Range

Max. Clock

Frequency

Temp

Ranges

34AA04

1.7-3.6

1 MHz⁽¹⁾

I, E

Note 1: 400 kHz for 1.8V ≤ VCC < 2.2V

100 kHz for VCC < 1.8V

Features

• 4 Kbit EEPROM:

- Internally organized as two 256 x 8-bit banks

- Byte or page writes (up to 16 bytes)

The 34AA04 is available in the 8-lead PDIP, SOIC,

TSSOP, TDFN, and UDFN packages.

- Byte or sequential reads within a single bank

Package Types

- Self-timed write cycle (5 ms max.)

• JEDEC^®JC42.4 (EE1004-v) Serial Presence

Detect (SPD) Compliant for DRAM (DDR4)

modules

PDIP/SOIC/TSSOP

TDFN/UDFN

A0

A1

1

2

3

4

8

7

6

5

VCC

NC

• High-Speed I²C™ Interface:

1

VCC

A0

8

7

6

5

NC

2

3

4

A1

A2

- Industry standard 1 MHz, 400 kHz, and

100 kHz

A2

SCL

SDA

SCL

SDA

VSS

- Schmitt Trigger inputs for noise suppression

- SMBus-compatible bus time out

- Cascadable up to eight devices

• Write Protection:

Block Diagram

- Reversible software write protection for four

individual 128-byte blocks

A0 A1 A2

HV Generator

• Low-Power CMOS Technology:

- Voltage range: 1.7V to 3.6V

- Write current: 1.5 mA at 3.6V

- Read current: 200 µA at 3.6V, 400 kHz

- Standby current: 1 µA at 3.6V

• High Reliability:

Block 0

(000h-07Fh)

Block 1

(080h-0FFh)

Block 2

(100h-17Fh)

Block 3

(180h-1FFh)

I/O

Control

Logic

Memory

Control

Logic

XDEC

SDA SCL

- More than one million erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

VCC

VSS

Write-Protect

Circuitry

YDEC

• 8-lead PDIP, SOIC, TSSOP, TDFN, and UDFN

Packages

Sense Amp.

R/W Control

• Available Temperature Ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

 2014 Microchip Technology Inc.

DS20005271B-page 1

34AA04

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All Inputs and Outputs (except A0) w.r.t. VSS...............................................................................................-0.3V to 6.5V

A0 Input w.r.t. VSS ........................................................................................................................................... -0.3 to 12V

Storage Temperature...............................................................................................................................-65°C to +150°C

Ambient Temperature with Power Applied ..............................................................................................-40°C to +125°C

ESD Protection on All Pins 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. These are stress ratings only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC SPECIFICATIONS

VCC = +1.7V to +3.6V

DC CHARACTERISTICS

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units

Conditions

—

A0, A1, A2, SCL, and SDA

High-Level Input Voltage

Low-Level Input Voltage

—

0.7 VCC

—

V

D1

D2

VIH

VIL

VCC + 0.5

0.3 VCC

0.2 VCC

V

VCC ≥ 2.5V

VCC < 2.5V

D3

D4

VHYS

VOL

Hysteresis of Schmitt

Trigger Inputs

0.0 VCC

—

V

(Note)

Low-Level Output Voltage

0.40

V

IOL = 20.0 mA, VCC = 2.2V

IOL = 6.0 mA, VCC = 1.7V

High-Voltage Detect

(A0 pin only)

7

10

±1

10

V

VCC < 2.2V

D5

VHV

VCC + 4.8

VCC  2.2V

D6

D7

D8

ILI

Input Leakage Current

Output Leakage Current

—

A

pF

VIN = VSS or VCC

VOUT = VSS or VCC

ILO

CIN, COUT Pin Capacitance

(all inputs/outputs)

VCC = 5.5V (Note)

TA = 25°C, FCLK = 1 MHz

D9

ICC write Operating Current

ICC read

—

1.5

mA

VCC = 3.6V

D10

D11

200

A

VCC = 3.6V, SCL = 400 kHz

ICCS

Standby Current

—

1

5

A

Industrial

Automotive

SDA, SCL, VCC = 3.6V

A0, A1, A2 = VSS

Note: This parameter is periodically sampled and not 100% tested.

DS20005271B-page 2

 2014 Microchip Technology Inc.

34AA04

TABLE 1-2:

AC SPECIFICATIONS

VCC = +1.7V to +3.6V

AC CHARACTERISTICS

Industrial (I): TA = -40°C to +85°C

Automotive (E): TA = -40°C to +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units

Conditions

1

2

3

4

5

6

7

FCLK

THIGH

TLOW

TR

Clock Frequency (Note 2)

10

100

400

1000

kHz

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

Clock High Time

4000

600

260

—

ns

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

Clock Low Time

4700

1300

500

—

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

SDA and SCL Rise Time (Note 1)

SDA and SCL Fall Time (Note 1)

Start Condition Hold Time

Start Condition Setup Time

—

1000

300

120

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

TF

—

300

120

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

THD:STA

TSU:STA

4000

600

260

—

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

4700

600

260

—

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

8

9

THD:DAT

TSU:DAT

Data Input Hold Time

Data Input Setup Time

0

—

ns

(Note 3)

250

100

50

—

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

10

11

12

13

TSU:STO

TAA

Stop Condition Setup Time

4000

600

260

—

ns

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

Output Valid from Clock (Note 3)

200

—

3450

900

350

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

TBUF

Bus Free Time: Time the bus must

be free before a new transmission

can start

4700

1300

500

—

1.7V  VCC < 1.8V

1.8V  VCC  2.2V

2.2V  VCC  3.6V

TSP

Input Filter Spike Suppression

(SDA and SCL pins)

—

50

(Note 1)

14

15

16

TWC

Write Cycle Time (byte or page)

—

25

5

ms

—

TTIMEOUT Bus Timeout Time

Endurance

35

—

1M

cycles Page mode, 25°C, VCC = 3.6V

(Note 4)

Note 1: Not 100% tested.

2: The minimum clock frequency of 10 kHz is to prevent the bus timeout from occurring.

3: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

200 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

 2014 Microchip Technology Inc.

DS20005271B-page 3

34AA04

FIGURE 1-1:

BUS TIMING DATA

5

4

D3

2

SCL

7

3

10

8

9

SDA

In

6

13

12

11

SDA

Out

DS20005271B-page 4

 2014 Microchip Technology Inc.

34AA04

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

Symbol

PIN FUNCTION TABLE

PDIP

SOIC

TSSOP

UDFN

TDFN

Description

A0/VHV

A1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Chip Address Input, High-Voltage Input

Chip Address Input

Ground

A2

VSS

SDA

SCL

NC

Serial Address/Data I/O

Serial Clock

Not Connected

VCC

+1.7V to 3.6V Power Supply

Note:

Exposed pad on TDFN/UDFN can be connected to VSS or left floating.

2.1

A0, A1, A2 Chip Address Inputs

2.3

Serial Clock (SCL)

The levels on these inputs are compared with the

corresponding bits in the slave address. The chip is

selected if the compare is true.

This input is used to synchronize the data transfer to

and from the device.

Up to eight 34AA04 devices may be connected to the

same bus by using different Chip Select bit combina-

tions. These inputs must be connected to either VSS or

VCC.

The A0 pin also serves as the high-voltage input for

enabling the SWPn and CWP instructions.

Note:

The comparison between the A0, A1, and

A2 pins and the corresponding Chip

Select bits is disabled for software Write-

Protect and Bank Select commands.

2.2

Serial Address/Data Input/Output

(SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal. Therefore, the SDA bus requires a pull-

up resistor to VCC (typical 10 k for 100 kHz, 2 k for

400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

 2014 Microchip Technology Inc.

DS20005271B-page 5

34AA04

will be stored when doing a write operation. When an

overwrite does occur, it will replace data in a first-in,

first-out (FIFO) fashion.

3.0

FUNCTIONAL DESCRIPTION

The 34AA04 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data, as a receiver. The bus has to be

controlled by a master device, which generates the

Serial Clock (SCL), controls the bus access and gener-

ates the Start and Stop conditions, while the 34AA04

works as slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated.

4.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge after the reception of each

byte. Exceptions to this rule relating to software write

protection are described in Section 9.0 “Software

Write Protection”. The master device must generate

an extra clock pulse, which is associated with this

Acknowledge bit.

The 4 Kbit array of the 34AA04 is divided into two

separate banks of 2 Kbits each. The 34AA04 also

offers reversible software write protection for each of

four 1 Kbit blocks.

Note:

The 34AA04 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end-of-

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (34AA04) will leave the data line

high to enable the master to generate the Stop

condition.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.6

Bus Timeout

4.1

Bus Not Busy (A)

If SCL remains low for the time specified by TTIMEOUT,

the 34AA04 will reset the serial interface and ignore all

further communication until another Start condition is

detected (Figure 4-2). This dictates the minimum clock

speed as defined by FCLK.

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoretically, unlimited; although only the last sixteen

DS20005271B-page 6

 2014 Microchip Technology Inc.

34AA04

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

FIGURE 4-2:

BUS TIMEOUT

TTIMEOUT(MIN)

TTIMEOUT(MAX)

SCL

TLOW < TTIMEOUT(MIN): Bus interface does not reset.

TTIMEOUT(MIN) < TLOW < TTIMEOUT(MAX): Bus interface may or may not reset.

TTIMEOUT(MAX) < TLOW: Bus interface will reset.

4.7

Device Addressing

Control

Code

Chip

Select

Operation

R/W

A control byte is the first byte received following the

Start condition from the master device. The first part of

the control byte consists of a 4-bit control code which is

set to ‘1010’ for normal read and write operations and

‘0110’ for accessing the software write-protect features

and bank selection. The control byte is followed by

three Chip Select bits (A2, A1, A0). The Chip Select bits

allow the use of up to eight 34AA04 devices on the

same bus and are used to determine which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond.

Read

Write

1010

A2 A1 A0

1

0

Read Write-Protect/

Bank Address

0110

A2 A1 A0

1

0

Set Write-Protect/

Bank Address

FIGURE 4-3:

CONTROL BYTE

ALLOCATION

Start

Read/Write

The eighth bit of slave address determines if the master

device wants to read or write to the 34AA04

(Figure 4-3). When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected.

Slave Address

R/W A

1

0

1

0

A2

A1

A0

OR

1

0

A2

 2014 Microchip Technology Inc.

DS20005271B-page 7

34AA04

5.0

BANK ADDRESSING

Note: Sequential read operations cannot

cross a bank boundary and will roll over

back to the beginning of the selected

bank.

To support backwards-compatibility with DDR2/3

(JEDEC EE1002) SPD EEPROMs, the memory array

of the 34AA04 is divided into two separate 256-byte

banks. The Set Bank Address (SBA) commands are

used to set the bank address to either 0 or 1. The

Read Bank Address (RBA) command is used to

determine which bank is currently selected.

TABLE 5-1:

Bank

BANK ADDRESS RANGE

Logical Array Address

Bank 0

Bank 1

000h-0FFh

100h-1FFh

Note 1: The bank address is volatile and is reset

to Bank 0 upon power-up.

2: The comparison between the A0, A1, and

A2 pins and the corresponding Chip

Select bits is disabled for Bank Select

commands.

TABLE 5-2:

BANK ADDRESSING INSTRUCTION SET

Control Byte

Chip Select Bits

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Function

Abbr

Control Code

R/W

A0 Pin

Set Bank Address to 0

Set Bank Address to 1

Read Bank Address

SBA0

SBA1

RBA

1

0

1

0

1

0, 1, or VHV

0

1

0

34AA04 will respond with an Acknowledge, and then

the master transmits two dummy bytes. The 34AA04

will not acknowledge either dummy byte. Finally, the

master generates a Stop condition to end the

operation (Figure 5-1).

5.1

Set Bank Address (SBA)

The Set Bank Address (SBA) commands are used to

select the array bank for future read and write

operations.

The master generates a Start condition followed by the

corresponding control byte for the chosen SBA

command (Table 5-2), with the R/W bit set to a logic

‘0’. Note that Chip Select bit A0 of the control byte

effectively determines which bank is selected. The

Array Read and Write commands will operate in the

newly-selected bank until another SBA command is

executed, or the 34AA04 experiences a POR or BOR

event.

FIGURE 5-1: SET BANK ADDRESS

S

T

A

R

T

Bus Activity

Master

Control

Byte

Dummy

Byte

Dummy

Byte

T

O

P

A¹

0

SDA Line

0

1

1 0

1

0

S

P

A

C

K

N

o

N

o

Bus Activity

A

C

K

A

C

K

Note 1: Chip Select bit A0 specifies which bank to select.

DS20005271B-page 8

 2014 Microchip Technology Inc.

34AA04

5.2

Read Bank Address (RBA)

The Read Bank Address (RBA) command allows the

34AA04 to indicate which array bank is currently

selected.

The master generates a Start condition and transmits

the RBA control byte (Table 5-2), with the R/W bit set

to logic ‘1’. If Bank 0 is currently selected, the 34AA04

will respond with an Acknowledge signal. If Bank 1 is

currently selected, an Acknowledge will not be

generated. Regardless of the result, the master must

read at least one dummy byte from the 34AA04,

transmitting a Not Acknowledge signal after each byte,

and generate a Stop condition to end the command

(Figure 5-2).

FIGURE 5-2: READ BANK ADDRESS

S

Bus Activity

Master

T

A

R

Control

Byte

Dummy

Byte

S

T

O

P

T

SDA Line

0

1

0 1 1 0 1

S

P

A¹

C

N

o

Bus Activity

K

A

C

K

Note 1: The 34AA04 will only acknowledge if Bank 0 is currently selected.

2: In accordance with the JEDEC spec, the master is allowed to read multiple dummy bytes,

transmitting a Not Acknowledge after each byte.

 2014 Microchip Technology Inc.

DS20005271B-page 9

34AA04

Pointer bits are internally incremented by one. The

higher order four bits of the array address, as well as

the bank selection, remain constant. If the master

should transmit more than 16 bytes prior to generating

the Stop condition, the address counter will roll over

and the previously received data will be overwritten. As

with the byte write operation, once the Stop condition is

received, an internal write cycle will begin (Figure 6-2).

If an attempt is made to write to a software write-pro-

tected portion of the array, the 34AA04 will not

acknowledge the data byte, no data will be written, and

the device will immediately accept a new command.

6.0

6.1

WRITE OPERATIONS

Byte Write

Following the Start signal from the master, the control

code (4 bits), the Chip Select bits (3 bits) and the R/W

bit, which is a logic low, are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that the array address byte will follow,

once it has generated an Acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the array address and will be written

into the Address Pointer of the 34AA04.

Note:

When doing a write of less than 16 bytes,

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle. For this reason,

endurance is specified per page.

After receiving another Acknowledge signal from the

34AA04, the master device will transmit the data byte to

be written into the addressed memory location. The

34AA04 acknowledges again and the master generates

a Stop condition. This initiates the internal write cycle,

which means that during this time, the 34AA04 will not

generate Acknowledge signals (Figure 6-1).

Note:

Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer multi-

ples of the page buffer size (or ‘page size’)

and end at addresses that are integer mul-

tiples of [page size – 1]. If a Page Write

command attempts to write across a phys-

ical page boundary, the result is that the

data wraps around to the beginning of the

current page (overwriting data previously

stored there), instead of being written to

the next page, as might be expected. It is,

therefore, necessary for the application

software to prevent page write operations

that would attempt to cross a page

boundary.

Note:

It is recommended to perform a Set Bank

Address command before initiating a

Write command to ensure the desired

bank is selected.

If an attempt is made to write to a software write-pro-

tected portion of the array, the 34AA04 will not acknowl-

edge the data byte, no data will be written, and the

device will immediately accept a new command.

6.2

Page Write

The write control byte, array address and the first data

byte are transmitted to the 34AA04 in the same way as

in a byte write. Instead of generating a Stop condition,

the master transmits up to 15 additional data bytes to

the 34AA04, which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the master has transmitted a Stop condition. Upon

receipt of each word, the four lower order Address

TABLE 6-1:

Status

DEVICE RESPONSE WHEN WRITING DATA

Command

ACK

Address

ACK

Data Byte

ACK Write Cycle

Page or Byte Write in

Protected Block

Protected with SWPn

Not Protected

ACK

Address

ACK

Data

NoACK

ACK

No

Page or Byte Write

Yes

FIGURE 6-1:

BYTE WRITE

S

T

O

P

T

A

R

T

Bus Activity

Master

Control

Byte

Array

Address

Data

SDA Line

S

P

A

C

K

A

C

K

A

C

K

Bus Activity

DS20005271B-page 10

 2014 Microchip Technology Inc.

34AA04

FIGURE 6-2:

PAGE WRITE

S

T

Bus Activity

Master

Control

Byte

Array

Address (n)

A

O

Data (n + 15)

P

Data (n)

Data (n + 1)

R

T

S

SDA Line

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

 2014 Microchip Technology Inc.

DS20005271B-page 11

34AA04

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 7-1 for flow

diagram.

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

No

Yes

DS20005271B-page 12

 2014 Microchip Technology Inc.

34AA04

master will not acknowledge the transfer, but does

8.0

READ OPERATION

generate

a

Stop condition and the 34AA04

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

discontinues transmission (Figure 8-2).

Note: It is recommended to perform a Set Bank

Address command before initiating a

Read command to ensure the desired

bank is selected.

8.1

Current Address Read

8.3

Sequential Read

The 34AA04 contains an address counter that

maintains the address of the last byte accessed, inter-

nally incremented by ‘1’. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n+1. Upon receipt of

the slave address with R/W bit set to ‘1’, the 34AA04

issues an acknowledge and transmits the 8-bit data

value. The master will not acknowledge the transfer,

but does generate a Stop condition and the 34AA04

discontinues transmission (Figure 8-1).

Sequential reads are initiated in the same way as a

random read, with the exception that after the 34AA04

transmits the first data byte, the master issues an

acknowledge, as opposed to a Stop condition in a

random read. This directs the 34AA04 to transmit the

next sequentially addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 34AA04 contains an

internal Address Pointer, which is incremented by one

at the completion of each operation. Sequential reads

are limited to a single bank per operation, so the

Address Pointer allows the entire memory contents of

the current bank to be serially read during one opera-

tion.

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the array address must first

be set. This is done by sending the array address to the

34AA04 as part of a write operation. Once the array

address is sent, the master generates a Start condition

following the acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. The master then issues the control byte again, but

with the R/W bit set to a ‘1’. The 34AA04 then issues

an acknowledge and transmits the 8-bit data word. The

8.4

Noise Protection and Brown-Out

The 34AA04 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.35V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

FIGURE 8-1:

CURRENT ADDRESS READ

S

Bus Activity

Master

T

A

R

Control

Byte

S

T

Data (n)

O

P

T

SDA Line

S

P

A

C

K

N

O

Bus Activity

A

C

K

 2014 Microchip Technology Inc.

DS20005271B-page 13

34AA04

FIGURE 8-2:

RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Array

Address (n)

Control

Byte

Data (n)

S

P

S

SDA Line

Bus Activity

A

C

K

A

C

K

A

C

K

N

O

A

C

K

FIGURE 8-3:

SEQUENTIAL READ

S

T

O

P

Bus Activity

Master

Control

Byte

Data (n)

Data (n + 1)

Data (n + 2)

Data (n + X)

SDA Line

P

A

C

K

A

C

K

A

C

K

A

C

K

N

O

Bus Activity

A

C

K

DS20005271B-page 14

 2014 Microchip Technology Inc.

34AA04

TABLE 9-1:

Block

BLOCK ADDRESS RANGE

Logical Array Address

9.0

SOFTWARE WRITE

PROTECTION

Block 0

Block 1

Block 2

Block 3

000h - 07Fh

080h - 0FFh

100h - 17Fh

180h - 1FFh

The 34AA04 has a reversible software write-protect

feature that allows each of four 128-byte blocks to be

individually write-protected. The write protection is set

by executing the Set Write Protect (SWPn)

commands. The Clear All Write Protect (CWP)

command is used to unprotect all of the blocks at

once. It is not possible to unprotect blocks individually.

The Read Protection Status (RPS) commands are

used to determine if a given block is currently write-

protected.

Note:

The comparison between the A0, A1, and

A2 pins and the corresponding Chip

Select bits is disabled for software Write-

Protect commands.

The 34AA04 will not respond with an Acknowledge

following the data bytes of write operations that are

attempted within a write-protected block.

Note: The write-protect state of each block is

stored in nonvolatile bits.

TABLE 9-2:

SOFTWARE WRITE PROTECTION INSTRUCTION SET

Control Byte

Function

Abbr

Control Code

Chip Select Bits

R/W

A0 Pin

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Set Write Protection, block 0

Set Write Protection, block 1

Set Write Protection, block 2

Set Write Protection, block 3

Clear All Write Protection

SWP0

SWP1

SWP2

SWP3

CWP

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VHV

0

1

0

VHV

Read Protection Status, block 0

Read Protection Status, block 1

Read Protection Status, block 2

Read Protection Status, block 3

RPS0

RPS1

RPS2

RPS3

0, 1, or VHV

If the specified block is already write-protected, the

SWP command is ignored, no Acknowledges will be

sent, and the internal write cycle will not be executed.

9.1

Set Write Protection (SWPn)

The Set Write Protection (SWP) commands are used

to set the reversible write protection for individual array

blocks. There are four different SWP commands, one

for each block.

VHV must be applied to the A0 pin for the entire SWP

command. Then, the command is executed in a

manner similar to an array byte Write command.

Following the Start condition, the ‘0110’ control code

and the three Chip Select bits that correspond to the

desired SWP command (Table 9-2) are transmitted by

the master, along with the R/W bit as a logic ‘0’. After

the 34AA04 responds with an Acknowledge, the

master transmits two dummy bytes, after each of

which the 34AA04 responds with an Acknowledge.

Finally, the master generates a Stop condition, which

initiates the internal write cycle and, during this time,

the 34AA04 will not generate Acknowledge signals

(Figure 9-1).

 2014 Microchip Technology Inc.

DS20005271B-page 15

34AA04

FIGURE 9-1: SET WRITE PROTECTION

VHV

A0 Pin

S

T

A

R

T

Bus Activity

Master

Control

Byte

Dummy

Byte

Dummy

Byte

O

P

A¹A¹A¹

SDA Line

0

1

1 0

0

S

P

2

1 0

A²

C

A²

C

A²

C

Bus Activity

K

Note 1: Chip Select bits A0-A2 vary depending on which SWP command is being executed.

2: The 34AA04 will only acknowledge if the specified block is not currently write-protected.

TABLE 9-3:

Status

DEVICE RESPONSE WHEN DEFINING WRITE PROTECTION

Command ACK Address ACK Data Byte

SWPn NoACK Don’t Care NoACK Don’t Care NoACK

ACK Write Cycle

No

Yes

Protected with SWPn

CWP

ACK

Don’t Care

ACK

Don’t Care

ACK

Not Protected

SWPn or CWP

Following the Start condition, the master transmits the

control byte for the desired RPS command (Table 9-2),

with the R/W bit set to logic ‘1’. If the specified block is

not write-protected, the 34AA04 will respond with an

Acknowledge signal. If the block is currently write-

protected, an Acknowledge will not be generated.

Regardless of the result, the master must read at least

one dummy byte from the 34AA04, transmitting a Not

Acknowledge signal after each byte, and generate a

Stop condition to end the command (Figure 9-3).

9.2

Clear All Write Protection (CWP)

The Clear All Write Protection (CWP) command resets

all of the write protection in a single operation. It is

executed in the same manner as a SWP command,

except using the CWP control byte (Table 9-2).

The 34AA04 will always acknowledge and execute a

CWP command if an internal write cycle is not in

progress, regardless of the state of write protection.

9.3

Read Protection Status (RPS)

The Read Protection Status (RPS) commands provide

a way of determining whether or not the specified

block is currently write-protected.

FIGURE 9-2: CLEAR ALL WRITE PROTECTION

VHV

A0 Pin

S

T

A

R

T

Bus Activity

Master

Control

Byte

Dummy

Byte

Dummy

Byte

T

O

P

SDA Line

0

1 1 0 0 1 1 0

S

P

A

C

K

A

C

K

A

C

K

Bus Activity

DS20005271B-page 16

 2014 Microchip Technology Inc.

34AA04

FIGURE 9-3: READ PROTECTION STATUS

S

Bus Activity

Master

T

A

R

Control

Byte

Dummy

Byte

S

T

O

P

T

A¹A¹A¹

SDA Line

0

1

0

1

S

P

2

1 0

A²

C

N

o

Bus Activity

K

A

C

K

Note 1: Chip Select bits A0-A2 vary depending on which RPS command is being performed.

2: The 34AA04 will only acknowledge if the specified block is not currently write-protected.

3: In accordance with the JEDEC spec, the master is allowed to read multiple dummy bytes,

transmitting a Not Acknowledge after each byte.

TABLE 9-4:

DEVICE RESPONSE WHEN READING WRITE PROTECTION STATUS

Status

Command

ACK

Data Byte

ACK

Protected with SWPn

Not Protected

RPSn

NoACK

ACK

Don’t Care

NoACK

 2014 Microchip Technology Inc.

DS20005271B-page 17

34AA04

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

8-Lead PDIP (300 mil)

Example:

34AA04

XXXXXXXX

XXXXXNNN

e

3

3EC

YYWW

1442

8-Lead SOIC (3.90 mm)

Example:

34AA04

XXXXXXXX

e

3

XXXXYYWW

1442

NNN

3EC

Example:

8-Lead TSSOP

AACK

1442

3EC

XXXX

YYWW

NNN

8-Lead 2x3 TDFN

Example:

ACB

442

3E

XXX

YWW

NN

8-Lead 2x3 UDFN

Example:

CAC

442

3E

XXX

YWW

NN

1st Line Marking Codes

Part Number

PDIP

SOIC

TSSOP

TDFN

UDFN

34AA04

AACK

ACB

CAC

DS20005271B-page 18

 2014 Microchip Technology Inc.

34AA04

Legend: XX...X Part number or part number code

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

JEDEC^®designator for Matte Tin (Sn)

e

3

Note:

For very small packages with no room for the JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

 2014 Microchip Technology Inc.

DS20005271B-page 19

34AA04

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

N

B

E1

NOTE 1

1

2

TOP VIEW

E

A2

A

C

PLANE

L

c

A1

e

eB

8X b1

8X b

.010

C

SIDE VIEW

END VIEW

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

DS20005271B-page 20

 2014 Microchip Technology Inc.

34AA04

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

DATUM A

b

e

2

e

2

e

Units

Dimension Limits

INCHES

NOM

8

.100 BSC

-

MIN

MAX

Number of Pins

Pitch

N

e

A

Top to Seating Plane

-

.210

.195

-

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

A2

A1

E

E1

D

L

c

b1

b

eB

.115

.015

.290

.240

.348

.115

.008

.040

.014

-

.130

-

.310

.250

.365

.130

.010

.060

.018

-

.325

.280

.400

.150

.015

.070

.022

.430

Lower Lead Width

Overall Row Spacing

§

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

 2014 Microchip Technology Inc.

DS20005271B-page 21

34AA04

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005271B-page 22

 2014 Microchip Technology Inc.

34AA04

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014 Microchip Technology Inc.

DS20005271B-page 23

34AA04

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34AA04

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 2014 Microchip Technology Inc.

DS20005271B-page 25

34AA04

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005271B-page 26

 2014 Microchip Technology Inc.

34AA04

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2014 Microchip Technology Inc.

DS20005271B-page 27

34AA04

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005271B-page 28

 2014 Microchip Technology Inc.

34AA04

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 2014 Microchip Technology Inc.

DS20005271B-page 29

34AA04

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DS20005271B-page 30

 2014 Microchip Technology Inc.

34AA04

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 2014 Microchip Technology Inc.

DS20005271B-page 31

34AA04

APPENDIX A: REVISION HISTORY

Revision B (10/2014)

• Removed “Preliminary” condition.

• Updated Section 10.0, Packaging Information.

• Minor typographical corrections.

Revision A (03/2014)

Original release of this document.

DS20005271B-page 32

 2014 Microchip Technology Inc.

34AA04

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

tion:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers should contact their distributor, representa-

tive or Field Application Engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included in

the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

 2014 Microchip Technology Inc.

DS20005217B-page 33

34AA04

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

–

X

/XX

Examples:

Temperature Package

Range

a) 34AA04-I/P: Industrial Temperature,

1.7V, PDIP package

b) 34AA04-I/SN: Industrial Temperature,

1.7V, SOIC package

2

Device:

34AA04:

34AA04T:

=

1.7V, 4 Kbit I C Serial EEPROM

2

1.7V, 4 Kbit I C Serial EEPROM

c) 34AA04T-E/MUY: Tape and Reel,

Automotive Temperature, 1.7V, UDFN

package

(Tape and Reel)

d) 34AA04T-I/MNY: Tape and Reel, Indus-

trial Temperature, 1.7V, TDFN package

Temperature

Range:

I

E

=

-40°C to +85°C

-40°C to +125°C

e) 34AA04-E/ST: Automotive Temperature,

1.7V, TSSOP package

Package:

P

=

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

Plastic Dual Flat, No Lead Package

(2x3x0.75 mm body), 8-lead

SN

ST

MNY

(1)

MUY

=

Plastic Dual Flat, No Lead Package

(2x3x0.5 mm body), 8-lead

Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.

DS20005271B-page 34

 2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,

MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-63276-747-9

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2014 Microchip Technology Inc.

DS20005271B-page 35

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-3019-1500

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Austin, TX

Tel: 512-257-3370

Germany - Pforzheim

Tel: 49-7231-424750

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Poland - Warsaw

Tel: 48-22-3325737

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Sweden - Stockholm

Tel: 46-8-5090-4654

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Novi, MI

Tel: 248-848-4000

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Houston, TX

Tel: 281-894-5983

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Taiwan - Kaohsiung

Tel: 886-7-213-7830

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Los Angeles

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

03/25/14

DS20005271B-page 36

 2014 Microchip Technology Inc.


型号：	34AA04T-I/ST
厂家：	MICROCHIP
描述：	4K I2Câ¢ Serial EEPROM with Software Write-Protect 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总36页 (文件大小：666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

34AA04T-I/ST [MICROCHIP]

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