37LV128-I/P [MICROCHIP]
4K X 32 OTPROM, PDIP8, PLASTIC, DIP-8;
| 型号： | 37LV128-I/P |
| 厂家： | 
MICROCHIP |
| 描述： | 4K X 32 OTPROM, PDIP8, PLASTIC, DIP-8 可编程只读存储器 OTP只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete Device
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
PACKAGE TYPES
• Operationally equivalent to Xilinx XC1700 family
• Wide voltage range 3.0 V to 6.0 V
PDIP
DATA
CLK
1
2
3
4
8
7
6
5
VCC
VPP
CEO
VSS
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
RESET/OE
CE
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
SOIC
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
1
2
3
4
8
7
6
5
• Programming with industry standard EPROM pro-
grammers
VCC
DATA
CLK
VPP
CEO
VSS
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
RESET/OE
CE
• Temperature ranges:
-
Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
PLCC
DATA VCC
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
4
5
6
7
8
CLK
18
17
16
15
14
VPP
RESET/OE
CE
CEO
Vss
BLOCK DIAGRAM
Device
Bits
Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
2004 Microchip Technology Inc.
DS21109F-page 1
37LV36/65/128
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
8
20
VCC and input voltages w.r.t. VSS.......... -0.6V to +0.6V
DATA
CLK
Data I/O
Clock Input
1
2
3
2
4
6
VPP voltage w.r.t. VSS during
programming......................................-0.6V to +14.0V
RESET/OE Reset Input and Output
Enable
Output voltage w.r.t. VSS ................-0.6V to VCC +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Soldering temperature of leads (10 sec.) .........+300°C
ESD protection on all pins ..................................... ≥ 4 kV
CE
VSS
CEO
VPP
VCC
Chip Enable Input
4
5
6
7
8
8
Ground
10
14
17
20
Chip Enable Output
Programming Voltage Supply
+3.0V to 6.0V Power Supply
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
Not Labeled Not utilized, not connected
TABLE 1-2:
READ OPERATION DC CHARACTERISTICS
VCC = +3.0 to 6.0V
Commercial (C):
Industrial (I):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
DATA, CE, CEO and Reset pins:
High level input voltage
VIH
VIL
VOH1
VOH2
VOL
2.0
-0.3
3.86
2.4
VCC
0.8
V
V
V
Low level input voltage
High level output voltage
IOH = -4 mA VCC ≥ 4.5V
IOH = -4 mA VCC ≥ 3.0V
IOL = 4.0 mA
Low level output voltage
Input Leakage
—
.32
10
10
10
V
ILI
ILO
-10
-10
—
µA
µA
pF
VIN = .1V to VCC
Output Leakage
VOUT = .1V to VCC
Input Capacitance
(all inputs/outputs)
CINT
Tamb = 25°C; FCLK = 1 MHz (Note 1)
Operating Current
ICC Read
ICCS
—
—
10
2
mA VCC = 6.0V, CLK = 10 MHz
mA VCC = 3.6V, CLK = 2.5 MHz
Outputs open
Standby Current
—
100
50
µA
µA
VCC = 6.0V, CE = 5.8V
VCC = 3.6V, CE = 3.4V
Note 1: This parameter is initially characterized and not 100% tested.
DS21109F-page 2
2004 Microchip Technology Inc.
37LV36/65/128
2.0
DATA
8.0
CASCADING SERIAL EPROMS
Cascading Serial EPROMs provide additional memory
for multiple FPGAs configured as a daisy-chain, or for
future applications requiring larger configuration mem-
ories.
2.1
Data I/O
Three-state DATA output for reading and input during
programming.
When the last bit from the first Serial EPROM is read,
the next clock signal to the Serial EPROM asserts its
CEO output LOW and disables its DATA line. The sec-
ond Serial EPROM recognizes the LOW level on its CE
input and enables its DATA output.
3.0
CLK
3.1
Clock Input
Used to increment the internal address and bit counters
for reading and programming.
When configuration is complete, the address counters
of all cascaded Serial EPROMs are reset if RESET
goes LOW forcing the RESET/OE on each Serial
EPROM to go HIGH. If the address counters are not to
be reset upon completion, then the RESET/OE inputs
can be tied to ground.
4.0
RESET/OE
4.1
Reset Input and Output Enable
A LOW level on both the CE and RESET/OE inputs
enables the data output driver. A HIGH level on
RESET/OE resets both the address and bit counters.
In the 37LVXXX, the logic polarity of this input is pro-
grammable as either RESET/OE or OE/RESET. This
document describes the pin as RESET/OE although
the opposite polarity is also possible. This option is
defined and set at device program time.
Additional logic may be required if cascaded memories
are so large that the rippled chip enable is not fast
enough to activate successive Serial EPROMs.
9.0
STANDBY MODE
The 37LVXXX enters a low-power Standby Mode
whenever CE is HIGH. In Standby Mode, the Serial
EPROM consumes less than 100 µA of current. The
output will remain in a high-impedance state regardless
of the state of the OE input.
5.0
CE
5.1
Chip Enable Input
10.0 PROGRAMMING MODE
CE is used for device selection. A LOW level on both
CE and OE enables the data output driver. A HIGH
level on CE disables both the address and bit counters
and forces the device into a low power mode.
Programming Mode is entered by holding VPP HIGH
(+13 volts) for two clock edges and then holding VPP =
VDD for one clock edge. Programming mode is exited
by driving a LOW on both CE and OE and then remov-
ing power from the device. Figures 4 through 7 show
the programming algorithm.
6.0
CEO
6.1
Chip Enable Output
11.0 37LVXXX RESET POLARITY
This signal is asserted LOW on the clock cycle follow-
ing the last bit read from the memory. It will stay LOW
as long as CE and OE are both LOW. It will then follow
CE until OE goes HIGH. Thereafter, CEO will stay
HIGH until the entire EPROM is read again. This pin
also used to sense the status of RESET polarity when
Programming Mode is entered.
The 37LVXXX lets the user choose the reset polarity as
either RESET/OE or OE/RESET. Any third-party com-
mercial programmer should prompt the user for the
desired reset polarity.
The programming of the overflow word should be han-
dled transparently by the EPROM programmer; it is
mentioned here as supplemental information only.
7.0
VPP
The polarity is programmed into the first overflow word
location, maximum address+1. 00000000 in these
locations makes the reset active LOW, FFFFFFFF in
these locations makes the reset active HIGH. The
default condition is RESET active HIGH.
7.1
Programming Voltage Supply
Used to enter programming mode (+13 volts) and to
program the memory (+13 volts). Must be connected
directly to Vcc for normal Read operation. No over-
shoot above +14 volts is permitted.
2004 Microchip Technology Inc.
DS21109F-page 3
37LV36/65/128
FIGURE 11-1: READ CHARACTERISTICS TIMING
TABLE 11-1: READ CHARACTERISTICS
AC Testing Waveform: VIL = 0.2V; VIH = 3.0V
AC Test Load: 50 pF
VOL = VOL_MAX; VOH = VOH_MIN
Limits 3.0V ≤
Vcc ≤ 6.0V
Limits 4.5V ≤
Vcc ≤ 6.0V
Symbol
Parameter
Units
Conditions
Min.
Max.
Min.
Max.
TOE
TCE
OE to Data Delay
—
—
45
60
200
—
—
—
—
0
45
50
60
—
50
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
CE to Data Delay
TCAC
TOH
TDF
TLC
CLK to Data Delay
—
Data Hold from CE, OE or CLK
CE or OE to Data Float Delay
CLK Low Time
0
—
50
—
—
25
25
25
Notes 1, 2
Note 1
100
100
40
THC
TSCE
CLK High Time
—
CE Set up Time to CLK
—
(to guarantee proper counting)
TSCED
THCE
CE setup time to CLK
(to guarantee proper DATA read)
100
0
—
—
—
80
0
—
—
—
—
10
ns
ns
CE Hold Time to CLK
(to guarantee proper counting)
Note 1
THCED
THOE
CE hold time to CLK
(to guarantee proper DATA read)
50
100
—
0
ns
OE High Time
(Guarantees counters are Reset)
20
—
ns
CLK max Clock Frequency
2.5
MHz
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kΩ to VLOAD = VCC/2.
DS21109F-page 4
2004 Microchip Technology Inc.
37LV36/65/128
FIGURE 11-2: READ CHARACTERISTICS AT END OF ARRAY TIMING
TABLE 11-2: READ CHARACTERISTICS AT END OF ARRAY
AC Testing Waveform: VIL = 0.2V; VIH = 3.0V
AC Test Load: 50 pF
VOL = VOL_MAX; VOH = VOH_MIN
Limits 3.0V ≤ Vcc ≤ Limits 4.5V ≤ Vcc ≤
6.0V
6.0V
Symbol
Parameter
Units
Conditions
Min.
Max.
Min.
Max.
TCDF
TOCK
TOCE
TOOE
CLK to Data Float Delay
CLK to CEO Delay
—
—
—
—
50
65
45
45
—
—
—
—
50
40
40
40
ns
ns
ns
ns
Notes 1, 2
CE to CEO Delay
RESET/OE to CEO Delay
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kΩ to VLOAD = VCC/2.
2004 Microchip Technology Inc.
DS21109F-page 5
37LV36/65/128
TABLE 11-3: PIN ASSIGNMENTS IN THE PROGRAMMING MODE
DIP/SOIC
PLCC Pin
Name
DATA
CLK
I/O
I/O
I
Description
Pin
The rising edge of the clock shifts a data word in or out of the
EPROM one bit at a time.
1
2
4
2
3
Clock Input. Used to increment the internal address/word
counter for reading and programming operation.
6
8
RESET/OE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
Note 1: Any modified polarity of the RESET/OE pin is
ignored in the programming mode.
4
CE
I
The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
5
6
10
14
VSS
Ground pin.
CEO
O
The polarity of the RESET/OE pin can be read by sensing the
CEO pin.
Note 1: The polarity of the RESET/OE pin is ignored while in
the Programming Mode. In final verification, this pin
must be monitored to go LOW one clock cycle after
the last data bit has been read.
7
8
17
20
VPP
VCC
Programming Voltage Supply. Programming Mode is entered
by holding CE and OE HIGH and VPP at VPP1 for two rising
clock edges and then lowering VPP to VPP2 for one more ris-
ing clock edge. A word is programmed by strobing the device
with VPP for the duration TPGM. VPP must be tied to VCC for
normal read operation.
+5 V power supply input.
DS21109F-page 6
2004 Microchip Technology Inc.
37LV36/65/128
TABLE 11-4: DC PROGRAMMING SPECIFICATIONS
Limits
Units
Symbol
Parameter
Ambient Temperature: Tamb = 25°C ±5°C
Min.
Max.
VCCP
VIL
Supply voltage during programming
Low-level input voltage
5.0
0.0
2.4
—
6.0
0.5
V
V
VIH
High-level input voltage
VCC
0.4
V
VOL
Low-level output voltage
V
VOH
VPP1
VPP2
IPPP
IL
High-level output voltage
3.7
12.5
VCCP
—
—
V
Programming voltage*
13.5
VCCP+1
100
10
V
Programming Mode access voltage
Supply current in Programming Mode
Input or output leakage current
First pass Low-level supply voltage for final verification
Second pass High-level supply voltage for final verification
V
mA
µA
V
-10
2.8
6.4
VCCL
VCCH
3.0
6.6
V
* No overshoot is permitted on this signal. VPP must not be allowed to exceed 14 volts.
TABLE 11-5: AC PROGRAMMING SPECIFICATIONS (SEE NOTE 2)
Limits
Max.
Symbol
Parameter
Units
Conditions
Min.
TRPP
TFPP
TPGM
TSVC
TSVCE
TSVOE
THVC
TSDP
THDP
TLCE
TSCC
TSIC
10% to 90% Rise Time of VPP
1
µs
µs
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
90% to 10% Fall Time of VPP
1
VPP Programming Pulse Width
.50
100
100
100
300
50
1.05
VPP Setup to CLK for Entering Programming Mode
CE Setup to CLK for Entering Programming Mode
OE Setup to CLK for Entering Programming Mode
VPP Hold from CLK for Entering Programming Mode
Data Setup to CLK for Programming
Data Hold from CLK for Programming
CE Low time to clear data latches
Note 1
Note 1
Note 1
Note 1
0
100
100
100
0
CE Setup to CLK for Programming/Verifying
OE Setup to CLK for Incrementing Address Counter
OE Hold from CLK for Incrementing Address Counter
OE Hold from VPP
THIC
THOV
TPCAC
TPOH
TPCE
200
Note 1
CLK to Data Valid
400
250
Data Hold from CLK
0
CE Low to Data Valid
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: While in Programming Mode, CE should only be changed while OE is HIGH and has been HIGH for 200 ns,
and OE should only be changed while CE is HIGH and has been HIGH for 200 ns.
2004 Microchip Technology Inc.
DS21109F-page 7
37LV36/65/128
FIGURE 11-3: ENTER AND EXIT PROGRAMMING MODES
Enter Mode
Exit Mode
VCCP
VPP1
VCC
VPP
VPP2
TRPP
TSVC
TFPP
THVC
TSVC
CLK
DATA
TSVCE
CE
TSVOE
RESET/OE
FIGURE 11-4: PROGRAMMING CYCLE OVERVIEW (NO VERIFY UNTIL ENTIRE ARRAY IS
PROGRAMMED)
V
CC = VCCP
PP1
V
CC
V
VPP = VPP2
500 µs
Programming
Mode
Enter
500 µs
500 µs
Programming
Mode
500 µs
Programming
Mode
V
PP
Programming Programming
Mode
Mode
CLK
**Load
Word 1
CE low to clear
data latches
**Load
Word 2
**Load
Word 3
**Load
Word 5
Clock Increments
Address Counter
**Load
Word 4
2 CLKS
CE
RESET/OE
High if RESET/OE configured
*
*
*
*
*
CEO
Low if RESET/OE configured
** 32 Clocks
*Note: The CEO pin is high impedance when VPP = VPP
1
FIGURE 11-5: DETAILS OF PROGRAM CYCLE
DS21109F-page 8
2004 Microchip Technology Inc.
37LV36/65/128
FIGURE 11-6: READ MANUFACTURER AND DEVICE ID OVERVIEW
FIGURE 11-7: DETAILS OF READ MANUFACTURER AND DEVICE ID
2004 Microchip Technology Inc.
DS21109F-page 9
37LV36/65/128
FIGURE 11-8: 37LVXXX PROGRAMMING SPECIFICATIONS
Start
Check Device ID
Device Power Off
Device Power On
Enter Programming Mode
1. VCC = VCCP VPP = VPP2 CE = OE = VIH
2. VPP = VPP1 for 2 CLK Rising Edges
3. VPP = VPP2 for 1 CLK Rising Edge
Yes
32 bit data word to be
programmed =
FFFFFFFFhex
No
CE low to clear
EPROM internal data
latches
Load 32-bit word to be
programmed
Pulse VPP to VPP1
(13V) for Tpgm
(500 µs)
Increment Address
Counter
No
Last Word?
Yes
Exit Programming Mode
Device Power Off
Device Power On
Verify
Yes
Fail
All Data Bits (Read Mode)
VCC = VPP = VCCL and
VCC = VPP = VCCH
1st Pass?
No
Device Failure
Pass
Device Passed
DS21109F-page 10
2004 Microchip Technology Inc.
37LV36/65/128
37LV36/65/128 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
37LV36/65/128
–
I
T
/P
P = Plastic DIP, 8 lead
SN = Plastic SOIC (150 mil Body), 8 lead
L = Plastic Leaded Chip Carrier (PLCC), 20 lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
Blank = Tube
Shipping:
Device:
T = Tape and Reel
37LV128 128K Serial EPROM
37LV65 64K Serial EPROM
37LV36 36K Serial EPROM
2004 Microchip Technology Inc.
DS21109F-page 11
37LV36/65/128
NOTES:
DS21109F-page 12
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21109F-page 13
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Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
16200 Addison Road, Suite 255
Addison Plaza
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Room 401, Hongjian Building, No. 2
Fengxiangnan Road, Ronggui Town, Shunde
District, Foshan City, Guangdong 528303, China
Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
25950 Acero St., Suite 200
Mission Viejo, CA 92691
Tel: 949-462-9523
Germany
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Fax: 949-462-9608
San Jose
1300 Terra Bella Avenue
Mountain View, CA 94043
Tel: 650-215-1444
Italy
India
Via Salvatore Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
NL-5152 JR, Drunen, Netherlands
Tel: 31-416-690399
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Yusen Shin Yokohama Building 10F
3-17-2, Shin Yokohama, Kohoku-ku,
Yokohama, Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Fax: 905-673-6509
Fax: 31-416-690340
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Unit 32 41 Rawson Street
Epping 2121, NSW
Sydney, Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
United Kingdom
505 Eskdale Road
Winnersh Triangle
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
2004 Microchip Technology Inc.
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