85C82/S [MICROCHIP]
256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC8;
| 型号： | 85C82/S |
| 厂家： | 
MICROCHIP |
| 描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
85C72/82/92
1K/2K/4K 5.0V CMOS Serial EEPROM
FEATURES
PACKAGE TYPE
• Low power CMOS technology
DIP
2
• Two wire serial interface bus, I C compatible
• 5 volt only operation
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
NC
85C72
85C82
85C92
• Self-timed write cycle (including auto-erase)
• Page-write buffer
SCL
SDA
• 1ms write cycle time for single byte
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention >200 years
• 8-pin DIP or SOIC package
8-lead
SOIC
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
1
2
3
4
8
VCC
A0
85C72
85C82
85C92
- Industrial: -40˚C to +85˚C
7
6
5
NC
A1
- Automotive: -40˚C to +125˚C
SCL
SDA
A2
85C72
128 x 8
2 Bytes
85C82
256 x 8 2 x 256 x 8
2 Bytes 8 Bytes
85C92
VSS
Organization
14-lead
SOIC
Page Write
Buffer
14
13
1
2
3
4
5
6
7
NC
NC
A0
VCC
NC
NC
12
11
DESCRIPTION
A1
85C92
NC
The Microchip Technology Inc. 85C72/82/92 is a 1K/
2K/4K bit Electrically Erasable PROM. The device is
organized as shown with a two wire serial interface.
Advanced CMOS technology allows a significant
reduction in power over NMOS serial devices. The
85C72/82/92 also has a page-write capability for up to
8 bytes of data (see chart). Up to eight 85C72/82/92s
may be connected to the two wire bus. The 85C72/82/
92 is available in standard 8-pin DIP and surface mount
SOIC packages.
10
9
SCL
SDA
NC
A2
VSS
NC
8
BLOCK DIAGRAM
DATA
VCC
VPP
R/W AMP
BUFFER
VSS
(FIF0)
DATA REG.
A P
D O
D I
MEMORY
ARRAY
SDA
R N
E T
S E
S R
SLAVE ADR.
A0 to
A7
CONTROL
LOGIC
INCREMENT
SCL
A0A1 A2
I2C is a trademark of Philips Corporation
1995 Microchip Technology Inc.
DS11182C-page 1
85C72/82/92
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
VCC........................................................................ 7.0V
All inputs and outputs w.r.t. VSS ....-0.6V to VCC +1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins..................................... 4 kV
A0, A1, A2
VSS
Chip Address Inputs
Ground
SDA
Serial Address/Data Input/Output
Serial Clock
SCL
NC
No Connect
VCC
+5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +5V (10%)
Commercial
(C): Tamb = 0˚C to +70˚C
Industrial
(I):
Tamb = -40˚C to +85˚C
Automotive
(E): Tamb = -40˚C to 125˚C
Parameter
Symbol
Min
Max
Units Conditions
VCC detector threshold
VTH
2.8
4.5
V
SCL and SDA pins:
High level input voltage
VIH
VIL
VCC x 0.7 VCC + 1
V
V
V
Low level input voltage
Low level output voltage
A0, A1 & A2 pins:
-0.3
VCC X 0.3
0.4
VOL
IOL = 3.2 mA (SDA 0nly)
HIgh level input voltage
Low level input voltage
Input leakage current
Output leakage current
VIH
VIL
ILI
VCC - 0.5 VCC + 0.5
V
V
-0.3
—
0.5
10
µA
µA
pF
VIN = 0V TO Vcc
ILO
—
10
VOUT = 0V TO Vcc
Pin capacitance
(all inputs/outputs)
CIN,
COUT
—
7.0
VIN/VOUT = 0V (Note 1)
Tamb = +25˚C, f = 1 MHz
Operating current
ICCO
—
3.5
mA
mA
FCLK = 100 kHz, program cycle time = 1 ms,
VCC = 5V, Tamb = 0˚C to +70˚C
FCLK = 100 kHz, program cycle time = 1 ms,
VCC = 5V, Tamb = (I) and (E)
4.25
read cycle
ICCR
ICCS
—
—
750
100
µA
µA
VCC = 5V, Tamb = (C), (I) and (E)
Standby current
SDA=SCL=VCC=5V (no PROGRAM active)
Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STO
TSU:STA
SDA
START
STOP
DS11182C-page 2
1995 Microchip Technology Inc.
85C72/82/92
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol Min
Typ
Max
Units
Remarks
Clock frequency
Clock high time
Clock low time
FCLK
THIGH
TLOW
TR
—
4000
4700
—
—
—
—
—
—
—
100
—
kHz
ns
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
ns
TF
—
ns
THD:STA 4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA 4700
—
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
THD:DAT
TSU:DAT
TPD
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
250
300
3500
—
Note 1
TSU:STO 4700
TBUF
4700
—
Time the bus must be free
before a new transmission
can start
Input filter time constant
(SDA and SCL pins)
TI
—
—
—
100
ns
Program cycle time
TWC
.4
.4N
1
N
ms
ms
Byte Mode
Page Mode, N = # of bytes
to be written
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
FIGURE 1-2: BUS TIMING DATA
t
t
R
F
t
t
HIGH
t
LOW
SCL
t
SU:STA
t
SU:DAT
HD:DAT
t
SU:STO
t
HD:STA
SDA
IN
t
BUF
t
AA
t
AA
SDA
OUT
1995 Microchip Technology Inc.
DS11182C-page 3
85C72/82/92
3.3
Stop Data Transfer (C)
2.0
FUNCTIONAL DESCRIPTION
The 85C72/82/92 supports a bidirectional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
85C72/82/92 works as slave. Both, master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Up to eight 85C72/82/92s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs.
Other devices can be connected to the bus, but require
different device codes than the 85C72/82/92 (refer to
section Slave Address).
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
3.5
Acknowledge
• Data transfer may be initiated only when the bus
is not busy.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Note: The 85C72/82/92 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case the slave must leave the data line HIGH to enable
the master to generate the STOP condition
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START CONDITION
ADDRESS
OR
ACKNOWLEDGE
VALID
DATA ALLOWED
TO CHANGE
STOP
CONDITION
DS11182C-page 4
1995 Microchip Technology Inc.
85C72/82/92
4.0
SLAVE ADDRESS
5.0
BYTE PROGRAM MODE
The chip address inputs A0, A1 and A2 of each 85C72/
82/92 must be externally connected to either VCC or
ground (VSS), assigning to each 85C72/82/92 a unique
3-bit address. Up to eight 85C72/82/92s may be con-
nected to the bus. Chip selection is then accomplished
through software by setting the bits A0, A1 and A2 of
the transmitted slave address to the corresponding
hardwired logic levels of the selected 85C72/82/92.
In this mode, the master sends addresses and one
data byte to the 85C72/82/92.
Following the START condition, the device code (4-bit),
the slave address (3-bit), and the R/Wbit, which is logic
LOW, are placed onto the bus by the master. This indi-
cates to the addressed 85C72/82/92 that a byte with a
word address will follow after it has generated an
acknowledge bit. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 85C72/82/92. After
receiving the acknowledge of the 85C72/82/92, the
master device transmits the data word to be written into
the addressed memory location. The 85C72/82/92
acknowledges again and the master generates a
STOP condition. This initiates the internal program-
ming cycle of the 85C72/82/92 (see Figure 6-1).
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 85C72/82/92, followed by the chip
address bits A0, A1 and A2. In the 85C92 the seventh
bit of that byte (BA) is used to select the upper block
(addresses 100 - 1FF) or the lower block (000 - FFF) of
the array.
The eighth bit of slave address determines if the master
device wants to read or write to the 85C72/82/92 (see
Figure 4-1).
6.0
PAGE PROGRAM MODE
To program the 85C72/82/92, the master sends
addresses and data to the 85C72/82/92 which is the
slave (see Figure 6-1). This is done by supplying a
START condition followed by the 4-bit device code, the
3-bit slave address, and the R/Wbit which is defined as
a logic LOW for a write. This indicates to the addressed
slave that a word address will follow so the slave out-
puts the acknowledge pulse to the master during the
ninth clock pulse. When the word address is received
by the 85C72/82/92, it places it in the lower 8 bits of the
address pointer defining which memory location is to
be written. The 85C72/82/92 will generate an acknowl-
edge after every 8 bits received and store them con-
secutively in a 2-byte RAM until a stop condition is
detected which initiates the internal programming
cycle. If more than 2 bytes are transmitted by the mas-
ter, the 85C72/82/92 will terminate the write cycle. This
does not affect erase/write cycles of the EEPROM
array.
The 85C72/82/92 monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 4-1: SLAVE ADDRESS
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
If the master generates a STOP condition after trans-
mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received (up to two) data bytes will
be written in a serial manner.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 2).
FIGURE 6-1: PROGRAM MODE (ERASE/WRITE)
ACKNOWLEDGES FROM SLAVE
SLAVE
ADDRESS
WORD
ADDRESS
START
0 A
A
DATA BYTE 1
A
P
DATA BYTE N A STOP
R/W
1995 Microchip Technology Inc.
DS11182C-page 5
85C72/82/92
7.0
ACKNOWLEDGE POLLING
8.0
READ MODE
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
read or write command. See Figure 7-1 for flow dia-
gram.
This mode illustrates master device reading data from
the 85C72/82/92.
As can be seen from Figure 8-1, the master first sets up
the slave and word addresses by doing a write.
Note: Although this is a read mode, the address
pointer must be written to.
During this period the 85C72/82/92 generates the nec-
essary acknowledge bits as defined in the appropriate
section.
The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs
the data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This autoincrement sequence is
only aborted when the master sends a STOP condition
instead of an acknowledge.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Note 1: If the master knows where the address
pointer is, it can begin the read sequence
at point ‘R’ indicated on Figure 8-1 and
save time transmitting the slave and word
addresses.
Send Start
Note 2: In all modes, the address pointer will auto-
matically increment from the end of the
memory block (256 byte) back to the first
location in that block.
Send Control Byte
with R/W = 0
Did Device
No
Acknowledge
(ACK = 0)?
Yes
Next
Operation
FIGURE 8-1: READ MODE
ACKNOWLEDGES FROM MASTER RECEIVER
LAST
ACKNOWLEDGES FROM SLAVE RECEIVER
SLAVE
ADDRESS
SLAVE
START
0 A WORD ADDRESS A START
1 A
A
STOP
DATA BYTE 1
DATA BYTE
ADDRESS
R/W
R
R/W
AUTO INCREMENT
WORD ADDRESS
DS11182C-page 6
1995 Microchip Technology Inc.
85C72/82/92
9.0
PIN DESCRIPTION
9.1
A0, A1 and A2 Chip Address Inputs
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true. For 85C92, A0 is no
function.
Up to eight 85C72/82s or four 85C92s can be con-
nected to the bus.
These inputs must be connected to either VSS or VCC.
9.2
SDASerialAddress/DataInput/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10KW). For normal data trans-
fer SDA is allowed to change only during SCL LOW.
Changes during SCL HIGH are reserved for indicating
the START and STOP conditions.
9.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
9.4
NC No Connect
This pin can be left open or used as a tie point.
Note 1: A “page” is defined as the maximum num-
ber of bytes that can be programmed in a
single write cycle. The 85C72/82 page is
2 bytes long and the 85C92 page is 8
bytes long.
Note 2: A “block” is defined as a continuous area
of memory with distinct boundaries. The
address pointer can not cross the bound-
ary from one block to another. It will, how-
ever, wrap around from the end of a block
to the first location in the same block. The
85C72/82 has only one block (256 bytes),
while the 85C92 has two blocks of 256
bytes each.
1995 Microchip Technology Inc.
DS11182C-page 7
85C72/82/92
85C72/82/92 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
85C82 - /P
Package:
P = Plastic DIP (300 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
SL = Plastic SOIC 14-lead (85C92 only)
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
E = -40°C to +125°C
Device:
85C72
85C72T
85C82
1K CMOS Serial EEPROM
1K CMOS Serial EEPROM (Tape and Reel)
2K CMOS Serial EEPROM
85C82
2K CMOS Serial EEPROM (Tape and Reel)
4K CMOS Serial EEPROM
4K CMOS Serial EEPROM (Tape and Reel)
85C92
85C92T
EUROPE
AMERICAS (continued)
AMERICAS
United Kingdom
San Jose
Corporate Office
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 0 1628 851077 Fax: 44 0 1628 850259
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.mchip.com/biz/mchip
Tel: 408 436-7950 Fax: 408 436-7955
ASIA/PACIFIC
Hong Kong
Microchip Technology
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Metroplaza
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Tel: 852 2 401 1200 Fax: 852 2 401 3431
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2 Rue du Buisson aux Fraises
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Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
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D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Atlanta
Microchip Technology Inc.
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Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
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Marlborough, MA 01752
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Tel: 82 2 554 7200 Fax: 82 2 558 5934
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Tel: 508 480-9990
Fax: 508 480-8575
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Chicago
Microchip Technology Inc.
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Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
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Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
Dayton
Microchip Technology Inc.
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JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
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Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Englewood, OH 45322
Tel: 513 832-2543 Fax: 513 832-2841
9/5/95
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
Printed in the USA, 9/95
1995, Microchip Technology Incorporated
"Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products
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The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11182C-page 8
1995 Microchip Technology Inc.
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