93AA66-P_技术文档

93AA46/56/66

1K/2K/4K 1.8V Microwire Serial EEPROM

FEATURES

PACKAGE TYPES

DIP

• Single supply with programming operation down

to 1.8V

CS

CLK

DI

1

2

3

4

8

7

6

5

V_CC

NU

• Low power CMOS technology

- 70 µA typical active READ current at 1.8V

- 2 µA typical standby current at 1.8V

• ORG pin selectable memory conﬁguration

- 128 x 8- or 64 x 16-bit organization (93AA46)

ORG

V_SS

DO

- 256 x 8- or 128 x 16-bit organization

(93AA56)

SOIC

- 512 x 8 or 256 x 16 bit organization (93AA66)

1

2

3

4

8

7

6

5

V_CC

NU

CS

• Self-timed ERASE and WRITE cycles

(including auto-erase)

CLK

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

ORG

V_SS

DI

DO

SOIC

• 10,000,000 ERASE/WRITE cycles guaranteed on

93AA56 and 93AA66

1

2

3

4

8

7

6

5

ORG

Vss

DO

DI

NU

Vcc

CS

• 1,000,000 E/W cycles guaranteed on 93AA46

• Data retention > 200 years

• 8-pin PDIP/SOIC

(SOIC in JEDEC and EIAJ standards)

• Temperature ranges supported

CLK

- Commercial (C):

0°C to +70°C

DESCRIPTION

BLOCK DIAGRAM

The Microchip Technology Inc. 93AA46/56/66 are 1K,

2K and 4K low voltage serial Electrically Erasable

PROMs. The device memory is conﬁgured as x8 or x16

bits depending on the ORG pin setup. Advanced

CMOS technology makes these devices ideal for low

power non-volatile memory applications. The 93AA

Series is available in standard 8-pin DIP and surface

mount SOIC packages. The rotated pin-out 93AA46X/

56X/66X are offered in the “SN” package only.

VCC

VSS

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

COUNTER

OUTPUT

BUFFER

DATA REGISTER

DO

DI

MODE

DECODE

LOGIC

ORG

CS

CLOCK

GENERATOR

CLK

Microwire is a registered trademark of National Semiconductor Incorporated.

1996 Microchip Technology Inc.

DS20067G-page 1

This document was created with FrameMaker 4 0 4

93AA46/56/66

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings

CS

CLK

DI

Chip Select

VCC ............................................................................ 7.0V

All inputs and outputs w.r.t. VSS..........-0.6V to VCC +1.0V

Storage temperature................................-65˚C to +150˚C

Ambient temp. with power applied...........-65˚C to +125˚C

Soldering temperature of leads (10 seconds)........+300˚C

ESD protection on all pins ......................................... 4 kV

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DO

VSS

ORG

NU

Memory Conﬁguration

Not Utilized

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

VCC

Power Supply

TABLE 1-2:

DC AND AC ELECTRICAL CHARACTERISTICS

VCC = +1.8V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Parameter

Symbol

Min

Typ

Max

Units

Conditions

High level input voltage

Low level input voltage

Low level output voltage

High level output voltage

VIH1

VIH2

VIL1

2.0

0.7 VCC

-0.3

—

2.4

VCC-0.2

-10

—

VCC+1

0.8

0.2 VCC

0.4

0.2

—

10

V

VCC ≥ 2.7V

VCC < 2.7V

VCC ≥ 2.7V

VCC < 2.7V

IOL = 2.1 mA; VCC = 4.5V

IOL = 100µA; VCC = 1.8V

IOH = -400 µA; VCC = 4.5V

IOH = -100 µA; VCC = 1.8V

VIN = 0.1V to VCC

VIL2

VOL1

VOL2

VOH1

VOH2

ILI

Input leakage current

Output leakage current

Pin capacitance

(all inputs/outputs)

Operating current

µA

pF

ILO

CIN, COUT

10

7

VOUT = 0.1V to VCC

—

VIN/VOUT = 0V (Note 1 & 2)

Tamb = +25˚C, FCLK = 1 MHz

FCLK=2 MHz; VCC=5.5V (Note 2)

FCLK = 2 MHz; VCC = 5.5V

FCLK = 1 MHz; VCC = 3.0V

FCLK = 1 MHz; VCC = 1.8V

CLK = CS = 0V; VCC = 5.5V

CLK = CS = 0V; VCC = 3.0V

CLK = CS = 0V; VCC = 1.8V

VCC ≥ 4.5V

ICC write

ICC read

—

3

1

500

mA

µA

MHz

ns

70

2

Standby current

Clock frequency

ICCS

100

30

FCLK

2

1

VCC < 4.5V

Clock high time

Clock low time

TCKH

TCKL

TCSS

TCSH

TCSL

TDIS

TDIH

TPD

TCZ

TSV

TWC

TEC

TWL

250

50

Chip select setup time

Chip select hold time

Chip select low time

Data input setup time

Data input hold time

Data output delay time

Data output disable time

Status valid time

Relative to CLK

0

250

100

ns

Relative to CLK

CL = 100 pF

CL = 100 pF (Note 2)

CL = 100 pF

ERASE/WRITE mode

ERAL mode (Vcc = 5V ± 10%)

WRAL mode (Vcc = 5V ± 10%)

400

100

500

10

15

30

ns

Program cycle time

4

8

16

ms

Endurance

93AA46

—

1M

10M

—

1M

10M

—

25°C, Vcc = 5.0V, Block Mode

(Note 3)

93AA56/66

Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

DS20067G-page 2

1996 Microchip Technology Inc.

93AA46/56/66

TABLE 1-3:

INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

A5 A4 A3 A2 A1 A0

—

D15 - D0

High-Z

25

9

1

1 X X X X

A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

9

1

0

X

—

9

WRITE

WRAL

EWDS

A5 A4 A3 A2 A1 A0

D15 - D0

—

25

9

0

1

0

X

TABLE 1-4:

INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

High-Z

18

10

18

10

1

1 X X X X X

A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

1

0

X

—

WRITE

WRAL

EWDS

A6 A5 A4 A3 A2 A1 A0

D7 - D0

—

0

1

0

X

TABLE 1-5:

INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

X A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

High-Z

27

11

27

11

1

1 X X X X X X

X A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

1

0

X

—

WRITE

WRAL

EWDS

X A6 A5 A4 A3 A2 A1 A0

D15 - D0

—

0

1

0

X

TABLE 1-6:

INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

X A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

High-Z

20

12

20

12

1

1 X X X X X X X

X A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

1

0

X

—

WRITE

WRAL

EWDS

X A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

—

0

1

0

X

TABLE 1-7:

INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

A7 A6 A5 A4 A3 A2 A1 A0

—

D15 - D0

High-Z

27

11

27

11

1

1 X X X X X X

A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

1

0

X

—

WRITE

WRAL

EWDS

A7 A6 A5 A4 A3 A2 A1 A0

D15 - D0

—

0

1

0

X

TABLE 1-8:

INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)

Instruction

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

READ

EWEN

ERASE

ERAL

1

10

00

11

00

01

00

A8 A7 A6 A5 A4 A3 A2 A1 A0

—

D7 - D0

High-Z

20

12

20

12

1

1 X X X X X X X

A8 A7 A6 A5 A4 A3 A2 A1 A0

—

(RDY/BSY)

High-Z

1

0

X

—

WRITE

WRAL

EWDS

A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 - D0

—

0

1

0

X

1996 Microchip Technology Inc.

DS20067G-page 3

93AA46/56/66

2.4

READ

2.0

FUNCTIONAL DESCRIPTION

When the ORG pin is connected to VCC, the (x16) orga-

nization is selected. When it is connected to ground,

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16 bit (x16 organization) or 8 bit

(x8 organization) output string. The output data bits will

toggle on the rising edge of the CLK and are stable after

the speciﬁed time delay (TPD). Sequential read is pos-

sible when CS is held high. The memory data will auto-

matically cycle to the next register and output

sequentially.

the (x8) organization is selected.

Instructions,

addresses and write data are clocked into the DI pin on

the rising edge of the clock (CLK). The DO pin is nor-

mally held in a high-Z state except when reading data

from the device, or when checking the READY/BUSY

status during a programming operation. The ready/

busy status can be veriﬁed during an Erase/Write oper-

ation by polling the DO pin; DO low indicates that pro-

gramming is still in progress, while DO high indicates

the device is ready. The DO will enter the high-Z state

on the falling edge of the CS.

2.5

Erase/Write Enable and Disable

(EWEN,EWDS)

The 93AA46/56/66 power up in the Erase/Write Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or VCC is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be

used to disable all Erase/Write functions and should fol-

low all programming operations. Execution of a READ

instruction is independent of both the EWEN and

EWDS instructions.

2.1

START Condition

The START bit is detected by the device if CS and DI

are both HIGH with respect to the positive edge of CLK

for the ﬁrst time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,

and WRAL). As soon as CS is HIGH, the device is no

longer in the standby mode.

2.6

ERASE

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

The ERASE instruction forces all data bits of the spec-

iﬁed address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new start condition is

detected.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the speciﬁed address has been erased

and the device is ready for another instruction.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins

together. However, with this conﬁguration it is possible

for a “bus conﬂict” to occur during the “dummy zero” that

precedes the READ operation, if A0 is a logic HIGH

level. Under such a condition the voltage level seen at

Data Out is undeﬁned and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin.

The ERASE cycle takes 4 ms per word typical.

2.7

WRITE

The WRITE instruction is followed by 16 bits (or by 8

bits) of data which are written into the speciﬁed

address. After the last data bit is put on the DI pin, CS

must be brought low before the next rising edge of the

CLK clock. This falling edge of CS initiates the self-

timed auto-erase and programming cycle.

2.3

Data Protection

During power-up, all programming modes of operation

are inhibited until VCC has reached a level greater than

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

VCC has fallen below 1.4V at nominal conditions.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the speciﬁed address has been written with the data

speciﬁed and the device is ready for another instruc-

tion.

The EWEN and EWDS commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

The WRITE cycle takes 4 ms per word typical.

DS20067G-page 4

1996 Microchip Technology Inc.

93AA46/56/66

2.8

Erase All (ERAL)

2.9

Write All (WRAL)

The ERAL instruction will erase the entire memory

array to the logical “1” state. The ERAL cycle is identical

to the ERASE cycle except for the different opcode. The

ERAL cycle is completely self-timed and commences at

the falling edge of the CS. Clocking of the CLK pin is not

necessary after the device has entered the self clocking

mode. The ERAL instruction is guaranteed at 5V ±

10%.

The WRALinstruction will write the entire memory array

with the data speciﬁed in the command. The WRAL

cycle is completely self-timed and commences at the

falling edge of the CS. Clocking of the CLK pin is not

necessary after the device has entered the self clocking

mode. The WRAL command does include an auto-

matic ERAL cycle for the device. Therefore, the WRAL

instruction does not require an ERAL instruction but the

chip must be in the EWEN status. The WRAL instruc-

tion is guaranteed at 5V ± 10%.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

The ERAL cycle takes (8 ms typical).

The WRAL cycle takes 16 ms typical.

FIGURE 2-1: SYNCHRONOUS DATA TIMING

VIH

CS

TCSS

TCKH

TCKL

VIL

TCSH

VIH

CLK

DI

VIL

TDIH

TDIS

VIH

VIL

TCZ

TPD

T PD

VOH

DO

(READ)

T CZ

VOL

VOH

TSV

DO

(PROGRAM)

STATUS VALID

VOL

FIGURE 2-2: READ TIMING

TCSL

CS

CLK

DI

1

0

• A

• • •

A0

n

TRI-STATE

TRI-STATE™

DO

0

Dx

• • •

D0

Dx*

• • •

D0

Dx*

• • •

D0

Tri-State is a registered trademark of National Semiconductor Incorporated.

1996 Microchip Technology Inc.

DS20067G-page 5

93AA46/56/66

FIGURE 2-3: EWEN TIMING

T

CSL

CS

CLK

DI

• • •

1

0

1

X

FIGURE 2-4: EWDS TIMING

TCSL

CS

CLK

DI

• • •

1

0

X

FIGURE 2-5: WRITE TIMING

TCSL

CS

CLK

• • •

1

0

1

•A

A0

Dx

D0

DI

n

TRI-STATE

BUSY

DO

READY

TWC

DS20067G-page 6

1996 Microchip Technology Inc.

93AA46/56/66

FIGURE 2-6: WRAL TIMING

TCSL

CS

STANDBY

CLK

1

0

1

X

• • •

X

Dx

• • •

D0

DI

TRI-STATE

BUSY

READY

TRI-STATE

DO

TWL

Guaranteed at Vcc = +4.5V to +6.0V.

FIGURE 2-7: ERASE TIMING

TCSL

CS

STANDBY

CHECK STATUS

CLK

1

An An-1 An-2 • • •

A0

DI

TCZ

TSV

BUSY

TRI-STATE

READY

DO

TWC

FIGURE 2-8: ERAL TIMING

TCSL

CS

STANDBY

CHECK STATUS

CLK

1

0

1

0

DI

TCZ

TSV

TRI-STATE

READY

BUSY

DO

TEC

• Guaranteed at VCC = 5.0V ±10%.

1996 Microchip Technology Inc.

DS20067G-page 7

93AA46/56/66

3.4

Data Out (DO)

3.0

PIN DESCRIPTION

Data Out is used in the READ mode to output data syn-

chronously with the CLK input (TPD after the positive

edge of CLK).

3.1

Chip Select (CS)

A HIGH level selects the device. A LOW level deselects

the device and forces it into standby mode. However, a

programming cycle which is already initiated and/or in

progress will be completed, regardless of the CS input

signal. If CS is brought LOW during a program cycle,

the device will go into standby mode as soon as the pro-

gramming cycle is completed.

This pin also provides READY/BUSYstatus information

during ERASE and WRITE cycles. READY/BUSY sta-

tus information is available on the DO pin if CS is

brought HIGH after being LOW for minimum chip select

LOW time (TCSL) and an ERASE or WRITE operation

has been initiated.

CS must be LOW for 250 ns minimum (TCSL) between

consecutive instructions. If CS is LOW, the internal con-

trol logic is held in a RESET status.

The status signal is not available on DO, if CS is held

LOW or HIGH during the entire WRITE or ERASE

cycle. In all other cases DO is in the HIGH-Z mode. If

status is checked after the WRITE/ERASE cycle, a pull-

up resistor on DO is required to read the READY signal.

3.2

Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93AAXX.

Opcode, address, and data bits are clocked in on the

positive edge of CLK. Data bits are also clocked out on

the positive edge of CLK.

3.5

Organization (ORG)

When ORG is connected to VCC, the (x16) memory

organization is selected. When ORG is tied to VSS, the

(x8) memory organization is selected. ORG can only be

ﬂoated for clock speeds of 1MHz or less for the (x16)

memory organization. For clock speeds greater than 1

MHz, ORG must be tied to VCC or VSS.

CLK can be stopped anywhere in the transmission

sequence (at HIGH or LOW level) and can be continued

anytime with respect to clock HIGH time (TCKH) and

clock LOW time (TCKL). This gives the controlling mas-

ter freedom in preparing opcode, address, and data.

CLK is a “Don't Care” if CS is LOW (device deselected).

If CS is HIGH, but START condition has not been

detected, any number of clock cycles can be received

by the device without changing its status (i.e., waiting

for START condition).

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

After detection of a start condition the speciﬁed number

of clock cycles (respectively LOW to HIGH transitions of

CLK) must be provided. These clock cycles are

required to clock in all required opcode, address, and

data bits before an instruction is executed (see instruc-

tion set truth table). CLK and DI then become don't care

inputs waiting for a new start condition to be detected.

Note: CS must go LOW between consecutive

instructions.

3.3

Data In (DI)

Data In is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

DS20067G-page 8

1996 Microchip Technology Inc.

93AA46/56/66

NOTES:

1996 Microchip Technology Inc.

DS20067G-page 9

93AA46/56/66

NOTES:

DS20067G-page 10

1996 Microchip Technology Inc.

93AA46/56/66

93AA46/56/66 Product Identiﬁcation System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

93AA46/56/66

-

/P

Package:

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

(93AA46/56/66)

Temperature

Range:

Blank = 0°C to +70°C

Device:

Microwire Serial EEPROM

93AA46/56/66

Microwire Serial EEPROM in alternate

pinouts (SN package only)

93AA46/56/66X

93AA46T/56T/66T

93AA46XT/56XT/66XT

Microwire Serial EEPROM (Tape and Reel)

1996 Microchip Technology Inc.

DS20067G-page 11

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14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 972 991-7177 Fax: 972 991-8588

Dayton

Microchip Technology Inc.

Suite 150

Arizona Microchip Technology SRL

Centro Direzionale Colleone Pas Taurus 1

Viale Colleoni 1

20041 Agrate Brianza

Milan Italy

Korea

Microchip Technology

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology

200 Middle Road

#10-03 Prime Centre

Singapore 188980

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan, R.O.C

Microchip Technology

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

Tel: 39 39 6899939 Fax: 39 39 689 9883

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Two Prestige Place

Miamisburg, OH 45342

Tel: 513 291-1654 Fax: 513 291-9175

Tel: 81 45 471 6166 Fax: 81 45 471 6122

9/3/96

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 714 263-1888 Fax: 714 263-1338

NewYork

Microchip Technmgy Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 436-7950 Fax: 408 436-7955

Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada

Tel: 905 405-6279 Fax: 905 405-6253

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-

sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement

of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-

rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and

DS20067G-page 12

1996 Microchip Technology Inc.


型号：	93AA66-P
厂家：	MICROCHIP
描述：	1K/2K/4K 1.8V Microwire Serial EEPROM 1K / 2K / 4K 1.8V Microwire串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总13页 (文件大小：79K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

93AA66-P [MICROCHIP]

相关型号：

93AA66-SM

93AA66-SN

93AA66/P

93AA66/SM

93AA66/SN

93AA66A

93AA66A-E/CH

93AA66A-E/MC

93AA66A-E/MCG

93AA66A-E/MS

93AA66A-E/MSG

93AA66A-E/OT