93AA76C-E/MCG [MICROCHIP]
8K Microwire Compatible Serial EEPROM; 8K的Microwire兼容串行EEPROM
| 型号： | 93AA76C-E/MCG |
| 厂家： | 
MICROCHIP |
| 描述： | 8K Microwire Compatible Serial EEPROM |
| 文件： | 总28页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
93AA76A/B/C, 93LC76A/B/C,
93C76A/B/C
8K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
VCC Range
ORG Pin
PE Pin
Word Size
Temp Ranges
Packages
93AA76A
93AA76B
93LC76A
93LC76B
93C76A
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
No
No
No
No
8-bit
16-bit
I
OT
I
OT
No
No
8-bit
I, E
I, E
I, E
I, E
I
OT
No
No
16-bit
OT
No
No
8-bit
OT
93C76B
No
No
16-bit
OT
93AA76C
93LC76C
93C76C
Yes
Yes
Yes
Yes
Yes
Yes
8 or 16-bit
8 or 16-bit
8 or 16-bit
P, SN, ST, MS, MC
P, SN, ST, MS, MC
P, SN, ST, MS, MC
I, E
I, E
Features:
Description:
• Low-power CMOS technology
The Microchip Technology Inc. 93XX76A/B/C devices
are 8K bit, low-voltage, serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX76C are dependent upon external logic levels
driving the ORG pin to set word size. In the SOT-23
package, the 93XX76A devices provide dedicated 8-bit
memory organization, while the 93XX76B devices
provide dedicated 16-bit memory organization. A
Program Enable (PE) pin allows the user to write-protect
the entire memory array. Advanced CMOS technology
makes these devices ideal for low-power, nonvolatile
memory applications. The 93XX Series is available in
standard packages including 8-lead PDIP and SOIC,
and advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All
packages are Pb-free and RoHS compliant.
• ORG pin to select word size for ‘76C’ version
• 1024 x 8-bit organization ‘A’ devices (no ORG)
• 512 x 16-bit organization ‘B’ devices (no ORG)
• Program Enable pin to write-protect the entire
array (‘76C’ version only)
• Self-timed erase/write cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
Package Types (not to scale)
• Pb-free and RoHS compliant
• Temperature ranges supported:
SOT-23
(OT)
PDIP/SOIC
(P, SN)
- Industrial (I)
-40°C to +85°C
CS
CLK
DI
1
2
3
4
8
7
6
5
V
PE
CC
1
6
5
4
- Automotive (E) -40°C to +125°C
DO
V
CC
2
3
VSS
CS
Pin Function Table
ORG
DI
CLK
DO
VSS
Name
CS
Function
Chip Select
DFN
(MC)
TSSOP/MSOP
(ST, MS)
CLK
DI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
1
VCC
CS
8
1
8
7
6
5
CS
CLK
DI
V
PE
ORG
VSS
CC
7 PE
2
3
4
CLK
DI
DO
2
3
4
DO
ORG
6
5
DO
VSS
PE
VSS
Program Enable
Memory Configuration
Power Supply
ORG
VCC
© 2006 Microchip Technology Inc.
DS21796H-page 1
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
D1
VIH1
VIH2
High-level input voltage
2.0
0.7 VCC
—
—
VCC +1
VCC +1
V
V
VCC ≥ 2.7V
VCC < 2.7V
D2
D3
D4
VIL1
VIL2
Low-level input voltage
Low-level output voltage
High-level output voltage
-0.3
-0.3
—
—
0.8
0.2 VCC
V
V
VCC ≥ 2.7V
VCC < 2.7V
VOL1
VOL2
—
—
—
—
0.4
0.2
V
V
IOL = 2.1 mA, VCC = 4.5V
IOL = 100 μA, VCC = 2.5V
VOH1
VOH2
2.4
VCC - 0.2
—
—
—
—
V
V
IOH = -400 μA, VCC = 4.5V
IOH = -100 μA, VCC = 2.5V
D5
D6
D7
ILI
Input leakage current
Output leakage current
—
—
—
—
—
—
±1
±1
7
μA
μA
pF
VIN = VSS or VCC
ILO
VOUT = VSS or VCC
CIN,
COUT
Pin capacitance (all inputs/
outputs)
VIN/VOUT = 0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D8
D9
ICC write Write current
—
—
—
500
3
—
mA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 2.5V
ICC read Read current
—
—
—
—
—
100
1
500
—
mA
μA
μA
FCLK = 3 MHz, VCC = 5.5V
FCLK = 2 MHz, VCC = 3.0V
FCLK = 2 MHz, VCC = 2.5V
D10
D11
ICCS
Standby current
—
—
—
—
1
5
μA
μA
I – Temp
E – Temp
CLK = CS = 0V
ORG = DI = PE = VSS or VCC
(Note 2) (Note 3)
VPOR
VCC voltage detect
(Note 1)
—
—
1.5
3.8
—
—
V
V
93AA76A/B/C, 93LC76A/B/C
93C76A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG and PE pins not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO, see Section 3.4 “Data Out (DO)”.
DS21796H-page 2
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
Industrial (I):
TA = -40°C to +85°C, VCC = +1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V
Param.
No.
Symbol
Parameter
Clock frequency
Min
Max
Units
Conditions
A1
FCLK
—
3
2
1
MHz 4.5V ≤ VCC < 5.5V
MHz 2.5V ≤ VCC < 4.5V
MHz 1.8V ≤ VCC < 2.5V
A2
A3
A4
TCKH
TCKL
TCSS
Clock high time
200
250
450
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
Clock low time
100
200
450
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
Chip Select setup time
50
100
250
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A5
A6
A7
TCSH
TCSL
TDIS
Chip Select hold time
Chip Select low time
Data input setup time
0
—
—
—
ns
ns
1.8V ≤ VCC < 5.5V
1.8V ≤ VCC < 5.5V
250
50
100
250
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
A8
A9
TDIH
TPD
Data input hold time
50
100
250
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
Data output delay time
—
100
250
400
ns
ns
ns
A10
A11
TCZ
TSV
Data output disable time
Status valid time
—
—
100
200
ns
ns
4.5V ≤ VCC < 5.5V, (Note 1)
1.8V ≤ VCC < 4.5V, (Note 1)
200
300
500
ns
ns
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
1.8V ≤ VCC < 2.5V, CL = 100 pF
A12
A13
TWC
TWC
Program cycle time
—
—
5
ms
Erase/Write mode (AA and LC
versions)
2
ms
Erase/Write mode
(93C versions)
A14
A15
A16
TEC
TWL
—
—
—
6
ms
ms
ERAL mode, 4.5V ≤ VCC ≤ 5.5V
WRAL mode, 4.5V ≤ VCC ≤ 5.5V
15
—
Endurance
1M
cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site
at www.microchip.com.
© 2006 Microchip Technology Inc.
DS21796H-page 3
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
VIH
VIL
VIH
CS
TCSS
TCKH
TCKL
TCSH
CLK
DI
VIL
TDIS
TDIH
VIH
VIL
TCZ
TCZ
TPD
TPD
VOH
DO
(Read)
VOL
VOH
TSV
DO
(Program)
Status Valid
VOL
Note:
TSV is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX76B OR 93XX76C WITH ORG = 1)
Req. CLK
Cycles
Instruction SB Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X
1
X
1
X
0
0
A8 A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
D15-D0
High-Z
29
13
13
13
29
29
13
1
x
x
x
x
x
x
x
x
A8 A7 A6 A5 A4 A3 A2 A1 A0
(RDY/BSY)
(RDY/BSY)
0
X
X
X
X
X
X
X
X
A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY)
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D15-D0 (RDY/BSY)
High-Z
—
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX76A OR 93XX76C WITH ORG = 0)
Req.CLK
Cycles
Instruction SB Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X
1
X
1
X
0
0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
D7-D0
High-Z
22
14
14
14
22
22
14
1
x
x
x
x
x
x
x
x
x
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
0
x
x
x
x
x
x
x
x
x
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7-D0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D7-D0
—
DS21796H-page 4
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.2
Data In/Data Out (DI/DO)
2.0
FUNCTIONAL DESCRIPTION
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high-
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
When the ORG pin (93XX76C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.3
Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
Note:
For added protection, an EWDS
command should be performed after
every write operation and an external 10
kΩ pull-down protection resistor should be
added to the CS pin.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
After power-up the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASEor WRITEinstruction
can be executed.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
Note:
To prevent accidental writes to the array in
the 93XX76C devices, set the PE pin to a
logic low.
Block Diagram
VCC
VSS
Memory
Array
Address
Decoder
Address
Counter
DO
Output
Buffer
Data Register
DI
Mode
Decode
Logic
ORG*
CS
PE*
Clock
Register
CLK
*ORG and PE inputs are not available on
A/B devices.
© 2006 Microchip Technology Inc.
DS21796H-page 5
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
The DO pin indicates the Ready/Busy status of the
2.4
Erase
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
The ERASEinstruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 2-1:
ERASE TIMING
TCSL
CS
Check Status
CLK
DI
1
1
1
AN
AN-1 AN-2
A0
•••
TSV
TCZ
High-Z
Busy
Ready
DO
High-Z
TWC
DS21796H-page 6
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
low (TCSL).
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
FIGURE 2-2:
ERAL TIMING
TCSL
CS
Check Status
CLK
DI
1
0
0
1
0
x
x
•••
TSV
TCZ
High-Z
Busy
Ready
DO
High-Z
TEC
© 2006 Microchip Technology Inc.
DS21796H-page 7
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
Once the EWEN instruction is executed, programming
remains enabled until an EWDSinstruction is executed
or VCC is removed from the device.
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
The 93XX76A/B/C powers up in the Erase/Write
Disable (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
To protect against accidental data disturbance, the
EWDSinstruction can be used to disable all erase/write
functions and should follow all programming opera-
tions. Execution of a READinstruction is independent of
both the EWENand EWDSinstructions.
FIGURE 2-3:
EWDS TIMING
TCSL
CS
CLK
DI
•••
1
0
0
0
0
x
x
FIGURE 2-4:
EWEN TIMING
TCSL
CS
CLK
DI
•••
1
0
0
1
1
x
x
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (TPD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
2.7
Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string.
FIGURE 2-5:
READ TIMING
CS
CLK
DI
An
•••
A0
1
1
0
High-Z
DO
0
Dx
D0
Dx
D0
Dx
D0
•••
•••
•••
DS21796H-page 8
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
2.8
Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data which are written into the
specified address. The self-timed auto-erase and
programming cycle is initiated by the rising edge of CLK
on the last data bit.
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 2-6:
WRITE TIMINGS
TCSL
CS
CLK
DI
0
1
1
An
A0
Dx
D0
•••
•••
TSV
TCZ
High-Z
Busy
Ready
DO
High-Z
TWC
© 2006 Microchip Technology Inc.
DS21796H-page 9
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL)..
2.9
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command does include an automatic ERAL cycle for
the device. Therefore, the WRAL instruction does not
require an ERALinstruction, but the chip must be in the
EWEN status.
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-7:
WRAL TIMING
TCSL
CS
CLK
DI
0
0
0
1
x
1
•••
Dx
•••
x
D0
TSV
TCZ
High-Z
Busy Ready
DO
High-Z
TWL
DS21796H-page 10
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
3.0
PIN DESCRIPTIONS
TABLE 3-1:
Name
PIN DESCRIPTIONS
SOIC/PDIP/MSOP/
TSSOP/DFN
SOT-23
Function
CS
1
2
3
4
5
6
7
8
5
4
Chip Select
Serial Clock
Data In
CLK
DI
3
DO
VSS
ORG
PE
1
Data Out
Ground
2
—
—
6
Organization / 93XX76C
Program Enable
VCC
Power Supply
3.1
Chip Select (CS)
3.3
Data In (DI)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (TPD after the
positive edge of CLK).
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select Low Time
(TCSL) and an erase or write operation has been
initiated.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
The Status signal is not available on DO, if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
CLK can be stopped anywhere in the transmission
sequence (at high or low-level) and can be continued
anytime with respect to Clock High Time (TCKH) and
Clock Low Time (TCKL). This gives the controlling
master freedom in preparing opcode, address and
data.
Note:
After a programming cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
3.5
Organization (ORG)
CLK is a “don’t care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to VSS or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
93XX76A devices are always x8 organization and
93XX76B devices are always x16 organization.
After detection of a Start condition the specified number
of clock cycles (respectively, low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become “don’t care” inputs waiting for a new Start
condition to be detected.
© 2006 Microchip Technology Inc.
DS21796H-page 11
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
3.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is tied
to VCC, the device can be programmed. If the PE pin is
tied to VSS, programming will be inhibited. This pin
cannot be floated, it must be tied to VCC or VSS. PE is
not available on 93XX76A or 93XX76B. On those
devices, programming is always enabled.
DS21796H-page 12
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP (150 mil)
Example:
3L76CI
5281L7
XXXXXXT
YWWNNN
Example:
4EL7
6-Lead SOT-23
XXNN
SOT23 Marking Codes
Device
I-temp
E-temp
93AA76A
93AA76B
93LC76A
93LC76B
93C76A
4BNN
4LNN
4ENN
4PNN
4HNN
4TNN
–
–
4FNN
4RNN
4JNN
4UNN
Example:
93LC76C
8-Lead PDIP
93C76B
Pb-free topside mark is same; Pb-free
noted only on carton label.
XXXXXXXX
T/XXXNNN
I/P
1L7
e
3
0528
YYWW
Example:
93LC76CI
8-Lead SOIC
XXXXXXXT
SN
0528
3
e
XXXXYYWW
1L7
NNN
Example:
8-Lead TSSOP
L76C
I528
1L7
XXXX
TYWW
NNN
Example:
8-Lead 2x3 DFN
3B4
528
L7
XXX
YWW
NN
© 2006 Microchip Technology Inc.
DS21796H-page 13
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
1st Line Marking Codes
Part Number
DFN
TSSOP
MSOP
I Temp.
E Temp.
93AA76C
A76C
3A76CT
3L76CT
3C76CT
3B1
3B4
3B7
—
93LC76C
93C76C
Note:
L76C
C76C
3B5
3B8
T = Temperature grade (I, E)
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note:
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS21796H-page 14
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
2
b
1
e
c
ϕ
A2
A
L1
L
A1
Units
MILLIMETERS
Dimension Limits
NOM
8
MAX
MIN
Number of Pins
Pitch
N
e
0.65 BSC
—
—
Overall Height
A
1.10
0.95
0.15
0.75
0.00
0.85
Molded Package Thickness
Standoff
A2
A1
E
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
0.40
L
0.80
0.95 REF
—
Footprint
L1
0°
Foot Angle
ϕ
8°
0.08
0.22
—
Lead Thickness
Lead Width
c
0.23
0.40
—
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21796H-page 15
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
6-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
D
n
1
α
c
A
φ
A2
A1
β
L
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
MIN
NOM
6
MAX
n
p
Number of Pins
Pitch
6
.038 BSC
.075 BSC
0.95 BSC
1.90 BSC
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
p1
Outside lead pitch
Overall Height
A
A2
A1
E
.035
.035
.000
.102
.046
.057
0.90
1.45
Molded Package Thickness
Standoff
.043
.003
.110
.064
.116
.018
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
1.30
0.15
3.00
1.75
3.10
0.55
Overall Width
Molded Package Width
Overall Length
E1
D
.059
.110
.014
Foot Length
L
φ
Foot Angle
0
5
0
10
c
Lead Thickness
Lead Width
.004
.014
.006
.017
.008
.020
10
0.09
0.35
0.15
0.43
5
0.20
0.50
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
0
0
5
5
0
0
10
10
β
10
5
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
Revised 09-12-05
DS21796H-page 16
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
8
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.155
.130
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
DS21796H-page 17
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
8
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.053
.061
.056
.007
.237
.154
.193
.015
.025
4
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21796H-page 18
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
e
D
2
1
n
b
α
c
ϕ
A
β
A2
L
A1
Units
Dimension Limits
MILLIMETERS*
INCHES
NOM
MIN
MAX
MIN
NOM
8
0.65 BSC
MAX
Number of Pins
Pitch
n
e
A
8
.026 BSC
Overall Height
–
–
1.20
–
–
.047
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Molded Package Length
Foot Length
A2
A1
E
E1
D
L
0.80
0.05
1.00
1.05
0.15
.031
.002
.039
.041
.006
–
6.40 BSC
4.40
–
.252 BSC
.173
4.30
2.90
0.45
0°
4.50
3.10
0.75
8°
.169
.114
.018
0°
.177
.122
.030
8°
3.00
0.60
.118
.024
Foot Angle
ϕ
–
–
Lead Thickness
Lead Width
c
b
0.09
0.19
–
–
0.20
0.30
.004
.007
–
–
.008
.012
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12° REF
12° REF
12° REF
12° REF
*Controlling Parameter
Notes:
1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
Drawing No. C04-086
Revised 7-25-06
© 2006 Microchip Technology Inc.
DS21796H-page 19
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
e
D
b
N
N
L
K
E
E2
EXPOSED PAD
NOTE 1
NOTE 1
2
2
1
1
D2
TOP VIEW
BOTTOM VIEW
A
NOTE 2
A1
A3
Units
MILLIMETERS
Dimension Limits
NOM
8
MAX
MIN
Number of Pins
Pitch
N
e
0.50 BSC
0.90
0.80
0.00
Overall Height
Standoff
A
1.00
0.05
0.02
A1
A3
D
0.20 REF
2.00 BSC
3.00 BSC
—
Contact Thickness
Overall Length
Overall Width
E
1.30
1.50
0.18
0.30
0.20
Exposed Pad Length
Exposed Pad Width
Contact Width
D2
E2
b
1.75
1.90
0.30
0.50
—
—
0.25
0.40
Contact Length §
L
—
Contact-to-Exposed Pad §
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. § Significant Characteristic
4. Package is saw singulated
5. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–123, Sept. 8, 2006
DS21796H-page 20
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
APPENDIX A: REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
Revision D
Corrections to Device Selection Table, Table 1-1, Table
1-2, Section 2.4, Section 2.5, Section 2.8 and Section
2.9. Added note to Figure 2-7.
Revision E
Added DFN package.
Revision F
Added notes throughout.
Revision G
Revised note in Sections 2.8 and 2.9.
Replaced DFN package drawing.
Revision H
Updated Package Drawings
© 2006 Microchip Technology Inc.
DS21796H-page 21
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
NOTES:
DS21796H-page 22
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2006 Microchip Technology Inc.
DS21796H-page 23
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796H
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21796H-page 24
© 2006 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
/XX
X
PART NO.
X
X
Examples:
a)
93AA76C-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, 1.8V
Package
Device Tape & Reel
Lead Finish
Temperature
Range
b)
93AA76AT-I/OT: 8K, 1024x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
Device:
93AA76A: 8K 1.8V Microwire Serial EEPROM (x8)
93AA76B: 8K 1.8V Microwire Serial EEPROM (x16)
93AA76C: 8K 1.8V Microwire Serial EEPROM w/ORG
c)
93AA76CT-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, tape and reel, 1.8V
a)
b)
93LC76C-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, 2.5V
93LC76BT-I/OT: 8K, 512x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
93LC76A: 8K 2.5V Microwire Serial EEPROM (x8)
93LC76B: 8K 2.5V Microwire Serial EEPROM (x16)
93LC76C: 8K 2.5V Microwire Serial EEPROM w/ORG
93C76A: 8K 5.0V Microwire Serial EEPROM (x8)
93C76B: 8K 5.0V Microwire Serial EEPROM (x16)
93C76C: 8K 5.0V Microwire Serial EEPROM w/ORG
a)
b)
93C76C-I/MS: 8K, 1024x8 or 512x16 Serial
EEPROM, MSOP package, 5.0V
93C76AT-I/OT: 8K, 1024x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
Tape & Reel:
Blank
T
=
=
Standard pinout
Tape & Reel
Temperature Range:
Package:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
MS
OT
P
SN
ST
MC
=
=
=
=
=
=
Plastic MSOP (Micro Small outline, 8-lead)
SOT-23, 6-lead (Tape & Reel only)
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
2x3 DFN, 8-lead
Lead Finish:
Blank
G
=
=
Pb-free – Matte Tin (see Note 1)
Pb-free – Matte Tin only
Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured
before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).
Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.
© 2006 Microchip Technology Inc.
DS21796H-page 25
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
NOTES:
DS21796H-page 26
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21796H-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
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Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Germany - Munich
Tel: 49-89-627-144-0
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Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
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Korea - Gumi
Tel: 82-54-473-4301
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Boston
China - Chengdu
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Tel: 774-760-0087
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Tel: 86-591-8750-3506
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Chicago
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Spain - Madrid
Tel: 34-91-708-08-90
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Dallas
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China - Shanghai
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Singapore
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Kokomo
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Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
10/19/06
DS21796H-page 28
© 2006 Microchip Technology Inc.
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