93C46BT/ST [MICROCHIP]

64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, TSSOP-8;


型号：	93C46BT/ST
厂家：	MICROCHIP
描述：	64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, TSSOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
文件：	总12页 (文件大小：211K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

93C46B

1K 5.0V Microwire^®Serial EEPROM

FEATURES

BLOCK DIAGRAM

• Single supply 5.0V operation

• Low power CMOS technology

- 1 mA active current (typical)

ADDRESS

DECODER

MEMORY

ARRAY

- 1 µA standby current (maximum)

• 64 x 16 bit organization

• Self-timed ERASE and WRITE cycles (including

auto-erase)

ADDRESS

COUNTER

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial interface

• Device status signal during ERASE/WRITE

cycles

DATA

OUTPUT

BUFFER

MEMORY

DECODE

LOGIC

• Sequential READ function

• 1,000,000 E/W cycles ensured

• Data retention > 200 years

VCC

VSS

CLOCK

GENERATOR

CLK

• 8-pin PDIP/SOIC and 8-pin TSSOP packages

• Available for the following temperature ranges:

DESCRIPTION

- Commercial (C):

- Industrial (I):

0°C to

-40°C to

+70°C

+85°C

The Microchip Technology Inc. 93C46B is a 1 Kbit,

low-voltage serial Electrically Erasable PROM. The

device memory is configured as 64 x 16 bits. Advanced

CMOS technology makes this device ideal for

low-power, nonvolatile memory applications. The

93C46B is available in standard 8-pin DIP, surface

mount SOIC, and TSSOP packages. The 93C46BX are

only offered in a 150 mil SOIC package.

- Automotive (E):

-40°C to +125°C

PACKAGE TYPE

DIP

SOIC

TSSOP

VCC

VSS

VCC

CLK

VSS

CLK

VSS

CLK

VSS

Microwire is a registered trademark of National Semiconductor Incorporated.

 2001 Microchip Technology Inc.

DS21172E-page 1

93C46B

TABLE 1-1

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL

CHARACTERISTICS

1.1

Maximum Ratings*

CLK

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS .............. -0.6V to VCC +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins................................................4 kV

VSS

No Connect

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is

not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

VCC

Power Supply

TABLE 1-2

DC AND AC ELECTRICAL CHARACTERISTICS

All parameters apply over

the specified operating

ranges unless otherwise

noted

Commercial (C) VCC = +4.5V to +5.5V TAMB = 0°C to +70°C

Industrial (I)

VCC = +4.5V to +5.5V TAMB = -40°C to +85°C

Automotive (E) VCC = +4.5V to +5.5V TAMB = -40°C to +125°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High level input voltage

Low level input voltage

Low level output voltage

High level output voltage

Input leakage current

Output leakage current

VIH

VIL

2.0

-0.3

—

VCC +1

0.8

(Note 2)

—

VOL

VOH

ILI

0.4

IOL = 2.1 mA; VCC = 4.5V

IOH = -400 µA; VCC = 4.5V

VIN = VSS to VCC

2.4

-10

—

µA

ILO

VOUT = VSS to VCC

Pin capacitance

(all inputs/outputs)

VIN/VOUT = 0 V (Notes 1 & 2)

TAMB = +25°C, FCLK = 1 MHz

CIN, COUT

—

ICC read

ICC write

ICCS

FCLK

TCKH

TCKL

TCSS

TCSH

TCSL

TDIS

TDIH

TPD

—

1.5

µA

MHz

—

Operating current

—

Standby current

—

CS = VSS; DI = VSS

VCC = 4.5V

—

Clock frequency

—

Clock high time

250

—

400

100

500

Clock low time

—

Chip select setup time

Chip select hold time

Chip select low time

Data input setup time

Data input hold time

Data output delay time

Data output disable time

Status valid time

Relative to CLK

—

250

100

—

Relative to CLK

CL = 100 pF

CL = 100 pF (Note 2)

CL = 100 pF

ERASE/WRITE mode

ERAL mode

WRAL mode

TCZ

—

TSV

—

TWC

—

Program cycle time

Endurance

TEC

—

TWL

—

cycles 25°C, VCC = 5.0V, Block Mode (Note 3)

Note 1: This parameter is tested at TAMB = 25°C and FCLK = 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

3: This application is not tested but ensured by characterization. For endurance estimates in a specific applica-

tion, please consult the Total Endurance Model which may be obtained on our website:

www.microchip.com

DS21172E-page 2

 2001 Microchip Technology Inc.

93C46B

After detecting a START condition, the specified num-

ber of clock cycles (respectively low to high transitions

of CLK) must be provided. These clock cycles are

required to clock in all required opcodes, addresses,

and data bits before an instruction is executed

(Table 2-1). CLK and DI then become don't care inputs

waiting for a new START condition to be detected.

2.0

PIN DESCRIPTION

2.1

Chip Select (CS)

A high level selects the device; a low level deselects

the device and forces it into standby mode. However, a

programming cycle which is already in progress will be

completed, regardless of the Chip Select (CS) input

signal. If CS is brought low during a program cycle, the

device will go into standby mode as soon as the pro-

gramming cycle is completed.

Note: CS must go low between consecutive

instructions.

2.3

Data In (DI)

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal con-

trol logic is held in a RESET status.

Data In (DI) is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

2.4

Data Out (DO)

2.2

Serial Clock (CLK)

Data Out (DO) is used in the READ mode to output

data synchronously with the CLK input (TPD after the

positive edge of CLK).

The Serial Clock (CLK) is used to synchronize the com-

munication between a master device and the 93C46B.

Opcodes, addresses, and data bits are clocked in on

the positive edge of CLK. Data bits are also clocked out

on the positive edge of CLK.

This pin also provides READY/BUSY status informa-

tion during ERASE and WRITE cycles. READY/BUSY

status information is available on the DO pin if CS is

brought high after being low for minimum chip select

low time (TCSL) and an ERASE or WRITE operation

has been initiated.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing the opcode, address, and data.

The status signal is not available on DO, if CS is held

low during the entire ERASE or WRITE cycle. In this

case, DO is in the HIGH-Z mode. If status is checked

after the ERASE/WRITE cycle, the data line will be high

to indicate the device is ready.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but START condition has not been

detected, any number of clock cycles can be received

by the device, without changing its status (i.e., waiting

for a START condition).

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

TABLE 2-1

INSTRUCTION SET FOR 93C46B

Instruction

Opcode

Address

Data In

Data Out

Req. CLK Cycles

—

(RDY/BSY)

HIGH-Z

ERASE

ERAL

—

EWDS

EWEN

READ

WRITE

WRAL

—

HIGH-Z

—

D15 - D0

(RDY/BSY)

 2001 Microchip Technology Inc.

DS21172E-page 3

93C46B

3.2

Data In (DI) and Data Out (DO)

3.0

FUNCTIONAL DESCRIPTION

Instructions, addresses and write data are clocked into

the DI pin on the rising edge of the clock (CLK). The DO

pin is normally held in a HIGH-Z state except when

reading data from the device, or when checking the

READY/BUSY status during a programming operation.

The READY/BUSY status can be verified during an

ERASE/WRITE operation by polling the DO pin; DO

low indicates that programming is still in progress,

while DO high indicates the device is ready. The DO will

enter the HIGH-Z state on the falling edge of the CS.

It is possible to connect the Data In (DI)and Data Out

(DO) pins together. However, with this configuration, if

A0 is a logic-high level, it is possible for a “bus conflict”

to occur during the “dummy zero” that precedes the

READ operation. Under such a condition, the voltage

level seen at DO is undefined and will depend upon the

relative impedances of DO and the signal source driv-

ing A0. The higher the current sourcing capability of A0,

the higher the voltage at the DO pin.

3.3

Data Protection

3.1

START Condition

During power-up, all programming modes of operation

are inhibited until Vcc has reached a level greater than

3.8V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

Vcc has fallen below 3.8V at nominal conditions.

The START bit is detected by the device if CS and DI

are both high with respect to the positive edge of CLK

for the first time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,

and WRAL). As soon as CS is high, the device is no

longer in the standby mode.

The ERASE/SRITE Disable (EWDS) and ERASE/

WRITE Enable (EWEN) commands give additional

protection against accidental programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction

can be executed.

An instruction following a START condition will only be

executed if the required amount of opcodes,

addresses, and data bits for any particular instruction is

clocked in.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don’t care bits until a new START condition is

detected.

FIGURE 3-1: SYNCHRONOUS DATA TIMING

VIH

TCSS

TCKH

TCKL

VIL

VIH

TCSH

CLK

VIL

TDIS

TDIH

VIH

VIL

TCZ

TPD

VOH

(READ)

TCZ

VOL

VOH

TSV

STATUS VALID

(PROGRAM)

VOL

Note: AC test conditions: VIL = 0.4V, VIH = 2.4V

DS21172E-page 4

 2001 Microchip Technology Inc.

93C46B

3.4

ERASE

3.5

Erase All (ERAL)

The ERASE instruction forces all data bits of the spec-

ified address to the logical “1” state. This cycle begins

on the rising clock edge of the last address bit.

The Erase All (ERAL) instruction will erase the entire

memory array to the logical “1” state. The ERAL cycle

is identical to the ERASE cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the rising clock edge of the last address

bit. Clocking of the CLK pin is not necessary after the

device has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the specified address has been erased

and the device is ready for another instruction.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire ERAL cycle is

complete.

FIGURE 3-2: ERASE TIMING

TCSL

CHECK STATUS

CLK

AN-1 AN-2

•••

TSV

TCZ

HIGH-Z

BUSY

READY

HIGH-Z

TWC

FIGURE 3-3: ERAL TIMING

TCSL

CHECK STATUS

CLK

•••

TSV

TCZ

HIGH-Z

BUSY

READY

HIGH-Z

TEC

 2001 Microchip Technology Inc.

DS21172E-page 5

93C46B

3.6

ERASE/WRITE Disable and Enable

(EWDS/EWEN)

3.7

READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16-bit output string. The output

data bits will toggle on the rising edge of the CLK and

are stable after the specified time delay (TPD). Sequen-

tial read is possible when CS is held high. The memory

data will automatically cycle to the next register and

output sequentially.

The device powers up in the ERASE/WRITE Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or Vcc is removed from the device. To protect against

accidental data disturbance, the EWDS instruction can

be used to disable all ERASE/WRITE functions and

should follow all programming operations. Execution of

a READ instruction is independent of both the EWDS

and EWEN instructions.

FIGURE 3-4: EWDS TIMING

TCSL

CLK

•••

FIGURE 3-5: EWEN TIMING

TCSL

CLK

•••

FIGURE 3-6: READ TIMING

CLK

•••

HIGH-Z

•••

DS21172E-page 6

 2001 Microchip Technology Inc.

93C46B

3.8

WRITE

3.9

Write All (WRAL)

The WRITE instruction is followed by 16 bits of data,

which are written into the specified address. After the

last data bit is clocked into the DI pin, the self-timed

auto-erase and programming cycle begins.

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

The WRAL cycle is completely self-timed and com-

mences at the rising clock edge of the last data bit.

Clocking of the CLK pin is not necessary after the

device has entered the WRAL cycle. The WRAL com-

mand does include an automatic ERAL cycle for the

device. Therefore, the WRAL instruction does not

require an ERAL instruction, but the chip must be in the

EWEN status.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the specified address has been written with the data

specified and the device is ready for another instruc-

tion.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

FIGURE 3-7: WRITE TIMING

TCSL

CLK

•••

TSV

TCZ

HIGH-Z

BUSY

READY

HIGH-Z

Twc

FIGURE 3-8: WRAL TIMING

TCSL

CLK

•••

TSV

TCZ

HIGH-Z

BUSY

READY

HIGH-Z

TWL

 2001 Microchip Technology Inc.

DS21172E-page 7

93C46B

93C46B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

93C46B

—

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (208 mil Body), 8-lead

ST = TSSOP, 8-lead

Package:

Blank = 0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Temperature

Range:

93C46B = 1K Microwire Serial EEPROM

93C46BT = 1K Microwire Serial EEPROM Tape and Reel

93C46BX = 1K Microwire Serial EEPROM in alternate pinout

(SN only)

Device:

93C46BXT = 1K Microwire Serial EEPROM in alternate pinout,

Tape and Reel (SN only)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Web Site (www.microchip.com)

DS21172E-page 8

 2001 Microchip Technology Inc.

93C46B

NOTES:

 2001 Microchip Technology Inc.

DS21172E-page 9

93C46B

NOTES:

DS21172E-page 10

 2001 Microchip Technology Inc.

93C46B

Technology Incorporated, USA. Information contained

in this publication regarding device applications and the

like is intended through suggestion only and may be

superseded by updates. No representation or warranty

is given and no liability is assumed by Microchip

Technology Incorporated with respect to the accuracy

or use of such information, or infringement of patents or

other intellectual property rights arising from such use

or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized

except with express written approval by Microchip. No

licenses are conveyed, implicitly or otherwise, under

any intellectual property rights. The Microchip logo and

name are registered trademarks of Microchip

Technology Inc. in the U.S.A. and other countries. All

rights reserved. All other trademarks mentioned herein

are the property of their respective companies. No

licenses are conveyed, implicitly or otherwise, under

any intellectual property rights.”

Trademarks

The Microchip name, logo, PIC, PICmicro,

PICMASTER, PICSTART, PRO MATE, KEELOQ,

SEEVAL, MPLAB and The Embedded Control

Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and

other countries.

Total Endurance, ICSP, In-Circuit Serial Programming,

FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,

MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,

Migratable Memory, FanSense, ECONOMONITOR,

SelectMode and microPort are trademarks of

Microchip Technology Incorporated in the U.S.A.

Serialized Quick Term Programming (SQTP) is a

service mark of Microchip Technology Incorporated in

the U.S.A.

All other trademarks mentioned herein are property of

their respective companies.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

 2001 Microchip Technology Inc.

DS21172E-page 11

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Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

ASIA/PACIFIC (continued)

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01/30/01

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by

updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual

property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with

express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-

tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights

reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21172E-page 12

 2001 Microchip Technology Inc.

93C46BT/ST [MICROCHIP]

相关型号：

93C46BTE/SM

93C46BTE/SN

93C46BTE/SNG

93C46BTE/ST

93C46BTI/SN

93C46BTI/ST

93C46BX-/SN

93C46BX-E/MC

93C46BX-E/MCG

93C46BX-E/MS

93C46BX-E/MSG

93C46BX-E/OT