93LC76I/SN [MICROCHIP]
512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, NSOIC-8;
| 型号： | 93LC76I/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, NSOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
93LC76/86
8K/16K 2.5V CMOS Serial EEPROM
PIN CONFIGURATION
DIP Package
FEATURES
• Single supply with programming operation down
to 2.5V
93LC76/86
• Low power CMOS technology
- 1 mA active current typical
V
CS
CLK
DI
CC
- 5 µA standby current (typical) at 3.0V
PE
• ORG pin selectable memory configuration
1024 x 8 or 512 x 16 bit organization (93LC76)
2048 x 8 or 1024 x 16 bit organization (93LC86)
ORG
DO
V
SS
• Self-timed ERASE and WRITE cycles
(including auto-erase)
SOIC Package
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
93LC76/86
CS
CLK
DI
V
CC
PE
• Device status signal during ERASE/WRITE
cycles
ORG
V
DO
• Sequential READ function
SS
• 10,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
BLOCK DIAGRAM
• 8-pin PDIP/SOIC package
• Temperature ranges available:
- Commercial (C): 0°C to +70°C
VCC VSS
- Industrial (I):
-40°C to +85°C
Address
Decoder
Memory
Array
DESCRIPTION
The Microchip Technology Inc. 93LC76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93LC76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.
Address
Counter
Data
Register
Output
Buffer
DO
DI
Mode
Decode
PE
Logic
CS
Clock
CLK
Generator
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 1
93LC76/86
AC Test Conditions
1.0 ELECTRICAL CHARACTERISTICS
Maximum Ratings*
Input Pulse Levels
0.4V to 2.4V
Output Reference Levels
0.8V and 2.0V
VCC........................................................................7.0V
All inputs and outputs w.r.t. VSS .... -0.6V to Vcc +1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Soldering temperature of leads (10 seconds) ..+300°C
ESD protection on all pins.....................................4 kV
PIN FUNCTION TABLE
Function
Name
CS
Chip Select
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
CLK
DI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
VSS
ORG
PE
Memory Configuration
Program Enable
Power Supply
VCC
TABLE 1-1:
D.C. CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
VCC = +2.5V to +6.0V
Parameter
Symbol
Min.
Max.
Units
Conditions
High level input voltage
VIH1
VIH2
VIL1
VIL2
VOL1
VOL2
VOH1
VOH2
ILI
2.0
0.7 VCC
-0.3
-0.3
—
VCC +1
VCC +1
0.8
V
V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
Low level input voltage
Low level output voltage
High level output voltage
V
0.2 VCC
0.4
V
V
IOL = 2.1 mA; VCC = 4.5V
IOL =100 µA; VCC = VCC Min.
IOH = -400 µA; VCC = 4.5V
IOH = -100 µA; VCC = VCC Min.
VIN = 0.1V to VCC
—
0.2
V
2.4
—
V
VCC-0.2
-10
—
V
Input leakage current
Output leakage current
10
µA
µA
pF
ILO
-10
10
VOUT = 0.1V to VCC
Pin capacitance
(all inputs/outputs)
CINT
—
7
(Note 1)
Tamb = +25°C, FCLK = 1 MHz
Operating current
ICC write
ICC read
—
—
3
mA
FCLK = 3 MHz; VCC = 6.0V
1
500
mA
µA
FCLK = 3 MHz; VCC = 6.0V
FCLK = 1 MHz; VCC = 3.0V
Standby current
ICCS
—
100
30
µA
µA
CLK = CS = 0V; VCC = 6.0V
CLK = CS = 0V; VCC = 3.0V
Note 1: This parameter is periodically sampled and not 100% tested.
DS21131A-page 2
Preliminary
1995 Microchip Technology Inc.
93LC76/86
TABLE 1-2:
A.C. CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
VCC = +2.5V to +6.0V
Parameter
Symbol
Min.
Max.
Units
Conditions
Clock frequency
FCLK
—
3
1
MHz
MHz
4.5V ≤ VCC ≤ 6.0V
2.5V ≤ VCC < 4.5V
Clock high time
TCKH
TCKL
TCSS
100
250
—
—
—
ns
ns
ns
4.5V ≤ VCC ≤ 6.0V
2.5V ≤ VCC < 4.5V
Clock low time
100
250
4.5V ≤ VCC ≤ 6.0V
2.5V ≤ VCC < 4.5V
Chip select setup time
50
100
4.5V ≤ VCC ≤ 6.0V, Relative to CLK
2.5V ≤ VCC < 4.5V, Relative to CLK
Chip select hold time
Chip select low time
Data input setup time
TCSH
TCSL
TDIS
0
—
—
—
ns
ns
ns
250
Relative to CLK
50
100
4.5V ≤ VCC ≤ 6.0V, Relative to CLK
2.5V ≤ VCC <4.5V, Relative to CLK
Data input hold time
TDIH
TPD
TCZ
50
100
—
ns
ns
ns
4.5V ≤ VCC ≤ 6.0V, Relative to CLK
2.5V ≤ VCC < 4.5V, Relative to CLK
Data output delay time
Data output disable time
—
100
250
4.5V ≤ VCC ≤ 6.0V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
—
100
500
4.5V ≤ VCC ≤ 6.0V
2.5V ≤ VCC < 4.5V (Note 2)
Status valid time
T
—
100
250
ns
4.5V ≤ VCC ≤ 6.0V, CL = 100 pF
2.5V ≤ VCC <4.5V, CL = 100 pF
SV
Program cycle time
TWC
TEC
TWL
—
—
—
5
ms
ms
ms
ERASE/WRITE mode
ERAL mode
15
30
WRAL mode
Note 2: This parameter is periodically sampled and not 100% tested.
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 3
93LC76/86
2.3
Data In (DI)
2.0
PIN DESCRIPTIONS
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.1
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
2.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available when CS is high. It will
be displayed until the next start bit occurs as long as
CS stays high.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
2.2
Serial Clock (CLK)
2.5
Organization (ORG)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
When ORG is connected to VCC, the x16 memory orga-
nization is selected. When ORG is tied to VSS, the x8
memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16
organization when left unconnected.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
2.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is
floated or tied to VCC, the device can be programmed.
If the PE pin is tied to VSS, programming will be inhib-
ited. There is an internal pull-up on this device that
enables programming if this pin is left floating.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 2-1
through Table 2-4 for more details). CLK and DI then
become don't care inputs waiting for a new start condi-
tion to be detected.
Note: CS must go LOW between consecutive
instructions, except when performing a
sequential read (Refer to Section 4.1 for
more detail on sequential reads).
DS21131A-page 4
Preliminary
1995 Microchip Technology Inc.
93LC76/86
Table 2-1:
INSTRUCTION SET FOR 93LC76: ORG=1 (x16 ORGANIZATION)
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X X
0 0 X X X X X X X X
—
—
—
—
D15 - D0
High-Z
29
13
13
13
29
29
13
(RDY/BSY)
(RDY/BSY)
WRITE
WRAL
EWDS
D15 - D0 (RDY/BSY)
D15 - D0 (RDY/BSY)
—
High-Z
Table 2-2:
INSTRUCTION SET FOR 93LC76: ORG=0 (x8 ORGANIZATION)
Req. CLK
Cycles
Instruction SB Opcode
Address
Data In
Data Out
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X X
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
D7 - D0
22
14
14
14
22
22
14
High-Z
(RDY/BSY)
(RDY/BSY)
1 0 X X X X X X X
X
WRITE
WRAL
EWDS
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0 (RDY/BSY)
D7 - D0 (RDY/BSY)
0 1 X X X X X X X
0 0 X X X X X X X
X
X
—
High-Z
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 5
93LC76/86
Table 2-3:
INSTRUCTION SET FOR 93LC86: ORG=1 (x16 ORGANIZATION)
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X X
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X X
0 0 X X X X X X X X
—
—
—
—
D15 - D0
High-Z
29
13
13
13
29
29
13
(RDY/BSY)
(RDY/BSY)
WRITE
WRAL
EWDS
D15 - D0 (RDY/BSY)
D15 - D0 (RDY/BSY)
—
High-Z
Table 2-4:
INSTRUCTION SET FOR 93LC86: ORG=0 (x8 ORGANIZATION)
Req. CLK
Cycles
Instruction SB Opcode
Address
DataIn
Data Out
READ
EWEN
ERASE
ERAL
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
D7 - D0
22
14
14
14
22
22
14
1
1
X
X
X X
X
X
X
X
High-Z
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(RDY/BSY)
(RDY/BSY)
1
0
X
X
X
X
X
X
X
X
WRITE
WRAL
EWDS
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
D7 - D0 (RDY/BSY)
High-Z
X X X X
—
DS21131A-page 6
Preliminary
1995 Microchip Technology Inc.
93LC76/86
3.3
ERASE/WRITE ENABLE AND
DISABLE
3.0
PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground,
the x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/BUSY status
during a programming operation. The READY/BUSY
status can be verified during an Erase/Write operation
by polling the DO pin; DO low indicates that program-
ming is still in progress, while DO high indicates the
device is ready. The DO will enter the high impedance
state on the falling edge of the CS.
The 93LC76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should
follow all programming operations. Execution of a
READ instruction is independent of both the EWEN
and EWDS instructions.
3.4
Data Protection
3.1
START Condition
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
3.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undefined and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the Data Out pin.
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 7
93LC76/86
4.4
ERASE ALL
4.0
DEVICE OPERATION
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences on the rising edge of the last address bit (A0).
Note that the least significant 8 or 9 address bits are
don’t care bits, depending on selection of x16 or x8
mode. Clocking of the CLK pin is not necessary after
the device has entered the self clocking mode. The
ERAL instruction is guaranteed at Vcc = +4.5V to
+6.0V.
4.1
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (TPD). Sequential read is
possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
erased and is ready for another instruction.
4.2
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. The self-timed pro-
gramming cycle is initiated on the rising edge of CLK as
the last address bit (A0) is clocked in. At this point, the
CLK, CS, and DI inputs become don’t cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been erased and the device is ready for
another instruction.
The ERAL cycle takes 15 ms maximum (8 ms typical).
4.5
WRITE ALL
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the least significant 8 or 9 address bits are don’t cares,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL instruction but the chip must be in the EWEN sta-
tus. The WRAL instruction is guaranteed at Vcc =
+4.5V to +6.0V.
The ERASE cycle takes 3 ms per word (Typical).
4.3
WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the ris-
ing edge of CLK as the last data bit (D0) is clocked in.
At this point, the CLK, CS, and DI inputs become don’t
cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the entire device has been
written and is ready for another instruction.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical “0”
indicates that programming is still in progress. DO at
logical “1” indicates that the register at the specified
address has been written and the device is ready for
another instruction.
The WRAL cycle takes 30 ms maximum (16 ms
typical).
The WRITE cycle takes 3 ms per word (Typical).
DS21131A-page 8
Preliminary
1995 Microchip Technology Inc.
93LC76/86
FIGURE 4-1: TIMING DIAGRAMS
SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
TCKH
TCKL
VIL
TCSH
VIH
CLK
TDIH
VIL
TDIS
VIH
VIL
DI
TCZ
TPD
TPD
VOH
DO
(Read)
VOL
VOH
VOL
TCZ
TSV
DO
(Program)
STATUS VALID
The memory automatically cycles to the next register.
READ
TCSL
CS
CLK
DI
...
1
1
0
A
A
0
N
HIGH IMPEDANCE
...
...
0
D
D
D
D
0
DO
N
0
N
EWEN
TCSL
CS
CLK
DI
...
1
0
0
1
1
X
X
ORG=V , 8 X’s
CC
ORG=V , 9 X’s
SS
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 9
93LC76/86
EWDS
TCSL
CS
CLK
DI
...
1
0
0
0
0
X
X
ORG=V , 8 X’s
CC
ORG=V , 9 X’S
SS
WRITE
CS
STANDBY
CLK
DI
...
...
1
0
1
A
A
D
N
D
0
N
0
TCZ
HIGH IMPEDANCE
BUSY
READY
DO
TWC
WRAL
STANDBY
CS
CLK
DI
...
...
1
0
0
0
1
X
X
D
D
0
N
TCZ
HIGH IMPEDANCE
READY
BUSY
DO
ORG=V , 8 X’s
CC
TWL
ORG=V , 9 X’s
Guarantee at Vcc = +4.5V to +6.0V.
SS
DS21131A-page 10
Preliminary
1995 Microchip Technology Inc.
93LC76/86
ERASE
CS
STANDBY
CLK
DI
...
...
1
1
1
A
A
0
N
TCZ
HIGH IMPEDANCE
DO
BUSY
READY
TWC
ERAL
CS
STANDBY
CLK
DI
...
1
0
0
1
0
X
X
TCZ
HIGH IMPEDANCE
BUSY
READY
DO
TEC
ORG=V , 8 X’s
CC
Guarantee at VCC = +4.5V to +6.0V.
ORG=V , 9 X’s
SS
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 11
93LC76/86
93LC76/86 Product Identification System
To order or obtain information, e.g., on pricing or delivery, please use listed part numbers, and refer to factory or listed sales office.
93LC76/86 –
E
/
P
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +125°C
Device:
93LC76/86
93LC76T/86T
CMOS Serial EEPROM
CMOS Serial EEPROM (Tape and Reel)
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below).
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
EUROPE
AMERICAS (continued)
AMERICAS
United Kingdom
San Jose
Corporate Office
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 0 1628 851077 Fax: 44 0 1628 850259
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.mchip.com/biz/mchip
Tel: 408 436-7950 Fax: 408 436-7955
ASIA/PACIFIC
Hong Kong
Microchip Technology
Unit No. 3002-3004, Tower 1
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
France
Arizona Microchip Technology SARL
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Pegaso Ingresso No. 2
Via Paracelso 23, 20041
Agrate Brianza (MI) Italy
Tel: 39 039 689 9939 Fax: 39 039 689 9883
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 508 480-9990
Fax: 508 480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
Dayton
Microchip Technology Inc.
35 Rockridge Road
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Englewood, OH 45322
Tel: 513 832-2543 Fax: 513 832-2841
Tel: 886 2 717 7175 Fax: 886 2 545 0139
9/5/95
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
All rights reserved.
1995, Microchip Technology Inc.,USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or
otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise,
under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of
their respective companies.
DS21131A-page 12
Preliminary
1995 Microchip Technology Inc.
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