AT25128B-MAHL-E_技术文档

AT25128B/AT25256B

SPI Serial EEPROM 128 Kbits (16,384 x 8)

and 256 Kbits (32,768 x 8)

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1):

– Data sheet describes mode 0 operation

• Low-Voltage Operation:

– 1.8V (V_CC= 1.8V to 5.5V)

• Industrial Temperature Range: -40°C to +85°C

• 20 MHz Clock Rate (5V)

• 64‑Byte Page Mode

• Block Write Protection:

– Protect 1/4, 1/2 or entire array

• Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data

Protection

• Self-Timed Write Cycle within 5 ms Maximum

• ESD Protection > 4,000V

• High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

• Green (Lead-free/Halide-free/RoHS Compliant) Package Options

• Die Sale Options: Wafer Form and Bumped Wafers

Packages

• 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA

DS20006193A-page 1

AT25128B/AT25256B

Table of Contents

Features.......................................................................................................................... 1

Packages.........................................................................................................................1

1. Package Types (not to scale).................................................................................... 4

2. Pin Description.......................................................................................................... 5

2.1. Chip Select (CS)...........................................................................................................................5

2.2. Serial Data Output (SO)............................................................................................................... 5

2.3. Write-Protect (WP)....................................................................................................................... 5

2.4. Ground (GND)..............................................................................................................................5

2.5. Serial Data Input (SI)....................................................................................................................6

2.6. Serial Data Clock (SCK)...............................................................................................................6

2.7. Suspend Serial Input (HOLD).......................................................................................................6

2.8. Device Power Supply (V_CC)......................................................................................................... 6

3. Description.................................................................................................................7

3.1. SPI Bus Master Connections to Serial EEPROMs.......................................................................7

3.2. Block Diagram..............................................................................................................................8

4. Electrical Characteristics........................................................................................... 9

4.1. Absolute Maximum Ratings..........................................................................................................9

4.2. DC and AC Operating Range.......................................................................................................9

4.3. DC Characteristics....................................................................................................................... 9

4.4. AC Characteristics......................................................................................................................10

4.5. SPI Synchronous Data Timimg.................................................................................................. 13

4.6. Electrical Specifications..............................................................................................................13

5. Device Operation.....................................................................................................15

5.1. Interfacing the AT25128B/AT25256B on the SPI Bus................................................................ 15

5.2. Device Opcodes.........................................................................................................................16

5.3. Hold Function............................................................................................................................. 16

5.4. Write Protection..........................................................................................................................17

6. Device Commands and Addressing........................................................................ 18

6.1. STATUS Register Bit Definition and Function............................................................................ 18

6.2. Read STATUS Register (RDSR).................................................................................................19

6.3. Write Enable (WREN) and Write Disable (WRDI)........................................................................19

6.4. Write STATUS Register (WRSR).................................................................................................20

7. Read Sequence.......................................................................................................23

8. Write Sequence....................................................................................................... 24

8.1. Byte Write...................................................................................................................................24

8.2. Page Write..................................................................................................................................25

DS20006193A-page 2

AT25128B/AT25256B

8.3. Polling Routine........................................................................................................................... 25

9. Packaging Information.............................................................................................27

9.1. Package Marking Information.....................................................................................................27

10. Revision History.......................................................................................................37

The Microchip Web Site................................................................................................ 38

Customer Change Notification Service..........................................................................38

Customer Support......................................................................................................... 38

Product Identification System........................................................................................39

Microchip Devices Code Protection Feature................................................................. 39

Legal Notice...................................................................................................................40

Trademarks................................................................................................................... 40

Quality Management System Certified by DNV.............................................................41

Worldwide Sales and Service........................................................................................42

DS20006193A-page 3

AT25128B/AT25256B

Package Types (not to scale)

1.

Package Types (not to scale)

8-Lead SOIC/TSSOP

(Top View)

CS

1

2

8

7

Vcc

SO

WP

HOLD

SCK

SI

3

4

6

5

GND

8-Ball VFBGA

(Top View)

8-Pad UDFN

(Top View)

1

2

3

4

8

7

6

5

Vcc

CS

SO

1

2

8

Vcc

SO

WP

HOLD

SCK

SI

7

6

5

HOLD

SCK

SI

WP 3

GND

4

GND

DS20006193A-page 4

AT25128B/AT25256B

Pin Description

2.

Pin Description

The descriptions of the pins are listed in Table 2-1.

Table 2-1.ꢀPin Function Table

(1)

Name

CS

8-Lead SOIC

8-Lead TSSOP

8-Pad UDFN

8-Ball VFBGA Function

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

Chip Select

SO

Serial Data Output

Write-Protect

(2)

WP

GND

SI

Ground

Serial Data Input

Serial Data Clock

Suspends Serial Input

Device Power Supply

SCK

(2)

HOLD

V

CC

Note:ꢀ

1. The exposed pad on this package can be connected to GND or left floating.

2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.

2.1

Chip Select (CS)

The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not

selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will

remain in a high-impedance state.

To ensure robust operation, the CS pin should follow V_CCupon power-up. It is therefore recommended to

connect CS to V_CCusing a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on

CS is required prior to any sequence being initiated.

2.2

2.3

Serial Data Output (SO)

The Serial Data Output (SO) pin is used to transfer data out of the AT25128B/AT25256B. During a read

sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).

Write-Protect (WP)

The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is

brought low and WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are inhibited.

WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal

write cycle has already been initiated, WP going low will have no effect on any write operation to the

STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a

logic ‘0’. This will allow the user to install the AT25128B/AT25256B in a system with the WP pin tied to

ground and still be able to write to the STATUS register. All WP pin functions are enabled when the

WPEN bit is set to a logic ‘1’.

2.4

Ground (GND)

The ground reference for the Device Power Supply (V_CC). The Ground (GND) pin should be connected to

the system ground.

DS20006193A-page 5

AT25128B/AT25256B

Pin Description

2.5

2.6

Serial Data Input (SI)

The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses

and data. Data is latched on the rising edge of the Serial Data Clock (SCK).

Serial Data Clock (SCK)

The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the

AT25128B/AT25256B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched

in on the rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling

edge of SCK.

2.7

Suspend Serial Input (HOLD)

The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the

AT25128B/AT25256B. When the device is selected and a serial sequence is underway, HOLD can be

used to pause the serial communication with the master device without resetting the serial sequence. To

pause, the HOLD pin must be brought low while the Serial Data Clock (SCK) pin is low. To resume serial

communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during

HOLD). Inputs to the Serial Data Input (SI) pin will be ignored while the Serial Data Output (SO) pin will

be in the high‑impedance state.

2.8

Device Power Supply (V_CC)

The Device Power Supply (V_CC) pin is used to supply the source voltage to the device. Operations at

invalid V_CCvoltages may produce spurious results and should not be attempted.

DS20006193A-page 6

AT25128B/AT25256B

Description

3.

Description

The AT25128B/AT25256B provides 131,072/262,144 bits of Serial Electrically Erasable and

Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each.

The device is optimized for use in many industrial and commercial applications where low‑power and

low‑voltage operation are essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP,

8‑pad UDFN and 8‑ball VFBGA packages. All packages operate from 1.8V to 5.5V.

3.1

SPI Bus Master Connections to Serial EEPROMs

SPI Master:

Microcontroller

Data Clock (SCK)

Data Output (SO)

Data Input (SI)

SI SO SCK

Slave 0

Slave 1

Slave 2

Slave 3

AT25XXX

CS

CS3 CS2 CS1 CS0

DS20006193A-page 7

AT25128B/AT25256B

Description

3.2

Block Diagram

Memory

System Control

Module

Power-on

Reset

Generator

CS

VCC

High-Voltage

Generation

Circuit

Register Bank:

STATUS Register

Pause

Operation

Control

SO

HOLD

EEPROM Array

1 page

Address Register

and Counter

Column Decoder

Data Register

SCK

WP

Data Output

Buffer

GND

SI

Write Protection

Control

DS20006193A-page 8

AT25128B/AT25256B

Electrical Characteristics

4.

Electrical Characteristics

4.1

Absolute Maximum Ratings

Operating temperature

Storage temperature

Voltage on any pin with respect to ground

V_CC

-55°C to +125°C

-65°C to +150°C

-1.0V to +7.0V

6.25V

DC output current

5.0 mA

ESD protection

> 4 kV

Note:ꢀ Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operation listings of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

4.2

4.3

DC and AC Operating Range

Table 4-1.ꢀDC and AC Operating Range

AT25128B/AT25256B

Operating Temperature (Case)

V_CCPower Supply

Industrial Temperature Range

Low-Voltage Grade

-40°C to +85°C

1.8V to 5.5V

DC Characteristics

Table 4-2.ꢀDC Characteristics⁽¹⁾

Parameter

Symbol Minimum Typical Maximum Units Conditions

Supply Voltage

Supply Current

V_CC1

V_CC2

V_CC3

I_CC1

1.8

2.5

4.5

—

5.5

V

—

5.5

9.0

10.0

mA V_CC= 5.0V at 20 MHz,

SO = Open, Read

Supply Current

Standby Current

I_CC2

I_CC3

I_SB1

—

5.0

2.2

0.2

7.0

3.5

3.0

mA V_CC= 5.0V at 10 MHz,

SO = Open, Read, Write

mA V_CC= 5.0V at 1 MHz,

SO = Open, Read, Write

µA V_CC= 1.8V, CS = V_CC

DS20006193A-page 9

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter

Symbol Minimum Typical Maximum Units Conditions

Standby Current

Input Leakage

I_SB2

I_SB3

I_IL

—

0.5

2.0

—

3.0

5.0

3.0

µA V_CC= 2.5V, CS = V_CC

µA V_CC= 5.0V, CS = V_CC

µA V_IN= 0V to V_CC

-3.0

Output Leakage

I_OL

—

µA V_IN= 0V to V_CC,

T_AC= 0°C to +70°C

(2)

Input

Low-Voltage

V_IL

-1.0

V_CCx 0.7

—

V_CCx 0.3

V

(2)

Input

High-Voltage

V_IH

V_CC+ 0.5

Output

Low-Voltage

V_OL1

V_OH1

V_OL2

V_OH2

0.4

—

3.6V ≤ V_CC≤ 5.5V I_OL= 3.0 mA

3.6V ≤ V_CC≤ 5.5V I_OH= -1.6 mA

1.8V ≤ V_CC≤ 3.6V I_OL= 0.15 mA

1.8V ≤ V_CC≤ 3.6V I_OH= -100 µA

Output

High-Voltage

V_CC- 0.8

—

Output

Low-Voltage

0.2

—

Output

V_CC- 0.2

High-Voltage

Note:ꢀ

1. Applicable over recommended operating range from: T_A= -40°C to +85°C, V_CC= 1.8V to 5.5V

(unless otherwise noted).

2. V_ILmin and V_IHmax are reference only and are not tested.

4.4

AC Characteristics

Table 4-3.ꢀAC Characteristics⁽¹⁾

Parameter

Symbol

Minimum Maximum

Units

MHz

ns

Conditions

SCK Clock Frequency

f_SCK

0

20

10

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

0

5

Input Rise Time

t_RI

—

2000

ns

DS20006193A-page 10

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter

Symbol

Minimum Maximum

Units

ns

Conditions

Input Fall Time

SCK High Time

SCK Low Time

CS High Time

t_FI

—

2000

—

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

—

t_WH

t_WL

t_CS

t_CSS

t_CSH

t_SU

t_H

20

40

80

20

40

80

100

200

100

200

100

200

5

—

CS Setup Time

CS Hold Time

—

Data In Setup Time

Data In Hold Time

HOLD Setup Time

HOLD Hold Time

—

10

20

5

—

10

20

5

—

t_HD

—

10

20

5

—

t_CD

—

10

20

—

DS20006193A-page 11

AT25128B/AT25256B

Electrical Characteristics

...........continued

Parameter

Symbol

Minimum Maximum

Units

ns

Conditions

Output Valid

t_V

0

20

40

80

—

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

V_CC= 4.5V to 5.5V

V_CC= 2.5V to 5.5V

V_CC= 1.8V to 5.5V

ns

0

ns

Output Hold Time

HOLD to Output Low Z

HOLD to Output High Z

Output Disable Time

Write Cycle Time

t_HO

0

ns

0

—

ns

0

—

ns

t_LZ

0

25

50

100

25

50

100

25

50

100

5

ns

0

ns

0

ns

t_HZ

t_DIS

t_WC

—

ns

ms

5

Note:ꢀ

1. Applicable over recommended operating range from T_A= -40°C to +85°C, V_CC= As Specified,

C_L= 1 TTL Gate and 30 pF (unless otherwise noted).

DS20006193A-page 12

AT25128B/AT25256B

Electrical Characteristics

4.5

SPI Synchronous Data Timimg

t_CS

V_IH

CS

V_IL

t_CSS

t_CSH

V_IH

t_WH

t_WL

SCK

V_IL

t_SU

t_H

V_IH

V_IL

SI

Valid Data In

t_HO

t_DIS

t_V

V_OH

High

SO

Impedance

V_OL

4.6

Electrical Specifications

4.6.1

Power-Up Requirements and Reset Behavior

During a power-up sequence, the V_CCsupplied to the AT25128B/AT25256B should monotonically rise

from GND to the minimum V_CClevel, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.

4.6.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up

sequence, the AT25128B/AT25256B includes a Power-on Reset (POR) circuit. Upon power-up, the

device will not respond to any instructions until the V_CClevel crosses the internal voltage threshold (V_POR

that brings the device out of Reset and into Standby mode.

)

The system designer must ensure the instructions are not sent to the device until the V_CCsupply has

reached a stable value greater than or equal to the minimum V_CClevel. Additionally, once the V_CCis

greater than or equal to the minimum V_CClevel, the bus master must wait at least t_PUPbefore sending the

first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.

Table 4-4.ꢀPower-Up Conditions⁽¹⁾

Symbol

Parameter

Min. Max. Units

t_PUP

Time required after V_CCis stable before the device can accept instructions 100

－

1.5

－

µs

V

V_PORPower-on Reset Threshold Voltage

－

t_POFFMinimum time at V_CC= 0V between power cycles

0.03

ms

Note:ꢀ

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the V_CClevel supplied to the AT25128B/AT25256B drops below

the maximum V_PORlevel specified, it is recommended that a full-power cycle sequence be performed by

first driving the V_CCpin to GND in less than 1 ms, waiting at least the minimum t_POFFtime and then

performing a new power-up sequence in compliance with the requirements defined in this section.

DS20006193A-page 13

AT25128B/AT25256B

Electrical Characteristics

4.6.2

Pin Capacitance

Table 4-5.ꢀPin Capacitance^(1,2)

Symbol Test Condition

Max. Units Conditions

C_OUT

C_IN

Output Capacitance (SO)

8

6

pF

V_OUT= 0V

V_IN= 0V

Input Capacitance (CS, SCK, SI, WP, HOLD)

Note:ꢀ

1. This parameter is characterized but is not 100% tested in production.

2. Applicable over recommended operating range from: T_A= 25°C, f_SCK= 1.0 MHz, V_CC= 5.0V

(unless otherwise noted).

4.6.3

EEPROM Cell Performance Characteristics

Table 4-6.ꢀEEPROM Cell Performance Characteristics

Operation

Test Condition

Min.

Max.

Units

Write Endurance⁽¹⁾

T_A= 25°C, V_CC= 3.3V,

Page Write mode

1,000,000

—

Write Cycles

Data Retention⁽¹⁾

T_A= 55°C

100

—

Years

Note:ꢀ

1. Performance is determined through characterization and the qualification process.

4.6.4

4.6.5

Software Reset

The SPI interface of the AT25128B/AT25256B can be reset by toggling the CS input. If the CS line is

already in the active state, it must complete a transition from the inactive state (≥V_IH) to the active state

(≤V_IL) and then back to the inactive state (≥V_IH) without sending clocks on the SCK line. Upon completion

of this sequence, the device will be ready to receive a new opcode on the SI line.

Device Default State at Power-Up

The AT25128B/AT25256B default state upon power-up consists of:

• Standby Power mode

• A high-to-low-level transition on CS is required to enter active state

• Write Enable Latch (WEL) bit in the STATUS register = 0

• Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command

• Device is not selected

• Not in Hold condition

• WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the

fact that they are nonvolatile values

4.6.6

Device Default Condition

The AT25128B/AT25256B is shipped from Microchip to the customer with the EEPROM array set to an all

FFh data pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0’

(the ability of the EEPROM array to write is dictated by the values of the Block Write‑Protect bits while the

STATUS register’s ability to write is controlled by the WEL bit). The Block Write Protection bits in the

STATUS register are set to logic ‘0’ (no write protection selected).

DS20006193A-page 14

AT25128B/AT25256B

Device Operation

5.

Device Operation

The AT25128B/AT25256B is controlled by a set of instructions that are sent from a host controller,

commonly referred to as the SPI Master. The SPI Master communicates with the AT25128B/AT25256B

via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial

Data Input (SI), and Serial Data Output (SO).

The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in

respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI

bus. The AT25128B/AT25256B supports the two most common modes, SPI Modes 0 and 3. With SPI

Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge

of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the

inactive state (when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is

defined as a low SCK while CS is not asserted (at V_CC) and SPI Mode 3 has SCK high in the inactive

state. The SCK Idle state must match when the CS is deasserted both before and after the

communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid

line on SCK while CS is inactive and Mode 3 with a dotted line.

Figure 5-1.ꢀSPI Mode 0 and Mode 3

CS

Mode 3

Mode 0

Mode 3

Mode 0

SCK

SI

MSB

LSB

MSB

LSB

SO

5.1

Interfacing the AT25128B/AT25256B on the SPI Bus

Communication to and from the AT25128B/AT25256B must be initiated by the SPI Master device, such

as a microcontroller. The SPI Master device must generate the serial clock for the AT25128B/AT25256B

on the Serial Data Clock (SCK) pin. The AT25128B/AT25256B always operates as a slave due to the fact

that the SCK is always an input.

5.1.1

5.1.2

Selecting the Device

The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not

selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin

will remain in a high‑impedance state.

Sending Data to the Device

The AT25128B/AT25256B uses the SI pin to receive information. All instructions, addresses and data

input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the

first rising edge of the SCK line after the CS has been asserted.

DS20006193A-page 15

AT25128B/AT25256B

Device Operation

5.1.3

Receiving Data from the Device

Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is

latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the

Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See Read Sequence

for more details.

5.2

Device Opcodes

5.2.1

Serial Opcode

After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte

contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes

that the AT25128B/AT25256B will respond to.

5.2.2

Invalid Opcode

If an invalid opcode is received, no data will be shifted into AT25128B/AT25256B and the SO pin will

remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the

serial communication.

5.3

Hold Function

The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without

having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the

internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the

operation and the write cycle will continue to completion.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by

asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse,

then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will

remain in the Hold mode as long as the HOLD pin and CS pin are asserted.

While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the

SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in

the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the

SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end

until the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been

started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’

state.

DS20006193A-page 16

AT25128B/AT25256B

Device Operation

Figure 5-2.ꢀHold Mode

CS

SCK

HOLD

Hold

Figure 5-3.ꢀHold Timing

CS

t_CD

SCK

HOLD

SO

t_HD

t_HZ

t_LZ

5.4

Write Protection

The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin

is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The

WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write

cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS

register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will

allow the user to install the AT25128B/AT25256B device in a system with the WP pin tied to ground and

still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to

a logic ‘1’.

DS20006193A-page 17

AT25128B/AT25256B

Device Commands and Addressing

6.

Device Commands and Addressing

The AT25128B/AT25256B is designed to interface directly with the synchronous Serial Peripheral

Interface (SPI). The AT25128B/AT25256B utilizes an 8‑bit instruction register. The list of instructions and

their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with

the MSb first and start with a high‑to‑low CS transition.

Table 6-1.ꢀInstruction Set for the AT25128B/AT25256B

Instruction Name

WREN

Instruction Format Operates On

Operation Description

Set Write Enable Latch (WEL)

Reset Write Enable Latch (WEL)

Read STATUS Register

Write STATUS Register

0000 X110

0000 X100

0000 X101

0000 X001

0000 X011

0000 X010

STATUS Register

Memory Array

WRDI

RDSR

WRSR

READ

Read from Memory Array

Write to Memory Array

WRITE

Memory Array

6.1

STATUS Register Bit Definition and Function

The AT25128B/AT25256B includes an 8‑bit STATUS register. The STATUS register bits modulate various

features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific

instructions that are detailed in the following sections.

Table 6-2.ꢀSTATUS Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN

X

BP1

BP0

WEL

RDY/BSY

Table 6-3.ꢀSTATUS Register Bit Definition

Bit

Name

Type

Description

0

1

0

7

WPEN Write-Protect Enable

R/W

See Table 6-5 (Factory Default)

6:4

3:2

RFU

Reserved for Future Use

Block Write Protection

R

Reads as zeros when the device is not in a write

cycle

1

00

01

10

11

0

Reads as ones when the device is in a write cycle

No array write protection (Factory Default)

Quarter array write protection (see Table 6-4)

Half array write protection (see Table 6-4)

Entire array write protection (see Table 6-4)

Device is not write enabled (Power-up Default)

Device is write enabled

BP1

BP0

R/W

1

WEL

Write Enable Latch

R/W

1

DS20006193A-page 18

AT25128B/AT25256B

Device Commands and Addressing

...........continued

Bit

Name

Type

Description

Device is ready for a new sequence

0

1

0

RDY/BSY Ready/Busy Status

R

Device is busy with an internal operation

6.2

Read STATUS Register (RDSR)

The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy

and write enable status of the device can be determined by the RDSRinstruction. Similarly, the Block

Write Protection (BP<1:0>) bits indicate the extent of memory array protection employed. The STATUS

register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon

completion of the opcode, the device will return the 8‑bit STATUS register value on the SO pin.

Figure 6-1.ꢀRDSR Waveform

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

SI

RDSR Opcode (05h)

0

1

0

1

MSB

STATUS Register Data Out

High-Impedance

SO

D7

D6

D5 D4

D3 D2

D1

D0

MSB

6.3

Write Enable (WREN) and Write Disable (WRDI)

Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the

Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the

status of the WEL bit in the STATUS register.

6.3.1

Write Enable Instruction (WREN)

The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write

STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by

sending a WREN(06h) instruction to the AT25128B/AT25256B. First, the CS pin is driven low to select the

device and then a WRENinstruction is clocked in on the SI pin. Then the CS pin can be driven high and

the WEL bit will be updated in the STATUS register to a logic ‘1’. The device will power‑up in the write

disable state (WEL = 0).

DS20006193A-page 19

AT25128B/AT25256B

Device Commands and Addressing

Figure 6-2.ꢀWREN Timing

CS

0

1

2

3

4

5

6

7

SCK

SI

WREN Opcode (06h)

0

1

0

MSB

High-Impedance

SO

6.3.2

Write Disable Instruction (WRDI)

To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h)

disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDIinstruction is independent

of the status of the WP pin.

Figure 6-3.ꢀWRDI Timing

CS

0

1

2

3

4

5

6

7

SCK

SI

WRDI Opcode (04h)

0

1

0

MSB

High-Impedance

SO

6.4

Write STATUS Register (WRSR)

The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the

STATUS register. Before a WRSRinstruction can be initiated, a WRENinstruction must be executed to set

the WEL to logic ‘1’. Upon completion of a WRENinstruction, a WRSRinstruction can be executed.

Note:ꢀ The WRSRinstruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only

bit 7, bit 3 and bit 2 can be changed via the WRSRinstruction. These modifiable bits are the Write Protect

Enable (WPEN) and Block Protect (BP<1:0>) bits. These three bits are nonvolatile bits that have the

same properties and functions as regular EEPROM cells. Their values are retained while power is

removed from the device.

DS20006193A-page 20

AT25128B/AT25256B

Device Commands and Addressing

The AT25128B/AT25256B will not respond to commands other than a RDSRafter a WRSRinstruction until

the self-timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the

STATUS register is reset to logic ‘0’.

Figure 6-4.ꢀWRSR Waveform

(1)

CS

t_WC

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

SI

STATUS Register Data In

WRSR Opcode (01h)

0

1

D7

X

D3

D2

X

MSB

High-Impedance

SO

Note:ꢀ

1. This instruction initiates a self-timed internal write cycle (t_WC) on the rising edge of CS after a valid

sequence.

6.4.1

Block Write-Protect Function

The WRSRinstruction allows the user to select one of four possible combinations as to how the memory

array will be inhibited from writing through changing the Block Write-Protect bits (BP<1:0>). The four

levels of array protection are:

• None of the memory array is protected.

• Upper quarter (¼) address range is write-protected meaning the highest order address bits are read-

only.

• Upper half (½) address range is write-protected meaning the highest order address bits are read-

only.

• All of the memory array is write-protected meaning all address bits are read-only.

The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.

Table 6-4.ꢀBlock Write-Protect Bits

Level

STATUS Register Bits

Write-Protected/Read‑Only Address Range

BP1

0

BP0

0

AT25128B

None

AT25256B

None

0

1

1(1/4)

2(1/2)

3(All)

3000h-3FFFh

2000h-3FFFh

0000h-3FFFh

6000h-7FFFh

4000h – 7FFFh

0000h – 7FFFh

1

0

1

DS20006193A-page 21

AT25128B/AT25256B

Device Commands and Addressing

6.4.2

Write-Protect Enable Function

The WRSRinstruction also allows the user to enable or disable the Write-Protect (WP) pin through the use

of the Write-Protect Enable (WPEN) bit. When the WPEN bit is set to logic ‘0’, the ability to write the

EEPROM array is dictated by the values of the Block Write-Protect (BP<1:0>) bits. The ability to write the

STATUS register is controlled by the WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS register

is read-only.

Hardware Write Protection is enabled when both the WP pin is low and the WPEN bit has been set to a

logic ‘1’. When the device is Hardware Write‑Protected, writes to the STATUS register, including the Block

Write‑Protect , WEL and WPEN bits, and to the sections in the memory array selected by the Block

Write‑Protect bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to

sections of the memory that are not block‑protected.

Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is a logic ‘0’. When

Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not

block‑protected. Refer to Table 6-5 for additional information.

Note:ꢀ When the WPEN bit is Hardware Write‑Protected, it cannot be set back to a logic ‘0’ as long as

the WP pin is held low.

Table 6-5.ꢀWPEN Operation

WPEN

WP

WEL

Protected Blocks

Unprotected Blocks

STATUS Register

0

1

x

0

1

0

1

0

1

Protected

Writable

Protected

Writable

Protected

Writable

Protected

Writable

x

Low

High

Protected

Writable

DS20006193A-page 22

AT25128B/AT25256B

Read Sequence

7.

Read Sequence

Reading the AT25128B/AT25256B via the SO pin requires the following sequence. After the CS line is

pulled low to select a device, the READ(03h) instruction is transmitted via the SI line followed by the

16‑bit address to be read. Refer to Table 7-1 for the address bits for AT25128B/AT25256B.

Table 7-1.ꢀAT25128B/AT25256B Address Bits

Address

A_N

AT25128B

A₁₃–A₀

AT25256B

A₁₄–A₀

A₁₅

Don’t Care Bits

A₁₅–A₁₄

Upon completion of the 16‑bit address, any data on the SI line will be ignored. The data (D7‑D0) at the

specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be

driven high after the data comes out. The read sequence can be continued since the byte address is

automatically incremented and data will continue to be shifted out. When the highest‑order address bit is

reached, the address counter will rollover to the lowest‑order address bit allowing the entire memory to be

read in one continuous read cycle regardless of the starting address.

Figure 7-1.ꢀRead Waveform

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

19 20 21 22 23 24 25 26 27 28 29 30 31

SCK

SI

READ Opcode (03h)

Address Bits A15-A0

0

1

A

MSB

Data Byte 1

High-Impedance

D

SO

MSB

DS20006193A-page 23

AT25128B/AT25256B

Write Sequence

8.

Write Sequence

In order to program the AT25128B/AT25256B, two separate instructions must be executed. First, the

device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write

sequences described in this section may be executed.

Note:ꢀ If the device is not Write Enabled (WREN), the device will ignore the WRITEinstruction and will

return to the standby state when CS is brought high. A new CS assertion is required to re‑initiate

communication.

The address of the memory location(s) to be programmed must be outside the protected address field

location selected by the block write protection level. During an internal write cycle, all commands will be

ignored except the RDSRinstruction. Refer to Table 8-1 for the address bits for AT25128B/AT25256B.

Table 8-1.ꢀAT25128B/AT25256B Address Bits

Address

A_N

AT25128B

A₁₃–A₀

AT25256B

A₁₄–A₀

A₁₅

Don’t Care Bits

A₁₅–A₁₄

8.1

Byte Write

A Byte Write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low

to select the device, the WRITE(02h) instruction is transmitted via the SI line followed by the 16‑bit

address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high.

The low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time

(Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25128B/AT25256B is automatically

returned to the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.

Figure 8-1.ꢀByte Write

CS

(1)

t_WC

0

1

2

3

4

5

6

7

8

9

10 11 12

21 22 23 24 25 26 27 28 29 30 31

SCK

SI

WRITE Opcode (02h)

Address Bits A15-A0

Data In

0

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

MSB

High-Impedance

SO

Note:ꢀ

1. This instruction initiates a self-timed internal write cycle (t_WC) on the rising edge of CS after a valid

sequence.

DS20006193A-page 24

AT25128B/AT25256B

Write Sequence

8.2

Page Write

A Page Write sequence allows up to 64 bytes to be written in the same write cycle, provided that all bytes

are in the same row of the memory array. Partial Page Writes of less than 64 bytes are allowed. After

each byte of data is received, the six lowest order address bits are internally incremented following the

receipt of each data byte. The higher order address bits are not incremented and retain the memory array

page location. If more bytes of data are transmitted that what will fit to the end of that memory row, the

address counter will rollover to the beginning of the same row. Nevertheless, creating a rollover event

should be avoided as previously loaded data in the page could become unintentionally altered. The

AT25128B/AT25256B is automatically returned to the Write Disable state (WEL = 0) at the completion of

a write cycle.

Figure 8-2.ꢀPage Write

CS

(1)

t_WC

0

1

2

3

4

5

6

7

8

9

21 22 23 24 25 26 27 28 29 30 31

SCK

SI

WRITE Opcode (02h)

Address Bits A15-A0

Data In Byte 1

Data In Byte 64

0

1

0

A

D

MSB

High-Impedance

SO

Note:ꢀ

1. This instruction initiates a self‑timed internal write cycle (t_WC) on the rising edge of CS after a valid

sequence.

8.3

Polling Routine

A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait

the fixed maximum write cycle time (t_WC). This method allows the application to know immediately when

the write cycle has completed to start a subsequent operation.

Once the internally-timed write cycle has started, a polling routine can be initiated. This involves

repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed

its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still

in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSRcommands can

be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction.

Only the Read STATUS Register (RDSR) instruction is enabled during the write cycle.

DS20006193A-page 25

AT25128B/AT25256B

Write Sequence

Figure 8-3.ꢀPolling Flowchart

Deassert

CS to V_CCto

Initiate a

Send Valid

Write

Protocol

Send RDSR

Instruction

to the Device

Does

RDY/BSY

Continue to

Next Operation

YES

= 0?

Write Cycle

NO

DS20006193A-page 26

AT25128B/AT25256B

Packaging Information

9.

Packaging Information

9.1

Package Marking Information

AT25128B and AT25256B: Package Marking Information

8-Lead TSSOP

8-Lead SOIC

ATMLHYWW

###% CO

YYWWNNN

ATHYWW

###%CO

YYWWNNN

8-Ball VFBGA

8-Pad UDFN

2.0 x 3.0 mm Body

2.35 x 3.73 mm Body

###

H%

NNN

###U

WWNNN

Note 1:

designates pin 1

Note 2: Package drawings are not to scale

Catalog Number Truncation

AT25128B

Truncation Code ###: 5DB

Truncation Code ###: 5EB

AT25256B

Date Codes

Voltages

% = Minimum Voltage

YY = Year

16: 2016

17: 2017

18: 2018

19: 2019

Y = Year

WW = Work Week of Assembly

20: 2020

21: 2021

22: 2022

23: 2023

6: 2016

7: 2017

8: 2018

9: 2019

0: 2020

1: 2021

2: 2022

3: 2023

02: Week 2

04: Week 4

...

L: 1.8V min

52: Week 52

Country of Origin

Device Grade

H or U: Industrial Grade

Atmel Truncation

CO = Country of Origin

AT: Atmel

ATM: Atmel

ATML: Atmel

Lot Number or Trace Code

NNN = Alphanumeric Trace Code (2 Characters for Small Packages)

DS20006193A-page 27

AT25128B/AT25256B

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

2X

0.10 C A–B

D

A

D

NOTE 5

N

E

2

E1

2

E1

E

1

2

NOTE 1

e

NX b

0.25

C A–B D

B

NOTE 5

TOP VIEW

0.10 C

C

A2

A

SEATING

PLANE

8X

SIDE VIEW

A1

h

R0.13

h

H

0.23

L

SEE VIEW C

(L1)

VIEW A–A

VIEW C

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2

DS20006193A-page 28

AT25128B/AT25256B

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

Molded Package Thickness

Standoff

Overall Width

A

-

1.75

-

0.25

A2

A1

E

1.25

0.10

§

6.00 BSC

Molded Package Width

Overall Length

E1

D

3.90 BSC

4.90 BSC

Chamfer (Optional)

Foot Length

h

L

0.25

0.40

-

0.50

1.27

Footprint

L1

1.04 REF

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0°

0.17

0.31

5°

-

8°

c

0.25

0.51

15°

b

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.15mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2

DS20006193A-page 29

AT25128B/AT25256B

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

SILK SCREEN

C

Y1

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

E

C

X1

Y1

1.27 BSC

5.40

Contact Pad Spacing

Contact Pad Width (X8)

Contact Pad Length (X8)

0.60

1.55

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev E

DS20006193A-page 30

AT25128B/AT25256B

Packaging Information

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

b

e

c

φ

A

A2

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.20

1.05

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.80

0.05

1.00

–

Overall Width

6.40 BSC

Molded Package Width

Molded Package Length

Foot Length

E1

D

4.30

2.90

0.45

4.40

4.50

3.10

0.75

3.00

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

c

0.09

0.20

0.30

Lead Width

b

0.19

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-086B

DS20006193A-page 31

AT25128B/AT25256B

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006193A-page 32

AT25128B/AT25256B

Packaging Information

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

(DATUM A)

(DATUM B)

NOTE 1

2X

0.10 C

1

2

2X

TOP VIEW

0.10 C

A1

0.10 C

0.08 C

C

A

SEATING

PLANE

8X

(A3)

SIDE VIEW

0.10

C A B

D2

e

2

1

2

0.10

K

C A B

E2

N

L

8X b

0.10

0.05

C A B

e

C

BOTTOM VIEW

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2

DS20006193A-page 33

AT25128B/AT25256B

Packaging Information

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Length

Exposed Pad Length

Overall Width

Exposed Pad Width

Terminal Width

Terminal Length

N

e

8

0.50 BSC

0.55

0.02

0.152 REF

2.00 BSC

1.50

3.00 BSC

1.30

A

A1

A3

D

D2

E

E2

b

L

0.50

0.00

0.60

0.05

1.40

1.60

1.20

0.18

0.35

0.20

1.40

0.30

0.45

-

0.25

0.40

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2

DS20006193A-page 34

AT25128B/AT25256B

Packaging Information

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

X2

EV

G2

8

ØV

C

Y2

G1

Y1

1

2

SILK SCREEN

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.50 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C

1.60

1.40

2.90

Contact Pad Width (X8)

Contact Pad Length (X8)

Contact Pad to Center Pad (X8)

Contact Pad to Contact Pad (X6)

Thermal Via Diameter

X1

Y1

G1

G2

V

0.30

0.85

0.20

0.33

0.30

1.00

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-21355-Q4B Rev A

DS20006193A-page 35

AT25128B/AT25256B

Packaging Information

f

0.10 C

d

0.10

A

(4X)

d

0.08

Øb

C

A1 BALL

PAD

CORNER

C

D

A1 BALL PAD CORNER

2

1

A

B

C

D

j

n 0.15 m C A B

n 0.08 m

C

e

E

B

(e1)

A1

d

A2

A

(d1)

TOP VIEW

BOTTOM VIEW

SIDE VIEW

8 SOLDER BALLS

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

NOTE

SYMBOL

A

0.81 0.91 1.00

0.15 0.20 0.25

0.40 0.45 0.50

0.25 0.30 0.35

2.35 BSC

A1

A2

b

D

Notes:

E

3.73 BSC

1. This drawing is for general

e

0.75 BSC

e1

d

0.74 REF

2. Dimension 'b' is measured at the maximum solder ball diameter.

3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.

0.75 BSC

d1

0.80 REF

6/11/13

TITLE

GPC

DRAWING NO.

8U2-1

REV.

G

8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,

Very Thin, Fine-Pitch Ball Grid Array Package

(VFBGA)

GWW

Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

DS20006193A-page 36

AT25128B/AT25256B

Revision History

10.

Revision History

Revision A (May 2019)

Updated to the Microchip template. Microchip DS20006193 replaces Atmel document 8698. Updated Part

Marking Information. Added ESD rating. Removed lead finish designation. Added POR recommendations

section. Updated trace code format in package markings. Updated section content throughout for

clarification. Updated the SOIC, TSSOP, and UDFN package drawings to the Microchip equivalents.

Atmel Document 8698 Revision E (January 2015)

Added the UDFN Expanded Quantity Option and ordering information. Updated the 8MA2 package

outline drawing.

Atmel Document 8698 Revision D (July 2014)

Updated part markings, 8MA2 and 8U2-1 package drawings, package 8A2 to 8X, template, logos, and

disclaimer page. No change to functional specification.

Atmel Document 8698 Revision C (August 2011)

Updated 8A2 and 8S1 package drawings. Corrected page 13, Device Density from 156K to 256K.

Corrected page 9, table headings. Corrected cross references on pages 7, 8, and 9.

Atmel Document 8698 Revision B (March 2010)

Updated Catalog Numbering Scheme. Updated Ordering Information and package types.

Atmel Document 8698 Revision A (December 2009)

Initial document release.

DS20006193A-page 37

AT25128B/AT25256B

The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as

a means to make files and information easily available to customers. Accessible by using your favorite

Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design

resources, user’s guides and hardware support documents, latest software releases and archived

software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online

discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Microchip sales offices, distributors and factory

representatives

Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products.

Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata

related to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on

“Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.

Local sales offices are also available to help customers. A listing of sales offices and locations is included

in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

DS20006193A-page 38

AT25128B/AT25256B

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

A T 2 5 1 2 8 B - S S H L - B

Shipping Carrier Option

B = Bulk (Tubes)

T

= Tape and Reel, Standard Quantity Option

E = Tape and Reel, Extended Quantity Option

Product Family

25 = Standard SPI

Serial EEPROM

Operating Voltage

L

= 1.8V to 5.5V

Device Grade or

Wafer/Die Thickness

H or U = Industrial Temperature Range

(-40°C to +85°C)

Device Density

128 = 128-Kilobit

256 = 256-Kilobit

11

= 11mil Wafer Thickness

Device Revision

Package Option

SS

X

= SOIC

= TSSOP

MA = 2.0mm x 3.0mm UDFN

= VFBGA

C

WWU = Wafer Unsawn

WDT = Die in Tape and Reel

Examples:

Device

Package Package Package

Shipping Carrier

Option

Device Grade

Drawing

Code

Option

AT25128B‑SSHL‑B

AT25128B‑SSHL‑T

AT25256B‑SSHL‑T

AT25128B‑XHL‑B

AT25256B‑XHL‑T

AT25128B‑MAHL‑E

AT25256B‑MAHL‑T

AT25256B‑MAHL‑E

AT25256B‑CUL‑T

SOIC

SN

SS

X

Bulk (Tubes)

Tape and Reel

Bulk (Tubes)

Industrial

Temperature

(-40°C to 85°C)

SOIC

SN

TSSOP

UDFN

VFBGA

ST

X

Tape and Reel

Q4B

8U2-1

MA

C

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

DS20006193A-page 39

AT25128B/AT25256B

• Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the

operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is

engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their

code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the

code protection features of our products. Attempts to break Microchip’s code protection feature may be a

violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software

or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for

your convenience and may be superseded by updates. It is your responsibility to ensure that your

application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS

CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life

support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting

from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,

chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,

SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight

Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,

CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,

ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient

Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,

Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

DS20006193A-page 40

AT25128B/AT25256B

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

ISBN: 978-1-5224-4457-2

Quality Management System Certified by DNV

ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer

fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures are for its PIC^®MCUs and dsPIC^®

DSCs, KEELOQ^®code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design and manufacture of development

systems is ISO 9001:2000 certified.

DS20006193A-page 41

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

China - Nanjing

Tel: 91-20-4121-0141

Japan - Osaka

Fax: 45-4485-2829

Finland - Espoo

Tel: 81-6-6152-7160

Japan - Tokyo

Tel: 358-9-4520-820

France - Paris

Web Address:

www.microchip.com

Atlanta

Tel: 81-3-6880- 3770

Korea - Daegu

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Duluth, GA

Tel: 82-53-744-4301

Korea - Seoul

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

Tel: 60-4-227-8870

Philippines - Manila

Tel: 63-2-634-9065

Singapore

Germany - Haan

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-67-3636

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Tel: 512-257-3370

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Tel: 86-25-8473-2460

China - Qingdao

Tel: 86-532-8502-7355

China - Shanghai

Tel: 86-21-3326-8000

China - Shenyang

Tel: 86-24-2334-2829

China - Shenzhen

Tel: 86-755-8864-2200

China - Suzhou

Itasca, IL

Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-9-744-7705

Italy - Milan

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Tel: 86-186-6233-1526

China - Wuhan

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Novi, MI

Tel: 86-27-5980-5300

China - Xian

Tel: 248-848-4000

Houston, TX

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Tel: 86-29-8833-7252

China - Xiamen

Tel: 281-894-5983

Indianapolis

Tel: 86-592-2388138

China - Zhuhai

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS20006193A-page 42


型号：	AT25128B-MAHL-E
厂家：	MICROCHIP
描述：	EEPROM, 16KX8, Serial, CMOS, PDSO8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总42页 (文件大小：1320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT25128B-MAHL-E [MICROCHIP]

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AT25128B-MAHL-T

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AT25128B-XHL-B

AT25128B-XHL-B

AT25128B-XHL-T

AT25128C1-10CC

AT25128C1-10CC-1.8

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