AT25256B-SSHL-T [MICROCHIP]
IC EEPROM 256KBIT 20MHZ 8SOIC;
| 型号： | AT25256B-SSHL-T |
| 厂家： | 
MICROCHIP |
| 描述： | IC EEPROM 256KBIT 20MHZ 8SOIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT25128B and AT25256B
SPI Serial EEPROM
128K (16,384 x 8), 256K (32,768 x 8)
DATASHEET
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
̶
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
VCC = 1.8V to 5.5V
̶
20MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
̶
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and
Software Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
̶
̶
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
Green (Pb/Halogen-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT25128B/256B provides 131,072/262,144 bits of Serial Electrically
Erasable Programmable Read-Only Memory (EEPROM) organized as
16,384/32,768 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operation are essential. The AT25128B/256B is available in space saving JEDEC
SOIC, TSSOP, UDFN, and VFBGA packages.
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed
via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block Write protection is enabled by programming the status register with one of
four blocks of Write Protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware Data Protection
is provided via the WP pin to protect against inadvertent write attempts. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
1.
Pin Configurations
Table 1-1.
Pin Configurations
8-lead SOIC
8-lead TSSOP
Pin Name
CS
Function
1
2
3
4
8
7
6
5
CS
SO
VCC
Chip Select
CS
SO
WP
VCC
1
2
3
4
8
7
6
5
HOLD
SCK
SI
HOLD
SCK
SI
GND
HOLD
SCK
SI
Ground
WP
GND
Suspends Serial Input
Serial Data Clock
Serial Data Input
Serial Data Output
Power Supply
Write Protect
GND
Top View
Top View
SO
8-ball VFBGA
8-pad UDFN
VCC
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
VCC
CS
CS
VCC
HOLD
SCK
SI
WP
HOLD
SCK
SI
SO
SO
WP
GND
WP
GND
Bottom View
Bottom View
Note: Drawings are not to scale.
2.
Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
Operating Temperature . . . . . . . . . . .-55C to +125C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
absolute maximum rating conditions for
extended periods may affect device reliability.
2
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
Memory Array
16,384/32,768 x 8
Address
Decoder
Status
Register
Data
Register
Output
Buffer
Mode
Decode
Logic
Clock
Generator
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
3
4.
Electrical Characteristics
4.1
Pin Capacitance(1)
Table 4-1.
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1MHz, VCC = +5V (unless otherwise noted).
Symbol Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
COUT
CIN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
4.2
DC Characteristics
Table 4-2.
DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted).
Symbol Parameter
Test Condition
Min
1.8
2.5
4.5
Typ
Max
5.5
5.5
5.5
Units
VCC1
VCC2
VCC3
Supply Voltage
V
V
V
Supply Voltage
Supply Voltage
VCC = 5V at 20MHz
SO = Open, Read
ICC1
ICC2
ICC3
Supply Current
Supply Current
Supply Current
9
5
10
7
mA
mA
mA
VCC = 5V at 10MHz
SO = Open, Read, Write
VCC = 5V at 1MHz
SO = Open, Read, Write
2.2
3.5
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.5V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
0.2
0.5
2
3
3
5
3
μA
μA
μA
μA
-3
-3
VIN = 0V to VCC
TAC = 0°C to 70°C
IOL
Output Leakage
3
μA
(1)
VIL
Input Low-voltage
Input High-voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
V
V
(1)
VIH
VCC x 0.7
VOL1
VOH1
VOL2
VOH2
Output Low-voltage 3.6V VCC 5.5V
Output High-voltage 3.6V VCC 5.5V
Output Low-voltage 1.8V VCC 3.6V
Output High-voltage 1.8V VCC 3.6V
IOL = 3.00mA
IOH = -1.60mA
IOL = 0.15mA
IOH = -100μA
VCC – 0.8
VCC – 0.2
0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
4.3
AC Characteristics
Table 4-3.
AC Characteristics
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
2
2
2
tFI
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
20
40
80
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
20
40
80
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
CS Setup Time
CS Hold Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
tHD
tCD
tV
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
20
40
80
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
tHO
Output Hold Time
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
5
Table 4-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
25
50
100
tLZ
Hold to Output Low Z
ns
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
25
50
100
tHZ
Hold to Output High Z
Output Disable Time
ns
ns
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
25
50
100
tDIS
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
3.3V, 25C, Page Mode
1,000,000
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5.
Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave.
Transmitter/Receiver: The AT25128B/256B has separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode which defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25128B/256B, and the serial
output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
Chip Select: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the SO pin will remain in a high-impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high-impedance
state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25128B/256B
in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions
are enabled when the WPEN bit is set to one.
6
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
Figure 5-1.
SPI Serial Interface
Master:
Slave:
Microcontroller
Data Out (MOSI)
Data In (MISO)
Serial Clock (SPI CK)
SS0
AT25128B/256B
SI
SO
SCK
CS
SS1
SI
SS2
SO
SCK
CS
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
7
6.
Functional Description
The AT25128B/256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of
the 6800 series of microcontrollers.
The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in Figure 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Table 6-1.
Instruction Set for the AT25010B/020B/040B
Instruction Name
Instruction Format
0000 X110
Operation
WREN
WRDI
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
0000 X100
RDSR
WRSR
READ
WRITE
0000 X101
0000 X001
0000 X011
0000 X010
Write Enable (WREN): The device will power-up in the Write Disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held
high during a WREN instruction.
Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR): The Read Status Register instruction provides access to the status register.
The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 6-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 0 (RDY)
Bit 1 = 0 indicates the device is not write enabled.
Bit 1 = 1 indicates the device is write enabled.
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
See Table 6-4.
See Table 6-4.
Bits 4 to 6 are zeros when the device is not in an internal write cycle.
See Table 6-5.
Bit 7 (WPEN)
Bits 0 to 7 are ones during an internal write cycle.
8
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The AT25128B/256B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the
memory segments can be protected. Any of the data within any selected segment will therefore be read-only.
The block write protection levels and corresponding status register control bits are shown in Table 6-4.
Bits BP1, BP0, and WPEN are nonvolatile cells that have the same properties and functions as the regular
memory cells (e.g., WREN, tWC, RDSR).
Table 6-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25128B
None
AT25256B
None
0
0
0
1
1
0
1
0
1
1 (¼)
2 (½)
3 (All)
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN
bit is one. The hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero.
When the device is hardware write protected, writes to the Status Register including the Block Protect bits, the
WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to
sections of the memory which are not block-protected.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP
pin is held low.
Table 6-5.
WPEN Operation
WPEN
WP
X
WEN
Protected Blocks
Protected
Unprotected Blocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
0
1
0
1
0
1
X
Protected
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
Read Sequence (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After
the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the byte
address to be read (Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The Read Sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous
read cycle.
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
9
Write Sequence (WRITE): In order to program the AT25128B/256B, the Write Protect pin (WP) must be held
high and two separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to
be programmed must be outside the protected address field location selected by the Block Write Protection
level. During an internal write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
opcode is transmitted via the SI line followed by the byte address and the data (D7 D0) to be programmed
(see Table 6-6 for the address key). Programming will start after the CS pin is brought high. The low-to-high
transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)
instruction. If Bit 0 is one, the write cycle is still in progress. If Bit 0 is zero, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
The AT25128B/256B is capable of an 64-byte Page Write operation. After each byte of data is received, the six
low-order address bits are internally incremented by one; the high-order bits of the address will remain constant.
If more than 64 bytes of data are transmitted, the address counter will roll-over, and the previously written data
will be overwritten. The AT25128B/256B is automatically returned to the Write Disable state at the completion of
a write cycle.
Note: If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS falling edge is
required to reinitiate the serial communication.
Table 6-6.
Address Key
Address
AN
AT25128B
A13 – A0
AT25256B
A14 – A0
A15
Don’t Care Bits
A15 – A14
10
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
7.
Timing Diagrams — SPI Mode 0 (0,0)
Figure 7-1.
Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
VIL
tWH
tWL
SCK
tSU
tH
VIH
VIL
Valid In
SI
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 7-2.
WREN Timing
CS
SCK
SI
WREN Opcode
HI-Z
SO
Figure 7-3.
WRDI Timing
CS
SCK
SI
WRDI Opcode
HI-Z
SO
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
11
Figure 7-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 7-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
5
11
12
13
14
1
15
0
SCK
SI
Data In
3
Instruction
7
6
4
2
High-impedance
SO
Figure 7-6.
READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Byte Address
...
Instruction
AN
A0
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
MSB
12
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
Figure 7-7.
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Byte Address
Data In
...
Instruction
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
High-impedance
SO
Figure 7-8.
HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
13
8.
Ordering Code Detail
A T 2 5 1 2 8 B - S S H L - B
Atmel Designator
Shipping Carrier Option
B or Blank = Bulk (Tubes)
T
E
= Tape and Reel, Standard Quantity Option
= Tape and Reel, Expanded Quantity Option
Product Family
25 = Standard SPI
Serial EPPROM
Operating Voltage
L
= 1.8V to 5.5V
Device Density
Package Device Grade or
Wafer/Die Thickness
128 = 128 kilobit
256 = 256 kilobit
H
= Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
Device Revision
U
= Green, Matte Sn Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS = JEDEC SOIC
X
= TSSOP
MA = UDFN
C
= VFBGA
WWU = Wafer Unsawn
WDT = Die in Tape and Reel
14
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
9.
Part Markings
AT25128B and AT25256B: Package Marking Information
8-lead TSSOP
8-lead SOIC
ATHYWW
AAAAAAA
ATMLHYWW
###%
AAAAAAAA
###% @
@
8-pad UDFN
8-ball VFBGA
2.0 x 3.0 mm Body
2.35 x 3.73 mm Body
###
###U
@YMXX
H%@
YXX
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25128B
AT25256B
Truncation Code ###: 5DB
Truncation Code ###: 5EB
Date Codes
Voltages
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
M = Month
WW = Work Week of Assembly
% = Minimum Voltage
L: 1.8V min
8: 2018
9: 2019
0: 2020
1: 2021
A: January
B: February
...
02: Week 2
04: Week 4
...
L: December
52: Week 52
Country of Assembly
Lot Number
AAA...A = Atmel Wafer Lot Number
Grade/Lead Finish Material
@ = Country of Assembly
U: Industrial/Matte Tin/SnAgCu
H: Industrial/NiPdAu
Trace Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/11/14
TITLE
DRAWING NO.
REV.
25128-256BSM, AT25128B and AT25256B Package Marking
Information
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
25128-256BSM
A
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
15
10. Ordering Information
Delivery Information
Operation
Range
Atmel Ordering Code
Lead Finish
Package
Form
Quantity
AT25128B-SSHL-B
Bulk (Tubes)
Tape and Reel
Bulk (Tubes)
100 per Tube
8S1
AT25128B-SSHL-T
AT25128B-XHL-B
AT25128B-XHL-T
AT25128B-MAHL-T
AT25128B-MAHL-E
4,000 per Reel
100 per Tube
NiPdAu
(Lead-free/Halogen-free)
8X
Tape and Reel
Tape and Reel
Tape and Reel
5,000 per Reel
5,000 per Reel
15,000 per Reel
Industrial
Temperature
(-40 to +85C)
8MA2
SnAgCu
(Lead-free/Halogen-free)
AT25128B-CUL-T
8U2-1
Wafer
Tape and Reel
5,000 per Reel
AT25128B-WWU11L (1)
N/A
Note 1
AT25256B-SSHL-B
AT25256B-SSHL-T
AT25256B-XHL-B
AT25256B-XHL-T
AT25256B-MAHL-T
AT25256B-MAHL-E
Bulk (Tubes)
Tape and Reel
Bulk (Tubes)
100 per Tube
4,000 per Reel
100 per Tube
8S1
8X
NiPdAu
(Lead-free/Halogen-free)
Tape and Reel
Tape and Reel
Tape and Reel
5,000 per Reel
5,000 per Reel
15,000 per Reel
Industrial
Temperature
(-40 to +85C)
8MA2
SnAgCu
(Lead-free/Halogen-free)
AT25256B-CUL-T
8U2-1
Wafer
Tape and Reel
5,000 per Reel
AT25256B-WWU11L (1)
N/A
Note 1
Note:
1. Contact Atmel Sales for Wafer sales.
Package Type
8-lead, 0.15" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
8S1
8X
8MA2
8U2-1
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN)
8-ball, 2.35mm x 3.73mm body, 0.75mm pitch, Very Thin, Fine-Pitch Ball Grid Array (VFBGA)
16
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
11. Packaging Information
11.1 8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
–
–
NOTE
SYMBOL
A1
A
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Ø
6/22/11
DRAWING NO. REV.
8S1
TITLE
GPC
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
G
Package Drawing Contact:
packagedrawings@atmel.com
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
17
11.2 8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
A2
D
SYMBOL
MIN
-
NOM
-
MAX
1.20
0.15
1.05
3.10
NOTE
2, 5
A
Side View
A1
A2
D
0.05
0.80
2.90
-
Notes: 1. This drawing is for general information only.
1.00
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
3.00
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
E
6.40 BSC
4.40
E1
b
4.30
0.19
4.50
0.30
3, 5
4
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
0.25
e
0.65 BSC
0.60
L
0.45
0.09
0.75
0.20
L1
C
1.00 REF
-
2/27/14
TITLE
GPC
TNR
DRAWING NO.
REV.
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
8X
E
Package Drawing Contact:
packagedrawings@atmel.com
18
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
11.3 8MA2 — 8-pad UDFN
E
1
8
7
6
5
Pin 1 ID
2
3
4
D
C
TOP VIEW
E2
SIDE VIEW
A2
A
A1
b (8x)
8
1
2
3
4
COMMON DIMENSIONS
(Unit of Measure = mm)
7
6
5
Pin#1 ID
D2
MIN
0.50
MAX
0.60
NOM
0.55
NOTE
SYMBOL
A
A1
A2
D
0.0
-
0.02
-
0.05
0.55
2.10
1.60
3.10
1.40
0.30
e (6x)
L (8x)
BOTTOM VIEW
K
1.90
1.40
2.90
1.20
0.18
2.00
D2
E
1.50
3.00
Notes:
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
E2
b
1.30
0.25
3
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
C
1.52 REF
0.35
L
0.30
0.20
0.40
-
e
0.50 BSC
-
K
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
11/26/14
TITLE
DRAWING NO.
REV.
GPC
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
YNZ
8MA2
G
Package Drawing Contact:
packagedrawings@atmel.com
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
19
11.4 8U2-1 — 8-ball VFBGA
f 0.10
C
d 0.10
(4X)
d 0.08
C
A1 BALL
D
C
A
A1 BALL PAD CORNER
PAD
2
1
CORNER
Øb
A
B
C
D
j n0.15 m C A B
j n0.08 m C
e
E
B
(e1)
A1
A2
A
d
(d1)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
A
0.81 0.91 1.00
0.15 0.20 0.25
0.40 0.45 0.50
0.25 0.30 0.35
2.35 BSC
A1
A2
b
D
Notes:
E
e
3.73 BSC
0.75 BSC
1. This drawing is for general
e1
d
d1
0.74 REF
0.75 BSC
0.80 REF
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
6/11/13
TITLE
GPC
DRAWING NO.
8U2-1
REV.
G
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package
(VFBGA)
GWW
Package Drawing Contact:
packagedrawings@atmel.com
20
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
12. Revision History
Doc. Rev.
Date
Comments
Add the UDFN Expanded Quantity Option and ordering information.
Update the 8MA2 package outline drawing.
8698E
01/2015
Update part markings, 8MA2 and 8U2-1 package drawings, package 8A2 to 8X, template,
logos, and disclaimer page. No change to functional specification.
8698D
8698C
07/2014
08/2011
Update 8A2 and 8S1 package drawings.
Correct page 13, Device Density from 156K to 256K.
Correct page 9, table headings.
Correct cross references on pages 7, 8, and 9.
Update Catalog Numbering Scheme.
8698B
8698A
03/2010
12/2009
Update Ordering Information and package types.
Initial document release.
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
21
X
X X X X
X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015.
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