AT27C010-45JJ [MICROCHIP]
OTP ROM, 128KX8, 45ns, CMOS, PQCC32;
| 型号： | AT27C010-45JJ |
| 厂家： | 
MICROCHIP |
| 描述： | OTP ROM, 128KX8, 45ns, CMOS, PQCC32 OTP只读存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 45 ns
• Low-Power CMOS Operation
– 100 µA Max Standby
– 25 mA Max Active at 5 MHz
• JEDEC Standard Packages
– 32-lead PDIP
– 32-lead PLCC
– 32-lead TSOP
1-Megabit
(128K x 8)
OTP EPROM
• 5V 10% Supply
• High Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
• Rapid Programming Algorithm – 100 µs/Byte (Typical)
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial Temperature Range
• Green (Pb/Halide-free) Packaging Option
AT27C010
1. Description
The AT27C010 is a low-power, high-performance 1,048,576-bit one-time programma-
ble read-only memory (OTP EPROM) organized as 128K by 8 bits. They require only
one 5V power supply in normal read mode operation. Any byte can be accessed in
less than 45 ns, eliminating the need for speed reducing WAIT states on high-perfor-
mance microprocessor systems.
In read mode, the AT27C010 typically consumes only 8 mA. Standby mode supply
current is typically less than 10 µA.
The AT27C010 is available in a choice of industry-standard JEDEC-approved one-
time programmable (OTP) plastic PDIP, PLCC, and TSOP packages. All devices fea-
ture two line control (CE, OE) to give designers the flexibility to prevent bus
contention.
With 128K byte storage capability, the AT27C010 allows firmware to be stored reliably
and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C010 has additional features to ensure high quality and efficient produc-
tion use. The Rapid Programming Algorithm reduces the time required to program the
part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
0321M–EPROM–12/07
2. Pin Configurations
Pin Name
A0 - A16
O0 - O7
CE
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
No Connect
OE
PGM
NC
2.3
32-lead TSOP (Type 1) Top View
2.1
32-lead PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
2
A8
3
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 O7
A13
A14
NC
4
5
6
PGM
VCC
VPP
A16
A15
A12
A7
7
8
A2 10
A1 11
A0 12
O0 13
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
2.2
32-lead PDIP Top View
VPP
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 PGM
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 O7
20 O6
19 O5
18 O4
17 O3
A6
A5
A4
A3
A2 10
A1 11
A0 12
O0 13
O1 14
O2 15
GND 16
2
AT27C010
0321M–EPROM–12/07
AT27C010
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute Max-
imum Ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these or any other
conditions beyond those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
CC + 0.75V DC which may overshoot to +7.0 volts for pulses of less than 20 ns.
V
3
0321M–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
VIL
X
OE
VIL
VIH
X
PGM
X(1)
X
Ai
VPP
X
Outputs
DOUT
Read
Ai
Output Disable
X
X
High Z
High Z
DIN
Standby
VIH
VIL
VIL
VIH
X
X
X
Rapid Program(2)
PGM Verify
PGM Inhibit
VIH
VIL
X
VIL
VIH
X
Ai
Ai
VPP
VPP
VPP
DOUT
X
High Z
(3)
A9 = VH
Product Identification(4)
VIL
VIL
X
A0 = VIH or VIL
A1 - A16 = VIL
X
Identification Code
Note:
1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. VH = 12.0 0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27C010
-45
-70
Operating Temp. (Case)
VCC Power Supply
Ind.
-40°C - 85°C
5V 10%
-40°C - 85° C
5V 10%
8. DC and Operating Characteristics for Read Operation
Min
Max
Units
µA
µA
µA
µA
mA
mA
V
Symbol
Parameter
Condition
ILI
Input Load Current
VIN = 0V to VCC
VOUT = 0V to VCC
VPP = VCC
Ind.
Ind.
1
ILO
Output Leakage Current
VPP(1)) Read/Standby Current
5
10
IPP1(2)
ISB1 (CMOS), CE = VCC 0.3V
100
1
ISB
VCC(1) Standby Current
I
SB2 (TTL), CE = 2.0 to VCC + 0.5V
ICC
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
f = 5 MHz, IOUT = 0 mA, CE = VIL
25
VIL
-0.6
2.0
0.8
VIH
VOL
VOH
VCC + 0.5
0.4
V
IOL = 2.1 mA
IOH = -400 µA
V
2.4
V
Note:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
4
AT27C010
0321M–EPROM–12/07
AT27C010
9. AC Characteristics for Read Operation
AT27C010
-45
-70
Symbol
Parameter
Condition
CE = OE = VIL
OE = VIL
Min
Max
Min
Max
70
Units
ns
(3)
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
45
45
20
20
(2)
tCE
70
ns
(2)(3)
tOE
CE = VIL
30
ns
(4)(5)
tDF
OE or CE High to Output Float, whichever occurred first
25
ns
tOH
Output Hold from Address, CE or OE, whichever occurred first
7
7
ns
10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing
measurement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL =
0.45V and VIH = 2.4V.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0321M–EPROM–12/07
11. Input Test Waveforms and Measurement Levels
For -45 devices only:
tR, tF < 5 ns (10% to 90%)
For -70 devices:
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note:
CL = 100 pF including jig
capacitance, except for
the -45 devices, where
CL = 30 pF.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
8
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
6
AT27C010
0321M–EPROM–12/07
AT27C010
14. Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C010 at 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
7
0321M–EPROM–12/07
15. DC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits
Symbol
ILI
Parameter
Test Conditions
Min
Max
10
Units
µA
V
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
-0.6
2.0
0.8
VIH
Input High Level
VCC + 1
0.4
V
VOL
VOH
ICC2
IPP2
VID
Output Low Voltage
IOL = 2.1 mA
V
Output High Voltage
VCC Supply Current (Program and Verify)
VPP Supply Current
IOH = -400 µA
2.4
V
40
20
mA
mA
V
CE = PGM = VIL
A9 Product Identification Voltage
11.5
12.5
16. AC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25 V, VPP = 13.0 0.25V
Limits
Symbol
tAS
Parameter
Test Conditions(1)
Min
Max
Units
µs
Address Setup Time
CE Setup Time
2
2
tCES
tOES
tDS
µs
Input Rise and Fall Times
(10% to 90%) 20 ns
OE Setup Time
2
µs
Data Setup Time
2
µs
Input Pulse Levels
0.45V to 2.4V
tAH
Address Hold Time
Data Hold Time
0
µs
tDH
2
µs
tDFP
tVPS
tVCS
tPW
OE High to Output Float Delay(2)
0
130
ns
Input Timing Reference Level
0.8V to 2.0V
VPP Setup Time
2
µs
VCC Setup Time
2
µs
Output Timing Reference Level
0.8V to 2.0V
PGM Program Pulse Width(3)
Data Valid from OE
VPP Pulse Rise TIme During Programming
95
105
150
µs
tOE
ns
tPRT
50
ns
Note:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP..
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µsec 5%.
17. Atmel’s AT27C010 Integrated Product Identification Code
Pins
Hex
Codes
A0
0
O7
0
O6
0
O5
0
O4
1
O3
1
O2
1
O1
1
O0
0
Data
Manufacturer
Device Type
1E
05
1
0
0
0
0
0
1
0
1
8
AT27C010
0321M–EPROM–12/07
AT27C010
18. Rapid Programming Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs
PGM pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are
applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been
applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All bytes
are read again and compared with the original data to determine if the device passes or fails.
9
0321M–EPROM–12/07
19. Ordering Information
19.1 Standard Package
I
Active
25
CC (mA)
tACC
(ns)
Standby
Ordering Code
AT27C010-45JI
Package
32J
Operation Range
45
70
0.1
0.1
Industrial
AT27C010-45PI
AT27C010-45TI
32P6
32T
(-40°C to 85°C)
25
AT27C010-70JI
AT27C010-70PI
AT27C010-70TI
32J
Industrial
32P6
32T
(-40°C to 85°C)
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package Option (Pb/Halide-free)
I
Active
25
CC (mA)
tACC
(ns)
Standby
Ordering Code
AT27C010-45JU
Package
Operation Range
45
70
0.1
0.1
32J
Industrial
AT27C010-45PU
AT27C010-45TU
32P6
32T
(-40°C to 85°C)
25
AT27C010-70JU
AT27C010-70PU
AT27C010-70TU
32J
Industrial
32P6
32T
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6
32T
32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32-lead, Plastic Thin Small Outline Package (TSOP)
10
AT27C010
0321M–EPROM–12/07
AT27C010
20. Package Information
20.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
11
0321M–EPROM–12/07
20.2 32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
41.783
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
42.291 Note 1
15.875
E
–
E1
B
–
13.970 Note 1
0.559
–
B1
L
–
1.651
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
32P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
12
AT27C010
0321M–EPROM–12/07
AT27C010
20.3 32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
13
0321M–EPROM–12/07
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International
Atmel Corporation
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Tel: 1(408) 441-0311
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0321M–EPROM–12/07
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