AT28C010-12TU [MICROCHIP]
IC EEPROM 1MBIT 120NS 32TSOP;
| 型号： | AT28C010-12TU |
| 厂家： | 
MICROCHIP |
| 描述： | IC EEPROM 1MBIT 120NS 32TSOP 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总16页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 120 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
• Low Power Dissipation
1-megabit
(128K x 8)
Paged Parallel
EEPROM
– 40 mA Active Current
– 200 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• Single 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option Only
AT28C010
1. Description
The AT28C010 is a high-performance electrically-erasable and programmable read-
only memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Man-
ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 200 µA.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28C010 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
128 bytes of EEPROM for device identification or tracking.
0353I–PEEPR–08/09
AT28C010
2.2
32-lead PLCC Top View
2. Pin Configurations
Pin Name
A0 - A16
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
OE
WE
I/O0 - I/O7
NC
A2 10
A1 11
A0 12
I/O0 13
DC
Don’t Connect
Note:
PLCC package pin 1 is Don’t Connect.
2.1
32-lead TSOP Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
2
0353I–PEEPR–08/09
AT28C010
3. Block Diagram
4. Device Operation
4.1
Read
The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28C010 allows 1 to 128 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 127 additional
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC
limit is exceeded the AT28C010 will cease accepting data and commence the internal program-
ming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes which
are specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
4.4
DATA Polling
The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write
cycle.
3
0353I–PEEPR–08/09
4.5
Toggle Bit
In addition to DATA Polling the AT28C010 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28C010 in the following ways: (a)
CC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay –
V
once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing
a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles;
and (d) noise filter—pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a
write cycle.
4.6.2
Software Data Protection
A software controlled data protection feature has been implemented on the AT28C010. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP
disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC the entire AT28C010 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C010. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
4.7
Device Identification
An extra 128 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
4.8
Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see Software Chip Erase
application note for details.
4
AT28C010
0353I–PEEPR–08/09
AT28C010
5. DC and AC Operating Range
AT28C010-12
-40°C - 85°C
5V 10%
AT28C010-15
-40°C - 85°C
5V 10%
Operating Temperature (Case)
Ind.
V
CC Power Supply
6. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
High Z
VIH
X
X
VIL
VIH
Output Disable
X
X
High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
7. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
μA
μA
μA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
10
ISB1
ISB2
ICC
CE = VCC - 0.3V to VCC + 1V
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
200
3
40
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
5
0353I–PEEPR–08/09
9. AC Read Characteristics
AT28C010-12
AT28C010-15
Symbol
Parameter
Min
Max
Min
Max
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
120
120
50
150
150
55
(1)
tCE
ns
(2)
tOE
0
0
0
0
ns
(3)(4)
tDF
50
55
ns
Output Hold from OE, CE or Address, Whichever
Occurred First
tOH
0
0
ns
ns
(5)
tCEPH
CE Pulse High Time
50
50
10. AC Read Waveforms(1)(2)(3)(4)
t
CEPH
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations otherwise incorrect data may be
read.
6
AT28C010
0353I–PEEPR–08/09
AT28C010
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
10
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0353I–PEEPR–08/09
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
100
50
0
ns
tDS
ns
t
DH, tOEH
Data, OE Hold Time
ns
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
8
AT28C010
0353I–PEEPR–08/09
AT28C010
16. Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
50
50
0
tAH
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
tBLC
tWPH
150
µs
50
ns
17. Page Mode Write Waveforms(1)(2)
Notes: 1. A7 through A16 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
tS = 5 μsec (min.)
tW = tH = 10 msec (min.)
VH = 12.0V 0.5V
9
0353I–PEEPR–08/09
19. Software Data Protection
Enable Algorithm(1)
20. Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA A0
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA AA
TO
LOAD DATA XX
TO
ANY ADDRESS(4)
ADDRESS 5555
LOAD DATA 55
TO
LOAD LAST BYTE
TO
ADDRESS 2AAA
LAST ADDRESS
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
2. Write Protect state will be activated at end of write
even if no other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS(4)
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 128 bytes of data are loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
21. Software Protected Write Cycle Waveforms(1)(2)(3)
Notes: 1. A0 through A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
10
AT28C010
0353I–PEEPR–08/09
AT28C010
22. Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
23. Data Polling Waveforms
24. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
25. Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0353I–PEEPR–08/09
26. Ordering Information
26.1 Green Package Option (Pb/Halide-free)
26.1.1
tACC
AT28C010
ICC (mA)
(ns)
Active
Standby
Ordering Code
AT28C010-12JU
AT28C010-12TU
AT28C010-15JU
AT28C010-15TU
Package
32J
Operation Range
120
40
40
0.2
32T
Industrial
(-40° to 85°C)
32J
150
0.2
32T
26.1.2
AT28C010E
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
AT28C010E-12JU
AT28C010E-12TU
AT28C010E-15JU
AT28C010E-15TU
Package
32J
Operation Range
120
150
40
40
0.2
32T
Industrial
(-40° to 85°C)
32J
0.2
32T
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32-lead, Plastic Thin Small Outline Package (TSOP)
32T
Options
Blank
E
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High-endurance Option: Endurance = 100K Write Cycles
26.2 Die Products
Reference Section: Contact Atmel Sales for Parallel EEPROM Die Product availability.
12
AT28C010
0353I–PEEPR–08/09
AT28C010
27. Packaging Information
27.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
13
0353I–PEEPR–08/09
27.2 32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
14
AT28C010
0353I–PEEPR–08/09
AT28C010
Revision History
Doc. Rev.
Date
Comments
0353I
08/2009
Updated AC Charcteristisitics and ordering information.
Add a revision history page and update this version ‘I’ with the
changes (AC charactertistics and ordering info from the word file).
0353I
07/2009
15
0353I–PEEPR–08/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Le Krebs
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Japan
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Tel: (852) 2245-6100
Fax: (852) 2722-1369
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
p_eeprom@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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0353I–PEEPR–08/09
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