AT28C256E-20DM/883-815 [MICROCHIP]
200NS CERDIP 883C; LEV B COMPLIANT;
| 型号： | AT28C256E-20DM/883-815 |
| 厂家： | 
MICROCHIP |
| 描述： | 200NS CERDIP 883C; LEV B COMPLIANT 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 150 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
• Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-byte Page Write Operation
• Low Power Dissipation
256K (32K x 8)
Paged Parallel
EEPROM
– 50 mA Active Current
– 200 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
AT28C256
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Full Military and Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT28C256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,
the CMOS standby current is less than 200 µA.
The AT28C256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28C256 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
0006M–PEEPR–12/09
2. Pin Configurations
Pin Name
A0 - A14
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
DC
Don’t Connect
2.3
32-pad LCC, 28-lead PLCC Top View
2.1
28-lead TSOP Top View
OE
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
A11
A9
2
CE
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
A13
WE
VCC
A14
A12
A7
5
6
7
A1 10
A0 11
8
9
NC 12
I/O0 13
10
11
12
13
14
A6
A5
A4
A1
A3
A2
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2.4
28-lead Cerdip/PDIP/Flatpack/SOIC –
Top View
2.2
28-lead PGA Top View
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
2
3
A6
4
A5
5
A9
A4
6
A11
OE
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
GND
2
AT28C256
0006M–PEEPR–12/09
AT28C256
3. Block Diagram
4. Device Operation
4.1
Read
The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28C256 allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC
limit is exceeded the AT28C256 will cease accepting data and commence the internal program-
ming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page
write operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes which
are specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
4.4
DATA Polling
The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write
cycle.
3
0006M–PEEPR–12/09
4.5
Toggle Bit
In addition to DATA Polling the AT28C256 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a)
VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay –
once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing
a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles;
and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a
write cycle.
4.6.2
Software Data Protection
A software controlled data protection feature has been implemented on the AT28C256. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP
disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to “Software Data Protection” algo-
rithm). After writing the 3-byte command sequence and after tWC the entire AT28C256 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C256. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
4.7
Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
4.8
Optional Chip Erase Mode
The entire device can be erased using a 6-byte software code. Please see “Software Chip
Erase” application note for details.
4
AT28C256
0006M–PEEPR–12/09
AT28C256
5. DC and AC Operating Range
AT28C256-15
AT28C256-20
AT28C256-25
AT28C256-35
Ind.
Mil.
-40°C - 85°C
-55°C - 125°C
5V ± 10%
Operating Temperature
(Case)
-55°C - 125°C
-55°C - 125°C
-55°C - 125°C
VCC Power Supply
5V ± 10%
5V ± 10%
5V ± 10%
6. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
Chip Erase
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V 0.5V.
7. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
10
Ind.
Mil.
200
300
3
ISB1
VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V
ISB2
ICC
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
50
VIL
0.8
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 2.1 mA
IOH = -400 µA
0.45
V
V
5
0006M–PEEPR–12/09
9. AC Read Characteristics
AT28C256-15
AT28C256-20
AT28C256-25
AT28C256-35
Symbol
Parameter
Min
Max
150
150
70
Min
Max
200
200
80
Min
Max
250
250
100
60
Min
Max
350
350
100
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
ns
(2)
tOE
0
0
0
0
0
0
0
0
ns
(3)(4)
tDF
50
55
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
0
0
0
ns
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT28C256
0006M–PEEPR–12/09
AT28C256
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0006M–PEEPR–12/09
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
50
0
ns
tCS
ns
tCH
0
ns
tWP
100
50
0
ns
tDS
ns
tDH, tOEH
tDV
Note:
Data, OE Hold Time
Time to Data Valid
ns
NR(1)
1. NR = No Restriction
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
8
AT28C256
0006M–PEEPR–12/09
AT28C256
16. Page Mode Characteristics
Symbol
Parameter
Min
Max
10
3
Units
ms
ms
ns
AT28C256
tWC
Write Cycle Time (option available)
AT28C256F
tAS
Address Setup Time
Address Hold Time
Data Setup Time
0
50
50
0
tAH
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
tBLC
tWPH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
150
µs
50
ns
17. Page Mode Write Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V 0.5V
9
0006M–PEEPR–12/09
19. Software Data Protection
Enable Algorithm(1)
20. Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA A0
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA AA
TO
LOAD DATA XX
TO
ANY ADDRESS(4)
ADDRESS 5555
LOAD DATA 55
TO
LOAD LAST BYTE
TO
ADDRESS 2AAA
LAST ADDRESS
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
2. Write Protect state will be activated at end of write
even if no other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS(4)
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
21. Software Protected Write Cycle Waveforms(1)(2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
10
AT28C256
0006M–PEEPR–12/09
AT28C256
22. Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
0
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See“AC Read Characteristics” on page 6.
23. Data Polling Waveforms
24. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
25. Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0006M–PEEPR–12/09
26. Normalized ICC Graphs
12
AT28C256
0006M–PEEPR–12/09
AT28C256
27. Ordering Information
27.1 27.1Military Dual Marked Package
27.1.1
AT28C256
tACC
ICC (mA)
Standby
(ns)
Active
Ordering Code
Package
Operation Range
AT28C256-15DM/883
5962-88525 14 XX(1)
5962-88525 06 XX
150
50
50
50
0.3
0.3
0.3
28D6
AT28C256-15FM/883
5962-88525 14 ZX(1)
5962-88525 06 ZX
28F
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256-15LM/883
5962-88525 14 YX(1)
5962-88525 06 YX
AT28C256-15UM/883
5962-88525 14 UX(1)
5962-88525 06 UX
28U
28D6
28F
32L
AT28C256-20DM/883
5962-88525 12 XX(1)
5962-88525 04 XX
200
AT28C256-20FM/883
5962-88525 12 ZX(1)
5962-88525 04 ZX
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256-20LM/883
5962-88525 12 YX(1)
5962-88525 04 YX
AT28C256-20UM/883
5962-88525 12 UX(1)
5962-88525 04 UX
28U
28D6
28F
32L
AT28C256-25DM/883
5962-88525 11 XX(1)
5962-88525 03 XX
250
AT28C256-25FM/883
5962-88525 11 ZX(1)
5962-88525 03 ZX
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256-25LM/883
5962-88525 11 YX(1)
5962-88525 03 YX
AT28C256-25UM/883
5962-88525 11 UX(1)
5962-88525 03 UX
28U
Note:
1. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual
marked along with Atmel part number.
13
0006M–PEEPR–12/09
27.1.2
AT28C256E
tACC
ICC (mA)
Standby
(ns)
Active
Ordering Code
Package
Operation Range
AT28C256E-15DM/883
5962-88525 16 XX(1)
5962-88525 08 XX
150
50
0.3
28D6
AT28C256E-15FM/883
5962-88525 16 ZX(1)
5962-88525 08 ZX
28F
32L
28U
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256E-15LM/883
5962-88525 16 YX(1)
5962-88525 08 YX
AT28C256E-15UM/883
5962-88525 16 UX(1)
5962-88525 08 UX
AT28C256E-20DM/883
AT28C256E-20FM/883
AT28C256E-20LM/883
AT28C256E-20UM/883
28D6
28F
200
250
50
50
0.3
0.3
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
32L
28U
AT28C256E-25DM/883
5962-88525 13 XX(1)
5962-88525 05 XX
28D6
28F
5962-88525 05 XX
5962-88525 13 ZX(1)
5962-88525 05 ZX
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256E-25LM/883
5962-88525 13 YX(1)
5962-88525 05 YX
32L
AT28C256E-25UM/883
5962-88525 13 UX(1)
5962-88525 05 UX
28U
Note:
1. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual
marked along with Atmel part number.
14
AT28C256
0006M–PEEPR–12/09
AT28C256
27.1.3
AT28C256F
tACC
ICC (mA)
Standby
0.3
(ns)
Active
50
Ordering Code
Package
Operation Range
150
AT28C256F-15DM/883
5962-88525 15 XX(3)
5962-88525 07 XX
28D6
AT28C256F-15FM/883
5962-88525 15 ZX(3)
5962-88525 07 ZX
28F
32L
28U
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
AT28C256F-15LM/883
5962-88525 15 YX(3)
5962-88525 07 YX
AT28C256F-15UM/883
5962-88525 15 UX(3)
5962-88525 07 UX
Notes: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525.
2. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type in the
SMD is 100% tested for this feature.
3. Where two DESC numbers apply to the Atmel ordering code apply SL815 to receive parts with the noted DESC number dual
marked along with Atmel part number.
Package Type
28D6
28F
32L
28U
W
28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip)
28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack)
32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC)
28-pin, Ceramic Pin Grid Array (PGA)
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
Fast Write Option: Write Time = 3 ms
E
F
15
0006M–PEEPR–12/09
27.2 Industrial Green Package Option (Pb/Halide-free)
27.2.1
AT28C256
tACC
ICC (mA)
Standby
0.2
(ns)
Active
Ordering Code
Package
Operation Range
150
50
AT28C256-15JU
AT28C256-15PU
AT28C256-15SU
AT28C256-15TU
32J
28P6
28S
28T
Industrial
(-40°C to 85°C)
27.2.2
AT28C256E
tACC
(ns)
150
ICC (mA)
Active
50
Standby
Ordering Code
Package
Operation Range
0.2
AT28C256E-15JU
AT28C256E-15SU
AT28C256E-15TU
32J
28S
28T
Industrial
(-40°C to 85°C)
27.2.3
AT28C256F
tACC
(ns)
150
ICC (mA)
Active
Standby
Ordering Code
Package
Operation Range
50
0.2
AT28C256F-15JU
AT28C256F-15SU
AT28C256F-15TU
32J
28S
28T
Industrial
(-40°C to 85°C)
Package Type
32J
28P6
28S
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
Options
28T
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
Fast Write Option: Write Time = 3 ms
E
F
28. Die Products
Reference Section: Contact Atmel sales for die sales options.
16
AT28C256
0006M–PEEPR–12/09
AT28C256
29. Packaging Information
29.1 28D6 – Cerdip
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 D-10 Config A (Glass Sealed)
37.85(1.490)
36.58(1.440)
PIN
1
15.49(0.610)
12.95(0.510)
33.02(1.300) REF
5.72(0.225)
MAX
0.127(0.005)MIN
SEATING
PLANE
1.52(0.060)
0.38(0.015)
0.66(0.026)
0.36(0.014)
5.08(0.200)
3.18(0.125)
1.65(0.065)
1.14(0.045)
2.54(0.100)BSC
15.70(0.620)
15.00(0.590)
0º~ 15º REF
0.46(0.018)
0.20(0.008)
17.80(0.700) MAX
10/23/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28D6, 28-lead, 0.600" Wide, Non-windowed,
Ceramic Dual Inline Package (Cerdip)
28D6
B
R
17
0006M–PEEPR–12/09
29.2 28F – Flatpack
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 F-12 Config B
9.40(0.370)
6.35(0.250)
PIN #1 ID
0.56(0.022)
0.38(0.015)
1.27(0.050) BSC
18.49(0.728)
18.08(0.712)
1.14(0.045) MAX
10.57(0.416)
9.75(0.384)
0.23(0.009)
0.10(0.004)
3.02(0.119)
2.29(0.090)
1.96(0.077)
1.09(0.043)
1.14(0.045)
7.26(0.286)
6.96(0.274)
0.660(0.026)
10/21/03
DRAWING NO. REV.
28F
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28F, 28-lead, Non-windowed, Ceramic Bottom-brazed
Flat Package (FlatPack)
B
R
18
AT28C256
0006M–PEEPR–12/09
AT28C256
29.3 32J – PLCC
1.14(0.045) X 45
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45 MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
19
0006M–PEEPR–12/09
29.4 32L – LCC
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
MIL-STD 1835 C-12
11.63(0.458)
11.23(0.442)
2.54(0.100)
2.16(0.085)
14.22(0.560)
13.72(0.540)
1.91(0.075)
1.40(0.055)
PIN 1
1.40(0.055)
1.14(0.045)
INDEX CORNER
2.41(0.095)
1.91(0.075)
0.635(0.025)
X 45˚
0.381(0.015)
0.305(0.012)
0.178(0.007)
RADIUS
10.16(0.400) BSC
0.737(0.029)
0.533(0.021)
1.27(0.050) TYP
1.02(0.040) X 45˚
2.16(0.085)
1.65(0.065)
7.62(0.300) BSC
10/21/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip
Carrier (LCC)
32L
B
R
20
AT28C256
0006M–PEEPR–12/09
AT28C256
29.5 28P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
36.703
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
37.338 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
28P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
21
0006M–PEEPR–12/09
29.6 28S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
PIN 1
1.27(0.50) BSC
TOP VIEW
18.10(0.7125)
17.70(0.6969)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
0º ~ 8º
1.27(0.050)
0.40(0.016)
8/4/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
28S
B
R
22
AT28C256
0006M–PEEPR–12/09
AT28C256
29.7 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
23
0006M–PEEPR–12/09
29.8 28U – PGA
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
7.26(0.286)
6.50(0.256)
13.74(0.540)
13.36(0.526)
2.57(0.101)
2.06(0.081)
1.40(0.055)
1.14(0.045)
0.58(0.023)
0.43(0.017)
15.24(0.600)
14.88(0.586)
3.12(0.123)
2.62(0.103)
1.83(0.072)
1.57(0.062)
14.17(0.558)
13.77(0.542)
2.54(0.100) TYP
16.71(0.658)
16.31(0.642)
12.70(0.500) TYP
2.54(0.100) TYP
10.41(0.410)
9.91(0.390)
10/21/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28U, 28-pin, Ceramic Pin Grid Array (PGA)
28U
B
R
24
AT28C256
0006M–PEEPR–12/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
p_eeprom@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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0006M–PEEPR–12/09
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