AT28HC64B-70JU-T [MICROCHIP]
EEPROM, 8KX8, 70ns, Parallel, CMOS, PQCC32;
| 型号： | AT28HC64B-70JU-T |
| 厂家： | 
MICROCHIP |
| 描述： | EEPROM, 8KX8, 70ns, Parallel, CMOS, PQCC32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 70 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
• Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum (Standard)
2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)
– 1 to 64-byte Page Write Operation
• Low Power Dissipation
64K (8K x 8)
High-speed
Parallel
– 40 mA Active Current
– 100 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling and Toggle Bit for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 100,000 Cycles
EEPROM with
Page Write and
Software Data
Protection
– Data Retention: 10 Years
• Single 5 V ±10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option Only
1. Description
AT28HC64B
The AT28HC64B is a high-performance electrically-erasable and programmable read-
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 55 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel’s AT28HC64B has additional features to ensure high quality and manufactura-
bility. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mecha-
nism is available to guard against inadvertent writes. The device also includes an
extra 64 bytes of EEPROM for device identification or tracking.
0274L–PEEPR–2/3/09
2.2
32-lead PLCC Top View
2. Pin Configurations
Pin Name
A0 - A12
CE
Function
Addresses
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
A1 10
A0 11
I/O0 - I/O7
NC
NC 12
I/O0 13
DC
Don’t Connect
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2.1
28-lead SOIC Top View
2.3
28-lead TSOP Top View
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
OE
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
A11
A9
2
3
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A8
4
A5
5
A9
NC
WE
VCC
NC
A12
A7
5
A4
6
A11
OE
6
A3
7
7
A2
8
A10
CE
8
A1
9
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A3
A2
2
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
3. Block Diagram
DATA INPUTS/OUTPUTS
VCC
GND
I/O0 - I/O7
OE
DATA LATCH
OE, CE and WE
LOGIC
WE
INPUT/OUTPUT
BUFFERS
CE
Y-GATING
Y DECODER
X DECODER
ADDRESS
INPUTS
CELL MATRIX
IDENTIFICATION
4. Device Operation
4.1
Read
The AT28HC64B is accessed like a Static RAM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high-impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus contention in their systems.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of tWC, a read operation will effectively be a polling operation.
4.3
Page Write
The page write operation of the AT28HC64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63
additional bytes. Each successive byte must be loaded within 150 µs (tBLC) of the previous
byte. If the tBLC limit is exceeded, the AT28HC64B will cease accepting data and commence
the internal programming operation. All bytes during a page write operation must reside on the
same page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition
during the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
4.4
DATA Polling
The AT28HC64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time
during the write cycle.
3
0274L–PEEPR–2/3/09
4.5
Toggle Bit
In addition to DATA Polling, the AT28HC64B provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling, and valid data will be read. Toggle bit reading may begin at any time during the write
cycle.
4.6
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect
the memory against inadvertent writes.
4.6.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28HC64B in the following ways:
(a) VCC sense – if VCC is below 3.8 V (typical), the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8 V, the device will automatically time out 5 ms (typical)
before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhib-
its write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a write cycle.
4.6.2
Software Data Protection
A software-controlled data protection feature has been implemented on the AT28HC64B.
When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28HC64B is shipped from Atmel with
SDP disabled.
SDP is enabled by the user issuing a series of three write commands in which three specific
bytes of data are written to three specific addresses (refer to the “Software Data Protection
Algorithm” diagram on page 10). After writing the 3-byte command sequence and waiting tWC
,
the entire AT28HC64B will be protected against inadvertent writes. It should be noted that
even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64B.
This is done by preceding the data to be written by the same 3-byte command sequence used
to enable SDP.
Once set, SDP remains active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP protects the AT28HC64B during power-up and power-
down conditions. All command sequences must conform to the page write timing specifica-
tions. The data in the enable and disable command sequences is not actually written into the
device; their addresses may still be written with user data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device, however. For the dura-
tion of tWC, read operations will effectively be polling operations.
4.7
Device Identification
An extra 64 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12 V ±0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the regular memory array.
4
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
5. DC and AC Operating Range
AT28HC64B-70
AT28HC64B-90
-40°C - 85°C
5 V ±10%
AT28HC64B-120
-40°C - 85°C
5 V ±10%
Operating Temperature (Case)
CC Power Supply
-40°C - 85°C
V
5 V ±10%
6. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
VIL
VIH
X(1)
X
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
Chip Erase
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. See “AC Write Waveforms” on page 8.
3. VH = 12.0 V ±0.5 V.
7. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground.................................-0.6 V to +6.25 V
All Output Voltages
with Respect to Ground...........................-0.6 V to VCC + 0.6 V
Voltage on OE and A9
with Respect to Ground..................................-0.6 V to +13.5V
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0 V to VCC + 1 V
VI/O = 0 V to VCC
ILO
10
ISB1
ISB2
ICC
CE = VCC - 0.3 V to VCC + 1 V
CE = 2.0 V to VCC + 1 V
f = 5 MHz; IOUT = 0 mA
100(1)
2(1)
40
VIL
0.8
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
VOL
VOH
IOL = 2.1 mA
IOH = -400 µA
0.40
V
V
Note:
1. ISB1 and ISB2 for the 55 ns part is 40 mA maximum.
5
0274L–PEEPR–2/3/09
9. AC Read Characteristics
AT28HC64B-70
AT28HC64B-90
AT28HC64B-120
Symbol Parameter
tACC Address to Output Delay
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Units
ns
(1)
tCE
CE to Output Delay
OE to Output Delay
OE to Output Float
Output Hold
70
90
ns
(2)
tOE
0
0
0
35
0
0
0
40
0
0
0
ns
(3)(4)
tDF
tOH
35
40
50
ns
ns
10. AC Read Waveforms(1)(2)(3)(4)
ADDRESS VALID
ADDRESS
CE
OE
tCE
tOE
tDF
tOH
tACC
HIGH Z
OUTPUT
OUTPUT VALID
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0 V
COUT
8
12
pF
VOUT = 0 V
Note:
1. This parameter is characterized and is not 100% tested.
7
0274L–PEEPR–2/3/09
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
50
0
ns
tCS
ns
tCH
0
ns
tWP
100
50
0
ns
tDS
ns
tDH, tOEH
Data, OE Hold Time
ns
15. AC Write Waveforms
15.1 WE Controlled
tOES
OE
tOEH
ADDRESS
tCH
tAS
tAH
CE
tCS
WE
tWP
tDS
tDH
DATA IN
15.2 CE Controlled
tOES
OE
tOEH
ADDRESS
tCH
tAS
tAH
WE
CE
tCS
tWP
tDS
tDH
DATA IN
8
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
16. Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
ms
ms
ns
tWC
Write Cycle Time
10
2
tWC
Write Cycle Time (Use AT28HC64BF))
Address Setup Time
Address Hold Time
Data Setup Time
tAS
0
50
50
0
tAH
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
100
ns
tBLC
tWPH
Byte Load Cycle Time
Write Pulse Width High
150
µs
50
ns
17. Page Mode Write Waveforms(1)(2)
OE
CE
tBLC
tWPH
tWP
WE
tAS
tDH
tAH
A0 -A12
VALID ADD
tDS
VALID DATA
DATA
tWC
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
18. Chip Erase Waveforms
tS
tH
tW
tS = tH = 5 µs (min.)
tW = 10 ms (min.)
VH = 12.0 V ±0.5 V
9
0274L–PEEPR–2/3/09
19. Software Data Protection Enable
Algorithm(1)
20. Software Data Protection Disable
Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 1555
ADDRESS 1555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 0AAA
ADDRESS 0AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 1555
ADDRESS 1555
WRITES ENABLED(2)
LOAD DATA XX
TO
LOAD DATA AA
TO
ANY ADDRESS(4)
ADDRESS 1555
LOAD LAST BYTE
TO
LOAD DATA 55
TO
LAST ADDRESS
ENTER DATA
ADDRESS 0AAA
PROTECT STATE
LOAD DATA 20
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A12 - A0 (Hex).
ADDRESS 1555
EXIT DATA
PROTECT STATE(3)
2. Write Protect state will be activated at end of write
even if no other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS(4)
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
4. 1 to 64 bytes of data are loaded.
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A12 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
21. Software Protected Write Cycle Waveforms(1)(2)
OE
CE
tBLC
tWPH
tWP
WE
tAS
tDH
tAH
A0 -A5
A6 - A12
tDS
DATA
tWC
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
10
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
22. Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
0
ns
OE to Output Delay(1)
Write Recovery Time
ns
tWR
0
ns
Note:
1. These parameters are characterized and not 100% tested. See “AC Read Characteristics” on page 6.
23. Data Polling Waveforms
tOEH
tDH
tWR
tOE
24. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
25. Toggle Bit Waveforms(1)(2)(3)
tOEH
tOE
tDH
(2)
tWR
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used, but the address should not vary.
11
0274L–PEEPR–2/3/09
26. Normalized ICC Graphs
12
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
27. Ordering Information
27.1 Green Package Option (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
AT28HC64B-70TU
AT28HC64B-70JU
AT28HC64B-70SU
AT28HC64B-90JU
AT28HC64B-90SU
Package
28T
Operation Range
70
40
0.1
32J
28S
32J
Industrial
28S
90
40
40
0.1
0.1
(-40°C to 85°C)
AT28HC64B-90TU
AT28HC64B-12JU
AT28HC64B-12SU
28T
32J
28S
120
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28S
28T
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
27.2 Die Products
Contact Atmel Sales for die sales options.
13
0274L–PEEPR–2/3/09
28. Packaging Information
28.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
14
AT28HC64B
0274L–PEEPR–2/3/09
AT28HC64B
28.2 28S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
PIN 1
1.27(0.50) BSC
TOP VIEW
18.10(0.7125)
17.70(0.6969)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
0º ~ 8º
1.27(0.050)
0.40(0.016)
8/4/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
28S
B
R
15
0274L–PEEPR–2/3/09
28.3 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
16
AT28HC64B
0274L–PEEPR–2/3/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
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0274L–PEEPR–2/3/09
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