AT89C51ID2-RLTUM_技术文档

Features

• 80C52 Compatible

– 8051 Instruction Compatible

– Six 8-bit I/O Ports (64 pins or 68 Pins Versions)

– Four 8-bit I/O Ports (44 Pins Version)

– Three 16-bit Timer/Counters

– 256 bytes Scratch Pad RAM

– 10 Interrupt Sources With 4 Priority Levels

• ISP (In-System Programming) Using Standard V_CCPower Supply

• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

• Boot ROM Contains Low Level Flash Programming Routines and a Default Serial

Loader

8-bit Flash

Microcontroller

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)

– In X2 Mode (6 Clocks/Machine Cycle)

20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)

• 64K bytes On-chip Flash Program/Data Memory

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

AT89C51ID2

• On-chip 1792 bytes Expanded RAM (XRAM)

– Software Selectable Size (0, 256, 512, 768, 1024, 1792 bytes)

– 768 bytes Selected at Reset for T89C51RD2 Compatibility

• On-chip 2048 bytes EEPROM block for Data Storage

– 100k Write Cycles

• Dual Data Pointer

• 32 KHz Crystal Oscillator

• Variable Length MOVX for Slow RAM/Peripherals

• Improved X2 Mode with Independant Selection for CPU and Each Peripheral

• Keyboard Interrupt Interface on Port 1

• SPI Interface (Master/Slave Mode)

• 8-bit Clock Prescaler

• Two Wire Interface 400K bit/s

• Programmable Counter Array with:

– High Speed Output

– Compare/Capture

– Pulse Width Modulator

– Watchdog Timer Capabilities

• Asynchronous Port Reset

• Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator

• Low EMI (inhibit ALE)

• Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag

• Power Control Modes: Idle Mode, Power-down Mode

• Power Supply: 2.7V to 5.5V

• Temperature Ranges: Industrial (-40 to +85°C)

• Packages: PLCC44, VQFP44

Description

AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single

chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program

and for data.

The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial

mode with the ISP capability or with software. The programming voltage is internally

generated from the standard V_CCpin.

4289C–8051–11/05

1

The AT89C51ID2 retains all features of the Atmel 80C52 with 256 bytes of internal

RAM, a 10-source 4-level interrupt controller and three timer/counters.

In addition, the AT89C51ID2 has a Programmable Counter Array, an XRAM of 1792

bytes, a Hardware Watchdog Timer, SPI and Keyboard, a more versatile serial channel

that facilitates multiprocessor communication (EUART) and a speed improvement

mechanism (X2 mode).

The fully static design of the AT89C51ID2 allows to reduce system power consumption

by bringing the clock frequency down to any value, even DC, without loss of data.

The AT89C51ID2 has 2 software-selectable modes of reduced activity and 8-bit clock

prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen

while the peripherals and the interrupt system are still operating. In the power-down

mode the RAM is saved and all other functions are inoperative.

The added features of the AT89C51ID2 make it more powerful for applications that need

pulse width modulation, high speed I/O and counting capabilities such as alarms, motor

control, corded phones, smart card readers.

Table 1. Memory Size and I/O pins

TOTAL RAM

AT89C51ID2

Flash (bytes)

XRAM (bytes)

(bytes)

I/O

PLCC44/VQFP44

64K

1792

2048

34

2

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Block Diagram

Figure 1. Block Diagram

(1)

(2) (2)

(1)

(1) (1)

(1)

XTALA1

Watch

Dog

POR

PFD

Flash

64Kx8

RAM

256x8

XRAM

1792 x 8

PCA

EUART

XTALA2

E² DATA

2K x 8

Keyboard

Timer2

XTALB1(1)

XTALB2

C51

CORE

IB-bus

CPU

ALE/PROG

PSEN

EA

RD

Parallel I/O Ports &

External Bus

BOOT Regulator

(2)

Timer 0

Timer 1

INT

Ctrl

SPI

TWI

2K x8

POR / PFD

ROM

Port 2

Port 0 Port 1

Port 3 Port4 Port 5

WR

(2) (2)

(3) (3)

(1)

(1)(1)

(1): Alternate function of Port 1

(2): Alternate function of Port 3

(3): Alternate function of Port I2

3

4289C–8051–11/05

AT89C51ID2

SFR Mapping

The Special Function Registers (SFRs) of the AT89C51ID2 fall into the following

categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP

I/O port registers: P0, P1, P2, P3, PI2

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,

RCAP2L, RCAP2H

•

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,

CCAPxL (x: 0 to 4)

•

Power and clock control registers: PCON

Hardware Watchdog Timer registers: WDTRST, WDTPRG

Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1

Keyboard Interface registers: KBE, KBF, KBLS

SPI registers: SPCON, SPSTR, SPDAT

2-wire Interface registers: SSCON, SSCS, SSDAT, SSADR

BRG (Baud Rate Generator) registers: BRL, BDRCON

Flash register: FCON

Clock Prescaler register: CKRL

32 kHz Sub Clock Oscillator registers: CKSEL, OSSCON

Others: AUXR, AUXR1, CKCON0, CKCON1

4

4289C–8051–11/05

Table 2. C51 Core SFRs

Mnemonic

ACC

B

Add Name

7

6

5

4

3

2

1

0

E0h Accumulator

F0h B Register

PSW

SP

D0h Program Status Word

81h Stack Pointer

CY

AC

F0

RS1

RS0

OV

F1

P

DPL

82h Data Pointer Low byte

83h Data Pointer High byte

DPH

Table 3. System Management SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

PCON

87h Power Control

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

EXTRA

M

AUXR

8Eh Auxiliary Register 0

A2h Auxiliary Register 1

-

M0

XRS1

GF3

XRS0

0

AO

ENBOO

T

AUXR1

-

DPS

CKRL

97h Clock Reload Register

85h Clock Selection Register

86h Oscillator Control Register

8Fh Clock Control Register 0

AFh Clock Control Register 1

-

CKSEL

-

CKS

OSCON

CKCKON0

CKCKON1

-

SIX2

-

T2X2

-

SCLKT0 OscBEn

OscAEn

X2

TWIX2

-

WDTX2

-

PCAX2

-

T1X2

-

T0X2

-

SPIX2

Table 4. Interrupt SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

IEN0

A8h Interrupt Enable Control 0

B1h Interrupt Enable Control 1

B7h Interrupt Priority Control High 0

B8h Interrupt Priority Control Low 0

B3h Interrupt Priority Control High 1

B2h Interrupt Priority Control Low 1

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

IEN1

IPH0

IPL0

IPH1

IPL1

-

PSH

PSL

-

ESPI

PX1H

PX1L

SPIH

SPIL

ETWI

PT0H

PT0L

IE2CH

IE2CL

EKBD

PX0H

PX0L

KBDH

KBDL

PPCH

PT2H

PT1H

PPCL

PT2L

PT1L

-

5

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 5. Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

P0

80h 8-bit Port 0

P1

P2

P3

P4

P5

90h 8-bit Port 1

A0h 8-bit Port 2

B0h 8-bit Port 3

C0h 8-bit Port 4

E8h 8-bit Port 5

-

C7h 8-bit Port 5 (byte addressable)

Table 6. Flash and EEPROM Data Memory SFR

Mnemonic

Add Name

7

6

5

4

3

2

1

0

FCON

D1h Flash Control

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

EECON

EEPROM data Control

Table 7. Timer SFRs

Mnemonic

TCON

TMOD

TL0

Add Name

7

6

5

4

3

2

1

0

88h Timer/Counter 0 and 1 Control

89h Timer/Counter 0 and 1 Modes

8Ah Timer/Counter 0 Low Byte

8Ch Timer/Counter 0 High Byte

8Bh Timer/Counter 1 Low Byte

8Dh Timer/Counter 1 High Byte

A6h WatchDog Timer Reset

A7h WatchDog Timer Program

C8h Timer/Counter 2 control

C9h Timer/Counter 2 Mode

TF1

TR1

C/T1#

TF0

M11

TR0

M01

IE1

IT1

IE0

M10

IT0

M00

GATE1

GATE0

C/T0#

TH0

TL1

TH1

WDTRST

WDTPRG

T2CON

T2MOD

-

TF2

-

EXF2

-

RCLK

-

TCLK

-

WTO2

TR2

-

WTO1

C/T2#

T2OE

WTO0

CP/RL2#

DCEN

EXEN2

-

Timer/Counter 2 Reload/Capture

High byte

RCAP2H

RCAP2L

CBh

Timer/Counter 2 Reload/Capture

Low byte

CAh

TH2

TL2

CDh Timer/Counter 2 High Byte

CCh Timer/Counter 2 Low Byte

6

4289C–8051–11/05

Table 8. PCA SFRs

Mnemo

-nic

Add Name

7

6

5

-

4

3

2

1

0

CCON

CMOD

CL

D8h PCA Timer/Counter Control

D9h PCA Timer/Counter Mode

E9h PCA Timer/Counter Low byte

F9h PCA Timer/Counter High byte

CF

CIDL

CR

CCF4

-

CCF3

-

CCF2

CPS1

CCF1

CPS0

CCF0

ECF

WDTE

-

CH

CCAPM0 DAh PCA Timer/Counter Mode 0

CCAPM1 DBh PCA Timer/Counter Mode 1

CCAPM2 DCh PCA Timer/Counter Mode 2

CCAPM3 DDh PCA Timer/Counter Mode 3

CCAPM4 DEh PCA Timer/Counter Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

-

CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0

CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0

CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0

CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0

CCAP4H FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0

CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0

CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0

CCAP2L ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0

CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0

CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0

Table 9. Serial I/O Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

SCON

98h Serial Control

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SBUF

99h Serial Data Buffer

B9h Slave Address Mask

A9h Slave Address

9Bh Baud Rate Control

9Ah Baud Rate Reload

SADEN

SADDR

BDRCON

BRL

BRR

TBCK

RBCK

SPD

SRC

Table 10. SPI Controller SFRs

Mnemonic

SPCON

SPSTA

Add Name

7

6

5

4

3

2

1

0

C3h SPI Control

C4h SPI Status

C5h SPI Data

SPR2

SPIF

SPD7

SPEN

WCOL

SPD6

SSDIS

SSERR

SPD5

MSTR

MODF

SPD4

CPOL

-

CPHA

-

SPR1

-

SPR0

-

SPDAT

SPD3

SPD2

SPD1

SPD0

7

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 11. Two-Wire Interface Controller SFRs

Mnemonic

SSCON

SSCS

Add Name

7

6

5

4

3

2

1

0

93h Synchronous Serial control

94h Synchronous Serial Status

95h Synchronous Serial Data

96h Synchronous Serial Address

SSCR2

SSC4

SSD7

SSA7

SSPE

SSC3

SSD6

SSA6

SSSTA

SSC2

SSD5

SSA5

SSSTO

SSC1

SSD4

SSA4

SSI

SSAA

0

SSCR1

0

SSCR0

0

SSC0

SSD3

SSA3

SSDAT

SSD2

SSA2

SSD1

SSA1

SSD0

SSGC

SSADR

Table 12. Keyboard Interface SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

KBLS

9Ch Keyboard Level Selector

9Dh Keyboard Input Enable

9Eh Keyboard Flag Register

KBLS7

KBE7

KBF7

KBLS6

KBE6

KBF6

KBLS5

KBE5

KBF5

KBLS4

KBE4

KBF4

KBLS3

KBE3

KBF3

KBLS2

KBE2

KBF2

KBLS1

KBE1

KBF1

KBLS0

KBE0

KBF0

KBE

KBF

Table 13. EEPROM data Memory SFR

Mnemonic

Add Name

7

6

5

4

3

2

1

0

EECON

D2h EEPROM Data Control

EEE

EEBUSY

8

4289C–8051–11/05

Table below shows all SFRs with their address and their reset value.

Table 14. SFR Mapping

Bit

addressable

Non Bit addressable

0/8

1/9

CH

2/A

3/B

4/C

5/D

6/E

7/F

PI2

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

F8h

FFh

F7h

XXXX XX11

0000 0000

XXXX XXXX

B

F0h

E8h

0000 0000

P5 bit

addressable

CL

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

EFh

0000 0000

XXXX XXXX

1111 1111

ACC

0000 0000

E0h

D8h

D0h

C8h

E7h

DFh

D7h

CFh

CCON

CMOD

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

00X0 0000

00XX X000

X000 0000

FCON (1)

PSW

0000 0000

EECON

xxxx xx00

XXXX 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

P5 byte

Addressable

P4

SPCON

SPSTA

SPDAT

C0h

C7h

1111 1111

0001 0100

0000 0000

XXXX XXXX

1111 1111

IPL0

SADEN

B8h

B0h

A8h

A0h

98h

90h

88h

80h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

X000 000

0000 0000

P3

IEN1

IPL1

IPH1

IPH0

1111 1111

XXXX X000

XXXX X111

X000 0000

IEN0

SADDR

CKCON1

0000 0000

XXXX XXX0

P2

AUXR1

WDTRST

WDTPRG

1111 1111

XXXX X0X0

XXXX XXXX

XXXX X000

SCON

SBUF

BRL

BDRCON

KBLS

KBE

KBF

0000 0000

XXXX XXXX

0000 0000

XXX0 0000

0000 0000

P1

SSCON

SSCS

SSDAT

SSADR

CKRL

1111 1111

0000 0000

1111 1000

1111 1111

1111 1110

1111 1111

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON0

AUXR

XX00 1000

0000 0000

P0

CKSEL

OSSCON

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

1111 1111

XXXX XXX0

XXXX X001

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

9

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Pin Configurations

6

5 4 3 2 1

44 43 42 41 40

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEx4/MOSI

RST

39

38

7

8

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

37

9

10

11

12

13

36

35

34

33

P3.0/RxD

AT89C51ID2

PLCC44

PI2.1/SDA

P3.1/TxD

PI2.0/SCL

ALE/PROG

PSEN

P3.2/INT0

P3.3/INT1

P3.4/T0

14

15

16

17

32

31

30

29

P2.7/A15

P2.6/A14

P2.5/A13

P3.5/T1

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40 39 38 37 36 35 34

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

33

32

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEX4/MOSI

RST

1

2

31

30

3

4

29

28

27

P3.0/RxD

5

6

AT89C51ID2

VQFP44 1.4

PI2.1/SDA

P3.1/TxD

PI2.0/SCL

ALE/PROG

PSEN

7

8

26

25

24

23

P3.2/INT0

P3.3/INT1

P3.4/T0

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

P3.5/T1

1213141516171819202122

10

4289C–8051–11/05

Table 15. Pin Description

Pin Number

Type

Mnemonic

V_SS

PLCC44

VQFP44

Name and Function

22

44

16

I

Ground: 0V reference

Power Supply: This is the power supply voltage for normal, idle and power-down opera-

tion

V_CC

38

P0.0 - P0.7

43 - 36

37 - 30

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high impedance inputs. Port 0 must be polarized to V_CCor

V

_SSin order to prevent any parasitic current consumption. Port 0 is also the multiplexed

I/O

low-order address and data bus during access to external program and data memory. In

this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code

bytes during EPROM programming. External pull-ups are required during program verifica-

tion during which P0 outputs the code bytes.

P1.0 - P1.7

2 - 9

40 - 44

1 - 3

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, Port 1 pins that are externally pulled low will source current because of the internal

pull-ups. Port 1 also receives the low-order address byte during memory programming and

verification.

Alternate functions for AT89C51ID2 Port 1 include:

2

3

40

41

I/O

I

P1.0: Input/Output

T2 (P1.0): Timer/Counter 2 external count input/Clockout

XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier

P1.1: Input/Output

I/O

I

T2EX: Timer/Counter 2 Reload/Capture/Direction Control

SS: SPI Slave Select

I

4

5

6

7

42

43

44

1

I/O

I

P1.2: Input/Output

ECI: External Clock for the PCA

I/O

P1.3: Input/Output

CEX0: Capture/Compare External I/O for PCA module 0

P1.4: Input/Output

CEX1: Capture/Compare External I/O for PCA module 1

P1.5: Input/Output

CEX2: Capture/Compare External I/O for PCA module 2

MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in

slave mode, MISO outputs data to the master controller.

8

9

2

3

I/O

P1.6: Input/Output

CEX3: Capture/Compare External I/O for PCA module 3

SCK: SPI Serial Clock

P1.7: Input/Output:

CEX4: Capture/Compare External I/O for PCA module 4

11

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 15. Pin Description (Continued)

Pin Number

Type

Mnemonic

PLCC44

VQFP44

Name and Function

I/O

MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in

slave mode, MOSI receives data from the master controller.

Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock genera-

tor circuits.

XTALA1

21

15

I

XTALA2

XTALB1

20

2

14

40

O

I

Crystal A 2: Output from the inverting oscillator amplifier

Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

XTALB2

1

39

O

Crystal B 2: (Sub Clock) Output from the inverting oscillator amplifier

P2.0 - P2.7

24 - 31

18 - 25

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, Port 2 pins that are externally pulled low will source current because of the internal

pull-ups. Port 2 emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that use 16-bit addresses (MOVX

@DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to

external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of

the P2 SFR.

I/O

P3.0 - P3.7

11,

13 - 19

5,

7 - 13

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, Port 3 pins that are externally pulled low will source current because of the internal

pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below.

11

13

14

15

16

17

18

19

5

7

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

I

10

11

12

13

I

O

Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, Port 4 pins that are externally pulled low will source current because of the internal

pull-ups.

P4.0 - P4.7

-

I/O

Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, Port 5 pins that are externally pulled low will source current because of the internal

pull-ups.

P5.0 - P5.7

PI2.0 - PI2.1

Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc with

external resistor to prevent any parasitic current consumption).

34, 12

34

28, 6

28

I/O

SCL (PI2.0): 2-wire Serial Clock

SCL output the serial clock to slave peripherals

SCL input the serial clock from master

12

4289C–8051–11/05

Table 15. Pin Description (Continued)

Pin Number

Type

Mnemonic

PLCC44

VQFP44

Name and Function

SDA (PI2.1): 2-wire Serial Data

SDA is the bidirectional 2-wire data line

12

6

I/O

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V_SSpermits a power-on reset using only an external

capacitor to V_CC. This pin is an output when the hardware watchdog forces a system reset.

RST

10

33

4

I

ALE/PROG

27

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external

timing or clocking. Note that one ALE pulse is skipped during each access to external data

memory. This pin is also the program pulse input (PROG) during Flash programming. ALE

can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during

internal fetches.

PSEN

EA

32

35

26

29

O

I

Program Strobe ENable: The read strobe to external program memory. When executing

code from the external program memory, PSEN is activated twice each machine cycle,

except that two PSEN activations are skipped during each access to external data memory.

PSEN is not activated during fetches from internal program memory.

External Access Enable: EA must be externally held low to enable the device to fetch

code from external program memory locations 0000H to FFFFH. If security level 1 is pro-

grammed, EA will be internally latched on Reset.

13

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Oscillators

Overview

Two oscillators are available (for AT8xC51IxD2 devices only, the others part number

provide only the main high frequency oscillator):

•

OSCA used for high frequency: Up to 40 MHz

OSCB used for low frequency: 32.768 kHz

Several operating modes are available and programmable by software:

•

to switch OSCA to OSCB and vice-versa

to stop OSCA or OSCB to reduce consumption

In order to optimize the power consumption and the execution time needed for a specific

task, an internal prescaler feature has been implemented between the selected oscilla-

tor and the CPU.

Registers

Table 16. CKSEL Register (for AT8xC51Ix2 only)

CKSEL - Clock Selection Register (85h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

CKS

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

-

Reserved

CPU Oscillator Select Bit: (CKS)

Cleared, CPU and peripherals connected to OSCB

Set, CPU and peripherals connected to OSCA

0

CKS

Programmed by hardware after a Power-up regarding Hardware Security Byte

(HSB).HSB.OSC (Default setting, OSCA selected)

Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB))

Not bit addressable

14

4289C–8051–11/05

Table 17. OSCCON Register (for AT8xC51Ix2 only)

OSCCON- Oscillator Control Register (86h)

7

-

6

-

5

-

4

-

3

-

2

1

0

SCLKT0

OscBEn

OscAEn

Bit

Number

Mnemonic Description

7

6

5

4

3

-

Reserved

Sub Clock Timer0

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

Cleared by hardware after a Power Up

2

1

SCLKT0

OscBEn

OscB enable bit

Set by software to run OscB

Cleared by software to stop OscB

Programmed by hardware after a Power-up regarding HSB.OSC (Default

cleared, OSCB stopped)

OscA enable bit

Set by software to run OscA

Cleared by software to stop OscA

0

OscAEn

Programmed by hardware after a Power-up regarding HSB.OSC(Default Set,

OSCA runs)

Reset Value = XXXX X0’HSB.OSC’’HSB.OSC’b (see Hardware Security Byte (HSB))

Not bit addressable

Table 18. CKRL Register

CKRL - Clock Reload Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

Clock Reload Register:

7:0

CKRL

Prescaler value

Reset Value = 1111 1111b

Not bit addressable

15

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 19. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

Serial port Mode bit 0

SMOD0 Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

4

POF

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by software for general purpose usage.

Set by software for general purpose usage.

General purpose Flag

Cleared by software for general purpose usage.

Set by software for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

16

4289C–8051–11/05

Functional Block

Diagram

Figure 2. Functional Oscillator Block Diagram

Reload

Reset

PwdOscA

CKRL

FOSCA

XtalA1

OscA

1

0

8-bit

Prescaler-Divider

XtalA2

:2

0

1

OscAEn

1

0

X2

OSCCON

CLK

PERIPH

Peripheral Clock

CPU clock

CKCON0

CLK

CPU

CKRL=0xFF?

FOSCB

Idle

CKS

CKSEL

PwdOscB

XtalB1

:128

OscB

Sub

Clock

XtalB2

OscBEn

OSCCON

Operating Modes

Reset

A hardware RESET puts the Clock generator in the following state:

The selected oscillator depends on OSC bit in Hardware Security Byte (HSB).

HSB.OSC = 1 (Oscillator A selected)

•

OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped.

CKS = 1: OscA is selected for CPU.

HSB.OSC = 0 (Oscillator B selected)

•

OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped.

CKS = 0: OscB is selected for CPU.

Functional Modes

Normal Modes

•

CPU and Peripherals clock depend on the software selection using CKCON0,

CKCON1 and CKRL registers

•

CKS bit in CKSEL register selects either OscA or OscB

CKRL register determines the frequency of the OscA clock.

It is always possible to switch dynamically by software from OscA to OscB, and vice

versa by changing CKS bit.

17

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Idle Modes

•

IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL)

IDLE modes A and B depend on previous software sequence, prior to writing into

PCON.0 bit:

•

IDLE MODE A: OscA is running (OscAEn = 1) and selected (CKS = 1)

IDLE MODE B: OscB is running (OscBEn = 1) and selected (CKS = 0)

The unused oscillator OscA or OscB can be stopped by software by clearing

OscAEn or OscBEn respectively.

•

IDLE mode can be canceled either by Reset, or by activation of any enabled

interruption

•

In both cases, PCON.0 bit (IDL) is cleared by hardware

Exit from IDLE modes will leave Oscillators control bits (OscEnA, OscEnB, CKS)

unchanged.

Power Down Modes

•

POWER DOWN modes are achieved by using any instruction that writes into

PCON.1 bit (PD)

POWER DOWN modes A and B depend on previous software sequence, prior to

writing into PCON.1 bit:

•

Both OscA and OscB will be stopped.

POWER DOWN mode can be cancelled either by a hardware Reset, an external

interruption, or the keyboard interrupt.

•

By Reset signal: The CPU will restart according to OSC bit in Hardware Security Bit

(HSB) register.

By INT0 or INT1 interruption, if enabled: (standard behavioral), request on Pads

must be driven low enough to ensure correct restart of the oscillator which was

selected when entering in Power down.

•

By keyboard Interrupt if enabled: a hardware clear of the PCON.1 flag ensure the

restart of the oscillator which was selected when entering in Power down.

Table 20. Overview

PCON.1 PCON.0 OscBEn OscAEn CKS

Selected Mode

Comment

NORMAL MODE

A, OscB stopped

Default mode after power-up or

Warm Reset

0

1

0

X

0

1

0

1

0

X

1

0

X

1

0

NORMAL MODE

A, OscB running

Default mode after power-up or

Warm Reset + OscB running

NORMAL MODE

B, OscA stopped

0

OscB running and selected

NORMAL MODE

B, OscA running

OscB running and selected +

OscA running

0

OscA & OscB cannot be stopped

at the same time

X

INVALID

OscA must not be stopped, as

used for CPU and peripherals

OscB must not be stopped as

used for CPU and peripherals

The CPU is off, OscA supplies the

peripherals, OscB can be disabled

(OscBEn = 0)

0

1

X

1

IDLE MODE A

18

4289C–8051–11/05

Table 20. Overview (Continued)

PCON.1 PCON.0 OscBEn OscAEn CKS

Selected Mode

Comment

The CPU is off, OscB supplies the

peripherals, OscA can be disabled

(OscAEn = 0)

0

1

X

1

0

IDLE MODE B

POWER DOWN

MODE

The CPU and peripherals are off,

OscA and OscB are stopped

X

Design Considerations

Oscillators Control

•

PwdOscA and PwdOscB signals are generated in the Clock generator and used to

control the hard blocks of oscillators A and B.

•

PwdOscA =’1’ stops OscA

PwdOscB =’1’ stops OscB

The following tables summarize the Operating modes:

PCON.1

OscAEn

PwdOscA

Comments

0

1

0

OscA running

OscA stopped by

Power-down mode

1

0

X

0

1

OscA stopped by

clearing OscAEn

PCON.1

OscBEn

PwdOscB

Comments

0

1

0

OscB running

OscB stopped by

Power-down mode

1

0

X

0

1

OscB stopped by

clearing OscBEn

Prescaler Divider

•

A hardware RESET puts the prescaler divider in the following state:

CKRL = FFh: F_{CLK CPU}= F_{CLK PERIPH}= F_OSCA/2 (Standard C51 feature)

–

•

CKS signal selects OSCA or OSCB: F_{CLK OUT}= F_OSCAor F_OSCB

Any value between FFh down to 00h can be written by software into CKRL register

in order to divide frequency of the selected oscillator:

–

CKRL = 00h: minimum frequency

F

_{CLK CPU}= F_{CLK PERIPH}= F_OSCA/1020 (Standard Mode)

_{CLK CPU}= F_{CLK PERIPH}= F_OSCA/510 (X2 Mode)

–

CKRL = FFh: maximum frequency

F

_{CLK CPU}= F_{CLK PERIPH}= F_OSCA/2 (Standard Mode)

_{CLK CPU}= F_{CLK PERIPH}= F_OSCA(X2 Mode)

19

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

–

F_{CLK CPU}and F_{CLK PERIPH}, for CKRL≠0xFF

In X2 Mode:

F_OSCA

2 × (255 – CKRL)

----------------------------------------------

F_CPU= F_CLKPERIPH

=

In X1 Mode:

F_OSCA

----------------------------------------------

4 × (255 – CKRL)

F_CPU= F_CLKPERIPH

=

Timer 0: Clock Inputs

Figure 1. Timer 0: Clock Inputs

FCLK PERIPH

T0 pin

:6

0

1

Timer 0

0

Control

1

Sub Clock

(AT 8xC51Ix2 only)

C/T

TMOD

SCLKT0

OSCCON

Gate

INT0

TR0

Note:

The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.

SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)

SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use

as periodic interrupt for time clock.

20

4289C–8051–11/05

AT89C51ID2

Enhanced Features

In comparison to the original 80C52, the AT89C51ID2 implements some new features,

which are:

•

X2 option

Dual Data Pointer

Extended RAM

Programmable Counter Array (PCA)

Hardware Watchdog

SPI interface

4-level interrupt priority system

power-off flag

ONCE mode

ALE disabling

Enhanced features on the UART and the timer 2

X2 Feature

The AT89C51ID2 core needs only 6 clock periods per machine cycle. This feature

called ‘X2’ provides the following advantages:

•

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Save power consumption while keeping same CPU power (oscillator power saving).

Save power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.

•

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 3 shows the clock generation block diagram. X2 bit is validated on the rising edge

of the XTAL1÷2 to avoid glitches when switching from X2 to STD mode. Figure 4 shows

the switching mode waveforms.

Figure 3. Clock Generation Diagram

CKRL

F_OSC

XTAL1:2

2

XTAL1

F_{CLK CPU}

F_{CLK PERIPH}

0

1

8 bit Prescaler

FXTAL

X2

CKCON0

21

4289C–8051–11/05

Figure 4. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 bit

F_OSC

CPU clock

STD Mode

X2 Mode

STD Mode

The X2 bit in the CKCON0 register (see Table 21) allows a switch from 12 clock periods

per instruction to 6 clock periods and vice versa. At reset, the speed is set according to

X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the

X2 bit activates the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See

Table 21.) and SPIX2 bit in the CKCON1 register (see Table 22) allows a switch from

standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph-

eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2

mode.

22

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 21. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

6

5

4

3

2

1

0

TWIX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect)

Cleared to select 6 clock periods per peripheral clock cycle.

7

6

TWIX2

WDX2

Set to select 12 clock periods per peripheral clock cycle.

Watchdog Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

5

4

3

2

1

PCAX2

SIX2

Enhanced UART Clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer2 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

T2X2

T1X2

T0X2

Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer0 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

CPU Clock

Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and

all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and

to enable the individual peripherals’X2’ bits. Programmed by hardware after

Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is

cleared.

0

X2

Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)

Not bit addressable

23

4289C–8051–11/05

Table 22. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

SPIX2

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

-

Reserved

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

0

SPIX2

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = XXXX XXX0b

Not bit addressable

24

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Dual Data Pointer

Register DPTR

The additional data pointer can be used to speed up code execution and reduce code

size.

The dual DPTR structure is a way by which the chip will specify the address of an exter-

nal data memory location. There are two 16-bit DPTR registers that address the external

memory, and a single bit called DPS = AUXR1.0 (see Table 23) that allows the program

code to switch between them (Refer to Figure 5).

Figure 5. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

25

4289C–8051–11/05

Table 23. AUXR1 register

AUXR1- Auxiliary Register 1(0A2h)

7

-

6

-

5

4

-

3

2

1

-

0

ENBOOT

GF3

0

DPS

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Boot Flash

Cleared to disable boot ROM.

5

4

ENBOOT

-

Set to map the boot ROM between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

2

GF3

0

This bit is a general purpose user flag. *

Alwayscleared.

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

DPS

Reset Value: XXXX XX0X0b

Not bit addressable

Note:

*Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

26

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1

SFR. However, note that the INC instruction does not directly force the DPS bit to a par-

ticular state, but simply toggles it. In simple routines, such as the block move example,

only the fact that DPS is toggled in the proper sequence matters, not its actual value. In

other words, the block move routine works the same whether DPS is '0' or '1' on entry.

Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in

the opposite state.

27

4289C–8051–11/05

AT89C51ID2

Expanded RAM

(XRAM)

The AT89C51ID2 provides additional Bytes of random access memory (RAM) space for

increased data parameter handling and high level language usage.

AT89C51ID2 devices have expanded RAM in external data space configurable up to

1792bytes (see Table 24.).

The AT89C51ID2 has internal data memory that is mapped into four separate

segments.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly

addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable

only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly

addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and

with the EXTRAM bit cleared in the AUXR register (see Table 24).

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper

128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy

the same address space as the SFR. That means they have the same address, but are

physically separate from SFR space.

Figure 6. Internal and External Data Memory Address

0FFh to 6FFh

0FFh

0FFFFh

Upper

128 bytes

Internal

Special

Function

External

Data

Memory

Register

Ram

direct accesses

indirect accesses

80h

7Fh

80h

XRAM

Lower

128 bytes

Internal

Ram

direct or indirect

accesses

00FFh up to 06FFh

0000

00

When an instruction accesses an internal location above address 7Fh, the CPU knows

whether the access is to the upper 128 bytes of data RAM or to SFR space by the

addressing mode used in the instruction.

•

Instructions that use direct addressing access SFR space. For example: MOV

0A0H, # data, accesses the SFR at location 0A0h (which is P2).

•

Instructions that use indirect addressing access the Upper 128 bytes of data RAM.

For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte

at address 0A0h, rather than P2 (whose address is 0A0h).

•

The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared

and MOVX instructions. This part of memory which is physically located on-chip,

logically occupies the first bytes of external data memory. The bits XRS0 and XRS1

are used to hide a part of the available XRAM as explained in Table 24. This can be

28

4289C–8051–11/05

useful if external peripherals are mapped at addresses already used by the internal

XRAM.

•

With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An

access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For

example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,

accesses the XRAM at address 0A0H rather than external memory. An access to

external data memory locations higher than the accessible size of the XRAM will be

performed with the MOVX DPTR instructions in the same way as in the standard

80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and

read timing signals. Accesses to XRAM above 0FFH can only be done by the use of

DPTR.

•

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard

80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0

and any output port pins can be used to output higher order address bits. This is to

provide the external paging capability. MOVX @DPTR will generate a sixteen-bit

address. Port2 outputs the high-order eight address bits (the contents of DPH) while

Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and

MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7

(RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and

upper RAM) internal data memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses

are extended from 6 to 30 clock periods. This is useful to access external slow

peripherals.

29

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Registers

Table 24. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

-

5

4

3

2

1

0

M0

XRS2

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock

periods (default).

5

M0

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock

periods.

4

3

XRS2

XRS1

XRAM Size

XRS2XRS1XRS0XRAM size

0

1

0

0256bytes

0

1

1512 bytes

0768 bytes(default)

11024 bytes

01792 bytes

2

XRS0

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

EXTRAM Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

1

0

(HSB), default setting, XRAM selected.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AO

Reset Value = XX00 10’HSB. XRAM’0b

Not bit addressable

30

4289C–8051–11/05

AT89C51ID2

Reset

Introduction

The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and

Reset input.

Figure 7. Reset schematic

Power

Monitor

Hardware

Watchdog

Internal Reset

PCA

Watchdog

RST

Reset Input

The Reset input can be used to force a reset pulse longer than the internal reset con-

trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on

reset by simply connecting an external capacitor to V_CCas shown in Figure 8. Resistor

value and input characteristics are discussed in the Section “DC Characteristics” of the

AT89C51ID2 datasheet.

Figure 8. Reset Circuitry and Power-On Reset

VDD

To internal reset

RST

+

RST

VSS

a. RST input circuitry

b. Power-on Reset

31

4289C–8051–11/05

Reset Output

As detailed in Section “Hardware Watchdog Timer”, page 107, the WDT generates a 96-

clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of

the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ

resistor must be added as shown Figure 9.

Figure 9. Recommended Reset Output Schematic

VDD

+

RST

VDD

1K

AT89C51ID2

RST

To other

on-board

VSS

circuitry

32

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Power Monitor

The POR/PFD function monitors the internal power-supply of the CPU core memories

and the peripherals, and if needed, suspends their activity when the internal power sup-

ply falls below a safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when

AT89C51ID2 is powered up.

Description

In order to startup and maintain the microcontroller in correct operating mode, V_CChas

to be stabilized in the V_CCoperating range and the oscillator has to be stabilized with a

nominal amplitude compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation

and power going down. See Figure 10.

Figure 10. Power Monitor Block Diagram

VCC

CPU core

Regulated

Supply

Power On Reset

Power Fail Detect

Voltage Regulator

Memories

Peripherals

XTAL1

(1)

Internal Reset

RST pin

PCA

Watchdog

Hardware

Watchdog

Note:

1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock

period delay will extend the reset coming from the Power Fail Detect. If the power

falls below the Power Fail Detect threshold level, the Reset will be applied

immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the mem-

ories and the peripherals. Spikes on the external Vcc are smoothed by the voltage

regulator.

33

4289C–8051–11/05

The Power fail detect monitor the supply generated by the voltage regulator and gener-

ate a reset if this supply falls below a safety threshold as illustrated in the Figure 11

below.

Figure 11. Power Fail Detect

Vcc

t

Reset

Vcc

When the power is applied, the Power Monitor immediately asserts a reset. Once the

internal supply after the voltage regulator reach a safety level, the power monitor then

looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 lev-

els are above and below VIH and VIL. Further more. An internal counter will count 1024

clock periods before the reset is de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

34

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Timer 2

The Timer 2 in the AT89C51ID2 is the standard C52 Timer 2.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2 are cascaded. It is controlled by T2CON (Table 25) and T2MOD (Table 26)

registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F_OSC/12

(timer operation) or external pin T2 (counter operation) as the timer clock input. Setting

TR2 allows TL2 to increment by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These

modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).

Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Cap-

ture and Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

•

Auto-reload mode with up or down counter

Programmable clock-output

Auto-Reload Mode

The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-

matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to

the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as

an Up/down timer/counter as shown in Figure 12. In this mode the T2EX pin controls the

direction of count.

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of

the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit

resolution.

35

4289C–8051–11/05

Figure 12. Auto-Reload Mode Up/Down Counter (DCEN = 1)

F_{CLK PERIPH}

0

:6

1

T2

TR2

T2CON

C/T2

T2CON

T2EX:

(DOWN COUNTING RELOAD VALUE)

if DCEN=1, 1=UP

FFh

(8-bit)

FFh

(8-bit)

if DCEN=1, 0=DOWN

if DCEN = 0, up counting

T2CON

EXF2

TOGGLE

TIMER 2

INTERRUPT

TL2

(8-bit)

TH2

(8-bit)

TF2

T2CON

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

Programmable Clock-

Output

In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock gen-

erator (See Figure 13). The input clock increments TL2 at frequency F_{CLK PERIPH}/2.The

timer repeatedly counts to overflow from a loaded value. At overflow, the contents of

RCAP2H and RCAP2L registers are loaded into TH2 and TL2.In this mode, Timer 2

overflows do not generate interrupts. The formula gives the clock-out frequency as a

function of the system oscillator frequency and the value in the RCAP2H and RCAP2L

registers:

F

CLKPERIPH

--------------------------------------------------------------------------------------------

Clock–OutFrequency =

4 × (65536 – RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(F_{CLK PERIPH}/2¹⁶) to 4 MHz (F_{CLK PERIPH}/4). The generated clock signal is brought out to

T2 pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

•

Set T2OE bit in T2MOD register.

Clear C/T2 bit in T2CON register.

Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

•

Enter a 16-bit initial value in timer registers TH2/TL2.It can be the same as the

reload value or a different one depending on the application.

•

To start the timer, set TR2 run control bit in T2CON register.

It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

36

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Figure 13. Clock-Out Mode C/T2 = 0

:6

FCLK PERIPH

TR2

T2CON

TL2

(8-bit)

TH2

(8-bit)

OVER-

FLOW

RCAP2H

RCAP2L

(8-bit) (8-bit)

Toggle

T2

Q

D

T2OE

T2MOD

TIMER 2

INTERRUPT

T2EX

EXF2

T2CON

EXEN2

T2CON

37

4289C–8051–11/05

Registers

Table 25. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2

interrupt is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down

counter mode (DCEN = 1).

Receive Clock bit

5

4

RCLK

TCLK

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0

for clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

Timer 2 overflow.

Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin

if EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

38

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 26. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1

0

T2OE

DCEN

Cleared to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Cleared to disable Timer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

39

4289C–8051–11/05

AT89C51ID2

Programmable

Counter Array PCA

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. The PCA consists of a dedicated timer/counter which serves as the time base for

an array of five compare/capture modules. Its clock input can be programmed to count

any one of the following signals:

•

Peripheral clock frequency (F_{CLK PERIPH}) ÷ 6

Peripheral clock frequency (F_{CLK PERIPH}) ÷ 2

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

•

Rising and/or falling edge capture

Software timer

High-speed output

Pulse width modulator

Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog

Timer", page 51).

When the compare/capture modules are programmed in the capture mode, software

timer, or high speed output mode, an interrupt can be generated when the module exe-

cutes its function. All five modules plus the PCA timer overflow share one interrupt

vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O.

These pins are listed below. If the port is not used for the PCA, it can still be used for

standard I/O.

PCA component

16-bit Counter

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

External I/O Pin

P1.2 / ECI

P1.3 / CEX0

P1.4 / CEX1

P1.5 / CEX2

P1.6 / CEX3

The PCA timer is a common time base for all five modules (See Figure 14). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD register

(Table 27) and can be programmed to run at:

•

1/6 the peripheral clock frequency (F_{CLK PERIPH}

1/2 the peripheral clock frequency (F_{CLK PERIPH}

The Timer 0 overflow

)

The input on the ECI pin (P1.2)

40

4289C–8051–11/05

Figure 14. PCA Timer/Counter

To PCA

modules

Fclk periph /6

Fclk periph / 2

T0 OVF

overflow

It

CH

CL

16 bit up counter

P1.2

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

41

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 27. CMOD Register

CMOD - PCA Counter Mode Register (D9h)

7

6

5

-

4

-

3

-

2

1

0

CIDL

WDTE

CPS1

CPS0

ECF

Bit

Number

Mnemonic Description

Counter Idle Control

7

6

CIDL

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

Watchdog Timer Enable

WDTE

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

CPS1

PCA Count Pulse Select

CPS1

0

CPS0Selected PCA input

0 Internal clock fCLK PERIPH/6

0

1

1Internal clock fCLK PERIPH/2

1

0

CPS0

ECF

0Timer 0 Overflow

1 External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.

Set to enable CF bit in CCON to generate an interrupt.

Reset Value = 00XX X000b

Not bit addressable

The CMOD register includes three additional bits associated with the PCA (See

Figure 14 and Table 27).

•

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the watchdog function on module 4.

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in

the CCON SFR) to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer (CF) and each module (Refer to Table 28).

•

Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by

clearing this bit.

•

Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an

interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can

only be cleared by software.

42

4289C–8051–11/05

•

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,

etc.) and are set by hardware when either a match or a capture occurs. These flags

also can only be cleared by software.

Table 28. CCON Register

CCON - PCA Counter Control Register (D8h)

7

6

5

-

4

3

2

1

0

CF

CR

CCF4

CCF3

CCF2

CCF1

CCF0

Bit

Number

Mnemonic Description

PCA Counter Overflow flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in

CMOD is set. CF

7

CF

may be set by either hardware or software but can only be cleared by software.

PCA Counter Run control bit

6

5

4

CR

-

Must be cleared by software to turn the PCA counter off.

Set by software to turn the PCA counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA Module 4 interrupt flag

CCF4

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 3 interrupt flag

3

2

1

0

CCF3

CCF2

CCF1

CCF0

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 2 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 1 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 0 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

Reset Value = 00X0 0000b

Not bit addressable

The watchdog timer function is implemented in module 4 (See Figure 17).

The PCA interrupt system is shown in Figure 15.

43

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Figure 15. PCA Interrupt System

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

To Interrupt

priority decoder

Module 4

CMOD.0

IEN0.6

EC

IEN0.7

EA

CCAPMn.0

ECCFn

ECF

PCA Modules: each one of the five compare/capture modules has six possible func-

tions. It can perform:

•

16-bit Capture, positive-edge triggered

16-bit Capture, negative-edge triggered

16-bit Capture, both positive and negative-edge triggered

16-bit Software Timer

16-bit High Speed Output

8-bit Pulse Width Modulator

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These regis-

ters are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 29). The

registers contain the bits that control the mode that each module will operate in.

•

The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)

enables the CCF flag in the CCON SFR to generate an interrupt when a match or

compare occurs in the associated module.

•

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes the CEX output associated with the

module to toggle when there is a match between the PCA counter and the module's

capture/compare register.

•

The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON

register to be set when there is a match between the PCA counter and the module's

capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge

that a capture input will be active on. The CAPN bit enables the negative edge, and

the CAPP bit enables the positive edge. If both bits are set both edges will be

enabled and a capture will occur for either transition.

•

The last bit in the register ECOM (CCAPMn.6) when set enables the comparator

function.

44

4289C–8051–11/05

Table 29 shows the CCAPMn settings for the various PCA functions.

Table 29. CCAPMn Registers (n = 0-4)

CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)

CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)

CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)

CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)

CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Comparator

ECOMn Cleared to disable the comparator function.

Set to enable the comparator function.

Capture Positive

5

4

CAPPn

CAPNn

Cleared to disable positive edge capture.

Set to enable positive edge capture.

Capture Negative

Cleared to disable negative edge capture.

Set to enable negative edge capture.

Match

When MATn = 1, a match of the PCA counter with this module's

compare/capture register causes the

3

MATn

CCFn bit in CCON to be set, flagging an interrupt.

Toggle

When TOGn = 1, a match of the PCA counter with this module's

compare/capture register causes the

2

1

TOGn

CEXn pin to toggle.

Pulse Width Modulation Mode

PWMn

Cleared to disable the CEXn pin to be used as a pulse width modulated output.

Set to enable the CEXn pin to be used as a pulse width modulated output.

Enable CCF interrupt

Cleared to disable compare/capture flag CCFn in the CCON register to generate

an interrupt.

0

CCF0

Set to enable compare/capture flag CCFn in the CCON register to generate an

interrupt.

Reset Value = X000 0000b

Not bit addressable

45

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 30. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn MATn

TOGn

PWMm ECCFn Module Function

0

1

0

No Operation

16-bit capture by a positive-edge

trigger on CEXn

X

0

X

16-bit capture by a negative trigger

on CEXn

X

1

0

1

0

1

0

1

0

X

16-bit capture by a transition on

CEXn

16-bit Software Timer / Compare

mode.

1

0

1

0

1

0

1

0

X

0

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

There are two additional registers associated with each of the PCA modules. They are

CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a

capture occurs or a compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output (See Table 31 &

Table 32).

Table 31. CCAPnH Registers (n = 0-4)

CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)

CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)

CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)

CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)

CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)

7

6

5

4

3

2

1

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnH Value

7-0

-

Reset Value = 0000 0000b

Not bit addressable

46

4289C–8051–11/05

Table 32. CCAPnL Registers (n = 0-4)

CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)

CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)

CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)

CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)

CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnL Value

7-0

-

Reset Value = 0000 0000b

Not bit addressable

Table 33. CH Register

CH - PCA Counter Register High (0F9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA counter

CH Value

7-0

-

Reset Value = 0000 0000b

Not bit addressable

Table 34. CL Register

CL - PCA Counter Register Low (0E9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Counter

CL Value

7-0

-

Reset Value = 0000 0000b

Not bit addressable

47

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM

bits CAPN and CAPP for that module must be set. The external CEX input for the mod-

ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA

hardware loads the value of the PCA counter registers (CH and CL) into the module's

capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON

SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated

(Refer to Figure 16).

Figure 16. PCA Capture Mode

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAP nH

CCA PnL

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

16-bit Software Timer/

Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT

bits in the modules CCAPMn register. The PCA timer will be compared to the module's

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 17).

48

4289C–8051–11/05

Figure 17. PCA Compare Mode and PCA Watchdog Timer

CCON

0xD8

CF

CCF4 CCF3 CCF2 CCF1 CCF0

CR

Write to

CCAPnL Reset

PCA IT

Write t o

CCAPnH

CCAP nH

CCA PnL

Enable

1

0

Match

16 bit comparator

RESET *

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CA PPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module's capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR

must be set (See Figure 18).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

49

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Figure 18. PCA High Speed Output Mode

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

1

Enable

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could happen.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

Pulse Width Modulator

Mode

All of the PCA modules can be used as PWM outputs. Figure 19 shows the PWM func-

tion. The frequency of the output depends on the source for the PCA timer. All of the

modules will have the same frequency of output because they all share the PCA timer.

The duty cycle of each module is independently variable using the module's capture

register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-

ule's CCAPLn SFR the output will be low, when it is equal to or greater than the output

will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in

CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in

the module's CCAPMn register must be set to enable the PWM mode.

50

4289C–8051–11/05

Figure 19. PCA PWM Mode

CCAPnH

Overflow

CCAPnL

“0”

“1”

CEXn

Enable

8 bit comparator

CL

PCA counter/timer

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the

system without increasing chip count. Watchdog timers are useful for systems that are

susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only

PCA module that can be programmed as a watchdog. However, this module can still be

used for other modes if the watchdog is not needed. Figure 17 shows a diagram of how

the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just

like the other compare modes, this 16-bit value is compared to the PCA timer value. If a

match is allowed to occur, an internal reset will be generated. This will not cause the

RST pin to be driven high.

In order to hold off the reset, the user has three options:

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-

enable it.

The first two options are more reliable because the watchdog timer is never disabled as

in option #3. If the program counter ever goes astray, a match will eventually occur and

cause an internal reset. The second option is also not recommended if other PCA mod-

ules are being used. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most appli-

cations the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

51

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Serial I/O Port

The serial I/O port in the AT89C51ID2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

Automatic address recognition

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 20).

Figure 20. Framing Error Block Diagram

SM0/FE SM1

SM2 REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

PCON (87h)

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See Table 38.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 21. and Figure 22.).

Figure 21. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

52

4289C–8051–11/05

Figure 22. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, the user may enable the automatic address recognition feature in mode 1.In

this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when

the received command frame address matches the device’s address and is terminated

by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN

register is a mask byte that contains don’t-care bits (defined by zeros) to form the

device’s given address. The don’t-care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

53

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To commu-

nicate with slave A only, the master must send an address where bit 0 is clear (e. g.

1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both

set (e. g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e. g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e. g. :

SADDR0101 0110b

SADEN1111 1100b

Broadcast =SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR=1111 0011b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and

broadcast addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial

port will reply to any address, and so, that it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition.

54

4289C–8051–11/05

Registers

Table 35. SADEN Register

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 36. SADDR Register

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Baud Rate Selection for

UART for Mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via

the T2CON and BDRCON registers.

Figure 23. Baud Rate Selection

TIMER1

TIMER_BRG_RX

0

1

0

1

TIMER2

/ 16

Rx Clock

RCLK

RBCK

INT_BRG

TIMER1

TIMER2

TIMER_BRG_TX

0

1

0

1

/ 16

Tx Clock

TCLK

TBCK

INT_BRG

55

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 37. Baud Rate Selection Table UART

TCLK

RCLK

TBCK

RBCK

Clock Source

UART Rx

(T2CON)

(BDRCON)

UART Tx

0

1

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

Timer 1

Timer 2

Timer 1

Timer 2

INT_BRG

Timer 1

Timer 2

INT_BRG

Timer 2

INT_BRG

Internal Baud Rate Generator When the internal Baud Rate Generator is used, the Baud Rates are determined by the

(BRG)

BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)

in BDRCON register and the value of the SMOD1 bit in PCON register.

Figure 24. Internal Baud Rate

auto reload counter

/2

overflow

F_PER

0

1

/6

BRG

0

1

INT_BRG

BRL

SPD

SMOD1

BRR

•

The baud rate for UART is token by formula:

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

Baud_Rate =

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

BRL = 256 -

56

4289C–8051–11/05

Table 38. SCON Register

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

FE

SMOD0 must be set to enable access to the FE bit.

7

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SM1

SMOD0 must be cleared to enable access to the SM0 bit.

Serial port Mode bit 1

SM0 SM1

Mode

Baud Rate

0

1

0

1

0

1

Shift Register F_XTAL/12 (or F_XTAL/6 in mode X2)

6

5

8-bit UART

9-bit UART

Variable

_XTAL/64 or F_XTAL/32

Variable

F

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

SM2

Set to enable multiprocessor communication feature in mode 2 and 3, and

eventually mode 1.This bit should be cleared in mode 0.

Reception Enable bit

4

3

REN

TB8

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not

used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning

of the stop bit in the other modes.

1

0

TI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 21.

and Figure 22. in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

57

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 39. Example of Computed Value When X2=1, SMOD1=1, SPD=1

Baud Rates

F_OSC= 16. 384 MHz

F_OSC= 24MHz

Error (%)

BRL

Error (%)

1.23

BRL

243

230

217

204

178

100

-

115200

57600

38400

28800

19200

9600

247

238

229

220

203

149

43

0.16

-

1.23

0.63

0.31

4800

1.23

Table 40. Example of Computed Value When X2=0, SMOD1=0, SPD=0

Baud Rates

F_OSC= 16. 384 MHz

F_OSC= 24MHz

BRL

Error (%)

1.23

BRL

243

230

202

152

Error (%)

0.16

4800

2400

1200

600

247

238

220

185

1.23

0.16

1.23

3.55

0.16

The baud rate generator can be used for mode 1 or 3 (refer to Figure 23.), but also for

mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 47.)

UART Registers

Table 41. SADEN Register

SADEN - Slave Address Mask Register for UART (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Table 42. SADDR Register

SADDR - Slave Address Register for UART (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

58

4289C–8051–11/05

Table 43. SBUF Register

SBUF - Serial Buffer Register for UART (99h)

7

6

5

4

3

2

1

0

Reset Value = XXXX XXXXb

Table 44. BRL Register

BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

59

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 45. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic

Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2

interrupt is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down

counter mode (DCEN = 1)

Receive Clock bit for UART

5

4

RCLK

TCLK

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit for UART

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be

0 for clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

timer 2 overflow.

Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin

if EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

60

4289C–8051–11/05

Table 46. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic

Description

Serial port Mode bit 1 for UART

7

6

5

SMOD1

SMOD0

-

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0 for UART

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

4

POF

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset

doesn’t affect the value of this bit.

61

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 47. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Mnemonic Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

4

3

2

1

BRR

TBCK

RBCK

SPD

Cleared to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

Cleared to select F_OSC/12 as the Baud Rate Generator (F_{CLK PERIPH}/6 in X2

mode).

0

SRC

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset Value = XXX0 0000b

Not bit addressablef

62

4289C–8051–11/05

AT89C51ID2

Interrupt System

The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt,

Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure

25.

Figure 25. Interrupt Control System

High priority

interrupt

IPH, IPL

3

0

INT0

IE0

IE1

3

0

3

0

3

TF0

Interrupt

polling

INT1

sequence, decreasing from

high to low priority

TF1

0

3

PCA IT

0

3

0

RI

TI

3

TF2

EXF2

0

3

KBD IT

TWI IT

SPI IT

0

3

0

3

0

Low priority

interrupt

Individual Enable

Global Disable

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (Table 52 and Table 50). This register also

contains a global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority lev-

els by setting or clearing a bit in the Interrupt Priority register (Table 53) and in the

Interrupt Priority High register (Table 51 and Table 52) shows the bit values and priority

levels associated with each combination.

63

4289C–8051–11/05

Registers

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located

at address 0043H and Keyboard interrupt vector is located at address 004BH. All other

vectors addresses are the same as standard C52 devices.

Table 48. Priority Level Bit Values

IPH. x

IPL. x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

64

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AT89C51ID2

Table 49. IENO Register

IEN0 - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic Description

Enable All interrupt bit

7

6

EA

EC

Cleared to disable all interrupts.

Set to enable all interrupts.

PCA interrupt enable bit

Cleared to disable.

Set to enable.

Timer 2 overflow interrupt Enable bit

Cleared to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

5

4

3

2

1

0

ET2

ES

Serial port Enable bit

Cleared to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Cleared to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Cleared to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Cleared to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Cleared to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

Bit addressable

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4289C–8051–11/05

Table 50. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7

-

6

5

4

3

2

1

0

PPCL

PT2L

PSL

PT1L

PX1L

PT0L

PX0L

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority bit

Refer to PPCH for priority level.

PPCL

PT2L

PSL

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

PT1L

PX1L

PT0L

PX0L

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = X000 0000b

Bit addressable

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AT89C51ID2

Table 51. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7

6

5

4

3

2

1

0

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt Priority high bit.

PPCHPPCLPriority Level

0

1

0Lowest

1

0

6

PPCH

PT2H

PSH

1Highest

Timer 2 overflow interrupt Priority High bit

PT2HPT2LPriority Level

0

1

0Lowest

1

0

5

4

3

2

1

0

1Highest

Serial port Priority High bit

PSH PSLPriority Level

0

1

0Lowest

1

0

1Highest

Timer 1 overflow interrupt Priority High bit

PT1HPT1L Priority Level

0

1

0 Lowest

1

0

PT1H

PX1H

PT0H

PX0H

1Highest

External interrupt 1 Priority High bit

PX1HPX1LPriority Level

0

1

0Lowest

1

0

1Highest

Timer 0 overflow interrupt Priority High bit

PT0HPT0LPriority Level

0

1

0Lowest

1

0

1Highest

External interrupt 0 Priority High bit

PX0H PX0LPriority Level

0

1

0Lowest

1

0

1Highest

Reset Value = X000 0000b

Not bit addressable

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Table 52. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)

7

6

5

4

3

2

1

0

-

ESPI

ETWI

EKBD

Bit

Number

Mnemonic Description

7

6

5

4

3

-

Reserved

SPI interrupt Enable bit

Cleared to disable SPI interrupt.

2

1

0

ESPI

ETWI

EKBD

Set to enable SPI interrupt.

TWI interrupt Enable bit

Cleared to disable TWI interrupt.

Set to enable TWI interrupt.

Keyboard interrupt Enable bit

Cleared to disable keyboard interrupt.

Set to enable keyboard interrupt.

Reset Value = XXXX X000b

Bit addressable

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AT89C51ID2

Table 53. IPL1 Register

IPL1 - Interrupt Priority Register (B2h)

Table 54.

7

6

-

5

-

4

-

3

-

2

1

0

-

SPIL

TWIL

KBDL

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

SPI interrupt Priority bit

Refer to SPIH for priority level.

SPIL

TWIL

KBDL

TWI interrupt Priority bit

Refer to TWIH for priority level.

Keyboard interrupt Priority bit

Refer to KBDH for priority level.

Reset Value = XXXX X000b

Bit addressable

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Table 55. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)

7

-

6

-

5

-

4

-

3

-

2

1

0

SPIH

TWIH

KBDH

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI interrupt Priority High bit

SPIH

SPILPriority Level

0

1

0Lowest

1

0

2

1

0

SPIH

TWIH

KBDH

1Highest

TWI interrupt Priority High bit

TWIH

0

1

TWILPriority Level

0Lowest

1

0

1Highest

Keyboard interrupt Priority High bit

KB DH KBDLPriority Level

0

1

0 Lowest

1

0

1Highest

Reset Value = XXXX X000b

Not bit addressable

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AT89C51ID2

Interrupt Sources and

Vector Addresses

Table 56. Interrupt Sources and Vector Addresses

Vector

Interrupt

Request

Number

Polling Priority

Interrupt Source

Reset

Address

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

6

7

5

8

9

0000h

0003h

000Bh

0013h

001Bh

0023h

002Bh

INT0

IE0

TF0

Timer 0

INT1

IE1

Timer 1

UART

IF1

RI+TI

TF2+EXF2

Timer 2

PCA

CF + CCFn (n = 0-4)

KBDIT

0033h

003Bh

0043h

004Bh

Keyboard

TWI

TWIIT

SPI

SPIIT

71

4289C–8051–11/05

AT89C51ID2

Power Management

Introduction

Two power reduction modes are implemented in the AT89C51ID2. The Idle mode and

the Power-Down mode. These modes are detailed in the following sections. In addition

to these power reduction modes, the clocks of the core and peripherals can be dynami-

cally divided by 2 using the X2 mode detailed in Section “Enhanced Features”, page 21.

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

preserved, i.e., the program counter and program status word register retain their data

for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The

status of the Port pins during Idle mode is detailed in Table 57.

Entering Idle Mode

Exiting Idle Mode

To enter Idle mode, set the IDL bit in PCON register (see Table 58). The AT89C51ID2

enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that

sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT89C51ID2 enters Power-Down mode.

Then it does not go in Idle mode when exiting Power-Down mode.

There are two ways to exit Idle mode:

1. Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

2. Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the AT89C51ID2 and vectors the CPU to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-Down Mode

The Power-Down mode places the AT89C51ID2 in a very low power state. Power-Down

mode stops the oscillator, freezes all clock at known states. The CPU status prior to

entering Power-Down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-Down mode. In addition, the SFR

72

4289C–8051–11/05

and RAM contents are preserved. The status of the Port pins during Power-Down mode

is detailed in Table 57.

Note:

VCC may be reduced to as low as V_RETduring Power-Down mode to further reduce

power dissipation. Take care, however, that VDD is not reduced until Power-Down mode

is invoked.

Entering Power-Down Mode

Exiting Power-Down Mode

To enter Power-Down mode, set PD bit in PCON register. The AT89C51ID2 enters the

Power-Down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

Note:

If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until

VCC is restored to the normal operating level.

There are two ways to exit the Power-Down mode:

1. Generate an enabled external interrupt.

–

The AT89C51ID2 provides capability to exit from Power-Down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# input,

execution resumes when the input is released (see Figure 26). Execution

resumes with the interrupt service routine. Upon completion of the interrupt

service routine, program execution resumes with the instruction immediately

following the instruction that activated Power-Down mode.

Note:

The external interrupt used to exit Power-Down mode must be configured as level sensi-

tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the

duration of the interrupt must be long enough to allow the oscillator to stabilize. The exe-

cution will only resume when the interrupt is deasserted.

Note:

Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM

content.

Figure 26. Power-Down Exit Waveform Using INT1:0#

INT1:0#

OSC

Active phase

Power-down phase

Oscillator restart phase

Active phase

2. Generate a reset.

–

A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-Down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the AT89C51ID2 and vectors

the CPU to address 0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

73

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

pins, the instruction immediately following the instruction that activated the Power-Down

mode should not write to a Port pin or to the external RAM.

Note:

Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

Table 57. Pin Conditions in Special Operating Modes

Mode

Port 0

Port 1

Port 2

Port 3

Port 4

ALE

PSEN#

Reset

Floating

High

Idle

(internal

code)

Data

Floating

Data

High

Low

High

Low

Idle

(external

code)

Power-

Down(inter

nal code)

Power-

Down

(external

code)

Floating

Data

Low

74

4289C–8051–11/05

Registers

Table 58. PCON Register

PCON (S87:h) Power configuration Register

7

-

6

-

5

-

4

3

2

1

0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Reserved

7-5

4

-

The value read from these bits is indeterminate. Do not set these bits.

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

POF

General Purpose flag 1

3

2

GF1

GF0

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

General Purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

1

0

PD

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value= XXXX 0000b

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AT89C51ID2

Keyboard Interface

The AT89C51ID2 implements a keyboard interface allowing the connection of a

8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on

both high or low level. These inputs are available as alternate function of P1 and allow to

exit from idle and power down modes.

The keyboard interface interfaces with the C51 core through 3 special function registers:

KBLS, the Keyboard Level Selection register (Table 61), KBE, The Keyboard interrupt

Enable register (Table 60), and KBF, the Keyboard Flag register (Table 59).

Interrupt

The keyboard inputs are considered as 8 independent interrupt sources sharing the

same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or dis-

able of the keyboard interrupt (see Figure 27). As detailed in Figure 28 each keyboard

input has the capability to detect a programmable level according to KBLS. x bit value.

Level detection is then reported in interrupt flags KBF. x that can be masked by software

using KBE. x bits.

This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage

of P1 inputs for other purpose.

Figure 27. Keyboard Interface Block Diagram

Vcc

0

P1:x

KBF. x

1

KBE. x

Internal Pullup

KBLS. x

Figure 28. Keyboard Input Circuitry

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Input Circuitry

KBDIT

Keyboard Interface

Interrupt Request

KBD

IE1

Power Reduction Mode

P1 inputs allow exit from idle and power down modes as detailed in Section “Power

Management”, page 72.

76

4289C–8051–11/05

Registers

Table 59. KBF Register

KBF-Keyboard Flag Register (9Eh)

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Bit

Number

Mnemonic Description

Keyboard line 7 flag

Set by hardware when the Port line 7 detects a programmed level. It generates a

Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.

Must be cleared by software.

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Keyboard line 6 flag

Set by hardware when the Port line 6 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 5 flag

Set by hardware when the Port line 5 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 4 flag

Set by hardware when the Port line 4 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 3 flag

Set by hardware when the Port line 3 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 2 flag

Set by hardware when the Port line 2 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 1 flag

Set by hardware when the Port line 1 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 0 flag

Set by hardware when the Port line 0 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set.

Must be cleared by software.

Reset Value= 0000 0000b

This register is read only access, all flags are automatically cleared by reading the

register.

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Table 60. KBE Register

KBE-Keyboard Input Enable Register (9Dh)

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Bit

Number

Mnemonic Description

Keyboard line 7 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 7 bit in KBF register to generate an interrupt request.

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Keyboard line 6 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 6 bit in KBF register to generate an interrupt request.

Keyboard line 5 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 5 bit in KBF register to generate an interrupt request.

Keyboard line 4 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 4 bit in KBF register to generate an interrupt request.

Keyboard line 3 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 3 bit in KBF register to generate an interrupt request.

Keyboard line 2 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 2 bit in KBF register to generate an interrupt request.

Keyboard line 1 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 1 bit in KBF register to generate an interrupt request.

Keyboard line 0 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF. 0 bit in KBF register to generate an interrupt request.

Reset Value= 0000 0000b

78

4289C–8051–11/05

Table 61. KBLS Register

KBLS-Keyboard Level Selector Register (9Ch)

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Bit

Number

Mnemonic Description

Keyboard line 7 Level Selection bit

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Cleared to enable a low level detection on Port line 7.

Set to enable a high level detection on Port line 7.

Keyboard line 6 Level Selection bit

Cleared to enable a low level detection on Port line 6.

Set to enable a high level detection on Port line 6.

Keyboard line 5 Level Selection bit

Cleared to enable a low level detection on Port line 5.

Set to enable a high level detection on Port line 5.

Keyboard line 4 Level Selection bit

Cleared to enable a low level detection on Port line 4.

Set to enable a high level detection on Port line 4.

Keyboard line 3 Level Selection bit

Cleared to enable a low level detection on Port line 3.

Set to enable a high level detection on Port line 3.

Keyboard line 2 Level Selection bit

Cleared to enable a low level detection on Port line 2.

Set to enable a high level detection on Port line 2.

Keyboard line 1 Level Selection bit

Cleared to enable a low level detection on Port line 1.

Set to enable a high level detection on Port line 1.

Keyboard line 0 Level Selection bit

Cleared to enable a low level detection on Port line 0.

Set to enable a high level detection on Port line 0.

Reset Value= 0000 0000b

79

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AT89C51ID2

2-wire Interface (TWI) This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire

serial communication standard. It is designed primarily for simple but efficient integrated

circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA

(Serial Data) that carry information between the ICs connected to them. The serial data

transfer is limited to 400 Kbit/s in standard mode. Various communication configuration

can be designed using this bus. Figure 29 shows a typical 2-wire bus configuration. All

the devices connected to the bus can be master and slave.

Figure 29. 2-wire Bus Configuration

...

device1

device2 device3

deviceN

SCL

SDA

80

4289C–8051–11/05

Figure 30. Block Diagram

8

SSADR

Address Register

Comparator

Input

Filter

SDA

PI2.1

Output

Stage

ACK

SSDAT

Shift Register

8

Arbitration &

Sink Logic

Input

Filter

Timing &

Control

logic

F_{CLK PERIPH}/4

SCL

PI2.0

Interrupt

Output

Stage

Serial clock

generator

Timer 1

overflow

SSCON

Control Register

7

Status

Decoder

Status

Bits

SSCS

Status Register

8

81

AT89C51ID2

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AT89C51ID2

Description

The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis-

ters: the Synchronous Serial Control register (SSCON; Table 71), the Synchronous

Serial Data register (SSDAT; Table 72), the Synchronous Serial Control and Status reg-

ister (SSCS; Table 73) and the Synchronous Serial Address register (SSADR Table 76).

SSCON is used to enable the TWI interface, to program the bit rate (see Table 64), to

enable slave modes, to acknowledge or not a received data, to send a START or a

STOP condition on the 2-wire bus, and to acknowledge a serial interrupt. A hardware

reset disables the TWI module.

SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire

bus. The three least significant bits are always zero. The five most significant bits con-

tains the status code. There are 26 possible status codes. When SSCS contains F8h,

no relevant state information is available and no serial interrupt is requested. A valid sta-

tus code is available in SSCS one machine cycle after SI is set by hardware and is still

present one machine cycle after SI has been reset by software. to Table 70. give the

status for the master modes and miscellaneous states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been

received. It is addressable while it is not in process of shifting a byte. This occurs when

2-wire logic is in a defined state and the serial interrupt flag is set. Data in SSDAT

remains stable as long as SI is set. While data is being shifted out, data on the bus is

simultaneously shifted in; SSDAT always contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the

TWI module will respond when programmed as a slave transmitter or receiver. The LSB

is used to enable general call address (00h) recognition.

Figure 31 shows how a data transfer is accomplished on the 2-wire bus.

Figure 31. Complete Data Transfer on 2-wire Bus

MSB

SDA

SCL

acknowledgement

signal from receiver

acknowledgement

signal from receiver

1

2

3-8

9

7

1

2

8

9

S

ACK

P

clock line held low

while interrupts are serviced

start

condition

stop

condition

The four operating modes are:

•

Master Transmitter

Master Receiver

Slave transmitter

Slave receiver

Data transfer in each mode of operation is shown in Table to Table 70 and Figure 32. to

Figure 35.. These figures contain the following abbreviations:

S : START condition

R : Read bit (high level at SDA)

82

4289C–8051–11/05

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P : STOP condition

In Figure 32 to Figure 35, circles are used to indicate when the serial interrupt flag is set.

The numbers in the circles show the status code held in SSCS. At these points, a ser-

vice routine must be executed to continue or complete the serial transfer. These service

routines are not critical since the serial transfer is suspended until the serial interrupt

flag is cleared by software.

When the serial interrupt routine is entered, the status code in SSCS is used to branch

to the appropriate service routine. For each status code, the required software action

and details of the following serial transfer are given in Table to Table 70.

Master Transmitter Mode

In the master transmitter mode, a number of data bytes are transmitted to a slave

receiver (Figure 32). Before the master transmitter mode can be entered, SSCON must

be initialised as follows:

Table 62. SSCON Initialization

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

bit rate

1

0

X

bit rate

CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not

used. SSIE must be set to enable TWI. STA, STO and SI must be cleared.

The master transmitter mode may now be entered by setting the STA bit. The 2-wire

logic will now test the 2-wire bus and generate a START condition as soon as the bus

becomes free. When a START condition is transmitted, the serial interrupt flag (SI bit in

SSCON) is set, and the status code in SSCS will be 08h. This status must be used to

vector to an interrupt routine that loads SSDAT with the slave address and the data

direction bit (SLA+W).

When the slave address and the direction bit have been transmitted and an acknowl-

edgement bit has been received, SI is set again and a number of status code in SSCS

are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if

the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each

of these status code is detailed in Table . This scheme is repeated until a STOP condi-

tion is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to

Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may

switch to the master receiver mode by loading SSDAT with SLA+R.

Master Receiver Mode

In the master receiver mode, a number of data bytes are received from a slave transmit-

ter (Figure 33). The transfer is initialized as in the master transmitter mode. When the

START condition has been transmitted, the interrupt routine must load SSDAT with the

7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must

then be cleared before the serial transfer can continue.

83

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AT89C51ID2

When the slave address and the direction bit have been transmitted and an acknowl-

edgement bit has been received, the serial interrupt flag is set again and a number of

status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and

also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate

action to be taken for each of these status code is detailed in Table . This scheme is

repeated until a STOP condition is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to

Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may

switch to the master transmitter mode by loading SSDAT with SLA+W.

Slave Receiver Mode

In the slave receiver mode, a number of data bytes are received from a master transmit-

ter (Figure 34). To initiate the slave receiver mode, SSADR and SSCON must be loaded

as follows:

Table 63. SSADR: Slave Receiver Mode Initialization

A6

A5

A4

A3

A2

A1

A0

GC

own slave address

The upper 7 bits are the address to which the TWI module will respond when addressed

by a master. If the LSB (GC) is set the TWI module will respond to the general call

address (00h); otherwise it ignores the general call address.

Table 64. SSCON: Slave Receiver Mode Initialization

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

bit rate

1

0

1

bit rate

CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the

TWI. The AA bit must be set to enable the own slave address or the general call address

acknowledgement. STA, STO and SI must be cleared.

When SSADR and SSCON have been initialised, the TWI module waits until it is

addressed by its own slave address followed by the data direction bit which must be at

logic 0 (W) for the TWI to operate in the slave receiver mode. After its own slave

address and the W bit have been received, the serial interrupt flag is set and a valid sta-

tus code can be read from SSCS. This status code is used to vector to an interrupt

service routine.The appropriate action to be taken for each of these status code is

detailed in Table . The slave receiver mode may also be entered if arbitration is lost

while TWI is in the master mode (states 68h and 78h).

If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1)

to SDA after the next received data byte. While AA is reset, the TWI module does not

respond to its own slave address. However, the 2-wire bus is still monitored and

address recognition may be resume at any time by setting AA. This means that the AA

bit may be used to temporarily isolate the module from the 2-wire bus.

Slave Transmitter Mode

In the slave transmitter mode, a number of data bytes are transmitted to a master

receiver (Figure 35). Data transfer is initialized as in the slave receiver mode. When

SSADR and SSCON have been initialized, the TWI module waits until it is addressed by

84

4289C–8051–11/05

its own slave address followed by the data direction bit which must be at logic 1 (R) for

TWI to operate in the slave transmitter mode. After its own slave address and the R bit

have been received, the serial interrupt flag is set and a valid status code can be read

from SSCS. This status code is used to vector to an interrupt service routine. The appro-

priate action to be taken for each of these status code is detailed in Table . The slave

transmitter mode may also be entered if arbitration is lost while the TWI module is in the

master mode.

If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the

transfer and enter state C0h or C8h. the TWI module is switched to the not addressed

slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-

ter receiver receives all 1’s as serial data. While AA is reset, the TWI module does not

respond to its own slave address. However, the 2-wire bus is still monitored and

address recognition may be resume at any time by setting AA. This means that the AA

bit may be used to temporarily isolate the TWI module from the 2-wire bus.

Miscellaneous States

There are two SSCS codes that do not correspond to a define TWI hardware state

(Table 70 ). These codes are discuss hereafter.

Status F8h indicates that no relevant information is available because the serial interrupt

flag is not set yet. This occurs between other states and when the TWI module is not

involved in a serial transfer.

Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus

error is caused when a START or a STOP condition occurs at an illegal position in the

format frame. Examples of such illegal positions happen during the serial transfer of an

address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To

recover from a bus error, the STO flag must be set and SI must be cleared. This causes

the TWI module to enter the not addressed slave mode and to clear the STO flag (no

other bits in SSCON are affected). The SDA and SCL lines are released and no STOP

condition is transmitted.

Notes

the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock

line) and SDA (serial data line). To avoid low level asserting on these lines when the

TWI module is enabled, the output latches of SDA and SLC must be set to logic 1.

Table 65. Bit Frequency Configuration

Bit Frequency ( kHz)

CR2

0

CR1

0

CR0

0

F

_OSCA= 12 MHz

F_OSCA= 16 MHz

F_OSCAdivided by

47

53.5

62.5

75

62.5

71.5

83

256

224

0

1

0

1

0

192

0

1

100

-

160

1

0

-

Unused

120

1

0

1

100

200

133.3

266.6

1

0

60

96 · (256 - reload valueTimer 1)

(reload value range: 0-254 in mode 2)

1

0.5 <. < 62.5

0.67 <. < 83

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Figure 32. Format and State in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

Data

A

P

transmission

to a slave

receiver

28h

08h

18h

Next transfer

started with a

repeated start

condition

S

SLA

W

R

10h

Not acknowledge

received after the

slave address

A

P

20h

MR

Not acknowledge

received after a data

byte

A

P

30h

Other master

continues

Other master

continues

Arbitration lost in slave

address or data byte

A or A

38h

A or A

38h

A

Arbitration lost and

addressed as slave

Other master

continues

68h 78h B0h

To corresponding

states in slave mode

Any number of data bytes and their associated

acknowledge bits

From master to slave

From slave to master

Data

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

n

86

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Table 66. Status in Master Transmitter Mode

Application software response

To SSCON

SSSTO SSI

Status Status of the Two-

Code wire Bus and Two-

SSSTA wire Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by Two-wire Hardware

A START condition has

08h

Write SLA+W

X

0

X

SLA+W will be transmitted.

been transmitted

Write SLA+W

Write SLA+R

X

0

X

A repeated START

10h

18h

condition has been

transmitted

SLA+R will be transmitted.

Logic will switch to master receiver mode

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

SLA+W has been

transmitted; ACK has

been received

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

SLA+W has been

STOP condition will be transmitted and SSSTO flag

will be reset.

20h

28h

transmitted; NOT ACK

has been received

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

Data byte has been

transmitted; ACK has

been received

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Data byte will be transmitted.

Write data byte

0

1

0

1

0

X

Repeated START will be transmitted.

No SSDAT action

Data byte has been

transmitted; NOT ACK

has been received

STOP condition will be transmitted and SSSTO flag

will be reset.

30h

38h

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

1

0

X

Two-wire bus will be released and not addressed

slave mode will be entered.

No SSDAT action

0

1

0

X

Arbitration lost in

SLA+W or data bytes

A START condition will be transmitted when the bus

becomes free.

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Figure 33. Format and State in the Master Receiver Mode

MR

Successfull

transmission

to a slave

receiver

Data

A

P

S

SLA

R

A

Data

50h

58h

08h

40h

Next transfer

started with a

repeated start

condition

S

SLA

R

10h

Not acknowledge

received after the

slave address

W

A

P

MT

48h

Arbitration lost in slave

address or acknowledge bit

Other master

continues

Other master

continues

A

A or A

38h

A

38h

Other master

continues

Arbitration lost and

addressed as slave

To corresponding

states in slave mode

68h 78h B0h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

n

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

88

4289C–8051–11/05

Table 67. Status in Master Receiver Mode

Application software response

To SSCON

SSSTO SSI

Status Status of the Two-

Code wire Bus and Two-

SSSTA wire Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by Two-wire Hardware

A START condition has

08h

Write SLA+R

X

0

X

SLA+R will be transmitted.

been transmitted

Write SLA+R

Write SLA+W

X

0

X

A repeated START

10h

condition has been

transmitted

SLA+W will be transmitted.

Logic will switch to master transmitter mode.

Two-wire bus will be released and not addressed

slave mode will be entered.

No SSDAT action

0

1

0

X

0

1

Arbitration lost in

SLA+R or NOT ACK

bit

38h

40h

A START condition will be transmitted when the bus

becomes free.

Data byte will be received and NOT ACK will be

returned.

SLA+R has been

transmitted; ACK has

been received

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

No SSDAT action

1

0

1

0

X

SLA+R has been

STOP condition will be transmitted and SSSTO flag

will be reset.

48h

50h

58h

transmitted; NOT ACK

has been received

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

No SSDAT action

Read data byte

1

0

1

0

X

0

1

Data byte will be received and NOT ACK will be

returned.

Data byte has been

received; ACK has

been returned

Data byte will be received and ACK will be returned.

Repeated START will be transmitted.

Read data byte

1

0

1

0

X

Data byte has been

received; NOT ACK

has been returned

STOP condition will be transmitted and SSSTO flag

will be reset.

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

Read data byte

1

0

X

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Figure 34. Format and State in the Slave Receiver Mode

Reception of the own

P or S

A

Data

A

S

SLA

W

A

slave address and one or

more data bytes. All are

acknowledged.

60h

80h

A0h

80h

A

Last data byte received

is not acknowledged.

P or S

88h

Arbitration lost as master

and addressed as slave

A

68h

Reception of the general call

address and one or more data

bytes.

P or S

Data

A

General Call

A

90h

A

70h

90h

A0h

Last data byte received is

not acknowledged.

P or S

98h

A

Arbitration lost as master and

addressed as slave by general call

78h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

n

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

90

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Table 68. Status in Slave Receiver Mode

Application Software Response

To/from SSDAT To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

X

STO

SI

0

AA Next Action Taken By 2-wire Software

Data byte will be received and NOT ACK will be

returned

No SSDAT action or

No SSDAT action

0

Own SLA+W has been

received; ACK has been

returned

60h

68h

70h

78h

80h

Data byte will be received and ACK will be

returned

X

0

1

Data byte will be received and NOT ACK will be

returned

Arbitration lost in SLA+R/W as

master; own SLA+W has been

received; ACK has been

returned

No SSDAT action or

No SSDAT action

X

0

Data byte will be received and ACK will be

returned

1

Data byte will be received and NOT ACK will be

returned

No SSDAT action or

No SSDAT action

X

0

General call address has been

received; ACK has been

returned

Data byte will be received and ACK will be

returned

1

Data byte will be received and NOT ACK will be

returned

Arbitration lost in SLA+R/W as

master; general call address

has been received; ACK has

been returned

No SSDAT action or

No SSDAT action

X

0

Data byte will be received and ACK will be

returned

1

Data byte will be received and NOT ACK will be

returned

Previously addressed with

own SLA+W; data has been

received; ACK has been

returned

No SSDAT action or

No SSDAT action

X

0

Data byte will be received and ACK will be

returned

1

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Read data byte or

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

1

Previously addressed with

own SLA+W; data has been

received; NOT ACK has been

returned

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

becomes free

88h

Read data byte or

Read data byte

1

0

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be

1

transmitted when the bus becomes free

Data byte will be received and NOT ACK will be

returned

Previously addressed with

general call; data has been

received; ACK has been

returned

X

0

Read data byte or

Read data byte

90h

Data byte will be received and ACK will be

returned

1

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Table 68. Status in Slave Receiver Mode (Continued)

Application Software Response

To/from SSDAT

To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

STO

SI

AA Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

Read data byte or

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

becomes free

98h

Read data byte or

Read data byte

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be

transmitted when the bus becomes free

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

A STOP condition or repeated

START condition has been

received while still addressed

as slave

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

becomes free

A0h

No SSDAT action or

No SSDAT action

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be

transmitted when the bus becomes free

92

4289C–8051–11/05

Figure 35. Format and State in the Slave Transmitter Mode

Reception of the

own slave address

and one or more

data bytes

A

P or S

Data

A

S

SLA

R

A

A8h

A

B8h

C0h

Arbitration lost as master

and addressed as slave

B0h

Last data byte transmitted.

Switched to not addressed

slave (AA=0)

All 1’s

P or S

A

C8h

From master to slave

From slave to master

Any number of data bytes and their associated

acknowledge bits

Data

A

This number (contained in SSCS) corresponds

to a defined state of the 2-wire bus

n

Table 69. Status in Slave Transmitter Mode

Application Software Response

To/from SSDAT To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

X

STO

SI

0

AA Next Action Taken By 2-wire Software

Last data byte will be transmitted and NOT ACK

will be received

Load data byte or

Load data byte

0

Own SLA+R has been

received; ACK has been

returned

A8h

B0h

B8h

Data byte will be transmitted and ACK will be

received

X

0

1

Last data byte will be transmitted and NOT ACK

will be received

Arbitration lost in SLA+R/W as

master; own SLA+R has been

received; ACK has been

returned

Load data byte or

Load data byte

X

0

Data byte will be transmitted and ACK will be

received

1

Last data byte will be transmitted and NOT ACK

will be received

Load data byte or

Load data byte

X

0

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Data byte will be transmitted and ACK will be

received

1

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Table 69. Status in Slave Transmitter Mode (Continued)

Application Software Response

To/from SSDAT

To SSCON

Status

Code

(SSCS)

Status of the 2-wire bus and

2-wire hardware

STA

STO

SI

AA Next Action Taken By 2-wire Software

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

Data byte in SSDAT has been

transmitted; NOT ACK has

been received

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

becomes free

C0h

No SSDAT action or

No SSDAT action

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted

when the bus becomes free

Switched to the not addressed slave mode; no

recognition of own SLA or GCA

No SSDAT action or

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1

Last data byte in SSDAT has

been transmitted (AA=0); ACK

has been received

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START

condition will be transmitted when the bus

becomes free

C8h

No SSDAT action or

No SSDAT action

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognised; GCA will be recognised if

GC=logic 1. A START condition will be transmitted

when the bus becomes free

Table 70. Miscellaneous Status

Application Software Response

To/from

SSDAT

To SSCON

Status Status of the 2-wire

Code

(SSCS)

bus and 2-wire

hardware

Next Action Taken By 2-wire

STA STO SI AA Software

No relevant state

information

available; SI= 0

No SSDAT

action

F8h

00h

No SSCON action

Wait or proceed current transfer

Only the internal hardware is

affected, no STOP condition is

sent on the bus. In all cases,

the bus is released and STO is

reset.

Bus error due to an

illegal START or

STOP condition

No SSDAT

action

0

1

0

X

94

4289C–8051–11/05

Registers

Table 71. SSCON Register

SSCON - Synchronous Serial Control register (93h)

7

6

5

4

3

2

1

0

CR2

SSIE

STA

STO

SI

AA

CR1

CR0

Bit

Number

Mnemonic Description

Control Rate bit 2

See Table 65.

7

6

CR2

Synchronous Serial Interface Enable bit

Clear to disable the TWI module.

Set to enable the TWI module.

SSIE

Start flag

5

4

STA

ST0

Set to send a START condition on the bus.

Stop flag

Set to send a STOP condition on the bus.

Synchronous Serial Interrupt flag

3

SI

Set by hardware when a serial interrupt is requested.

Must be cleared by software to acknowledge interrupt.

Assert Acknowledge flag

Clear in master and slave receiver modes, to force a not acknowledge (high level

on SDA).

Clear to disable SLA or GCA recognition.

2

AA

Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter

modes.

Set in master and slave receiver modes, to force an acknowledge (low level on

SDA).

This bit has no effect when in master transmitter mode.

Control Rate bit 1

See Table 65.

1

0

CR1

CR0

Control Rate bit 0

See Table 65.

Table 72. SSDAT (095h) - Syncrhonous Serial Data register (read/write)

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

0

7

6

5

4

3

2

1

Bit

Number

Mnemonic Description

7

6

5

4

3

2

SD7

SD6

SD5

SD4

SD3

SD2

Address bit 7 or Data bit 7.

Address bit 6 or Data bit 6.

Address bit 5 or Data bit 5.

Address bit 4 or Data bit 4.

Address bit 3 or Data bit 3.

Address bit 2 or Data bit 2.

95

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AT89C51ID2

Bit

Number

Mnemonic Description

1

0

SD1

SD0

Address bit 1 or Data bit 1.

Address bit 0 (R/W) or Data bit 0.

Table 73. SSCS (094h) read - Synchronous Serial Control and Status Register

7

6

5

4

3

2

1

0

SC4

SC3

SC2

SC1

SC0

0

Table 74. SSCS Register: Read Mode - Reset Value = F8h

Bit

Number

Mnemonic Description

0

1

2

0

Always zero

Status Code bit 0

See to Table 70.

3

4

5

6

7

SC0

SC1

SC2

SC3

SC4

Status Code bit 1

See to Table 70.

Status Code bit 2

See to Table 70.

Status Code bit 3

See to Table 70.

Status Code bit 4

See to Table 70.

Table 75. SSADR (096h) - Synchronus Serial Address Register (read/write)

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Table 76. SSADR Register - Reset value = FEh

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

A7

A6

A5

A4

A3

A2

A1

Slave Address bit 7

Slave Address bit 6

Slave Address bit 5

Slave Address bit 4

Slave Address bit 3

Slave Address bit 2

Slave Address bit 1

96

4289C–8051–11/05

Bit

Number

Mnemonic Description

General Call bit

0

GC

Clear to disable the general call address recognition.

Set to enable the general call address recognition.

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AT89C51ID2

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AT89C51ID2

Serial Port Interface

(SPI)

The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial

communication between the MCU and peripheral devices, including other MCUs.

Features

Features of the SPI Module include the following:

•

Full-duplex, three-wire synchronous transfers

Master or Slave operation

Eight programmable Master clock rates

Serial clock with programmable polarity and phase

Master Mode fault error flag with MCU interrupt capability

Write collision flag protection

Signal Description

Figure 36 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices.

Figure 36. SPI Master/Slaves Interconnection

Slave 1

MISO

MOSI

SCK

SS

VDD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output

(MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK)

Slave Select (SS)

This signal is used to synchronize the data movement both in and out of the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles

which allows to exchange one Byte on the serial lines.

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. It is obvious that only one Master (SS high level) can

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drive the network. The Master may select each Slave device by software through port

pins (Figure 37). To prevent bus conflicts on the MISO line, only one slave should be

selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in

the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and

SCK (see Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

•

The device is configured as a Master and the SSDIS control bit in SPCON is set.

This kind of configuration can be found when only one Master is driving the network

and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in

the SPSTA will never be set⁽¹⁾.

The Device is configured as a Slave with CPHA and SSDIS control bits set⁽²⁾. This

kind of configuration can happen when the system comprises one Master and one

Slave only. Therefore, the device should always be selected and there is no reason

that the Master uses the SS pin to select the communicating Slave device.

Note:

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because

in this mode, the SS is used to start the transmission.

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is con-

trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is

selected from one of seven clock rates resulting from the division of the internal clock by

2, 4, 8, 16, 32, 64 or 128.

Table 77 gives the different clock rates selected by SPR2:SPR1:SPR0.

Table 77. SPI Master Baud Rate Selection

SPR2

SPR1

SPR0

Clock Rate

F_{CLK PERIPH}/2

F_{CLK PERIPH}/4

F_{CLK PERIPH}/8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

F_{CLK PERIPH}/128

Don’t Use

Baud Rate Divisor (BD)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

No BRG

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AT89C51ID2

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AT89C51ID2

Functional Description

Figure 37 shows a detailed structure of the SPI Module.

Figure 37. SPI Module Block Diagram

Internal Bus

SPDAT

Shift Register

FCLK PERIPH

7

6

5

4

3

2

1

0

/4

/8

/16

/32

/64

Clock

Divider

Receive Data Register

Control

Logic

MOSI

MISO

/128

Clock

Logic

M

S

SCK

SS

Clock

Select

SPR2

SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

Control

1-bit signal

SPI Interrupt Request

SPSTA

-

SPIF WCOL

MODF

Operating Modes

The Serial Peripheral Interface can be configured in one of the two modes: Master

mode or Slave mode. The configuration and initialization of the SPI Module is made

through one register:

•

The Serial Peripheral Control register (SPCON)

Once the SPI is configured, the data exchange is made using:

•

SPCON

The Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave

device responds by sending data to the Master device via the MISO line. This implies

full-duplex transmission with both data out and data in synchronized with the same clock

(Figure 38).

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Figure 38. Full-Duplex Master-Slave Interconnection

MISO

MOSI

MISO

MOSI

8-bit Shift register

SPI

SCK

SS

SCK

Clock Generator

SS

VDD

Master MCU

Slave MCU

VSS

Master Mode

The SPI operates in Master mode when the Master bit, MSTR ⁽¹⁾, in the SPCON register

is set. Only one Master SPI device can initiate transmissions. Software begins the trans-

mission from a Master SPI Module by writing to the Serial Peripheral Data Register

(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift

register. The Byte begins shifting out on MOSI pin under the control of the serial clock,

SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.

The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA

becomes set. At the same time that SPIF becomes set, the received Byte from the Slave

is transferred to the receive data register in SPDAT. Software clears SPIF by reading

the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the

SPDAT.

Slave Mode

The SPI operates in Slave mode when the Master bit, MSTR⁽²⁾, in the SPCON register is

cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave

device must be set to ’0’. SS must remain low until the transmission is complete.

In a Slave SPI Module, data enters the shift register under the control of the SCK from

the Master SPI Module. After a Byte enters the shift register, it is immediately trans-

ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an

overflow condition, Slave software must then read the SPDAT before another Byte

enters the shift register ⁽³⁾. A Slave SPI must complete the write to the SPDAT (shift reg-

ister) at least one bus cycle before the Master SPI starts a transmission. If the write to

the data register is late, the SPI transmits the data already in the shift register from the

previous transmission. The maximum SCK frequency allowed in slave mode is F_{CLK PERIPH}

/4.

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity

using two bits in the SPCON: the Clock Polarity (CPOL ⁽⁴⁾) and the Clock Phase

(CPHA⁴). CPOL defines the default SCK line level in idle state. It has no significant

effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 39 and Figure 40).

The clock phase and polarity should be identical for the Master SPI device and the com-

municating Slave device.

1.

The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,

the Master SPI should be configured before the Slave SPI.

2.

3.

The SPI Module should be configured as a Slave before it is enabled (SPEN set).

The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock

speed.

4.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

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AT89C51ID2

Figure 39. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MISO (from Slave)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MSB

SS (to Slave)

Capture Point

Figure 40. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

LSB

bit6

MISO (from Slave)

SS (to Slave)

Capture Point

Figure 41. CPHA/SS Timing

Byte 3

MISO/MOSI

Byte 1

Byte 2

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

As shown in Figure 39, the first SCK edge is the MSB capture strobe. Therefore, the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each Byte transmitted (Figure 41).

Figure 40 shows an SPI transmission in which CPHA is ’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 41). This format may be preffered in systems having only one Master and

only one Slave driving the MISO data line.

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Error Conditions

The following flags in the SPSTA signal SPI error conditions:

Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)

pin is inconsistent with the actual mode of the device. MODF is set to warn that there

may be a multi-master conflict for system control. In this case, the SPI system is

affected in the following ways:

•

An SPI receiver/error CPU interrupt request is generated

The SPEN bit in SPCON is cleared. This disables the SPI

The MSTR bit in SPCON is cleared

When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set

when the SS signal becomes ’0’.

However, as stated before, for a system with one Master, if the SS pin of the Master

device is pulled low, there is no way that another Master attempts to drive the network.

In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in

the SPCON register and therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,

followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-

inal set state after the MODF bit has been cleared.

Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is

done during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA

and an access to SPDAT.

Overrun Condition

An overrun condition occurs when the Master device tries to send several data Bytes

and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte

transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was

last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost.

This condition is not detected by the SPI peripheral.

SS Error Flag (SSERR)

A Synchronous Serial Slave Error occurs when SS goes high before the end of a

received data in slave mode. SSERR does not cause in interruption, this bit is cleared

by writing 0 to SPEN bit (reset of the SPI state machine).

Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 78. SPI Interrupts

Flag

Request

SPIF (SP data transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer

has been completed. SPIF bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is

inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error

CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.

Figure 42 gives a logical view of the above statements.

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AT89C51ID2

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AT89C51ID2

Figure 42. SPI Interrupt Requests Generation

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SPI Receiver/error

CPU Interrupt Request

SSDIS

Registers

There are three registers in the Module that provide control, status and data storage functions. These registers

are describes in the following paragraphs.

Serial Peripheral Control

Register (SPCON)

•

The Serial Peripheral Control Register does the following:

Selects one of the Master clock rates

Configure the SPI Module as Master or Slave

Selects serial clock polarity and phase

Enables the SPI Module

Frees the SS pin for a general-purpose

Table 79 describes this register and explains the use of each bit

Table 79. SPCON Register

SPCON - Serial Peripheral Control Register (0C3H)

Table 1.

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit Number

Bit Mnemonic

Description

Serial Peripheral Rate 2

7

SPR2

SPEN

Bit with SPR1 and SPR0 define the clock rate.

Serial Peripheral Enable

6

5

Cleared to disable the SPI interface.

Set to enable the SPI interface.

SS Disable

Cleared to enable SS in both Master and Slave modes.

SSDIS

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated.

Serial Peripheral Master

4

3

MSTR

CPOL

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle low.

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

2

CPHA

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

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4289C–8051–11/05

Bit Number

Bit Mnemonic

Description

SPR2 SPR1

SPR0 Serial Peripheral Rate

SPR1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

F_{CLK PERIPH}/2

1

F_{CLK PERIPH}/4

F_{CLK PERIPH}/8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

F_{CLK PERIPH}/128

0

SPR0

Invalid

Reset Value = 0001 0100b

Not bit addressable

Serial Peripheral Status Register The Serial Peripheral Status Register contains flags to signal the following conditions:

(SPSTA)

•

Data transfer complete

Write collision

Inconsistent logic level on SS pin (mode fault error)

Table 80 describes the SPSTA register and explains the use of every bit in the register.

Table 80. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

Table 2.

7

6

5

4

3

-

2

-

1

-

0

-

SPIF

WCOL

SSERR

MODF

Bit

Number

Mnemonic Description

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.

7

SPIF

Set by hardware to indicate that the data transfer has been completed.

Write Collision Flag

Cleared by hardware to indicate that no collision has occurred or has been

approved by a clearing sequence.

6

5

4

WCOL

Set by hardware to indicate that a collision has been detected.

Synchronous Serial Slave Error Flag

SSERR Set by hardware when SS is deasserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or

has been approved by a clearing sequence.

MODF

Set by hardware to indicate that the SS pin is at inappropriate logic level.

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

105

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Bit

Number

Mnemonic Description

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reset Value = 00X0 XXXXb

Not Bit addressable

Serial Peripheral DATa Register The Serial Peripheral Data Register (Table 81) is a read/write buffer for the receive data

(SPDAT)

register. A write to SPDAT places data directly into the shift register. No transmit buffer is

available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content

of the shift register.

Table 81. SPDAT Register

SPDAT - Serial Peripheral Data Register (0C5H)

Table 3.

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there

is no on-going exchange. However, special care should be taken when writing to them

while a transmission is on-going:

•

Do not change SPR2, SPR1 and SPR0

Do not change CPHA and CPOL

Do not change MSTR

Clearing SPEN would immediately disable the peripheral

Writing to the SPDAT will cause an overflow.

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AT89C51ID2

Hardware Watchdog

Timer

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer

ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location

0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator

is running and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST-pin.

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR

location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH

and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it

reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This means the user must

reset the WDT at least every 16383 machine cycle. To reset the WDT the user must

write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter

cannot be read or written. When WDT overflows, it will generate an output RESET pulse

at the RST-pin. The RESET pulse duration is 96 x T_{CLK PERIPH}, where T_{CLK PERIPH}= 1/F_CLK

_PERIPH. To make the best use of the WDT, it should be serviced in those sections of code

that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out

capability, ranking from 16ms to 2s @ F_OSCA= 12MHz. To manage this feature, refer to

WDTPRG register description, Table 82.

Table 82. WDTRST Register

WDTRST - Watchdog Reset Register (0A6h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

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Table 83. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)

7

-

6

-

5

-

4

-

3

-

2

1

0

S2

S1

S0

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

0

-

Reserved

-

The value read from this bit is undetermined. Do not try to set this bit.

-

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2S1 S0

Selected Time-out

0

1

0

1

0

1

0 (2¹⁴- 1) machine cycles, 16. 3 ms @ F_OSCA=12 MHz

1 (2¹⁵- 1) machine cycles, 32.7 ms @ F_OSCA=12 MHz

0 (2¹⁶- 1) machine cycles, 65. 5 ms @ F_OSCA=12 MHz

1 (2¹⁷- 1) machine cycles, 131 ms @ F_OSCA=12 MHz

0 (2¹⁸- 1) machine cycles, 262 ms @ F_OSCA=12 MHz

1 (2¹⁹- 1) machine cycles, 542 ms @ F_OSCA=12 MHz

0 (2²⁰- 1) machine cycles, 1.05 s @ F_OSCA=12 MHz

1 (2²¹- 1) machine cycles, 2.09 s @ F_OSCA=12 MHz

Reset value = XXXX X000

WDT During Power Down In Power Down mode the oscillator stops, which means the WDT also stops. While in

Power Down mode the user does not need to service the WDT. There are 2 methods of

and Idle

exiting Power Down mode: by a hardware reset or via a level activated external inter-

rupt which is enabled prior to entering Power Down mode. When Power Down is exited

with hardware reset, servicing the WDT should occur as it normally should whenever the

AT89C51ID2 is reset. Exiting Power Down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabilize. When the interrupt is

brought high, the interrupt is serviced. To prevent the WDT from resetting the device

while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.

It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it

is better to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT89C51ID2 while in Idle mode, the user should always set up a timer that will periodi-

cally exit Idle, service the WDT, and re-enter Idle mode.

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AT89C51ID2

ONCE^(TM)Mode (ON

Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using AT89C51ID2 with-

out removing the circuit from the board. The ONCE mode is invoked by driving certain

pins of the AT89C51ID2; the following sequence must be exercised:

•

Pull ALE low while the device is in reset (RST high) and PSEN is high.

Hold ALE low as RST is deactivated.

While the AT89C51ID2 is in ONCE mode, an emulator or test CPU can be used to drive

the circuit Table 84 shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 84. External Pin Status during ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

Port I2

XTALA1/2

XTALB1/2

Weak

pull-up

Weak

pull-up

Weak

pull-up

Weak

pull-up

Weak

pull-up

Float

Active

(a) "Once" is a registered trademark of Intel Corporation.

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AT89C51ID2

Power-off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a

“warm start” reset.

A cold start reset is the one induced by V_CCswitch-on. A warm start reset occurs while

V_CCis still applied to the device and could be generated for example by an exit from

power-down.

The power-off flag (POF) is located in PCON register (Table 85). POF is set by hard-

ware when V_CCrises from 0 to its nominal voltage. The POF can be set or cleared by

software allowing the user to determine the type of reset.

Table 85. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

Serial port Mode bit 0

SMOD0 Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by

software.

4

POF

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

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EEPROM Data

Memory

The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh

of the XRAM/ERAM memory space and is selected by setting control bits in the EECON

register.

A read or write access to the EEPROM memory is done with a MOVX instruction.

Write Data

Data is written by byte to the EEPROM memory block as for an external RAM memory.

The following procedure is used to write to the EEPROM memory:

•

Check EEBUSY flag

If the user application interrupts routines use XRAM memory space: Save and

disable interrupts.

•

Load DPTR with the address to write

Store A register with the data to be written

Set bit EEE of EECON register

Execute a MOVX @DPTR, A

Clear bit EEE of EECON register

Restore interrupts.

EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading or writing.

•

The end of programming is indicated by a hardware clear of the EEBUSY flag.

Figure 43 represents the optimal write sequence to the on-chip EEPROM data memory.

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Figure 43. Recommended EEPROM Data Write Sequence

EEPROM Data Write

Sequence

EEBusy

Cleared?

Save & Disable IT

EA= 0

EEPROM Data Mapping

EECON = 02h (EEE=1)

Data Write

DPTR= Address

ACC= Data

Exec: MOVX @DPTR, A

EEPROM Mapping

EECON = 00h (EEE=0)

Restore IT

Last Byte

to Load?

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Read Data

The following procedure is used to read the data stored in the EEPROM memory:

•

Check EEBUSY flag

If the user application interrupts routines use XRAM memory space: Save and

disable interrupts.

•

Load DPTR with the address to read

Set bit EEE of EECON register

Execute a MOVX A, @DPTR

Clear bit EEE of EECON register

Restore interrupts.

Figure 44. Recommended EEPROM Data Read Sequence

EEPROM Data Read

Sequence

EEBusy

Cleared?

Save & Disable IT

EA= 0

EEPROM Data Mapping

EECON = 02h (EEE=1)

Data Read

DPTR= Address

ACC= Data

Exec: MOVX A, @DPTR

Last Byte

to Read?

EEPROM Data Mapping

EECON = 00h (EEE = 0

Restore IT

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Registers

Table 86. EECON Register

EECON (0D2h)

EEPROM Control Register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

EEE

EEBUSY

Bit

Bit Number Mnemonic Description

Reserved

7 - 2

-

The value read from this bit is indeterminate. Do not set this bit.

Enable EEPROM Space bit

Set to map the EEPROM space during MOVX instructions (Write or Read to

the EEPROM .

1

EEE

Clear to map the XRAM space during MOVX.

Programming Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

0

EEBUSY

Reset Value = XXXX XX00b

Not bit addressable

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AT89C51ID2

Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting

AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no

longer output but remains active during MOVX and MOVC instructions and external

fetches. During ALE disabling, ALE pin is weakly pulled high.

Table 87. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

-

5

4

3

2

1

0

M0

XRS2

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock

periods (default).

5

M0

Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock

periods.

4

3

XRS2

XRS1

XRAM Size

XRS2 XRS1XRS0XRAM size

0 0 0 256 bytes

0 0 1 512 bytes

0 1 0 768 bytes(default)

0 1 1 1024 bytes

1 0 0 1792 bytes

2

XRS0

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

1

0

EXTRAM Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

(HSB), default setting, XRAM selected.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AO

Reset Value = XX00 10’HSB. XRAM’0b

Not bit addressable

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AT89C51ID2

Flash Memory

The Flash memory increases EPROM and ROM functionality with in-circuit electrical

erasure and programming. It contains 64K bytes of program memory organized respec-

tively in 512 pages of 128 bytes. This memory is both parallel and serial In-System

Programmable (ISP). ISP allows devices to alter their own program memory in the

actual end product under software control. A default serial loader (bootloader) program

allows ISP of the Flash.

The programming does not require external dedicated programming voltage. The nec-

essary high programming voltage is generated on-chip using the standard V_CCpins of

the microcontroller.

Features

•

Flash internal program memory.

Boot vector allows user provided Flash loader code to reside anywhere in the Flash

memory space. This configuration provides flexibility to the user.

•

Default loader in Boot ROM allows programming via the serial port without the need

of a user provided loader.

Up to 64K byte external program memory if the internal program memory is disabled

(EA = 0).

•

Programming and erase voltage with standard power supply.

Read/Programming/Erase:

Byte-wise read without wait state

Byte or page erase and programming (10 ms)

Typical programming time (64K bytes) is 22s with on chip serial bootloader

Parallel programming with 87C51 compatible hardware interface to programmer

Programmable security for the code in the Flash

100k write cycles

10 years data retention

Flash Programming and The 64K bytes Flash is programmed by bytes or by pages of 128 bytes. It is not neces-

sary to erase a byte or a page before programming. The programming of a byte or a

page includes a self erase before programming.

Erasure

There are three methods of programming the Flash memory:

•

First, the on-chip ISP bootloader may be invoked which will use low level routines to

program the pages. The interface used for serial downloading of Flash is the UART.

Second, the Flash may be programmed or erased in the end-user application by

calling low-level routines through a common entry point in the Boot ROM.

Third, the Flash may be programmed using the parallel method by using a

conventional EPROM programmer. The parallel programming method used by

these devices is similar to that used by EPROM 87C51 but it is not identical and the

commercially available programmers need to have support for the AT89C51ID2.

The bootloader and the Application Programming Interface (API) routines are

located in the BOOT ROM.

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Flash Registers and

Memory Map

The AT89C51ID2 Flash memory uses several registers for his management:

•

Hardware registers can only be accessed through the parallel programming modes

which are handled by the parallel programmer.

•

Software registers are in a special page of the Flash memory which can be

accessed through the API or with the parallel programming modes. This page,

called "Extra Flash Memory", is not in the internal Flash program memory

addressing space.

Hardware Register

The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB).

Table 88. Hardware Security Byte (HSB)

7

6

5

4

-

3

2

1

0

X2

BLJB

OSC

XRAM

LB2

LB1

LB0

Bit

Number Mnemonic Description

X2 Mode

Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.

7

6

X2

Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset

(Default).

Boot Loader Jump Bit

Unprogrammed (‘1’ value) to start the user’s application on next reset at address

0000h.

BLJB

Programmed (‘0’ value) to start the boot loader at address F800h on next reset

(Default).

Oscillator Bit

5

4

3

OSC

-

Programmed to allow oscillator B at startup

Unprogrammed this bit to allow oscillator A at startup ( Default).

Reserved

XRAM config bit (only programmable by programmer tools)

Programmed to inhibit XRAM

XRAM

Unprogrammed, this bit to valid XRAM (Default)

User Memory Lock Bits (only programmable by programmer tools)

2-0

LB2-0

See Table 89

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

•

When this bit is programmed (‘1’ value) the boot address is 0000h.

When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,

this bit is unprogrammed and the ISP is enabled.

Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 89.

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Table 89. Program Lock Bits

Program Lock Bits

Security

level

LB0

LB1

LB2 Protection description

1

U

No program lock features enabled.

MOVC instruction executed from external program memory is disabled

from fetching code bytes from internal memory, EA is sampled and

latched on reset, and further parallel programming of the on chip code

memory is disabled.

2

P

U

ISP and software programming with API are still allowed.

Writing EEprom Data from external parallel programmer is disabled but

still allowed from internal code execution.

Same as 2, also verify code memory through parallel programming

interface is disabled.

3

4

X

P

X

U

P

Writing And Reading EEPROM Data from external parallel programmer

is disabled but still allowed from internal code execution..

Same as 3, also external execution is disabled. (Default)

Note:

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X: do not care

WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

These security bits protect the code access through the parallel programming interface.

They are set by default to level 4. The code access through the ISP is still possible and

is controlled by the "software security bits" which are stored in the extra Flash memory

accessed by the ISP firmware.

To load a new application with the parallel programmer, a chip erase must first be done.

This will set the HSB in its inactive state and will erase the Flash memory. The part ref-

erence can always be read using Flash parallel programming modes.

Default Values

The default value of the HSB provides parts ready to be programmed with ISP:

•

BLJB: Programmed force ISP operation.

X2: Unprogrammed to force X1 mode (Standard Mode).

XRAM: Unprogrammed to valid XRAM

LB2-0: Security level four to protect the code from a parallel access with maximum

security.

Software Registers

Several registers are used, in factory and by parallel programmers. These values are

used by Atmel ISP.

These registers are in the "Extra Flash Memory" part of the Flash memory. This block is

also called "XAF" or eXtra Array Flash. They are accessed in the following ways:

•

Commands issued by the parallel memory programmer.

Commands issued by the ISP software.

Calls of API issued by the application software.

Several software registers described in Table 90.

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Table 90. Default Values

Mnemonic

SBV

Definition

Default value

FCh

Description

Software Boot Vector

HSB

Copy of the Hardware security byte

Boot Status Byte

101x 1011b

0FFh

BSB

SSB

Software Security Byte

FFh

Copy of the Manufacturer Code

Copy of the Device ID #1: Family Code

58h

ATMEL

D7h

C51 X2, Electrically Erasable

AT89C51ID2 64KB

Copy of the Device ID #2: memories size

and type

ECh

EFh

Copy of the Device ID #3: name and

revision

AT89C51ID2 64KB, Revision

0

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 90 and Table 93.

To assure code protection from a parallel access, the HSB must also be at the required

level.

Table 91. Software Security Byte

Table 92.

7

6

-

5

-

4

-

3

-

2

-

1

0

-

LB1

LB0

Bit

Number

Mnemonic Description

Reserved

Do not clear this bit.

7

6

-

Reserved

Do not clear this bit.

-

Reserved

Do not clear this bit.

5

-

Reserved

Do not clear this bit.

4

-

Reserved

Do not clear this bit.

3

-

Reserved

Do not clear this bit.

2

User Memory Lock Bits

See Table 93

1-0

LB1-0

The two lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown to Table 93.

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Table 93. Program Lock bits of the SSB

Program Lock Bits

Security

level

LB0

U

LB1

U

Protection description

No program lock features enabled.

ISP programming of the Flash is disabled.

Same as 2, also verify through ISP programming interface is disabled.

1

2

3

P

U

X

P

Note:

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X: do not care

WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

Flash Memory Status

AT89C51ID2 parts are delivered in standard with the ISP rom bootloader.

After ISP or parallel programming, the possible contents of the Flash memory are sum-

marized on the figure below:

Figure 45. Flash memory possible contents

FFFFh

Virgin

or

application

Virgin

or

application

Virgin

Application

Virgin

or

application

Application

Dedicated

ISP

Dedicated

ISP

0000h

After parallel After parallel

programming programming

After parallel

programming

After ISP

Default

After ISP

Memory Organization

When the EA pin high, the processor fetches instructions from internal program Flash. .

If the EA pin is tied low, all program memory fetches are from external memory.

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Bootloader Architecture

Introduction

The bootloader manages a communication according to a specific defined protocol to

provide the whole access and service on Flash memory. Furthermore, all accesses and

routines can be called from the user application.

Figure 46. Diagram Context Description

access via

specific

protocol

Flash memory

Bootloader

access from

user

application

Acronyms

ISP : In-System Programming

SBV: Software Boot Vector

BSB: Boot Status Byte

SSB: Software Security Bit

HW : Hardware Byte

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AT89C51ID2

Functional Description

Figure 47. Bootloader Functional Description

Exernal host with

Specific Protocol

Communication

User

Application

User Call

Management (API )

ISP Communication

Management

Flash Memory

Management

Flash

Memory

On the above diagram, the on chip bootloader processes are:

ISP Communication Management

•

The purpose of this process is to manage the communication and its protocol between

the on-chip bootloader and a external device. The on-chip ROM implement a serial pro-

tocol (see section Bootloader Protocol). This process translate serial communication

frame (UART) into flash memory acess (read, write, erase ...).

•

User Call Management

Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

through a common interface (API calls), included in the ROM bootloader. The program-

ming functions are selected by setting up the microcontroller’s registers before making a

call to a common entry point (0xFFF0). Results are returned in the registers. The pur-

pose on this process is to translate the registers values into internal Flash Memory

Management.

•

Flash Memory Management

This process manages low level access to flash memory (performs read and write

access).

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Bootloader Functionality

Introduction

The bootloader can be activated by two means: Hardware conditions or regular boot

process.

The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the

on-chip bootloader execution. This allows an application to be built that will normally

execute the end user’s code but can be manually forced into default ISP operation.

As PSEN is a an output port in normal operating mode after reset, user application

should take care to release PSEN after falling edge of reset signal. The hardware condi-

tions are sampled at reset signal falling edge, thus they can be released at any time

when reset input is low.

To ensure correct microcontroller startup, the PSEN pin should not be tied to ground

during power-on (See Figure 48).

Figure 48. Hardware conditions typical sequence during power-on.

VCC

PSEN

RST

The on-chip bootloader boot process is shown Figure 49

Purpose

The Hardware Conditions force the bootloader execution whatever BLJB,

BSB and SBV values.

Hardware Conditions

The Boot Loader Jump Bit forces the application execution.

BLJB = 0 => Boot loader execution.

BLJB = 1 => Application execution

The BLJB is a fuse bit in the Hardware Byte.

BLJB

That can be modified by hardware (programmer) or by software (API).

Note:

The BLJB test is perform by hardware to prevent any program

execution..

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Purpose

The Software Boot Vector contains the high address of custumer

bootloader stored in the application.

SBV = FCh (default value) if no custumer bootloader in user Flash.

SBV

Note:

The costumer bootloader is called by JMP [SBV]00h instruction.

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Boot Process

Figure 49. Bootloader Process

RESET

If BLJB=0 then ENBOOT bit (AUXR1) is set

else ENBOOT bit (AUXR1) is cleared

Yes (PSEN = 0, EA = 1, and ALE =1 or not connected)

FCON = 00h

Hardware

condition?

FCON = F0h

BLJB=1

BLJB!= 0

?

ENBOOT=0

BLJB=0

ENBOOT=1

F800h

yes = hardware boot conditions

FCON = 00h

?

BSB = 00h

?

PC=0000h

USER APPLICATION

SBV = FCh

?

USER BOOT LOADER

Atmel BOOT LOADER

PC= [SBV]00h

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ISP Protocol Description

Physical Layer

The UART used to transmit information has the following configuration:

•

Character: 8-bit data

Parity: none

Stop: 2 bits

Flow control: none

Baudrate: autobaud is performed by the bootloader to compute the baudrate

choosen by the host.

Frame Description

The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and

are summarized below

Figure 50. Intel Hex Type Frame

Data

Record

Mark

’:’

Load

Offset

Record

Type

or

Checksum

Reclen

Info

1-byte

2-bytes

n-bytes

1-byte

•

Record Mark:

Record Mark is the start of frame. This field must contain ’:’.

Reclen:

•

Reclen specifies the number of bytes of information or data which follows the Record

Type field of the record.

•

Load Offset:

Load Offset specifies the 16-bit starting load offset of the data bytes, therefore this field

is used only for

Data Program Record (see Section “ISP Commands Summary”).

•

Record Type:

Record Type specifies the command type. This field is used to interpret the remaining

information within the frame. The encoding for all the current record types is described

in Section “ISP Commands Summary”.

•

Data/Info:

Data/Info is a variable length field. It consists of zero or more bytes encoded as pairs of

hexadecimal digits. The meaning of data depends on the Record Type.

•

Checksum:

The two’s complement of the 8-bit bytes that result from converting each pair of ASCII

hexadecimal digits to one byte of binary, and including the Reclen field to and including

the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record

after converting to binary, from the Reclen field to and including the Checksum field, is

zero.

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Functional Description

Software Security Bits (SSB)

The SSB protects any Flash access from ISP command.

The command "Program Software Security bit" can only write a higher priority level.

There are three levels of security:

•

level 0: NO_SECURITY (FFh)

This is the default level.

From level 0, one can write level 1 or level 2.

•

level 1: WRITE_SECURITY (FEh )

For this level it is impossible to write in the Flash memory, BSB and SBV.

The Bootloader returns ’P’ on write access.

From level 1, one can write only level 2.

•

level 2: RD_WR_SECURITY (FCh

The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.

The Bootloader returns ’L’ on read or write access.

Only a full chip erase in parallel mode (using a programmer) or ISP command can reset

the software security bits.

From level 2, one cannot read and write anything.

Table 94. Software Security Byte Behavior

Level 0

Level 1

Level 2

Flash/EEprom

Fuse bit

Any access allowed

Read only access allowed

Write level 2 allowed

Read only access allowed

Not allowed

Any access not allowed

Read only access allowed

Not allowed

Any access allowed

Read only access allowed

Allowed

BSB & SBV

SSB

Manufacturer info

Bootloader info

Erase block

Full chip erase

Blank Check

Allowed

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Full Chip Erase

The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and

sets some bytes used by the bootloader at their default values:

•

BSB = FFh

SBV = FCh

SSB = FFh and finally erase the Software Security Bits

The Full Chip Erase does not affect the bootloader.

Checksum Error

When a checksum error is detected send ‘X’ followed with CR&LF.

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Flow Description

Overview

An initialization step must be performed after each Reset. After microcontroller reset,

the bootloader waits for an autobaud sequence ( see section ‘autobaud performance’).

When the communication is initialized the protocol depends on the record type

requested by the host.

FLIP, a software utility to implement ISP programming with a PC, is available from the

Atmel the web site.

Communication Initialization

The host initializes the communication by sending a ’U’ character to help the bootloader

to compute the baudrate (autobaud).

Figure 51. Initialization

Bootloader

Host

Init communication

"U"

Performs autobaud

If (not received "U")

Else

Sends back U character

Communication opened

Autobaud Performances

The ISP feature allows a wide range of baud rates in the user application. It is also

adaptable to a wide range of oscillator frequencies. This is accomplished by measuring

the bit-time of a single bit in a received character. This information is then used to pro-

gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP

feature requires that an initial character (an uppercase U) be sent to the AT89C51ID2 to

establish the baud rate. Table show the autobaud capability.

Table 95. Autobaud Performances

Frequency (MHz)

Baudrate (kHz)

1.8432

2

2.4576

OK

-

3

3.6864

OK

-

4

5

6

7.3728

OK

2400

OK

-

OK

-

OK

-

4800

-

OK

9600

OK

19200

-

OK

38400

OK

-

OK

57600

-

OK

115200

-

OK

Frequency (MHz)

Baudrate (kHz)

8

10

11.0592

12

14.746

16

20

24

26.6

2400

OK

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Table 95. Autobaud Performances (Continued)

Frequency (MHz)

Baudrate (kHz)

1.8432

2

2.4576

OK

3

3.6864

OK

4

5

6

7.3728

OK

-

4800

OK

-

OK

-

OK

-

OK

-

OK

-

OK

-

9600

OK

19200

OK

38400

OK

57600

-

OK

115200

-

OK

-

OK

Command Data Stream

Protocol

All commands are sent using the same flow. Each frame sent by the host is echoed by

the bootloader.

Figure 52. Command Flow

Host

Bootloader

":"

If (not received ":")

Sends first character of the

Frame

Else

Sends echo and start

reception

Sends frame (made of 2 ASCII

characters per byte)

Echo analysis

Gets frame, and sends back ec

for each received byte

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Write / Program Commands

This flow is common to the following frames:

•

Flash / Eeprom Programming Data Frame

EOF or Atmel Frame (only Programming Atmel Frame)

Config Byte Programming Data Frame

Baud Rate Frame

Description

Figure 53. Write/Program Flow

Bootloader

Host

Write Command

Send Write Command

Wait Write Command

OR

Checksum error

NO_SECURITY

’X’ & CR & LF

Wait Checksum Error

COMMAND ABORTED

Send Checksum error

OR

’P’ & CR & LF

’.’ & CR & LF

Wait Security Error

Send Security error

COMMAND ABORTED

Wait Programming

Wait COMMAND_OK

COMMAND FINISHED

Send COMMAND_OK

Example

Programming Data (write 55h at address 0010h in the Flash)

HOST

: 01 0010 00 55 9A

BOOTLOADER

: 01 0010 00 55 9A . CR LF

Programming Atmel function (write SSB to level 2)

HOST

: 02 0000 03 05 01 F5

BOOTLOADER

: 02 0000 03 05 01 F5. CR LF

Writing Frame (write BSB to 55h)

HOST

: 03 0000 03 06 00 55 9F

: 03 0000 03 06 00 55 9F . CR LF

BOOTLOADER

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Blank Check Command

Description

Figure 54. Blank Check Flow

Bootloader

Host

Blank Check Command

’X’ & CR & LF

Send Blank Check Command

Wait Blank Check Command

OR

Wait Checksum Error

Checksum error

Send Checksum error

COMMAND ABORTED

Flash blank

’.’ & CR & LF

Wait COMMAND_OK

COMMAND FINISHED

OR

Send COMMAND_OK

address & CR & LF

Send first Address

not erased

Wait Address not

erased

COMMAND FINISHED

Example

Blank Check ok

HOST

: 05 0000 04 0000 7FFF 01 78

: 05 0000 04 0000 7FFF 01 78 . CR LF

BOOTLOADER

Blank Check ko at address xxxx

HOST

: 05 0000 04 0000 7FFF 01 78

BOOTLOADER

: 05 0000 04 0000 7FFF 01 78 xxxx CR LF

Blank Check with checksum error

HOST

: 05 0000 04 0000 7FFF 01 70

BOOTLOADER

: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF

132

4289C–8051–11/05

Display Data

Description

Figure 55. Display Flow

Bootloader

Host

Display Command

’X’ & CR & LF

Send Display Command

Wait Display Command

OR

Checksum error

Wait Checksum Error

Send Checksum Error

COMMAND ABORTED

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security Error

COMMAND ABORTED

Read Data

All data read

Complet Frame

"Address = "

"Reading value"

CR & LF

Wait Display Data

Send Display Data

All data read

COMMAND FINISHED

Note:

The maximum size of block is 400h. To read more than 400h bytes, the Host must send a new command.

133

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Example

Display data from address 0000h to 0020h

HOST

: 05 0000 04 0000 0020 00 D7

BOOTLOADER

: 05 0000 04 0000 0020 00 D7

0000=-----data------ CR LF

0010=-----data------ CR LF

0020=data CR LF

(16 data)

( 1 data)

Read Function

This flow is similar for the following frames:

•

Reading Frame

EOF Frame/ Atmel Frame (only reading Atmel Frame)

Description

Figure 56. Read Flow

Bootloader

Host

Read Command

’X’ & CR & LF

Send Read Command

Wait Read Command

OR

Checksum error

Wait Checksum Error

COMMAND ABORTED

Send Checksum error

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security error

COMMAND ABORTED

Read Value

’value’ & ’.’ & CR & LF

Wait Value of Data

Send Data Read

COMMAND FINISHED

134

4289C–8051–11/05

Example

Read function (read SBV)

HOST

: 02 0000 05 07 02 F0

: 02 0000 05 07 02 F0 Value . CR LF

BOOTLOADER

Atmel Read function (read Bootloader version)

HOST

: 02 0000 01 02 00 FB

BOOTLOADER

: 02 0000 01 02 00 FB Value . CR LF

135

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

ISP Commands Summary

Table 96. ISP Commands Summary

Command

Command Name

data[0]

data[1]

Command Effect

Program Nb Data Byte.

Bootloader will accept up to 128

(80h) data bytes. The data bytes

should be 128 byte page flash

boundary.

00h

Program Data

00h

20h

40h

80h

C0h

00h

01h

Erase block0 (0000h-1FFFh)

Erase block1 (2000h-3FFFh)

Erase block2 (4000h-7FFFh)

Erase block3 (8000h- BFFFh)

Erase block4 (C000h- FFFFh)

Hardware Reset

01h

03h

04h

Erase SBV & BSB

Program SSB level 1

05h

Program SSB level 2

Program BSB (value to write in

data[2])

03h

Write Function

00h

01h

06h

Program SBV (value to write in

data[2])

Full Chip Erase (This command

needs about 6 sec to be

executed)

07h

0Ah

-

Program Osc fuse (value to write

in data[2])

02h

04h

08h

Program BLJB fuse (value to

write in data[2])

Program X2 fuse (value to write in

data[2])

Data[0:1] = start address

Data [2:3] = end address

Display Data

Blank Check

04h

Display Function

Data[4] = 00h -> Display data

Data[4] = 01h -> Blank check

Data[4] = 02h -> Display EEPROMk

Display EEPROM data

136

4289C–8051–11/05

Table 96. ISP Commands Summary (Continued)

Command

Command Name

data[0]

data[1]

00h

01h

02h

03h

00h

01h

02h

06h

00h

01h

00h

Command Effect

Manufacturer Id

Device Id #1

00h

Device Id #2

Device Id #3

Read SSB

Read BSB

05h

Read Function

07h

Read SBV

Read Extra Byte

Read Hardware Byte

Read Device Boot ID1

Read Device Boot ID2

Read Bootloader Version

Program Nb EEProm Data Byte.

0Bh

0Eh

0Fh

07h

Program EEPROM data

Bootloader will accept up to 128

(80h) data bytes.

137

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

API Call Description

Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

through a common interface, PGM_MTP. The programming functions are selected by

setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h.

Results are returned in the registers.

When several bytes have to be programmed, it is highly recommended to use the Atmel

API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 bytes in a sin-

gle command.

All routines for software access are provided in the C Flash driver available on Atmel

web site.

The API calls description and arguments are shown in Table

Table 97. API Call Summary

Command

R1

A

DPTR0

DPTR1

Returned Value

Command Effect

ACC = Manufacturer

Id

READ MANUF ID

00h

XXh

0000h

XXh

Read Manufacturer identifier

READ DEVICE ID1

READ DEVICE ID2

READ DEVICE ID3

00h

XXh

0001h

0002h

XXh

ACC = Device Id 1

ACC = Device Id 2

ACC = Device Id 3

Read Device identifier 1

Read Device identifier 2

Read Device identifier 3

Erase block 0

0003h

DPH = 00h

DPH = 20h

DPH = 40h

Erase block 1

Erase block 2

ERASE BLOCK

01h

XXh

00h

ACC = DPH

Address of

byte to

Program one Data Byte in user Flash

program

Erase Software boot vector and boot status

byte. (SBV = FCh and BSB = FFh)

XXh

DPH = 00h

DPL = 00h

Set SSB level 1

Set SSB level 2

Set SSB level 0

DPH = 00h

DPL = 01h

PROGRAM SSB

05h

XXh

00h

ACC = SSB value

DPH = 00h

DPL = 10h

DPH = 00h

DPL = 11h

Set SSB level 1

New BSB

value

PROGRAM BSB

PROGRAM SBV

06h

0000h

0001h

XXh

none

Program boot status byte

Program software boot vector

New SBV

value

READ SSB

READ BSB

READ SBV

07h

XXh

0000h

0001h

0002h

XXh

ACC = SSB

ACC = BSB

ACC = SBV

Read Software Security Byte

Read Boot Status Byte

Read Software Boot Vector

138

4289C–8051–11/05

Table 97. API Call Summary (Continued)

Command

R1

A

DPTR0

DPTR1

Returned Value

Command Effect

Program up to 128 bytes in user Flash.

Address of

the first byte

to program in

the Flash

Address in

XRAM of the

first data to

program

Number of

byte to

program

Remark: number of bytes to program is

limited such as the Flash write remains in a

single 128 bytes page. Hence, when ACC

is 128, valid values of DPL are 00h, or, 80h.

ACC = 0: DONE

PROGRAM DATA

PAGE

09h

memory

Fuse value

00h or 01h

PROGRAM X2 FUSE

0Ah

0008h

0004h

XXh

none

Program X2 fuse bit with ACC

Program BLJB fuse bit with ACC

Fuse value

00h or 01h

PROGRAM BLJB

FUSE

READ HSB

0Bh

0Eh

XXh

XXXXh

DPL = 00h

DPL = 01h

XXXXh

XXh

ACC = HSB

ACC = ID1

Read Hardware Byte

Read boot ID1

READ BOOT ID1

READ BOOT ID2

ACC = ID2

Read boot ID2

READ BOOT VERSION 0Fh

ACC = Boot_Version

Read bootloader version

139

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Electrical Characteristics

Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

I = industrial ........................................................-40°C to 85°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on V_CCto V_SS(standard voltage).........-0.5V to + 6.5V

Voltage on V_CCto V_SS(low voltage)..................-0.5V to + 4.5V

Voltage on Any Pin to V_SS..........................-0.5V to V_CC+ 0.5V

Power Dissipation........................................................... 1 W⁽²⁾

Power dissipation is based on the maximum allow-

able die temperature and the thermal resistance of

the package.

DC Parameters

T_A= -40°C to +85°C; V_SS= 0V;

V

_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)

Symbol

V_IL

Parameter

Min

-0.5

Typ

Max

Unit Test Conditions

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V

V_IH

Input High Voltage except RST, XTAL1

Input High Voltage RST, XTAL1

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

V

_CC= 4.5V to 5.5V

0.3

0.45

1.0

V

I

_OL= 100 μA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL

Output Low Voltage, ports 1, 2, 3, 4 ⁽⁶⁾

V_CC= 2.7V to 5.5V

0.45

V

I

_OL= 0.8 mA⁽⁴⁾

V

_CC= 4.5V to 5.5V

0.3

0.45

1.0

V

I

_OL= 200 μA⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

I_OL= 7.0 mA⁽⁴⁾

V_OL1

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

V_CC= 2.7V to 5.5V

0.45

V

I

_OL= 1.6 mA⁽⁴⁾

V

_CC= 5V ± 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -10 μA

I_OH= -30 μA

I_OH= -60 μA

V_OH

Output High Voltage, ports 1, 2, 3, 4

V_CC= 2.7V to 5.5V

I_OH= -10 μA

0.9 V_CC

V

140

4289C–8051–11/05

T_A= -40°C to +85°C; V_SS= 0V;

V

_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)

Symbol

Parameter

Min

Typ

Max

Unit Test Conditions

_CC= 5V ± 10%

V

V_CC- 0.3

V

I_OH= -200 μA

I_OH= -3.2 mA

I_OH= -7.0 mA

V_CC- 0.7

_CC- 1.5

V

V_OH1

Output High Voltage, port 0, ALE, PSEN

V_CC= 2.7V to 5.5V

I_OH= -10 μA

0.9 V_CC

50

V

R_RST

I_IL

RST Pull-down Resistor

200⁽⁵⁾

250

-50

kΩ

μA

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current

V_IN= 0.45V

I_LI

±10

-650

0.45V < V_IN< V_CC

V_IN= 2.0V

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3, 4

F_C= 3 MHz

T_A= 25°C

C_IO

Capacitance of I/O Buffer

10

pF

I_PD

Power-down Current

75

150

μA

2.7 < V_{CC <}5.5V⁽³⁾

I_CCOP

Power Supply Current on normal mode

Power Supply Current on idle mode

Power Supply Current on flash or EEdata write

Flash or EEdata programming time

0.4 x Frequency (MHz) + 5

0.3 x Frequency (MHz) + 5

0.8 x Frequency (MHz) + 15

10

mA V_CC= 5.5V⁽¹⁾

mA V_CC= 5.5V⁽²⁾

mA V_CC= 5.5V

I_CCIDLE

I_CCWRITE

t_WRITE

7

ms 2.7 < V_{CC <}5.5V

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 60), V_IL

=

V_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used

(see Figure 57).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 58).

-

3. Power-down I_CCis measured with all output pins disconnected; EA = V_CC, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 59).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLSof ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature

and 5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

141

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Figure 57. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V_SS

All other pins are disconnected.

Figure 58. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 59. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

P0

EA

V_CC

RST

XTAL2

XTAL1

(NC)

V_SS

All other pins are disconnected.

Figure 60. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

142

4289C–8051–11/05

AC Parameters

Explanation of the AC

Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T

_LLPL= Time for ALE Low to PSEN Low.

(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other

outputs = 80 pF.)

Table 98 Table 101, and Table 104 give the description of each AC symbols.

Table 99, Table 100, Table 102 and Table 105 gives the range for each AC parameter.

Table 99, Table 100 and Table 106 give the frequency derating formula of the AC

parameter for each speed range description. To calculate each AC symbols. take the x

value in the correponding column (-M or -L) and use this value in the formula.

Example: T_LLIUfor -M and 20 MHz, Standard clock.

x = 35 ns

T 50 ns

T

_CCIV= 4T - x = 165 ns

External Program Memory

Characteristics

Table 98. Symbol Description

Symbol

T

Parameter

Oscillator clock period

ALE pulse width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

Address to Valid Instruction In

PSEN Low to Address Float

143

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 99. AC Parameters for a Fix Clock

Symbol

-M

-L

Units

Min

25

35

5

Max

Min

25

35

5

Max

T

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

5

n 65

30

65

30

5

50

0

10

80

10

80

10

Table 100. AC Parameters for a Variable Clock

Standard

X parameter for

-M range

X parameter for

-L range

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Clock

2 T - x

T - x

4 T - x

T - x

3 T - x

x

X2 Clock

T - x

Units

15

20

35

15

25

45

0

15

20

35

15

25

45

0

ns

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

Min

Max

Min

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

Min

Max

Min

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

15

45

10

15

45

10

T_PLAZ

144

4289C–8051–11/05

External Program Memory

Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

T_PLPH

PSEN

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

External Data Memory

Characteristics

Table 101. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

Address to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

Data Valid to WR Transition

Data Set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

145

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 102. AC Parameters for a Fix Clock

-M

-L

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

125

Max

Min

125

Max

Units

ns

95

0

25

155

160

105

155

160

105

T_AVDV

T_LLWL

45

70

5

45

70

5

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

155

10

0

155

10

0

5

45

5

45

Table 103. AC Parameters for a Variable Clock

Standard

Clock

X parameter for

-L range

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

X2 Clock

3 T - x

2.5 T - x

x

-M range

Units

6 T - x

5 T - x

x

25

30

0

ns

25

30

0

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

25

45

65

30

20

15

0

4T -x

45

T_AVDV

T_LLWL

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

65

30

T_LLWL

30

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

30

20

7 T - x

T - x

20

15

x

0

T - x

0.5 T - x

0.5 T + x

20

T + x

20

146

4289C–8051–11/05

External Data Memory Write

Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RHDZ

T_AVDV

T_LLAX

A0-A7

T_RHDX

DATA IN

PORT 0

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

Serial Port Timing - Shift

Register Mode

Table 104. Symbol Description

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

147

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Table 105. AC Parameters for a Fix Clock

-M

-L

Symbol

T_XLXL

Min

300

200

30

Max

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

117

ns

Table 106. AC Parameters for a Variable Clock

Standard

Clock

X Parameter For

Symbol

T_XLXL

Type

Min

Max

X2 Clock

6 T

-M Range

-L Range

Units

12 T

10 T - x

2 T - x

x

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

5 T - x

T - x

50

20

0

50

20

0

x

10 T - x

5 T- x

133

Shift Register Timing

Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

External Clock Drive

Waveforms

V_CC-0.5V

0.45V

0.7V_CC

0.2V_CC-0.1

T_CHCX

T_CLCH

T_CLCX

T_CHCL

T_CLCL

148

4289C–8051–11/05

AC Testing Input/Output

Waveforms

V

_CC-0.5V

0.45V

0.2 V_CC+ 0.9

0.2 V_CC- 0.1

INPUT/OUTPUT

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

Float Waveforms

FLOAT

V_OH- 0.1V

V_OL+ 0.1V

V_LOAD+ 0.1V

V_LOAD- 0.1V

V_LOAD

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH≥ ± 20 mA.

Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

149

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

Figure 61. Internal Clock Signals

STATE4

INTERNAL

STATE5

P1 P2

STATE6

STATE1

P2

STATE2

P1 P2

STATE3

P1 P2

STATE4

P1 P2

STATE5

P1 P2

CLOCK

P1

P2

P1 P2 P1

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

DATA

PCL OUT

DATA

PCL OUT

DATA

PCL OUT

SAMPLED

FLOAT

P2 (EXT)

INDICATES ADDRESS TRANSITIONS

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

DATA

SAMPLED

P0

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DATA OUT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

MOV PORT SRC

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

(INCLUDES INTO. INT1. TO T1)

SERIAL PORT SHIFT CLOCK

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-

tion also varies from output to output and component. Typically though (T_A= 25°C fully loaded) RD and WR propagation

delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC

specifications.

150

4289C–8051–11/05

AT89C51ID2

Ordering Information

Table 107. Possible Order Entries

Supply

Voltage

Temperature

Range

Part Number

Package Packing

Product Marking

AT89C51ID2-IM

AT89C51ID2-UM

AT89C51ID2-SLSIM

AT89C51ID2-RLTIM

AT89C51ID2-SLSUM

AT89C51ID2-RLTUM

PLCC44

VQFP44

PLCC44

VQFP44

Stick

Tray

Stick

Tray

Industrial

2.7V-5.5V

Industrial &

Green

Change Log for 4289A -

09/03 to 4289B - 12/03

1. Improvement of explanations throughout the document.

4289B - 12/03 to 4289C - 1. Added ‘Industrial & Green” product versions.

11/05

151

4289C–8051–11/05

Packaging Information

PLCC44

152

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

VQFP44

153

4289C–8051–11/05

Table of Contents

Features................................................................................................. 1

Description............................................................................................ 1

Block Diagram....................................................................................... 3

SFR Mapping......................................................................................... 4

Pin Configurations.............................................................................. 10

Oscillators ........................................................................................... 14

Overview............................................................................................................. 14

Registers............................................................................................................. 14

Functional Block Diagram................................................................................... 17

Operating Modes ................................................................................................ 17

Design Considerations........................................................................................ 19

Timer 0: Clock Inputs.......................................................................................... 20

Enhanced Features............................................................................. 21

X2 Feature.......................................................................................................... 21

Dual Data Pointer Register DPTR...................................................... 25

Expanded RAM (XRAM) ..................................................................... 28

Registers............................................................................................................. 30

Reset.................................................................................................... 31

Introduction......................................................................................................... 31

Reset Input ......................................................................................................... 31

Reset Output....................................................................................................... 32

Power Monitor..................................................................................... 33

Description.......................................................................................................... 33

Timer 2................................................................................................. 35

Auto-Reload Mode.............................................................................................. 35

Programmable Clock-Output .............................................................................. 36

Registers............................................................................................................. 38

Programmable Counter Array PCA................................................... 40

PCA Capture Mode............................................................................................. 48

16-bit Software Timer/ Compare Mode............................................................... 48

High Speed Output Mode ................................................................................... 49

Pulse Width Modulator Mode.............................................................................. 50

i

AT89C51ID2

4289C–8051–11/05

AT89C51ID2

PCA Watchdog Timer......................................................................................... 51

Serial I/O Port...................................................................................... 52

Framing Error Detection ..................................................................................... 52

Automatic Address Recognition.......................................................................... 53

Registers............................................................................................................. 55

Baud Rate Selection for UART for Mode 1 and 3............................................... 55

UART Registers.................................................................................................. 58

Interrupt System ................................................................................. 63

Registers............................................................................................................. 64

Interrupt Sources and Vector Addresses............................................................ 71

Power Management............................................................................ 72

Introduction......................................................................................................... 72

Idle Mode............................................................................................................ 72

Power-Down Mode ............................................................................................. 72

Registers............................................................................................................. 75

Keyboard Interface ............................................................................. 76

Registers............................................................................................................. 77

2-wire Interface (TWI) ......................................................................... 80

Description.......................................................................................................... 82

Notes .................................................................................................................. 85

Registers............................................................................................................. 95

Serial Port Interface (SPI)................................................................... 98

Features.............................................................................................................. 98

Signal Description............................................................................................... 98

Functional Description ...................................................................................... 100

Hardware Watchdog Timer .............................................................. 107

Using the WDT ................................................................................................. 107

WDT During Power Down and Idle................................................................... 108

ONCE(TM) Mode (ON Chip Emulation) ........................................... 109

Power-off Flag................................................................................... 110

EEPROM Data Memory..................................................................... 111

Write Data......................................................................................................... 111

Read Data......................................................................................................... 113

Registers........................................................................................................... 114

Reduced EMI Mode........................................................................... 115

ii

4289C–8051–11/05

Flash Memory.................................................................................... 116

Features............................................................................................................ 116

Flash Programming and Erasure...................................................................... 116

Flash Registers and Memory Map.................................................................... 117

Flash Memory Status........................................................................................ 120

Memory Organization ....................................................................................... 120

Bootloader Architecture .................................................................................... 121

ISP Protocol Description................................................................................... 126

Functional Description ...................................................................................... 127

Flow Description ............................................................................................... 129

API Call Description.......................................................................................... 138

Electrical Characteristics................................................................. 140

Absolute Maximum Ratings.............................................................................. 140

DC Parameters................................................................................................. 140

AC Parameters ................................................................................................. 143

Ordering Information........................................................................ 151

Change Log for 4289A - 09/03 to 4289B - 12/03.............................................. 151

4289B - 12/03 to 4289C - 11/05 ....................................................................... 151

Packaging Information..................................................................... 152

PLCC44 ............................................................................................................ 152

VQFP44............................................................................................................ 153

Table of Contents .................................................................................. i

iii

AT89C51ID2

4289C–8051–11/05

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

Fax: (33) 4-76-58-34-80

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4289C–8051–11/05


型号：	AT89C51ID2-RLTUM
厂家：	MICROCHIP
描述：	IC MCU 8BIT 64KB FLASH 44VQFP 时钟微控制器外围集成电路
文件：	总157页 (文件大小：1028K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT89C51ID2-RLTUM [MICROCHIP]

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