AT90PWM81-16MN_技术文档

AT90PWM81/161

3. AVR CPU Core

3.1

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

3.2

Architectural Overview

Figure 3-1. Block diagram of the AVR architecture.

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-register, Y-register, and Z-register, described later in

this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16-bit or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM (Store Program Memory) instruction that writes into the Application Flash

memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

AT90PWM81/161 has Extended I/O space from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

3.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set Summary” on page 301 for a detailed description.

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3.4

Status Register

The Status Register contains information about the result of the most recently executed arithme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the “Instruction Set Summary” on page 301. This will in many cases remove the

need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt

enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the “Instruction Set Summary”

on page 301.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Summary” on page 301 for detailed information.

• Bit 4 – S: Sign Bit, S = N Å V

The S-bit is always an exclusive or between the negative flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Summary” on page 301 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the

“Instruction Set Summary” on page 301 for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Summary” on page 301 for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Summary” on page 301 for detailed information.

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• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Summary” on page 301 for detailed information.

3.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 3-2. AVR CPU General Purpose Working Registers.

7

0

Addr.

R0

0x00

0x01

0x02

R1

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 3-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

3.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 3-3 on page 12.

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Figure 3-3. The X-register, Y-register, and Z-register.

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

0

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see “Instruction Set Summary” on page 301 for

details).

3.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the

Stack with the PUSH instruction, and it is decremented by two when the return address is

pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one

when data is popped from the Stack with the POP instruction, and it is incremented by two when

data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

Bit

15

14

13

12

11

10

9

8

SP15

SP7

7

SP14

SP6

6

SP13

SP5

5

SP12

SP4

4

SP11

SP3

3

SP10

SP2

2

SP9

SP1

1

SP8

SP0

0

SPH

SPL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

3.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

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Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 3-4. The parallel instruction fetches and instruction executions.

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 3-5. Single cycle ALU operation.

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

3.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 248 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 62. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is PSC2 CAPT – the PSC2 Capture

Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the

IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 62 for more infor-

mation. The Reset Vector can also be moved to the start of the Boot Flash section by

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programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Pro-

gramming” on page 233.

3.8.1

Interrupt Behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector

in order to execute the interrupt handling routine, and hardware clears the corresponding inter-

rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be

cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,

the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared

by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable

bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global

Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

Assembly code example

in r16, SREG

; store SREG value

cli

; disable interrupts during timed sequence

sbiEECR, EEMWE ; start EEPROM write

sbiEECR, EEWE

outSREG, r16

; restore SREG value (I-bit)

C code example

char cSREG;

cSREG = SREG;

/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG;

/* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly code example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C code example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

3.8.2

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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4. Memories

This section describes the different memories in the Atmel AT90PWM81/161. The AVR architec-

ture has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the AT90PWM81/161 features an EEPROM Memory for data storage. All three mem-

ory spaces are linear and regular.

4.1

In-System Reprogrammable Flash Program Memory

The AT90PWM81/161 contains 8/16Kbytes On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

4K × 16bits for the AT90PWM81, and 8K × 16bits for the AT90PWM161. For software security,

the Flash Program memory space is divided into two sections, Boot Program section and Appli-

cation Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM81

Program Counter (PC) is 12 bits wide, thus addressing the 8Kbytes program memory locations.

The AT90PWM161 Program Counter (PC) is 13 bits wide, thus addressing the 16Kbytes pro-

gram memory locations. The operation of Boot Program section and associated Boot Lock bits

for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-

Programming” on page 233. “Memory Programming” on page 248 contains a detailed descrip-

tion on Flash programming in SPI or Parallel programming mode.

Constant tables can be allocated within the entire program memory address space (see the

description of LPM – Load Program Memory in “Instruction Set Summary” on page 301).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

Figure 4-1. Program memory map.

Program Memory

0x0000

Application Flash Section

Boot Flash Section

0x0FFF/0x1FFF

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4.2

SRAM Data Memory

Figure 4-2 shows how the Atmel AT90PWM81/161 SRAM memory is organized.

The AT90PWM81/161 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

The lower 512 data memory locations address both the Register File, the I/O memory, Extended

I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the

next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the

next 256 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y-register or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 256/1024 bytes of internal data SRAM in the AT90PWM81/161 are all accessible through all

these addressing modes. The Register File is described in “General Purpose Register File” on

page 11.

Figure 4-2. Data memory map.

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

0x0100

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(256/1024 x 8)

0x01FF/0x04FF

4.2.1

SRAM Data Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 4-3 on page

18.

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Figure 4-3. On-chip data SRAM access cycles.

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

4.3

EEPROM Data Memory

The AT90PWM81/161 contains 512 bytes of data EEPROM memory. It is organized as a sepa-

rate data space, in which single bytes can be read and written. The EEPROM has an endurance

of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is

described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-

ister, and the EEPROM Control Register.

For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial

Downloading” on page 261, and “Parallel Programming Parameters, Pin Mapping, and Com-

mands” on page 252 respectively.

4.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 4-2 on page 21. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered

power supplies, V_CCis likely to rise or fall slowly on power-up/down. This causes the device for

some period of time to run at a voltage lower than specified as minimum for the clock frequency

used. For details on how to avoid problems in these situations see “Preventing EEPROM Cor-

ruption” on page 25.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

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4.3.2

EEARH and EEARL - EEPROM Address Registers

Bit

15

14

13

12

11

10

9

8

–

EEAR8

EEAR0

0

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEARL

7

6

5

4

3

2

1

Read/Write

Initial Value

R

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15..9 – Reserved Bits

These bits are reserved bits in the AT90PWM81/161 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM

may be accessed.

4.3.3

EEDR - EEPROM Data Register

Bit

7

6

5

4

3

2

1

0

EEDR7

R/W

0

EEDR6

R/W

0

EEDR5

R/W

0

EEDR4

R/W

0

EEDR3

R/W

0

EEDR2

R/W

0

EEDR1

R/W

0

EEDR0

R/W

0

EEDR

Read/Write

Initial Value

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

4.3.4

EECR - EEPROM Control Register

Bit

7

6

5

4

3

2

1

0

NVMBSY EEPAGE

EEPM1

R/W

X

EEPM0

R/W

X

EERIE

R/W

0

EEMWE

R/W

0

EEWE

R/W

X

EERE

R/W

0

EECR

Read/Write

Initial Value

R/W

X

R/W

X

• Bits 7 – NVMBSY: Non-volatile memory busy

The NVMBSY bit is a status bit that indicates that the NVM memory (FLASH, EEPROM, Lock-

bits) is busy programming. Once a program operation is started, the bit will be set and it remains

set until the program operation is completed.

Bits 6 – EEPAGE: EEPROM page access (multiple bytes access mode)

Writing EEPAGE to one enables the multiple bytes access mode. That means that several bytes

can be programmed simultaneously into the EEPROM. When the EEPAGE bit has been written

to one, the EEPAGE bit remains set until an EEPROM program operation is completed. Alterna-

tively the bit is cleared when the temporary EEPROM buffer is flushed in software (see EEPMn

bits description). Any write to EEPAGE while EEPE is one will be ignored. See

Section “Program multiple bytes in one Atomic operation”, page 21 for details on how to load

data into the temporary EEPROM page and the usage of the EEPAGE bit.

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• Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be trig-

gered when writing EEWE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 4-1. While

EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to

0b00 unless the EEPROM is busy programming.

Table 4-1.

EEPROM mode bits.

Programming

EEPM1

EEPM0

time

3.4ms

1.8ms

–

Operation

0

1

0

1

0

1

Erase and write in one operation (atomic operation)

Erase only

Write only

Flush temporary EEPROM page buffer

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Mem-

ory Control and Status Register) becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming” on page 233 for details about Boot

programming.

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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 4-2 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 4-2.

Symbol

EEPROM programming time.

Number of calibrated RC oscillator cycles

Typical programming time

EEPROM write

(from CPU)

26368

3.3ms

4.3.5

Program multiple bytes in one Atomic operation

It is possible to write multiple bytes into the EEPROM. Before initiating a programming

(erase/write), the data to be written has to be loaded into the temporary EEPROM page buffer.

Writing EEPAGE to one enables a load operation.

When EEPAGE bit is written to one, the temporary EEPROM page buffer is ready for loading. To

load data into the temporary EEPROM page buffer, the address and data must be written into

EEARL and EEDR respectively. Note that the data is loaded when EEDR is updated. Therefore,

the address must be written before data. This operation is repeated until the temporary

EEPROM page buffer is filled up or until all data to be written have been loaded. The number of

bytes that is loaded must not exceed the temporary EEPROM page size before performing a

program operation. Note that it is not possible to write more than one time to each byte in the

temporary EEPROM page buffer before executing a program operation. If the same byte is writ-

ten multiple times, the content in the temporary EEPROM page will be bit wise AND between the

written data (that is, if 0xaa and 0x55 is loaded to the same byte, the result will be 0x00). The

temporary EEPROM buffer will be ready for new data after the program operation has com-

pleted. Alternatively, the temporary EEPROM buffer is flushed and ready for new data by writing

EEPE (within four cycles after EEMPE is written) if the EEPMn bits are 0b11. When the tempo-

rary EEPROM buffer is flushed, the EEPAGE bit will be cleared. Loading data into the temporary

EEPROM buffer takes three CPU clock cycles. If EEDR is written while EEPAGE is set, the CPU

is halted to ensure that the operation takes three cycles.

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The order the different bits and registers should be accessed is:

1

2

3

4

5

Write EEPAGE in EECR (loading of temporary EEPROM buffer is enabled).

Write the address bits needed to address bytes within a page into EEARL.

Write data to EEDR.

Repeat 2 and 3 above until the buffer is filled up or until all data is loaded.

Write the remaining address bits into EEARH:EEARL.

a.

Select which programming mode that should be executed (EEPMn bits). Write the EEPE

bit in EECR (within four cycles after EEMPE has been written) to start a program opera-

tion. The temporary EEPROM page buffer will auto-erase after program operation is

completed.

OR

b.

If an error situation occurred and the loading should be terminated by software: Write

EEPM1:0 to 0b11 and trigger the flushing by writing EEPE (within four cycles after

EEMPE has been written).

4.4

Fuse Bits

The AT90PWM81/161 has three Fuse bytes. Table 4-3 through Table 4-5 on page 23 describe

briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that

the fuses are read as logical zero, “0”, if they are programmed.

Table 4-3.

Extended low fuse byte.

Extended fuse byte

PSC2RB

Bit no.

Description

Default value

7

6

5

4

3

2

1

0

PSC2 reset behavior

1

PSC2RBA

PSC2 reset behavior for OUT22 & 23

PSC reduced reset behavior

PSCOUT & PSCOUTR reset value

PSC & PSCR inputs reset behavior

Brown-out detector trigger level

1

PSCRRB

1

PSCRV

1

PSCINRB

1

BODLEVEL2 ⁽¹⁾

BODLEVEL1 ⁽¹⁾

BODLEVEL0 ⁽¹⁾

1 (unprogrammed)

0 (programmed)

1 (unprogrammed)

Notes: 1. See Table 7-2 on page 53 for BODLEVEL fuse decoding.

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Table 4-4.

High fuse byte

RSTDISBL ⁽¹⁾

DWEN

Fuse high byte.

Bit no.

Description

Default value

7

6

External reset disable

debugWIRE enable

1 (unprogrammed)

Enable serial program and data

downloading

0 (programmed, SPI

programming enabled)

SPIEN ⁽²⁾

WDTON ⁽³⁾

EESAVE

5

4

3

Watchdog timer always on

1 (unprogrammed)

EEPROM memory is preserved

through the chip erase

1 (unprogrammed), EEPROM

not reserved

Select boot size

(see Table 20-7 on page 246 for

details)

BOOTSZ1

2

0 (programmed) ⁽⁴⁾

Select boot size

(see Table 20-7 on page 246 for

details)

BOOTSZ0

BOOTRST

1

0

0 (programmed) ⁽⁴⁾

1 (unprogrammed)

Select reset vector

Notes: 1. See “Alternate Functions of Port E” on page 80 for description of RSTDISBL fuse.

2. The SPIEN Fuse is not accessible in serial programming mode.

3. See “Watchdog timer configuration.” on page 60 for details.

4. The default value of BOOTSZ1..0 results in maximum boot size.

Table 4-5.

Low fuse byte

CKDIV8 ⁽⁴⁾

CKOUT ⁽³⁾

SUT1

Fuse low byte.

Bit no.

Description

Default value

7

6

5

4

3

2

1

0

Divide clock by 8

Clock output

0 (programmed)

1 (unprogrammed)

1 (unprogrammed) ⁽¹⁾

0 (programmed) ⁽¹⁾

0 (programmed) ⁽²⁾

1 (unprogrammed) ⁽²⁾

0 (programmed) ⁽²⁾

Select start-up time

Select clock source

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Note:

1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 5-4 on page 30 for details.

2. The default setting of CKSEL3..0 results in internal RC oscillator @ 8MHz. See Table 5-1 on

page 28 for details.

3. The CKOUT fuse allows the system clock to be output on PORTD0. See “Clock Output Buffer”

on page 34 for details.

4. See “System Clock Prescaler” on page 39 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

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4.4.1

Code examples

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (for example, by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The examples

also assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly code example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C code example

void EEPROM_write (unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly code example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C code example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

4.4.2

Preventing EEPROM Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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4.5

I/O Memory

The I/O space definition of the AT90PWM81/161 is shown in “Register Summary” on page 297.

All AT90PWM81/161 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

“Instruction Set Summary” on page 301 for more details. When using the I/O specific commands

IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as

data space using LD and ST instructions, 0x20 must be added to these addresses. The

AT90PWM81/161 is a complex microcontroller with more peripheral units than can be supported

within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O

space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be

used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other

AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be

used on registers containing such status flags. The CBI and SBI instructions work with registers

0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

4.6

General Purpose I/O Registers

The AT90PWM81/161 contains four General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global variables and

status flags.

The General Purpose I/O Registers, within the address range 0x00 - 0x1F, are directly bit-

accessible using the SBI, CBI, SBIS, and SBIC instructions.

4.6.1

4.6.2

4.6.3

GPIOR0 - General Purpose I/O Register 0

Bit

7

6

5

4

3

2

1

0

GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR1 - General Purpose I/O Register 1

Bit

7

6

5

4

3

2

1

0

GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 GPIOR1

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR2 - General Purpose I/O Register 2

Bit

7

6

5

4

3

2

1

0

GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 GPIOR2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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5. System Clock and Clock Options

The Atmel AT90PWM81/161 provides a large number of clock sources. Those can be divided in

two categories: internal and external.

After reset, CKSEL fuses select one clock source. Once the device is running, software clock

switching is available on any other clock sources.

Some hardware controls are provided for clock switching management but some specific proce-

dures must be observed. Some settings may lead the user to program the device in an

inadequate configuration.

5.1

Clock Systems and their Distribution

Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

may not be active at a given time. In order to reduce power consumption, the clocks from mod-

ules not being used can be halted by using different sleep modes or by using features of the

dynamic clock switch (“Power Management and Sleep Modes” on page 45 or “Dynamic Clock

Switch” on page 35). The clock systems are detailed below.

Figure 5-1. Clock distribution.

PSC2/PSCR

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_ADC

clk_CPU

clk_I/O

AVR Clock

Control Unit

clk_FLASH

CLK

PLL

Reset Logic

Watchdog Timer

Source Clock

CLK _PLL/4

Prescaler

Watchdog Clock

PLL Input

Multiplexer

Clock switch

CKOUT

Fuse

(Crystal

Oscillator)

Calibrated RC

Oscillator

External Clock

Watchdog

Oscillator

XTAL1

XTAL2

CLKO

5.1.1

clk_CPU- CPU Clock

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

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AT90PWM81/161

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

5.1.2

clk_I/O- I/O Clock

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

5.1.3

5.1.4

5.1.5

clk_FLASH- Flash Clock

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

clk_PLL- PLL Clock

The PLL clock allows the PSC modules to be clocked directly from a 64/32MHz clock. A 16MHz

clock is also derived for the CPU.

clk_ADC- ADC Clock

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

5.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits (default) or by

the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the

selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 5-1.

Device clocking options select ⁽¹⁾, PLL source and PE1 and PE2 functionality.

Device clocking option

System

clock

CKSEL3..0 ⁽³⁾

CSEL3..0 ⁽⁴⁾

PLL input ⁽²⁾

RC Osc ⁽⁶⁾

N/A

PE1

CLKI

I/O

PE2

I/O

External clock

Ext Clk ⁽⁸⁾

0000

0001

0010

0011

PLL output divided by 4 : 16MHz driven by internal RC

Calibrated internal RC oscillator 8MHz

Internal 128kHz RC oscillator (WD)

PLL / 4

RC Osc ⁽⁶⁾

WD ⁽⁷⁾

I/O

PLL output divided by 4 / PLL driven by external

crystal/ceramic resonator

PLL / 4

Ext Osc ⁽⁵⁾

0100

XTAL1

XTAL2

PLL output divided by 4/ PLL driven by external clock

Calibrated internal RC oscillator 1MHz

PLL / 4

Ext Clk ⁽⁸⁾

N/A

0101

0110

CLKI

I/O

RC Osc ⁽⁶⁾

Ext Osc ⁽⁵⁾

I/O

External crystal/ceramic resonator (3.0MHz - 8.0MHz)

External crystal/ceramic resonator (0.9MHz - 3.0MHz)

External crystal/ceramic resonator (3.0MHz - 8.0MHz)

Ext Osc ⁽⁵⁾

RC Osc ⁽⁶⁾

0111 _b

1000 _b

1001 _b

1010 _b

1011 _b

1100 _b

XTAL1

XTAL2

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Table 5-1.

Device clocking options select ⁽¹⁾, PLL source and PE1 and PE2 functionality. (Continued)

Device clocking option

System

clock

CKSEL3..0 ⁽³⁾

PLL input ⁽²⁾

RC Osc ⁽⁶⁾

CSEL3..0 ⁽⁴⁾

1101 _b

PE1

PE2

External crystal/ceramic resonator (3.0MHz - 8.0MHz)

External crystal/ceramic resonator (8.0MHz - 16.0MHz)

Ext Osc ⁽⁵⁾

XTAL1

XTAL2

1110 _b

1111 _b

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

2. PLL must be driven by a nominal 8MHz clock source.

3. Flash fuse bits.

4. CLKSELR register bits.

5. Ext Osc: External oscillator.

6. RC Osc: Internal RC oscillator (1MHz or 8MHz).

7. WD:

Internal watch dog RC oscillator 128kHz.

8. Ext Clk: External clock input.

The various choices for each clocking option is given in the following sections.

When the CPU wakes up from Power-down, or when a new clock source is enabled by the

dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring sta-

ble oscillator operation before instruction execution starts.

When the CPU starts from reset, there is an additional delay allowing the power to reach a sta-

ble level before commencing normal operation. The Watchdog Oscillator is used for timing this

real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out

is shown in Table 5-2.

Table 5-2.

Number of watchdog oscillator cycles.

Typical time-out

4ms

Number of cycles

512

64ms

8K (8,192)

5.2.1

Default Clock Source

The device will always starts up from reset using the clock source defined by CKSEL Fuses the

start-up time defined by SUT Fuses. This configuration is latched in CLKSELR register at reset.

The device will always starts up at Power-on using the clock source defined by CLKSELR regis-

ter (CSEL3..0 and CSUT1:0).

The device is shipped with CKSEL Fuses = 0010 _b, SUT Fuses = 10 _b, and CKDIV8 Fuse pro-

grammed. The default clock source setting is therefore the Internal RC Oscillator running at

8MHz with longest start-up time and an initial system clock prescaling of 8. This default setting

ensures that all users can make their desired clock source setting using an In-System or High-

voltage Programmer. This set-up must be taken into account when using ISP tools.

5.2.2

Calibrated Internal RC Oscillator

By default, the Internal RC OScillator provides an approximate 8.0MHz clock or a 1MHz clock.

Though voltage and temperature dependent, this clock can be very accurately calibrated by the

user.

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The switch between 8MHz and 1MHz is done by the CKRC81 bit in MCUCR register. See

“MCUCR - MCU Control Register” on page 42 for more details.The RC oscillator can be

accessed by two CKSEL or CSEL configurations. At reset, the CKRC81 bit is initialised with the

value compatible with CKSEL value (1 for CKSEL3..0 = 0110, 0 for all other values).

The RC oscillator is active for any CKSEL3..0 or CSEL3..0 configuration where it is used as sys-

tem clock or PLL source clock. The RC oscillator is diabled in the following CKSEL3..0 or

CSEL3..0 cases:

•

0011 (128k oscillator)

0100, 0101 (PLL/4 system clock driven by external clock or oscillator)

1100, 1101 (External oscillator)

The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on

page 39 for more details. This clock may be selected as the system clock by programming the

CKSEL Fuses or CSEL field as shown in Table 5-1 on page 28. If selected, it will operate with no

external components. During reset, hardware loads the calibration byte into the OSCCAL Regis-

ter and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is

shown as Factory calibration in Table 22-1 on page 270.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 39, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 22-1 on page 270.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section “Calibration Byte” on page 252.

Table 5-3.

Internal calibrated RC oscillator operating modes ⁽¹⁾⁽³⁾

.

Frequency range ⁽²⁾(MHz)

CKSEL3..0

0010

7.6 - 8.4

0.95 - 1.05 ⁽⁴⁾

0010

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

4. Switch between 8MHz and 1MHz is done by CKRC81 bit in MCUCR register.

When this oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 5-4 on page 30.

Table 5-4.

Start-up times for the internal calibrated RC Oscillator clock selection.

Start-up time from power-

down

Additional delay from

reset (V_CC= 5.0V)

Power conditions

BOD enabled

SUT1..0

00

6CK

14CK ⁽¹⁾

Fast rising power

Slowly rising power

14CK + 4.1ms

14CK + 65ms ⁽²⁾

01

6CK

10

Reserved

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1ms to ensure programming mode can be entered.

2. The device is shipped with this option selected.

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5.2.2.1

RC Oscillator calibration at Factory

The RC oscillator is calibrated at 3V, 25°C for an 8MHz target frequency with an Accuracy 1%.

The corresponding value OSCAL (@Amb.) is stored in the signature row and automatically

loaded in the OSCAL register at reset.

The RC oscillator is monitored at 105°C or 125°C (versus Product version) with an accuracy

within 5% limits.

5.2.3

128KHz Internal Oscillator

The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming CKSEL Fuses or CSEL field as shown in Table 5-1 on page 28.

When this clock source is selected, start-up times are determined by the SUT Fuses or by CSUT

field as shown in Table 5-5.

Table 5-5.

Start-up times for the 128kHz internal oscillator.

SUT1..0 ⁽¹⁾

Start-up time from power-

down

Additional delay from

Recommended

usage

CSUT1..0 ⁽²⁾

reset

00

01

10

11

6 CK

14CK

BOD enabled

14CK + 4ms

14CK + 64ms

Fast rising power

Slowly rising power

Reserved

Notes: 1. Flash Fuse bits.

2. CLKSELR register bits.

5.2.4

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 5-2 on page 31. Either a quartz

crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 5-6. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

Figure 5-2. Crystal oscillator connections.

C2

XTAL2

C1

XTAL1

GND

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7734Q–AVR–02/12

AT90PWM81/161

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in

Table 5-6.

CKSEL3..1 ⁽¹⁾

CSEL3..1 ⁽²⁾

Crystal oscillator operating modes.

Recommended range for capacitors

C1 and C2 for use with crystals [pF]

Frequency range [MHz]

100 ⁽³⁾

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 - 16.0

–

101

12 - 22

110

111

Notes: 1. Flash fuse bits.

2. CLKSELR register bits.

3. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field

select the start-up times as shown in Table 5-7.

Table 5-7.

Start-up times for the crystal oscillator clock selection.

CKSEL0

Start-up time from

power-down and

power-save

Additional delay

from reset

(V_CC= 5.0V)

SUT1..0 ⁽¹⁾

CSUT1..0 ⁽²⁾

(1)

CSEL0 ⁽²⁾

Recommended usage

Ceramic resonator,

fast rising power

0

00

01

10

11

00

01

10

11

258CK ⁽³⁾

14CK + 4.1ms

14CK + 65ms

14CK

Ceramic resonator,

slowly rising power

0

1

258CK ⁽³⁾

Ceramic resonator,

BOD enabled

1K (1024)CK ⁽⁴⁾

16K (16384)CK

Ceramic resonator,

fast rising power

14CK + 4.1ms

14CK + 65ms

14CK

Ceramic resonator,

slowly rising power

Crystal oscillator,

BOD enabled

Crystal oscillator,

fast rising power

14CK + 4.1ms

14CK + 65ms

Crystal oscillator,

slowly rising power

Notes: 1. Flash fuse bits.

2. CLKSELR register bits.

3. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

4. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

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5.2.5

External Clock

To drive the device from this external clock source, CLKI should be driven as shown in Figure 5-

3. To run the device on an external clock, the CKSEL Fuses or CSEL field must be programmed

as shown in Table 5-1 on page 28.

Figure 5-3. External clock drive configuration.

External

Clock

Signal

CLKI

(XTAL1)

GND

When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT

field as shown in Table 5-8.

Table 5-8.

Start-up times for the external clock selection.

SUT1..0 ⁽¹⁾

CSUT1..0 ⁽²⁾

Start-up time from

Additional delay from reset

Recommended usage

power-down

00

01

10

11

6CK

14CK

BOD enabled

6CK

14CK + 4ms

14CK + 64ms

Reserved

Fast rising power

Slowly rising power

6CK

Notes: 1. Flash Fuse bits.

2. CLKSELR register bits.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

39 for details.

5.2.6

PLL

To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency

clock input. This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of

PLL must be configured by software.

The internal PLL in AT90PWM81/161 generates a clock frequency multiplied from nominally

8MHz input. The source of the 8MHz PLL input clock can be selected from three possible

sources (see the Figure 5-4 on page 34):

•

Internal RC Oscillator

Crystal oscillator

External clock

The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit

PLOCK from the register PLLCSR is set when PLL is locked.

When selected as clock source by fuse, the PLL multiplication factor is initialized at the value of

6, compatible with a 3V supply.

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The PLL is locked on the source oscillator which must remains close to 8MHz to assure proper

lock of the PLL.

Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes

Start-up times when the PLL is selected as system clock.

Table 5-9.

CKSEL3..0

Start-up time from power-

down

Additional delay from reset

(V_CC= 5.0V)

SUT1..0

00

Clock source

1K CK

16K CK

1K CK

14CK

01

14CK + 4ms

14CK + 64ms

14CK

External crystal or

resonator

0100

10

11

00

14CK

01

14CK + 4ms

14CK + 64ms

14CK

0101

0001

External clock

10

11

00

01

14CK + 4ms

14CK + 64ms

Internal RC oscillator

10

Figure 5-4. PCK clocking system.

PLLF3..0

OSCCAL

PLLE

CKSEL3..0

Lock

Detector

PLOCK

RCOSCILLATOR

CLK _PLL

PLL

*N

8MHz

DIVIDE

BY 4

CK _SOURCE

XTAL1

OSCILLATORS

XTAL2

5.2.7

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse or COUT bit of CLKSELR register has to be programmed. This mode is suitable when the

chip clock is used to drive other circuits on the system. Note that the clock will not be output dur-

ing reset and the normal operation of I/O pin will be overridden when the fuses are programmed.

Any clock source can be selected when the clock is output on CLKO. If the System Clock Pres-

caler is used, it is the divided system clock that is output.

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5.3

Dynamic Clock Switch

5.3.1

Features

AT90PWM81/161 provides a powerful dynamic clock switch that allows users to turn on and off

clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or

disabled asynchronously. This enables efficient power management schemes to be imple-

mented easily and quickly. In a safety application, the dynamic clock switch circuit may

continuously monitor the external clock fails.

The AT90PWM81/161 provides one register for Clock Fuse substitution (CLKSELR) and one

register to control the dynamic clock switch circuit (CLKCSR). The watchdog is used to monitor

external clock source if needed. The control of the dynamic clock switch circuit must be super-

vised by software. The low level control is performed by hardware through the CLKCSR register.

The features are:

• Safe commands, to avoid unintentional commands, a special write procedure must be

followed to change the CLKCSR register bits (see “CLKCSR – Clock Control & Status

Register” on page 42):

• Exclusive action, the actions are controlled by a decoding (command table). The main

commands of the dynamic clock switching are:

– ‘Disable Clock Source’,

– ‘Enable Clock Source’,

– ‘Request for Clock Availability’,

– ‘Clock Source Switching’,

– ‘Recover System Clock Source’.

• Status, a status on the availability of the enabled clock and the code recovering of clock

source used to drive the system clock are provided.

5.3.2

5.3.3

Fuses substitution

During reset, bits of the Low Fuse Byte are latched in the CLKSELR register. The content of this

register can operate as well as the Low Fuse Byte. CKSEL3..0, SUT1..0 and CKOUT fuses are

substituted as shown in Figure 5-5 and replaced respectively by CSEL3..0, CSUT1:0 and

COUT.

Clock Source Selection

The available codes of clock source is given are in Table 5-1 on page 28.

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Figure 5-5. Fuses substitution and clock source selection.

Fuse:

Register:

Fuse Low Byte

CLKSELR

SEL-0

SEL-1

SEL-2

CKSEL[3..0]

SEL-n

Reset

Selected

Configuration

SUT[1..0]

(

)

*

SCLKRq

CKOUT

EN-0

EN-1

EN-2

Clock

Switch

Current

Configuration

(

)

*

EN-n

SCLKRq : Command of Clock Control & Status Register

When ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’

command is entered, the selected configuration provided by the CLKSELR register is latched for

each targeted clock source.

‘Recover System Clock Source’ command enables the code recovering of clock source used to

drive the system clock. The CKSEL field of CLKSELR register is then updated with this code.

There is no information on the SUT used or status on CKOUT.

Because the selected configuration is latched at clock source level, it is possible to enable many

clock sources at a given time (ex: the internal RC oscillator for system clock + an oscillator with

external crystal). The user’s software has the responsibility of this management.

‘Request for Clock Availability’ command returns the working order of the clock source

addressed. The status is set in the CLKRDY bit of CLKCSR register.

5.3.4

Enable/Disable Clock Source

‘Enable Clock Source’ command selects and enables the clock source provided by the setting of

CLKSELR register (CSEL3..0 and CSUT1:0). CSEL field will select the clock source and CSUT

field will select the start-up time (as CKSEL and SUT fuse bits do it). To be sure that a clock

source has been enabled, it will be better to perform a ‘Request for Clock Availability’ command

after the ‘Enable Clock Source’ command.

‘Disable Clock Source’ command disables the clock source provided by the setting of CLKSELR

register (only CSEL3..0). If the clock source is the one that is used to drive the system clock, the

command is not taken into account.

5.3.5

Clock Availability

‘Request for Clock Availability’ command enables an oscillation-counting of the selected source

clock, CSEL3..0. The count is provided by CSUT1..0. The clock is declared ready (CLKRDY = 1)

when the count is finished. This flag remains unchanged up to a new count. The CLKRDY flag is

reset when the count starts. To perform this checking, the CKSEL and CSUT fields should not

change all long the operation is running.

Two usages are possible:

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AT90PWM81/161

1. Clock stability before switching

Once the new clock source is selected, the count procedure is running. The user (code)

should wait for the setting of the CLKRDY flag in CLKSCR register before to perform a

switching.

2. Clock available on request

AT any time, the user (code) can ask for the availability of a clock source. The user (code)

can request it writing the appropriate command in the CLKSCR register. A full status on

clock sources then can be done.

5.3.6

Clock Switching

To drive the system clock, the user can switch from the current clock source to the following

ones (one of them is the current clock source):

1. Calibrated internal RC oscillator 8.0MHz/1.0MHz,

2. Internal watchdog oscillator 128kHz,

3. External clock,

4. External Crystal/Ceramic Resonator,

5. PLL output divided by four.

The clock switching is performed in a sequence of commands. First, the user (code) must make

sure that the new clock source is running. Then the switching command can be entered. At the

end, the user (code) can stop the previous clock source. It will be better to run this sequence

once the interrupts disabled. The user (code) has the responsibility of the clock switching

sequence.

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Here is a “light” C-code that describes such a sequence of commands.

C code example

void ClockSwiching (unsigned char clk-number, unsigned char sut) {

#define CLOCK-RECOVER 0x05

#define CLOCK-ENABLE

#define CLOCK-SWITCH

0x02

0x04

#define CLOCK-DISABLE 0x01

unsigned char previous-clk, temp;

// Disable interrupts

asm ("cli"); temp = SREG;

// “Recover System Clock Source” command

CLKCSR = 1 << CLKCCE;

CLKCSR = CLOCK-RECOVER;

previous-clk = CLKSELR & 0x0F;

// “Enable Clock Source” command

CLKSELR = ((sut << 4 ) & 0x30) | (clk-number & 0x0F);

CLKCSR = 1 << CLKCCE;

CLKCSR = CLOCK-ENABLE;

// Wait for clock availability

while ((CLKCSR & (1 << CLKRDY)) == 0);

// “Clock Source Switching” command

CLKCSR = 1 << CLKCCE;

CLKCSR = CLOCK-SWITCH;

// Wait for effective switching

while (1){

CLKCSR = 1 << CLKCCE;

CLKCSR = CLOCK-RECOVER;

if ((CLKSELR & 0x0F) == (clk-number & 0x0F)) break;

}

// “Disable Clock Source” command

CLKSELR = previous-clk;

CLKCSR = 1 << CLKCCE;

CLKCSR = CLOCK-DISABLE;

// Re-enable interrupts

SREG = temp; asm ("sei");

}

Warning:

In the AT90PWM81/161, only one among the external clock sources can be enabled at a given

time and it is not possible to switch from external clock to external oscillator as both sources

share one pin.

Also, it is not possible to switch the synchronization source of the PLL when the sytem clock is

PLL/4. See Table 5-1 on page 28 to identify these cases.

As they are two CSEL adresses to access the Calibrated internal RC oscillator 8.0MHz/1.0MHz,

the change between the two frequencies is not allowed by the clock switching features. The

CKRC81 bit in MCUCR register must be used for this purpose.

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5.4

System Clock Prescaler

5.4.1

Features

The AT90PWM81/161 system clock can be divided by setting the Clock Prescaler Register –

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH

are divided by a factor as shown in Table 5-10 on page 40.

5.4.2

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 × T2 before

the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is

the previous clock period, and T2 is the period corresponding to the new prescaler setting.

5.5

Register Description

5.5.1

OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. The factory-calibrated value is automat-

ically written to this register during chip reset, giving an oscillator frequency of 8.0MHz at 25°C.

The application software can write this register to change the oscillator frequency. The oscillator

can be calibrated to any frequency in the range 7.6MHz - 8.4MHz within 1% accuracy. Calibra-

tion outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range. Incrementing CAL7..0 by 1 will give a frequency increment of less than 0.5% in the fre-

quency range 7.6MHz - 8.4MHz.

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7734Q–AVR–02/12

AT90PWM81/161

5.5.2

CLKPR – Clock Prescaler Register

Bit

7

CLKPCE

R/W

6

–

5

–

4

–

3

2

1

0

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM81/161 and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 5-10.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting in order not to disturb the

procedure.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of eight at start up. This feature should be used if the selected

clock source has a higher frequency than the maximum frequency of the device at the present

operating conditions. Note that any value can be written to the CLKPS bits regardless of the

CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selected clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse

programmed.

Table 5-10. Clock prescaler select.

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock division factor

0

1

0

1

0

1

0

1

0

1

2

4

8

16

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Table 5-10. Clock prescaler select. (Continued)

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock division factor

32

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64

128

256

Reserved

5.5.3

PLLCSR - PLL Control and Status Register

Bit

7

–

R

0

6

–

R

0

5

4

3

2

1

0

$29 ($29)

Read/Write

Initial Value

PLLF3

R/W

0

PLLF2

R/W

1

PLLF1

R/W

0

PLLF0

R/W

0

PLLE

R/W

0/1

PLOCK

PLLCSR

R

0

• Bit 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM81/161 and always read as zero.

• Bit 5..2-– PLLF: PLL Factor

The PLLF bits is used to select the multiplication factor of the PLL.

Table 5-11. PLL multiplication factor.

PLLF3..0

N+2

PLL frequency [MHz]

7-F

6

Reserved

8

7

6

5

4

64

56

5

4

48

3

40

2

32

0-1

Reserved

Note:

PLLF3 is used for debug purpose (must be wired).

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• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is

started as PLL reference clock. If PLL is selected as a system clock source the value for this bit

is always 1.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable

CLK_PLLfor PSC. The time to lock is specified in Table 5-9 on page 34.

5.5.4

MCUCR - MCU Control Register

Bit

7

6

–

R

0

5

–

R

0

4

3

2

1

0

–

R

0

PUD

R/W

0

RSTDIS

R/W

0/1 ⁽¹⁾

CKRC81

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

R/W

0

Notes: 1. Value is initialized with the fuse CKSEL2.

2. Value is initialized with fuses CKSEL3..0 (1 when CKSEL3..0= 0110, 0 in all other cases).

• Bit 2– CKRC81: Frequency Selection of the calibrated 8/1MHz RC Oscillator

Thanks to CKRC81 in MCUCR Sfr, the typical frequency of the calibrated RC oscillator is

changed.

– When the CKRC81 bit is written to zero, the RC oscillator frequency is 8MHz.

– When the CKRC81 bit is written to one, the RC oscillator frequency is 1MHz.

Note: This bit only can be changed only when the RC oscillator is enabled.

Note: When the RC oscillator is used as the PLL source, CKRC81 must not be written to 1.

Note: If the RC oscillator is disabled, this bit is cleared by hardware.

5.5.5

CLKCSR – Clock Control & Status Register

Bit

7

6

5

–

4

3

CLKC3

R/W

0

2

CLKC2

R/W

0

1

CLKC1

R/W

0

CLKC0

R/W

0

CLKCCE

–

CLKRDY

CLKCSR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

• Bit 7 – CLKCCE: Clock Control Change Enable

The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The

CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to zero.

CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits are

written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out

period, nor clear the CLKCCE bit.

• Bits 6:5 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM81/161 and will always read as zero.

• Bits 4 – CLKRDY: Clock Ready Flag

This flag is the output of the ‘Clock Availability’ logic.

This flag is reset once the ‘Request for Clock Availability’ command is entered.

It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is stable.

The delay from the request and the flag setting is not fixed, it depends on the clock start-up time,

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AT90PWM81/161

the clock frequency and, of course, if the clock is alive. The user’s has itself to do the difference

between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’.

• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0

These bits define the command to provide to the ‘Clock Switch’ module. The special write

procedure must be followed to change the CLKC bits (see “Bit 7 – CLKCCE: Clock Control Change

Enable” on page 42).

1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in

CLKCSR to zero.

2. Within four cycles, write the desired value to CLKCSR register while clearing CLKCCE

bit.

Interrupts should be disabled when setting CLKCSR register in order not to disturb the

procedure.

Table 5-12. Clock command list.

Clock command

CLKC3..0

0000 _b

0001 _b

0010 _b

0011 _b

0100 _b

0101 _b

0111 _b

1xxx _b

No command

Disable clock source

Enable clock source

Request for clock availability

Clock source switch

Recover system clock source code

CKOUT command

No command

5.5.6

CLKSELR - Clock Selection Register

Bit

7

6

5

4

3

2

1

0

-

COUT

R/W

CSUT1

R/W

CSUT0

R/W

CSEL3

R/W

CSEL2

R/W

CSEL1

R/W

CSEL0

R/W

CLKSELR

Read/Write

Initial Value

R

0

CKOUT

fuse

SUT1..0

fuses

CKSEL3..0

fuses

• Bit 7– Res: Reserved Bit

This bit is reserved bit in the AT90PWM81/161 and will always read as zero.

• Bit 6 – COUT: Clock Out

The COUT bit is initialized with CKOUT Fuse bit.

The COUT bit is only used in case of ‘CKOUT’ command. Refer to Section 5.2.7 ”Clock Output

Buffer” on page 34 for using.

In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of

this setting).

• Bits 5:4 – CSUT1:0: Clock Start-up Time

CSUT bits are initialized with the values of SUT Fuse bits.

In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock

start-up time. Refer to subdivisions of Section 5.2 ”Clock Sources” on page 28 for code of clock

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start-up times.

In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recovering

of SUT code).

• Bits 3:0 – CSEL3:0: Clock Source Select

CSEL bits are initialized with the values of CKSEL Fuse bits.

In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source

Switch’ command, CSEL field gets back the code of the clock source. Refer to Table 5-1 on

page 28 and subdivisions of Section 5.2 ”Clock Sources” on page 28 for clock source codes.

In case of ‘Recover System Clock Source’ command, CSEL field receives the code of the clock

source used to drive the Clock Control Unit as described in Figure 5-1 on page 27.

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6. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

6.1

Sleep Modes

Figure 5-1 on page 27 presents the different clock systems in the AT90PWM81/161, and their

distribution. The figure is helpful in selecting an appropriate sleep mode. Table 6-1 shows the

different sleep modes, their wake up sources.

Table 6-1.

Active clock domains and wake-up sources in the different sleep modes.

Active clock domains

Oscillators

Wake-up sources

Sleep

mode

Idle

X

ADC noise

reduction

X ⁽²⁾

Power-

down

X ⁽²⁾

X

Standby ⁽¹⁾

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. Only level interrupt.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode (Idle, ADC Noise Reduction, Power-down or Standby) will be activated by the

SLEEP instruction. See Table 6-2 on page 48 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the register file and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

6.2

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing SPI, Analog Comparator, ADC, Timer/Counters, Watch-

dog, and the interrupt system to continue operating. This sleep mode basically halt clk_CPUand

clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow interrupts. If wake-up from the Analog Comparator interrupt is not

required, the Analog Comparator can be powered down by clearing the ACnEN bit in the Analog

Comparator Control and Status Register – ACnCON. This will reduce power consumption in Idle

mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

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6.3

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts,

Timer/Counter (if their clock source is external - T0 or T1) and the Watchdog to continue operat-

ing (if enabled). This sleep mode basically halts clk_I/O, clk_CPU, and clk_FLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, a Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt

on INT2:0 can wake up the MCU from ADC Noise Reduction mode.

6.4

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the External Oscillator is stopped, while the External Interrupts and

the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a

Brown-out Reset, a PSC Interrupt, an External Level Interrupt on INT2:0 can wake up the MCU.

This sleep mode basically halts all generated clocks, allowing operation of asynchronous mod-

ules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 83

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 28.

6.5

6.6

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-

als to reduce power consumption. The current state of the peripheral is frozen and the I/O

registers can not be read or written. Resources used by the peripheral when stopping the clock

will remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

A full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping

and starting of its clock. So its recommended to stop a peripheral before stopping its clock with

PRR register.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.

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6.7

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

6.7.1

6.7.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “ADC Noise Canceler” on page 210 for

details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled.

In other sleep modes, the Analog Comparator is NOT automatically disabled, so it should be dis-

abled if not used.

However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the

Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-

erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 194

for details on how to configure the Analog Comparator.

6.7.3

6.7.4

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to “Brown-out Detection” on page 53 for details

on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 55 for details on the start-up time.

6.7.5

6.7.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 56 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device will

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be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “I/O-Ports” on page 68 for details on which pins are enabled. If the

input buffer is enabled and the input signal is left floating or have an analog signal level close to

V

_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “DIDR1 - Digital Input Disable Register 1” on page 222 and “DIDR0 - Digital

Input Disable Register 0” on page 202 for details.

6.7.7

On-chip Debug System

If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the

main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,

this will contribute significantly to the total current consumption.

6.8

Register description

6.8.1

SMCR - Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

SM2

R/W

0

SM1

R/W

0

SM0

R/W

0

SE

R/W

0

SMCR

Read/Write

Initial Value

• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 6-2.

Table 6-2.

Sleep mode select.

SM2

SM1

SM0

Sleep mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC noise reduction

Power-down

Reserved

Standby ⁽¹⁾

Reserved

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

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6.8.2

PRR - Power Reduction Register

Bit

7

6

-

5

4

3

-

2

1

-

0

PRPSC2

PRPSCR

PRTIM1

R/W

0

PRSPI

R/W

0

PRADC

R/W

0

PRR

Read/Write

Initial Value

R/W

0

R

0

R/W

0

R

0

R

0

• Bit 7 - PRPSC2: Power Reduction PSC2

Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this

module. When waking up the PSC2 again, the PSC2 should be re initialized to ensure proper

operation.

• Bit 6 - Reserved

• Bit 5 - PRPSCR: Power Reduction PSC reduced

Writing a logic one to this bit reduces the consumption of the PSCR by stopping the clock to this

module. When waking up the PSCR again, the PSCR should be re initialized to ensure proper

operation.

• Bit 4 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit reduces the consumption of the Timer/Counter1 module. When the

Timer/Counter1 is enabled, operation will continue like before the setting of this bit.

• Bit 3 - Reserved

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit reduces the consumption of the Serial Peripheral Interface by stop-

ping the clock to this module. When waking up the SPI again, the SPI should be re initialized to

ensure proper operation.

• Bit 1 - Reserved

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this

module. The ADC must be disabled before using this function. The analog comparator cannot

use the ADC input MUX when the clock of ADC is stopped.

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7. System Control and Reset

7.1

System Control overview

7.1.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the Interrupt

Vectors are in the Boot section or vice versa. The circuit diagram in Figure 7-1 on page 51

shows the reset logic. Table 7-1 on page 51 defines the electrical parameters of the reset

circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 28.

7.1.2

Reset Sources

The Atmel AT90PWM81/161 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length. The external reset pin can be disabled in 2 ways:

– By the RSTDISBL fuse. In this case , the SPI programming is disabled.

– By software using the RSTDIS bit in MCUCR register. In this case , the SPI

programming is still active at power up time.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the brown-out detector is enabled.

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Figure 7-1. Reset logic.

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

Spike

Filter

RSTDIS

Watchdog

Oscillator

Delay Counters

Clock

Generator

CK

TIMEOUT

CKSEL[3:0]

SUT[1:0]

Table 7-1.

Symbol Parameter

Power-on reset threshold

Reset characteristics ⁽¹⁾

.

Condition

Minimum Typical Maximum

Units

1.4

1.3

2.3

V

voltage (rising)

V_POT

Power-on reset threshold

voltage (falling) ⁽²⁾

2.3

V

V_RST

t_RST

RESET pin threshold voltage

0.2V_CC

0.85V_CC

Minimum pulse width on

RESET pin

400

ns

Notes: 1. Values are guidelines only.

2. The power-on reset will not work unless the supply voltage has been below V_POT(falling).

7.1.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 7-1. The POR is activated whenever V_CCis below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

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Figure 7-2. MCU start-up, RESET tied to V_CC

.

V_POT

V_CC

RESET

V_RST

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 7-3. MCU start-up, RESET extended externally.

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

7.1.4

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see Table 7-1 on page 51) will generate a reset, even if the clock is not

running. Shorter pulses are not guaranteed to generate a reset. When the applied signal

reaches the Reset Threshold Voltage – V_RST– on its positive edge, the delay counter starts the

MCU after the Time-out period – t_TOUT– has expired.

Figure 7-4. External reset during operation.

CC

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7.1.5

Brown-out Detection

AT90PWM81/161 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as

V

_BOT+= V_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

BODLEVEL fuse coding ⁽¹⁾⁽²⁾

BODLEVEL 2..0 fuses Min V_BOT

Table 7-2.

.

Typ V_BOT

Max V_BOT

Units

111

Forbidden, BOD must be enabled

110

1.8

2.7

101 (default configuration)

100

011

010

001

000

3.9

4.3

2.3

2.2

1.9

2.0

4.6

V

2.5

2.9

Notes: 1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-Out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 010 for Low Operating Voltageand BODLEVEL = 101 for High Operating

Voltage.

2. Values are guidelines only.

Table 7-3.

Symbol

V_HYST

Brown-out characteristics ⁽¹⁾

Parameter

.

Minimum

Typical

Maximum

Units

mV

Brown-out detector hysteresis

70

2

t_BOD

Minimum pulse width on brown-out reset

µs

Notes: 1. Values are guidelines only.

When V_CCdecreases to a value below the trigger level (V_BOT-in Figure 7-5 on page 54), the

Brown-out Reset is immediately activated. When V_CCincreases above the trigger level (V_BOT+in

Figure 7-5 on page 54), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for lon-

ger than t_BODgiven in Table 7-3.

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Figure 7-5. Brown-out reset during operation.

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

7.1.6

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 56 for details on operation of the Watchdog Timer.

Figure 7-6. Watchdog reset during operation.

CC

CK

7.2

System Control registers

7.2.1

MCUSR - MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

See Bit Description

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

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• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the reset flags.

7.2.2

MCUCR - MCU Control Register

Bit

7

6

–

R

0

5

–

R

0

4

3

2

1

0

–

R

0

PUD

R/W

0

RSTDIS

R/W

0

CKRC81

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

R/W

0

• Bit 3– RSTDIS: Reset Pin Disable

Thanks to RSTDIS in MCUCR Sfr, the reset function can be disabled, leaving this pin for func-

tional purpose.

– When the RSTDIS bit is written to zero, the reset signal is active.

– When the RSTDIS bit is written to one, the reset signal is inactive.

7.3

Internal Voltage Reference

AT90PWM81/161 features an internal bandgap reference. This bandgap reference is used for

Brown-out Detection and can be used as analog input for the analog comparators or the ADC.

The internal voltage reference for the DAC and/or the ADC and the comparators is derived from

this bandgap voltage, see “On Chip voltage Reference and Temperature sensor overview” on

page 189.

The V_REFvoltage is configured thanks to the REFS1 and REFS0 bits in the ADMUX register; see

“ADMUX - ADC Multiplexer Register” on page 217.

7.3.1

Bandgap and Internal Voltage Reference Enable Signals and Start-up Time

The bandgap and the internal voltage reference characteristics is given on Table 7-4 on page

56. To save power, the reference is not always turned on. The bandgap and the internal refer-

ence is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the internal reference is selected (REFS1 = 1).

3. When the bandgap reference is connected to the Analog Comparator.

4. When the ADC is enabled.

Thus, when the BOD is not enabled, after enabling the ADC, comparator or the internal refer-

ence, the user must always allow the reference to start up before the output from the Analog

Comparator or ADC or DAC is used. To reduce power consumption in Power-down mode, the

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user can avoid the four conditions above to ensure that the reference is turned off before enter-

ing Power-down mode.

7.3.2

Voltage Reference Characteristics

Table 7-4.

Symbol

V_BG

Internal voltage reference characteristics ⁽¹⁾

.

Parameter

Condition

Minimum

Typical

Maximum

Units

Bandgap reference voltage

1.1

V

Bandgap reference start-up

time

t_BG

40

15

µs

Bandgap reference current

consumption

I_BG

µA

Note:

1. Values are guidelines only.

7.4

Watchdog Timer

AT90PWM81/161 has an Enhanced Watchdog Timer (WDT). The main features are:

• Clocked from separate On-chip Oscillator

• Three operating modes

– Interrupt

– System reset

– Interrupt and system reset

• Selectable time-out period from 1ms to 8s

• Possible hardware fuse watchdog always on (WDTON) for fail-safe mode

Figure 7-7. Watchdog timer.

128 KHz

OSCILLATOR

WDP3

MCU RESET

WDIF

INTERRUPT

WDIE

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator.

The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.

In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset

- instruction to restart the counter before the time-out value is reached. If the system doesn't

restart the counter, an interrupt or system reset will be issued.

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In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used

to wake the device from sleep-modes, and also as a general system timer. One example is to

limit the maximum time allowed for certain operations, giving an interrupt when the operation

has run longer than expected. In System Reset mode, the WDT gives a reset when the timer

expires. This is typically used to prevent system hang-up in case of runaway code. The third

mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-

rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown

by saving critical parameters before a system reset.

The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the Watchdog Timer

to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-

rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,

alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing

WDE and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)

and WDE. A logic one must be written to WDE regardless of the previous value of the

WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watch-

dog Timer. The example assumes that interrupts are controlled (for example by disabling

interrupts globally) so that no interrupts will occur during the execution of these functions.

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Assembly code example ⁽¹⁾

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

; Write logical one to WDCE and WDE

r16, MCUSR

; Keep old prescaler setting to prevent unintentional time-out

lds r16, WDTCSR

ori

r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; Turn off WDT

ldi

r16, (0<<WDE)

sts WDTCSR, r16

; Turn on global interrupt

sei

ret

C code example ⁽¹⁾

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out

condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not

set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this

situation, the application software should always clear the Watchdog System Reset Flag

(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out

value of the Watchdog Timer.

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Assembly code example ⁽¹⁾

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

lds r16, WDTCSR

ori

r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

sts WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C code example ⁽¹⁾

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change

in the WDP bits can result in a time-out when switching to a shorter time-out period.

7.4.1

WDTCSR - Watchdog Timer Control Register

Bit

7

6

5

4

3

2

1

0

WDIF

WDIE

WDP3

R/W

0

WDCE

R/W

0

WDE

R/W

X

WDP2

R/W

0

WDP1

R/W

0

WDP0

R/W

0

WDTCSR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

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• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE

and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

Table 7-5.

Watchdog timer configuration.

WDTON ⁽¹⁾

WDE

WDIE

Mode

Action on time-out

None

0

1

0

1

0

Stopped

Interrupt mode

System reset mode

Interrupt

Reset

Interrupt and system reset

mode

Interrupt, then go to system

reset mode

0

1

x

1

x

System reset mode

Reset

Note:

1. For the WDTON fuse “1” means unprogrammed while “0” means programmed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 7-6 on page 61.

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7734Q–AVR–02/12

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.

Table 7-6.

Watchdog timer prescaler select.

Number of WDT oscillator

Typical time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

4K (4096) cycles

8K (8192) cycles

16K (16384) cycles

32K (32768) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1K (1024) cycles

512 cycles

16ms

32ms

64ms

0.125s

0.25s

0.5s

1.0s

2.0s

4.0s

8.0s

8ms

4ms

256 cycles

2ms

128 cycles

1ms

Reserved

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8. Interrupts

This section describes the specifics of the interrupt handling as performed in the Atmel

AT90PWM81/161. For a general explanation of the AVR interrupt handling, refer to “Reset and

Interrupt Handling” on page 13.

8.1

Interrupt Vectors in AT90PWM81/161

Table 8-1.

Reset and interrupt vectors.

AT90PWM81

program

address

AT90PWM161

program

Vector

no.

address

Source

Interrupt definition

External pin, power-on reset, brown-out

reset, watchdog reset, and emulation

AVR reset

1

0x0000

RESET

2

3

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

PSC2 CAPT

PSC2 EC

PSC2 capture event

PSC2 end cycle

4

PSC2 EEC

PSCr CAPT

PSCr EC

PSC2 end of enhanced cycle

PSC reduced capture event

PSC reduced end cycle

PSC reduced end of enhanced cycle

Analog comparator 0

5

6

7

PSCr EEC

ANACOMP 0

ANACOMP 1

ANACOMP 2

INT0

8

9

Analog comparator 1

10

11

Analog comparator 2

External interrupt request 0

TIMER1

CAPT

12

0x000B

0x0016

Timer/Counter1 capture event

13

14

15

16

17

18

19

20

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

0x0013

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

TIMER1 OVF

ADC

Timer/Counter1 overflow

ADC conversion complete

External interrupt request 1

SPI serial transfer complete

External interrupt request 2

Watchdog time-out interrupt

EEPROM ready

INT1

SPI, STC

INT2

WDT

EE READY

SPM READY

Store program memory ready

Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at

reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 233.

2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot

flash section. The address of each interrupt vector will then be the address in this table added

to the start address of the boot flash section.

Table 8-2 on page 63 shows reset and Interrupt Vectors placement for the various combinations

of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt

Vectors are not used, and regular program code can be placed at these locations. This is also

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the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the

Boot section or vice versa.

Table 8-2.

BOOTRST

Reset and interrupt vectors placement in AT90PWM81/161 ⁽¹⁾

.

IVSEL

Reset address

0x000

Interrupt vectors start address

0x001

1

0

1

0

1

0x000

Boot reset address + 0x001

0x001

Boot reset address

Boot reset address + 0x001

Note:

1. The Boot Reset Address is shown in Table 20-7 on page 246. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

AT90PWM81 is:

(for AT90PWM161, interrupt vector address have an increment equal to 2 in place of 1 for

AT90PWM81)

Address

0x000

0x001

0x002

0x003

0x004

0x005

0x006

0x007

0x008

0x009

0x00A

0x00B

0x00C

0x00D

0x00E

0x00F

0x010

0x011

0x012

0x013

0x014

0x015

0x016

0x017

0x018

0x019

0x01A

0x01B

Labels Code

Comments

rjmp

RESET

; Reset Handler

PSC2_CAPT

PSC2_EC

PSC2_EEC

PSCR_CAPT

PSCR_EC

PSCR_EEC

ANA_COMP_0

ANA_COMP_1

ANA_COMP_2

EXT_INT0

TIM1_CAPT

TIM1_OVF

ADC

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

; PSC2 End Enhanced Cycle Handler

; PSCr Capture event Handler

; PSC0 End Cycle Handler

; PSCr End Enhanced Cycle Handler

; Analog Comparator 0 Handler

; Analog Comparator 1 Handler

; Analog Comparator 2 Handler

; IRQ0 Handler

; Timer1 Capture Handler

; Timer1 Overflow Handler

; ADC Conversion Complete Handler

; IRQ1 Handler

EXT_INT1

SPI_STC

EXT_INT2

WDT

; SPI Transfer Complete Handler

; IRQ2 Handler

; Watchdog Timer Handler

; EEPROM Ready Handler

EE_RDY

SPM_RDY

; Store Program Memory Ready Handler

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0x01C

0x01F

;

rjmp

0x020RESET:

0x021

0x022

ldi

out

ldi

r16, high(RAMEND); Main program start

SPH,r16 ; Set Stack Pointer to top of RAM

r16, low(RAMEND)

0x023

0x024

out

sei

SPL,r16

; Enable interrupts

0x025

<instr> xxx

... ...

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in AT90PWM81/161 is:

Address Labels Code

Comments

0x000

0x001

0x002

RESET: ldi

out

r16,high(RAMEND); Main program start

SPH,r16

; Set Stack Pointer to top of RAM

ldi

r16,low(RAMEND)

SPL,r16

0x003

0x004

out

sei

; Enable interrupts

0x005

;

<instr> xxx

For AT90PWM81

.org 0xC01

0xC01

rjmp

...

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

;

0xC02

...

0xC1F

rjmp

SPM_RDY

; Store Program Memory Ready Handler

For AT90PWM161

.org 0xC01

0xC02

rjmp

...

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

;

0xC04

...

0xC3F

rjmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in

AT90PWM81/161 is:

Address Labels Code

For AT90PWM81

.org 0x001

Comments

0x001

0x002

...

rjmp

...

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

;

0x01F

rjmp

SPM_RDY

; Store Program Memory Ready Handler

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AT90PWM81/161

For AT90PWM161

.org 0x001

0x002

rjmp

...

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

0x004

; PSC2 End Cycle Handler

...

;

0x03F

rjmp

SPM_RDY

; Store Program Memory Ready Handler

;

.org 0xC00

0xC00

0xC01

0xC02

RESET: ldi

r16,high(RAMEND); Main program start

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0xC03

0xC04

out

sei

; Enable interrupts

0xC05

<instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in AT90PWM81/161 is:

Address Labels Code

;

Comments

For AT90PWM81

.org 0xC00

0xC00

rjmp

...

RESET

; Reset handler

0xC01

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

;

0xC02

...

0xC1F

rjmp

SPM_RDY

; Store Program Memory Ready Handler

For AT90PWM161

.org 0xC00

0xC00

rjmp

...

RESET

; Reset handler

0xC02

0xC04

...

PSC2_CAPT

PSC2_EC

...

; PSC2 Capture event Handler

; PSC2 End Cycle Handler

;

0xC3F

;

rjmp

SPM_RDY

; Store Program Memory Ready Handler

0xC20

0xC21

0xC22

RESET: ldi

r16,high(RAMEND); Main program start

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0xC23

0xC24

out

sei

; Enable interrupts

0xC25

<instr> xxx

8.1.1

Moving Interrupts Between Application and Boot Space

The MCU Control Register controls the placement of the Interrupt Vector table.

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8.1.2

MCUCR - MCU Control Register

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

3

2

1

0

PUD

R/W

0

RSTDIS

R/W

0

CKRC81

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

R/W

0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming” on page 233 for details. To avoid unintentional changes of Interrupt Vector

tables, a special write procedure must be followed to change the IVSEL bit:

a. Write the Interrupt Vector Change Enable (IVCE) bit to one.

b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-

Write Self-Programming” on page 233 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See code example next page.

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Assembly code example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C code example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = (1<<IVSEL);

}

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9. I/O-Ports

9.1

Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. All port pins have individually selectable pull-up resistors with a supply-voltage invari-

ant resistance. All I/O pins have protection diodes to both V_CCand Ground as indicated in Figure

9-1. Refer to “Electrical Characteristics (1)” on page 265 for a complete list of parameters.

Figure 9-1. I/O pin equivalent schematic.

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description for I/O-Ports” on page 81.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

69. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 73. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

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9.2

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 9-2. General digital I/O ⁽¹⁾

.

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

WPx

WRx

RESET

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx: WRITE DDRx

RDx: READ DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

SLEEP: SLEEP CONTROL

clk_I/O: I/O CLOCK

WPx: WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

9.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 81, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin.

The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

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7734Q–AVR–02/12

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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

9.2.2

9.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 9-1 summarizes the control signals for the pin value.

Table 9-1.

Port pin configurations.

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

Comment

Default configuration after reset.

Tri-state (Hi-Z)

0

X

Input

No

0

1

0

1

0

1

Input

Yes

No

Pxn will source current if ext. pulled low

Tri-state (Hi-Z)

X

Output

Output low (Sink)

Output high (Source)

9.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 9-2 on page 69, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes

value near the edge of the internal clock, but it also introduces a delay. Figure 9-3 on page 71

shows a timing diagram of the synchronization when reading an externally applied pin value.

The maximum and minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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Figure 9-3. Synchronization when reading an externally applied pin value.

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

XXX

in r17, PINx

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows t_pd,maxand t_pd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay t_pdthrough the synchronizer is 1 system clock period.

Figure 9-4. Synchronization when reading a software assigned pin value.

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

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Assembly code example ⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17, (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB, r16

out DDRB, r17

; Insert nop for synchronization

nop

; Read port pins

in

r16, PINB

...

C code example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

9.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 9-2 on page 69, the digital input signal can be clamped to ground at the input

of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Control-

ler in Power-down mode, and Standby mode to avoid high power consumption if some input

signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 73.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned sleep modes, as the clamping in these sleep modes produces the requested

logic change.

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9.3

Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows

how the port pin control signals from the simplified Figure 9-2 on page 69 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 9-5. Alternate port functions ⁽¹⁾

.

PUOExn

PUOVxn

1

0

PUD

DDOExn

DDOVxn

1

0

Q

D

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

Pxn

Q

D

0

PORTxn

PTOExn

WPx

Q _CLR

DIEOExn

DIEOVxn

SLEEP

RESET

WRx

1

0

RRx

RPx

SYNCHRONIZER

SET

D

Q

D

L

Q

PINxn

Q

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

PUD: PULLUP DISABLE

WDx: WRITE DDRx

RDx: READ DDRx

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

RRx: READ PORTx REGISTER

WRx: WRITE PORTx

RPx: READ PORTx PIN

WPx: WRITE PINx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

clk_I/O

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

: I/O CLOCK

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

Table 9-2 on page 74 summarizes the function of the overriding signals. The pin and port

indexes from Figure 9-5 are not shown in the succeeding tables. The overriding signals are gen-

erated internally in the modules having the alternate function.

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Table 9-2.

Generic description of overriding signals for alternate functions.

Signal name

Full name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up override

enable

PUOE

PUOV

DDOE

DDOV

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up override

value

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data direction

override enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data direction

override value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port value override

enable

PVOE

Port value override

value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port toggle

override enable

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

Digital input enable

override enable

DIEOE

DIEOV

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

Digital input enable

override value

This is the Digital Input to alternate functions. In the Figure 9-5

on page 73, the signal is connected to the output of the schmitt

trigger but before the synchronizer. Unless the Digital Input is

used as a clock source, the module with the alternate function

will use its own synchronizer.

DI

Digital input

This is the Analog Input/output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

input/output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description Table 9-2

for further details.

9.3.1

MCUCR - MCU Control Register

Bit

7

6

–

R

0

5

–

R

0

4

3

2

1

0

–

R

0

PUD

R/W

0

RSTDIS

CKRC81

IVSEL

R/W

0

IVCE

R/W

0

MCUCR

Read/Write

Initial Value

RW

0

R/W

0

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• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 69 for more details about this feature.

9.3.2

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 9-3.

Table 9-3.

Port pin

Port B pins alternate functions.

Alternate functions

PSCOUT22 output

PB7

PB6

ICP1 (Timer/Counter1 Input Capture Pin )

ADC9 (Analog Input Channel 9)

MISO (SPI Master In Slave Out)

ACMP3 (Analog Comparator 3 Positive Input )

ADC8 (Analog Input Channel 8)

ADC5 (Analog Input Channel 5)

ACMP2 (Analog Comparator 2 Positive Input)

INT1(External Interrupt 1 Input)

SCK (SPI Clock)

PB5

MOSI (SPI Master Out Slave In)

PB4

PB3

ADC3 (Analog Input Channel 3)

ACMPM reference for analog comparators

PSCOUTR1 Output

ADC2 (Analog Input Channel 2)

ACMP2M (Analog Comparator 2 Negative Input)

INT0 (External Interrupt 0 Input)

PSCOUT21 output

PB2

PB1

PSCOUT20 output

T1 counter source

PB0

PSCOUT23 output

ACMP3_OUT( Analog Comparator3 Output)

The alternate pin configuration is as follows:

• PSCOUT22/ICP1/ADC9 – Bit 7

PSCOUT22: Output 2 of PSC 2

ICP1 – Input Capture Pin1: This pin can act as an input capture pin for Timer/Counter1.

ADC9: Analog to Digital Converter, input channel 9.

• MISO/ACMP3/ADC8– Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is

enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to

be an input, the pull-up can still be controlled by the PORTB6 and PUD bits.

ACMP3: Analog Comparator 3 Positive Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

ADC8: Analog to Digital Converter, input channel 8.

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• ADC5/ACMP2/INT1/SCK – Bit 5

ADC5: Analog to Digital Converter, input channel 5.

ACMP2: Analog Comparator 2 Positive Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

INT1: External Interrupt source 1. This pin can serve as an external interrupt source to the MCU.

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB5 bit.

• MOSI/ADC3/ACMPM– Bit 4

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB4 When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB4. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB4 and PUD bits.

ADC3: Analog to Digital Converter, input channel 3.

ACMPM: Analog Comparators Negative Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

• PSCOUTR1/ADC2/ACMP2M– Bit 3

PSCOUTR1: Output 1 of PSCR.

ADC2: Analog to Digital Converter, input channel 2.

ACMP2M: Analog Comparator 2 Negative Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

• INT0/PSCOUT21 – Bit 2

INT0: External Interrupt source 0. This pin can serve as an external interrupt source to the MCU.

PSCOUT21: Output 1 of PSC 2.

• PSCOUT20 – Bit 1

PSCOUT20: Output 0 of PSC 2.

• T1/PSCOUT23/ACMP3_OUT – Bit 0

T1: Timer/Counter1 counter source.

PSCOUT23: Output 3 of PSC 2.

ACMP3_OUT: Analog Comparator3 Output.

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Table 9-4 and Table 9-5 relates the alternate functions of Port B to the overriding signals shown

in Figure 9-5 on page 73.

Table 9-4.

Overriding signals for alternate functions in PB7..PB4.

Signal

name

PB7/PSCOUT22/

ICP1/ADC9

PB6/MISO/

ACMP3/ADC8

PB5/ADC5/

ACMP2/INT1/SCK

PB4/MOSI/ADC3

/ACMPM

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

SPE.MSTR

PB6.PUD

SPE.MSTR

0

SPE.MSTR

PB5.PUD

SPE.MSTR

0

SPE.MSTR

PB4.PUD

SPE.MSTR

0

PSCen22

1

PSCen22

PSCout22

ADC9D

0

SPE.MSTR

MISO

SPE.MSTR

SCK

SPE.MSTR

MOSI

ADC8D

0

ADC5D|In1en

In1en

ADC3D

0

ICP1

-

INT1

-

AIO

ADC9

ACMP3/ADC8

ADC5/ACMP2

ADC3/ACMPM

Table 9-5.

Overriding signals for alternate functions in PB3..PB0.

Signal

name

PB3/PSCOUTR1/ PB2/INT0/PSCOUT21/

PB0/T1/PSCOUT23

PB1/PSCOUT20 /ACMP3_OUT

ADC2/ACMP2M

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

PSCen01

PSCen21

1

PSCen20

PSCen23|AC3EN

1

PSCen01

PSCen21

PCOUT21

In0en

INT0

PSCen20

PSCen23|AC3EN

PSCOUTR1

PCOUT20

(1)

ADC2D

-

0

-

AIO

ADC2/ACMP2M

-

Note:

1. If PSCen23 : PSCOUT23

else

{if AC3EN : ACMP3OUT

else : Ø

}

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The alternate pin configuration is as follows:

9.3.3

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 9-6.

Table 9-6.

Port pin

Port D pins alternate functions.

Alternate function

ADC10 (Analog Input Channel 10)

PCSINrA (PSCR first Alternate Digital Input )

PD7

PD6

PD5

AMP0+ (Analog Differential Amplifier 0 Input Channel )

AMP0- (Analog Differential Amplifier 0 Input Channel )

ADC7 (Analog Input Channel 7)

ACMP3M (Analog Comparator 3 Negative Input)

ADC4 (Analog Input Channel 4)

PD4

PCSIN2A (PSC 2 Digital Input)

ADC1 (Analog Input Channel 1)

ACMP2_OUT (Analog Comparator 2 Output)

PD3

PD2

PD1

ADC0 (Analog Input Channel 0)

ACMP1 (Analog Comparator 1 Positive Input)

PSCOUTR0 Output 0

PCSINrB (PSCR Second Alternate Digital Input)

ACMP3_OUT_A (Analog Comparator 2 Alternate Output)

CLKO ( System Clock)

PD0

SS ( SPI Slave Select)

The alternate pin configuration is as follows:

• ADC10/PSCINrA – Bit 7

ADC10: Analog to Digital Converter, input channel 10.

PCSINrA: PSCR First Alternate Digital Input.

• APM0+ – Bit 6

AMP0+: Analog Differential Amplifier 0 Positive Input Channel.

• AMP0-/ADC7 – Bit 5

AMP0-: Analog Differential Amplifier 0 Negative Input Channel.

ADC7: Analog to Digital Converter, input channel 7.

• ACMP3M/ADC4/PSCIN2A – Bit 4

ACMP3M: Analog Comparator 3 Negative Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

ADC4: Analog to Digital Converter, input channel 4.

PCSIN2A: PSC 2 Alternate Digital Input.

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• ADC1/ACMP2_OUT, Bit 3

ADC1: Analog to Digital Converter, input channel 1.

ACMP2_OUT: Analog Comparator 2 Output.

• ADC0/ACMP1, Bit 2

ADC0: Analog to Digital Converter, input channel 0.

ACMP1: Analog Comparator 1 Positive Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

• PSCOUTR0/PSCINrB – Bit 1

PSCOUTR0: Output 0 of PSCR.

PCSINrB: PSCR Second Alternate Digital Input.

• ACMP3_OUT_A/SS/CLKO – Bit 0

ACMP2_OUT_A: Analog Comparator 2 Alternate Output.

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an

input regardless of the setting of DDDn. As a slave, the SPI is activated when this pin is driven

low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDDn.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTDn bit.

CLKO: Divided System Clock: The divided system clock can be output on this pin. The divided

system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTDn and

DDDn settings. It will also be output during reset.

Table 9-7 and Table 9-8 on page 80 relates the alternate functions of Port D to the overriding

signals shown in Figure 9-5 on page 73.

Table 9-7.

Overriding signals for alternate functions PD7..PD4.

PD7/ADC10/

PSCINrA

PD4/ACMP3M/

ADC4/PSCIN2A

Signal name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PD6/APM0+

PD5/AMP0-/ADC7

0

ADC10D

0

AMP0+D

ADC7D

ADC4D

0

PSCiNrA

ADC10

-

PSCIN2A

ADC4/ACMP3M

AIO

AMP0+

ADC7/AMP0-

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Table 9-8.

Overriding signals for alternate functions in PD3..PD0.

PD3/ADC1/

ACMP2_OUT

PD2/ADC0/

ACMP1

PD1/PSCOUTR0/

PSCINrB

PD0/ACMP3_OUT/SS/

CLKO

Signal name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

SPE.MSTR

0

PD0.PUD

ACE2EN

0

PSCen00

ACMP3D|(SPE.MSTR)

1

0

1

AC3EN

AC2EN

0

PSCen00

AC3EN

ACMP2_OUT

0

PSCOUT00

AVCMP3_OUT

ADC1D

ADC0D

0

-

PSCINrB

-

SS

-

AIO

ADC1

ADC0/ACMP1

9.3.4

Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 9-9.

Table 9-9.

Port pin

Port E pins alternate functions.

Alternate function

AREF (Analog reference voltage)

ADC6 (Analog input channel 6)

PE3

XTAL2: XTAL Output

PE2

ACMP1M (Analog Comparator 1 Negative Input)

PCSINr (PSCR Digital Input)

XTAL1: XTAL Input

PE1

PE0

PCSIN2 (PSC 2 Digital Input)

ACMP1_OUT (Analog Comparator 1 Output)

RESET (Reset Input)

OCD (On Chip Debug I/O)

INT2 (External Interrupt 2 Input)

The alternate pin configuration is as follows:

• AREF/ADC6, Bit 3

AREF: Analog reference voltage. See Table 17-3 on page 218 for the definition of this pin.

ADC6: Analog to Digital Converter, input channel 6.

This pin can only be used as a digital output pin. It cannot be read as a digital input.

• XTAL2/ACMP1M/PSCINr – Bit 2

XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency

crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

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ACMP1M: Analog Comparator 1 Negative Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the Ana-

log Comparator.

PCSINr: PSCR Digital Input.

• XTAL1/PSCIN2/ACMP1_OUT – Bit 1

XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC

Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

PCSIN2: PSC 2 Digital Input.

ACMP1_OUT: Analog Comparator 1 Output.

• RESET/OCD/INT2 – Bit 0

RESET: Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O

pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.

When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the

pin can not be used as an I/O pin.

If PE0 is used as a reset pin, DDE0, PORTE0 and PINE0 will all read 0.

INT2: External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU.

Table 9-10 relates the alternate functions of Port E to the overriding signals shown in Figure 9-5

on page 73.

Table 9-10. Overriding signals for alternate functions in PE2..PE0.

PE2/XTAL2/ACM

P1M/PSCINr

PE1/XTAL1/PSCI

N2/ ACMP1_OUT

PE0/RESET/OCD/

INT2

Signal name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PE3/AREF/ADC6

0

AC1EN

0

1

0

AC1EN

0

ACMP1_OUT

0

ACMP1MD

0

In2en

INT2

-

0

-

PSCINr

ACMP1M

PSCIN2

-

AIO

ADC6

9.4

Register Description for I/O-Ports

9.4.1

PORTB - Port B Data Register

Bit

7

6

5

4

3

2

1

0

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

PORTB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.4.9

DDRB - Port B Data Direction Register

Bit

7

6

5

4

3

2

1

0

DDB7

R/W

0

DDB6

R/W

0

DDB5

R/W

0

DDB4

R/W

0

DDB3

R/W

0

DDB2

R/W

0

DDB1

R/W

0

DDB0

R/W

0

DDRB

Read/Write

Initial Value

PINB - Port B Input Pins Address

Bit

7

6

5

4

3

2

1

0

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

PINB

Read/Write

Initial Value

PORTD - Port D Data Register

Bit

7

6

5

4

3

2

1

0

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

PORTD

DDRD

PIND

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DDRD - Port D Data Direction RegisterS

Bit

7

6

5

4

3

2

1

0

DDD7

R/W

0

DDD6

R/W

0

DDD5

R/W

0

DDD4

R/W

0

DDD3

R/W

0

DDD2

R/W

0

DDD1

R/W

0

DDD0

R/W

0

Read/Write

Initial Value

PIND - Port D Input Pins Address

Bit

7

6

5

4

3

2

1

0

PIND7

R/W

N/A

PIND6

R/W

N/A

PIND5

R/W

N/A

PIND4

R/W

N/A

PIND3

R/W

N/A

PIND2

R/W

N/A

PIND1

R/W

N/A

PIND0

R/W

N/A

Read/Write

Initial Value

PORTE - Port E Data Register

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

1

0

PORTE2

PORTE1

PORTE0

PORTE

DDRE

PINE

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

DDRE - Port E Data Direction Register

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

1

0

DDE2

R/W

0

DDE1

R/W

0

DDE0

R/W

0

Read/Write

Initial Value

PINE - Port E Input Pins Address

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

–

R

0

2

1

0

PINE2

R/W

N/A

PINE1

R/W

N/A

PINE0

R/W

N/A

Read/Write

Initial Value

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10. External Interrupts

The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts

will trigger even if the INT2:0 pins are configured as outputs. This feature provides a way of gen-

erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or

a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-

isters – EICRA (INT2:0). When the external interrupt is enabled and is configured as level

triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or

rising edge interrupts on INT2:0 requires the presence of an I/O clock, described in “Clock Sys-

tems and their Distribution” on page 27. The I/O clock is halted in all sleep modes except Idle

mode.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. This makes the MCU less sensitive to

noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the

Watchdog Oscillator is 1µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-

tor is voltage dependent as shown in the “Electrical Characteristics (1)” on page 265. The MCU

will wake up if the input has the required level during this sampling or if it is held until the end of

the start-up time. The start-up time is defined by the SUT fuses as described in “System Clock

and Clock Options” on page 27. If the level is sampled twice by the Watchdog Oscillator clock

but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will

be generated. The required level must be held long enough for the MCU to complete the wake

up to trigger the level interrupt.

10.0.1

EICRA - External Interrupt Control Register A

Bit

7

6

5

4

3

2

1

0

-

ISC21

R/W

0

ISC20

R/W

0

ISC11

R/W

0

ISC10

R/W

0

ISC01

R/W

0

ISC00

R/W

0

EICRA

Read/Write

Initial Value

R

0

R

0

• Bits 7..0 – ISC21, ISC20 – ISC01, ISC00: External Interrupt 2 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 10-1. Edges on INT3..INT0 are registered asynchro-

nously.The value on the INT2:0 pins are sampled before detecting edges. If edge or toggle

interrupt is selected, pulses that last longer than one clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency

can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is

selected, the low level must be held until the completion of the currently executing instruction to

generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as

long as the pin is held low.

Table 10-1.

Interrupt sense Ccntrol ⁽¹⁾

ISCn0 Description

.

ISCn1

0

1

0

1

0

1

The low level of INTn generates an interrupt request

Any logical change on INTn generates an interrupt request

The falling edge between two samples of INTn generates an interrupt request

The rising edge between two samples of INTn generates an interrupt request

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Note:

1. n = 3, 2, 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK register. Otherwise an interrupt can occur when the bits are changed.

10.0.2

EIMSK - External Interrupt Mask Register

Bit

7

6

5

4

3

2

1

0

-

INT2

R/W

0

INT1

R/W

0

IINT0

R/W

0

EIMSK

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 2..0 – INT2 – INT0: External Interrupt Request 3 - 0 Enable

When an INT2 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Register – EICRA – defines whether the external interrupt is activated

on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software

interrupt.

10.0.3

EIFR - External Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

-

INTF2

R/W

0

INTF1

R/W

0

IINTF0

R/W

0

EIFR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 2..0 – INTF2 - INTF0: External Interrupt Flags 3 - 0

When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT2:0 are configured as level interrupt.

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11. Reduced 16-bit Timer/Counter1

The 16-bit Timer/Counter unit allows accurate program execution timing (event management).

The main features are:

• Clear timer on compare match (auto reload)

• One input capture unit

• Input capture noise canceler

• External event counter

• Two independent interrupt sources (TOV1, ICF1)

11.1 Overview

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a program, the precise form must be

used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 11-1 on page 86. For

the actual placement of I/O pins, refer to Table 2-2 on page 6. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “16-bit Timer/Counter Register Description” on page 97.

The PRTIM1 bit in “Power Reduction Register” on page 46 must be written to zero to enable

Timer/Counter1 module.

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Figure 11-1. 16-bit timer/counter block diagram ⁽¹⁾

.

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

(Ckio )

Timer/Counter

TCNTn

=

= 0

Fixed

TOP

Values

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICPn

ICRn

AC1ICE

TCCRnB

Note:

1. Refer to Table 2-1 on page 5 for Timer/Counter1 pin placement and description.

11.1.1

Registers

The Timer/Counter (TCNT1), and Input Capture Register (ICR1) are all 16-bit registers. Special

procedures must be followed when accessing the 16-bit registers. These procedures are

described in the section “Accessing 16-bit Registers” on page 87. The Timer/Counter Control

Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt

requests (abbreviated to Int.Req. in Figure 11-1) signals are all visible in the Timer Interrupt Flag

Register (TIFR1). All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK1). TIFR1 and TIMSK1 are not shown in Figure 11-1.

The Timer/Counter can be clocked internally, or by an external clock source on the T1 pin. The

Clock Select logic block controls which clock source and edge the Timer/Counter uses to incre-

ment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected.

The output from the Clock Select logic is referred to as the timer clock (clk ).

1

T

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICP1). The Input Capture unit includes a digital

filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

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The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by the ICR1 Register, or by a set of fixed values.

11.1.2

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x0000.

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the ICR1 Register. The assignment is dependent of

the mode of operation.

TOP

11.2 Accessing 16-bit Registers

The TCNT1, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit

data bus. The 16-bit register must be byte accessed using two read or write operations. Each

16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access.

The same temporary register is shared between all 16-bit registers within each 16-bit timer.

Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit

register is written by the CPU, the high byte stored in the temporary register, and the low byte

written are both copied into the 16-bit register in the same clock cycle. When the low byte of a

16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary

register in the same clock cycle as the low byte is read.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.

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Assembly code examples ⁽¹⁾

...

; Set TCNT1 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNT1H,r17

outTCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C code examples ⁽¹⁾

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

the main code and the interrupt code update the temporary register, the main code must disable

the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT1 Register contents.

Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly code example ⁽¹⁾

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

outSREG,r18

ret

C code example ⁽¹⁾

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT1 Register contents.

Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly code example ⁽¹⁾

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

outTCNT1H,r17

outTCNT1L,r16

; Restore global interrupt flag

outSREG,r18

ret

C code example ⁽¹⁾

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

11.2.1

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

11.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits

located in the Timer/Counter control Register B (TCCR1B).

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11.3.1

External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk_T1/clk_T0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-2

shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector

logic. The registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch

is transparent in the high period of the internal system clock.

The edge detector generates one clk_T1/clk_Tpulse for each positive (CSn2:0 = 7) or negative

0

(CSn2:0 = 6) edge it detects.

Figure 11-2. T1/T0 pin sampling.

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

11.4 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 11-3 shows a block diagram of the counter and its surroundings.

Figure 11-3. Counter unit block diagram.

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Clear

Edge

Detector

Tn

TCNTnH (8-bit)

TCNTnL (8-bit)

clk_Tn

Control Logic

TCNTn (16-bit Counter)

( Ckio )

TOP

BOTTOM

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Signal description (internal signals):

Count

Clear

Increment TCNT1 by 1.

Clear TCNT1 (set all bits to zero).

Timer/Counter clock.

clk_T

1

TOP

Signalize that TCNT1 has reached maximum value.

BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-

taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight

bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNT1H value when the TCNT1L is read, and

TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk ). The clk ₁can be generated from an external or internal clock source,

1

T

selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the

timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of

whether clk_Tis present or not. A CPU write overrides (has priority over) all counter clear or

1

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bit

(WGM13) located in the Timer/Counter Control Registers B ( TCCR1B).

The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by

the WGM13 bit. TOV1 can be used for generating a CPU interrupt.

11.5 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 11-4 on page 93. The

elements of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n” in register and bit names indicates the Timer/Counter number.

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Figure 11-4. Input capture unit block diagram.

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ICNC

ICES

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPnA

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at

the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),

the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically

cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software

by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low

byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied

into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will

access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes

the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-

tion mode (WGM13) bits must be set before the TOP value can be written to the ICR1 Register.

When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before

the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 87.

11.5.1

Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture (AC1ICE) bit in the Analog Comparator Extended Control Register

(AC1ECON). Be aware that changing trigger source can trigger a capture. The Input Capture

Flag must therefore be cleared after the change.

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Both the Input Capture pin (ICP1) and the Analog Comparator 1 output (AC1O) inputs are sam-

pled using the same technique as for the T1 pin (see Figure 11-2 on page 91). The edge

detector is also identical. However, when the noise canceler is enabled, additional logic is

inserted before the edge detector, which increases the delay by four system clock cycles. Note

that the input of the noise canceler and edge detector is always enabled unless the Timer/Coun-

ter is set in a Waveform Generation mode that uses ICR1 to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

11.5.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in

Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

11.5.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICR1

Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICF1 Flag is not required (if an interrupt handler is used).

11.6 Modes of Operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,

is defined by the Waveform Generation mode (WGM1).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 95.

11.6.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in

the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

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interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt must be used to extend the resolution

for the capture unit.

11.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM13 = 1, previous mode 12), the ICR1 Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT1) matches the ICR1 . The ICR1 define the top value for the counter,

hence also its resolution. This mode allows greater control of the compare match output fre-

quency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 11-5. The counter value (TCNT1)

increases until a compare match occurs with ICR1, and then counter (TCNT1) is cleared.

Figure 11-5. CTC mode, timing diagram.

ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

An interrupt can be generated at each time the counter value reaches the TOP value by using

the ICF1 Flag . If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is

running with none or a low prescaler value must be done with care since the CTC mode does

not have the double buffering feature. If the new value written to ICR1 is lower than the current

value of TCNT1, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can

occur. In many cases this feature is not desirable.

As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

11.7 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set.

Figure 11-6 on page 96 shows the count sequence close to TOP in various modes.

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Figure 11-6. Timer/counter timing diagram, no prescaling.

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

ICFn

Figure 11-7 shows the count sequence close to MAX in various modes.

Figure 11-7. Timer/counter timing diagram, no prescaling.

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

BOTTOM

BOTTOM + 1

MAX-1

MAX

TOVn

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11.8 16-bit Timer/Counter Register Description

11.8.1

TCCR1B - Timer/Counter1 Control Register B

Bit

7

6

5

-

4

3

-

2

1

0

ICNC1

R/W

0

ICES1

R/W

0

WGM13

R/W

0

CS12

R/W

0

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial Value

R

0

R

0

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four

successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved

• Bit 4 – WGM13: Waveform Generation Mode

See Table 11-1 for the modes definition

Table 11-1. Waveform generation mode bit description.

Timer/counter mode of

operation

TOV1 flag

set on

Mode

0

WGM13

TOP

0

1

Normal

CTC

0xFFFF

ICR1

MAX

12

• Bit 3 – Reserved

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Table 11-2.

Table 11-2. Clock select bit description.

CS12

CS11

CS10

Description

0

1

0

1

0

No clock source (Timer/Counter stopped)

clkI/O/1 (No prescaling)

Reserved

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Table 11-2. Clock select bit description. (Continued)

CS12

CS11

CS10

Description

Reserved

0

1

0

1

0

1

0

1

External clock source on T1 pin. Clock on falling edge

External clock source on T1 pin. Clock on rising edge

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

11.8.2

TCNT1H and TCNT1L - Timer/Counter1

Bit

7

6

5

4

3

2

1

0

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 87.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-

pare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock

for all compare units.

11.8.3

ICR1H and ICR1L - Input Capture Register 1

Bit

7

6

5

4

3

2

1

0

ICR1[15:8]

ICR1[7:0]

R/W

ICR1H

ICR1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 87.

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11.8.4

TIMSK1 - Timer/Counter1 Interrupt Mask Register

Bit

7

–

R

0

6

–

R

0

5

4

–

R

0

3

–

R

0

2

1

0

ICIE1

R/W

0

–

TOIE1

R/W

0

TIMSK1

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the AT90PWM81/161, and will always read as zero.

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see Table 8-1 on page 62) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 4, 3, 2,1 – Res: Reserved Bits

These bits are unused bits in the AT90PWM81/161, and will always read as zero.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(see Table 8-1 on page 62) is executed when the TOV1 Flag, located in TIFR1, is set.

11.8.5

TIFR1 - Timer/Counter1 Interrupt Flag Register

Bit

7

6

5

4

–

R

0

3

–

R

0

2

1

0

–

ICF1

R/W

0

–

TOV1

R/W

0

TIFR1

Read/Write

Initial Value

R

0

R

0

R/W

0

R/W

0

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the AT90PWM81/161, and will always read as zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the coun-

ter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4, 3, 2,1 – Res: Reserved Bits

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WG.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

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12. Power Stage Controller – (PSCn)

The Power Stage Controller is a high performance waveform controller.

The Atmel AT90PWM81 includes one PSC2 block.

12.1 Features

• PWM waveform generation function (two complementary programmable outputs)

• Dead time control

• Standard mode up to 12 bit resolution

• Frequency and pulse width resolution enhancement mode (12 + 4 bits)

• Frequency up to 64Mhz

• Conditional waveform on external events (zero crossing, current sensing ...)

• All on chip PSC synchronization

• ADC synchronization with digital delay register

• Input blanking

• Overload protection function

• Abnormality protection function, emergency input to force all outputs to low level

• Center aligned and edge aligned modes synchronization

• Fast emergency stop by hardware

12.2 Overview

Many register and bit references in this section are written in general form.

• A lower case “n” replaces the PSC number, in this case 2. However, when using the register

or bit defines in a program, the precise form must be used, that is, PSOC2 for accessing PSC

2 Synchro and Output Configuration register and so on.

• A lower case “x” replaces the PSC part , in this case A or B. However, when using the register

or bit defines in a program, the precise form must be used, that is, PFRC2A for accessing

PSC n Fault/Retrigger 2 A Control register and so on.

The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has

two outputs on PSCn and four outputs on PSC2.

These outputs can be used in various ways:

• “Two Outputs” to drive a half bridge (lighting, DC motor ...)

• “One Output” to drive single power transistor (DC/DC converter, PFC, DC motor ...)

• “Four Outputs” in the case of PSC2 to drive a full bridge (lighting, DC motor ...)

Each PSC has two inputs the purpose of which is to provide means to act directly on the gener-

ated waveforms:

• Current sensing regulation

• Zero crossing retriggering

• Demagnetization retriggering

• Fault input

The PSC can be chained and synchronized to provide a configuration to drive three half bridges.

Thanks to this feature it is possible to generate a three phase waveforms for applications such

as Asynchronous or BLDC motor drive.

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12.3 PSC Description

Figure 12-1. Power Stage Controller 0 or 1 block diagram.

PSC Counter

Waveform

Generator B

PSCOUTn1

=

OCRnRB

PSC Input

Module B

PSCn Input B

=

OCRnSB

Par t B

PSC Input

Module A

PSCn Input A

=

OCRnRA

PSCOUTn0

Waveform

Generator A

=

OCRnSA

Par t A

PICRn

PCNFEn

PCNFn

PASDLYn

PFRCnB

PFRCnA

PCTLn

PSOCn

Note:

n = 0, 1.

The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to

count up and count down from and to values stored in registers according to the selected run-

ning mode.

The PSC is seen as two symmetrical entities. One part named part A which generates the output

PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output.

Each part A or B has its own PSC Input Module to manage selected input.

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12.3.1

PSC2 Distinctive Feature

Figure 12-2. PSC2 versus PSC1&PSC0 block diagram.

PSC Counter

PSCOUTn3

PSCOUTn1

POS23

Waveform

Generator B

=

OCRnRB

PSC Input

Module B

PSCn Input B

=

OCRnSB

Output

Matrix

Part A

PSC Input

Module A

=

PSCn Input A

OCRnRA

PSCOUTn2

PSCOUTn0

POS22

Waveform

Generator A

=

OCRnSA

Part B

PICRn

PCNFEn

PCNFn

PASDLYn

PFRCnB

PFRCnA

POM2(PSC2 only)

PSOCn

PCTLn

Note:

n = 2.

PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector

PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23

can duplicate PSCOUT20 or PSCOUT21.

The Output Matrix is a kind of 2 × 2 look up table which gives the possibility to program the out-

put values according to a PSC sequence (see “Output Matrix” on page 129).

12.3.2

Output Polarity

The polarity “active high” or “active low” of the PSC outputs is programmable. All the timing dia-

grams in the following examples are given in the “active high” polarity.

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12.4 Signal Description

Figure 12-3. PSC external block view.

CLK

PLL

CLK

I/O

SYnIn

StopOut

12

4

OCRnRB[11:0]

OCRnSB[11:0]

OCRnRA[11:0]

OCRnSA[11:0]

OCRnRB[15:12]

PSCOUTn0

PSCOUTn1

PSCOUTn2

PSCOUTn3

(1)

(Flank Width

Modulation)

12

2

PICRn[11:0]

PSCINn

IRQ PSCn

Analog

Comparator

n Output

StopIn SYnOut PSCnASY

Note:

1. available only for PSC2.

2. n = 0, 1 or 2.

12.4.1

Input Description

Table 12-1. Internal inputs.

Name

Description

Type width

Register 12 bits

OCRnRB[11:0]

OCRnSB[11:0]

OCRnRA[11:0]

OCRnSA[11:0]

Compare value which reset signal on Part B (PSCOUTn1)

Compare value which set signal on Part B (PSCOUTn1)

Compare value which reset signal on Part A (PSCOUTn0)

Compare value which set signal on Part A (PSCOUTn0)

Frequency resolution enhancement value (flank width

modulation)

OCRnRB[15:12]

Register 4 bits

CLK I/O

CLK PLL

SYnIn

Clock input from I/O clock

Signal

Clock input from PLL

Synchronization in (from adjacent PSC) ⁽¹⁾

StopIn

Stop input (for synchronized mode)

Note:

1. See Figure 12-41 on page 132

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Table 12-2. Block inputs.

Name Description

PSCINn

Type width

Signal

Input 0 used for Retrigger or Fault functions

Input 1 used for Retrigger or Fault functions

Input 2 used for Retrigger or Fault functions

Input 3 used for Retrigger or Fault functions

from 1st A C

PSCINnA

Signal

from 2nd A C

Signal

12.4.2

Output Description

Table 12-3. Block outputs.

Name

PSCOUTn0

PSCOUTn1

Description

Type width

Signal

PSC n Output 0 (from part A of PSC)

PSC n Output 1 (from part B of PSC)

Signal

PSCOUTn2

(PSC2 only)

PSC n Output 2 (from part A or part B of PSC)

PSC n Output 3 (from part A or part B of PSC)

Signal

PSCOUTn3

(PSC2 only)

Table 12-4. Internal outputs.

Name Description

SYnOut

Type width

Signal

Synchronization Output ⁽¹⁾

PICRn

[11:0]

PSC n Input Capture Register

Counter value at retriggering event

Register

12 bits

PSC Interrupt Request : three sources, overflow, fault, and

input capture

IRQPSCn

Signal

PSCnASY

StopOut

ADC Synchronization (+ Amplifier Syncho.) ⁽²⁾

Stop Output (for synchronized mode)

Note:

1. See Figure 12-41 on page 132

2. See “Analog Synchronization” on page 131

12.5 Functional Description

12.5.1

Waveform Cycles

The waveform generated by PSC can be described as a sequence of two waveforms.

The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform

is sub-cycle A in Figure 12-4 on page 105.

The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this wave-

form is sub-cycle B in Figure 12-4 on page 105.

The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform

B.

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Figure 12-4. Cycle presentation in 1, 2, and 4 ramp mode.

PSC Cycle

Sub-Cycle A

Sub-Cycle B

4 Ramp Mode

Ramp A0

Ramp A1

Ramp B0

Ramp B1

2 Ramp Mode

Ramp A

Ramp B

1 Ramp Mode

UPDATE

Figure 12-5. Cycle presentation in centered mode.

PSC Cycle

Centered Mode

UPDATE

Ramps illustrate the output of the PSC counter included in the waveform generators. Centered

Mode is like a one ramp mode which count down up and down.

Notice that the update of a new set of values is done regardless of ramp Mode at the top of the

last ramp.

12.5.2

Running Mode Description

Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1,

OT1) and by the running mode. Four modes are possible:

– Four Ramp mode

– Two Ramp mode

– One Ramp mode

– Center Aligned mode

12.5.2.1

Four Ramp Mode

In Four Ramp mode, each time in a cycle has its own definition.

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Figure 12-6. PSCn0 & PSCn1 basic waveforms in Four Ramp mode.

OCRnRA

PSC Counter

OCRnSA

OCRnRB

OCRnSB

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

The input clock of PSC is given by CLKPSC.

PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and

Dead-Time 1 values with:

On-Time 0 = OCRnRAH/L × 1/Fclkpsc

On-Time 1 = OCRnRBH/L × 1/Fclkpsc

Dead-Time 0 = (OCRnSAH/L + 2) × 1/Fclkpsc

Dead-Time 1 = (OCRnSBH/L + 2) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 and Dead-Time 1 = 2 × 1/Fclkpsc.

12.5.2.2

Two Ramp Mode

In Two Ramp mode, the whole cycle is divided in two moments:

One moment for PSCn0 description with OT0 which gives the time of the whole moment.

One moment for PSCn1 description with OT1 which gives the time of the whole moment.

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Figure 12-7. PSCn0 & PSCn1 basic waveforms in Two Ramp mode.

OCRnRA

OCRnRB

PSC Counter

OCRnSA

OCRnSB

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and

Dead-Time 1 values with:

On-Time 0 = (OCRnRAH/L - OCRnSAH/L) × 1/Fclkpsc

On-Time 1 = (OCRnRBH/L - OCRnSBH/L) × 1/Fclkpsc

Dead-Time 0 = (OCRnSAH/L + 1) × 1/Fclkpsc

Dead-Time 1 = (OCRnSBH/L + 1) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc.

12.5.2.3

One Ramp Mode

In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other.

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Figure 12-8. PSCn0 & PSCn1 basic waveforms in One Ramp mode.

OCRnRB

OCRnSB

OCRnRA

PSC Counter

OCRnSA

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

On-Time 0 = (OCRnRAH/L - OCRnSAH/L) × 1/Fclkpsc

On-Time 1 = (OCRnRBH/L - OCRnSBH/L) × 1/Fclkpsc

Dead-Time 0 = (OCRnSAH/L + 1) × 1/Fclkpsc

Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 = 1/Fclkpsc.

12.5.2.4

Center Aligned Mode

In center aligned mode, the center of PSCn00 and PSCn01 signals are centered.

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Figure 12-9. PSCn0 & PSCn1 basic waveforms in Center Aligned mode.

PSC Counter

OCRnRB

OCRnSB

OCRnSA

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time

PSC Cycle

On-Time 0 = 2 × OCRnSAH/L × 1/Fclkpsc

On-Time 1 = 2 × (OCRnRBH/L - OCRnSBH/L + 1) × 1/Fclkpsc

Dead-Time = (OCRnSBH/L - OCRnSAH/L) × 1/Fclkpsc

PSC Cycle = 2 × (OCRnRBH/L + 1) × 1/Fclkpsc

Note:

Minimal value for PSC Cycle = 2 × 1/Fclkpsc.

OCRnRAH/L is not used to control PSC Output waveform timing. Nevertheless, it can be useful

to adjust ADC synchronization (see “Analog Synchronization” on page 131).

Figure 12-10. Run and stop mechanism in Centered mode.

OCRnRB

OCRnSB

OCRnSA

PSC Counter

0

Run

PSCOUTn0

PSCOUTn1

Note:

See “PCTL2 - PSC 2 Control Register” on page 140 (or PCTL1 or PCTL2).

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12.5.3

Fifty Percent Waveform Configuration

When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the

PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRn-

SBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not

necessary to program OCRnSAH/L and OCRnRAH/L registers.

12.6 Update of Values

The update of PSC waveform registers are done in the following way:

• Immediately when the PSC is stopped

• At the PSC end of cycle when the PSC is running

• At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes

are used

To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is

necessary, all values can be updated at the same time at the end of the cycle by the PSC. The

new set of values is calculated by software and the update is initiated by software.

Figure 12-11. Update at the end of complete PSC cycle.

Regulation Loop

Calculation

Writting in

PSC Registers

Request for

an Update

Software

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

PSC

Cycle

With Set j

End of Cycle

The software can stop the cycle before the end to update the values and restart a new PSC

cycle.

12.6.1

Value Update Synchronization

New timing values or PSC output configuration can be written during the PSC cycle. Thanks to

LOCK and AUTOLOCK configuration bits, the new whole set of values can be taken into

account with the following conditions:

• When AUTOLOCK configuration is selected, the update of the PSC internal registers will be

done at the end of the PSC cycle following a write in the Output Compare Register RB. The

AUTOLOCK configuration bit is taken into account at the end of the first PSC cycle.

• When LOCK configuration bit is set, there is no update. The update of the PSC internal

registers will be done at the end of the PSC cycle if the LOCK bit is released to zero.

The registers which update is synchronized thanks to LOCK and AUTOLOCK are PSOCn,

POM2, OCRnSAH/L, OCRnRAH/L, OCRnSBH/L and OCRnRBH/L.

See these register’s description starting on page 135.

When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.

See “PCNF2 - PSC 2 Configuration Register” on page 136.

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12.7 Enhanced Resolution

Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve

the normal resolution is based on Flank Width Modulation (also called Fractional Divider).

Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the

fractional divider number. The resulting output frequency is the average of the frequencies in the

frame. The fractional divider (d) is given by OCRnRB[15:12].

The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0)

and PSCOUTn1 On Time + Dead Time (OT1+DT1) values. These values are 12 bits numbers.

The frequency adjustment can only be done in steps like the dedicated counters. The step width

is defined as the frequency difference between two neighboring PSC frequencies.

It is possible to apply the Flank Width Modulation (FWM) on RB, RB+RA, SB, SB+SA. The

selection is done bit the bits PBFMn0 and PBFMn.

According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the fre-

quency difference Df can take three different values:

Δf = 0

f_PSCf_PSC

Δf1 = f1 – f2 = ---------- – ----------- = f_PSC

k + 1

1

-------------------

×

k(k + 1)

k

f_PSCf_PSC

Δf2 = f1 – f2 = ---------- – ----------- = f_PSC

k + 2

2

-------------------

k(k + 2)

k

with k is the number of CLK_PSCperiod in a PSC cycle and is given by the following formula:

f_PSC

k = ----------

f_OP

with f_OPis the output operating frequency.

Example, in normal mode, with maximum operating frequency 160kHz and f_PLL= 64Mhz, k

equals 400. The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400Hz.

In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu-

tive cycles.

f_b1and f_b2are two neighboring base frequencies.

16 – d

16

d

16

--------------

-----

f_AVERAGE

=

× f_b1

+

× f_b2

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Then the frequency resolution is divided by 16. In the example above, the resolution equals

25Hz.

f_PLL

16 – d

16

d

-------------- ---------- ----- -----------

f_AVERAGE

=

×

+

×

k

16 k + 1

According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the

average frequency deviation Df can take three different values:

Δf(average) = 0

d

-------------------------

Δf1(average) = f_PSC

×

16k(k + 1)

d

----------------------

Δf2(average) = f_PSC

×

8k(k + 2)

These values are applied according to the running mode and the enhanced resolution mode as

per Table 12-5;

It must be noted that, in one and two ramps modes, it is possible to apply the FWM only on

pulse width while keeping a constant frequency.

Table 12-5. Frequency deviation with Flank Width Modulation.

PBFMn1:0

00

01

RB+RA

Df2

10

SB

Df1

0 ⁽¹⁾

0

11

SB+SA

Df2

0

Running mode

Four Ramps

RB

Df1

Df2

Two Ramps

One Ramp

Df2

Df1

0

Center aligned

Df2

Notes: 1. The modulation is on the pulse width.

12.7.1

Frequency distribution

The frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame.

These two frequencies are f_b1and f_b2where f_b1is the nearest base frequency above the wanted

frequency and f_b2is the nearest base frequency below the wanted frequency. The number of f_b1

in the frame is (d-16) and the number of f_b2is d. The f_b1and f_b2frequencies are evenly distrib-

uted in the frame according to a predefined pattern. This pattern can be as given in the following

table or by any other implementation which give an equivalent evenly distribution.

At the end of the 15th cycle (numbered 14 on Table 12-6 on page 113) an interrupt can be gen-

erated. This is the case if the bit PEOEPEn (PSC n End Of Enhanced Cycle Interrupt Enable) is

set. This allows:

• To modify the modulation only on a new enhanced cycle start

• To extend the enhanced modulation accuracy by software

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Table 12-6. Distribution of f_b2in the modulated frame.

Distribution of fb2 in the modulated frame

PWM - cycle

Fractional

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

divider (d)

0

1

X

2

X

3

X

4

X

5

X

6

X

7

X

8

X

9

X

10

11

12

13

14

15

X

While ‘X’ in the table, f_b2prime to f_b1in cycle corresponding cycle.

So for each row, a number of fb2 take place of fb1.

Figure 12-12. Resulting frequency versus d.

f

b2

b1

0

f_OP

d:

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

12.7.2

Modes of Operation

12.7.2.1

Normal Mode

The simplest mode of operation is the normal mode. See Figure 12-6 on page 106.

The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given

by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time

between PSCOUTn0 and PSCOUTn1 active signals.

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The waveform frequency is defined by the following equation:

f

1

CLK_PSCn

f

= ----------------------------- = --------------------------------------------------------------------

PSCn

PSCnCycle

(OT0 + OT1 + DT0 + DT1)

12.7.2.2

Enhanced Mode

The Enhanced Mode uses the previously described method to generate a high resolution fre-

quency. Figure 12-13 gives an example of FWM with PBFMn1:0 = 00.

Figure 12-13. Enhanced mode, timing diagram.

DT1

DT0

OT0

DT1

OT1

DT0

OT1+1

OT0

PSCOUTn0

PSCOUTn1

Period

T2

T1

The supplementary step in counting to generate f_b2is added on the PSCn0 signal while needed

in the frame according to the fractional divider. See Table 12-6 on page 113.

The waveform frequency is defined by the following equations:

f

1

CLK_PSCn

f1

= ----- = --------------------------------------------------------------------

PSCn

T

(OT0 + OT1 + DT0 + DT1)

1

f

1

CLK_PSCn

f2

= ----- = ------------------------------------------------------------------------------

PSCn

T

(OT0 + OT1 + DT0 + DT1 + 1)

2

d

16

16 – d

16

-----

--------------

f_AVERAGE

=

× f1_PSCn

+

× f2_PSCn

d is the fractional divider factor.

The FWM can be applied on different locations within the PSC output waveforms as defined per

Table 12-15 on page 138.

12.8 PSC Inputs

Part A or B of PSC has its own system to take into account one PSC n internal input. Each part

A or B is configured by the PSC n Input A/B Control Register (“PFRCnA - PSC n Input A Control

Register” on page 141 and “PFRCnB - PSC n Input B Control Register” on page 141) and the

PSC n Extended Configuration Register (see Section “PCNF2 - PSC 2 Configuration Register”,

page 136).

The PSC input module A is shown in Table 12-14 on page 115.

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According to PSC n Input A Control Register (see “PFRCnA - PSC n Input A Control Register”

on page 141), PSC n input A can act as a Retrigger or Fault input.

Each part A or B can be triggered by up to four signals as defined per Table 12-18 on page 139

and Table 12-19 on page 139.

Part A of PSC has also a blanking module allowing to cancel unwanted transitions which may

appear on the PSC n input A during a certain period of time.

The blanking start is defined by the bits PASDLKn(2:0) as per Table 12-14 on page 138.

The blanking duration is defined by the register PASDLYn. If the blanking is selected by the cor-

responding PASDLKn(2:0) bit, all transitions which may appears from the blanking start until a

time period are ignored.

Blanking is level sensitive, that is, a pulse started in the blanking window and still at active level

after the window will generate a valid retriggering event.

Figure 12-14. PSC input module A.

PAOCnA

Input

Blanking

0

PSCINn

0

AC2O: Analog

Comparator

Output

PSC n Input A

0

1

0

Digital

Filter

1

PSCINnA

AC3O: Analog

Comparator

Output

PFLTEnA

1

PISELnA1 PISELnA0

CLK

PSC

PASDLY

OCR SB

OSR SA

3

2

1

Blanking Start

PSC start

cycle

Input

Processing

(retriggering ...)

PCAEnA

=0, 4..7

No Blanking

PASDLKn(2:0)

4

PRFMnA3:0

PELEVnA /

PSC Core

(Counter,

Waveform

Generator, ...)

Output

Control

PSCOUTn0

(PSCOUTn1)

(PSCOUT22)

(PSCOUT23)

CLK

PSC

PSC input module B is shown on Table 12-15 on page 116.

According to PSC n Input B Control Register (see “PFRCnB - PSC n Input B Control Register”

on page 141), PSC n input B can act as a Retrigger or Fault input.

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Figure 12-15. PSC input module B.

PAOCnB

0

PSCINn

AC2O: Analog

Comparator

Output

0

1

0

PSC n Input B

Digital

Filter

1

PSCINnA

PFLTEnB

CLK

PSC

AC3O:Analog

Comparator

Output

1

PCAEnB

Input

PELEVnB

Processing

(retriggering ...)

4

PISELnB1 PISELnB0

PRFMnB3:0

CLK

PSC

PSC Core

(Counter,

Waveform

Generator, ...)

Output

Control

PSCOUTn0

(PSCOUTn1)

(PSCOUT22)

(PSCOUT23)

CLK

PSC

12.8.1

12.8.2

PSC Retrigger Behavior versus PSC running modes

In centered mode, Retrigger Inputs have no effect.

In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding

cycle A or B and the beginning of the following cycle B or A.

In one ramp mode, Retrigger Inputs A or B reset the current PSC counting to zero.

Retrigger PSCOUTn0 On External Event

PSCOUTn0 output can be reset before end of On-Time 0 on the change on PSCn Input A.

PSCn Input A can be configured to do not act or to act on level or edge modes. The polarity of

PSCn Input A is configurable thanks to a sense control block. PSCn Input A can be the Output of

the analog comparator or the PSCINn input.

As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.

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Figure 12-16. PSCOUTn0 retrograde by PSCn Input A (edge retriggering).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input A

(falling edge)

PSCn Input A

(rising edge)

Dead-Time 0

Dead-Time 1

Note:

This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 12-33 on page 126 for

details.

Figure 12-17. PSCOUTn0 retriggered by PSCn Input A (level acting).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input A

(high level)

PSCn Input A

(low level)

Dead-Time 0

Dead-Time 1

Note:

This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 12-22 on page 121 for

details.

12.8.3

Retrigger PSCOUTn1 On External Event

PSCOUTn1 output can be reset before end of On-Time 1 on the change on PSCn Input B. The

polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can be

configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of the

analog comparator or the PSCINn input.

As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.

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Figure 12-18. PSCOUTn1 retriggered by PSCn Input B (edge retriggering).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input B

(falling edge)

PSCn Input B

(rising edge)

Dead-Time 0

Dead-Time 1

Dead-Time 0

Note:

This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 12-33 on page 126 for

details.

Figure 12-19. PSCOUTn1 retriggered by PSCn Input B (level acting).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input B

(high level)

PSCn Input B

(low level)

Dead-Time 0

Dead-Time 1

Dead-Time 0

Note:

This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 12-22 on page 121 for

details.

12.8.3.1

Burst Generation

Note:

On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 (see

Figure 12-26 on page 123 and Figure 12-27 on page 123 for details).

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Figure 12-20. Burst generation.

OFF

BURST

PSCOUTn0

PSCOUTn1

PSCn Input A

(high level)

PSCn Input A

(low level)

12.8.4

PSC Input Configuration

The PSC Input Configuration is done by programming bits in configuration registers.

12.8.4.1

Filter Enable

If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the sig-

nal. The disable of this function is mainly needed for prescaled PSC clock sources, where the

noise cancellation gives too high latency.

Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock

to deactivate the outputs (emergency protection of external component). Likewise when used as

fault input, PSCn Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output.

This way needs that CLK_PSCis running. So thanks to PSC Asynchronous Output Control bit

(PAOCnA/B), PSCnIN0/1 input can deactivate directly the PSC output. Notice that in this case,

input is still taken into account as usually by Input Module System as soon as CLK_PSCis running.

Figure 12-21. PSC input filtering.

CLK

PSC

Digital

Filter

PSCn Input A or B

4 x CLK

PSC

PSC Input

Module X

Ouput

Stage

PSCOUTnX

12.8.4.2

Signal Polarity

One can select the active edge (edge modes) or the active level (level modes). See PELEVnx bit

description in “PFRCnA - PSC n Input A Control Register” on page 141.

If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active

level is high (level modes) and vice versa for unset/falling/low.

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- In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-

Time0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B).

- In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp.

12.8.4.3

Input Mode Operation

Thanks to 4 configuration bits (PRFM3:0), it’s possible to define the mode of the PSC input.

Thanks to four configuration bits (PRFM3:0), it is possible to define all the modes of the PSCR

input. These modes are listed in Table 12-7.

Table 12-7. PSC input mode operation.

PRFM3:0

Description

PSCn input has no action on PSC output

0

1

0000b

See “PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and

Wait” on page 121.

0001b

0010b

0011b

See “PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait”

on page 122.

2

3

See “PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault

active” on page 123.

See “PSC Input Mode 4: Deactivate outputs without changing timing” on

page 124.

4

5

6

0100b

0101b

0110b

See “PSC Input Mode 5: Stop signal and Insert Dead-Time” on page 124.

See “PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and

Wait” on page 125.

See “PSC Input Mode 7: Halt PSC and Wait for Software Action” on page

125.

See “PSC Input Mode 8: Edge Retrigger PSC” on page 126.

7

8

9

0111b

1000b

1001b

See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page

127.

Reserved: Do not use

10

11

12

13

1010b

1011b

1100b

1101b

See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and

Deactivate Output” on page 128.

Reserved: Do not use

14

15

1110b

1111b

Note: All following examples are given with rising edge or high level active inputs.

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12.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait

Figure 12-22. PSCn behavior versus PSCn Input A in Fault Mode 1.

DT0 OT0 DT1 OT1 DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and

OT1.

When PSC Input A event occurs, PSC releases PSCOUTn0, waits for PSC Input A inactive state

and then jumps and executes DT1 plus OT1.

Figure 12-23. PSCn behavior versus PSCn Input B in Fault Mode 1.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.

When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state

and then jumps and executes DT0 plus OT0.

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12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait

Figure 12-24. PSCn behavior versus PSCn Input A in Fault Mode 2.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1.

When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus

OT1 and then waits for PSC Input A inactive state.

Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-

pletely executed.

Figure 12-25. PSCn behavior versus PSCn Input B in Fault Mode 2.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.

When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0

and then waits for PSC Input B inactive state.

Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-

pletely executed.

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12.11 PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active

Figure 12-26. PSCn behavior versus PSCn Input A in Mode 3.

DT0 OT0

DT1 OT1

DT0 OT0 DT1 OT1

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and

OT1.

When PSC Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus OT1

plus DT0 while PSC Input A is in active state.

Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-

pletely executed.

Figure 12-27. PSCn behavior versus PSCn Input B in Mode 3.

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSC Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and

OT0.

When PSC Input B event occurs, PSC releases PSCnOUT1, jumps and executes DT0 plus OT0

plus DT1 while PSC Input B is in active state.

Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-

pletely executed.

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12.12 PSC Input Mode 4: Deactivate outputs without changing timing

Figure 12-28. PSC behavior versus PSCn Input A or Input B in Mode 4.

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Figure 12-29. PSC behavior versus PSCn Input A or Input B in Fault Mode 4.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-

Time1/Dead-Time1.

12.13 PSC Input Mode 5: Stop signal and Insert Dead-Time

Figure 12-30. PSC behavior versus PSCn Input A in Fault Mode 5.

DT0 OT0

DT1

OT1

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

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12.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait

Figure 12-31. PSC behavior versus PSCn Input A in Fault Mode 6.

DT0 OT0 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Used in Fault mode 6, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

12.15 PSC Input Mode 7: Halt PSC and Wait for Software Action

Figure 12-32. PSC behavior versus PSCn Input A in Fault Mode 7.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Software Action (1)

Note:

1. Software action is the setting of the PRUNn bit in PCTLn register.

Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

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12.16 PSC Input Mode 8: Edge Retrigger PSC

Figure 12-33. PSC behavior versus PSCn Input A in Mode 8.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is modulated by the occurrence of significative edge of retriggering input.

Figure 12-34. PSC behavior versus PSCn Input B in Mode 8.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

or

PSCn Input B

The output frequency is modulated by the occurrence of significative edge of retriggering input.

The retrigger event is taken into account only if it occurs during the corresponding On-Time.

Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC

doesn’t jump to the opposite dead-time.

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12.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC

Figure 12-35. PSC behavior versus PSCn Input A in Mode 9.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is not modified by the occurrence of significative edge of retriggering input.

Only the output is deactivated when significative edge on retriggering input occurs.

Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrig-

ger/Fault input is active. Only the significative edge of Retrigger/Fault input is taken into account.

Figure 12-36. PSC behavior versus PSCn Input B in Mode 9.

DT0 OT0 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

The retrigger event is taken into account only if it occurs during the corresponding On-Time.

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12.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output

Figure 12-37. PSC behavior versus PSCn Input A in Mode 14.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is not modified by the occurrence of significative edge of retriggering input.

Figure 12-38. PSC behavior versus PSCn Input B in Mode 14.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

The output is deactivated while retriggering input is active.

The output of the PSC is set to an inactive state and the corresponding ramp is not aborted. The

output stays in an inactive state while the Retrigger/Fault input is active. The PSC runs at con-

stant frequency.

12.18.1 Available Input Mode according to Running Mode

Some input modes are not consistent with some running modes. Table 12-8 gives the input

modes which are valid according to running modes.

Table 12-8. Available input modes according to running modes.

Input mode

number:

1 ramp mode

Valid

2 ramp mode

Valid

4 ramp mode

Valid

Centered mode

Do not use

Valid

1

2

3

4

5

6

Do not use

Valid

Do not use

Valid

Do not use

Valid

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Table 12-8. Available input modes according to running modes. (Continued)

Input mode

number:

1 ramp mode

Valid

2 ramp mode

Valid

4 ramp mode

Valid

Centered mode

Valid

7

8

Valid

Do not use

9

Valid

10

11

12

13

14

15

Do not use

Valid

Do not use

12.18.2 Event Capture

The PSC can capture the value of time (PSC counter) when a retrigger event or fault event

occurs on PSC inputs. This value can be read by software in PICRnH/L register.

12.18.3 Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the PICR1 Register before the next event occurs, the PICR1 will

be overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the PICR1 Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

12.19 PSC2 Outputs

12.19.1 Output Matrix

PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and

PSCOUT21 binary value for each ramp.

Table 12-9. Output matrix versus ramp number.

Ramp 0

Ramp 1

Ramp 2

Ramp 3

PSCOUT20

PSCOUT21

POMV2A0

POMV2B0

POMV2A1

POMV2B1

POMV2A2

POMV2B2

POMV2A3

POMV2B3

PSCOUT2m takes the value given in Table 12-9. during all corresponding ramp. Thanks to the

Output Matrix it is possible to generate all kind of PSCOUT20/PSCOUT21 combination.

When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.

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12.19.2 PSCOUT22 & PSCOUT23 Selectors

PSC 2 has two supplementary outputs PSCOUT22 and PSCOUT23.

According to POS22 and POS23 bits in PSOC2 register, PSCOUT22 and PSCOUT23 duplicate

PSCOUT20 and PSCOU21.

If POS22 bit in PSOC2 register is clear, PSCOUT22 duplicates PSCOUT20.

If POS22 bit in PSOC2 register is set, PSCOUT22 duplicates PSCOUT21.

If POS23 bit in PSOC2 register is clear, PSCOUT23 duplicates PSCOUT21.

If POS23 bit in PSOC2 register is set, PSCOUT23 duplicates PSCOUT20.

Figure 12-39. PSCOUT22 and PSCOUT23 outputs.

PSCOUT20

PSCOUT22

Waveform

Generator A

0

1

POS22

POS23

Output

Matrix

1

0

PSCOUT23

PSCOUT21

Waveform

Generator B

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12.20 Analog Synchronization

PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is

mandatory for measurements.

This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as

defined per Table 12-11 on page 134 and Table 12-12 on page 135.

The signal can be shifted by a digital delay defined by the register PASDLY. The shifting clock

can be either Clkpsc or Clkpsc/4, as described per Bit 7, 6, 5– PASDLKn(2:0): Analog Synchro-

nization Output Delay or Input Blanking select on page 137.

Figure 12-40. Analog synchronization.

OCRnRA

match

OCRnRB

match

A Trig/Fault B Trig/Fault

OCRnSA

match

OCRnSB

match

PSYNCn(1:0)

CLKPSCn/8

CLKPSCn/4

CLKPSCn/2

CLKPSCn

7

6

5

4

Digital

Delay

PASDLYn

0

PSCnASY

1

PASDLKn(2:0)

PASDLKn(2)

12.21 Interrupt Handling

As each PSC can be dedicated for one function, each PSC has its own interrupt system.

List of interrupt sources:

• Counter reload (end of On Time 1)

• End of Enhanced Cycle

• PSC Input event (active edge or at the beginning of level configured event)

• PSC Mutual Synchronization Error

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12.22 PSC Synchronization

Note: In AT90PWM81/161, this feature is not relevant and PRUN2, PARUN2 are stuck at zero.

2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible:

• The waveforms are center aligned in the Center Aligned mode if master and slaves are all

with the same PSC period (which is the natural use).

• The waveforms are edge aligned in the 1, 2 or 4 ramp mode

Figure 12-41. PSC run synchronization.

SY0In

PRUN0

Run PSC0

PARUN0

PSC0

SY0Out

SY1In

PRUN1

Run PSC1

PARUN1

PSC1

SY1Out

SY2In

PRUN2

Run PSC2

PARUN2

PSC2

SY2Out

If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1.

PRUNn and PARUNn bits are located in PCTLn register. See “PCTL2 - PSC 2 Control Register”

on page 140.

Note: Do not set the PARUNn bits on the three PSC at the same time.

Thanks to this feature, we can for example configure two PSC in slave mode (PARUNn = 1 /

PRUNn = 0) and one PSC in master mode (PARUNm = 0 / PRUNm = 0). This PSC master can

start all PSC at the same moment (PRUNm = 1).

12.22.1 Fault events in Autorun mode

To complete this master/slave mechanism, fault event (input mode 7) is propagated from PSCn-

1 to PSCn and from PSCn to PSCn-1.

A PSC which propagate a Run signal to the following PSC stops this PSC when the Run signal

is deactivate.

According to the architecture of the PSC synchronization which build a “daisy-chain on the PSC

run signal” between the three PSC, only the fault event (mode 7) which is able to “stop” the PSC

through the PRUN bits is transmitted along this daisy-chain.

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A PSC which receive its Run signal from the previous PSC transmits its fault signal (if enabled)

to this previous PSC. So a slave PSC propagates its fault events when they are configured and

enabled.

12.23 PSC Clock Sources

PSC must be able to generate high frequency with enhanced resolution.

Each PSC has two clock inputs:

• CLK PLL from the PLL

• CLK I/O

Figure 12-42. Clock selection.

CLK

1

0

PLL

I/O

CK

PRESCALER

PCLKSELn

PPREn1/0

CLK

PSCn

PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source.

PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the

clock.

Table 12-10. Output Clock versus selection and prescaler.

PCLKSELn

PPREn1

PPREn0

CLKPSCn output

CLK I/O

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CLK I/O / 4

CLK I/O / 32

CLK I/O / 256

CLK PLL

CLK PLL / 4

CLK PLL / 32

CLK PLL / 256

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12.24 Interrupts

This section describes the specifics of the interrupt handling as performed in AT90PWM81/161.

12.24.1 List of Interrupt Vector

Each PSC provides three interrupt vectors

• PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs

• PSCn EEC (End of Enhanced Cycle): When enabled and when a match with OCRnRB

occurs at the 15^thenhanced cycle

• PSCn CAPT (Capture Event): When enabled and one of the two following events occurs:

retrigger, capture of the PSC counter or Synchro Error.

See “PIM2 - PSC2 Interrupt Mask Register” on page 143.

12.25 PSC Register Definition

Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers

are described.

12.25.1 PSOC2 - PSC 2 Synchro and Output Configuration

Bit

7

6

5

4

3

2

1

0

POS23

POS22

PSYNC21 PSYNC20 POEN2D

POEN2B

POEN2C

POEN2A

PSOC2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – POS23: PSCOUT23 Selection (PSC2 only)

When this bit is clear, PSCOUT23 outputs the waveform generated by Waveform Generator B.

When this bit is set, PSCOUT23 outputs the waveform generated by Waveform Generator A.

• Bit 6 – POS22: PSCOUT22 Selection (PSC2 only)

When this bit is clear, PSCOUT22 outputs the waveform generated by Waveform Generator A.

When this bit is set, PSCOUT22 outputs the waveform generated by Waveform Generator B.

• Bit 5:4 – PSYNCn1:0: Synchronization Out for ADC Selection

Select the polarity and signal source for generating a signal which will be sent to the ADC for

synchronization.

Table 12-11. Synchronization source description in one/two/four ramp modes.

PSYNCn1

PSYNCn0

Description

0

Send signal on leading edge of PSCOUTn0 (match with OCRnSA)

Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or

fault/retrigger on part A)

0

1

0

1

Send signal on leading edge of PSCOUTn1 (match with OCRnSB)

Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or

fault/retrigger on part B)

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Table 12-12. Synchronization source description in centered mode.

PSYNCn1

PSYNCn0

Description

Send signal on match with OCRnRA (during counting down of PSC)

The minimum value of OCRnRA must be 1

0

Send signal on match with OCRnRA (during counting up of PSC)

The minimum value of OCRnRA must be 1

0

1

0

1

No synchronization signal

• Bit 3 – POEN2D: PSCOUT23 Output Enable (PSC2 only)

When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port.

When this bit is set, second I/O pin affected to PSCOUT23 is connected to the PSC waveform

generator B output and is set and clear according to the PSC operation.

• Bit 2 – POENnB: PSC n OUT Part B Output Enable

When this bit is clear, I/O pin affected to PSCOUTn1 acts as a standard port.

When this bit is set, I/O pin affected to PSCOUTn1 is connected to the PSC waveform generator

B output and is set and clear according to the PSC operation.

• Bit 1 – POEN2C: PSCOUT22 Output Enable (PSC2 only)

When this bit is clear, second I/O pin affected to PSCOUT22 acts as a standard port.

When this bit is set, second I/O pin affected to PSCOUT22 is connected to the PSC waveform

generator A output and is set and clear according to the PSC operation.

• Bit 0 – POENnA: PSC n OUT Part A Output Enable

When this bit is clear, I/O pin affected to PSCOUTn0 acts as a standard port.

When this bit is set, I/O pin affected to PSCOUTn0 is connected to the PSC waveform generator

A output and is set and clear according to the PSC operation.

12.25.2 OCRnSAH and OCRnSAL - Output Compare SA Register

Bit

7

6

5

4

3

2

1

0

–

OCRnSA[11:8]

OCRnSAH

OCRnSAL

OCRnSA[7:0]

Read/Write

Initial Value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

12.25.3 OCRnRAH and OCRnRAL - Output Compare RA Register

Bit

7

6

5

4

3

2

1

0

–

OCRnRA[11:8]

OCRnRAH

OCRnRAL

OCRnRA[7:0]

Read/Write

Initial Value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

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12.25.4 OCRnSBH and OCRnSBL - Output Compare SB Register

Bit

7

6

5

4

3

2

1

0

–

OCRnSB[11:8]

OCRnSBH

OCRnSBL

OCRnSB[7:0]

Read/Write

Initial Value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

12.25.5 OCRnRBH and OCRnRBL - Output Compare RB Register

Bit

7

6

5

4

3

2

1

0

OCRnRB[15:12]

OCRnRB[7:0]

OCRnRB[11:8]

OCRnRBH

OCRnRBL

Read/Write

Initial Value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

Note: n = 0 to 2 according to PSC number.

The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously

compared with the PSC counter value. A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the associated pin.

The Output Compare Registers RB contains also a 4-bit value that is used for the flank width

modulation.

The Output Compare Registers are 16-bit and 12-bit in size. To ensure that both the high and

low bytes are written simultaneously when the CPU writes to these registers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by

all the other 16-bit registers.

12.25.6 PCNF2 - PSC 2 Configuration Register

Bit

7

6

5

4

3

2

1

0

PFIFTY2

PALOCK2 PLOCK2

PMODE21 PMODE20 POP2

PCLKSEL2 POME2

PCNF2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The PSC n Configuration Register is used to configure the running mode of the PSC.

• Bit 7 - PFIFTYn: PSC n Fifty

Writing this bit to one, set the PSC in a fifty percent mode where only OCRnRBH/L and OCRn-

SBH/L are used. They are duplicated in OCRnRAH/L and OCRnSAH/L during the update of

OCRnRBH/L. This feature is useful to perform fifty percent waveforms.

• Bit 6 - PALOCKn: PSC n Autolock

When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and

the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The

update of the PSC internal registers will be done at the end of the PSC cycle if the Output Com-

pare Register RB has been the last written.

When set, this bit prevails over LOCK (bit 5).

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• Bit 5 – PLOCKn: PSC n Lock

When this bit is set, the Output Compare Registers RA, RB, SA, SB, the Output Matrix POM2

and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles.

The update of the PSC internal registers will be done if the LOCK bit is released to zero.

• Bit 4:3 – PMODEn1: 0: PSC n Mode

Select the mode of PSC.

Table 12-13. PSC n mode selection.

PMODEn1

PMODEn0

Description

0

1

0

1

0

1

One Ramp mode

Two Ramp mode

Four Ramp mode

Center Aligned mode

• Bit 2 – POPn: PSC n Output Polarity

If this bit is cleared, the PSC outputs are active Low.

If this bit is set, the PSC outputs are active High.

• Bit 1 – PCLKSELn: PSC n Input Clock Select

This bit is used to select between CLKPF or CLKPS clocks.

Set this bit to select the fast clock input (CLKPF).

Clear this bit to select the slow clock input (CLKPS).

• Bit 0 – POME2: PSC 2 Output Matrix Enable (PSC2 only)

Set this bit to enable the Output Matrix feature on PSC2 outputs. See “PSC2 Outputs” on page

129.

When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.

12.25.7 PCNFE2 - PSC 2 Extended Configuration Register

Bit

7

6

5

4

3

2

1

0

PASDLKn2 PASDLKn1 PASDLKn0 PBFMn1

PELEVnA1 PELEVnB1 PISELnA1 PISELnB1 PCNFE2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The PSC n Extended Configuration Register is used to configure the running mode of the PSC.

• Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output Delay or Input Blanking

select

Defines the modes for Analog signal synchronization delay or Input Blanking.

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Table 12-14. Analog signal synchronization or Input Blanking mode selection.

PASDLKn2

PASDLKn1

PASDLKn0

Description

0

No Analog signal synchronization delay, no Input Blanking

No Analog signal synchronization delay, Input Blanking using PSC clock,

started on PSC end of cycle

0

1

0

1

No Analog signal synchronization delay, Input Blanking using PSC clock,

started on OCR SA event

No Analog signal synchronization delay, Input Blanking using PSC clock,

started on OCR SB event

1

0

1

0

1

0

1

Analog signal synchronization delay with PSC clock, no Input Blanking

Analog signal synchronization delay with PSC clock /2, no Input Blanking

Analog signal synchronization delay with PSC clock /4, no Input Blanking

Analog signal synchronization delay with PSC clock /8, no Input Blanking

• Bit 4- PBFMn1: Balance Flank Width Modulation, bit 1

Defines the Flank Width Modulation, together with PBFMn0 bit in PCTLn register.

Table 12-15. Flank Width Mode selection.

PBFMn1

PBFMn0

Description

0

Flank Width Modulation operates on RB (On-Time 1 only)

Flank Width Modulation operates on RB + RA (On-Time 0 and On-

Time 1)

0

1

0

1

Flank Width Modulation operates on SB (Dead-Time 1 only) ⁽¹⁾

Flank Width Modulation operates on SB +SA (Dead-Time 0 and

Dead-Time 1)

Note:

1. In one ramp mode, changing SA or SA+BSB also affect On-Time; see Figure 12-8 on page

108.

• Bit 3– PELEVnA1: PSC n Input Select for part A

Together with PELEVnA0, defines active edge or level on PSC part A.

Table 12-16. PSC edge & level input selection.

PELEVnA1

PELEVnA0

Description

The falling edge or low level of selected input generates the

significative event for retrigger or fault function

0

The rising edge or high level of selected input generates the

significative event for retrigger or fault function

0

1

The toggle of selected input generates the significative event for

retrigger or fault function

1

0

1

Reserved

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• Bit 2– PELEVnB1: PSC n Input Select for part B

Together with PELEVnB0, defines active edge or level on PSC part B.

Table 12-17. PSC edge & level input selection.

PELEVnB1

PELEVnB0

Description

The falling edge or low level of selected input generates the

significative event for retrigger or fault function

0

The rising edge or high level of selected input generates the

significative event for retrigger or fault function

0

1

The toggle of selected input generates the significative event for

retrigger or fault function

1

0

1

Reserved

• Bit 1– PISELnA1: PSC n Input Select for part A

Together with PISELnA0, defines active signal on PSC part A.

Table 12-18. PSC trigger & fault input selection.

PISELnA1

PISELnA0

Description

0

1

0

1

0

1

PSCINn

First analog comparator output

PSCINnA

Second analog comparator output

• Bit 0– PISELnB1: PSC n Input Select for part B

Together with PISELnB0, defines active signal on PSC part B.

Table 12-19. PSC trigger & fault input selection.

PISELnB1

PISELnB0

Description

0

1

0

1

0

1

PSCINn

First analog comparator output

PSCINnA

Second analog comparator output

12.25.8 PASDLYn - Analog Synchronization Delay Register

Bit

7

6

5

4

3

2

1

0

PASDLYn[7:0]

PASDLYn

Read/Write

Initial Value

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

The Analog Synchronization Delay Register store an 8 bit delay used:

• For the input signal blanking. See Section “PSC Inputs”, page 114

• For shifting the PSCOUTnx edges and the PSCnASY signal. See Section “Analog

Synchronization”, page 131

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See also the bit definition Section “Bit 7, 6, 5– PASDLKn(2:0): Analog Synchronization Output

Delay or Input Blanking select”, page 137 and Section “Bit 5:4 – PSYNCn1:0: Synchronization

Out for ADC Selection”, page 134.

12.25.9 PCTL2 - PSC 2 Control Register

Bit

7

6

5

4

3

2

1

0

PPRE21

R/W

0

PPRE20

R/W

0

PBFM20

R/W

PAOC2B

PAOC2A

PARUN2

PCCYC2

PRUN2

R/W

0

PCTL2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7:6 – PPREn1:0 : PSC n Prescaler Select

This two bits select the PSC input clock division factor. All generated waveform will be modified

by this factor.

Table 12-20. PSC n Prescaler selection.

PPREn1

PPREn0

Description

0

1

0

1

0

1

No divider on PSC input clock

Divide the PSC input clock by 4

Divide the PSC input clock by 16

Divide the PSC clock by 64

• Bit 5 – PBFMn0: Balance Flank Width Modulation bit 0

Defines the Flank Width Modulation, together with PBFMn1 bit in PCNFEn register. See Table

12-15 on page 138.

• Bit 4 – PAOCnB: PSC n Asynchronous Output Control B

When this bit is set, Fault input selected to block B can act directly to PSCOUTn1 and

PSCOUT23 outputs. See Section “PSC Clock Sources”, page 133.

• Bit 3 – PAOCnA: PSC n Asynchronous Output Control A

When this bit is set, Fault input selected to block A can act directly to PSCOUTn0 and

PSCOUT22 outputs. See Section “PSC Clock Sources”, page 133.

• Bit 2 – PARUNn: PSC n Autorun

When this bit is set, the PSC n starts with PSCn-1. That means that PSC n starts:

• when PRUNn bit in PCTLn register is set,

• or when PARUNn bit in PCTLn is set and PRUNn-1 bit in PCTLn-1 register is set (or PARUN0

bit and PRUN0)

• Bit 1 – PCCYCn: PSC n Complete Cycle

When this bit is set, the PSC n completes the entire waveform cycle before halt operation

requested by clearing PRUNn. This bit is not relevant in slave mode (PARUNn = 1).

• Bit 0 – PRUNn: PSC n Run

Writing this bit to one starts the PSC n.

When set, this bit prevails over PARUNn bit.

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12.25.10 PFRCnA - PSC n Input A Control Register

Bit

7

6

5

4

3

2

1

0

PCAEnA

PISELnA0 PELEVnA0 PFLTEnA PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 PFRCnA

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

12.25.11 PFRCnB - PSC n Input B Control Register

Bit

7

6

5

4

3

2

1

0

PCAEnB

PISELnB0 PELEVnB0 PFLTEnB PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 PFRCnB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The

2 blocks are identical, so they are configured on the same way.

• Bit 7 – PCAEnx: PSC n Capture Enable Input Part x

Writing this bit to one enables the capture function when external event occurs on input selected

as input for Part x (see PISELnx1:0 bit in the same register).

• Bit 6 – PISELnx0: PSC n Input Select for Part x

Together with PISELnx1 in PCNFEn register, defines active signal on PSC module A. See Table

12-18 on page 139 and Table 12-19 on page 139.

• Bit 5 –PELEVnx0: PSC n Edge Level Selector of Input Part x

Together with PELEVnx1 n PCNFEn register, defines active edge & level on PSC part x; See

Table 12-16 on page 138 and Table 12-17 on page 139.

• Bit 4 – PFLTEnx: PSC n Filter Enable on Input Part x

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the retrigger pin is filtered. The filter function requires four successive

equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore

delayed by four oscillator cycles when the noise canceler is enabled.

• Bit 3:0 – PRFMnx3:0: PSC n Fault Mode

These four bits define the mode of operation of the Fault or Retrigger functions.

(see Table 12-7 on page 120 for more explanations).

Table 12-21. Level sensitivity and Fault Mode operation.

PRFMnx3:0

Description

No action, PSC Input is ignored

0000b

“PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait”,

page 121

0001b

“PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait”,

page 122

0010b

0011b

“PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active”,

page 123

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Table 12-21. Level sensitivity and Fault Mode operation. (Continued)

PRFMnx3:0

0100b

Description

“PSC Input Mode 4: Deactivate outputs without changing timing”, page 124

“PSC Input Mode 5: Stop signal and Insert Dead-Time”, page 124

0101b

“PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait”,

page 125

0110b

“PSC Input Mode 7: Halt PSC and Wait for Software Action”, page 125

0111b

1000b

1001b

1010b

1011b

1100b

1101b

“PSC Input Mode 8: Edge Retrigger PSC”, page 126

“PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC”, page 127

Reserved (do not use)

“PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate

Output”, page 128

Reserved (do not use)

1110b

1111b

12.25.12 PICR2H and PICR2L - PSC 2 Input Capture Register

Bit

7

6

5

4

3

2

1

0

PCST2

–

PICR2[11:8]

PICR2H

PICR2L

PICR2[7:0]

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – PCSTn: PSC Capture Software Trig bit

Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means

that the capture operation was triggered by PCSTn setting otherwise it means that the capture

operation was triggered by a PSC input.

The Input Capture is updated with the PSC counter value each time an event occurs on the

enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is

enabled (bit PCAEnx in PFRCnx register is set).

The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or

12-bit registers.

12.26 PSC2 Specific Register

12.26.1 POM2 - PSC 2 Output Matrix

Bit

7

6

5

4

3

2

1

0

POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 POM2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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• Bit 7 – POMV2B3: Output Matrix Output B Ramp 3

This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3.

• Bit 6 – POMV2B2: Output Matrix Output B Ramp 2

This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2.

• Bit 5 – POMV2B1: Output Matrix Output B Ramp 1

This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1.

• Bit 4 – POMV2B0: Output Matrix Output B Ramp 0

This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0.

• Bit 3 – POMV2A3: Output Matrix Output A Ramp 3

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3.

• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2.

• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1.

• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0

This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0.

12.26.2 PIM2 - PSC2 Interrupt Mask Register

Bit

7

6

5

4

3

2

-

1

0

-

PSEIE2

R/W

0

PEVE2B

R/W

PEVE2A

R/W

PEOEPE2 PEOPE2

PIM2

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

R/W

0

• Bit 5 – PSEIEn: PSC n Synchro Error Interrupt Enable

When this bit is set, the PSEIn bit (if set) generate an interrupt.

• Bit 4 – PEVEnB: PSC n External Event B Interrupt Enable

When this bit is set, an external event which can generates a capture from Retrigger/Fault block

B generates also an interrupt.

• Bit 3 – PEVEnA: PSC n External Event A Interrupt Enable

When this bit is set, an external event which can generates a capture from Retrigger/Fault block

A generates also an interrupt.

• Bit 1– PEOEPEn: PSC n End Of Enhanced Cycle Interrupt Enable

When this bit is set, an interrupt is generated when PSC reaches the end of the 15^thPSC cycle.

This allows to update the PSC values in the interrupt routine and to start a new enhanced cycle

with the new values at the next PSC cycle end.

• Bit 0 – PEOPEn: PSC n End Of Cycle Interrupt Enable

When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.

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12.26.3 PIFR2 - PSC2 Interrupt Flag Register

Bit

7

6

5

4

3

2

1

0

POAC2B

POAC2A

PSEI2

R/W

0

PEV2B

R/W

0

PEV2A

R/W

0

PRN21

PRN20

PEOP2

R/W

0

PIFR2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7 – POACnB: PSC n Output B Activity

This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.

Must be cleared by software by writing a one to its location.

This feature is useful to detect that a PSC output doesn’t change due to a frozen external input

signal.

• Bit 6 – POACnA: PSC n Output A Activity

This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.

Must be cleared by software by writing a one to its location.

This feature is useful to detect that a PSC output doesn’t change due to a frozen external input

signal.

• Bit 5 – PSEIn: PSC n Synchro Error Interrupt

This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in

auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated

the input run signal. (For PSC0, PSCn-1 is PSC2).

Must be cleared by software by writing a one to its location.

This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase

than the PSC master.

• Bit 4 – PEVnB: PSC n External Event B Interrupt

This bit is set by hardware when an external event which can generates a capture or a retrigger

from Retrigger/Fault block B occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0).

• Bit 3 – PEVnA: PSC n External Event A Interrupt

This bit is set by hardware when an external event which can generates a capture or a retrigger

from Retrigger/Fault block A occurs.

Must be cleared by software by writing a one to its location.

This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0).

• Bit 2:1 – PRNn1:0: PSC n Ramp Number

Memorization of the ramp number when the last PEVnA or PEVnB occurred.

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Table 12-22. PSC n ramp number description.

PRNn1

PRNn0

Description

0

1

0

1

0

1

The last event which has generated an interrupt occurred during ramp 1

The last event which has generated an interrupt occurred during ramp 2

The last event which has generated an interrupt occurred during ramp 3

The last event which has generated an interrupt occurred during ramp 4

• Bit 0 – PEOPn: End Of PSC n Interrupt

This bit is set by hardware when PSC n achieves its whole cycle.

Must be cleared by software by writing a one to its location.

12.26.4 PSC Output Behavior During Reset

For external component safety reason, the state of PSC outputs during Reset can be pro-

grammed by fuses PSCRV, PSCRRB & PSC2RB.

These fuses are located in the Extended Fuse Byte:

Table 12-23. Extended Low Fuse byte.

Extended fuse byte

Bit No

Description

Default value

PSC2RB

7

PSC2 reset behavior

1

PSC2 reset behavior for

OUT22 & 23

PSC2RBA

PSCRRB

PSCRV

6

5

4

1

PSC reduced reset behavior

PSCOUT & PSCOUTR reset

value

PSC & PSCR inputs reset

behavior

PSCINRB

3

2

1

0

1

Brown-out detector trigger

level

BODLEVEL2 ⁽¹⁾

BODLEVEL1 ⁽¹⁾

BODLEVEL0 ⁽¹⁾

1 (unprogrammed)

0 (programmed)

1 (unprogrammed)

Brown-out detector trigger

level

Brown-out detector trigger

level

Notes: 1. See Table 7-2 on page 53 for BODLEVEL Fuse decoding.

PSCRV gives the state low or high which will be forced on PSC outputs selected by PSC0RB &

PSC2RB fuses.

If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to low state. If

PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to high state.

If PSCRRB fuse equals 1 (unprogrammed), PSCOUTR0 & PSCOUTR1 keep a standard port

behavior. If PSC0RB fuse equals 0 (programmed), PSCOUTR0 & PSCOUTR1 are forced at

reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUTR0 &

PSCOUTR1 keep the forced state until PSOC0 register is written.

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If PSC2RB fuse equals 1 (unprogrammed), PSCOUT20 & PSCOUT21 keep a standard port

behavior. If PSC2RB fuse equals 0 (programmed), PSCOUT20 & PSCOUT21 are forced at

reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT20 &

PSCOUT21 keep the forced state until PSOC2 register is written.

If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port

behavior. If PSC2RBA fuse equals 0 (programmed), PSCOUT22 & PSCOUT23 are forced at

reset to low level or high level according to PSCRV fuse bit. In this second case, PSCOUT22 &

PSCOUT23 keep the forced state until PSOC2 register is written.

12.26.5 PSC Input Behavior During Reset

For power consumption under reset reason, the state of PSC & PSCR inputs during Reset can

be programmed by fuse PSCINRB.

If PSCINRB fuse equals 1 (unprogrammed), PSC & PSCR input keep a standard port behavior.

If PSCINRB fuse equals 0 (programmed), PSC & PSCR input pull-up are forced while the reset

is active. Affected pins are PSCIN2, PSCINr, PSCIN2A, PSCINrA. To prevent any conflict on

PD1, this fuse has no effect on PSCINrB.

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13. Reduced Power Stage Controller – (PSCR)

The Reduced Power Stage Controller is a high performance waveform controller.

13.1 Features

• PWM waveform generation function (two complementary programmable outputs)

• Dead time control

• Standard mode up to 12-bit resolution

• Enhanced resolution up to 16 bits

• Frequency up to 64Mhz

• Conditional waveform on external events (zero crossing, current sensing ...)

• ADC synchronization

• Overload protection function

• Abnormality protection function, emergency input to force all outputs to high impedance or in

inactive state (fuse configurable)

• Fast emergency stop by hardware

13.2 Overview

Many register and bit references in this section are written in general form.

• A lower case “r” (or “n” replaces the PSC number, in this case 0. However, when using the

register or bit defines in a program, the precise form must be used, that is, PSOC0 for

accessing PSCR 0 Synchro and Output Configuration register and so on

• A lower case “x” replaces the PSCR part , in this case A or B. However, when using the

register or bit defines in a program, the precise form must be used, that is, PFRC0A for

accessing PSCR 0 Fault/Retrigger A Control register and so on

The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has

two outputs.

These outputs can be used in various ways:

• “Two Outputs” to drive a half bridge (for example, Lighting applications)

• “One Output” to drive single power transistor (for example, DC/DC converter, PFC

applications)

The PSCR has two inputs the purpose of which is to provide means to act directly on the gener-

ated waveforms:

• Current sensing regulation

• Zero crossing retriggering

• Demagnetization retriggering

• Fault input

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13.3 PSCR Description

Figure 13-1. Power Stage Controller block diagram.

PSCR Counter

Waveform

Gererator B

PSCOUTr1

=

OCRrRB

PSC Input

Module B

PSCr Input B

=

OCRrSB

Part B

PSC Input

Module A

PSCr Input A

=

OCRrRA

PSCOUTr0

Waveform

Gererator A

=

OCRrSA

Part A

PICRr

PCNFr

PCTLr

PFRCrB

PFRCrA

PSOCr

The principle of the PSCR is based on the use of a counter (PSCR counter). This counter is

able to count up and count down from and to values stored in registers according to the selected

running mode.

The PSCR is seen as two symmetrical entities. One part named part A which generates the out-

put PSCOUTr0 and the second one named part B which generates the PSCOUTr1 output.

Each part A or B has its own PSCR Input Module to manage selected input.

13.3.1

Output Polarity

The polarity “active high” or “active low” of the PSCR outputs is programmable. All the timing

diagrams in the following examples are given in the “active high” polarity.

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13.4 Signal Description

Figure 13-2. PSCR external block view.

CLK

PLL

CLK

I/O

12

OCRrRB[11:0]

OCRrSB[11:0]

OCRrRA[11:0]

OCRrSA[11:0]

PSCOUTr0

PSCOUTr1

12

3

PICRr[11:0]

PSCINr

IRQ PSCr

Analog

Comparator

Output

PSCrASY

13.4.1

Input Description

Table 13-1. Internal inputs.

Name

Description

Type width

Register 12 bits

Signal

OCRrRB[11:0]

OCRrSB[11:0]

OCRrRA[11:0]

OCRrSA[11:0]

CLK I/O

Compare value which reset signal on Part B (PSCOUTr1)

Compare value which set signal on Part B (PSCOUTr1)

Compare value which reset signal on Part A (PSCOUTr0)

Compare value which set signal on Part A (PSCOUTr0)

Clock input from I/O clock

CLK PLL

Clock input from PLL

Signal

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Table 13-2. Block inputs.

Name Description

PSCINr

Type width

Signal

Input 0 used for retrigger or fault functions

Input 1 used for retrigger or fault functions

From analog

comparator

Signal

PSCINrA

PSCINrB

Input 2 used for retrigger or fault functions

Input 3 used for retrigger or fault functions

Signal

13.4.2

Output Description

Table 13-3. Block outputs.

Name

PSCOUTr0

PSCOUTr1

Description

Type width

Signal

PSCR Output 0 (from part A of PSC)

PSCR Output 1 (from part B of PSC)

Signal

Table 13-4. Internal Outputs.

Name

Description

Type width

PSCR Input Capture Register

Counter value at retriggering event

PICRr[11:0]

Register 12 bits

PSCR Interrupt Request: three sources, overflow, fault, and

input capture

IRQPSCr

PSCrASY

Signal

ADC synchronization (+ amplifier synchro.) ⁽²⁾

2. See “Analog Synchronization” on page 169.

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13.5 Functional Description

13.5.1

Waveform Cycles

The waveform generated by PSCR can be described as a sequence of two waveforms.

The first waveform is relative to PSCOUTr0 output and part A of PSC. The part of this waveform

is sub-cycle A in Figure 13-3.

The second waveform is relative to PSCOUTr1 output and part B of PSC. The part of this wave-

form is sub-cycle B in Figure 13-3.

The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform

B.

Figure 13-3. Cycle presentation in 1, 2, and 4 Ramp mode.

PSC Cycle

Sub-Cycle A

Sub-Cycle B

4 Ramp Mode

Ramp A0

Ramp A1

Ramp B0

Ramp B1

2 Ramp Mode

Ramp A

Ramp B

1 Ramp Mode

UPDATE

Ramps illustrate the output of the PSCR counter included in the waveform generators. Centered

Mode is like a one ramp mode which count down up and down.

Notice that the update of a new set of values is done regardless of ramp Mode at the top of the

last ramp.

13.5.2

Running Mode Description

Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1,

OT1) and by the running mode. Three modes are possible:

– Four Ramp mode

– Two Ramp mode

– One Ramp mode

The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given

by the OT1 value. Both of them are 12 bit values. Thanks to DT0 & DT1 to adjust the dead time

between PSCOUTn0 and PSCOUTn1 active signals.

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The waveform frequency is defined by the following equation:

f

1

CLK_PSCn

f

= ----------------------------- = --------------------------------------------------------------------

PSCn

PSCnCycle

(OT0 + OT1 + DT0 + DT1)

13.5.2.1

Four Ramp Mode

In Four Ramp mode, each time in a cycle has its own definition.

Figure 13-4. PSCr0 & PSCr1 basic waveforms in Four Ramp mode.

OCRnRA

PSC Counter

OCRnSA

OCRnRB

OCRnSB

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

The input clock of PSCR is given by CLKPSC.

PSCOUTr0 and PSCOUTr1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and

Dead-Time 1 values with:

On-Time 0 = OCRrRAH/L × 1/Fclkpsc

On-Time 1 = OCRrRBH/L × 1/Fclkpsc

Dead-Time 0 = (OCRrSAH/L + 2) × 1/Fclkpsc

Dead-Time 1 = (OCRrSBH/L + 2) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 and Dead-Time 1 = 2 × 1/Fclkpsc.

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13.5.2.2

Two Ramp Mode

In Two Ramp mode, the whole cycle is divided in two moments:

• One moment for PSCr0 description with OT0 which gives the time of the whole moment

• One moment for PSCr1 description with OT1 which gives the time of the whole moment

Figure 13-5. PSCr0 & PSCr1 basic waveforms in Two Ramp mode.

OCRnRA

OCRnRB

PSC Counter

OCRnSA

OCRnSB

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

PSCOUTr0 and PSCOUTr1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and

Dead-Time 1 values with:

On-Time 0 = (OCRrRAH/L - OCRrSAH/L) × 1/Fclkpsc

On-Time 1 = (OCRrRBH/L - OCRrSBH/L) × 1/Fclkpsc

Dead-Time 0 = (OCRrSAH/L + 1) × 1/Fclkpsc

Dead-Time 1 = (OCRrSBH/L + 1) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc.

13.5.2.3

One Ramp Mode

In One Ramp mode, PSCOUTr0 and PSCOUTr1 outputs can overlap each other.

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Figure 13-6. PSCr0 & PSCr1 basic waveforms in One Ramp mode.

OCRnRB

OCRnSB

OCRnRA

PSC Counter

OCRnSA

0

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

Dead-Time 0

Dead-Time 1

PSC Cycle

On-Time 0 = (OCRrRAH/L - OCRrSAH/L) × 1/Fclkpsc

On-Time 1 = (OCRrRBH/L - OCRrSBH/L) × 1/Fclkpsc

Dead-Time 0 = (OCRrSAH/L + 1) × 1/Fclkpsc

Dead-Time 1 = (OCRrSBH/L - OCRrRAH/L) × 1/Fclkpsc

Note:

Minimal value for Dead-Time 0 = 1/Fclkpsc.

13.5.3

Fifty Percent Waveform Configuration

When PSCOUTr0 and PSCOUTr1 have the same characteristics, it’s possible to configure the

PSCR in a Fifty Percent mode. When the PSCR is in this configuration, it duplicates the

OCRrSBH/L and OCRrRBH/L registers in OCRrSAH/L and OCRrRAH/L registers. So it is not

necessary to program OCRrSAH/L and OCRrRAH/L registers.

13.6 Update of Values

The update of PSCR waveform registers are done in the following way:

•

Immediately when the PSC is stopped

At the PSC end of cycle when the PSC is running

At the PSC end of cycle following the required condition when LOCK or AUTOLOCK modes

are used

To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is

necessary, all values are updated at the same time at the end of the cycle by the PSC. The new

set of values is calculated by software and the update is initiated by software.

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Figure 13-7. Update at the end of complete PSCR cycle.

Regulation Loop

Calculation

Writting in

PSC Registers

Request for

an Update

Software

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

Cycle

With Set i

PSC

Cycle

With Set j

End of Cycle

The software can stop the cycle before the end to update the values and restart a new PSCR

cycle.

13.6.1

Value Update Synchronization

New timing values or PSCR output configuration can be written during the PSCR cycle. Thanks

to LOCK and AUTOLOCK configuration bits, the new whole set of values can be taken into

account with the following conditions:

• When AUTOLOCK configuration is selected, the update of the PSCR internal registers will be

done at the end of the PSCR cycle following a write in the Output Compare Register RB. The

AUTOLOCK configuration bit is taken into account at the end of the first PSCR cycle

• When LOCK configuration bit is set, there is no update. The update of the PSCR internal

registers will be done at the end of the PSCR cycle if the LOCK bit is released to zero

The registers which update is synchronized thanks to LOCK and AUTOLOCK are OCRrSAH/L,

OCRrRAH/L, OCRrSBH/L, OCRrRBH/L and PSOCr. PISELrA1 and PISELrB1 bits of PSOCr are

immediatly updated in order to behave as PISELrA0 and PISELrB0.

See these register’s description starting on page 172.

When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.

See “PCNF0 - PSCR Configuration Register” on page 173.

13.7 Enhanced resolution

The PSCR includes the same resolution enhancement as in PSC. Please see

Section “Enhanced Resolution”, page 111 for the description of this feature.

13.8 PSCR Inputs

Each part A or B of PSCR has its own system to take into account one PSCR input. According to

PSCR Input A/B Control Register (see description “PFRC0A - PSCR Input A Control Register”

on page 175), PSCrIN0/1 input can act has a Retrigger or Fault input.

This system A or B is also configured by this PSCR Input A/B Control Register (PFRCrA/B).

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Figure 13-8. PSCR input module.

PAOCrA

(PAOCrB)

0

1

PSCINr

0

1

AC1O: Analog

Comparator

Output

PSCR Input A

(PSCR Input B)

0

1

Digital

Filter

0

PSCINrA

PSCINrB

PFLTErA

(PFLTErB)

CLK

PSC

1

PELEVrA / PCAErA

(PELEVrB) (PCAErB)

2

4

Input

Processing

(retriggering ...)

PISELrA1 PISELrA0

(PISELrB1) (PISELrB0)

PRFMrA3:0

(PRFMrB3:0)

CLK

PSC

PSC Core

(Counter,

Waveform

Generator, ...)

Output

Control

PSCOUTr0

(PSCOUTr1)

CLK

PSC

13.8.1

13.8.2

PSCR Retrigger Behavior versus PSCR running modes

In two ramp or four ramp mode, Retrigger Inputs A or B cause the end of the corresponding

cycle A or B and the beginning of the following cycle B or A.

In one ramp mode, Retrigger Inputs A or B reset the current PSCR counting to zero.

Retrigger PSCOUTr0 On External Event

PSCOUTr0 output can be reset before end of On-Time 0 on the change on PSCr Input A. PSCr

Input A can be configured to do not act or to act on level or edge modes. The polarity of PSCr

Input A is configurable thanks to a sense control block. PSCr Input A can be the Output of the

analog comparator or the PSCINr input.

As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.

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Figure 13-9. PSCOUTr0 retriggered by PSCr Input A (edge retriggering).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input A

(falling edge)

PSCn Input A

(rising edge)

Dead-Time 0

Dead-Time 1

Note:

This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 13-26 on page 166 for

details.

Figure 13-10. PSCOUTr0 retriggered by PSCr Input A (level acting).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input A

(high level)

PSCn Input A

(low level)

Dead-Time 0

Dead-Time 1

Note:

This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 13-15 on page 161 for

details.

13.8.3

Retrigger PSCOUTr1 On External Event

PSCOUTr1 output can be reset before end of On-Time 1 on the change on PSCr Input B. The

polarity of PSCr Input B is configurable thanks to a sense control block. PSCr Input B can be

configured to do not act or to act on level or edge modes. PSCr Input B can be the Output of the

analog comparator or the PSCINr input.

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As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.

Figure 13-11. PSCOUTr1 retriggered by PSCr Input B (edge retriggering).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input B

(falling edge)

PSCn Input B

(rising edge)

Dead-Time 0

Dead-Time 1

Dead-Time 0

Note:

This example is given in “Input Mode 8” in “2 or 4 ramp mode”. See Figure 13-26 on page 166 for

details.

Figure 13-12. PSCOUTr1 retriggered by PSCr Input B (level acting).

On-Time 0

On-Time 1

PSCOUTn0

PSCOUTn1

PSCn Input B

(high level)

PSCn Input B

(low level)

Dead-Time 0

Dead-Time 1

Dead-Time 0

Note:

This example is given in “Input Mode 1” in “2 or 4 ramp mode”. See Figure 13-15 on page 161 for

details.

13.8.3.1

Burst Generation

Note:

On level mode, it’s possible to use PSCR to generate burst by using Input Mode 3 or Mode 4 (see

Figure 13-19 on page 163 and Figure 13-20 on page 163 for details.)

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Figure 13-13. Burst generation.

OFF

BURST

PSCOUTn0

PSCOUTn1

PSCn Input A

(high level)

PSCn Input A

(low level)

13.8.4

PSCR Input Configuration

The PSCR Input Configuration is done by programming bits in configuration registers.

13.8.4.1

Filter Enable

If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the sig-

nal. The disable of this function is mainly needed for prescaled PSCR clock sources, where the

noise cancellation gives too high latency.

Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSCR

clock to deactivate the outputs (emergency protection of external component). Likewise when

used as fault input, PSCr Input A or Input B have to go through PSCR to act on PSCOUTr0/1/2/3

output. This way needs that CLK_PSCRis running. So thanks to PSCR Asynchronous Output Con-

trol bit (PAOCrA/B), PSCrIN0/1 input can deactivate directly the PSCR output. Notice that in this

case, input is still taken into account as usually by Input Module System as soon as CLK_PSCRis

running.

Figure 13-14. PSCR input filtering.

CLK

PSC

Digital

Filter

PSCn Input A or B

4 x CLK

PSC

PSC Input

Module X

Ouput

Stage

PSCOUTnX

13.8.4.2

Signal Polarity

One can select the active edge (edge modes) or the active level (level modes). See PELEV0x bit

description in Section “PFRC0A - PSCR Input A Control Register”, page 175.

If PELEV0x bit set, the significant edge of PSCr Input A or B is rising (edge modes) or the active

level is high (level modes) and vice versa for unset/falling/low.

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- In 2- or 4-ramp mode, PSCr Input A is taken into account only during Dead-Time0 and On-

Time0 period (respectively Dead-Time1 and On-Time1 for PSCr Input B).

- In 1-ramp-mode PSCR Input A or PSCR Input B act on the whole ramp.

13.8.4.3

Input Mode Operation

Thanks to four configuration bits (PRFM3:0), it is possible to define all the modes of the PSCR

input. These modes are listed in Table 13-5.

Table 13-5. PSCR input mode operation.

PRFM3:0

Description

PSCr Input has no action on PSCR output

0

1

0000b

See “PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and

Wait” on page 161.

See “PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and

Wait” on page 162.

See “PSCR Input Mode 3: Stop signal, Execute Opposite while Fault

active” on page 163.

See “PSCR Input Mode 4: Deactivate outputs without changing timing” on

page 164.

See “PSCR Input Mode 5: Stop signal and Insert Dead-Time” on page

164.

See “PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and

Wait” on page 165.

0001b

0010b

0011b

0100b

0101b

0110b

2

3

4

5

6

See “PSCR Input Mode 7: Halt PSCR and Wait for Software Action” on

page 165.

See “PSCR Input Mode 8: Edge Retrigger PSC” on page 166.

7

8

9

0111b

1000b

1001b

See “PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC” on

page 167.

Reserved: Do not use

10

11

12

13

1010b

1011b

1100b

1101b

See “PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and

Deactivate Output” on page 168.

Reserved: Do not use

14

15

1110b

1111b

Note: All the following examples are given with rising edge or high level active inputs.

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13.9 PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait

Figure 13-15. PSCr behavior versus PSCr Input A in Fault Mode 1.

DT0 OT0 DT1 OT1 DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and

OT1.

When PSCR Input A event occurs, PSCR releases PSCOUTr0, waits for PSCR Input A inactive

state and then jumps and executes DT1 plus OT1.

Figure 13-16. PSCr behavior versus PSCr Input B in Fault Mode 1.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and

OT0.

When PSCR Input B event occurs, PSCR releases PSCOUTr1, waits for PSCR Input B inactive

state and then jumps and executes DT0 plus OT0.

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13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait

Figure 13-17. PSCr behavior versus PSCr Input A in Fault Mode 2.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and

OT1.

When PSCr Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus

OT1 and then waits for PSCR Input A inactive state.

Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-

pletely executed.

Figure 13-18. PSCr behavior versus PSCr Input B in Fault Mode 2.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and

OT0.

When PSCR Input B event occurs, PSCR releases PSCOUTr1, jumps and executes DT0 plus

OT0 and then waits for PSCR Input B inactive state.

Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-

pletely executed.

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13.11 PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active

Figure 13-19. PSCr behavior versus PSCr Input A in Mode 3.

DT0 OT0

DT1 OT1

DT0 OT0 DT1 OT1

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input A is taken into account during DT0 and OT0 only. It has no effect during DT1 and

OT1.

When PSCR Input A event occurs, PSCR releases PSCOUTr0, jumps and executes DT1 plus

OT1 plus DT0 while PSCR Input A is in active state.

Even if PSCR Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-

pletely executed.

Figure 13-20. PSCr behavior versus PSCr Input B in Mode 3.

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSC Input A

PSC Input B

PSCR Input B is taken into account during DT1 and OT1 only. It has no effect during DT0 and

OT0.

When PSCR Input B event occurs, PSCR releases PSCOUTR1, jumps and executes DT0 plus

OT0 plus DT1 while PSCR Input B is in active state.

Even if PSCR Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-

pletely executed.

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13.12 PSCR Input Mode 4: Deactivate outputs without changing timing

Figure 13-21. PSCR behavior versus PSCr Input A or Input B in Mode 4.

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Figure 13-22. PSCR behavior versus PSCr Input A or Input B in Fault Mode 4.

DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-

Time1.

13.13 PSCR Input Mode 5: Stop signal and Insert Dead-Time

Figure 13-23. PSCR behavior versus PSCr Input A in Fault Mode 5.

DT0 OT0

DT1

OT1

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Used in Fault mode 5, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

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13.14 PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait

Figure 13-24. PSCR behavior versus PSCr Input A in Fault Mode 6.

DT0 OT0 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Used in Fault mode 6, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

13.15 PSCR Input Mode 7: Halt PSCR and Wait for Software Action

Figure 13-25. PSCR behavior versus PSCr Input A in Fault Mode 7.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

or

PSCn Input B

Software Action (1)

Note:

1. Software action is the setting of the PRUNn bit in PCTLr register.

Used in Fault mode 7, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0

or on On-Time1/Dead-Time1.

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13.16 PSCR Input Mode 8: Edge Retrigger PSC

Figure 13-26. PSCR behavior versus PSCr Input A in Mode 8.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is modulated by the occurrence of significative edge of retriggering input.

Figure 13-27. PSCR behavior versus PSCr Input B in Mode 8.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

or

PSCn Input B

The output frequency is modulated by the occurrence of significative edge of retriggering input.

The retrigger event is taken into account only if it occurs during the corresponding On-Time.

Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSCR

doesn’t jump to the opposite dead-time.

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13.17 PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC

Figure 13-28. PSCR behavior versus PSCr Input A in Mode 9.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is not modified by the occurrence of significative edge of retriggering input.

Only the output is deactivated when significative edge on retriggering input occurs.

Note: In this mode the output of the PSCR becomes active during the next ramp even if the

Retrigger/Fault input is active. Only the significative edge of Retrigger/Fault input is taken into

account.

Figure 13-29. PSCR behavior versus PSCr Input B in Mode 9.

DT0 OT0 DT0 OT0

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

The retrigger event is taken into account only if it occurs during the corresponding On-Time.

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13.18 PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output

Figure 13-30. PSCR behavior versus PSCr Input A in Mode 14.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input A

The output frequency is not modified by the occurrence of significative edge of retriggering input.

Figure 13-31. PSCR behavior versus PSCr Input B in Mode 14.

DT0 OT0

DT1 OT1

PSCOUTn0

PSCOUTn1

PSCn Input B

The output is deactivated while retriggering input is active.

The output of the PSCR is set to an inactive state and the corresponding ramp is not aborted.

The output stays in an inactive state while the Retrigger/Fault input is active. The PSCR runs at

constant frequency.

13.18.1 Available Input Mode according to Running Mode

Some Input Modes are not consistent with some Running Modes. So Table 13-6 gives the input

modes which are valid according to running modes.

Table 13-6. Available input modes according to running modes.

Input mode number:

1 Ramp mode

Valid

2 Ramp mode

Valid

4 Ramp mode

Valid

1

2

3

4

5

6

7

8

9

Do not use

Valid

Do not use

Valid

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Table 13-6. Available input modes according to running modes. (Continued)

Input mode number:

1 Ramp mode

2 Ramp mode

4 Ramp mode

10

11

12

13

14

15

Do not use

Valid

Do not use

13.18.2 Event Capture

The PSCR can capture the value of time (PSCR counter) when a retrigger event or fault event

occurs on PSCR inputs. This value can be read by software in PICRrH/L register.

13.18.3 Using the Input Capture Unit