AT93C66AU3-10UU-2.7 [MICROCHIP]
EEPROM, 256X16, Serial, PBGA8;
| 型号： | AT93C66AU3-10UU-2.7 |
| 厂家： | 
MICROCHIP |
| 描述： | EEPROM, 256X16, Serial, PBGA8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• Sequential Read Operation
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms Max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature, and Lead-free/Halogen-free Devices
Three-wire
Serial
EEPROMs
Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2™ Packages
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
mable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-
lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball dBGA2™ packages.
AT93C56A
AT93C66A
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
Preliminary
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
8-lead SOIC
8-ball dBGA2
Pin Name
CS
Function
8
7
6
5
1
2
3
4
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
VCC
DC
CS
SK
DI
Chip Select
ORG
GND
ORG
GND
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
DO
Bottom view
DI
8-lead MAP
8-lead PDIP
DO
VCC 8
DC 7
1 CS CS
1
8
7
6
5
VCC
DC
2 SK
3 DI
SK
2
3
4
GND
VCC
ORG
DC
ORG 6
GND 5
DI
ORG
GND
4 DO DO
Power Supply
Internal Organization
Don’t Connect
Bottom view
8-lead TSSOP
CS
SK
DI
1
2
3
4
8
VCC
DC
7
6
5
ORG
GND
3378G–SEEPR–10/04
DO
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Note:
When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
2
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
CC = +1.8V to +5.5V (unless otherwise noted).
V
Symbol
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
5.5
5.5
2.0
2.0
0.1
10.0
30
Unit
V
VCC1
VCC2
VCC3
Supply Voltage
Supply Voltage
Supply Voltage
V
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V
VCC = 2.7V
CS = 0V
6.0
17
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
3.0
3.0
IOL
Output Leakage
(1)
VIL1
VIH1
Input Low Voltage
Input High Voltage
−0.6
0.8
VCC + 1
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
V
V
(1)
2.0
(1)
(1)
VIL2
Input Low Voltage
Input High Voltage
−0.6
VCC x 0.7
VCC x 0.3
CC + 1
VIH2
V
IOL = 2.1 mA
IOH = −0.4 mA
IOL = 0.15 mA
IOH = −100 µA
0.4
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
2.4
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC − 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
3378G–SEEPR–10/04
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
SK Clock
Frequency
fSK
MHz
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
Minimum CS
Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
200
tCSS
CS Setup Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tPD1
tPD0
tSV
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
CS to DO in High
Impedance
AC Test
CS = VIL
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
150
400
tDF
1.8V ≤ VCC ≤ 5.5V
0.1
1M
3
10
ms
tWP
Write Cycle Time
5.0V, 25°C
Endurance(1)
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
Table 5. Instruction Set for the AT93C56A and AT93C66A
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address.
READ
1
10
A8 – A0
A7 – A0
Write enable must precede all
programming modes.
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
WRITE
1
1
11
01
A8 – A0
A8 – A0
A7 – A0
A7 – A0
Erases memory location An – A0.
Writes memory location An – A0.
D7 – D0
D15 – D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
ERAL
1
00
10XXXXXXX
10XXXXXX
Writes all memory locations. Valid
only at VCC = 5.0V 10% and Disable
Register cleared.
WRAL
EWDS
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
D7 – D0
D15 – D0
Disables all programming instructions.
Note:
The Xs in the address field represent don’t care values and must be clocked.
Functional Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a Start
Bit (logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase instruction programs all bits in the specified memory loca-
tion to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction
and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is
brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO
indicates that the selected memory location has been erased, and the part is ready for
another instruction.
5
3378G–SEEPR–10/04
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
1. This is the minimum SK period.
6
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
Table 6. Organization Key for Timing Diagrams
AT93C56A (2K)
AT93C66A (4K)
I/O
AN
DN
x 8
x 16
x 8
A8
x 16
A7
(1)
(2)
A8
D7
A7
D15
D7
D15
Notes: 1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
Figure 3. READ Timing
tCS
High Impedance
Figure 4. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
7
3378G–SEEPR–10/04
Figure 5. EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
Figure 6. WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
Figure 7. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
8
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
Figure 9. ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
3378G–SEEPR–10/04
AT93C56A Ordering Information
Ordering Code
Package
Operation Range
AT93C56A-10PI-2.7
AT93C56A-10SI-2.7
AT93C56AW-10SI-2.7
AT93C56A-10TI-2.7
AT93C56AU3-10UI-2.7
AT93C56AY1-10YI-2.7
8P3
8S1
8S2
Industrial Temperature
8A2
(−40°C to 85°C)
8U3-1
8Y1
AT93C56A-10PI-1.8
AT93C56A-10SI-1.8
AT93C56AW-10SI-1.8
AT93C56A-10TI-1.8
AT93C56AU3-10UI-1.8
AT93C56AY1-10YI-1.8
8P3
8S1
8S2
Industrial Temperature
8A2
(−40°C to 85°C)
8U3-1
8Y1
AT93C56A-10PU-2.7
AT93C56A-10PU-1.8
AT93C56A-10SU-2.7
AT93C56A-10SU-1.8
AT93C56A-10TU-2.7
AT93C56A-10TU-1.8
AT93C56AU3-10UU-2.7
AT93C56AU3-10UU-1.8
AT93C56AY1-10YU-2.7
AT93C56AY1-10YU-1.8
8P3
8P3
8S1
8S1
8A2
8A2
8A2
8A2
8Y1
8Y1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8S2
8A2
8U3-1
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7
Low-voltage (2.7V to 5.5V)
1.8
Low-voltage (1.8V to 5.5V)
10
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
AT93C66A Ordering Information
Ordering Code
Package
Operation Range
AT93C66A-10PI-2.7
AT93C66A-10SI-2.7
AT93C66AW-10SI-2.7
AT93C66A-10TI-2.7
AT93C66AU3-10UI-2.7
AT93C66AY1-10YI-2.7
8P3
8S1
8S2
Industrial
8A2
(−40°C to 85°C)
8U3-1
8Y1
AT93C66A-10PI-1.8
AT93C66A-10SI-1.8
AT93C66AW-10SI-1.8
AT93C66A-10TI-1.8
AT93C66AU3-10UI-1.8
AT93C66AY1-10YI-1.8
8P3
8S1
8S2
Industrial
8A2
(−40°C to 85°C)
8U3-1
8Y1
AT93C66A-10PU-2.7
AT93C66A-10PU-1.8
AT93C66A-10SU-2.7
AT93C66A-10SU-1.8
AT93C66A-10TU-2.7
AT93C66A-10TU-1.8
AT93C66AU3-10UU-2.7
AT93C66AU3-10UU-1.8
AT93C66AY1-10YU-2.7
AT93C66AY1-10YU-1.8
8P3
8P3
8S1
8S1
Lead-free/Halogen-free/
Industrial Temperature
8A2
8A2
(−40°C to 85°C)
8U3-1
8U3-1
8Y1
8Y1
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8S2
8A2
8U3-1
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
−2.7
−1.8
Low-voltage (2.7V to 5.5V)
Low-voltage (1.8V to 5.5V)
11
3378G–SEEPR–10/04
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
13
3378G–SEEPR–10/04
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0˚
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8˚
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
∅
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
14
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
15
3378G–SEEPR–10/04
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side View
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
MIN
0.71
0.10
0.40
0.20
MAX
0.91
0.20
0.50
0.30
NOM
0.81
NOTE
SYMBOL
Bottom View
8 SOLDER BALLS
A
A1
A2
b
0.15
0.45
0.25
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
1. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
PO8U3-1
A
R
Small Die Ball Grid Array Package (dBGA2)
16
AT93C56A/66A
3378G–SEEPR–10/04
AT93C56A/66A
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
Bottom View
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
Side View
E
D1
E1
b
e
L
0.50
0.70
2/28/03
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
C
R
17
3378G–SEEPR–10/04
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