ATF1502AS-10AU44-T [MICROCHIP]
EE PLD, 10ns, PQFP44;
| 型号： | ATF1502AS-10AU44-T |
| 厂家： | 
MICROCHIP |
| 描述： | EE PLD, 10ns, PQFP44 |
| 文件： | 总29页 (文件大小：952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATF1502AS and ATF1502ASL
High-performance EEPROM
Complex Programmable Logic Device
DATASHEET
Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
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32 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
44 Pins
7.5ns Maximum Pin-to-pin Delay
Registered Operation up to 125MHz
Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
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D/T Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open Collector Option
Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
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Automatic 10μA Standby for “L” Version
Pin-controlled 1mA Standby Mode
Programmable Pin-keeper Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and 44-lead TQFP
Advanced EEPROM Technology
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100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993
Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-fee/RoHS Compliant) Package Options
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
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Input Transition Detection
Power-down (“L” Versions)
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs, and I/O
Description
The Atmel® ATF1502AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD)
which utilizes the Atmel proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it
easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1502AS(L)’s enhanced
routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1502AS(L) has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can serve as a global control signal, register clock, register reset,
or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 32 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin
also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the
global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic
between macrocells in the ATF1502AS(L) allows fast, efficient generation of complex logic functions. The
ATF1502AS(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to
40 product terms.
The ATF1502AS(L) macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions
operating at high speed. The macrocell consists of five sections:
Product Terms and Product Term Select Multiplexer
OR/XOR/CASCADE Logic
Flip-flop
Output Select and Enable
Logic Array Inputs
2
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Figure 1.
ATF1502AS(L) Macrocell
SWITCH REGIONAL
MATRIX FOLDBACK
OUTPUTS
BUS
LOGIC
FOLDBACK
CASIN
GOE[0:5]
MOE
I/O Pin
I/O Pin
GCK[0:2]
PTMUX
SLEW
RATE
OPEN COLLECTOR
OPTION
GCLEAR-
MACROCELL REDUCED POWER BIT
CASOUT
GLOBAL BUS
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
3
1.
Pin Configurations and Pinouts
Figure 1-1.
Pinouts
44-lead TQFP
(Top View)
44-lead PLCC
(Top View)
TDI/I/O
I/O
7
8
9
39 I/O
I/O/TDI
I/O
1
33 I/O
38 I/O/TDO
37 I/O
2
3
4
5
6
7
8
9
32 I/O/TDO
31 I/O
I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
GND
PD1/I/O
I/O
30 I/O
35 VCC
34 I/O
29 VCC
28 I/O
I/O/TMS 13
I/O 14
33 I/O
TMS/I/O
I/O
27 I/O
32 I/O/TCK
31 I/O
26 I/O/TCK
25 I/O
VCC 15
I/O 16
VCC
30 GND
29 I/O
I/O 10
I/O 11
24 GND
23 I/O
I/O 17
44-lead TQFP
Top View
44-lead PLCC
Top View
4
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
2.
Block Diagram
Figure 2-1.
Block Diagram
Logic Block A
Macrocells
1 to 16
Logic Block B
I/O Pins
I/O Pins
Output
Enable
Switch
Matrix
GOE[0:5]
Global
Clock
Mux
I/O (MC32)/GCLK3
GCK[0:2]
OE1/INPUT
INPUT/GCLK1
INPUT/OE2/GCLK2
Global
Clear
Mux
GCLEAR
INPUT/GCLR
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the contents of the ATF1502AS(L). Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
The ATF1502AS(L) device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin
JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language
(BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition
to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
5
3.
Macrocell Sections
Table 3-1.
Section
Macrocell Sections
Description
Each ATF1502AS(L) macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
Product Terms and
Select Mux
The Product Term Select Multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
The ATF1502AS(L) logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with little additional delay.
OR/XOR/CASCADE
Logic
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity
selection. For registered functions, the fixed levels allow DeMorgan minimization of product
terms. The XOR gate is also used to emulate T-type and JK-type flip-flops.
The ATF1502AS(L) flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term, or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically implemented by the fitter software). In addition to
D, T, JK, and SR operation, the flip-flop can be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low.
Flip-flop
The clock itself can be either one of the Global CLK signals (GCK[0:2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s Asynchronous Reset (AR) signal can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
Asynchronous Preset (AP) can be a product term or always off.
The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The extra
buried feedback signal can be either combinatorial or a registered signal regardless of whether
the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the
creation of a second latch within a macrocell.
I/O Control: The Output Enable Multiplexer (MOE) controls the output enable signal.
Each I/O can be individually configured as an input, output, or for bi-directional
operation. The output enable for each macrocell can be selected from the true or
compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O
macrocells. This selection is automatically done by the fitter software when the I/O is
configured as an input, all macrocell resources are still available, including the buried
feedback, expander, and cascade logic.
Extra Feedback
The global bus contains all input and I/O pin signals as well as the buried feedback signal from all
32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
Global Bus/Switch
Matrix
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The four foldback terms in each region allow generation of high fan-in sum terms
(up to nine product terms) with little additional delay.
Foldback Bus
6
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
4.
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1502AS(L) offers the option of programming all input and I/O pins so the pin-keeper circuits can be
utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or
low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which
causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external
pull-up resistors and eliminate their DC power consumption.
Figure 4-1.
Input Diagram
VCC
Input
100K
ESD
Protection
Circuit
Programmable
Option
Figure 4-2.
I/O Diagram
VCC
OE
I/O
Data
VCC
100K
Programmable
Option
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
7
5.
Speed/Power Management
The ATF1502AS(L) has several built-in speed and power management features. The ATF1502AS(L) contains
circuitry which automatically puts the device into a low-power standby mode when no logic transitions are occurring.
This not only reduces power consumption during inactive periods, but also provides proportional power savings for
most applications running at system speeds below 50MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS(L) macrocell has a reduced-power bit feature. This feature allows
individual macrocells to be configured for maximum power savings. This feature may be selected as a design
option.
The ATF1502AS(L) also has an optional power-down mode. In this mode, current drops to below 10mA. When
the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The
power-down option is selected in the design source file. When enabled, the device goes into power-down when
either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1
or PD2 pin cannot be used as a logic input or output; however, the pin’s macrocell may still be used to generate
buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder,
t
RPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH, and tSEXP.
The ATF1502AS(L) macrocell also has an option whereby the power can be reduced on a per-macrocell basis.
By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby
reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by slowing down
outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified
as fast switching in the design file.
6.
7.
Design Software Support
ATF1502AS(L) designs are supported by several third-party tools. Automated fitters allow logic synthesis using
a variety of high-level description languages and formats.
Power-up Reset
The ATF1502AS(L) is designed with a power-up reset, a feature critical for state machine initialization. At a
point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will
depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how
VCC actually rises in the system, the following conditions are required:
The VCC rise must be monotonic,
After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,
The clock must remain stable during TD.
The ATF1502AS(L) has two options for the hysteresis about the reset level, VRST, Small and Large. During the
fitting process, users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel
POF2JED users may select the Large option by including the flag “-power_reset” on the command line after
“filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the
following condition is added:
If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro amps as well.
8
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
8.
9.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1502AS(L) fuse patterns. Once
programmed, fuse verify is inhibited; however, the 16-bit User Signature remains accessible.
Programming
ATF1502AS(L) devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This
capability eliminates package handling normally required for programming and facilitates rapid design iterations
and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1502AS(L) via the PC. ISP is
performed by using either a download cable, a comparable board tester, or a simple microprocessor interface.
When using the ISP hardware or software to program the ATF1502AS(L) devices, four I/O pins must be
reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O
pins are still available to the design for burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF)
files can be created by Atmel-provided software utilities.
ATF1502AS(L) devices can also be programmed using standard third-party programmers. With a third-party
programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
10. ISP Programming Protection
The ATF1502AS(L) has a special feature which locks the device and prevents the inputs and I/O from driving if
the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a
condition. In addition, the pin-keeper option preserves the previous state of the input and I/O PMS during
programming.
All ATF1502AS(L) devices are initially shipped in the erased state, thereby making them ready to use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
9
11. Electrical Characteristics
11.1 Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is a
stress rating only and functional operation of
the device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on Input Pins with Respect
to Ground During Programming . . . . . . . . . . -2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6VDC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin
voltage is VCC + 0.75VDC, which may overshoot to 7.0V for pulses of less than 20ns.
11.2 Pin Capacitance
Table 11-1.
Pin Capacitance(1)
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1MHz
VOUT = 0V; f = 1MHz
CI/O
8
10
pF
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12pF.
11.3 DC and AC Operating Conditions
Table 11-2.
DC and AC Operating Conditions
Commercial
0C to 70C
5V± 5%
Industrial
-40C to 85C
5V± 10%
Operating Temperature (Ambient)
VCC (5.0V) Power Supply
10
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
11.4 DC Characteristics
Table 11-3.
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
VIN = VCC
-2
-10
μA
Input or I/O High
Leakage Current
IIH
2
10
40
Tri-state Output
Off-state Current
IOZ
VO = VCC or GND
-40
μA
mA
mA
μA
μA
mA
mA
mA
V
Com.
Ind.
60
75
10
10
1
Std Mode
Power Supply Current,
Standby
VCC = Max
IN = 0, VCC
ICC1
V
Com.
Ind.
“L” Mode
“PD” Mode
Std Mode
Power Supply Current,
Power-down Mode
VCC = Max
IN = 0, VCC
ICC2
5
V
Com.
Ind.
35
40
Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
(2)
ICC3
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
2.0
3.0
0.8
VCCIO + 0.3
0.45
V
Com.
Ind.
V
VIN = VIH or VIL
Output Low Voltage (TTL)
VCC = Min, IOL = 12mA
0.45
VOL
Com.
Ind.
0.2
V
V
V
VIN = VIH or VIL
VCC = Min, IOL = 0.1mA
Output Low Voltage (CMOS)
Output High Voltage (TTL)
0.2
VIN = VIH or VIL
VCC = Min, IOH = -4.0mA
VOH
2.4
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s.
2.
I
CC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
11
11.5 AC Characteristics
Table 11-4.
AC Characteristics(11.9)
-7
-10
-25
Symbol
tPD1
tPD2
tSU
Parameter
Min
Max Min Max
Min
Max Units
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
7.5
7
10
9
25
25
ns
ns
6
0
7
0
20
0
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
3
3
5
ns
0.5
0.5
2
MHz
ns
4.5
5
13
3
3
3
2
4
4
3
3
7
7
5
6
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
fCNT
tACNT
fACNT
fMAX
tIN
Array Clock Output Delay
Array Clock High Time
7.5
10
25
ns
3
3
4
4
10
10
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
8
8
10
10
22
22
ns
125
100
50
MHz
ns
125
100
125
50
60
MHz
MHz
ns
166.7
0.5
0.5
1
0.5
0.5
1
2
2
tIO
ns
tFIN
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Foldback Term Delay
4
5
12
2
ns
Cascade Logic Delay
0.8
3
0.8
5
ns
Logic Array Delay
8
ns
Logic Control Delay
3
5
8
ns
Internal Output Enable Delay
2
2
4
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCC = 5.0V; CL = 35pF)
tOD1
2
1.5
6
ns
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in
the reduced-power mode.
12
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Table 11-4.
AC Characteristics(11.9) (Continued)
Parameter
-7
-10
-25
Symbol
Min
Max Min Max
Min
Max Units
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35pF)
tZX1
4.0
4.5
5.0
5.5
10
10
ns
ns
ns
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35pF)
tZX2
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35pF)
tZX3
9
4
9
5
12
8
tXZ
Output Buffer Disable Delay (CL = 5pF)
Register Setup Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
3
2
3
3
6
6
3
5
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
3
3
0.5
0.5
tRD
1
1
2
2
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
3
5
8
tEN
Register Enable Time
Global Control Delay
3
5
8
tGLOB
tPRE
tCLR
tUIM
tRPA
1
1
1
Register Preset Time
2
3
6
Register Clear Time
2
3
6
Switch Matrix Delay
1
1
2
Reduced-power Adder(2)
10
11
15
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in
the reduced-power mode.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
13
11.6 Timing Model
Figure 11-1. Timing Model
Internal Output
Enable Delay
tIOE
Global Control
Delay
Input
Delay
tIN
Register
Delay
tSU
tGLOB
Cascade Logic
Delay
Output
Delay
tOD1
tOD2
tOD3
tXZ
Logic Array
Delay
tPEXP
Switch
Matrix
tUIM
tH
tLAD
tPRE
tCLR
tRD
tCOMB
tFSU
tFH
Register Control
Delay
tLAC
tIC
tZX1
Fast
Input Delay
tFIN
tZX2
tEN
tZX3
Foldback Term
Delay
I/O
Delay
tIO
tSEXP
11.7 Input Test Waveforms and Measurement Levels
Figure 11-2. Input Test Waveforms and Measurement Levels
3.0V
AC
AC
Driving
Levels
1.5V
Measurement
Level
0.0V
tR, tF = 1.5ns typical
Note:
11.8 Output AC Test Loads
Figure 11-3. Output AC Test Loads
5.0V
R1 = 464Ω
Output
Pin
R2 = 250Ω
CL = 35pF
14
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
11.9 Power-down Mode
The ATF1502AS(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than
5mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered
and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at
high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure the pins do not float to indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file. Designs using the power-down pin may not use the
PD pin logic array input; however, all other PD pin macrocell resources may still be used, including the buried
feedback and foldback product term array inputs.
11.9.1 Power-down AC Characteristics
Table 11-5.
Power-down AC Characteristics(1)(2)
-7
-10
-25
Symbol
tIVDH
Parameter
Min
7
Max
Min
10
Max
Min
25
Max
Units
ns
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
tGVDH
tCVDH
tDHIX
7
10
25
ns
7
10
25
ns
12
12
12
1
15
15
15
1
35
35
35
1
ns
tDHGX
tDHCX
tDLIV
ns
ns
μs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
μs
1
1
1
μs
1
1
1
μs
Notes: 1. For slow slew outputs, add tSSO
2. Pin or product term.
.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
15
12. JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS(L).
The boundary-scan technique involves the inclusion of a shift-register stage (contained in a Boundary-Scan
Cell) adjacent to each component so signals at component boundaries can be controlled and observed using
scan testing methods. Each input pin and I/O pin has its own Boundary-Scan Cell (BSC) to support
Boundary-Scan Testing (BST). The ATF1502AS(L) does not include a Test Reset (TRST) input pin because the
TAP controller is automatically reset at power-up. The five JTAG modes supported include:
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
HIGHZ
The ATF1502AS(L) ISP can fully be described using JTAG’s BSDL as described in IEEE Standard 1149.1b.
This allows ATF1502AS(L) programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502AS(L) has the option of using four JTAG-standard I/O pins for BST and ISP purposes. The
ATF1502AS(L) is programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface
for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed,
then the four JTAG control pins are available as I/O pins.
13. JTAG Boundary-scan Cell (BSC) Testing
The ATF1502AS(L) contains up to 32 I/O pins and four input pins, depending on the device type and package
type selected. Each input pin and I/O pin has its own BSC in order to support BST as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update
registers. There are two types of BSCs, one for input or I/O pin and one for the macrocells. The BSCs in the
device are chained together through the capture registers. Input to the capture register chain is fed in from the
TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data
signals, to shift data in and out of the device, and to load data into the update registers. Control signals are
generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 13-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Dedicated
Input
To Internal Logic
0
D
Q
TDO
1
Capture
Registers
Clock
Shift
TDI
(From Next Register)
Note:
1. The ATF1502AS(L) has a pull-up option on TMS and TDI pins. This feature is selected as a design option.
16
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Figure 13-2. BSC Configuration for Macrocell
TDO
0
1
D
Q
TDI
CLOCK
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
BSC for I/O Pins and Macrocells
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
17
14. PCI Compliance
The ATF1502AS(L) supports the growing need in the industry to support the new Peripheral Component
Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high
current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel
outputs to support the high current load required by the PCI interface. The ATF1502AS(L) allows this without
contributing to system noise while delivering low output to output skew. Having a programmable high drive
option is also possible without increasing output delay or pin capacitance.
Figure 14-1. PCI Voltage-to-current Curves for
+5.0V Signaling in Pull-up Mode
Figure 14-2. PCI Voltage-to-current Curves for
+5.0V Signaling in Pull-down Mode
Pull Down
Pull Up
VCC
VCC
Test Point
AC drive
point
2.4
2.2
DC
drive point
DC
drive point
1.4
0.55
AC drive
point
Test Point
Current (mA)
Current (mA)
95
3,6
380
-44
-2
-178
Table 14-1.
PCI DC Characteristics
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
Units
V
Supply Voltage
Input High Voltage
Input Low Voltage
5.25
VCC + 0.5
0.8
V
VIL
-0.5
V
IIH
Input High Leakage Current(1)
Input Low Leakage Current(1)
Output High Voltage
VIN = 2.7V
70
μA
μA
V
IIL
VIN = 0.5V
-70
VOH
VOL
CIN
IOUT = -2mA
IOUT = 3mA, 6mA
2.4
Output Low Voltage
0.55
10
12
8
V
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
1. Leakage current is with pin-keeper off.
18
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Table 14-2.
Symbol
PCI AC Characteristics
Parameter
Conditions
Min
-44
Max
Units
mA
mA
mA
μA
0 < VOUT 1.4
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
Switching
Current High
(Test High)
-44 + (VOUT - 1.4)/0.024
IOH(AC)
Equation A
-142
VOUT >2.2V
95
mA
mA
mA
mA
mA
V/ns
V/ns
Switching
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT = 0.71
VOUT/0.023
IOL(AC)
Current Low
(Test Point)
Equation B
206
ICL
Low Clamp Current
-5 < VIN -1
-25 + (VIN + 1)/0.015
SLEWR
SLEWF
Output Rise Slew Rate
Output Fall Slew Rate
0.4V to 2.4V Load
2.4V to 0.4V Load
1
1
5
5
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
19
15. Pinouts
15.1 ATF1502AS(L) Dedicated Pinouts
44-lead
TQFP
44-lead
J-lead
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
40
2
39
1
38
44
INPUT/GCLK1
I/O / GCLK3
37
43
35
41
I/O / PD (1,2)
I/O / TDI (JTAG)
I/O / TMS (JTAG)
I/O / TCK (JTAG)
I/O / TDO (JTAG)
GND
5, 19
11, 25
1
7
7
13
26
32
32
4, 16, 24, 36
9, 17, 29, 41
36
38
10, 22, 30, 42
3, 15, 23, 35
36
VCC
# of Signal Pins
# User I/O Pins
32
32
Note:
OE (1, 2) . . . . . . . . . . . . . Global OE pins
GCLR . . . . . . . . . . . . . . . Global Clear pin
GCLK (1, 2, 3). . . . . . . . . Global Clock pins
PD (1, 2) . . . . . . . . . . . . . Power-down pins
TDI, TMS, TCK, TDO . . . JTAG pins used for boundary-scan testing or in-system programming
GND . . . . . . . . . . . . . . . . Ground pins
VCC . . . . . . . . . . . . . . . . . VCC pins for the device (+5V)
20
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
15.2 ATF1502AS(L) I/O Pinouts
MC
1
PLC
A
44-lead PLCC
44-lead TQFP
4
42
43
44
1
2
A
5
3
A/PD1
A
6
4/TDI
5
7
A
8
2
6
A
9
3
7
A
11
12
13
14
16
17
18
19
20
21
41
40
39
38
37
36
34
33
32
31
29
28
27
26
25
24
5
8
A
6
9/TMS
10
A
7
A
8
11
A
10
11
12
13
14
15
35
34
33
32
31
30
28
27
26
25
23
22
21
20
19
18
12
A
13
A
14
A
15
A
16
A
17
B
18
B
19
B
20/TDO
21
B
B
22
B
23
B
24
B
25/TCK
26
B
B
27
B
28
B
29
B
30
B
31
B
32
B
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
21
22
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
ATF1502AS(L) [DATASHEET]
23
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
24
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
16. Ordering Information
16.1 Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
44A
Operation Range
ATF1502AS-7AX44
ATF1502AS-7JX44
ATF1502AS-10AU44
ATF1502AS-10JU44
Commercial
(0C to 70C)
7.5
10
4.5
5
166.7
125
44J
44A
Industrial
(-40C to +85C)
44J
ATF1502ASL-25AU44
ATF1502ASL-25JU44
44A
44J
Industrial
(-40C to +85C)
25
13
60
Package Type
44A
44J
44-lead, Thin Plastic Gull Wing Quad Flatpack Package (TQFP)
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
25
17. Packaging Information
17.1 44A — 44-lead TQFP
D1
D
e
E
E1
b
BOTTOM VIEW
TOP VIEW
C
0°~7°
A2
A1
A
L
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
E1
B
10.10 Note 2
0.45
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
L
–
0.75
3. Lead coplanarity is 0.10 mm maximum.
e
0.80 TYP
1/10/13
TITLE
DRAWING NO.
REV.
GPC
AIX
44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm
Lead Pitch, Thin Profile Plastic Quad Flat
Package (TQFP)
44A
D
Package Drawing Contact:
packagedrawings@atmel.com
26
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
17.2 44J — 44-lead PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO. REV.
44J
Package Drawing Contact:
packagedrawings@atmel.com
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
27
18. Revision History
Revision
0995L
Date
Comments
Remove lead based package offering and 15ns speed grade.
Update template, logos, and disclaimer page.
Green package options added.
03/2014
06/2005
0995K
28
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
X
X X X X
X
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014.
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