ATF1504ASV-15JU44-T [MICROCHIP]
EE PLD;
| 型号： | ATF1504ASV-15JU44-T |
| 厂家： | 
MICROCHIP |
| 描述： | EE PLD 时钟 输入元件 可编程逻辑 |
| 文件： | 总30页 (文件大小：847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATF1504ASV/ATF1504ASVL
ATF1504ASV(L) 3.3V 64-Macrocell CPLD Data Sheet
Features
Enhanced Features
• High-Density, High-Performance, Electri-
cally-Erasable Complex Programmable Logic
Device:
• Improved Connectivity (Additional Feedback
Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent-Latch Mode
- 3.0V to 3.6V operating range
- 64 macrocells
• Combinatorial Output with Registered Feedback
within any Macrocell
- 5 product terms per macrocell, expandable
up to 40 per macrocell
• Three Global Clock Pins
- 44 and 100 pins
• ITD (Input Transition Detection) Circuits on Global
Clocks, Inputs and I/O
- 15 ns maximum pin-to-pin delay
- Registered operation up to 77 MHz
- Enhanced routing resources
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-Up Reset Option
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell:
• Pull-Up Option on JTAG Pins (TMS and TDI)
• Advanced Power Management Features:
- D/T/Latch configurable flip-flops
- Global and individual register control signals
- Global and individual output enable
- Programmable output slew rate
- Programmable output open-collector option
- Edge-controlled power-down
(ATF1504ASVL)
- Individual macrocell power option
- Disable ITD on global clocks
- Maximum logic utilization by burying a regis-
ter with a COM output
Packages
• Advanced Power Management Features:
- Automatic 5 µA Standby (ATF1504ASVL)
- Pin-controlled 100 µA Standby mode (typical)
• 44-Lead PLCC
• 44-Lead and 100-Lead TQFP
- Programmable pin-keeper circuits on inputs
and I/Os
Description
The ATF1504ASV(L) is a high-performance, high-den-
sity complex programmable logic device (CPLD) that
utilizes Microchip’s proven electrically-erasable mem-
ory technology. With 64 logic macrocells and up to
68 inputs and I/Os, it easily integrates logic from sev-
eral TTL, SSI, MSI, LSI and classic PLDs. The
ATF1504ASV(L)’s enhanced routing switch matrices
increase usable gate count and the odds of successful
pin-locked design modifications.
- Reduced-power feature per macrocell
• Available in Industrial Temperature Range
• Robust EEPROM Technology:
- 100% tested
- Completely reprogrammable
- 10,000 Program/Erase cycles
- 20-year data retention
- 2000V ESD protection
The ATF1504ASV(L) has up to 64 bidirectional I/O pins
and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can also
serve as a global control signal (register clock, register
Reset or output enable). Each of these control signals
can be selected for use individually within each
macrocell.
- 200 mA latch-up immunity
• JTAG Boundary-Scan Testing to IEEE Std.
1149.1-1990 and 1149.1a-1993 Supported
• PCI-Compliant
• Security Fuse Feature
• Green (Pb/Halide-Free/RoHS Compliant)
Package Options
2019 Microchip Technology Inc.
DS20006185A-page 1
ATF1504ASV/ATF1504ASVL
Each of the 64 macrocells generates a buried feedback
that goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each
logic block then selects 40 individual signals from the
global bus. Each macrocell also generates a foldback
logic term that goes to a regional bus.
Cascade logic between macrocells in the ATF1504-
ASV(L) allows fast, efficient generation of complex
logic functions. The ATF1504ASV(L) contains four
such logic chains, each capable of creating sum term
logic with a fan-in of up to 40 product terms.
The ATF1504ASV(L) macrocell (see ATF1504ASV(L)
Macrocell), is flexible enough to support highly complex
logic functions operating at high speed. The macrocell
consists of five sections: product terms and product
term select multiplexer, OR/XOR/CASCADE logic, a
flip-flop, output select and enable, and logic array
inputs.
ATF1504ASV(L) Macrocell
2019 Microchip Technology Inc.
DS20006185A-page 2
ATF1504ASV/ATF1504ASVL
Pin Configurations and Pinouts
44-Lead PLCC
44-Lead TQFP
(Top View)
(Top View)
I/O
I/O
I/O
PD2/I/O
I/O
Vcc
GND
I/O
I/O
I/O
I/O 34
GCLK3/I/O 35
GND 36
GCLK1/I 37
I/OE1 38
GCLR/I 39
GCLK2/OE2/I 40
Vcc 41
22
21
20
19
18
17
16
15
14
13
12
TDI/I/O
I/O
7
8
9
39 I/O
38 I/O/TDO
37 I/O
I/O
GND 10
PD1/I/O 11
I/O 12
I/O/TMS 13
I/O 14
36 I/O
35
VCC
34 I/O
33 I/O
32 I/O/TCK
31 I/O
30 GND
29 I/O
I/O 42
I/O 43
I/O 44
VCC
I/O 16
I/O 17
15
I/O
100-Lead TQFP
(Top View)
I/O
NC
NC
I/O 79
I/O 80
I/O 81
76
77
78
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
NC
NC
I/O
I/O
I/O
I/O
I/O
GND
I/O/PD2
I/O
VCCIO
I/O 83
I/O 84
I/O/GCLK3 85
GND 86
82
I/O
NPUT/GCLK1 87
INPUT/OE1 88
INPUT/GCLR 89
INPUT/OE2/GCLK2 90
VCCINT
GND
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
VCCINT
91
I/O 92
I/O 93
I/O 94
GND 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100
I/O
NC
NC
GND
2019 Microchip Technology Inc.
DS20006185A-page 3
ATF1504ASV/ATF1504ASVL
Block Diagram
Unused product terms are automatically disabled by
the compiler to decrease power consumption. A secu-
rity fuse, when programmed, protects the contents of
the ATF1504ASV(L). Two bytes (16 bits) of User
Signature are accessible to the user for purposes such
as storing project name, part number, revision or date.
The User Signature is accessible regardless of the
state of the security fuse.
The ATF1504ASV(L) device is an in-system
programmable
(ISP)
device.
It
uses
the
industry-standard 4-pin JTAG interface (IEEE Std.
1149.1), and is fully compliant with JTAG’s
Boundary-scan Description Language (BSDL). ISP
allows the device to be programmed without removing
it from the printed circuit board. In addition to
simplifying the manufacturing flow, ISP also allows
design modifications to be made in the field via
software.
2019 Microchip Technology Inc.
DS20006185A-page 4
ATF1504ASV/ATF1504ASVL
PRODUCT TERMS AND SELECT MUX
EXTRA FEEDBACK
Each ATF1504ASV(L) macrocell has five product
terms. Each product term receives as its inputs all
signals from both the global bus and regional bus.
The ATF1504ASV(L) macrocell output can be selected
as registered or combinatorial. The extra buried feed-
back signal can be either combinatorial or a registered
signal regardless of whether the output is combinatorial
or registered. (This enhancement function is automati-
cally implemented by the fitter software.) Feedback of
a buried combinatorial output allows the creation of a
second latch within a macrocell.
The product term select multiplexer (PTMUX) allocates
the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the
optimum macrocell configuration.
I/O CONTROL
OR/XOR/CASCADE LOGIC
The output enable multiplexer (MOE) controls the
output enable signal. Each I/O can be individually
configured as an input, output or for bidirectional
operation. The output enable for each macrocell can be
selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the
I/O macrocells. This selection is automatically done by
the fitter software when the I/O is configured as an
input, all macrocell resources are still available,
including the buried feedback, expander and cascade
logic.
The ATF1504ASV(L)’s logic structure is designed to
efficiently support all types of logic. Within a single
macrocell, all the product terms can be routed to the
OR gate, creating a 5-input AND/OR sum term. With
the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms
with little additional delay.
The macrocell’s XOR gate allows efficient implementa-
tion of compare and arithmetic functions. One input to
the XOR comes from the OR sum term. The other XOR
input can be a product term or a fixed high- or low-level.
For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed
levels allow DeMorgan minimization of product terms.
The XOR gate is also used to emulate T- and JK-type
flip-flops.
GLOBAL BUS/SWITCH MATRIX
The global bus contains all input and I/O pin signals as
well as the buried feedback signal from all
64 macrocells. The switch matrix in each logic block
receives as its inputs all signals from the global bus.
Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
FLIP-FLOP
The ATF1504ASV(L)’s flip-flop has very flexible data
and control functions. The data input can come from
either the XOR gate, from a separate product term or
directly from the I/O pin. Selecting the separate product
term allows creation of a buried registered feedback
within a combinatorial output macrocell. (This feature is
automatically implemented by the fitter software).
FOLDBACK BUS
Each macrocell also generates a foldback product
term. This signal goes to the regional bus and is
available to four macrocells. The foldback is an inverse
polarity of one of the macrocell’s product terms. The
four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with
little additional delay.
In addition to D, T, JK and SR operation, the flip-flop
can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and
is latched when the clock is low.
Programmable Pin-Keeper Option for
Inputs and I/Os
The clock itself can either be one of the Global CLK
Signal (GCK[0:2]) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When
the GCK signal is used as the clock, one of the macro-
cell product terms can be selected as a clock enable.
When the clock enable function is active and the
enable signal (product term) is low, all clock edges are
ignored. The flip-flop’s asynchronous Reset signal (AR)
can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous pre-
set (AP) can be a product term or always off.
The ATF1504ASV(L) offers the option of programming
all input and I/O pins so that pin-keeper circuits can be
utilized. When any pin is driven high or low and then
subsequently left floating, it will stay at that previous
high or low level. This circuitry prevents unused input
and I/O lines from floating to intermediate voltage
levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their
DC power consumption.
2019 Microchip Technology Inc.
DS20006185A-page 5
ATF1504ASV/ATF1504ASVL
Input Diagram
I/O Diagram
All ATF1504ASV(L) also have an optional Power-Down
mode. In this mode, current drops to below 5 mA.
Speed/Power Management
The ATF1504ASV(L) has several built-in speed and
power management features. The ATF1504ASVL con-
tains circuitry that automatically puts the device into a
low-power Standby mode when no logic transitions are
occurring. This not only reduces power consumption
during inactive periods, but also provides proportional
power savings for most applications running at system
speeds below 5 MHz.
When the power-down option is selected, either PD1 or
PD2 pins (or both) can be used to power down the part.
The power-down option is selected in the design
software or design source file. When enabled, the
device goes into power-down when either PD1 or PD2
is high. In the Power-Down mode, all internal logic
signals are latched and held, as are any enabled
outputs.
To further reduce power, each ATF1504ASV(L) macro-
cell has a reduced-power bit feature. This feature
allows individual macrocells to be configured for maxi-
mum power savings. This feature may be selected as
a design option.
All pin transitions are ignored until the PD pin is brought
low. When the power-down feature is enabled, the PD1
or PD2 pin cannot be used as a logic input or output.
However, the pin’s macrocell may still be used to gen-
erate buried foldback and cascade logic signals.
2019 Microchip Technology Inc.
DS20006185A-page 6
ATF1504ASV/ATF1504ASVL
All power-down AC characteristic parameters are com-
When the Large hysteresis option is active, ICC is
reduced by several hundred microamps as well.
puted from external input or I/O pins, with
reduced-power bit turned on. For macrocells in
Reduced-Power mode (reduced-power bit turned on),
the reduced-power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD,
tLAC, tIC, tACL or tACH, tEN and tSEXP.
Details on the power Reset hysteresis feature are avail-
able in the “ATF15XX Power-on Reset Hysteresis Fea-
ture” application note.
Security Fuse Usage
The ATF1504ASV(L) macrocell also has an option
whereby the power can be reduced on a per macrocell
basis. By enabling this power-down option, macrocells
that are not used in an application can be turned down,
thereby reducing the overall power consumption of the
device. This option is automatically set by the device
fitter software.
A single fuse is provided to prevent unauthorized copy-
ing of the ATF1504ASV(L) fuse patterns. Once pro-
grammed, fuse verify is inhibited. However, the 16-bit
User Signature remains accessible.
Programming
Each output also has individual slew rate control. This
may be used to reduce system noise by slowing down
outputs that do not need to operate at maximum speed.
Outputs default to slow switching, and may be specified
as fast switching in the design software or design file.
ATF1504ASV(L) devices are in-system programmable
(ISP) devices utilizing the 4-pin JTAG protocol. This
capability eliminates package handling normally
required for programming and facilitates rapid design
iterations and field changes.
Microchip provides ISP hardware and software to allow
programming of the ATF1504ASV(L) via the PC. ISP is
performed by using either a download cable, a compa-
rable board tester or a simple microprocessor interface.
Design Software Support
ATF1504ASV(L) designs are supported by Microchip’s
ProChip Designer and WinCUPL software tools as well
as Precision Synthesis from Mentor Graphic as
described in the “Programmable Logic Device Design
Software Overview”.
To facilitate ISP programming by the Automated Test
Equipment (ATE) vendors, Serial Vector Format (SVF)
files can be created by Microchip provided software
utilities.
Power-Up Reset
ATF1504ASV(L) devices can also be programmed
using standard third-party programmers. With
a
The ATF1504ASV/ATF1504ASVL is designed with a
power-up Reset, a feature critical for state machine ini-
tialization. At a point delayed slightly from VCC crossing
VRST, all registers will be initialized, and the state of
each output will depend on the polarity of its buffer.
However, due to the asynchronous nature of Reset and
uncertainty of how VCC actually rises in the system, the
following conditions are required:
third-party programmer, the JTAG ISP port can be dis-
abled, thereby allowing four additional I/O pins to be
used for logic.
Refer to Programming of PLDs application note for
more details.
ISP Programming Protection
• The VCC rise must be monotonic
The ATF1504ASV(L) has a special feature that locks
the device and prevents the inputs and I/O from driving
if the programming process is interrupted for any rea-
son. The inputs and I/O default to high Z state during
such a condition. In addition, the pin-keeper option pre-
serves the former state during device programming, if
this circuit was previously programmed on the device.
This prevents disturbing the operation of other circuits
in the system while the ATF1504ASV(L) is being pro-
grammed via ISP.
• After Reset occurs, all input and feedback setup
times must be met before driving the clock pin
high
• The clock must remain stable during Power-up
Reset
The ATF1504ASV/ATF1504ASVL has two options for
the hysteresis about the Reset level, VRST, Small and
Large. To ensure a robust operating environment in
applications where the device is operated near 3.0V, it
is recommended that during the fitting process users
configure the device with the Power-up Reset hystere-
sis set to Large. Users of the POF2JED conversion util-
ity should include the flag “-power_reset” on the
command line after “filename.POF”. To allow the regis-
ters to be properly reinitialized with the Large hystere-
sis option selected, the following condition is added:
All ATF1504ASV(L) devices are initially shipped in the
erased state, thereby making them ready to use for ISP.
• If VCC falls below 2.0V, it must shut off completely
before the device is turned on again
2019 Microchip Technology Inc.
DS20006185A-page 7
ATF1504ASV/ATF1504ASVL
1.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (†)
Temperature under bias............................................................................................................................-40°C to +85°C
Storage temperature ...............................................................................................................................-65°C to +150°C
Voltage on any pin with respect to ground(1).............................................................................................. -2.0V to +7.0V
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum
output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
TABLE 1-1:
DC AND AC OPERATING CONDITIONS
Industrial
Operating Temperature (Ambient)
VCC (VCCIO/VCCINT) Power Supply
-40°C to +85°C
3.0V to 3.6V
TABLE 1-2:
Symbol
DC CHARACTERISTICS
Parameter Minimum Typical
Maximum
Units
Condition
IIL
Input or I/O Low Leakage
Current
—
—
-40
—
—
—
—
-2
-10
10
40
—
—
5
µA VIN = GND
IIH
Input or I/O High Leakage
Current
2
µA VIN = VCC
IOZ
ICC1
Tri-State Output Off-State
Current
—
75
5
µA VO = VCC or GND
Power Supply Current,
Standby
mA VCC = Max
VIN = 0, VCC
Std power
“L” power
“PD” mode
Std power
µA VCC = Max
VIN = 0, VCC
ICC2
Power Supply Current,
Power-Down mode
0.1
55
mA VCC = Max
VIN = 0, VCC
ICC3(1) Reduced Power mode
—
mA VCC = Max
VIN = 0, VCC
Supply Current, Standby
VIL
Input Low Voltage
Input High Voltage
-0.3
1.7
—
—
—
—
0.8
VCCIO + 0.3
0.45
V
V
VIH
VOL
Output Low Voltage
(3.3V TTL)
V
V
V
V
VIN = VIH or VIL
VCCIO = Min, IOL = 8 mA
Output Low Voltage
(3.3V CMOS)
—
2.4
—
—
—
0.2
—
VIN = VIH or VIL
VCCIO = Min, IOL = 0.1 mA
VOH
Output High Voltage
(3.3V TTL)
VIN = VIH or VIL
VCCIO = Min, IOH = -1.5 mA
Output High Voltage
(3.3V CMOS)
VCCIO - 0.2
—
VIN = VIH or VIL
VCCIO = Min, IOH = -0.1 mA
Note 1: When macrocell reduced-power feature is enabled.
2019 Microchip Technology Inc.
DS20006185A-page 8
ATF1504ASV/ATF1504ASVL
TABLE 1-3:
PIN CAPACITANCE
Typical
Maximum
Units
Conditions
CIN
—
—
8
8
pF
pF
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
Note 1: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
2: The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
Timing Model
Internal Output
Enable Delay
t
IOE
Global Control
Delay
Input
t
GLOB
Delay
Register
Delay
Cascade Logic
Delay
t
IN
Output
Delay
Logic Array
Delay
t
t
SU
PEXP
Switch
Matrix
t
H
t
OD1
t
t
LAD
PRE
CLR
RD
t
t
OD2
t
UIM
t
OD3
t
Register Control
Delay
t
XZ
t
COMB
t
t
ZX1
t
t
FSU
LAC
IC
EN
ZX2
t
t
FH
Fast Input
t
ZX3
t
Delay
t
FIN
Foldback Term
Delay
I/O
t
SEXP
Delay
t
IO
TABLE 1-4:
Symbol
AC CHARACTERISTICS
Parameter
-15
-20
Units
Min.
Max.
15
12
—
—
—
—
9
Min.
Max.
tPD1
tPD2
tSU
Input or Feedback to Non-Registered Output
3
3
—
—
13.5
0
20
16
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I/O Input or Feedback to Non-Registered Feedback
Global Clock Setup Time
11
0
tH
Global Clock Hold Time
—
tFSU
tFH
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
3
3
—
1.0
—
5
2
—
tCOP
tCH
—
6
12
—
—
—
—
—
15
—
tCL
Global Clock Low Time
5
6
—
tASU
tAH
Array Clock Setup Time
5
7
—
Array Clock Hold Time
4
4
—
tACOP
tACH
Array Clock Output Delay
—
6
—
8
18.5
—
Array Clock High Time
2019 Microchip Technology Inc.
DS20006185A-page 9
ATF1504ASV/ATF1504ASVL
TABLE 1-4:
Symbol
AC CHARACTERISTICS (CONTINUED)
Parameter
-15
-20
Units
Min.
6
Max.
—
13
—
13
—
—
2
Min.
8
Max.
—
17
—
17
—
—
2.5
2.5
2
tACL
tCNT
fCNT
tACNT
fACNT
fMAX
tIN
Array Clock Low Time
ns
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
—
—
76.9
—
66
—
MHz
ns
76.9
100
—
58.8
83.3
—
MHz
MHz
ns
tIO
—
2
—
ns
tFIN
—
2
—
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Foldback Term Delay
—
8
—
10
1
ns
Cascade Logic Delay
—
1
—
ns
Logic Array Delay
—
6
—
8
ns
Logic Control Delay
—
3.5
3
—
4.5
3
ns
Internal Output Enable Delay
—
—
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
tOD1
tOD3
tZX1
tZX3
—
—
—
—
3
5
—
—
—
—
4
6
ns
ns
ns
ns
Output Buffer and Pad Delay
(Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
7
9
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF)
10
11
tXZ
Output Buffer Disable Delay (CL = 5 pF)
Register Setup Time
—
5
6
—
—
—
—
2
—
6
7
—
—
—
—
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
tH
Register Hold Time
4
5
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
2
2
2
2
tRD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tCOMB
tIC
Combinatorial Delay
2
Array Clock Delay
6
7
tEN
Register Enable Time
Global Control Delay
6
7
tGLOB
tPRE
tCLR
tUIM
2
3
Register Preset Time
Register Clear Time
4
5
4
5
Switch Matrix Delay
2
2.5
2019 Microchip Technology Inc.
DS20006185A-page 10
ATF1504ASV/ATF1504ASVL
TABLE 1-4:
Symbol
AC CHARACTERISTICS (CONTINUED)
Parameter
-15
-20
Units
Min.
Max.
Min.
Max.
tRPA
Reduced-Power Adder(1)
—
10
—
13
ns
Note 1: The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL or tACH, tEN and tSEXP parameters for
macrocells running in the Reduced-Power mode.
FIGURE 1-1:
INPUT TEST WAVEFORMS AND MEASUREMENT LEVELS
Note:
tR, tF = 1.5 ns typical
FIGURE 1-2:
OUTPUT AC TEST LOADS
3.0V
R1 = 703
OUTPUT
PIN
R2 = 8060
CL = 35 pF
Input and I/O hold latches remain active to ensure that
pins do not float to indeterminate levels, further reduc-
ing system power. The Power-Down mode feature is
enabled in the logic design file or as a design software
option. Designs using the Power-Down pin may not use
the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the
buried feedback and foldback product term array
inputs.
Power-Down Mode
The ATF1504ASV(L) includes an optional pin-con-
trolled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When
the PD pin is high, the device supply current is reduced
to less than 5 mA. During power-down, all output data
and internal logic states are latched internally and held.
Therefore, all registered and combinatorial output data
remain valid. Any outputs that were in a high Z state at
the onset will remain at high Z. During power-down, all
input signals except the Power-Down pin are blocked.
2019 Microchip Technology Inc.
DS20006185A-page 11
ATF1504ASV/ATF1504ASVL
(1)(2)(3)
TABLE 1-5:
Symbol
POWER-DOWN AC CHARACTERISTICS
Parameter
-15
-20
Units
Min.
Max.
Min.
Max.
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid I, I/O before PD High
Valid OE(2) before PD High
15
15
15
—
—
—
—
—
—
—
—
—
—
25
25
25
1
20
20
20
—
—
—
—
—
—
—
—
—
—
30
30
30
1
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
1
1
1
Note 1: For slow slew outputs, add tSSO.
2: Pin or product term.
3: Includes tRPA for reduced-power bit enabled.
JTAG-BST/ISP Overview
JTAG Boundary-Scan Cell (BSC)
The JTAG boundary-scan testing is controlled by the
Test Access Port (TAP) controller in the ATF1504-
ASV(L). The boundary-scan technique involves the
inclusion of a shift-register stage (contained in a bound-
ary-scan cell) adjacent to each component so that sig-
nals at component boundaries can be controlled and
observed using scan testing principles. Each input pin
and I/O pin has its own boundary-scan cell (BSC) in
order to support boundary-scan testing.
The ATF1504ASV(L) contains up to 64 I/O pins and
four input pins, depending on the device type and pack-
age type selected. Each input pin and I/O pin has its
own boundary-scan cell (BSC) in order to support
boundary-scan testing as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three cap-
ture registers or scan registers and up to two update
registers.
There are two types of BSCs, one for input or I/O pin,
and one for the macrocells. The BSCs in the device are
chained together through the capture registers. Input to
the capture register chain is fed in from the TDI pin
while the output is directed to the TDO pin. Capture
registers are used to capture active device data sig-
nals, to shift data in and out of the device and to load
data into the update registers. Control signals are gen-
erated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells
are shown in Figure 1-3 and Figure 1-4.
The ATF1504ASV(L) does not include a Test Reset
(TRST) input pin because the TAP controller is auto-
matically reset at power-up. The five JTAG modes sup-
ported include: SAMPLE/PRELOAD, EXTEST,
BYPASS, IDCODE and HIGHZ. The ATF1504ASV(L)’s
ISP can be fully described using JTAG’s BSDL as
described in IEEE Standard 1149.1. This allows
ATF1504ASV(L) programming to be described and
implemented using any one of the third-party develop-
ment tools supporting this standard.
The ATF1504ASV(L) has the option of using four
JTAG-standard I/O pins for boundary-scan testing
(BST) and in-system programming (ISP) purposes.
The ATF1504ASV(L) is programmable through the four
JTAG pins using the IEEE standard JTAG program-
ming protocol established by IEEE Standard 1149.1
using 3.3V TTL/CMOS-level programming signals from
the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST
or ISP) is not needed, then the four JTAG control pins
are available as I/O pins.
2019 Microchip Technology Inc.
DS20006185A-page 12
ATF1504ASV/ATF1504ASVL
FIGURE 1-3:
BSC CONFIGURATION FOR INPUT AND I/O PINS (EXCEPT JTAG TAP PINS)
Note:
The ATF1504ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option.
FIGURE 1-4:
BSC CONFIGURATION FOR MACROCELL
Pin BSC
TDO
0
DQ
Pin
1
Capture
DR
Clock
Shift
TDI
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
2019 Microchip Technology Inc.
DS20006185A-page 13
ATF1504ASV/ATF1504ASVL
TABLE 1-6:
DEDICATED PINOUTS
44-Lead TQFP
40
Dedicated Pin
44-Lead J-lead
100-Lead TQFP
INPUT/OE2(1)/GCLK2(2)
INPUT/GCLR(3)
INPUT/OE1(1)
2
90
39
1
89
38
44
88
INPUT/GCLK1(2)
I/O /GCLK3(2)
37
43
87
35
41
85
I/O / PD (1,2)(4)
I/O / TDI (JTAG)(5)
I/O / TMS (JTAG)(5)
I/O / TCK (JTAG)(5)
I/O / TDO (JTAG)(5)
GND(6)
5, 19
11, 25
12, 42
1
7
4
7
13
15
26
32
32
38
62
73
4, 16, 24, 36
9, 17, 29, 41
—
10, 22, 30, 42
3, 15, 23, 35
—
11, 26, 38, 43, 59, 74, 86, 95
3, 18, 34, 39, 51, 66, 82, 91
(7)
VCC
N/C
1, 2, 5, 7, 22, 24, 27, 28, 49,
50, 53, 55, 70, 72, 77, 78
# of Signal Pins
# User I/O Pins
36
32
36
32
68
64
Note 1: OE (1, 2)
2: GCLK (1, 2, 3)
3: GCLR
= Global OE pins
= Global Clock pins
= Global Clear pin
= Power-Down pins
4: PD (1, 2)
5: TDI, TMS, TCK. TDO = JTAG pins used for boundary-scan testing or in-system programming
6: GND
7: VCC
= Ground pins
= VCC (VCCINT/VCCIO) pins for the device
2019 Microchip Technology Inc.
DS20006185A-page 14
ATF1504ASV/ATF1504ASVL
TABLE 1-7:
MC
I/O PINOUTS
44-Lead 44-Lead 100-Lead
44-Lead 44-Lead 100-Lead
PLC
MC
PLC
PLCC
TQFP
TQFP
PLCC
TQFP
TQFP
1
2
A
A
12
—
11
9
6
14
13
12
10
9
33
34
C
24
—
25
26
27
—
—
28
29
—
—
—
—
31
—
32
33
—
34
36
37
—
—
38
39
—
—
—
—
40
—
41
18
—
19
20
21
—
—
22
23
—
—
—
—
25
—
26
27
—
28
30
31
—
—
32
33
—
—
—
—
34
—
35
40
41
42
44
45
46
47
48
52
54
56
57
58
60
61
62
63
64
65
67
68
69
71
73
75
76
79
80
81
83
84
85
—
5
C
3
A/PD1
A
35
C/PD2
4
3
36
C
5
A
8
2
37
C
6
A
—
—
7
—
—
1
8
38
C
7
A
6
39
C
8/TDI
9
A
4
40
C
A
—
—
6
—
—
44
—
—
43
—
42
15
—
14
13
12
—
—
11
10
—
—
—
—
8
100
99
98
97
96
94
93
92
37
36
35
33
32
31
30
29
25
23
21
20
19
17
16
15
41
C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32/TMS
A
42
C
A
43
C
A
—
—
5
44
C
A
45
C
A
46
C
A
—
4
47
C
A
48/TCK
49
C
B
21
—
20
19
18
—
—
17
16
—
—
—
—
14
—
13
D
B
50
D
B
51
D
B
52
D
B
53
D
B
54
D
B
55
D
B
56/TDO
57
D
B
D
B
58
D
B
59
D
B
60
D
B
61
D
B
62
D
D
B
—
7
63
B
64
D/GCLK3
2019 Microchip Technology Inc.
DS20006185A-page 15
ATF1504ASV/ATF1504ASVL
FIGURE 1-5:
SUPPLY CURRENT VS.
SUPPLY VOLTAGE –
ATF1504ASV (TA = 25°C,
F = 0)
FIGURE 1-8:
SUPPLY CURRENT VS.
SUPPLY VOLTAGE –
ATF1504ASVL (TA = 25°C,
F = 0)
25
20
15
10
5
100
75
50
25
0
Standard Power
Reduced Power Mode
0
2.5
2.75
3
3.25
3.5
3.75
4
2.5
2.75
3
3.25
3.5
3.75
4
Supply Voltage (V)
Supply Voltage (V)
FIGURE 1-9:
SUPPLY CURRENT VS.
FREQUENCY –
ATF1504ASVL (TA = 25°C)
FIGURE 1-6:
SUPPLY CURRENT VS.
SUPPLY VOLTAGE –
PIN-CONTROLLED
POWER-DOWN MODE
(TA = 25°C, F = 0)
100.0
80.0
60.0
40.0
20.0
Standard Power
800
700
600
500
400
Reduced Power
Standard & Reduced Power Mode
0.0
0.00
5.00
10.00
Frequency (MHz)
15.00
20.00
FIGURE 1-10:
OUTPUT SOURCE
2.5
2.75
3
3.25
3.5
3.75
4
Supply Voltage (V)
CURRENT VS. SUPPLY
VOLTAGE (VOH = 2.4V,
TA = 25°C)
FIGURE 1-7:
SUPPLY CURRENT VS.
FREQUENCY –
ATF1504ASV (TA = 25°C)
0
-2
-4
-6
-8
-10
-12
-14
150.0
125.0
100.0
75.0
50.0
25.0
0.0
Standard Power
-16
2.75
Reduced Power Mode
3
3.25
3.5
3.75
4
Supply Voltage (V)
0.00
20.00
40.00
60.00
80.00
100.00
Frequency (MHz)
2019 Microchip Technology Inc.
DS20006185A-page 16
ATF1504ASV/ATF1504ASVL
FIGURE 1-11:
OUTPUT SOURCE
CURRENT VS. OUTPUT
VOLTAGE (VCC = 3.3V,
TA = 25°C)
FIGURE 1-14:
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
0
-20
10
0
-10
-20
-30
-40
-50
-60
-70
-40
-60
-80
-100
-1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Input Voltage (V)
Output Voltage (V)
FIGURE 1-15:
INPUT CURRENT VS.
INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
FIGURE 1-12:
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE
(VOL = 0.5V, TA = 25°C)
20
15
10
5
40
35
30
25
0
-5
-10
-15
20
2.75
3
3.25
3.5
3.75
4
Supply Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
FIGURE 1-13:
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
100
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage (V)
2019 Microchip Technology Inc.
DS20006185A-page 17
ATF1504ASV/ATF1504ASVL
2.0
2.1
PACKAGING INFORMATION
Package Marking Information
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXX
YYWWNNN
ATF1504ASV
15JU44
1902610
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXX
YYWWNNN
ATF1504ASV
15AU44
1902610
100-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXX
YYWWNNN
ATF1504ASV
15AU100
1902610
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
YY
WW
NNN
*
This packages are RoHs compliant. The JEDEC® designator
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006185A-page 18
ATF1504ASV/ATF1504ASVL
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ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢺꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢻꢣꢥꢶꢼ
2019 Microchip Technology Inc.
DS20006185A-page 19
ATF1504ASV/ATF1504ASVL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006185A-page 20
ATF1504ASV/ATF1504ASVL
44-Lead Plastic Thin Quad Flatpack (3EB) - 10x10x1.0 mm Body [TQFP]
Atmel Legacy Global Package Code AIX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1
2
D
2
D
E1
2
A
B
E
E1
A
A
NOTE 1
E
2
N
N/4 TIPS
0.25 C A-B D
1
2
3
4X
e
0.10 C A-B D
TOP VIEW
C
A2
A1
A
SEATING
PLANE
44X
0.08 C
44X b
0.07 C A-B D
SIDE VIEW
Microchip Technology Drawing C04-21019-3EB Rev A Sheet 1 of 2
2019 Microchip Technology Inc.
DS20006185A-page 21
ATF1504ASV/ATF1504ASVL
44-Lead Plastic Thin Quad Flatpack (3EB) - 10x10x1.0 mm Body [TQFP]
Atmel Legacy Global Package Code AIX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2
ࣄ
1
ࣄ
H
c
2
ࣄ
ࣄ
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Terminals
Pitch
N
e
44
0.80 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
A
A1
A2
D
-
-
-
1.20
0.15
1.05
0.05
0.95
1.00
12.00 BSC
Molded Package Length
Overall Width
D1
E
10.00 BSC
12.00 BSC
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
E1
b
10.00 BSC
0.30
0.09
0.45
-
-
0.45
0.20
0.75
-
c
L
0.60
1.00 REF
L1
R1
R2
ࣄ
ࣄ
1 ࣄ
2 0.08
0.08
0°
0°
11°
-
-
-
0.20
7°
-
3.5°
-
12°
Lead Angle
Terminal-to-Exposed-Pad
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21019-3EB Rev A Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006185A-page 22
ATF1504ASV/ATF1504ASVL
44-Lead Plastic Thin Quad Flatpack (3EB) - 10x10x1.0 mm Body [TQFP]
Atmel Legacy Global Package Code AIX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G1
C2
Y2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
0.80 BSC
11.40
11.40
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X20)
C1
C2
X1
0.55
1.50
Contact Pad Length (X20)
Contact Pad to Center Pad (X20)
Y1
G1
0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23019-3EB Rev A
2019 Microchip Technology Inc.
DS20006185A-page 23
ATF1504ASV/ATF1504ASVL
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α
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1 23
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β
L1
L
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2019 Microchip Technology Inc.
DS20006185A-page 24
ATF1504ASV/ATF1504ASVL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006185A-page 25
ATF1504ASV/ATF1504ASVL
APPENDIX A: REVISION HISTORY
Revision A (03/2019)
Updated to the Microchip template. Microchip
DS20006185 replaces Atmel document 1409.
Removed commercial temperature, 68-/84-lead
PLCCs and 100-lead PQFP.
2019 Microchip Technology Inc.
DS20006185A-page 26
ATF1504ASV/ATF1504ASVL
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.
2019 Microchip Technology Inc.
DS20006185A-page 27
ATF1504ASV/ATF1504ASVL
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
-XX
XXX
PART NO.
Device
X
X
-[X]
Examples:
Speed
Grade
Lead
Count
Temperature
Range
a)
ATF1504ASV-15JU44-T = Industrial temp.,
Package
Type
Tape and Reel
Option
Tape and Reel,
PLCC package.
b)
c)
d)
e)
ATF1504ASV-15JU44
ATF1504ASV-15AU44
ATF1504ASV-15AU100
= Industrial temp.,
PLCC package.
Device:
ATF1504ASV
ATF1504ASVL = 3.3V Low-Power 64 MC CPLD
=
3.3V Standard-Power 64 MC CPLD
= Industrial temp.,
TQFP package.
=
Industrial temp.,
TQFP package.
Speed Grade:
Package Type:
15
20
=
=
15 ns (tPD)
20 ns (tPD)
ATF1504ASVL-20JU44-T = Industrial temp.,
Tape and Reel,
TQFP package.
f)
ATF1504ASVL-20JU44
ATF1504ASVL-20AU44
ATF1504ASV-15AU100
=
=
=
Industrial temp.,
TQFP package.
Industrial temp.,
TQFP package.
Industrial temp.,
TQFP package.
A
J
=
=
TQFP (Thin Profile Plastic Quad Flat Package)
PLCC (Plastic J-leaded Chip Carrier)
g)
h)
Temperature
Range:
U
=
-40C to +85C (Industrial)
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Lead Count:
44
100
=
=
44 Leads
100 Leads
Tape and Reel
Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel
(1)
ORDERING INFORMATION
ATF1504ASV(L) Green Package Options (Pb/Halide-Free/RoHS Compliant)
tPD1 (ns) tCOP (ns) fMAX (MHz)
Ordering Code
Package
Operation Range
ATF1504ASV-15AU44
ATF1504ASV-15JU44
ATF1504ASV-15AU100
ATF1504ASVL-20AU44
ATF1504ASVL-20JU44
ATF1504ASVL-20AU100
44A
44J
15
20
9
100
Industrial (-40°C to +85°C)
100A
44A
44J
12
83.3
Industrial (-40°C to +85°C)
100A
2019 Microchip Technology Inc.
DS20006185A-page 28
ATF1504ASV/ATF1504ASVL
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4345-2
== ISO/TSꢀ16949ꢀ==ꢀ
2019 Microchip Technology Inc.
DS20006185A-page 29
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.micro-
chip.com/support
Web Address:
www.microchip.com
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Indianapolis
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Norway - Trondheim
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China - Zhuhai
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Poland - Warsaw
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Romania - Bucharest
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Raleigh, NC
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Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
2019 Microchip Technology Inc.
DS20006185A-page 30
08/15/18
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