ATF16V8B-15SU-T [MICROCHIP]
Flash PLD, 15ns, CMOS, PDSO20;
| 型号： | ATF16V8B-15SU-T |
| 厂家： | 
MICROCHIP |
| 描述： | Flash PLD, 15ns, CMOS, PDSO20 时钟 输入元件 光电二极管 可编程逻辑 |
| 文件： | 总26页 (文件大小：2085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATF16V8B, ATF16V8BQ*, and ATF16V8BQL
High-performance EE PLD
DATASHEET
Features
Industry-standard Architecture
̶
̶
Emulates Many 20-pin PALs®
Low-cost Easy-to-use Software Tools
High-speed Electrically-erasable Programmable Logic Devices
10ns Maximum Pin-to-pin Delay
̶
Automatic 5mA Standby for ATF16V8BQL
CMOS and TTL Compatible Inputs and Outputs
̶
Input and I/O Pull-up Resistors
Advanced Flash Technology
̶
̶
Reprogrammable
100% Tested
High-reliability CMOS Process
̶
̶
̶
̶
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200mA Latchup Immunity
Industrial Temperature Range
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-compliant
Green Package Options (Pb/Halide-free/RoHS Compliant)
Description
The Atmel® ATF16V8B(QL) is a high-performance CMOS Electrically-Erasable
Programmable Logic Device (EE PLD) that utilizes the Atmel proven
electrically-erasable Flash memory technology. All speed ranges are specified
over the full 5.0V 10% range for industrial temperature range.
The ATF16V8BQL provides edge-sensing low-power PLD solution with low
standby power consumption (5mA typical). The ATF16V8BQL powers down
automatically to the low-power mode through the Input Transition Detection (ITD)
circuitry when the device is idle.
The ATF16V8B(QL) incorporate a super set of the generic architectures, which
allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs.
Eight outputs are each allocated eight product terms. Three different modes of
operation, configured automatically with software, allow highly complex logic
functions to be realized.
*The ATF16V8BQ is
Replaced by ATF16V8B
and ATF16V8BQL
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Configurations
Pin Name
CLK
GND
I
Function
Clock
Ground
Logic Inputs
Bi-directional Buffers
Output Enable
+5V Power Supply
I/O
OE
VCC
Figure 1-1.
Pinouts
20-lead SOIC
20-lead TSSOP
(Top View)
(Top View)
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/CLK
I1
I/CLK
I1
1
20
19
18
17
16
15
14
13
12
11
VCC
I/O
1
20
19
18
17
16
15
14
13
12
11
2
2
3
I2
I3
I4
I5
I6
I7
I8
GND
I2
3
I/O
4
I3
4
I/O
5
I4
5
I/O
6
I5
6
I/O
7
I6
7
I/O
8
I7
8
I/O
9
I8
9
I/O
10
I9/OE
GND
10
I9/OE
20-lead PDIP
(Top View)
20-lead PLCC
(Top View)
1
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
VCC
I/O
2
3
I2
I/O
I3
I4
I5
I6
I7
4
5
6
7
8
18
17
16
15
14
I/O
4
I3
I/O
I/O
I/O
I/O
I/O
5
I4
I/O
6
I5
I/O
7
I6
I/O
8
I7
I/O
9
I8
I/O
10
GND
I9/OE
Note: Drawings are not to scale.
2
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
2.
Block Diagram
Figure 2-1.
Block Diagram
Programmable
Interconnect
and
Combinatorial
Logic Array
Logic
Option
10 Input Pins
8 I/O Pins
Up to
8 Flip-Flops
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
3
3.
Electrical Characteristics
3.1
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
*Notice: Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional
operation of the device at these or any
other conditions beyond those indicated
in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliability.
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on Input Pins with Respect to
Ground During Programming . . . . . . . . . . . . . -2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output
pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20ns.
3.2
Pin Capacitance
Table 3-1.
Pin Capacitance (f = 1MHz, T = 25°C(1)
)
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
3.3
DC and AC Operating Conditions
Table 3-2.
DC and AC Operating Conditions
Industrial
-40oC to +85oC
5.0V 10%
Operating Temperature (Ambient)
VCC Power Supply
4
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
3.4
DC Characteristics
Table 3-3.
Symbol
DC Characteristics
Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
0 VIN VIL(Max)
-35
-100
μA
Input or I/O High
Leakage Current
IIH
3.5 VIN VCC
10
μA
B-10
55
50
5
95
80
VCC = Max
Power Supply
Current, Standby
ICC
B-15
mA
VIN = Max, Outputs Open
BQL-15
B-10
15
60
55
20
100
95
VCC = Max, Outputs Open
f = 15MHz
Clocked Power
Supply Current
ICC2
B-15
mA
mA
BQL-15
40
Output Short
Circuit Current
(1)
IOS
VOUT = 0.5 V
-130
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
VCC + 0.75
VIN = VIH or VIL
VCC = Min
VOL
Output High Voltage
Output High Voltage
IOL = 24mA
0.5
V
V
VIN = VIH or VIL
VCC = Min
VOH
IOH = -4.0 mA
2.4
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s.
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
5
3.5
AC Characteristics
Table 3-4.
AC Characteristics(1)
-10
-15
Symbol
Parameter
Min
Max
Min
Max
Units
Input or Feedback to
Non-Registered Output
tPD
8 outputs switching
3
10
3
15
ns
tCF
tCO
tS
Clock to Feedback
Clock to Output
Input or Feedback Setup Time
Hold Time
6
7
8
ns
ns
ns
ns
ns
ns
2
7.5
0
2
12
0
10
tH
tP
Clock Period
12
6
16
8
tW
Clock Width
External Feedback 1/(tS + tCO
)
68
74
83
10
10
10
10
45
50
62
15
15
15
15
fMAX
Internal Feedback 1/(tS + tCF
)
MHz
No Feedback 1/(tP)
tEA
Input to Output Enable — Product Term
Input to Output Disable — Product Term
OE pin to Output Enable
3
2
3
2
ns
ns
ns
ns
tER
tPZX
tPXZ
2
2
OE pin to Output Disable
1.5
1.5
Note:
1. See ordering information for valid part numbers and speed grades.
Figure 3-1.
AC Waveforms(3.6)
Inputs, I/O
Reg. Feedback
tH
tS
tW
CLK
tW
tP
tER, tPXZ
tCO
tEA, tPZX
HIGH Z
Registered
Outputs
Output
Valid
Output
Valid
tPD
tEA, tPZX
tER, tPXZ
HIGH Z
Combinatorial
Outputs
Output
Valid
Output
Valid
Output
Valid
Note 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.
6
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
3.6
Input Test Waveforms
3.6.1 Input Test Waveforms and Measurement Levels
Figure 3-2.
Input Test Waveforms and Measurement Levels
3.0V
AC
AC
Driving
Levels
1.5V
Measurement
Level
0.0V
tR, tF < 5ns (10% to 90%)
3.6.2 Output Test Loads (Commercial)
Figure 3-3.
Output Test Loads
CL includes Test fixture and Probe capacitance
3.7
Power-up Reset
The registers in the ATF16V8B(QL) are designed to reset during power-up. At a point delayed slightly from VCC
crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be
high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and
3. The clock must remain stable during tPR
.
Figure 3-4.
Power-up Reset Waveforms
VRST
Power
tPR
Registered
Outputs
tS
tW
Clock
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
7
Table 3-5.
Power-up Reset Parameters
Parameter
tPR
Description
Typ
600
3.8
Max
1,000
4.5
Units
ns
Power-up Reset Time
Power-up Reset Voltage
VRST
V
3.8
Preload of Registered Outputs
The ATF16V8B(QL) device registers are provided with circuitry to allow loading of each register with either a
high or a low. This feature will simplify testing since any state can be forced into the registers to control test
sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once
downloaded, the JEDEC file preload sequence will be done automatically by most of the approved
programmers after the programming.
4.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B(QL) fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6.
7.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers.
Input and I/O Pull-ups
All ATF16V8B(QL) family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or
I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known
states. These are relatively weak active pull-ups that can easily be over driven by TTL-compatible drivers (see
input and I/O diagrams below).
Figure 7-1.
Input Diagram
VCC
VCC
R > 50KΩ
Input
ESD
Protection
Circuit
8
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Figure 7-2.
I/O Diagram
VCC
VCC
OE
R > 50KΩ
I/O
Data
Feedback
8.
Functional Logic Diagram Description
The logic option and functional diagrams describe the ATF16V8B(QL) architecture. Eight configurable
macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF16V8B(QL) can be configured in one of three different modes. Each mode makes the ATF16V8B(QL)
look like a different device. Most PLD compilers can choose the right mode automatically. The user can also
force the selection by supplying the compiler with a mode selection. The determining factors would be the usage
of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF16V8B(QL) universal architecture can be programmed to emulate many 20-pin PAL devices. These
architectural subsets can be found in each of the configuration modes described in the following pages. The
user can download the listed subset device JEDEC programming file to the PLD programmer, and the
ATF16V8B(QL) can be configured to act like the chosen device. Check with your programmer manufacturer for
this capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the content of the ATF16V8B(QL). Eight bytes (64 fuses) of User Signature
are accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
9.
Software Support
Atmel WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all members of the
ATF16V8B(QL) family of SPLDs. The below table lists the Atmel WinCUPL device mnemonics for the different
macrocell configuration modes.
Table 9-1.
Compiler Mode Selection
Registered
Complex
Simple
Auto Select
CUPL, Atmel WinCUPL
G16V8MS
G16V8MA
G16V8AS
G16V8
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
9
10. Macrocell Configuration
Software compilers support the three different OMC modes as different device types. Most compilers have the
ability to automatically select the device type, generally based on the register usage and Output Enable (OE)
usage. Register usage on the device forces the software to choose the registered mode. All combinatorial
outputs with OE controlled by the product term will force the software to choose the complex mode. The
software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The
different device types can be used to override the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user must pay special attention to the following
restrictions in each mode:
Registered Mode
Pin 1 and pin 11 are permanently configured as clock and output enable respectively. These pins cannot
be configured as dedicated inputs in the registered mode.
Complex Mode
Pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively.
Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode.
Simple Mode
All feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins
(pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated
combinatorial output.
10.1 ATF16V8B(QL) Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required.
Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a
registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight
product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by
a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an
input, the output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can be emulated
using this mode:
16R8
16R6
16R4
16RP8
16RP6
16RP4
10
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Figure 10-1. Registered Configuration for Registered Mode(1)(2)
CLK
D
Q
Q
XOR
OE
Notes: 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered
outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
Figure 10-2. Combinatorial Configuration for Registered Mode(1)(2)
XOR
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
11
Figure 10-3. Registered Mode Logic Diagram
CLK
1
Input Lines
0
4
8
12
16
20
24
28
19
18
17
16
15
14
13
Output
Logic
2
3
4
5
6
7
8
9
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
12
11
Output
Logic
12
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
10.2 ATF16V8B(QL) Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are
possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the
AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term
and one product term enabling the output.
Combinatorial applications with an OE requirement will make the compiler select this mode. The following
devices can be emulated using this mode:
16L8
16H8
16P8
Figure 10-4. Complex Mode Option
0
1
7
XOR
Pins 12 and 19 do not have this feedback path.
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
13
Figure 10-5. Complex Mode Logic Diagram
1
Input Lines
0
4
8
12
16
20
24
28
19
18
17
16
15
14
13
Output
Logic
2
3
4
5
6
7
8
9
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
12
11
Output
Logic
14
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
10.3 ATF16V8B(QL) Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term.
Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can
be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple
PALs can be emulated using this mode:
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
Figure 10-6. Simple Mode Option
VCC
0
1
S1*
0
7
XOR
Pins 15 and 16 do not have this feedback path.
* Pins 15 and 16 are always enabled.
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
15
Figure 10-7. Simple Mode Logic Diagram
1
Input Lines
0
4
8
12
16
20
24
28
Output
Logic
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
12
11
16
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
11. Test Characterization Data
Supply Current vs Input Frequency
Supply Current vs Input Frequency
ATF16V8B/BQ (VCC = 5V, TA = 25°C)
ATF16V8BL/BQL (VCC = 5V, TA = 25°C)
75
75
50
25
0
ATF16V8B
ATF16V8B
50
ATF16V8BQL
ATF16V8BQ
25
0
0
25
50
75
100
0
20
40
60
80
100
Frequency (MHz)
Frequency (MHz)
Supply Current vs Supply Voltage
Supply Current vs Supply Voltage
ATF16V8B/BQ (TA = 25°C)
ATF16V8BL/BQL (TA = 25°C)
65
55
45
35
25
6.0
5.5
5.0
4.5
4.0
ATF16V8B
ATF16V8BQ
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Current vs Ambient Temperature
Supply Current vs Ambient Temperature
ATF16V8B/BQ (VCC = 5.0V)
ATF16V8BL/BQL (VCC = 5.0V)
70
5.6
60
5.2
4.8
4.4
4.0
50
ATF16V8B
40
ATF16V8BQ
30
-55
-10
35
80
125
-55
-10
35
80
125
Ambient Temperature (C)
Ambient Temperature (C)
Output Source Current vs Supply Current
Output Sink Current vs Supply Current
TA = 25°C
TA = 25°C
-10
34.5
-12
-14
-16
-18
-20
-22
-24
34.0
33.5
33.0
32.5
32.0
4.50
4.75
5.00
5.25
5.50
4.5
4.7
4.9
5.1
5.3
5.5
Supply Voltage (V)
Supply Voltage (V)
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
17
Output Source Current vs Outpute Voltage
Output Sink Current vs Output Voltage
(VCC = 5.0V, TA = 25°C)
(VCC = 5.0V, TA = 25°C)
0.0
70
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
60
50
40
30
20
10
0
3.5
3.8
4.1
4.4
4.7
5.0
0.0
0.2
0.4
0.6
0.8
1.0
Output Voltage (V)
Output Voltage (V)
Output Source Current vs Output Voltage
Output Sink Current vs Output Voltage
(VCC = 5.0V, TA = 25°C)
(VCC = 5.0V, TA = 25°C)
0
140
120
100
80
60
40
20
0
-10
-20
-30
-40
0.0 0.5 1.0 1.5
2.0 2.5
3.0 3.5 4.0 4.5 5.0
0
1
2
3
4
5
Output Voltage (V)
Output Voltage (V)
Normalized TPD vs Supply Voltage
Normalized TPD vs Ambient Temperature
(TA = 25°C)
(VCC = 5.0V)
1.30
1.15
1.00
0.85
0.70
1.30
1.15
1.00
0.85
0.70
ATF16VB/BQ
ATF16VB/BQL
4.50
4.75
5.00
5.25
5.50
-55
-25
5
35
65
95
125
Supply Voltage (V)
Ambient Temperature (C)
Normalized TCO vs Supply Voltage
Normalized TCO vs Ambient Temperature
(TA = 25°C)
(VCC = 5.0V)
1.30
1.15
1.00
0.85
0.70
1.30
1.15
1.00
0.85
0.70
ATF16V8B/BQ
ATF16V8B/BQL
4.50
4.75
5.00
5.25
5.50
-55
-10
35
80
125
Supply Voltage (V)
Ambient Temperature (C)
18
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Normalized TS vs Supply Voltage
Normalized TS vs Ambient Temperature
(TA = 25°C)
(VCC = 5.0V)
1.30
1.15
1.00
0.85
0.70
1.30
1.15
1.00
0.85
0.70
-55
-10
35
80
125
300
8
-55
-10
35
80
125
300
8
Supply Voltage (V)
Ambient Temperature (C)
Delta TPD vs Output Loading
Delta TCO vs Output Loading
(VCC = 5.0V, TA = 25°C)
(VCC = 5V, TA = 25°C)
6
4
6
4
2
2
0
0
-2
-2
0
50
100
150
200
250
0
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
Delta TPD vs # Output Switching
Delta TCO vs # Output Switching
(VCC = 5.0V, TA = 25°C)
(VCC = 5.0V, TA = 25°C)
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
1
2
3
4
5
6
7
1
2
3
4
5
6
7
# of Output Switching
# of Output Switching
Input Current vs Input Voltage
Input Clamp Current vs Input Voltage
(VCC = 5.0V, TA = 25°C)
(VCC = 5.0V, TA = 25°C)
40
20
0
20
0
-20
-40
-60
-80
-20
-40
1
2
3
4
5
6
7
8
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
Input Voltage (V)
Input Voltage (V)
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
19
12. Ordering Information
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
ATF16V8B-10JU
ATF16V8B-15SU
ATF16V8B-15XU
ATF16V8B-15PU
ATF16V8B-15JU
Package
20J
Operation Range
10
15
7.5
12
7
20S2
20X
Industrial
(Pb/Halide-free/RoHS Compliant)
(-40C to +85C)
10
20P3
20J
ATF16V8BQL-15SU
ATF16V8BQL-15XU
ATF16V8BQL-15PU
ATF16V8BQL-15JU
20S2
20X
Industrial
(Pb/Halide-free/RoHS Compliant)
(-40C to +85C)
15
12
10
20P3
20J
Package Type
20S2
20-lead, 0.300" wide, Plastic Gull-wing Small Outline (SOIC)
20-lead, 4.4mm wide, Plastic Thin Shrink Small Outline (TSSOP)
20-lead, 0.300" wide, Plastic Dual Inline Package (PDIP)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20X
20P3
20J
20
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
13. Packaging Information
13.1 20S2 — 20-lead SOIC
C
1
10
E
E1
E1
11
20
TOP VIEW
L
A2
e
b
END VIEW
A1
A
D
SIDE VIEW
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing
MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold flash, protrusions or gate burrs. Mold
flash, protrustions or gate burrs shall not exceed 0.15 mm per end.
Diminsion E1 does not include interlead flash or protursion. Interlead flash
or protrusion shall not exceed 0.25 mm per side.
3. The package top may be smaller than the package bottom. Dimensions D
and E1 are determinded at the outermost extremes of the plastic body
exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. The dimensions apply to the flat section of the lead between 0.10 to
0.25 mm from the lead tip.
5. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar
protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum
material condition. The dambar may not be located on the lower radius of
the foot.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E1
E
12.80 BSC
2,3
2,3
7.50 BSC
10.30 BSC
A
-
-
2.65
0.30
-
A1
A2
e
0.10
2.05
-
6
-
1.27 BSC
b
0.31
0.40
0.20
-
-
-
0.51
1.27
0.33
4,5
4
L
6. ‘A1’ is defined as the vertical distance from the seating plane to the lowest
point on the package body excluding the lid or thermal enhancement on the
cavity down package configuration.
C
7/1/14
TITLE
DRAWING NO.
REV.
GPC
20S2, 20-lead, 0.300” Wide Body, Plastic
Gull Wing Small Outline Package (SOIC)
SRJ
20S2
E
Package Drawing Contact:
packagedrawings@atmel.com
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
21
13.2 20X — 20-lead TSSOP
b
L
L1
E
E1
End View
e
COMMON DIMENSIONS
(Unit of Measure = mm)
Top View
D
MIN
6.40
MAX
6.60
NOM
6.50
NOTE
2, 5
SYMBOL
D
E
6.40 BSC
4.40
A
A2
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
–
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional
information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
09/26/11
REV.
D
TITLE
20X, 20-lead 4.4 x 6.5 mm Body, 0.65 mm
DRAWING NO.
GPC
TLN
20X
Package Drawing Contact:
packagedrawings@atmel.com
Lead Pitch, Thin Shrink Small Outline Package
(TSSOP)
22
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
13.3 20P3 — 20-lead PDIP
20
11
10
E1
1
D
E
e
See
Lead Detail
A2 A
BASE PLANE
-C-
SEATING PLANE
A1
C
L
eA
L
c
b2
.015
eB
b
j
0.10
m
C
GAGE
PLANE
Z Z
COMMON DIMENSIONS
(UNIT OF MEASURE=MM)
Symbol
A
A1
A2
b
b2
c
D
Min.
Nom.
-
Max.
5.334
-
Note
-
0.381
2.921
0.356
1.143
0.203
24.892
7.620
6.096
2.921
-
3.302
0.457
1.524
0.254
26.162
7.874
6.350
3.302
2.54 BSC
7.62 BSC
-
4.953
0.588
1.778
0.356
26.924
8.255
7.112
3.810
eC
Lead Detail
Note 2
Note 2
E
E1
L
Notes:
1. This package conforms to JEDEC reference MS-001,
Variation AD.
2. Dimensions D and E1 do not include mold Flash or
Protrusion. Mold Flash or Protrusion shall not exceed
0.25 mm (0.010").
e
eA
eB
eC
-
10.922
1.524
0.000
-
1/6/12
DRAWING NO. REV.
TITLE
GPC
Package Drawing Contact:
packagedrawings@atmel.com
20P3, 20-lead, 0.300”/7.62 mm Wide Plastic Dual
20P3
F
PQD
Inline Package (PDIP)
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
23
13.4 20J — 20-lead PLCC
PIN NO. 1
1.14(0.045) X 45°
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102mm) maximum
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
20J
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
B
24
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
14. Revision History
Doc. Rev.
Date
Comments
Removed ATF16V8BQ device and commercial options due to becoming obsolete.
Updated package drawings to most current versions and the 20S to 20S2 package
drawing.
0364K
07/2014
Updated template, Atmel logos, disclaimer page.
Green Package options added in 2005.
0364J
07/2005
1999
ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI and ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI
were obsoleted in August 1999 and removed from the datasheet.
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
25
X
X X X X
X
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014.
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