ATMEGA6490P-AU [MICROCHIP]
IC MCU 8BIT 64KB FLASH 100TQFP;
| 型号： | ATMEGA6490P-AU |
| 厂家： | 
MICROCHIP |
| 描述： | IC MCU 8BIT 64KB FLASH 100TQFP 时钟 微控制器 外围集成电路 |
| 文件： | 总39页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash
DATASHEET SUMMARY
Features
• High performance, low power Atmel® AVR® 8-Bit Microcontroller
• Advanced RISC architecture
– 130 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at16MHz (Atmel ATmega169A/169PA/649A/649P)
– Up to 20 MIPS throughput at 20MHz (Atmel ATmega329A/329PA/3290A/3290PA/6490A/6490P)
– On-chip 2-cycle multiplier
• High endurance non-volatile memory segments
– In-system self-programmable flash program memory
• 16Kbytes (Atmel ATmega169A/ATmega169PA)
• 32Kbytes (Atmel ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 64Kbytes (Atmel ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
– EEPROM
• 512bytes (ATmega169A/ATmega169PA)
• 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
– Internal SRAM
• 1Kbytes (ATmega169A/ATmega169PA)
• 2Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 4Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
– Write/erase cyles: 10,000 flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True read-while-write operation
– Programming lock for software security
• Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral features
– 4 × 25 segment LCD driver
(ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P)
– 4 × 40 segment LCD driver (ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P)
– Two 8-bit Timer/Counters with Separate Prescaler and Compare mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare mode, and Capture mode
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– Real Time Counter with separate oscillator
– Four PWM channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip oscillator
– On-chip analog comparator
– Interrupt and Wake-up on pin change
• Special microcontroller features
– Power-on reset and programmable Brown-out detection
– Internal calibrated oscillator
– External and internal interrupt sources
– Five sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O and packages
– 54/69 programmable I/O lines
– 64/100-lead TQFP, 64-pad QFN/MLF, and 64-pad DRQFN
• Speed Grade:
– ATmega169A/169PA/649A/649P:
• 0 - 16MHz @ 1.8 - 5.5V
– ATmega3290A/3290PA/6490A/6490P:
• 0 - 20MHz @ 1.8 - 5.5V
• Temperature range:
– -40°C to 85°C industrial
• Ultra-low power consumption (picoPower® devices)
– Active mode:
• 1MHz, 1.8V: 215µA
• 32kHz, 1.8V: 8µA (including oscillator)
• 32kHz, 1.8V: 25µA (including oscillator and LCD)
– Power-down mode:
• 0.1µA at 1.8V
– Power-save mode:
• 0.6µA at 1.8V (Including 32kHz RTC)
• 750nA at 1.8V
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1.
Pin configurations
1.1
Pinout - 64A (TQFP) and 64M1 (QFN/MLF)
Figure 1-1.
Pinout Atmel ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P.
LCDCAP
1
2
3
PA3 (COM3)
PA4 (SEG0)
PA5 (SEG1)
PA6 (SEG2)
48
47
46
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
INDEX CORNER
(XCK/AIN0/PCINT2) PE2
4
45
(AIN1/PCINT3) PE3
5
6
PA7 (SEG3)
PG2 (SEG4)
PC7 (SEG5)
PC6 (SEG6)
PC5 (SEG7)
PC4 (SEG8)
PC3 (SEG9)
PC2 (SEG10)
PC1 (SEG11)
PC0 (SEG12)
44
43
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
7
8
9
42
41
40
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0 10
(SCK/PCINT9) PB1 11
(MOSI/PCINT10) PB2 12
(MISO/PCINT11) PB3 13
39
38
37
36
(OC0A/PCINT12) PB4 14
(OC1A/PCINT13) PB5 15
(OC1B/PCINT14) PB6 16
35
34
33
PG1 (SEG13)
PG0 (SEG14)
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1.2
Pinout - 100A (TQFP)
Figure 1-2.
Pinout Atmel ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P.
TQFP
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LCDCAP
PA3 (COM3)
PA4 (SEG0)
PA5 (SEG1)
PA6 (SEG2)
PA7 (SEG3)
PG2 (SEG4)
PC7 (SEG5)
PC6 (SEG6)
DNC
2
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
INDEX CORNER
3
4
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PH3 (PCINT19/SEG7)
PH2 (PCINT18/SEG8)
PH1 (PCINT17/SEG9)
PH0 (PCINT16/SEG10)
DNC
GND
DNC
(PCINT24/SEG35) PJ0
(PCINT25/SEG34) PJ1
DNC
DNC
DNC
DNC
DNC
DNC
DNC
PC5 (SEG11)
PC4 (SEG12)
PC3 (SEG13)
PC2 (SEG14)
PC1 (SEG15)
PC0 (SEG16)
PG1 (SEG17)
PG0 (SEG18)
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered
or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the
board.
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1.3
Pinout - 64MC (DRQFN)
Figure 1-3.
Pinout Atmel ATmega169A/ATmega169PA.
Top view
Bottom view
A1
A2
A3
A4
A1
A2
A3
A4
A5
A6
A7
A8
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
A25
B22
A24
B21
A23
B20
A22
B19
A21
B18
A20
B17
A19
B16
A18
B1
B2
B3
B1
B2
B3
B4
B5
B6
B7
B4
A5
B5
B6
B7
A6
A7
A8
Table 1-1.
DRQFN-64 Pinout ATmega169A/ATmega169PA.
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
PE0
A9
PB7
PB6
A18
B16
A19
B17
A20
B18
A21
B19
A22
B20
A23
B21
A24
B22
A25
PG1 (SEG13)
A26
B23
A27
B24
A28
B25
A29
B26
A30
B27
A31
B28
A32
B29
A33
B30
A34
PA2 (COM2)
PA3 (COM3)
PA1 (COM1)
PA0 (COM0)
VCC
VLCDCAP
B8
PG0 (SEG14)
PC0 (SEG12)
PC1 (SEG11)
PC2 (SEG10)
PC3 (SEG9)
PC4 (SEG8)
PC5 (SEG7)
PC6 (SEG6)
PC7 (SEG5)
PG2 (SEG4)
PA7 (SEG3)
PA6 (SEG2)
PA4 (SEG0)
PA5 (SEG1)
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PB0
PB1
PB2
PB3
PB5
PB4
A10
B9
PG3
PG4
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
A16
B15
A17
RESET
VCC
GND
GND
PF7
XTAL2 (TOSC2)
XTAL1 (TOSC1)
PD0 (SEG22)
PD1 (SEG21)
PD2 (SEG20)
PD3 (SEG19)
PD4 (SEG18)
PD5 (SEG17)
PD7 (SEG15)
PD6 (SEG16)
PF6
PF5
PF4
PF3
PF2
PF1
PF0
AREF
AVCC
GND
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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2.
Overview
The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit
microcontroller based on the Atmel®AVR® enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching
1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block diagram
Figure 2-1.
Block diagram.
PF0 - PF7
PA0 - PA7
PC0 - PC7
GND
VCC
PORTA DRIVERS
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
CALIB. OSC
AGND
AREF
ADC
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
JTAG TAP
TIMING AND
CONTROL
LCD
CONTROLLER/
DRIVER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
AVR CPU
UNIVERSAL
SERIAL INTERFACE
SPI
USART
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG. DATA DIR.
PORTG
REG. PORTG
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PORTE DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides the following
features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K
bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a
JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD
controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the
asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU
and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the XTAL/resonator Oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low-power consumption.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous
detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your
own touch applications.
The device is manufactured using the Atmel high density non-volatile memory technology. The On-chip In-System
re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial
interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR
core. The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation.
By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P AVR is supported with a full
suite of program and system development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2.2
Comparison between Atmel
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
Table 2-1.
Differences between: ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P.
Device
Flash
EEPROM
512Bytes
512Bytes
1Kbyte
1Kbyte
1Kbyte
1Kbyte
2Kbyte
2Kbyte
2Kbyte
2Kbyte
RAM
LCD Segments
4 × 25
ATmega169A
ATmega169PA
ATmega329A
ATmega329PA
ATmega3290A
ATmega3290PA
ATmega649A
ATmega649P
ATmega6490A
ATmega6490P
16Kbyte
16Kbyte
32Kbyte
32Kbyte
32Kbytes
32Kbyte
64Kbyte
64Kbyte
64Kbyte
64Kbyte
1Kbyte
1Kbyte
2Kbyte
2Kbyte
2Kbyte
2Kbyte
4Kbyte
4Kbyte
4Kbyte
4Kbyte
4 × 25
4 × 25
4 × 25
4 × 40
4 × 40
4 × 25
4 × 25
4 × 40
4 × 40
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2.3
Pin descriptions
The following section describes the I/O-pin special functions.
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7...PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the Atmel
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 72.
2.3.4 Port B (PB7...PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 73.
2.3.5 Port C (PC7...PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 76.
2.3.6 Port D (PD7...PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 77.
2.3.7 Port E (PE7...PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 79.
2.3.8 Port F (PF7...PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not
running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be
activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9 Port G (PG5...PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 83.
2.3.10 Port H (PH7...PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 85.
2.3.11 Port J (PJ6...PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 87.
2.3.12 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in ”System and reset characteristics” on page 332. Shorter
pulses are not guaranteed to generate a reset.
2.3.13 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.14 XTAL2
Output from the inverting Oscillator amplifier.
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2.3.15 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.3.16 AREF
This is the analog reference pin for the A/D Converter.
2.3.17 LCDCAP
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 24-2, if the LCD
module is enabled and configured to use internal power. This capacitor acts as a reservoir for LCD power (VLCD). A
large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value.
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3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note:
1.
4.
5.
Data retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
About code examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
6. Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library
User Guide - also available for download from the Atmel website.
7.
Register summary
Note:
Registers with bold type only available in Atmel ATmega3290A/3290PA/6490A/6490P.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
236
236
236
236
236
236
236
236
236
236
236
LCDDR19
LCDDR18
LCDDR17
LCDDR16
LCDDR15
LCDDR14
LCDDR13
LCDDR12
LCDDR11
LCDDR10
LCDDR09
SEG339
SEG331
SEG323
SEG315
SEG307
SEG239
SEG231
SEG223
SEG215
SEG207
SEG139
SEG338
SEG330
SEG322
SEG314
SEG306
SEG238
SEG230
SEG222
SEG214
SEG206
SEG138
SEG337
SEG329
SEG321
SEG313
SEG305
SEG237
SEG229
SEG221
SEG213
SEG205
SEG137
SEG336
SEG328
SEG320
SEG312
SEG304
SEG236
SEG228
SEG220
SEG212
SEG204
SEG136
SEG335
SEG327
SEG319
SEG311
SEG303
SEG235
SEG227
SEG219
SEG211
SEG203
SEG135
SEG334
SEG326
SEG318
SEG310
SEG302
SEG234
SEG226
SEG218
SEG210
SEG202
SEG134
SEG333
SEG325
SEG317
SEG309
SEG301
SEG233
SEG225
SEG217
SEG209
SEG201
SEG133
SEG332
SEG324
SEG316
SEG308
SEG300
SEG232
SEG224
SEG216
SEG208
SEG200
SEG132
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
12
8284FS–AVR–07/2014
Address
Name
LCDDR08
LCDDR07
LCDDR06
LCDDR05
LCDDR04
LCDDR03
LCDDR02
LCDDR01
LCDDR00
Reserved
Reserved
Reserved
Reserved
LCDCCR
LCDFRR
LCDCRB
LCDCRA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTJ
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
236
236
236
236
236
236
236
236
236
SEG131
SEG130
SEG129
SEG128
SEG127
SEG126
SEG125
SEG124
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG039
SEG038
SEG037
SEG036
SEG035
SEG034
SEG033
SEG032
SEG031
SEG030
SEG029
SEG028
SEG027
SEG026
SEG025
SEG024
SEG023
SEG022
SEG021
SEG020
SEG019
SEG018
SEG017
SEG016
SEG015
SEG014
SEG013
SEG012
SEG011
SEG010
SEG009
SEG008
SEG007
SEG006
SEG005
SEG004
SEG003
SEG002
SEG001
SEG000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCDDC2
LCDDC1
LCDDC0
LCDMDT
LCDCC3
LCDCC2
LCDCC1
LCDCC0
234
233
232
231
-
LCDPS2
LCDPS1
LCDPS0
-
LCDCD2
LCDCD1
LCDCD0
LCDCS
LCD2B
LCDMUX1
LCDMUX0
LCDPM3
LCDPM2
LCDPM1
LCDPM0
LCDEN
LCDAB
-
LCDIF
LCDIE
LCDBD
LCDCCD
LCDBL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTJ6
PORTJ5
PORTJ4
PORTJ3
PORTJ2
PORTJ1
PORTJ0
93
93
93
93
93
93
DDRJ
-
DDJ6
DDJ5
DDJ4
DDJ3
DDJ2
DDJ1
DDJ0
PINJ
-
PINJ6
PINJ5
PINJ4
PINJ3
PINJ2
PINJ1
PINJ0
PORTH
PORTH7
PORTH6
PORTH5
PORTH4
PORTH3
PORTH2
PORTH1
PORTH0
DDRH
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
PINH
PINH7
PINH6
PINH5
PINH4
PINH3
PINH2
PINH1
PINH0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART0 Data Register
186
190
190
UBRR0H
UBRR0L
Reserved
UCSR0C
UCSR0B
UCSR0A
Reserved
Reserved
Reserved
Reserved
Reserved
USIDR
USART0 Baud Rate Register High
USART0 Baud Rate Register Low
-
-
-
-
-
-
-
-
-
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
189
188
187
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USI Data Register
197
198
198
USISR
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
Reserved
ASSR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
153
Reserved
Reserved
-
-
-
-
-
-
-
-
-
-
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
13
8284FS–AVR–07/2014
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
153
OCR2A
Timer/Counter 2 Output Compare Register A
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
(0x7C)
(0x7B)
(0x7A)
(0x79)
(0x78)
(0x77)
(0x76)
(0x75)
(0x74)
(0x73)
TCNT2
Timer/Counter2
153
Reserved
TCCR2A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
-
-
-
-
-
-
-
-
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
151
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter1 Output Compare Register B High
Timer/Counter1 Output Compare Register B Low
Timer/Counter1 Output Compare Register A High
Timer/Counter1 Output Compare Register A Low
Timer/Counter1 Input Capture Register High
Timer/Counter1 Input Capture Register Low
Timer/Counter1 High
130
130
130
130
131
131
130
130
ICR1L
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
Timer/Counter1 Low
-
FOC1A
ICNC1
COM1A1
-
-
-
-
-
-
-
-
FOC1B
ICES1
COM1A0
-
-
-
-
-
CS12
-
-
-
129
128
126
203
220
-
WGM13
WGM12
CS11
WGM11
AIN1D
ADC1D
-
CS10
WGM10
AIN0D
ADC0D
-
COM1B1
COM1B0
-
-
-
ADC4D
-
-
ADC3D
-
-
DIDR0
ADC7D
-
ADC6D
-
ADC5D
-
ADC2D
-
Reserved
ADMUX
REFS1
-
REFS0
ACME
ADSC
ADLAR
-
MUX4
-
MUX3
-
MUX2
ADTS2
ADPS2
MUX1
ADTS1
ADPS1
MUX0
ADTS0
ADPS0
216
202/219
218
ADCSRB
ADCSRA
ADCH
ADEN
ADATE
ADIF
ADIE
ADC Data Register High
ADC Data Register Low
219
ADCL
219
Reserved
Reserved
Reserved
Reserved
PCMSK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
64
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
14
8284FS–AVR–07/2014
Address
Name
Reserved
Reserved
TIMSK2
TIMSK1
TIMSK0
PCMSK2
PCMSK1
PCMSK0
Reserved
EICRA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
-
-
-
-
-
-
-
-
(0x72)
-
-
-
-
-
-
-
-
(0x71)
-
-
-
-
-
-
OCIE2A
OCIE1A
OCIE0A
PCINT17
PCINT9
PCINT1
-
TOIE2
TOIE1
TOIE0
PCINT16
PCINT8
PCINT0
-
154
131
137
64
(0x70)
-
-
ICIE1
-
-
OCIE1B
(0x6F)
-
-
-
-
-
-
(0x6E)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
(0x6D)
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
64
(0x6C)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
64
(0x6B)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(0x6A)
ISC01
-
ISC00
-
61
(0x69)
Reserved
Reserved
OSCCAL
Reserved
PRR
(0x68)
-
-
(0x67)
Oscillator Calibration Register [CAL7...0]
38
46
(0x66)
-
-
-
-
-
-
-
-
-
-
(0x65)
-
PRLCD
PRTIM1
PRSPI
PSUSART0
PRADC
(0x64)
Reserved
Reserved
CLKPR
WDTCR
SREG
-
-
-
-
-
-
-
-
(0x63)
-
-
-
-
-
CLKPS3
WDE
V
-
-
-
(0x62)
CLKPCE
-
-
-
WDCE
S
CLKPS2
WDP2
N
CLKPS1
WDP1
Z
CLKPS0
WDP0
C
38
53
15
17
17
(0x61)
-
I
-
-
(0x60)
T
H
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
SPH
Stack Pointer High
Stack Pointer Low
SPL
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
289
JTD
BODS
BODSE
PUD
-
WDRF
SM2
-
-
BORF
SM1
-
IVSEL
EXTRF
SM0
-
IVCE
PORF
SE
59/90/275
-
-
-
JTRF
53
45
-
-
-
-
Reserved
OCDR
-
-
-
OCDR5
ACO
-
-
OCDR4
ACI
-
IDRD/OCDR7
OCDR6
ACBG
-
OCDR3
ACIE
-
OCDR2
ACIC
-
OCDR1
ACIS1
-
OCDR0
ACIS0
-
242
202
ACSR
ACD
-
Reserved
SPDR
-
SPI Data Register
165
164
163
29
SPSR
SPIF
SPIE
WCOL
SPE
-
-
-
-
-
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
CPHA
SPR1
GPIOR2
GPIOR1
Reserved
Reserved
OCR0A
TCNT0
General Purpose I/O Register
General Purpose I/O Register
29
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter0 Output Compare A
Timer/Counter0
138
137
Reserved
TCCR0A
GTCCR
EEARH
EEARL
-
FOC0A
TSM
-
-
-
-
-
-
CS02
-
-
-
WGM00
COM0A1
COM0A0
WGM01
CS01
PSR2
CS00
PSR10
135
138/155
28
-
-
-
-
-
-
-
-
EEPROM Address Register High
EEPROM Address Register Low
EEPROM Data Register
28
EEDR
28
EECR
-
-
-
-
EERIE
EEMWE
EEWE
EERE
28
GPIOR0
EIMSK
General Purpose I/O Register
29
PCIE
PCIE2
PCIE1
PCIE0
-
-
-
INT0
INTF0
-
62
EIFR
PCIF3
PCIF2
PCIF1
PCIF0
-
-
-
63
Reserved
Reserved
Reserved
Reserved
TIFR2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCF2A
OCF1A
OCF0A
PORTG1
DDG1
PING1
TOV2
TOV1
TOV0
PORTG0
DDG0
PING0
154
131
138
92
TIFR1
ICF1
-
-
OCF1B
-
TIFR0
-
-
-
PORTG
DDRG
-
PORTG4
DDG4
PING4
PORTG3
DDG3
PING3
PORTG2
DDG2
PING2
-
92
PING
PING5
92
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
15
8284FS–AVR–07/2014
Address
Name
Bit 7
PORTF7
DDF7
Bit 6
PORTF6
DDF6
Bit 5
PORTF5
DDF5
Bit 4
PORTF4
DDF4
Bit 3
PORTF3
DDF3
Bit 2
PORTF2
DDF2
Bit 1
PORTF1
DDF1
Bit 0
PORTF0
DDF0
Page
92
92
92
91
92
92
91
91
91
91
91
91
90
90
91
90
90
90
PORTF
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
DDRF
PINF
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
PORTE
DDRE
PINE
PORTE7
DDE7
PORTE6
DDE6
PORTE5
DDE5
PORTE4
DDE4
PORTE3
DDE3
PORTE2
DDE2
PORTE1
DDE1
PORTE0
DDE0
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
PORTD
DDRD
PIND
PORTD7
DDD7
PORTD6
DDD6
PORTD5
DDD5
PORTD4
DDD4
PORTD3
DDD3
PORTD2
DDD2
PORTD1
DDD1
PORTD0
DDD0
PIND7
PORTC7
DDC7
PIND6
PORTC6
DDC6
PIND5
PORTC5
DDC5
PIND4
PORTC4
DDC4
PIND3
PORTC3
DDC3
PIND2
PORTC2
DDC2
PIND1
PORTC1
DDC1
PIND0
PORTC0
DDC0
PORTC
DDRC
PINC
PINC7
PORTB7
DDB7
PINC6
PORTB6
DDB6
PINC5
PORTB5
DDB5
PINC4
PORTB4
DDB4
PINC3
PORTB3
DDB3
PINC2
PORTB2
DDB2
PINC1
PORTB1
DDB1
PINC0
PORTB0
DDB0
PORTB
DDRB
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
PORTA
DDRA
PINA
PORTA7
DDA7
PORTA6
DDA6
PORTA5
DDA5
PORTA4
DDA4
PORTA3
DDA3
PORTA2
DDA2
PORTA1
DDA1
PORTA0
DDA0
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a complex microcontroller with more
peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
16
8284FS–AVR–07/2014
8.
Instruction set summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
k
Direct Subroutine Call
Subroutine Return
PC ← k
4
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
k
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
17
8284FS–AVR–07/2014
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
BRIE
BRID
k
k
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
1/2
1/2
1/2
Branch if Interrupt Enabled
Branch if Interrupt Disabled
None
None
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
18
8284FS–AVR–07/2014
Mnemonics
Operands
Description
Operation
Flags
#Clocks
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
None
Watchdog Reset
Break
1
BREAK
N/A
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
19
8284FS–AVR–07/2014
9.
Ordering information
9.1
Atmel ATmega169A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
64A
Operational range
ATmega169A-AU
ATmega169A-AUR (4)
ATmega169A-MU
64A
64M1
64M1
64MC
64MC
Industrial
(-40°C to 85°C)
ATmega169A-MUR (4)
ATmega169A-MCH
ATmega169A-MCHR (4)
16
1.8 - 5.5V
ATmega169A-AN
64A
64A
64M1
64M1
Extended
(-40°C to 105°C)
ATmega169A-ANR (4)
ATmega169A-MN
ATmega169A-MNR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 29-1 on page 330.
4. Tape & Reel.
Package type
64A
64-lead, thin (1.0mm) plastic Gull Wing Quad Flat Package (TQFP)
64M1
64MC
64-pad, 9 × 9 × 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
64-lead (2-row Staggered), 7 × 7 × 1.0mm body, 4.0 × 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
20
8284FS–AVR–07/2014
9.2
Atmel ATmega169PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type(1)
64A
Operational range
ATmega169PA-AU
ATmega169PA-AUR(4)
ATmega169PA-MU
64A
64M1
64M1
64MC
64MC
Industrial
(-40°C to 85°C)
ATmega169PA-MUR(4)
ATmega169PA-MCH
ATmega169PA-MCHR(4)
16
1.8 - 5.5V
ATmega169PA-AN
64A
64A
64M1
64M1
ATmega169PA-ANR(4)
ATmega169PA-MN
ATmega169PA-MNR(4)
Extended
(-40°C to 105°C)(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 29-1 on page 330.
4. Tape & Reel.
5. See characterization specification at 105°C.
Package type
64A
64-lead, thin (1.0mm) plastic Gull Wing Quad Flat Package (TQFP)
64M1
64MC
64-pad, 9 × 9 × 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
64-lead (2-row Staggered), 7 × 7 × 1.0mm body, 4.0 × 4.0mm Exposed Pad, Quad Flat No-Lead Package (QFN)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
21
8284FS–AVR–07/2014
9.3
Atmel ATmega329A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
64A
64A
64M1
64M1
Operational range
ATmega329A-AU
ATmega329A-AUR (4)
ATmega329A-MU
Industrial
(-40°C to 85°C)
ATmega329A-MUR (4)
20
1.8 - 5.5V
ATmega329A-AN
64A
64A
64M1
64M1
ATmega329A-ANR (4)
ATmega329A-MN
Extended
(-40°C to 105°C)(5)
ATmega329A-MNR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape & Reel.
5. See characterization specifications at 105°C.
Package type
64A
64-lead, 14 × 14 × 1.0mm, thin profile plastic Quad Flat Package (TQFP)
64M1
64-pad, 9 × 9 × 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
22
8284FS–AVR–07/2014
9.4
Atmel ATmega329PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
64A
64A
64M1
64M1
Operational range
ATmega329PA-AU
ATmega329PA-AUR(4)
ATmega329PA-MU
ATmega329PA-MUR(4)
Industrial
(-40°C to 85°C)
20
1.8 - 5.5V
ATmega329PA-AN
64A
64A
64M1
64M1
ATmega329PA-ANR(4)
ATmega329PA-MN
ATmega329PA-MNR(4)
Extended
(-40°C to 105°C)(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape &Reel.
5. See characterization specification at 105°C.
Package type
64A
64-lead, 14 × 14 × 1.0mm, thin profile Plastic Quad Flat Package (TQFP)
64M1
64-pad, 9 × 9 × 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
23
8284FS–AVR–07/2014
9.5
Atmel ATmega3290A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
100A
Operational range
ATmega3290A-AU
Industrial
(-40°C to 85°C)
ATmega3290A-AUR (4)
100A
20
1.8 - 5.5V
ATmega3290A-AN
100A
100A
Extended
ATmega3290A-ANR (4)
(-40°C to 105°C)(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape & Reel.
5. See characterization specification at 105°C.
Package type
100A
100-lead, 14 × 14 × 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
24
8284FS–AVR–07/2014
9.6
Atmel ATmega3290PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
100A
Operational range
ATmega3290PA-AU
Industrial
(-40°C to 85°C)
ATmega3290PA-AUR(4)
100A
20
1.8 - 5.5V
ATmega3290PA-AN
100A
100A
Industrial
ATmega3290PA-ANR(4)
(-40°C to 105°C)(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape & Reel.
5. See characterization specification at 105°C.
Package type
100A
100-lead, 14 × 14 × 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
25
8284FS–AVR–07/2014
9.7
Atmel ATmega649A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
64A
64A
64M1
64M1
Operational range
ATmega649A-AU
ATmega649A-AUR (4)
ATmega649A-MU
Industrial
(-40°C to 85°C)
16
1.8 - 5.5V
ATmega649A-MUR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-1 on page 330.
4. Tape & Reel.
Package type
64A
64-lead, 14 × 14 × 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP)
64M1
64-pad, 9 × 9 × 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
26
8284FS–AVR–07/2014
9.8
Atmel ATmega649P
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
64A
64A
64M1
64M1
Operational range
ATmega649P-AU
ATmega649P-AUR (4)
ATmega649P-MU
Industrial
(-40°C to 85°C)
16
1.8 - 5.5 V
ATmega649P-MUR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-1 on page 330.
4. Tape & Reel.
Package type
64A
64-lead, 14 × 14 × 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP)
64M1
64-pad, 9 × 9 × 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
27
8284FS–AVR–07/2014
9.9
Atmel ATmega6490A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
100A
100A
Operational range
ATmega6490A-AU
Industrial
(-40°C to 85°C)
20
1.8 - 5.5V
ATmega6490A-AUR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape & Reel.
Package type
100A
100-lead, 14 × 14 × 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
28
8284FS–AVR–07/2014
9.10 Atmel ATmega6490P
Speed [MHz] (3)
Power supply
Ordering code (2)
Package type (1)
100A
100A
Operational range
ATmega6490P-AU
Industrial
(-40°C to 85°C)
20
1.8 - 5.5V
ATmega6490P-AUR (4)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see Figure 29-2 on page 330.
4. Tape & Reel.
Package Type
100A
100-lead, 14 × 14 × 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
10. Packaging Information
10.1 64A
PIN 1
B
e
PIN 1 IDENTIFIER
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
A
–
–
–
1.20
A1
0.15
0.05
0.95
A2
1.00
1.05
D
15.75
13.90
15.75
16.00
14.00
16.00
16.25
14.10
16.25
D1
Note 2
Notes:
E
Note 2
E1
13.90
14.00
14.10
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protruis.2 pe e. imon ane maximum
B
0.30–
0.45
–
0.20
s
i
o
n
0
5m
m
r
s
i
d
D
ensisD1dE1 ar
C
0.09
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
0.75
L
0.45
–
e
0.80 TYP
2010-10-20
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
64A
C
San Jose, CA 95131
0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
10.2 64M1
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
TOP VIEW
A
K
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Option A
1
Triangle
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MAX
NOM
NOTE
SYMBOL
MIN
E2
Option B
A
0.80
0.90
1.00
Pin #1
Chamfer
A1
0.02
0.05
(C 0.30)
–
b
0.18
0.25
0.30
8.90
9.00
9.10
D
D2
5.20
8.90
5.20
5.40
9.00
5.60
9.10
5.60
Option C
K
Pin #1
Notch
(0.20 R)
E
e
b
E2
5.40
BOTTOM VIEW
e
0.50 BSC
0.35
0.45
L
0.40
1.40
1.25
1.55
Notes:
K
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2010-10-19
2. Dimension and tolerance conform to ASMEY14.5M-1994.
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
64M1
H
San Jose, CA 95131
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
10.3 64MC
C
Pin 1 ID
D
SIDE VIEW
y
A1
E
A
TOP VIEW
eT
L
eT/2
A26
B23
A34
B30
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
A25
B1
B22
MIN
0.80
0.00
0.18
MAX
1.00
0.05
0.28
NOM
0.90
0.02
0.23
0.20 REF
7.00
4.00
7.00
4.00
0.65
0.65
–
NOTE
SYMBOL
0.40
A
b
R0.20
A1
b
D2
C
D
6.90
3.95
6.90
3.95
–
7.10
4.05
7.10
4.05
–
eT
D2
E
B7
B16
A8
A18
(0.18) REF
E2
eT
eR
K
B8
B15
A17
A9
L
E2
(0.1) REF
–
–
K
0.20
0.35
0.00
–
(REF)
BOTTOM VIEW
L
0.40
–
0.45
0.075
1. The terminal #1 ID is a Laser-marked Feature.
Note:
y
10/3/07
GPC
ZXC
DRAWING NO.
TITLE
REV.
64MC, 64QFN (2-Row Staggered),
Package Drawing Contact:
64MC
A
packagedrawings@atmel.com 7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad,
Quad Flat No Lead Package
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
10.4 100A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
E1
B
14.10 Note 2
0.27
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.08mm maximum.
L
–
0.75
e
0.50 TYP
2014-02-05
100A, 100-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
E
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
11. Errata
11.1 Atmel ATmega169A
No known errata
11.2 Atmel ATmega169A/169PA Rev. A to F
Not sampled.
11.3 Atmel ATmega169PA Rev. G
No known errata.
11.4 Atmel ATmega329A/329PA rev. A
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Using BOD disable will make the chip reset
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
2. Using BOD disable will make the chip reset
If the part enters sleep with the BOD turned off with the BOD disable option
enabled, a BOD reset will be generated at wakeup and the chip will reset.
Problem Fix/Workaround
Do not use BOD disable
11.5 Atmel ATmega329A/329PA rev. B
• Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
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8284FS–AVR–07/2014
11.6 Atmel ATmega329A/329PA rev. C
• Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
11.7 Atmel ATmega3290A/3290PA rev. A
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Using BOD disable will make the chip reset
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
2. Using BOD disable will make the chip reset
If the part enters sleep with the BOD turned off with the BOD disable option
enabled, a BOD reset will be generated at wakeup and the chip will reset.
Problem Fix/Workaround
Do not use BOD disable
11.8 Atmel ATmega3290A/3290PA rev. B
• Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
35
8284FS–AVR–07/2014
11.9 Atmel ATmega3290A/3290PA rev. C
• Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/ Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-
ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or
asynchronous Output Compare Register (OCRx).
11.10 Atmel ATmega649A/649P/ATmega6490A/6490P
No known errata.
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
36
8284FS–AVR–07/2014
12. Datasheet revision history
Please note that the referring page numbers in this section are referring to this document.The referring revision in
this section are referring to the document revision.
12.1 Rev. 8284F - 08/2014
1.
2.
New back page
Changed chip references in the text in Section 9.6 ”Low-frequency XTAL oscillator” on page 34.
12.2 Rev. 8284E - 02/2013
1.
2.
New template
Countless, small corrections made throughout the whole document
In Section ”System and reset characteristics” on page 332 the sentence “The following chara apply only
to...” has been deleted
3.
Former Section 29.6 on page 332 (“Power-on reset”), subsection 29.6.1
(“ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490PA revision C and later”) and
subsection 29.6.2 (“ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490PA revision A and B”)
have been deleted
4.
5.
6.
7.
8.
9.
The maximum limits for “Power Supply Current” in Table 29-9 on page 328 have been corrected
The maximum limits for “Power Supply Current” in Table 29-11 on page 329 have been corrected
Added ”Electrical Characteristics – TA = -40°C to 105°C” on page 337.
Added ”Typical Characteristics – TA = -40°C to 105°C” on page 658.
Updated ”Ordering information” on page 20
12.3 Rev. 8284D - 06/11
1.
2.
Removed “Preliminary” from the front page
Updated the Table 29-16 on page 344. VPOT falling / Min. is 0.05V, not 0.5V
12.4 Rev. 8284C - 06/11
1.
2.
Updated ”Signature Bytes” on page 294. A, P, and PA devices have different signature (0x002) bytes.
Updated all ”DC Characteristics” on page 323.
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
37
8284FS–AVR–07/2014
12.5 Rev. 8284B - 03/11
1.
2.
3.
Updated the datasheet according to the Atmel new Brand Style Guide.
Updated all ”Ordering information” on page 20.
Updated ”Packaging Information” on page 30.
12.6 Rev. 8284A - 10/10
1.
Initial revision
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]
38
8284FS–AVR–07/2014
X
X X X X
X
Atmel Corporation
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T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
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Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR ® and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
2014 Atmel Corporation. / Rev.: Atmel-8284FS-AVR-ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P-Datasheet_07/2014
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of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical
Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor
intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in
automotive applications unless specifically designated by Atmel as automotive-grade.
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