ATSAMA5D27C-D5M-CU [MICROCHIP]

SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM;


型号：	ATSAMA5D27C-D5M-CU
厂家：	MICROCHIP
描述：	SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM 时钟动态存储器双倍数据速率光电二极管外围集成电路
文件：	总56页 (文件大小：1680K)
中文：	中文翻译
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SAMA5D2 SIP

SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit

DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM

Scope

This document is an overview of the main features of the SAMA5D2 SIP. The sole reference documents for product

information on the SAMA5D2 and the LPDDR2/DDR2-SDRAM memories are listed in the table below.

Introduction

The SAMA5D2 System-In-Package (SIP) integrates the Arm Cortex -A5 processor-based SAMA5D2 MPU with up

to 1 Gbit DDR2-SDRAM or up to 2 Gbit LPDDR2-SDRAM in a single package.

By combining the high-performance, ultra-low power SAMA5D2 with LPDDR2/DDR2-SDRAM in a single package,

PCB routing complexity, area and number of layers is reduced in the majority of cases. This makes board design

easier and more robust by facilitating design for EMI, ESD and signal integrity.

DDR2-SDRAM memory sizes and package options available

•

128 Mbit, TFBGA196

512 Mbit and 1 Gbit, TFBGA289

LPDDR2-SDRAM memory sizes and package options available

1 Gbit and 2 Gbit, TFBGA361

•

While the smallest option targets applications with a small OS or bare metal, the larger options are suitable for

applications using Linux .

Reference Documents

Type

Document Title

Available

Ref. No.

Data sheet

SAMA5D2 Series

www.microchip.com

DS60001476

2 Mwords × 4 Banks × 16 bits

DDR2 SDRAM (128 Mbit)

Data sheet

www.winbond.com

www.apmemory.com

W9712G6KB25I

8 Mwords × 4 Banks × 16 bits

DDR2 SDRAM (512 Mbit)

W9751G6KB25I

8 Mwords × 8 Banks × 16 bits

DDR2 SDRAM (1 Gbit)

W971GG6SB25I

AD210032F-I-AB

AD220032D-I-ED/PC/AB

4 Mwords × 8 Banks × 32 bits

LPDDR2-SDRAM (1 Gbit)

8 Mwords × 8 Banks × 32 bits

LPDDR2-SDRAM (2 Gbit)

DS60001484D-page 1

Datasheet

SAMA5D2 SIP

Table of Contents

Scope............................................................................................................................................................. 1

Introduction.....................................................................................................................................................1

Reference Documents....................................................................................................................................1

1. Features..................................................................................................................................................4

2. DDR2-SDRAM Features.........................................................................................................................7

3. LPDDR2-SDRAM Features.....................................................................................................................8

4. Configuration Summary.......................................................................................................................... 9

5. Chip Identifier........................................................................................................................................10

6. Package and Ballout..............................................................................................................................11

7. Memory................................................................................................................................................. 39

8. Electrical Characteristics.......................................................................................................................40

8.1. Recommended Thermal Operating Conditions..........................................................................40

8.2. Decoupling................................................................................................................................. 40

8.3. Power Sequences...................................................................................................................... 40

9. Mechanical Characteristics................................................................................................................... 45

9.1. 361-ball TFBGA..........................................................................................................................45

9.2. 289-ball TFBGA..........................................................................................................................48

9.3. 196-ball TFBGA..........................................................................................................................49

10. Ordering Information............................................................................................................................. 50

11. Revision History.................................................................................................................................... 51

11.1. DS60001484D - 03/2021............................................................................................................51

11.2. DS60001484C - 01/2020............................................................................................................51

11.3. DS60001484B - 11/2018............................................................................................................51

11.4. DS60001484A - 09/2017............................................................................................................51

The Microchip Website.................................................................................................................................52

Product Change Notification Service............................................................................................................52

Customer Support........................................................................................................................................ 52

Product Identification System.......................................................................................................................53

Microchip Devices Code Protection Feature................................................................................................53

Legal Notice................................................................................................................................................. 54

Trademarks.................................................................................................................................................. 54

Quality Management System....................................................................................................................... 55

DS60001484D-page 2

Datasheet

SAMA5D2 SIP

Worldwide Sales and Service.......................................................................................................................56

DS60001484D-page 3

Datasheet

SAMA5D2 SIP

Features

•

Arm Cortex-A5 Core

– ARMv7-A architecture

– Arm TrustZone

– NEON^™Media Processing Engine

– Up to 500 MHz

– ETM/ETB 8 Kbytes

•

Memory Architecture

– Memory Management Unit

– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache

– 128-Kbyte L2 cache configurable to be used as an internal SRAM

– DDR2-SDRAM memory up to 1 Gb

– LPDDR2-SDRAM memory up to 2 Gb

– One 128-Kbyte scrambled internal SRAM

– One 160-Kbyte internal ROM

•

64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader

96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table

– High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting

Winbond DDR2-SDRAM up to 1 Gb, including “on-the-fly” encryption/decryption path

– High-bandwidth scramblable 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting

AP memory LPDDR2-SDRAM up to 2 Gb , including “on-the-fly” encryption/ decryption path

– 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)

System Running up to 166 MHz

•

– Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-

Time Clock (RTC) with clock calibration

– One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed

– Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)

– Internal low-power 12 MHz RC and 32 KHz typical RC

– Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator

– 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers

– 64-bit Advanced Interrupt Controller (AIC)

– 64-bit Secure Advanced Interrupt Controller (SAIC)

– Three programmable external clock signals

•

Low-Power Modes

– Ultra-Low-Power mode with fast wake-up capability

™

– Low-Power Backup mode with 5-Kbyte SRAM and SleepWalking features

•

Wake-up from up to nine wake-up pins, UART reception, analog comparison

Fast wake-up capability

Extended Backup mode with LPDDR2/DDR2-SDRAM in Self-Refresh mode

Peripherals

– LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit

parallel RGB

– ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel

12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface

– Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D

amplifier

– One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)

– One Pulse Density Modulation Interface Controller (PDMIC)

DS60001484D-page 4

Datasheet

SAMA5D2 SIP

Features

– One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host

ports (UHPHS)

– One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface

– One 10/100 Ethernet MAC (GMAC)

•

Energy efficiency support (IEEE 802.3az standard)

Ethernet AVB support with IEEE802.1AS time stamping

IEEE 802.1Qav credit-based traffic-shaping hardware support

IEEE1588 Precision Time Protocol (PTP)

– Two high-speed memory card hosts:

•

SDMMC0: SD 3.0, eMMC 4.51, 8 bits

SDMMC1: SD 2.0, eMMC 4.41, 4 bits only

– Two host/client Serial Peripheral Interfaces (SPI)

– Two Quad Serial Peripheral Interfaces (QSPI)

– Five FLEXCOMs (USART, SPI and TWI)

– Five UARTs

– Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered

transmission

MCAN implements the non-ISO CAN FD frame format and therefore does not pass the CAN FD

Conformance Test according to ISO 16845-1:2016.

WARNING

– One Rx only UART in backup area (RXLP)

– One analog comparator (ACC) in backup area

– Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I²C protocol and SMBUS (TWIHS)

– Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes

– One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller

– One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability

•

Safety

– Zero-power Power-On Reset (POR) cells

– Main crystal clock failure detector

– Write-protected registers

– Integrity Check Monitor (ICM) based on SHA256

– Memory Management Unit

– Independent watchdog

•

Security

– 5 Kbytes of internal scrambled SRAM:

•

1 Kbyte non-erasable on tamper detection

4 Kbytes erasable on tamper detection

– 256 bits of scrambled and erasable registers

– Up to eight tamper pins for static or dynamic intrusion detections⁽¹⁾

– Environmental monitors on specific versions: temperature, voltage, frequency and active die shield⁽²⁾

– Secure Boot Loader⁽³⁾

– On-the-fly AES encryption/decryption on LPDDR2/DDR2-SDRAM and QSPI memories (AESB)

– RTC including time-stamping on security intrusions

– Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)

Hardware Cryptography

•

– SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2

– AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197

– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3

DS60001484D-page 5

Datasheet

SAMA5D2 SIP

Features

– True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and

FIPS PUBs 140-2 and 140-3

•

Up to 128 I/Os

– Fully programmable through set/clear registers

– Multiplexing of up to eight peripheral functions per I/O line

– Each I/O line can be assigned to a peripheral or used as a general purpose I/O

– PIO controller features a synchronous output providing up to 32 bits of data output in one write operation

Operating Conditions

– Ambient temperature: -40°C to +85°C

Note:ꢀ

1. For information specific to dynamic tamper protection (PIOBU), refer to the document SAMA5D2 External

Tamper Protections (document no. 44095). Contact a Microchip sales representative for details.

2. For environmental monitors, refer to the document SAMA5D23 and SAMA5D28 Environmental Monitors

(document no. 44036), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales

representative for details.

3. For secure boot strategies, refer to the document SAMA5D2 Series Secure Boot Strategy (document no.

DS00002435), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales representative for

details.

DS60001484D-page 6

Datasheet

SAMA5D2 SIP

DDR2-SDRAM Features

•

Power Supply: DDRM_VDD, DDRM_VDDL, DDRM_VDDQ = 1.8 V ±0.1 V

Double Data Rate Architecture: Two Data Transfers per Clock Cycle

CAS Latency: 3

Burst Length: 8

Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data

Edge-Aligned with Read Data and Center-Aligned with Write Data

DLL Aligns DQ and DQS Transitions with Clock

Differential Clock Inputs (CLK and CLKN)

Data Masks (DM) for Write Data

Commands Entered on Each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS

Auto-Refresh and Self-Refresh Modes

Precharged Power-Down and Active Power-Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18

DS60001484D-page 7

Datasheet

SAMA5D2 SIP

LPDDR2-SDRAM Features

•

Power Supply: DDRM_VDD18 = 1.7 to 1.9V

Power Supply: DDRM_VDD12 = 1.14 to 1.3V

Double Data Rate Architecture: Two Data Transfers per Clock Cycle

Burst Length (BL): 8

Write Latency (WL): 1

Read Latency (RL): 3

Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data

Edge-Aligned with Read Data and Center-Aligned with Write Data

Differential Clock Inputs (CLK and CLKN)

Data Masks (DM) for Write Data

Commands Entered on each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS

Interface: HSUL_12

Auto-Refresh and Self-Refresh Modes

Low Power Consumption

JEDEC LPDDR2-S4B Compliance

Partial Array Self-Refresh (PASR)

Auto Temperature Compensated Self-Refresh (ATCSR) by Built-in Temperature Sensor

Deep Power-Down Mode

DS60001484D-page 8

Datasheet

SAMA5D2 SIP

Configuration Summary

Table 4-1.ꢀConfiguration Summary

Feature

SAMA5D225

TFBGA196

128 Mb

SAMA5D27

SAMA5D28

Package

TFBGA289

TFBGA361

TFBGA289

TFBGA361

DDR2-SDRAM

LPDDR2-SDRAM

SMC

512 Mb

–

1 Gb

–

1 Gb

–

1 Gb

2 Gb

1 Gb

2 Gb

Up to 16-bit

32-bit

Internal Memory Bus

Width

16-bit

32-bit

PIOs

SRAM

QSPI

LCD

128

128 Kbytes

24-bit RGB

Camera Interface

(ISC)

EMAC

PTC

4 X-lines x 8 Y-

lines

8 X-lines x 8 Y-lines

CAN

USB

(2 Hosts or 1

Host/1 Device)

(2 Hosts/1 HSIC or 1 Host/1 Device/1 HSIC)

UART/SPI/I C

9 / 7 / 7

10 / 7 / 7

SDIO/SD/MMC

I S/SSC/Class

2 / 2 / 1 / 1

D/PDM

ADC Inputs

Timers

4 (PWM) + 5

(TC)

PWM

4 (PWM) + 6 (TC)

Tamper Pins

AESB

Yes

Environmental

–

Yes

Monitors, Die Shield

DS60001484D-page 9

Datasheet

SAMA5D2 SIP

Chip Identifier

Table 5-1.ꢀSAMA5D2 SIP Chip ID Registers

Chip Name

CHIPID_CIDR

CHIPID_EXID

SAMA5D225C-D1M

SAMA5D27C-D5M

SAMA5D27C-D1G

SAMA5D27C-LD1G

0x00000053

0x00000032

0x00000033

0x00000061

0x00000062

0x00000013

0x00000071

0x00000072

0x8A5C08C2 or 0x8A5C08C4

SAMA5D27C-LD2G

SAMA5D28C-D1G

SAMA5D28C-LD1G

SAMA5D28C-LD2G

DS60001484D-page 10

Datasheet

SAMA5D2 SIP

Package and Ballout

The SAMA5D2 SIP is available in the packages listed below.

Important:ꢀ SAMA5D2 DDR2 SIP devices are not pin-to-pin compatible with SAMA5D2 devices.

Table 6-1.ꢀPackages

Package Name

TFBGA196

Ball Count

196

Ball Pitch

0.75 mm

0.8 mm

Package Size

11 x 11 (mm)

14 x 14 (mm)

16 x 16 (mm)

TFBGA289⁽¹⁾

TFBGA361⁽²⁾

289

361

0.8 mm

Notes:ꢀ

1. 512 Mbit and 1 Gbit DDR2 in TFBGA289 have the same ballout.

2. 1 Gbit and 2 Gbit LPDDR2 in TFBGA361 have the same ballout.

DS60001484D-page 11

Datasheet

Table 6-2.ꢀBall Description

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

BGA

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

W11

U13

VDDSDMMC

GPIO_EMMC

GGPIO_EMMC

GPIO_EMMC

PA0

PA1

PA2

PA3

PA4

PA5

PA6

I/O

–

SDMMC0_CK

QSPI0_SCK

I/O

PIO, I, PU, ST

I/O

VDDSDMMC

I/O

SDMMC0_CMD

QSPI0_CS

I/O

W12

V11

W14

V10

W15

U14

T13

U15

U16

U17

SDMMC0_DAT0

QSPI0_IO0

SDMMC0_DAT1

QSPI0_IO1

SDMMC0_DAT2

QSPI0_IO2

SDMMC0_DAT3

QSPI0_IO3

P10

SDMMC0_DAT4

QSPI1_SCK

TIOA5

I/O

FLEXCOM2_IO0

W16

R11

P11

VDDSDMMC

GPIO_EMMC

PA7

I/O

–

SDMMC0_DAT5

QSPI1_IO0

TIOB5

PIO, I, PU, ST

FLEXCOM2_IO1

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

V12

V16

V14

L18

VDDSDMMC

GPIO_EMMC

GPIO

PA8

I/O

–

SDMMC0_DAT6

QSPI1_IO1

TCLK5

I/O

PIO, I, PU, ST

FLEXCOM2_IO2

NWE/NANDWE

SDMMC0_DAT7

QSPI1_IO2

TIOA4

I/O

VDDSDMMC

VDDIOP1

PA9

I/O

FLEXCOM2_IO3

NCS3

R10

P15

N14

N13

PA10

PA11

SDMMC0_RSTN

QSPI1_IO3

TIOB4

I/O

FLEXCOM2_IO4

A21/NANDALE

SDMMC0_1V8SEL

QSPI1_CS

TCLK4

A22/NANDCLE

SDMMC0_WP

IRQ

T16

K18

R19

N17

P16

M17

L12

M14

J10

VDDIOP1

GPIO

PA12

PA13

PA14

I/O

–

PIO, I, PU, ST

NRD/NANDOE

SDMMC0_CD

FLEXCOM3_IO1

I/O

GPIO_QSPI

SPI0_SPCK

TK1

QSPI0_SCK

I2SC1_MCK

FLEXCOM3_IO2

I/O

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

L17

N19

M16

V19

V15

N16

L14

H14

K14

VDDIOP1

GPIO

PA15

PA16

PA17

PA18

PA19

I/O

–

SPI0_MOSI

TF1

I/O

PIO, I, PU, ST

QSPI0_CS

I2SC1_CK

FLEXCOM3_IO0

D10

I/O

M11

N14

T16

T15

VDDIOP1

GPIO_IO

I/O

SPI0_MISO

TD1

QSPI0_IO0

I2SC1_WS

FLEXCOM3_IO3

D11

I/O

SPI0_NPCS0

RD1

QSPI0_IO1

I2SC1_DI0

FLEXCOM3_IO4

D12

I/O

SPI0_NPCS1

RK1

I/O

QSPI0_IO2

I2SC1_DO0

SDMMC1_DAT0

D13

I/O

P12

SPI0_NPCS2

RF1

I/O

QSPI0_IO3

TIOA0

SDMMC1_DAT1

D14

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

T10

U19

VDDIOP1

GPIO_IO

PA20

PA21

I/O

–

SPI0_NPCS3

TIOB0

I/O

PIO, I, PU, ST

SDMMC1_DAT2

D15

P10

T17

VDDIOP1

I/O

–

IRQ

PIO, I, PU, ST

PCK2

TCLK0

SDMMC1_DAT3

NANDRDY

FLEXCOM1_IO2

I/O

V17

K10

GPIO_QSPI

PA22

–

I/O

PIO, I, PU, ST

TCK

SPI1_SPCK

SDMMC1_CK

QSPI0_SCK

FLEXCOM1_IO1

I/O

U18

W17

W18

T14

R17

R16

G10

P13

H10

VDDIOP1

GPIO

PA23

PA24

PA25

I/O

–

I/O

PIO, I, PU, ST

TDI

SPI1_MOSI

QSPI0_CS

FLEXCOM1_IO0

I/O

GPIO_IO

I/O

TDO

SPI1_MISO

QSPI0_IO0

FLEXCOM1_IO3

I/O

TMS

SPI1_NPCS0

QSPI0_IO1

I/O

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

U14

M18

P17

L10

VDDIOP1

GPIO_IO

PA26

I/O

–

FLEXCOM1_IO4

I/O

PIO, I, PU, ST

NTRST

SPI1_NPCS1

QSPI0_IO2

TIOA1

I/O

R15

P14

VDDIOP1

GPIO_IO

PA27

I/O

–

PIO, I, PU, ST

SPI0_NPCS2

SPI1_NPCS2

SDMMC1_RSTN

QSPI0_IO3

TIOB1

I/O

U13

R14

N12

VDDIOP1

GPIO

PA28

I/O

–

PIO, I, PU, ST

SPI0_NPCS3

SPI1_NPCS3

SDMMC1_CMD

CLASSD_L0

TCLK1

I/O

U16

U12

U17

P14

R13

P13

M12

N11

M11

VDDIOP1

GPIO

PA29

PA30

PA31

I/O

–

PIO, I, PU, ST

I/O

SPI0_NPCS1

SDMMC1_WP

CLASSD_L1

NWE/NANDWE

SPI0_NPCS0

PWMH0

I/O

SDMMC1_CD

CLASSD_L2

NCS3

SPI0_MISO

PWML0

I/O

CLASSD_L3

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO

PB0

I/O

–

A21/NANDALE

SPI0_MOSI

PWMH1

I/O

PIO, I, PU, ST

VDDIOP0

PB1

I/O

–

A22/NANDCLE

SPI0_SPCK

PWML1

PIO, I, PU, ST

CLASSD_R0

NRD/NANDOE

PWMFI0

CLASSD_R1

URXD4

A10

A11

VDDIOP0

GPIO

PB2

PB3

I/O

–

PIO, I, PU, ST

I/O

IRQ

PWMEXTRG1

CLASSD_R2

UTXD4

I/O

A12

VDDIOP0

GPIO

PB4

PB5

I/O

–

PIO, I, PU, ST

FIQ

CLASSD_R3

TCLK2

A10

GPIO_QSPI

D10

I/O

PWMH2

QSPI1_SCK

GTSUCOMP

TIOA2

VDDIOP0

GPIO

PB6

I/O

–

PIO, I, PU, ST

D11

PWML2

QSPI1_CS

GTXER

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO_IO

GPIO

PB7

I/O

–

TIOB2

D12

I/O

PIO, I, PU, ST

PWMH3

QSPI1_IO0

GRXCK

TCLK3

I/O

VDDIOP0

PB8

I/O

D13

I/O

PWML3

QSPI1_IO1

GCRS

I/O

PB9

TIOA3

I/O

D14

PWMFI1

QSPI1_IO2

GCOL

I/O

PB10

PB11

PB12

TIOB3

I/O

D15

PWMEXTRG2

QSPI1_IO3

GRX2

I/O

LCDDAT0

A0/NBS0

URXD3

PDMIC_DAT

GRX3

GPIO

LCDDAT1

UTXD3

PDMIC_CLK

GTX2

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO

PB13

PB14

I/O

–

LCDDAT2

I/O

PIO, I, PU, ST

PCK1

GTX3

VDDIOP0

GPIO_QSPI

I/O

–

LCDDAT3

PIO, I, PU, ST

TK1

I2SC1_MCK

QSPI1_SCK

GTXCK

LCDDAT4

GPIO

PB15

PB16

PB17

–

PIO, I, PU, ST

TF1

I2SC1_CK

QSPI1_CS

GTXEN

LCDDAT5

GPIO_IO

TD1

I2SC1_WS

QSPI1_IO0

GRXDV

LCDDAT6

GPIO_IO

RD1

I2SC1_DI0

QSPI1_IO1

GRXER

I/O

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO_IO

GPIO

PB18

PB19

PB20

PB21

PB22

I/O

–

LCDDAT7

PIO, I, PU, ST

RK1

I/O

I2SC1_DO0

QSPI1_IO2

GRX0

I/O

VDDIOP0

I/O

LCDDAT8

RF1

I/O

TIOA3

QSPI1_IO3

GRX1

LCDDAT9

TK0

I/O

TIOB3

PCK1

GTX0

GPIO

LCDDAT10

A10

TF0

I/O

TCLK3

FLEXCOM3_IO2

GTX1

I/O

GPIO

LCDDAT11

A11

TD0

TIOA2

I/O

FLEXCOM3_IO1

GMDC

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

PB23

Dir

Signal

–

Dir

–

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO

I/O

LCDDAT12

A12

PIO, I, PU, ST

RD0

TIOB2

I/O

FLEXCOM3_IO0

GMDIO

VDDIOP0

GPIO

PB24

I/O

–

LCDDAT13

A13

PIO, I, PU, ST

RK0

TCLK2

FLEXCOM3_IO3

ISC_D10

LCDDAT14

A14

VDDIOP0

GPIO

PB25

PB26

PB27

I/O

–

I/O

PIO, I, PU, ST

RF0

FLEXCOM3_IO4

ISC_D11

LCDDAT15

A15

URXD0

PDMIC_DAT

ISC_D0

LCDDAT16

A16

UTXD0

PDMIC_CLK

ISC_D1

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDIOP0

GPIO

PB28

PB29

PB30

PB31

PC0

I/O

–

LCDDAT17

A17

I/O

PIO, I, PU, ST

FLEXCOM0_IO0

TIOA5

ISC_D2

VDDIOP0

VDDIOP1

I/O

LCDDAT18

A18

I/O

FLEXCOM0_IO1

TIOB5

ISC_D3

LCDDAT19

A19

I/O

FLEXCOM0_IO2

TCLK5

ISC_D4

LCDDAT20

A20

I/O

FLEXCOM0_IO3

TWD0

ISC_D5

T14

R16

N10

N11

L13

H11

LCDDAT21

A23

I/O

FLEXCOM0_IO4

TWCK0

ISC_D6

PC1

LCDDAT22

A24

I/O

CANTX0

SPI1_SPCK

I2SC0_CK

ISC_D7

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

T15

T13

P16

L19

R15

L11

F13

G14

J14

J13

VDDIOP1

GPIO

PC2

PC3

PC4

PC5

PC6

I/O

–

LCDDAT23

A25

PIO, I, PU, ST

CANRX0

SPI1_MOSI

I2SC0_MCK

ISC_D8

I/O

M10

N15

M16

L11

VDDIOP1

I/O

LCDPWM

NWAIT

TIOA1

I/O

SPI1_MISO

I2SC0_WS

ISC_D9

LCDDISP

NWR1/NBS1

TIOB1

I/O

SPI1_NPCS0

I2SC0_DI0

ISC_PCK

LCDVSYNC

NCS0

TCLK1

SPI1_NPCS1

I2SC0_DO0

ISC_VSYNC

LCDHSYNC

NCS1

I/O

TWD1

SPI1_NPCS2

ISC_HSYNC

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

PC7

Dir

Signal

–

Dir

–

Func

Dir

(1)

Set

HiZ, ST)

N15

M15

F14

VDDIOP1

GPIO_CLK

I/O

LCDPCK

NCS2

I/O

PIO, I, PU, ST

TWCK1

SPI1_NPCS3

URXD1

ISC_MCK

LCDDEN

NANDRDY

FIQ

P11

M13

K13

VDDIOP1

GPIO

PC8

I/O

–

PIO, I, PU, ST

PCK0

UTXD1

ISC_FIELD

FIQ

–

VDDISC

GPIO

PC9

I/O

–

PIO, I, PU, ST

GTSUCOMP

ISC_D0

TIOA4

I/O

PC10

LCDDAT2

GTXCK

ISC_D1

TIOB4

I/O

CANTX0

LCDDAT3

GTXEN

ISC_D2

TCLK4

–

VDDISC

GPIO

PC11

I/O

–

PIO, I, PU, ST

CANRX0

A0/NBS0

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

PC12

Dir

Signal

–

Dir

–

Func

Dir

(1)

Set

HiZ, ST)

–

VDDISC

GPIO

I/O

LCDDAT4

GRXDV

ISC_D3

URXD3

TK0

PIO, I, PU, ST

I/O

–

VDDISC

GPIO

PC13

I/O

–

LCDDAT5

GRXER

ISC_D4

UTXD3

TF0

PIO, I, PU, ST

I/O

–

VDDISC

GPIO

PC14

PC15

PC16

I/O

–

LCDDAT6

GRX0

ISC_D5

TD0

PIO, I, PU, ST

LCDDAT7

GRX1

ISC_D6

RD0

LCDDAT10

GTX0

ISC_D7

RK0

I/O

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

–

VDDISC

GPIO

PC17

PC18

PC19

PC20

PC21

PC22

I/O

–

LCDDAT11

GTX1

PIO, I, PU, ST

ISC_D8

RF0

I/O

VDDISC

I/O

LCDDAT12

GMDC

ISC_D9

FLEXCOM3_IO2

I/O

LCDDAT13

GMDIO

ISC_D10

FLEXCOM3_IO1

I/O

LCDDAT14

GRXCK

ISC_D11

FLEXCOM3_IO0

I/O

LCDDAT15

GTXER

ISC_PCK

FLEXCOM3_IO3

A10

LCDDAT18

GCRS

ISC_VSYNC

FLEXCOM3_IO4

A11

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

–

VDDISC

GPIO

GPIO_CLK

GPIO

PC23

PC24

PC25

PC26

PC27

I/O

–

LCDDAT19

GCOL

PIO, I, PU, ST

ISC_HSYNC

A12

VDDISC

I/O

LCDDAT20

GRX2

ISC_MCK

A13

LCDDAT21

GRX3

ISC_FIELD

A14

VDDIOP2

GPIO

LCDDAT22

GTX2

CANTX1

A15

B10

GPIO

LCDDAT23

GTX3

PCK1

CANRX1

TWD0

I/O

A16

–

VDDIOP2

GPIO

PC28

PC29

I/O

–

LCDPWM

FLEXCOM4_IO0

PCK2

PIO, I, PU, ST

TWCK0

A17

LCDDISP

FLEXCOM4_IO1

A18

PIO, I, PU, ST

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

–

VDDIOP2

GPIO

PC30

I/O

–

LCDVSYNC

FLEXCOM4_IO2

A19

I/O

PIO, I, PU, ST

A11

VDDIOP2

PC31

I/O

–

LCDHSYNC

FLEXCOM4_IO3

URXD3

PIO, I, PU, ST

A20

–

GPIO_CLK

PD0

–

LCDPCK

FLEXCOM4_IO4

UTXD3

PIO, I, PU, ST

GTSUCOMP

A23

–

VDDIOP2

GPIO

PD1

PD2

I/O

–

LCDDEN

GRXCK

A24

PIO, I, PU, ST

GPIO_CLK

URXD1

GTXER

ISC_MCK

A25

–

VDDANA

GPIO_AD

PD3

PD4

I/O

PTC_X0

PTC_X1

–

UTXD1

PIO, I, PU, ST

FIQ

GCRS

ISC_D11

NWAIT

TWD1

I/O

PIO, I, PU, ST

URXD2

GCOL

ISC_D10

NCS0

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

–

VDDANA

GPIO_AD

PD5

PD6

PD7

PD8

I/O

PTC_X2

PTC_X3

PTC_X4

PTC_X5

–

TWCK1

UTXD2

I/O

PIO, I, PU, ST

GRX2

ISC_D9

NCS1

–

VDDANA

I/O

–

TCK

PCK1

GRX3

ISC_D8

NCS2

TDI

UTMI_RXVAL

GTX2

ISC_D0

NWR1/NBS1

TDO

UTMI_RXERR

GTX3

ISC_D1

NANDRDY

TMS

VDDANA

GPIO_AD

PD9

I/O

PTC_X6

PTC_X7

–

PIO, I, PU, ST

UTMI_RXACT

GTXCK

ISC_D2

NTRST

UTMI_HDIS

GTXEN

ISC_D3

I/O

PD10

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDANA

GPIO_AD

PD11

PD12

PD13

PD14

PD15

I/O

PTC_Y0

PTC_Y1

PTC_Y2

PTC_Y3

PTC_Y4

–

TIOA1

PCK2

I/O

PIO, I, PU, ST

A, PU, ST

UTMI_LS0

GRXDV

ISC_D4

ISC_MCK

TIOB1

VDDANA

I/O

–

I/O

FLEXCOM4_IO0

UTMI_LS1

GRXER

I/O

ISC_D5

ISC_D4

TCLK1

FLEXCOM4_IO1

UTMI_CDRCPSEL0

GRX0

I/O

ISC_D6

ISC_D5

TCK

FLEXCOM4_IO2

UTMI_CDRCPSEL1

GRX1

I/O

ISC_D7

ISC_D6

TDI

PIO, I, PU, ST

FLEXCOM4_IO3

UTMI_CDRCPDIVEN

GTX0

ISC_PCK

ISC_D7

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

PD16

Dir

Signal

PTC_Y5

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDANA

GPIO_AD

I/O

–

TDO

FLEXCOM4_IO4

UTMI_CDRBISTEN

GTX1

PIO, I, PU, ST

ISC_VSYNC

ISC_D8

VDDANA

GPIO_AD

PD17

I/O

PTC_Y6

–

TMS

A, PU, ST

UTMI_CDRCPSELDIV

GMDC

ISC_HSYNC

ISC_D9

VDDANA

GPIO_AD

PD18

PD19

I/O

PTC_Y7

AD0

–

NTRST

PIO, I, PU, ST

GMDIO

I/O

ISC_FIELD

ISC_D10

PCK0

I/O

TWD1

URXD2

I2SC0_CK

ISC_D11

I/O

VDDANA

GPIO_AD

PD20

PD21

I/O

AD1

AD2

–

TIOA2

I/O

PIO, I, PU, ST

TWCK1

UTXD2

I2SC0_MCK

ISC_PCK

TIOB2

I/O

PIO, I, PU, ST

TWD0

FLEXCOM4_IO0

I2SC0_WS

ISC_VSYNC

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

VDDANA

GPIO_AD

PD22

I/O

AD3

–

TCLK2

TWCK0

PIO, I, PU, ST

I/O

FLEXCOM4_IO1

I2SC0_DI0

ISC_HSYNC

URXD2

VDDANA

GPIO_AD

PD23

I/O

AD4

–

PIO, I, PU, ST

FLEXCOM4_IO2

I2SC0_DO0

ISC_FIELD

UTXD2

I/O

–

VDDANA

GPIO_AD

PD24

PD25

PD26

PD27

I/O

AD5

AD6

AD7

AD8

–

PIO, I, PU, ST

FLEXCOM4_IO3

SPI1_SPCK

FLEXCOM4_IO4

SPI1_MOSI

FLEXCOM2_IO0

SPI1_MISO

TCK

I/O

FLEXCOM2_IO1

SPI1_NPCS0

TDI

I/O

–

VDDANA

GPIO_AD

PD28

PD29

I/O

AD9

–

PIO, I, PU, ST

FLEXCOM2_IO2

SPI1_NPCS1

TDO

I/O

AD10

FLEXCOM2_IO3

TIOA3

I/O

TWD0

N10

–

VDDANA

GPIO_AD

PD30

I/O

AD11

–

SPI1_NPCS2

TMS

PIO, I, PU, ST

FLEXCOM2_IO4

TIOB3

I/O

TWCK0

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

–

VDDANA

GPIO

PD31

I/O

–

ADTRG

–

PIO, I, PU, ST

NTRST

IRQ

TCLK3

PCK0

–

VDDANA

–

ADVREF

VDDANA

–

G1, H6

F1, G5

M12, J10

K4, J5

J6, M1

J10, F11

K3, L2

L3, K1

power

ground

DDR

–

GNDANA

VDDIODDR

GNDANA

DDR_VREF

–

K12,

F12

–

C19

VDDIODDR

DDR

E11, E8, L10, L14, J8, F10, E8, E9,

power

VDDIODDR

–

H10, J13,

J8, L10,

P12

H10, G12,

E11, E8

E10, G12,

H12, J12

E10, F8,

G10, J9,

K10, M14, K11, J11, F9,

GNDIODDR

ground

GNDIODDR

–

J9, G10,

C10, E11,

F8, F11,

L11, M13, H12, E10, F8

N12

G13, H13

C3, C9, K3, H2, U3, P7, G7, H4, D14,

VDDCORE

GNDCORE

power

VDDCORE

GNDCORE

–

U9, V5,

W6, K8

L12, E9, D7

E14, L5

A1, D9,

E12, F12,

G11, E12,

ground

J11, K4, J11, K11, K6, E13, H3, H7,

K7, V9, W1

H8, J3

B4, D5

D4, F3

F4, E4

VDDIOP0

GNDIOP0

VDDIOP1

GNDIOP1

power

ground

power

ground

VDDIOP0

GNDIOP0

VDDIOP1

GNDIOP1

–

A5, D4

E3, F2

E5, F5

V13, V18

N12, P12

M12, P11

N9, N10

M9, M10

P13, R13,

W13, W19

–

VDDIOP2

GNDIOP2

power

ground

power

ground

VDDIOP2

GNDIOP2

–

VDDSDMMC

GNDSDMMC

VDDSDMMC

GNDSDMMC

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

N13

–

VDDISC

GNDISC

power

VDDISC

GNDISC

–

ground

U15

M13

–

VDDFUSE

VDDPLLA

GNDPLLA

VDDAUDIOPLL

GNDDPLL

GNDAUDIOPLL

VDDAUDIOPLL

VDDOSC

power

VDDFUSE

VDDPLLA

GNDPLLA

VDDAUDIOPLL

GNDDPLL

GNDAUDIOPLL

CLK_AUDIO

XIN

power

P10

ground

power

ground

R10

T11

–

VDDOSC

–

XOUT

VDDOSC

–

VDDOSC

GNDOSC

VDDUTMII

VDDHSIC

GNDUTMII

HHSDPA

HHSDMA

HHSDPB

HHSDMB

HHSDPDATC

HHSDMSTRC

VDDUTMIC

GNDUTMIC

VBG

GNDOSC

VDDUTMII

VDDHSIC

GNDUTMII

VDDUTMII

VDDHSIC

VDDUTMIC

GNDUTMIC

VDDUTMIC

VDDBU

ground

power

U10

T10

U11

T11

T12

U12

power

–

ground

–

I/O

–

I/O

–

I/O

–

I/O

W10

–

I/O

–

I/O

–

power

ground

–

TST

VDDBU

NRST

VDDBU

JTAGSEL

WKUP

VDDBU

RXD

VDDBU

SHDN

...........continued

Primary

Alternate

PIO Peripheral

Signal

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Dir

(1)

Set

HiZ, ST)

D17

VDDBU

GNDBU

VDDBU

DDRM_VDDQ

–

PIOBU0

PIOBU1

PIOBU2

PIOBU3

PIOBU4

PIOBU5

PIOBU6

PIOBU7

VDDBU

GNDBU

XIN32

I/O

–

D12

power

ground

–

XOUT32

COMPP

COMPN

ODT

–

(2)

DDRM_VDD

A16, B16,

C16, D16,

E15, G17,

J17, L16

B10, A12,

D10, D11

power

DDRM_VDD

(2)

E16

DDRM_VDDL

power

DDRM_VDDL

–

(2)

F15, G15, A7, A13, A9, DDRM_VDDQ

H15, J15, A11, B6, C12

K15, L15

DDRM_VDDQ

–

...........continued

Primary

Alternate

PIO Peripheral

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Signal

Dir

(1)

Set

HiZ, ST)

A14, A19,

B14, B18,

C14, C18,

D14, D18,

E14, E18,

F14, F18,

G14, G18,

H14, H18,

N14, N17,

N18, P14,

P18, R14,

R18, T18

A17, B17,

B14, A8,

DDRM_VSS

ground

DDRM_VSS

–

C17, D15, C11, C14, D8

E14, F17,

H17, L17

E17

D13

DDRM_VSSDL

DDRM_VSSQ

ground

DDRM_VSSDL

DDRM_VSSQ

–

F16, G16,

H16, J16,

K16, K17

A10, A14,

B11, B12,

B13, C13

(3)

B15, B17,

B19, D15,

D17, D19,

F15, F17,

F19, H15,

H17, H19,

K15, K17,

K19, M15,

M17, M19,

P15, P17,

P19, T17,

T19

DDRM_VDD12

power

DDRM_VDD12

(3)

B11, B13,

D11, D13,

K13, K16

DDRM_VDD18

power

DDRM_VDD18

...........continued

Primary

Alternate

PIO Peripheral

Reset State

(Signal, Dir,

PU, PD,

361-ball

289-ball

196-ball

BGA

I/O

Power Rail

BGA rotatethispage90

BGA

Type

Signal

Dir

Signal

Dir

Func

Signal

Dir

(1)

Set

HiZ, ST)

(4)

A13, A15,

A16, A17,

A18, B10,

B12, B16,

C10, C11,

C12, C13,

A12, A13,

A14, A15,

B11, B12,

B13, B14,

B15, C10,

C11, C12,

–

C15, C16, C13, C14,

C17, D10, C15, D10,

D12, D16,

E12, E13,

E15, E16,

E17, E19,

D11, D12,

D13, D14,

E13, F9,

F10, F13,

E5, E6, E9, F14, G11,

F10, F11,

F12, F13,

F16, F5,

G13, G14,

H11, H13,

H14, J12,

F6, F7, F9, J13, J14,

G11, G12,

G13, G15,

G16, G17,

G19, G7,

G8, G9,

K12, K13,

K14, L13,

R12, T9

H11, H12,

H13, H16,

H7, H8, H9,

J12, J14,

J15, J16,

J17, J18,

J19, K10,

K11, K12,

K14, L12,

L13, L14,

L15, L16,

M10, M11,

M14, N11,

N13, N16,

N7, R11,

R12, R17,

T12, T9,

U10, U11,

U8, V4

SAMA5D2 SIP

Package and Ballout

Notes:ꢀ

1. Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt

Trigger

2. Refer to the DDR2-SDRAM data sheet for DDRM_VDDQ and DDRM_VDDL definitions. DDRM_VDDQ/

DDRM_VDDL = 1.8V ±0.1V.

3. DDRM_VDD18 stands for VDD1, DDRM_VDD12 stands for VDD2, refer to the LPDDR2-SDRAM data sheet

for VDD1 and VDD2 definitions.

4. These balls are not internally connected, they can be left unconnected, connected to any GND, VDD or to any

slowly varying signal to avoid any EMI related issues.

DS60001484D-page 38

Datasheet

SAMA5D2 SIP

Memory

The SAMA5D2 SIP is available with 128 Mbits, 512 Mbits or 1 Gbit of DDR2-SDRAM memory, and with 1 Gbit

or 2 Gbits of LPDDR2-SDRAM memory. For the features of these memories, see DDR2-SDRAM Features and

LPDDR2-SDRAM Features.

For power consumption, electrical characteristics and timings of these memories, refer to the data sheets referenced

below on the manufacturer’s website.

Table 7-1.ꢀMemory Data Sheet References

Memory Type

Density

Manufacturer Packaged PN

Data Sheet Reference Number

W9712G6KB

128 Mbit Winbond W9712G6KB25I

512 Mbit Winbond W9751G6KB25I

DDR2-SDRAM

W9751G6KB

1 Gbit

2 Gbit

Winbond W971GG6SB25I

W971GG6SB

apmemory AD210032F-I-AB

apmemory AD220032D-I-ED/PC/AB

lpddr2_datasheet_1gb

lpddr2_datasheet_2gb

LPDDR2-SDRAM

DS60001484D-page 39

Datasheet

SAMA5D2 SIP

Electrical Characteristics

8.1

Recommended Thermal Operating Conditions

Symbol

T_A

Parameter

Conditions

–

Min

-40

–

Max

+85

+125

Unit

°C

Ambient temperature

Junction temperature

T_J

–

°C

BGA196

BGA289

BGA361

BGA196

BGA289

BGA361

R_thJA

Junction-to-ambient thermal resistance

Allowable power dissipation

–

°C/W

–

T_A=70°C

T_A=85°C

–

1.3

P_D

–

1.0

8.2

Decoupling

100 nF (min) decoupling capacitors must be added on each power supply pin, as close as possible to the device.

8.3

Power Sequences

8.3.1

SAMA5D2 DDR2 SIP

DDRM_VDD, DDRM_VDDL and DDRM_VDDQ power rails must be connected to VDDIODDR (1.8V) on the PCB.

Refer to the sections “Power-up Considerations” and “Power-down Considerations” in the SAMA5D2 Series data

sheet, ref. no. DS60001476, available on www.microchip.com.

8.3.2

SAMA5D2 LPDDR2 SIP

The DDRM_VDD12 power rail must be connected to VDDIODDR (1.2V). The DDRM_VDD18 power rail must be

connected to a 1.8V power supply. For Backup with Self-refresh mode, these power supplies must be maintained.

Important:ꢀ The sections below supersede “Recommended Power-up Sequence”, “Recommended

Power-up Sequence”, “Power Supply Sequencing at Backup Mode Entry and Exit” in the SAMA5D2 Series

data sheet.

8.3.2.1 Power-up Considerations

At power-up, from a supply sequencing perspective, the SAMA5D2 LPDDR2 SIP power supply inputs are

categorized into two groups:

•

Group 1 (core group) contains VDDCORE, VDDUTMIC, VDDHSIC and VDDPLLA.

Group 2 (periphery group) contains all other power supply inputs except VDDFUSE.

The figure below shows the recommended power-up sequence. Note that:

•

VDDBU, when supplied from a battery, is an always-on supply input and is therefore not part of the power

supply sequencing. When no backup battery is present in the application, VDDBU is part of Group 2.

•

VDDFUSE is the only power supply that may be left unpowered during operation. This is possible if and

only if the application does not access the Customer Fuse Matrix in Write mode. It is good practice to turn

DS60001484D-page 40

Datasheet

SAMA5D2 SIP

Electrical Characteristics

on VDDFUSE only when the Customer Fuse Matrix is accessed in Write mode, and to turn off VDDFUSE

otherwise.

Figure 8-1.ꢀRecommended Power-up Sequence

Group 2

No specific order and no

specific timing required

among these channels except

DDRM_VDD12 and DDRM_VDD18

VDDBU

VDDANA

VDDOSC

VDDUTMII

VDDAUDIOPLL

VDDIOP0

VDDIOP1

VDDIOP2

VDDISC

VDDSDMMC

t₅

DDRM_VDD18

t₄

DDRM_VDD12, VDDIODDR

t₃

VDDFUSE

Group 1

t₁

VDDCORE

VDDPLLA

VDDHSIC

VDDUTMIC

t₂

NRST

t_RSTPU

time

Table 8-1.ꢀPower-up Timing Specification

Symbol Parameter

Conditions

Min

Max

Unit

Delay from the last Group 2 established⁽¹⁾supply to the

first Group 1 supply turn-on

t₁

Group 2 to Group 1 delay

–

Delay from the first Group 1 established supply to the

last Group 1 established supply

t₂

t₃

t₄

Group 1 delay

–

VDDFUSE to VDDBU delay Delay from VDDBU established to VDDFUSE turn-on

DDRM_VDD18 to

DDRM_VDD12 delay

Delay from the DDRM_VDD18 established to

DDRM_VDD12 turn-on

Delay from DDRM_VDD18 turn-on to DDRM_VDD12

established

t₅

LPDDR2 power-on delay

–

t_RSTPUReset delay at power-up

From the last established supply to NRST high

Note:ꢀ

1. An “established” supply refers to a power supply established at 90% of its final value.

DS60001484D-page 41

Datasheet

SAMA5D2 SIP

Electrical Characteristics

8.3.2.2 Power-down Considerations

The figure below shows the SAMA5D2 LPDDR2 SIP power-down sequence that starts by asserting the NRST line

to 0. Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order

except for DDRM_VDD12 and DDRM_VDD18. VDDBU may not be shut down if the application uses a backup

battery on this supply input. In applications where VDDFUSE is powered, it is mandatory to shut down VDDFUSE

prior to removing any other supply. VDDFUSE can be removed before or after asserting the NRST signal.

Figure 8-2.ꢀRecommended Power-down Sequence

No specific order and no

t_RSTPD

specific timing required

among the channels

except DDRM_VDD12

and DDRM_VDD18

t₃

NRST

VDDBU

VDDANA

VDDOSC

VDDUTMII

VDDAUDIOPLL

VDDIOP0

VDDIOP1

VDDIOP2

VDDISC

VDDSDMMC

DDRM_VDD12, VDDIODDR

DDRM_VDD18

VDDFUSE

t₂

t₁

VDDCORE

VDDPLLA

VDDHSIC

VDDUTMIC

time

Table 8-2.ꢀPower-down Timing Specification

Symbol Parameter

Conditions

From NRST low to the first supply turn-off

Min

Max

Unit

t_RSTPD

t₁

Reset delay at power-down

–

VDDFUSE delay at shut-down

From VDDFUSE < 1V to the first supply turn-off

DDRM_VDD12 to

DDRM_VDD18 delay

From DDRM_VDD12 zeroed to DDRM_VDD18

turn-off

t₂

t₃

LPDDR2 power-off delay

From NRST low to DDRM_VDD18 zeroed

–

2000

8.3.2.3 Backup Mode Entry (Shutdown)

The figure below shows the recommended power-down sequence to place the SAMA5D2 LPDDR2 SIP either in

Backup mode or in Backup mode with the LPDDR2 in self-refresh. The SHDN signal, an output of the Shutdown

Controller (SHDWC), signals the shutdown request to the power supply. This output is supplied by VDDBU that is

present in Backup mode. Placing the LPDDR2 memory in self-refresh while in Backup mode requires maintaining

VDDIODDR, DDRM_VDD18 and DDRM_VDD12 as well. One possible way to signal this additional need to the

power supply is to position one of the general-purpose I/Os supplied by VDDBU (PIOBUx) in a predefined state.

DS60001484D-page 42

Datasheet

SAMA5D2 SIP

Electrical Characteristics

Figure 8-3.ꢀRecommended Backup Mode Entry (Shutdown)

t_RSTPD

Shutdown Request

in SHDWC

SHDN

PIOBUx

NRST

t₂

VDDBU

PIOBUx signals to

No specific order and no

specific timing required

among the channels

except DDRM_VDD12

and DDRM_VDD18

maintain or shutdown

VDDANA

VDDIODDR

VDDOSC

VDDUTMII

VDDAUDIOPLL

VDDIOP0

VDDIOP1

VDDIOP2

VDDISC

VDDSDMMC

VDDFUSE

DDRM_VDD12, VDDIODDR

DDRM_VDD18

t₁

VDDCORE

VDDPLLA

VDDHSIC

VDDUTMIC

time

Table 8-3.ꢀShutdown Timing Specification

Symbol

Parameter

Conditions

Min

Max

Unit

t_RSTPD

Reset delay at power-down

From NRST low to the first supply turn-off

–

DDRM_VDD12 to

DDRM_VDD18 delay

From DDRM_VDD12 zeroed to DDRM_VDD18

turn-off

t₁

t₂

–

LPDDR2 power-off delay

From NRST low to DDRM_VDD18 zeroed

2000

8.3.2.4 Backup Mode Exit (Wake-up)

The figure below shows the recommended power-up sequence to wake up the SAMA5D2 LPDDR2 SIP from Backup

mode. Upon a wake-up event, the Shutdown Controller toggles its SHDN output back to VDDBU to request the

power supply to restart. Except for VDDIODDR, DDRM_VDD18 and DDRM_VDD12 which may already be present if

the LPDDR2 memory was placed in Self-refresh mode, this power-up sequence is the same one as presented in the

figure “Recommended Power-up Sequence”. In particular, the definitions of Group 1 and Group 2 are the same.

DS60001484D-page 43

Datasheet

SAMA5D2 SIP

Electrical Characteristics

Figure 8-4.ꢀRecommended Backup Mode Exit (Wake-Up)

SHDN

VDDBU

Group 2

VDDANA

VDDOSC

No specific order and no

specific timing required

among these channels

except DDRM_VDD12

and DDRM_VDD18

VDDUTMII

VDDAUDIOPLL

VDDIOP0

VDDIOP1

VDDIOP2

VDDISC

VDDSDMMC

VDDFUSE

t₄

DDRM_VDD18

t₃

DDRM_VDD12, VDDIODDR

Group 1

t₁

VDDCORE

VDDPLLA

VDDHSIC

VDDUTMIC

t₂

NRST

t_RSTPU

time

Table 8-4.ꢀWake-up Timing Specification

Symbol Parameter Conditions

Min

Max

Unit

Delay from the last Group 2 established⁽¹⁾supply to the

first Group 1 supply turn-on

t₁

t₂

t₃

t₄

Group 2 to Group 1 delay

–

Delay from the first Group 1 established supply to the

last Group 1 established supply

Group 1 delay

–

DDRM_VDD18 to

DDRM_VDD12 delay

Delay from the DDRM_VDD18 established to

DDRM_VDD12 turn-on

Delay from DDRM_VDD18 turn-on to DDRM_VDD12

established

LPDDR2 power-on delay

–

t_RSTPUReset delay at power-up

From the last established supply to NRST high

Note:ꢀ

1. An “established” supply refers to a power supply established at 90% of its final value.

DS60001484D-page 44

Datasheet

SAMA5D2 SIP

Mechanical Characteristics

9.1

361-ball TFBGA

361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]

Atmel Legacy Global Package Code CEP

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

361X

0.15 C

0.20 C

NOTE 1

10 11 12 13 14 15 16 17 18 19

(DATUM B)

(DATUM A)

0.15 C

TOP VIEW

0.15 C

SEATING

PLANE

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

SIDE VIEW

NOTE 1

361X Øb

0.15

A B

0.08

BOTTOM VIEW

Microchip Technology Drawing C04-21149-DYB Rev A Sheet 1 of 2

DS60001484D-page 45

Datasheet

SAMA5D2 SIP

Mechanical Characteristics

361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]

Atmel Legacy Global Package Code CEP

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Overall Length

Overall Pitch

Overall Width

Overall Pitch

Terminal Width

361

0.80 BSC

1.20

0.37

0.27

16.00 BSC

14.40 BSC

16.00 BSC

14.40 BSC

0.38

0.48

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-21149-DYB Rev A Sheet 2 of 2

DS60001484D-page 46

Datasheet

SAMA5D2 SIP

Mechanical Characteristics

361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]

Atmel Legacy Global Package Code CEP

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

9 10 11 12 13 14 15 16 17 18 19

ØX1

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

0.80 BSC

14.40

MAX

Contact Pitch

Contact Pad Spacing

Contact Pad Width (X20)

14.40

0.45

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-23149-DYB Rev A

DS60001484D-page 47

Datasheet

SAMA5D2 SIP

Mechanical Characteristics

9.2

289-ball TFBGA

Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located at http://

www.microchip.com/packaging.

Table 9-1.ꢀ289-ball TFBGA Package Characteristics

Moisture Sensitivity Level

Table 9-2.ꢀDevice and 289-ball TFBGA Package Weight

Device

Weight (mg)

390

ATSAMA5D27C-D5M (512 Mb)

ATSAMA5D28C-D1G (1 Gbit)

400

DS60001484D-page 48

Datasheet

SAMA5D2 SIP

Mechanical Characteristics

Table 9-3.ꢀPackage Reference

JEDEC Drawing Reference

J-STD-609 Classification

Table 9-4.ꢀ289-ball TFBGA Package Information

Ball Land

0.450 mm ±0.05

0.4 mm

Nominal Ball Diameter

Solder Mask Opening

Solder Mask Definition

Solder

0.350 mm ±0.05

SMD

OSP

9.3

196-ball TFBGA

For mechanical characteristics of the 196-ball TFBGA package, refer to the SAMA5D2 Series data sheet, ref. no.

DS60001476, available on www.microchip.com.

Note:ꢀ The weight of the SAMA5D2 SIP is not the same as the weight of SAMA5D2. The SIP weight is given below:

Table 9-5.ꢀDevice and 196-ball TFBGA Package Weight

Device

Weight (mg)

ATSAMA5D225C-D1M (128 Mb)

240

DS60001484D-page 49

Datasheet

SAMA5D2 SIP

Ordering Information

10.

Ordering Information

Table 10-1.ꢀOrdering Information

Operating

Ordering Code

MRL

Package

Carrier Type

Temperature

Range

ATSAMA5D225C-D1M-CU

ATSAMA5D225C-D1M-CUR

ATSAMA5D27C-D5M-CU

ATSAMA5D27C-D5M-CUR

ATSAMA5D27C-D1G-CU

ATSAMA5D27C-D1G-CUR

ATSAMA5D28C-D1G-CU

ATSAMA5D28C-D1G-CUR

ATSAMA5D27C-LD1G-CU

ATSAMA5D27C-LD1G-CUR

ATSAMA5D27C-LD2G-CU

ATSAMA5D27C-LD2G-CUR

ATSAMA5D28C-LD1G-CU

ATSAMA5D28C-LD1G-CUR

ATSAMA5D28C-LD2G-CU

ATSAMA5D28C-LD2G-CUR

Tray

Tape & Reel

Tray

BGA196

Tape & Reel

Tray

BGA289

Tape & Reel

Tray

Tape & Reel

Tray

-40°C to +85°C

Tape & Reel

Tray

Tape & Reel

Tray

BGA361

Tape & Reel

Tray

Tape & Reel

DS60001484D-page 50

Datasheet

SAMA5D2 SIP

Revision History

11.

Revision History

11.1

DS60001484D - 03/2021

Changes

Updated SAMA5D2 SIP Chip ID Registers.

11.2

11.3

DS60001484C - 01/2020

Changes

Reference Documents: updated memory references.

LPDDR2-SDRAM Features: updated burst, write, read latencies.

Electrical Characteristics: added 8.1 Recommended Thermal Operating Conditions.

DS60001484B - 11/2018

Changes

Added 1 Gbit and 2 Gbit LPDDR2 memory options. Added 361-ball TFBGA package option and mechanical

drawing.

Pinout: added PTC signals.

Added section Electrical Characteristics.

11.4

DS60001484A - 09/2017

Changes

First issue.

DS60001484D-page 51

Datasheet

SAMA5D2 SIP

The Microchip Website

Microchip provides online support via our website at www.microchip.com/. This website is used to make files and

information easily available to customers. Some of the content available includes:

•

Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online

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receive email notification whenever there are changes, updates, revisions or errata related to a specified product

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To register, go to www.microchip.com/pcn and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

•

Distributor or Representative

Local Sales Office

Embedded Solutions Engineer (ESE)

Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to

help customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: www.microchip.com/support

DS60001484D-page 52

Datasheet

SAMA5D2 SIP

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

ATSAMA5 D225 C - D1M - C U R

Architecture

Product Group

Mask Revision

Memory Type and Size

Package

Temperature Range

Carrier Type

Architecture:

ATSAMA5

D225

= Arm Cortex-A5 CPU

Product Group:

= 196-ball general-purpose

microprocessor family

D27

D28

D1M

D5M

D1G

LD1G

LD2G

= 289-ball or 361-ball general-

purpose microprocessor family

Memory Type and Size:

= 128-Mbit DDR2 SDRAM

= 512-Mbit DDR2 SDRAM

= 1-Gigabit DDR2 SDRAM

= 1-Gigabit LPDDR2 SDRAM

= 2-Gigabit LPDDR2 SDRAM

Mask Revision:

Package:

= BGA

Temperature Range:

Carrier Type:

= -40°C to +85°C (Industrial)

= Standard packaging (tray)

= Tape and Reel

Blank

Examples:

•

ATSAMA5D225C-D1M-CU = ARM Cortex-A5 general-purpose microprocessor, 128-Mbit DDR2 SDRAM, 196-

ball, Industrial temperature, BGA Package.

Note:ꢀ Tape and Reel identifier only appears in the catalog part number description. This identifier is used for

ordering purposes and is not printed on the device package

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today,

when used in the intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the operating

specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of

intellectual property.

DS60001484D-page 53

Datasheet

SAMA5D2 SIP

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code

protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection

features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital

Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you

may have a right to sue for relief under that Act.

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Information contained in this publication regarding device applications and the like is provided only for your

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use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless

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BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,

KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,

MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip

Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer,

Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,

HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,

ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,

Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky,

BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,

INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM,

MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,

PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial

Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-7802-7

DS60001484D-page 54

Datasheet

SAMA5D2 SIP

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

DS60001484D-page 55

Datasheet

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

www.microchip.com/support

Web Address:

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

China - Nanjing

Tel: 91-20-4121-0141

Japan - Osaka

Fax: 45-4485-2829

Finland - Espoo

Tel: 81-6-6152-7160

Japan - Tokyo

Tel: 358-9-4520-820

France - Paris

www.microchip.com

Atlanta

Tel: 81-3-6880- 3770

Korea - Daegu

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 82-53-744-4301

Korea - Seoul

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

Tel: 60-4-227-8870

Philippines - Manila

Tel: 63-2-634-9065

Singapore

Germany - Haan

Tel: 512-257-3370

Boston

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-72400

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Tel: 86-25-8473-2460

China - Qingdao

Tel: 86-532-8502-7355

China - Shanghai

Tel: 86-21-3326-8000

China - Shenyang

Tel: 86-24-2334-2829

China - Shenzhen

Tel: 86-755-8864-2200

China - Suzhou

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Tel: 972-9-744-7705

Italy - Milan

Tel: 86-186-6233-1526

China - Wuhan

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Novi, MI

Tel: 248-848-4000

Houston, TX

Tel: 86-27-5980-5300

China - Xian

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Tel: 281-894-5983

Indianapolis

Tel: 86-29-8833-7252

China - Xiamen

Noblesville, IN

Tel: 86-592-2388138

China - Zhuhai

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS60001484D-page 56

Datasheet

ATSAMA5D27C-D5M-CU [MICROCHIP]

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