ATSAMD21G16A-AFT [MICROCHIP]
Low-Power, 32-bit Cortex-M0 MCU with Advanced Analog and PWM;型号: | ATSAMD21G16A-AFT |
厂家: | MICROCHIP |
描述: | Low-Power, 32-bit Cortex-M0 MCU with Advanced Analog and PWM |
文件: | 总1148页 (文件大小:9869K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SAM D21/DA1 Family
Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog
and PWM
Features
•
•
•
Processor
– Arm® Cortex®-M0+ CPU running at up to 48 MHz
•
•
Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
Memories
– 4/2/1/0.5 KB Read-While-Write (RWWEE) Flash section (not available on 256 KB devices)
– 256/128/64/32/16 KB in-system self-programmable Flash
– 32/16/8/4 KB SRAM Memory
System
– Power-on Reset (POR) and Brown-out Detection (BOD)
– Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to
96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One Non-maskable Interrupt (NMI)
– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
•
•
– Idle and Standby Sleep modes
– SleepWalking peripherals
Peripherals
– 12-channel Direct Memory Access Controller (DMAC)
– 12-channel Event System
– Up to five 16-bit Timer/Counters (TC), configurable as either:
•
•
•
One 16-bit TC with two compare/capture channels
One 8-bit TC with two compare/capture channels
One 32-bit TC with two compare/capture channels, by using two TCs
– Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:
•
•
•
•
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error
– PWM Channels using TC and TCC peripherals:
•
•
•
Up to eight PWM channels on each 24-bit TCC
Up to two PWM channels on each 16-bit TCC
Up to two PWM channels on each 16-bit TC
– 32-bit Real Time Counter (RTC) with clock/calendar function
– Watchdog Timer (WDT)
– CRC-32 generator
DS40001882G-page 1
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
•
•
Embedded host and device function
Eight endpoints
– Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
•
•
•
•
USART with full-duplex and single-wire half-duplex configuration
I2C up to 3.4 MHz
SPI
LIN client
– One two-channel Inter-IC Sound (I2S) interface
– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
•
•
•
•
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
– 10-bit, 350 ksps Digital-to-Analog Converter (DAC)
– Up to four Analog Comparators (AC) with Window Compare function
– Peripheral Touch Controller (PTC)
•
Up to 256-Channel capacitive touch and proximity sensing
•
•
I/O
– Up to 52 programmable I/O pins
Qualification
– SAM D21 AEC-Q100 Grade 1 (-40°C to 125°C)
– SAM DA1 AEC-Q100 Grade 2 (-40C to 105C)
Drop-in compatible with SAM D20
Packages
•
•
– 64-pin TQFP, QFN, UFBGA
– 48-pin TQFP, QFN
– 45-pin WLCSP
– 35-pin WLCSP
– 32-pin TQFP, QFN
•
Operating Voltage
– SAM D21: 1.62V – 3.63V
– SAM DA1: 2.7V - 3.63V
DS40001882G-page 2
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Table of Contents
Features......................................................................................................................................................... 1
1. Description............................................................................................................................................ 13
2. Configuration Summary........................................................................................................................ 14
3. SAM D21 Ordering Information(1)..........................................................................................................16
3.1. SAM DA1 Ordering Information..................................................................................................17
4. Block Diagram.......................................................................................................................................18
5. Pinout....................................................................................................................................................19
5.1. SAM D21J and SAM DA1J.........................................................................................................19
5.2. SAM D21GxxA/B/D and SAM DA1GxxA/B................................................................................ 21
5.3. SAM D21GxxA........................................................................................................................... 22
5.4. SAM D21GxxL............................................................................................................................23
5.5. SAM D21ExxA/B/D and SAM DA1ExxA/B.................................................................................24
5.6. SAM D21ExxB/C/D.................................................................................................................... 25
5.7. SAM D21ExxL............................................................................................................................26
6. Signal Descriptions List.........................................................................................................................27
7. I/O Multiplexing and Considerations..................................................................................................... 29
7.1. Multiplexed Signals.................................................................................................................... 29
7.2. Other Functions..........................................................................................................................32
8. Power Supply and Start-Up Considerations..........................................................................................35
8.1. Power Domain Overview............................................................................................................35
8.2. Power Supply Considerations.................................................................................................... 35
8.3. Power-Up................................................................................................................................... 37
8.4. Power-On Reset and Brown-Out Detector.................................................................................37
9. Product Mapping...................................................................................................................................39
10. Memories.............................................................................................................................................. 41
10.1. Embedded Memories................................................................................................................. 41
10.2. Physical Memory Map................................................................................................................41
10.3. NVM Calibration and Auxiliary Space........................................................................................ 42
11. Processor And Architecture.................................................................................................................. 46
11.1. Cortex M0+ Processor............................................................................................................... 46
11.2. Nested Vector Interrupt Controller..............................................................................................47
11.3. Micro Trace Buffer......................................................................................................................49
11.4. High-Speed Bus System............................................................................................................ 49
11.5. AHB-APB Bridge........................................................................................................................ 51
11.6. Peripheral Access Controller (PAC)........................................................................................... 52
11.7. Register Access and Behavior................................................................................................... 65
12. Peripherals Configuration Summary..................................................................................................... 66
DS40001882G-page 3
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
13. DSU - Device Service Unit....................................................................................................................68
13.1. Overview.................................................................................................................................... 68
13.2. Features..................................................................................................................................... 68
13.3. Block Diagram............................................................................................................................68
13.4. Signal Description...................................................................................................................... 69
13.5. Product Dependencies...............................................................................................................69
13.6. Debug Operation........................................................................................................................70
13.7. Chip Erase..................................................................................................................................71
13.8. Programming..............................................................................................................................72
13.9. Intellectual Property Protection.................................................................................................. 72
13.10. Device Identification...................................................................................................................73
13.11. Functional Description................................................................................................................74
13.12. Register Summary..................................................................................................................... 79
13.13. Register Description...................................................................................................................80
14. Clock System...................................................................................................................................... 103
14.1. Clock Distribution..................................................................................................................... 103
14.2. Synchronous and Asynchronous Clocks..................................................................................104
14.3. Register Synchronization......................................................................................................... 104
14.4. Enabling a Peripheral...............................................................................................................108
14.5. Disabling a Peripheral.............................................................................................................. 108
14.6. On-demand, Clock Requests................................................................................................... 109
14.7. Power Consumption vs. Speed................................................................................................109
14.8. Clocks after Reset....................................................................................................................109
15. GCLK - Generic Clock Controller.........................................................................................................111
15.1. Overview...................................................................................................................................111
15.2. Features....................................................................................................................................111
15.3. Block Diagram...........................................................................................................................111
15.4. Signal Description.....................................................................................................................112
15.5. Product Dependencies............................................................................................................. 112
15.6. Functional Description..............................................................................................................113
15.7. Register Summary....................................................................................................................119
15.8. Register Description................................................................................................................. 119
16. PM – Power Manager......................................................................................................................... 130
16.1. Overview.................................................................................................................................. 130
16.2. Features................................................................................................................................... 130
16.3. Block Diagram..........................................................................................................................131
16.4. Signal Description.................................................................................................................... 131
16.5. Product Dependencies.............................................................................................................131
16.6. Functional Description..............................................................................................................133
16.7. Register Summary....................................................................................................................139
16.8. Register Description.................................................................................................................139
17. SYSCTRL – System Controller...........................................................................................................158
17.1. Overview.................................................................................................................................. 158
17.2. Features................................................................................................................................... 158
DS40001882G-page 4
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
17.3. Block Diagram..........................................................................................................................159
17.4. Signal Description.................................................................................................................... 159
17.5. Product Dependencies.............................................................................................................160
17.6. Functional Description..............................................................................................................161
17.7. Register Summary....................................................................................................................175
17.8. Register Description.................................................................................................................176
18. WDT – Watchdog Timer...................................................................................................................... 211
18.1. Overview...................................................................................................................................211
18.2. Features................................................................................................................................... 211
18.3. Block Diagram.......................................................................................................................... 211
18.4. Signal Description.................................................................................................................... 212
18.5. Product Dependencies.............................................................................................................212
18.6. Functional Description..............................................................................................................213
18.7. Register Summary....................................................................................................................218
18.8. Register Description.................................................................................................................218
19. RTC – Real-Time Counter...................................................................................................................227
19.1. Overview.................................................................................................................................. 227
19.2. Features................................................................................................................................... 227
19.3. Block Diagram..........................................................................................................................227
19.4. Signal Description.................................................................................................................... 228
19.5. Product Dependencies.............................................................................................................228
19.6. Functional Description..............................................................................................................230
19.7. Register Summary....................................................................................................................234
19.8. Register Description.................................................................................................................236
20. DMAC – Direct Memory Access Controller.........................................................................................268
20.1. Overview.................................................................................................................................. 268
20.2. Features................................................................................................................................... 268
20.3. Block Diagram..........................................................................................................................269
20.4. Signal Description.................................................................................................................... 270
20.5. Product Dependencies.............................................................................................................270
20.6. Functional Description..............................................................................................................271
20.7. Register Summary....................................................................................................................289
20.8. Register Description.................................................................................................................290
20.9. Register Summary - SRAM......................................................................................................317
20.10. Register Description - SRAM................................................................................................... 317
21. EIC – External Interrupt Controller......................................................................................................324
21.1. Overview.................................................................................................................................. 324
21.2. Features................................................................................................................................... 324
21.3. Block Diagram..........................................................................................................................324
21.4. Signal Description.................................................................................................................... 324
21.5. Product Dependencies.............................................................................................................325
21.6. Functional Description..............................................................................................................326
21.7. Register Summary....................................................................................................................330
21.8. Register Description.................................................................................................................330
DS40001882G-page 5
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
22. Nonvolatile Memory Controller (NVMCTRL).......................................................................................341
22.1. Overview.................................................................................................................................. 341
22.2. Features................................................................................................................................... 341
22.3. Block Diagram..........................................................................................................................341
22.4. Signal Description.................................................................................................................... 342
22.5. Product Dependencies.............................................................................................................342
22.6. Functional Description..............................................................................................................343
22.7. Register Summary....................................................................................................................350
22.8. Register Description.................................................................................................................350
23. PORT - I/O Pin Controller....................................................................................................................363
23.1. Overview.................................................................................................................................. 363
23.2. Features................................................................................................................................... 363
23.3. Block Diagram..........................................................................................................................364
23.4. Signal Description.................................................................................................................... 364
23.5. Product Dependencies.............................................................................................................364
23.6. Functional Description..............................................................................................................366
23.7. Register Summary....................................................................................................................371
23.8. Register Description.................................................................................................................372
24. EVSYS – Event System......................................................................................................................388
24.1. Overview.................................................................................................................................. 388
24.2. Features................................................................................................................................... 388
24.3. Block Diagram..........................................................................................................................388
24.4. Signal Description.................................................................................................................... 388
24.5. Product Dependencies.............................................................................................................389
24.6. Functional Description..............................................................................................................390
24.7. Register Summary....................................................................................................................394
24.8. Register Description.................................................................................................................395
25. SERCOM – Serial Communication Interface...................................................................................... 408
25.1. Overview.................................................................................................................................. 408
25.2. Features................................................................................................................................... 408
25.3. Block Diagram..........................................................................................................................409
25.4. Signal Description.................................................................................................................... 409
25.5. Product Dependencies.............................................................................................................409
25.6. Functional Description..............................................................................................................411
26. SERCOM USART............................................................................................................................... 416
26.1. Overview.................................................................................................................................. 416
26.2. USART Features......................................................................................................................416
26.3. Block Diagram..........................................................................................................................417
26.4. Signal Description.................................................................................................................... 417
26.5. Product Dependencies.............................................................................................................417
26.6. Functional Description..............................................................................................................419
26.7. Register Summary....................................................................................................................430
26.8. Register Description.................................................................................................................430
27. SERCOM SPI – SERCOM Serial Peripheral Interface....................................................................... 448
DS40001882G-page 6
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
27.1. Overview.................................................................................................................................. 448
27.2. Features................................................................................................................................... 448
27.3. Block Diagram..........................................................................................................................449
27.4. Signal Description.................................................................................................................... 449
27.5. Product Dependencies.............................................................................................................449
27.6. Functional Description..............................................................................................................451
27.7. Register Summary....................................................................................................................459
27.8. Register Description.................................................................................................................459
28. SERCOM I2C – Inter-Integrated Circuit...............................................................................................475
28.1. Overview.................................................................................................................................. 475
28.2. Features................................................................................................................................... 475
28.3. Block Diagram..........................................................................................................................476
28.4. Signal Description.................................................................................................................... 476
28.5. Product Dependencies.............................................................................................................476
28.6. Functional Description..............................................................................................................478
28.7. Register Summary - I2C Client.................................................................................................494
28.8. Register Description - I2C Client.............................................................................................. 494
28.9. Register Summary - I2C Host.................................................................................................. 507
28.10. Register Description - I2C Host................................................................................................507
29. I2S - Inter-IC Sound Controller............................................................................................................525
29.1. Overview.................................................................................................................................. 525
29.2. Features................................................................................................................................... 525
29.3. Block Diagram..........................................................................................................................526
29.4. Signal Description.................................................................................................................... 526
29.5. Product Dependencies.............................................................................................................527
29.6. Functional Description..............................................................................................................528
29.7. I2S Application Examples.........................................................................................................538
29.8. Register Summary....................................................................................................................541
29.9. Register Description.................................................................................................................542
30. TC – Timer/Counter.............................................................................................................................555
30.1. Overview.................................................................................................................................. 555
30.2. Features................................................................................................................................... 555
30.3. Block Diagram..........................................................................................................................556
30.4. Signal Description.................................................................................................................... 556
30.5. Product Dependencies.............................................................................................................557
30.6. Functional Description..............................................................................................................558
30.7. Register Summary for 8-bit Registers...................................................................................... 570
30.8. Register Description for 8-bit Registers....................................................................................570
30.9. Register Summary for 16-bit Registers.................................................................................... 586
30.10. Register Description for 16-bit Registers................................................................................. 586
30.11. Register Summary for 32-bit Registers.................................................................................... 601
30.12. Register Description for 32-bit Registers................................................................................. 601
31. TCC – Timer/Counter for Control Applications....................................................................................616
31.1. Overview.................................................................................................................................. 616
31.2. Features................................................................................................................................... 616
DS40001882G-page 7
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
31.3. Block Diagram..........................................................................................................................617
31.4. Signal Description.................................................................................................................... 617
31.5. Product Dependencies.............................................................................................................618
31.6. Functional Description..............................................................................................................619
31.7. Register Summary....................................................................................................................650
31.8. Register Description.................................................................................................................652
32. USB – Universal Serial Bus................................................................................................................ 691
32.1. Overview.................................................................................................................................. 691
32.2. Features................................................................................................................................... 691
32.3. USB Block Diagram..................................................................................................................692
32.4. Signal Description.................................................................................................................... 692
32.5. Product Dependencies.............................................................................................................692
32.6. Functional Description..............................................................................................................694
32.7. Communication Device Host Register Summary..................................................................... 710
32.8. Communication Device Host Register Description...................................................................710
32.9. Device Registers - Common -Register Summary.................................................................... 717
32.10. Device Registers - Common.................................................................................................... 717
32.11. Device Endpoint Register Summary........................................................................................ 730
32.12. Device Endpoint Register Description......................................................................................730
32.13. Endpoint Descriptor Structure..................................................................................................739
32.14. Device Endpoint RAM Register Summary............................................................................... 740
32.15. Device Endpoint RAM Register Description.............................................................................740
32.16. Host Registers - Common - Register Summary.......................................................................746
32.17. Host Registers - Common - Register Description.................................................................... 746
32.18. Host Registers - Pipe - Register Summary.............................................................................. 760
32.19. Host Registers - Pipe - Register Description............................................................................760
32.20. Pipe Descriptor Structure.........................................................................................................771
32.21. Host Registers - Pipe RAM - Register Summary..................................................................... 772
32.22. Host Registers - Pipe RAM - Register Description...................................................................772
33. ADC – Analog-to-Digital Converter..................................................................................................... 780
33.1. Overview.................................................................................................................................. 780
33.2. Features................................................................................................................................... 780
33.3. Block Diagram..........................................................................................................................781
33.4. Signal Description.................................................................................................................... 781
33.5. Product Dependencies.............................................................................................................781
33.6. Functional Description..............................................................................................................783
33.7. Register Summary....................................................................................................................792
33.8. Register Description.................................................................................................................792
34. AC – Analog Comparators.................................................................................................................. 816
34.1. Overview.................................................................................................................................. 816
34.2. Features................................................................................................................................... 816
34.3. Block Diagram..........................................................................................................................817
34.4. Signal Description.................................................................................................................... 818
34.5. Product Dependencies.............................................................................................................818
34.6. Functional Description..............................................................................................................819
DS40001882G-page 8
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
34.7. Register Summary....................................................................................................................828
34.8. Register Description.................................................................................................................828
35. DAC – Digital-to-Analog Converter..................................................................................................... 843
35.1. Overview.................................................................................................................................. 843
35.2. Features................................................................................................................................... 843
35.3. Block Diagram..........................................................................................................................843
35.4. Signal Description.................................................................................................................... 843
35.5. Product Dependencies.............................................................................................................843
35.6. Functional Description..............................................................................................................845
35.7. Register Summary....................................................................................................................849
35.8. Register Description.................................................................................................................849
36. Peripheral Touch Controller (PTC)......................................................................................................859
36.1. Overview.................................................................................................................................. 859
36.2. Features................................................................................................................................... 859
36.3. Block Diagram..........................................................................................................................860
36.4. Signal Description.................................................................................................................... 861
36.5. System Dependencies............................................................................................................. 861
36.6. Functional Description..............................................................................................................862
37. Electrical Characteristics at 85℃........................................................................................................ 863
37.1. Disclaimer.................................................................................................................................863
37.2. Thermal Considerations........................................................................................................... 863
37.3. Absolute Maximum Ratings......................................................................................................864
37.4. General Operating Ratings.......................................................................................................864
37.5. Supply Characteristics..............................................................................................................865
37.6. Maximum Clock Frequencies...................................................................................................865
37.7. Power Consumption.................................................................................................................867
37.8. Peripheral Power Consumption................................................................................................871
37.9. I/O Pin Characteristics..............................................................................................................874
37.10. Injection Current.......................................................................................................................876
37.11. Analog Characteristics............................................................................................................. 877
37.12. NVM Characteristics................................................................................................................ 890
37.13. Oscillators Characteristics........................................................................................................891
37.14. PTC Typical Characteristics.....................................................................................................898
37.15. USB Characteristics.................................................................................................................906
37.16. Timing Characteristics..............................................................................................................907
38. Electrical Characteristics at 105°C......................................................................................................916
38.1. Disclaimer.................................................................................................................................916
38.2. Absolute Maximum Ratings......................................................................................................916
38.3. General Operating Ratings.......................................................................................................916
38.4. Maximum Clock Frequencies...................................................................................................917
38.5. Power Consumption.................................................................................................................918
38.6. Analog Characteristics............................................................................................................. 921
38.7. NVM Characteristics.................................................................................................................928
38.8. Oscillators Characteristics........................................................................................................929
38.9. PTC Characteristics at 105°C.................................................................................................. 934
DS40001882G-page 9
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
38.10. USB Characteristics.................................................................................................................935
39. Electrical Characteristics at 125°C......................................................................................................936
39.1. Disclaimer.................................................................................................................................936
39.2. Absolute Maximum Ratings......................................................................................................936
39.3. General Operating Ratings.......................................................................................................936
39.4. Maximum Clock Frequencies...................................................................................................937
39.5. Power Consumption.................................................................................................................940
39.6. Analog Characteristics............................................................................................................. 943
39.7. NVM Characteristics.................................................................................................................954
39.8. Oscillators Characteristics........................................................................................................955
40. AEC-Q100 125°C Specifications.........................................................................................................965
40.1. Disclaimer.................................................................................................................................965
40.2. Thermal Considerations........................................................................................................... 965
40.3. Absolute Maximum Ratings......................................................................................................965
40.4. General Operating Ratings.......................................................................................................966
40.5. Supply Characteristics..............................................................................................................966
40.6. Maximum Clock Frequencies...................................................................................................967
40.7. Power Consumption.................................................................................................................970
40.8. I/O Pin Characteristics..............................................................................................................974
40.9. Analog Characteristics............................................................................................................. 977
40.10. NVM Characteristics................................................................................................................ 988
40.11. Oscillator Characteristics..........................................................................................................989
40.12. PTC Characteristics................................................................................................................. 997
41. SAM DA1 Electrical Characteristics..................................................................................................1000
41.1. Disclaimer...............................................................................................................................1000
41.2. Thermal Considerations......................................................................................................... 1000
41.3. Absolute Maximum Ratings....................................................................................................1000
41.4. Supply Characteristics............................................................................................................1001
41.5. Maximum Clock Frequencies.................................................................................................1002
41.6. Power Consumption...............................................................................................................1003
41.7. Peripheral Power Consumption..............................................................................................1006
41.8. I/O Pin Characteristics............................................................................................................1009
41.9. Injection Current.....................................................................................................................1012
41.10. Analog Characteristics........................................................................................................... 1013
41.11. NVM Characteristics...............................................................................................................1022
41.12. Oscillators Characteristics......................................................................................................1022
41.13. PTC Typical Characteristics...................................................................................................1032
41.14. USB Characteristics...............................................................................................................1040
41.15. Timing Characteristics............................................................................................................1041
42. Appendix A........................................................................................................................................1049
42.1. SIL 2 Enabled Functional Safety Devices.............................................................................. 1049
43. Appendix B........................................................................................................................................1050
43.1. ISELED FULL License Enabled Functional Devices..............................................................1050
43.2. Ordering Information.............................................................................................................. 1050
DS40001882G-page 10
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
44. Packaging Information...................................................................................................................... 1051
44.1. Package Drawings................................................................................................................. 1051
44.2. Soldering Profile..................................................................................................................... 1107
44.3. Package Markings..................................................................................................................1107
45. Schematic Checklist.......................................................................................................................... 1108
45.1. Introduction.............................................................................................................................1108
45.2. Power Supply......................................................................................................................... 1108
45.3. External Analog Reference Connections................................................................................1109
45.4. External Reset Circuit............................................................................................................. 1110
45.5. Clocks and Crystal Oscillators................................................................................................ 1112
45.6. Unused or Unconnected Pins................................................................................................. 1114
45.7. Programming and Debug Ports.............................................................................................. 1114
45.8. USB Interface..........................................................................................................................1117
46. Conventions.......................................................................................................................................1119
46.1. Numerical Notation................................................................................................................. 1119
46.2. Memory Size and Type........................................................................................................... 1119
46.3. Frequency and Time...............................................................................................................1119
46.4. Registers and Bits.................................................................................................................. 1120
47. Acronyms and Abbreviations.............................................................................................................1121
48. Data Sheet Revision History..............................................................................................................1124
48.1. Revision G - April 2021...........................................................................................................1124
48.2. Revision F - March 2020........................................................................................................ 1128
48.3. Revision E - January 2020..................................................................................................... 1129
48.4. Rev D - 9/2018....................................................................................................................... 1131
48.5. Rev. C – 06/2018....................................................................................................................1131
48.6. Rev. B – 04/2018.................................................................................................................... 1132
48.7. Rev. A – 01/2017.................................................................................................................... 1132
48.8. Rev. O – 12/2016....................................................................................................................1133
48.9. Rev. N – 10/2016....................................................................................................................1133
48.10. Rev. M – 09/2016................................................................................................................... 1133
48.11. Rev. L – 09/2016.....................................................................................................................1134
48.12. Rev. K – 09/2016....................................................................................................................1134
48.13. Rev. J – 07/2016.................................................................................................................... 1135
48.14. Rev. I – 03/2016..................................................................................................................... 1135
48.15. Rev. H – 01/2016....................................................................................................................1136
48.16. Rev. G – 09/2015................................................................................................................... 1137
48.17. Rev. F – 07/2015....................................................................................................................1137
48.18. Rev. E – 02/2015....................................................................................................................1138
48.19. Rev. D – 09/2014....................................................................................................................1140
48.20. Rev. C – 07/2014....................................................................................................................1140
48.21. Rev. B – 07/2014....................................................................................................................1140
48.22. Rev. A - 02/2014.....................................................................................................................1144
The Microchip Web Site............................................................................................................................1145
DS40001882G-page 11
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Customer Change Notification Service.....................................................................................................1145
Customer Support.................................................................................................................................... 1145
Product Identification System...................................................................................................................1146
Microchip Devices Code Protection Feature............................................................................................ 1146
Legal Notice..............................................................................................................................................1147
Trademarks...............................................................................................................................................1147
Quality Management System Certified by DNV........................................................................................1147
Worldwide Sales and Service...................................................................................................................1148
DS40001882G-page 12
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Description
1.
Description
®
®
The SAM D21/DA1 is a series of low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor, and
ranging from 32-pins to 64-pins with up to 256 KB Flash and 32 KB of SRAM. The SAM D21/DA1 operates at a
maximum frequency of 48 MHz and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive migration
with identical peripheral modules, hex compatible code, identical linear address map, and pin compatible migration
paths between all devices in the product series. All devices include intelligent and flexible peripherals, Event System
for inter-peripheral signaling, and support for capacitive touch button, slider, and wheel user interfaces.
The SAM D21/DA1 provides the following features: In-system programmable Flash, 12-channel Direct Memory
Access Controller (DMAC), 12-channel Event System, programmable Interrupt Controller, up to 52 programmable
I/O pins, 32-bit Real-Time Clock and Calendar (RTC), up to five 16-bit Timer/Counters (TC) and up to four 24-bit
Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation,
accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs
can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters have
extended functions optimized for motor, lighting, and other control applications. The series provide one full-speed
USB 2.0 embedded host and device interface; up to six Serial Communication Modules (SERCOM) that each can
be configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN client; two-channel
I2S interface; up to twenty-channel 350 ksps 12-bit ADC with programmable gain and optional oversampling and
decimation supporting up to 16-bit resolution, one 10-bit 350 ksps DAC, up to four analog comparators with Window
mode, Peripheral Touch Controller (PTG) supporting up to 256 buttons, sliders, wheels, and proximity sensing;
programmable Watchdog Timer (WDT), brown-out detector and power-on Reset and two-pin Serial Wire Debug
(SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for
the system clock. Different clock domains can be independently configured to run at different frequencies, enabling
power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency
while reducing power consumption.
The SAM D21/DA1 have two software-selectable sleep modes, Idle and Stand-by. In Idle mode, the CPU is stopped
while all other functions can be kept running. In Stand-by mode, all clocks and functions are stopped, expect those
selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up
from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g., when
a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events,
allowing peripherals to receive, react to and send events even in Stand-by mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can
be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any
communication interface to download and upgrade the application program in the Flash memory.
The SAM D21/DA1 microcontrollers are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
DS40001882G-page 13
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Configuration Summary
2.
Configuration Summary
Table 2-1.ꢀSAM D21 E/G/J and SAM D21 EL/GL Product Family Features
Oscillators
Peripherals
Analog
Device
ATSAMD21E15A
ATSAMD21E16A
ATSAMD21E17A
ATSAMD21E18A
ATSAMD21E15B
ATSAMD21E16B
ATSAMD21E15C
ATSAMD21E16C
ATSAMD21G15A
ATSAMD21G16A
32
64
4
8
OSC32K,
OSCULP32K,
OSC8M,
128
256
32
16
32
4
TQFP,
QFN
32
3
12
Y
4
8/4/2
26
10
60/6
DFLL48M,
FDPLL96M
64
8
32
4
35
WLCSP
64
8
3-2
Y
12
16
32
4
64
8
OSC32K,
OSCULP32K,
OSC8M,
ATSAMD21G17A
(1)
128
16
XOSC32K,
XOSC,
Y
Y
2
3
12
Y
TQFP,
QFN
48
38
14
120/10
DFLL48M,
FDPLL96M
ATSAMD21G18A
( 1)
256
32
ATSAMD21G15B
ATSAMD21G16B
ATSAMD21J15A
ATSAMD21J16A
ATSAMD21J17A
ATSAMD21J18A
ATSAMD21J15B
32
64
4
8
Y
6
8/4/2
32
4
64
8
TQFP,
QFN
128
256
32
16
32
4
OSC32K,
OSCULP32K,
OSC8M,
64
5-2
52
20
256/16
TQFP,
QFN,
3
DFLL48M,
FDPLL96M
64
8
ATSAMD21J16B
UFBGA
12
Y
Y
12
16
ATSAMD21E15L
ATSAMD21E16L
ATSAMD21G16L
32
64
4
8
32
32
48
TQFP,
QFN
N
Y
Y
4
6
3-2
5-2
6/4/2
8/4/2
26
38
14
18
XOSC
N
Y
4
2
N
64
8
QFN
128
16
OSC32K,
OSCULP32K,
OSC8M,
TQFP,
QFN
XOSC32K,
XOSC
ATSAMD21E17D
ATSAMD21G17D
32
48
4
6
3-2
3-2
4
4
6/4/2/6
8/4/2/8
26
38
10
14
30/6
WLCSP
DFLL48M,
128
16
OSC32K,
OSCULP32K,
OSC8M,
XOSC32K,
XOSC,
QFN,
Y
12
Y
Y
12
16
2
Y
120/10
TQFP
DFLL48M,
FDPLL96M
DS40001882G-page 14
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Configuration Summary
...........continued
Oscillators
Peripherals
Analog
Device
128
128
128
16
16
16
OSC32K,
OSCULP32K,
OSC8M,
QFN,
XOSC32K,
XOSC,
TQFP
ATSAMD21J17D
ATSAMD21E17L
ATSAMD21G17L
64
32
48
Y
N
N
6
4
6
5-2
3-2
5-2
4
4
4
8/4/2/8
6/4/2/6
8/4/2/8
Y
N
N
12
12
12
Y
Y
Y
Y
Y
Y
12
12
12
16
16
16
52
26
38
20
14
18
2
4
4
Y
Y
Y
256/16
UFBGA
DFLL48M,
FDPLL96M
OSC32K,
OSCULP32K,
OSC8M,
QFN,
XOSC
N
TQFP
DFLL48M,
FDPLL96M
OSC32K,
OSCULP32K,
OSC8M,
QFN
XOSC
N
DFLL48M,
FDPLL96M
Note:ꢀ
1. This part number is also available in a 45-Ball WLCSP package with a total of five TC instances and 15 ADC
Channels.
Table 2-2.ꢀSAM DA1 E/G/J Product Family Features
Device
ATSAMDA1E14B 16
4
ATSAMDA1E15B 32
ATSAMDA1E16B 64
ATSAMDA1G14B 16
ATSAMDA1G15B 32
ATSAMDA1G16B 64
32
48
64
4
6/4/2
26 10
12 16 38 14
52 20
60/6
8
4
8
4
8
OSC32K,
TQFP, QFN
3-2
OSCULP32K,
OSC8M,
DFLL48M,
FDPLL96M
XOSC32K, XOSC
1
3
1
12
Y
Y
2
1
120/10
256/16
6
8/4/2
ATSAMDA1J14B
ATSAMDA1J15B
ATSAMDA1J16B
16
32
64
TQFP
5-2
DS40001882G-page 15
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM D21 Ordering Information(1)
3.
SAM D21 Ordering Information(1)
ATSAMD 21 E 15 A
- M U T
Product Family
SAMD = General Purpose Microcontroller
Package Carrier
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
Pin Count
U = -40 - 85°C Matte Sn Plating
N = -40 - 105°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Z = -40 - 125°C Matte Sn Plating
E = 32 Pins (35 Pins for WLCSP)
G = 48 Pins (45 Pins for WLCSP)
J = 64 Pins
P(aAcECk-aQ1g0e0 QTuaylipfieed)
Flash Memory Density
18 = 256 KB
17 = 128 KB
16 = 64 KB
15 = 32 KB
A = TQFP(4)
M = QFN(4)
(2,3)
U = WLCSP
C = UFBGA
Device Variant
A = Default Variant
B = Added RWWEE support for 32 KB and 64 KB memory options
C = Silicon revision F for WLCSP45 package option
L = Pinout optimized for Analog and PWM
D = Silicon Revision G with RWWEE Support in 128KB memory options
Notes:ꢀ
1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary.
2. WLCSP package is available in -40C to 85C operating temperature range.
3. WLCSP parts are programmed with a specific SPI/I2C bootloader. Refer to "Application Note AT09002" for
additional information. Contact Microchip sales office for additional information on availability.
4. The AEC-Q100 grade 1 qualified version is only offered in the TQFP and QFN packages. The QFN will have
wettable flanks, and both packages will be assembled with gold bond wires.
DS40001882G-page 16
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM D21 Ordering Information(1)
3.1
SAM DA1 Ordering Information
Figure 3-1.ꢀSAM DA1 Ordering Information
SAM D A1 E 14 A
-
A B T
Product Family
Package Carrier
SAM D = Baseline Cortex-M0+ MCU
T = Tape and Reel
Product Series
A1 = Automotive basic feature set + DMA,
Adv Timers, USB, I2S, PTC
Package Grade
O
O
B = -40 C - 105 C Matte Sn Plating (only DA1)
Pin Count
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
A = TQFP
Flash Memory Density
16 = 64KB
15 = 32KB
14 = 16KB
M = QFN Wettable Flanks
Device Variant
A = Silicon revision E (Initial revision)
B = Silicon revision F
Note:ꢀ
1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary.
DS40001882G-page 17
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Block Diagram
4.
Block Diagram
IOBUS
256/128/64/32KB
NVM
32/16/8/4KB
RAM
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SWCLK
SERIAL
WIRE
SWDIO
NVM
CONTROLLER
SRAM
CONTROLLER
Cache
DEVICE
SERVICE
UNIT
M
M
S
S
M
DMA
HIGH-SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
DP
USB FS
DEVICE
S
S
S
DM
MINI-HOST
SOF 1KHZ
AHB-APB
BRIDGE B
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
DMA
SYSTEM CONTROLLER
PAD0
PAD1
6 x SERCOM
VREF
OSCULP32K
OSC32K
PAD2
PAD3
BOD33
XOSC32K
XOSC
DMA
XIN32
XOUT32
WO0
WO1
OSC8M
5 x TIMER / COUNTER
DFLL48M
FDPLL96M
XIN
XOUT
WO0
WO1
DMA
4x TIMER / COUNTER
FOR CONTROL
(2)
WOn
POWER MANAGER
CLOCK
DMA
AIN[19..0]
VREFA
CONTROLLER
20-CHANNEL
12-bit ADC 350KSPS
RESET
SLEEP
VREFB
RESET
CONTROLLER
CONTROLLER
CMP[1..0]
AIN[3..0]
GENERIC CLOCK
CONTROLLER
Up to 4 ANALOG
COMPARATORS
GCLK_IO[7..0]
REAL TIME
COUNTER
DMA
VOUT
10-bit DAC
WATCHDOG
TIMER
VREFA
EXTINT[15..0]
NMI
EXTERNAL INTERRUPT
CONTROLLER
X[15..0]
Y[15..0]
PERIPHERAL
TOUCH
CONTROLLER
DMA
MCK[1..0]
SCK[1..0]
SD[1..0]
FS[1..0]
INTER-IC
SOUND
CONTROLLER
1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC
signals. Refer to the Configuration Summary for details.
2. The TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer
to the TCC Configuration for details.
Related Links
2. Configuration Summary
7.2.5 TCC Configurations
DS40001882G-page 18
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.
Pinout
5.1
SAM D21J and SAM DA1J
5.1.1
QFN64 / TQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDIO
GND
PA00
PA01
PA02
PA03
PB04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
DS40001882G-page 19
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.1.2
UFBGA64
DS40001882G-page 20
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.2
SAM D21GxxA/B/D and SAM DA1GxxA/B
5.2.1
QFN48 / TQFP48
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
1
2
3
4
5
6
7
8
9
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
10
11
12
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
DS40001882G-page 21
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.3
SAM D21GxxA
5.3.1
WLCSP45
DS40001882G-page 22
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.4
SAM D21GxxL
5.4.1
QFN48
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
PA02
PA03
PB04
1
2
3
4
5
6
7
8
9
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PB05
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
10
11
12
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
DS40001882G-page 23
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.5
SAM D21ExxA/B/D and SAM DA1ExxA/B
5.5.1
QFN32 / TQFP32
24
23
22
21
20
19
18
17
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
PA25
1
2
3
4
5
6
7
8
PA24
PA23
PA22
PA19
PA18
PA17
PA16
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
DS40001882G-page 24
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.6
SAM D21ExxB/C/D
5.6.1
WLCSP35
A B C D E F
1
2
3
4
5
6
DS40001882G-page 25
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Pinout
5.7
SAM D21ExxL
5.7.1
QFN32 / TQFP32
24
23
22
21
20
19
18
17
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
PA02
PA03
PB04
PB05
PA04
PA05
PA06
PA07
1
2
3
4
5
6
7
8
DIGITAL PIN
ANALOG PIN
OSCILLATOR PIN
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
DS40001882G-page 26
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Signal Descriptions List
6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Signal Name Function
Type
Active Level
Analog Comparators - AC
AIN[3:0]
CMP[:0]
AC Analog Inputs
Analog
Digital
AC Comparator Outputs
Analog Digital Converter - ADC
AIN[19:0]
VREFA
VREFB
ADC Analog Inputs
Analog
Analog
Analog
ADC Voltage External Reference A
ADC Voltage External Reference B
Digital Analog Converter - DAC
VOUT
DAC Voltage output
DAC Voltage External Reference
Analog
Analog
VREFA
External Interrupt Controller
EXTINT[15:0] External Interrupts
Input
Input
NMI
External Non-Maskable Interrupt
Generic Clock Generator - GCLK
GCLK_IO[7:0] Generic Clock (source clock or generic clock generator output)
Inter-IC Sound Controller - I2S
I/O
MCK[1:0]
SCK[1:0]
FS[1:0]
Host Clock
I/O
I/O
I/O
I/O
Serial Clock
I2S Word Select or TDM Frame Sync
Serial Data Input or Output
SD[1:0]
Power Manager - PM
RESET Reset
Serial Communication Interface - SERCOMx
PAD[3:0] SERCOM I/O Pads
System Control - SYSCTRL
Input
I/O
Low
XIN
Crystal Input
Analog/ Digital
Analog/ Digital
Analog
XIN32
XOUT
XOUT32
32kHz Crystal Input
Crystal Output
32kHz Crystal Output
Analog
Timer Counter - TCx
WO[1:0]
Waveform/PWM Outputs/ Capture Inputs
Output
Output
Timer Counter - TCCx
WO[7:0]
Waveform/PWM Outputs
DS40001882G-page 27
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Signal Descriptions List
...........continued
Signal Name Function
Type
Active Level
Peripheral Touch Controller - PTC
X[15:0]
Y[15:0]
PTC Input
PTC Input
Analog
Analog
General Purpose I/O - PORT
PA25 - PA00
PA28 - PA27
PA31 - PA30
PB17 - PB00
PB23 - PB22
PB31 - PB30
Parallel I/O Controller I/O Port A
I/O
I/O
I/O
I/O
I/O
I/O
Parallel I/O Controller I/O Port A
Parallel I/O Controller I/O Port A
Parallel I/O Controller I/O Port B
Parallel I/O Controller I/O Port B
Parallel I/O Controller I/O Port B
Universal Serial Bus - USB
DP
DP for USB
I/O
I/O
I/O
DM
DM for USB
SOF 1kHz
USB Start of Frame
DS40001882G-page 28
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
7.
I/O Multiplexing and Considerations
7.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of
the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer
Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT
must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing
Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1.ꢀ PORT Function Multiplexing for SAM D21 A/B/C/D Variant Devices and SAM DA1 A/B Variant Devices
(1)
(2)(3)
Pin
I/O Pin
Supply
A
B
C
D
E
F
G
H
(2)(3)
(4)
TC
SAMD2xE
SAMD2xG
SAMD2xJ
EIC
REF
ADC
AC
PTC
DAC
SERCOM
SERCOM-ALT
TCC
COM
AC/
/TCC
GCLK
1
2
3
1
2
3
1
2
3
PA00
PA01
PA02
VDDANA
VDDANA
VDDANA
EXTINT[0]
EXTINT[1]
EXTINT[2]
SERCOM1/
PAD[0]
TCC2/WO[0]
SERCOM1/
PAD[1]
TCC2/WO[1]
AIN[0]
AIN[1]
Y[0]
Y[1]
VOUT
TCC3/
WO[0]
4
4
4
PA03
VDDANA
EXTINT[3]
ADC/VREFA
DAC/VREFA
TCC3/
WO[1]
5
6
PB04
PB05
PB06
PB07
PB08
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
EXTINT[8]
AIN[12]
AIN[13]
AIN[14]
AIN[15]
AIN[2]
Y[10]
Y[11]
Y[12]
Y[13]
Y[14]
9
10
11
7
8
SERCOM4/
PAD[0]
TC4/WO[0]
TC4/WO[1]
TCC3/
WO[6]
12
13
14
15
16
PB09
PA04
PA05
PA06
PA07
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
EXTINT[9]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
AIN[3]
AIN[4]
AIN[5]
AIN[6]
AIN[7]
Y[15]
Y[2]
Y[3]
Y[4]
Y[5]
SERCOM4/
PAD[1]
TCC3/
WO[7]
5
6
7
8
9
ADC/VREFB
AIN[0]
AIN[1]
AIN[2]
AIN[3]
SERCOM0/
PAD[0]
TCC0/WO[0]
TCC0/WO[1]
TCC1/WO[0]
TCC1/WO[1]
TCC3/
WO[2]
10
11
12
SERCOM0/
PAD[1]
TCC3/
WO[3]
SERCOM0/
PAD[2]
TCC3/
WO[4]
SERCOM0/
PAD[3]
TCC3/
WO[5]
I2S/SD[0]
I2S/SD[1]
11
12
13
14
13
14
15
16
19
20
17
18
19
20
23
24
25
26
27
PA08
PA09
PA10
PA11
PB10
PB11
PB12
PB13
PB14
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
NMI
AIN[16]
AIN[17]
AIN[18]
AIN[19]
X[0]
X[1]
X[2]
X[3]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC0/WO[1]
TCC1/WO[0]
TCC1/WO[1]
TC5/WO[0]
TC5/WO[1]
TC4/WO[0]
TC4/WO[1]
TC5/WO[0]
TCC1/
WO[2]
EXTINT[9]
EXTINT[10]
EXTINT[11]
EXTINT[10]
EXTINT[11]
EXTINT[12]
EXTINT[13]
EXTINT[14]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC1/
WO[3]
I2S/
MCK[0]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC0/
WO[2]
I2S/
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[6]
GCLK_IO[7]
GCLK_IO[0]
SCK[0]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC0/
WO[3]
I2S/FS[0]
SERCOM4/
PAD[2]
TCC0/
WO[4]
I2S/
MCK[1]
SERCOM4/
PAD[3]
TCC0/
WO[5]
I2S/
SCK[1]
X[12]
X[13]
X[14]
SERCOM4/
PAD[0]
TCC0/
WO[6]
I2S/FS[1]
SERCOM4/
PAD[1]
TCC0/
WO[7]
SERCOM4/
PAD[2]
DS40001882G-page 29
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
...........continued
SAMD2xE
(1)
(2)(3)
Pin
I/O Pin
Supply
A
B
C
D
E
F
G
H
(2)(3)
(4)
TC
SAMD2xG
SAMD2xJ
EIC
REF
ADC
AC
PTC
DAC
SERCOM
SERCOM-ALT
TCC
COM
AC/
/TCC
GCLK
28
29
30
31
32
35
36
37
38
39
40
41
42
43
44
45
46
49
PB15
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PB16
PB17
PA20
PA21
PA22
PA23
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
EXTINT[15]
EXTINT[12]
EXTINT[13]
EXTINT[14]
EXTINT[15]
EXTINT[0]
EXTINT[1]
EXTINT[2]
EXTINT[3]
EXTINT[0]
EXTINT[1]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
EXTINT[12]
EXTINT[13]
EXTINT[6]
X[15]
SERCOM4/
PAD[3]
TC5/WO[1]
GCLK_IO[1]
AC/CMP[0]
AC/CMP[1]
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[2]
GCLK_IO[3]
AC/CMP[0]
AC/CMP[1]
GCLK_IO[2]
GCLK_IO[3]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[6]
GCLK_IO[7]
21
22
23
24
25
26
27
28
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC2/WO[0]
TCC2/WO[1]
TC3/WO[0]
TC3/WO[1]
TCC2/WO[0]
TCC2/WO[1]
TC3/WO[0]
TC3/WO[1]
TC6/WO[0]
TC6/WO[1]
TC7/WO[0]
TC7/WO[1]
TC4/WO[0]
TC4/WO[1]
TC5/WO[0]
TC5/WO[1]
TC7/WO[0]
TCC0/
WO[6]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC0/
WO[7]
15
16
17
18
19
20
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TCC0/
WO[4]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TCC0/
WO[5]
X[4]
X[5]
X[6]
X[7]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC0/WO[6]
TCC0/WO[7]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TCC0/
WO[2]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TCC0/
WO[3]
I2S/SD[0]
I2S/SD[1]
SERCOM5/
PAD[0]
TCC0/
WO[4]
SERCOM5/
PAD[1]
TCC0/
WO[5]
I2S/
MCK[0]
29
30
31
32
33
34
37
X[8]
X[9]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TCC0/
WO[6]
I2S/
SCK[0]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TCC0/
WO[7]
I2S/FS[0]
21
22
23
24
X[10]
X[11]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TCC0/
WO[4]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TCC0/
WO[5]
USB/SOF 1kHz
USB/DM
(6)
PA24
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TCC1/
WO[2]
(6)
PA25
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TCC1/
WO[3]
USB/DP
PB22
PB23
PA27
PA28
PA30
PA31
SERCOM5/
PAD[2]
TCC3/
WO[0]
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[0]
GCLK_IO[0]
GCLK_IO[0]
38
39
41
45
46
50
51
53
57
58
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
EXTINT[7]
EXTINT[15]
EXTINT[8]
EXTINT[10]
EXTINT[11]
SERCOM5/
PAD[3]
TC7/WO[1]
TCC3/
WO[1]
25
27
31
32
TCC3/
WO[6]
TCC3/
WO[7]
SERCOM1/
PAD[2]
TCC1/WO[0]
TCC1/WO[1]
TCC3/
WO[4]
SWCLK
(5)
SERCOM1/
PAD[3]
TCC3/
WO[5]
SWDIO
59
60
61
62
63
PB30
PB31
PB00
PB01
PB02
VDDIO
VDDIO
EXTINT[14]
EXTINT[15]
EXTINT[0]
EXTINT[1]
EXTINT[2]
SERCOM5/
PAD[0]
TCC0/WO[0]
TCC0/WO[1]
TC7/WO[0]
TC7/WO[1]
TC6/WO[0]
TCC1/
WO[2]
SERCOM5/
PAD[1]
TCC1/
WO[3]
VDDANA
VDDANA
VDDANA
AIN[8]
AIN[9]
Y[6]
Y[7]
Y[8]
SERCOM5/
PAD[2]
SERCOM5/
PAD[3]
47
48
AIN[10]
SERCOM5/
PAD[0]
TCC3/
WO[2]
64
PB03
VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
TC6/WO[1]
TCC3/
WO[3]
DS40001882G-page 30
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
1. Use the SAMD21J pinout muxing for WLCSP45 package.
2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the
digital control of the pin.
3. Only some pins can be used in SERCOM I2C mode. Refer to 7.2.3 SERCOM I2C Pins.
4. TC6 and TC7 are not supported on the SAM D21E. Refer to 2. Configuration Summary for details.
5. This function is only activated in the presence of a debugger.
6. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25
through input GPIO mode. The aim is to avoid an eventually extract power consumption (<1mA) due to a not
stable level on pad. The port PA24 and PA25 doesn't have Drive Strength option.
7. SERCOM4 and SERCOM5 are not supported in SAMD21ExxA, SAMD21E15(B/BU/CU/L),
SAMD21E16(B/BU/CU/L) and SAMD21E17(D/DU/L). Refer to the 2. Configuration Summary for details.
8. TCC3 is only supported in SAMD21x17D. Refer to the 2. Configuration Summary for details.
Table 7-2.ꢀ PORT Function Multiplexing for L Variant Devices
(1)(2)
Pin
I/O Pin
Supply
A
B
C
D
E
F
G
H
(1)(2)
(7)
(3)
TC
SAMD21ExL
SAMD21GxL
EIC
REF
ADC
AIN[0]
AIN[1]
AC
AC1
DAC
SERCOM
SERCOM-ALT
TCC
COM
AC/
/TCC
GCLK
1
2
1
2
PA02
PA03
VDDANA
VDDANA
EXTINT[2]
EXTINT[3]
VOUT
TCC3/
WO[0]
DAC/VREFA
TCC3/
WO[1]
3
4
3
4
7
PB04
PB05
PB08
VDDANA
VDDANA
VDDANA
EXTINT[4]
EXTINT[5]
EXTINT[8]
AIN[12]
AIN[13]
AIN[2]
AIN[0]
AIN[1]
SERCOM4/
PAD[0]
TC4/WO[0]
TC4/WO[1]
TCC3/
WO[6]
8
PB09
PA04
PA05
PA06
PA07
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
EXTINT[9]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
AIN[3]
AIN[4]
AIN[5]
AIN[6]
AIN[7]
SERCOM4/
PAD[1]
TCC3/
WO[7]
5
6
7
8
9
ADC/VREFB
AIN[0]
AIN[1]
AIN[2]
AIN[3]
SERCOM0/
PAD[0]
TCC0/WO[0]
TCC0/WO[1]
TCC1/WO[0]
TCC1/WO[1]
TCC3/
WO[2]
10
11
12
SERCOM0/
PAD[1]
TCC3/
WO[3]
SERCOM0/
PAD[2]
TCC3/
WO[4]
SERCOM0/
PAD[3]
TCC3/
WO[5]
11
12
13
14
13
14
15
16
19
20
21
22
23
24
25
26
PA08
PA09
PA10
PA11
PB10
PB11
PA12
PA13
PA14
PA15
PA16
PA17
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
NMI
AIN[16]
AIN[17]
AIN[18]
AIN[19]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC0/WO[1]
TCC1/WO[0]
TCC1/WO[1]
TC5/WO[0]
TC5/WO[1]
TCC2/WO[0]
TCC2/WO[1]
TC3/WO[0]
TC3/WO[1]
TCC2/WO[0]
TCC2/WO[1]
TCC1/
WO[2]
EXTINT[9]
EXTINT[10]
EXTINT[11]
EXTINT[10]
EXTINT[11]
EXTINT[12]
EXTINT[13]
EXTINT[14]
EXTINT[15]
EXTINT[0]
EXTINT[1]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC1/
WO[3]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC0/
WO[2]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[4]
GCLK_IO[5]
AC/CMP[0]
AC/CMP[1]
GCLK_IO[0]
GCLK_IO[1]
GCLK_IO[2]
GCLK_IO[3]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC0/
WO[3]
SERCOM4/
PAD[2]
TCC0/
WO[4]
SERCOM4/
PAD[3]
TCC0/
WO[5]
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC0/
WO[6]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC0/
WO[7]
15
16
17
18
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TCC0/
WO[4]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TCC0/
WO[5]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC0/WO[6]
TCC0/WO[7]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
DS40001882G-page 31
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
...........continued
SAMD21ExL
(1)(2)
Pin
I/O Pin
Supply
A
B
C
D
E
F
G
H
(1)(2)
(7)
(3)
TC
SAMD21GxL
EIC
REF
ADC
AC
AC1
DAC
SERCOM
SERCOM-ALT
TCC
COM
AC/
/TCC
GCLK
19
20
27
28
29
30
31
32
33
34
37
PA18
PA19
PA20
PA21
PA22
PA23
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
EXTINT[2]
EXTINT[3]
EXTINT[4]
EXTINT[5]
EXTINT[6]
EXTINT[7]
EXTINT[12]
EXTINT[13]
EXTINT[15]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC3/WO[0]
TCC0/
WO[2]
AC/CMP[0]
AC/CMP[1]
GCLK_IO[4]
GCLK_IO[5]
GCLK_IO[6]
GCLK_IO[7]
AC1/CMP[0]
AC1/CMP[1]
GCLK_IO[0]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC3/WO[1]
TC7/WO[0]
TC7/WO[1]
TC4/WO[0]
TC4/WO[1]
TC5/WO[0]
TC5/WO[1]
TCC0/
WO[3]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TCC0/
WO[6]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TCC0/
WO[7]
21
22
23
24
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TCC0/
WO[4]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TCC0/
WO[5]
(5)
PA24
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TCC1/
WO[2]
(5)
PA25
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TCC1/
WO[3]
PA27
PA28
PA30
PA31
TCC3/
WO[6]
39
43
44
VDDIO
VDDIO
VDDIO
EXTINT[8]
EXTINT[10]
EXTINT[11]
TCC3/
WO[7]
GCLK_IO[0]
GCLK_IO[0]
29
30
SERCOM1/
PAD[2]
TCC1/WO[0]
TCC1/WO[1]
TCC3/
WO[4]
SWCLK
(5)
SWDIO
SERCOM1/
PAD[3]
TCC3/
WO[5]
45
46
47
PB00
PB01
PB02
AIN[8]
AIN[9]
(6)
31
32
VDDANA
VDDANA
EXTINT[2]
EXTINT[3]
AIN[10]
AIN[2]
AIN[3]
SERCOM5/
PAD[0]
TC6/WO[0]
TCC3/
WO[2]
(6)
48
PB03
AIN[11]
SERCOM5/
PAD[1]
TC6/WO[1]
TCC3/
WO[3]
1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the
digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode.
3. TC6 and TC7 are not supported on the SAM D21ExL and SAM D21GxL devices. Refer to 2. Configuration
Summary for details.
4. This function is only activated in the presence of a debugger.
5. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25
through input GPIO mode. The aim is to avoid an eventually extract power consumption (<1mA) due to a not
stable level on pad. The port PA24 and PA25 doesn't have Drive Strength option.
6. TC6 is only available on the SAM D21GxL and not the SAM D21ExL.
7. SERCOM4 and SERCOM5 are not supported on the SAM D21E devices. Refer to 2. Configuration Summary
for details.
8. TCC3 is only supported in SAMD21x17L devices. Refer to the 2. Configuration Summary for details.
Related Links
37. Electrical Characteristics at 85℃
7.2
Other Functions
7.2.1
Oscillator Pinout
The oscillators are not mapped to the normal port functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL).
DS40001882G-page 32
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
Table 7-3.ꢀOscillator Pinout
Oscillator
Supply
Signal
XIN
I/O Pin
PA14
PA15
PA00
XOSC
VDDIO
XOUT
XIN32
XOSC32K
VDDANA
XOUT32
PA01
7.2.2
Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal port functions. A debugger cold-plugging or hot-plugging detection will
automatically switch the SWDIO port to the SWDIO function.
Table 7-4.ꢀSerial Wire Debug Interface Pinout
Signal
Supply
VDDIO
VDDIO
I/O Pin
PA30
SWCLK
SWDIO
PA31
7.2.3
SERCOM I2C Pins
Table 7-5.ꢀSERCOM Pins Supporting I2C
Device
32 pins
48 pins
64 pins
Pins Supporting I2C mode
PA08, PA09, PA16, PA17, PA22, PA23
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23, PB12, PB13, PB16, PB17, PB30,
PB31
7.2.4
GPIO Clusters
Table 7-6.ꢀGPIO Clusters
PACKAGE CLUSTER
GPIO
SUPPLIES PINS CONNECTED TO
THE CLUSTER
64pins
1
2
PB31 PB30 PA31 PA30
PA28 PA27 PB23 PB22
VDDIN pin56/GND pin54
VDDIN pin56/GND pin54 and VDDIO
pin 48/GND pin47
3
4
PA25 PA24 PA23 PA22 PA21 PA20 PB17 PB16 PA19 PA18 PA17 PA16
PA15 PA14 PA13 PA12 PB15 PB14 PB13 PB12 PB11 PB10
VDDIO pin 48/GND pin47 and VDDIO
pin34/GND pin33
VDDIO pin 34/GND pin33 and VDDIO
pin21/GND pin22
5
6
7
PA11 PA10 PA09 PA08
VDDIO pin21/GND pin22
PA07 PA06 PA05 PA04 PB09 PB08 PB07 PB06
PB05 PB04 PA03 PA02 PA01 PA00 PB03 PB02 PB01 PB00
VDDANA pin 8/GNDANA pin7
VDDANA pin 8/GNDANA pin7
DS40001882G-page 33
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I/O Multiplexing and Considerations
...........continued
PACKAGE CLUSTER
GPIO
SUPPLIES PINS CONNECTED TO
THE CLUSTER
48pins
1
2
PA31 PA30
VDDIN pin44/GND pin42
PA28 PA27 PB23 PB22
VDDIN pin44/GND pin42 and VDDIO
pin36/GND pin35
3
PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PB11 PB10 VDDIO pin36/GND pin35 and VDDIO
pin17/GND pin18
4
5
6
1
2
PA11 PA10 PA09 PA08
VDDIO pin17/GND pin18
VDDANA pin6/GNDANA pin5
VDDANA pin6/GNDANA pin5
VDDIN pin30/GND pin 28
PA07 PA06 PA05 PA04 PB09 PB08
PA03 PA02 PA01 PA00 PB03 PB02 PB05 PB04 PB01 PB00
PA31 PA30
32pins
PA28 PA27 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 PA15 PA14 PA11 PA10 PA09 PA08 VDDIN pin30/GND pin 28 and
VDDANA pin9/GND pin10
3
PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 PB05 PB04 PB03 PB02
VDDANA pin9/GND pin10
7.2.5
TCC Configurations
The SAM D21/DA1 has up to four instances of the Timer/Counter for Control applications (TCC) peripheral ,
TCC[3:0]. The following table lists the features for each TCC instance.
Table 7-7.ꢀTCC Configuration Summary
TCC#
Channels
(CC_NUM)
Waveform
Output
Counter Size
Fault
Dithering
Output
Matrix
Dead Time
Insertion
(DTI)
SWAP
Pattern
Generation
(WO_NUM)
0
1
2
3
4
2
2
4
8
4
2
8
24-bit
24-bit
16-bit
24-bit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note:ꢀ The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture
channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
DS40001882G-page 34
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Power Supply and Start-Up Considerations
8.
Power Supply and Start-Up Considerations
8.1
Power Domain Overview
ADC
AC
PB[31:10]
VOLTAGE
REGULATOR
BOD12
OSC8M
XOSC
PA[13:8]
PA[7:2]
PB[9:0]
PA[15:14]
AC1
DAC
PTC
PA[31:16]
Digital Logic
(CPU, peripherals)
PA[1:0]
XOSC32K
OSC32K
POR
DFLL48M
FDPLL96M
OSCULP32K
BOD33
8.2
Power Supply Considerations
8.2.1
Power Supplies
The device has several different power supply pins:
•
•
•
VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.62V to 3.63V.
VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.62V to 3.63V.
VDDANA: Powers I/O lines and the ADC, AC, DAC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.62V
to 3.63V.
•
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, FDPLL96M, and
DFLL48M. Voltage is 1.2V.
The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD
in the datasheet.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
For decoupling recommendations for the different power supplies. Refer to Schematic Checklist for details.
Related Links
45. Schematic Checklist
DS40001882G-page 35
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Power Supply and Start-Up Considerations
8.2.2
8.2.3
Voltage Regulator
The voltage regulator has two different modes:
•
•
Normal mode: To be used when the CPU and peripherals are running
Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby
mode
Typical Powering Schematics
The device uses a single main supply with a range of 1.62V - 3.63V.
The following figure shows the recommended power supply connection.
Figure 8-1.ꢀPower Supply Connection
DEVICE
Main Supply
(1.62V — 3.63V)
VDDIO
VDDANA
VDDIN
VDDCORE
GND
GNDANA
8.2.4
Power-Up Sequence
8.2.4.1 Minimum Rise Rate
The integrated Power-on Reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate.
Refer to the Electrical Characteristics for details.
Related Links
37. Electrical Characteristics at 85℃
8.2.4.2 Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the
Electrical Characteristics for details.
Related Links
37. Electrical Characteristics at 85℃
DS40001882G-page 36
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Power Supply and Start-Up Considerations
8.3
Power-Up
This section summarizes the power-up sequence of the device. The behavior after power-up is controlled by the
Power Manager. Refer to PM – Power Manager for details.
Related Links
16. PM – Power Manager
8.3.1
Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the
device. Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal
Oscillator (OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic
clock generator 0 is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” section in PM – Power Manager for the list of default peripheral clocks running.
Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through generic
clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
Related Links
16. PM – Power Manager
8.3.2
8.3.3
I/O Pins
After power-up, the I/O pins are tri-stated.
Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is
0x00000000. This address points to the first executable address in the internal Flash. The code read from the Internal
Flash is free to configure the clock system and clock sources. Refer to PM – Power Manager, GCLK – Generic Clock
Controller and SYSCTRL – System Controller for details. Refer to the ARM Architecture Reference Manual for more
information on CPU startup (http://www.arm.com).
Related Links
16. PM – Power Manager
17. SYSCTRL – System Controller
14. Clock System
8.4
Power-On Reset and Brown-Out Detector
The SAM D21 embeds three features to monitor, warn and/or reset the device:
•
•
•
POR: Power-On Reset on VDDANA
BOD33: Brown-Out Detector on VDDANA
BOD12: Voltage Regulator Internal Brown-Out Detector on VDDCORE. The Voltage Regulator Internal BOD
is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration
should not be changed if the user row is written to assure the correct behavior of the BOD12.
8.4.1
8.4.2
Power-On Reset on VDDANA
POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDANA goes below the threshold voltage, the entire chip is reset.
Brown-Out Detector on VDDANA
BOD33 monitors VDDANA. Refer to SYSCTRL – System Controller for details.
Related Links
17. SYSCTRL – System Controller
DS40001882G-page 37
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Power Supply and Start-Up Considerations
8.4.3
Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
DS40001882G-page 38
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Product Mapping
9.
Product Mapping
Figure 9-1.ꢀSAM D21 Product Mapping
Code
0x00000000
0x00040000
Device Variant B/C/D/L
Device Variant A
Internal Flash
Reserved
AHB-APB Bridge C
0x00000000
0x42000000
Global Memory Space
Internal Flash
Reserved
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
SERCOM5
TCC0
0x00000000
0x00040000
0x1FFFFFFF
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42001C00
0x42002000
0x42002400
0x42002800
0x42002C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
0x42004C00
0x42005000
0x42005400
0x00400000
Internal
RWWEE
Section
Code
SRAM
0x20000000
0x20008000
0x40000000
0x43000000
0x60000000
0x1FFFFFFF
SRAM
0x20000000
0x20007FFF
Internal SRAM
Undefined
Peripherals
AHB-APB
0x40000000
0x41000000
AHB-APB
Bridge A
AHB-APB
Bridge B
0x42000000
0x42FFFFFF
Reserved
AHB-APB
Bridge C
TCC1
TCC2
IOBUS
System
0xE0000000
0xE000E000
0xE000F000
0xE00FF000
TC3
Reserved
0x60000200
0xE0000000
Reserved
TC4
SCS
TC5
System
Reserved
ROMTable
Reserved
0xFFFFFFFF
TC6
0xE0100000
0xFFFFFFFF
TC7
ADC
AHB-APB Bridge A
AHB-APB Bridge B
0x41000000
0x40000000
AC
PAC1
DSU
PAC0
PM
0x41002000
0x41004000
0x41004400
0x41004800
0x41005000
0x41006000
0x40000400
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
DAC
PTC
NVMCTRL
PORT
SYSCTRL
GCLK
WDT
I2S
AC1
DMAC
USB
0x42005800
0x42006000
Reserved
TCC3
RTC
0x42006090
0x4200FFFF
Reserved
MTB
EIC
0x40001C00
0x40FFFFFF
0x41007000
0x41FFFFFF
Reserved
Reserved
DS40001882G-page 39
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Product Mapping
This figure represents the full configuration of the SAM D21 with maximum Flash and SRAM capabilities and a full set
of peripherals. Refer to the 2. Configuration Summary for details.
DS40001882G-page 40
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Memories
10.
Memories
10.1
Embedded Memories
•
Internal high-speed Flash
•
Read-While-Write EEPROM Emulation (RWWEE, standing for Read (the main array) while Write (the EEPROM
Emulation)) (Only available on device variant B, C, D, and L)
•
Internal high-speed RAM, single-cycle access at full speed
10.2
Physical Memory Map
The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never
remapped in any way, even during boot. The 32-bit physical address space is mapped as follow:
Table 10-1.ꢀSAM D21 Physical Memory Map(1)(1)
Memory
Start address
Size
SAMD21x18 SAMD21x17 SAMD21x16 SAMD21x15 SAMD21x16L SAMD21x15L
Internal Flash
0x00000000
0x00400000
256 Kbytes
-
128 Kbytes
4 Kbytes
64 Kbytes
2 Kbytes
32 Kbytes
1 Kbytes
64 Kbytes
2 Kbytes
32 Kbytes
1 Kbytes
Internal RWWEE Emulation
(2)
section
Internal SRAM
Peripheral Bridge A
Peripheral Bridge B
Peripheral Bridge C
IOBUS
0x20000000
0x40000000
0x41000000
0x42000000
0x60000000
32 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
16 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
8 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
4 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
8 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
4 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
0.5 Kbytes
Table 10-2.ꢀSAM DA1 Physical memory map(1)
Memory
Start Address
Size
SAMDA1x16
64Kbytes
2Kbytes
SAMDA1x15
32Kbytes
1Kbytes
SAMDA1x14
16Kbytes
512bytes
4Kbytes
Internal Flash
0x00000000
Internal RWWEE Emulation section
Internal SRAM
0x00400000
0x20000000
0x40000000
0x41000000
0x42000000
8Kbytes
4Kbytes
Peripheral Bridge A
Peripheral Bridge B
Peripheral Bridge C
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Notes:
1. x = G, J, or E.
2. Only applicable for device variants B, C, D, and L.
DS40001882G-page 41
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Memories
Table 10-3.ꢀSAM D21 Flash Memory Parameters(1,2)(1)
Device
Flash size
256 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
Number of pages
Page size
64 bytes
64 bytes
64 bytes
64 bytes
SAMD21x18
SAMD21x17
SAMD21x16
SAMD21x15
4096
2048
1024
512
Table 10-4.ꢀSAM DA1 Flash memory parameters(1)
Device
Flash Size
64Kbytes
32Kbytes
16Kbytes
Number of Pages
Page Size
64 bytes
64 bytes
64 bytes
SAMDA1x16
SAMDA1x15
SAMDA1x14
1024
512
256
Notes:
1. x = G, J, or E.
2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the
NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to NVM Parameter
(PARAM) register for details.
Table 10-5.ꢀSAM D21 RWWEE Emulation Section Parameters (Device Variants B, C, D,and L)
Device(1)
Flash size
4 Kbytes
2 Kbytes
1 Kbytes
Number of pages
Page size
64 bytes
64 bytes
64 bytes
SAMD21x17
SAMD21x16
SAMD21x15
64
32
16
Table 10-6.ꢀSAM DA1 RWWEE Emulation Section Parameters
Device
Flash Size
2Kbytes
Number of Pages
Page Size
64 bytes
64 bytes
64 bytes
SAMDA1x16
SAMDA1x15
SAMDA1x14
32
16
8
1Kbytes
512 bytes
Note:ꢀ
1. x = G, J, or E.
Related Links
22.8.3 PARAM
3. SAM D21 Ordering Information(1)
10.3
NVM Calibration and Auxiliary Space
The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in
the following figure.
DS40001882G-page 42
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Memories
Figure 10-1.ꢀCalibration and Auxiliary Space
AUX1
0x00806040
0x00806020
Calibration and
Area 4: Software
calibration area (256bits)
auxiliary space
0x00800000
NVM base address +
0x00800000
Area 4 offset address
Area 3: Reserved
(128bits)
NVM base address
+ NVM size
0x00806010
0x00806008
Area 3 offset address
Area 2: Device configuration
NVM main address
space
area (64 bits)
Area 2 offset address
Area 1: Reserved (64 bits)
0x00806000
Area 1 address offset
0x00000000
NVM Base Address
AUX1
0x00806000
0x00804000
AUX1 offset address
AUX0 offset address
AUX0 – NVM User
Row
Automatic calibration
row
Calibration and auxiliary
space address offset
0x00800000
The values from the automatic calibration row are loaded into their respective registers at startup.
10.3.1 NVM User Row Mapping
The first two 32-bit words of the NVM User Row contain calibration data that are automatically read at device power
on.
The NVM User Row can be read at address 0x804000.
To write the NVM User Row refer to NVMCTRL – Non-Volatile Memory Controller.
When writing to the user row the values do not get loaded by the other modules on the device until a device reset
occurs.
Table 10-7.ꢀNVM User Row Mapping
Bit Position
Name
Usage
2:0
BOOTPROT
Used to select one of eight different bootloader sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller”. Default value = 7 except for WLCSP (Default
value = 3).
3
Reserved
EEPROM
6:4
Used to select one of eight different EEPROM Emulation sizes. Refer to
“NVMCTRL – Non-Volatile Memory Controller”. Default value = 7.
7
Reserved
13:8
BOD33 Level
BOD33 Threshold Level at power on. Refer to the SYSCTRL BOD33 register.
Default value = 0x7 (non-AECQ100)
Default value = 0x22 (AECQ100)
14
BOD33 Enable BOD33 enable at power on. Refer to the SYSCTRL BOD33 register. Default
value = 1.
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SAM D21/DA1 Family
Memories
...........continued
Bit Position
Name
Usage
16:15
24:17
25
BOD33 Action
BOD33 Action at power on. Refer to the SYSCTRL BOD33 register. Default
value = 1.
Reserved
Voltage Regulator Internal BOD (BOD12) configuration. These bits are written in
production and must not be changed. Default value = 0x70.
WDT Enable
WDT Enable at power on. Refer to the WDT CTRL register.
Default value = 0.
26
30:27
34:31
38:35
39
WDT Always-On WDT Always-On at power on. Refer to the WDT CTRL register.
Default value = 0.
WDT Period
WDT Period at power on. Refer to the WDT CONFIG register.
Default value = 0x0B.
WDT Window
WDT Window mode time-out at power on. Refer to the WDT CONFIG register.
Default value = 0x05.
WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to the WDT
EWCTRL register. Default value = 0x0B.
WDT WEN
WDT Timer Window Mode Enable at power on. Refer to the WDT CTRL register.
Default value = 0.
40
BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to the SYSCTRL BOD33
register.
Default value = 0.
41
Reserved
Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in
production and must not be changed. Default value = 0.
47:42
63:48
Reserved
LOCK
NVM Region Lock Bits. Refer to “NVMCTRL – Non-Volatile Memory Controller”.
Default value = 0xFFFF.
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
17.8.14 BOD33
18.8.1 CTRL
10.3.2 NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x806020.
The NVM Software Calibration Area can not be written.
Table 10-8.ꢀNVM Software Calibration Area Mapping
Bit Position Name
Description
2:0
Reserved
14:3
Reserved
26:15
34:27
37:35
Reserved
ADC LINEARITY
ADC BIASCAL
ADC Linearity Calibration. Should be written to ADC CALIB register.
ADC Bias Calibration. Should be written to ADC CALIB register.
DS40001882G-page 44
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Memories
...........continued
Bit Position Name
Description
44:38
49:45
OSC32K CAL
OSC32KCalibration. Should be written to SYSCTRL OSC32K register.
USB TRANSN
USB TRANSP
USB TRIM
USB TRANSN calibration value. Should be written to USB PADCAL
register.
54:50
57:55
63:58
USB TRANSP calibration value. Should be written to USB PADCAL
register.
USB TRIM calibration value. Should be written to the USB PADCAL
register.
DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to SYSCTRL
DFLLVAL register.
73:64
Reserved
Reserved
127:74
10.3.3 Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the
following addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
DS40001882G-page 45
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.
Processor And Architecture
11.1
Cortex M0+ Processor
®
®
®
The SAM D21 implements the ARM Cortex -M0+ processor, based on the ARMv6 Architecture and Thumb -2 ISA.
The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible
to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more information refer to
www.arm.com.
11.1.1
Cortex M0+ Configuration
Table 11-1.ꢀCortex M0+ Configuration
Features
Configurable option
External interrupts 0-32
Little-endian or big-endian
Present or absent
0, 1, 2
Device configuration
28
Interrupts
Data endianness
Little-endian
Present
SysTick timer
Number of watchpoint comparators
Number of breakpoint comparators
Halting debug support
Multiplier
2
0, 1, 2, 3, 4
4
Present or absent
Fast or small
Present
Fast (single cycle)
Present
Single-cycle I/O port
Wake-up interrupt controller
Vector Table Offset Register
Unprivileged/Privileged support
Memory Protection Unit
Reset all registers
Present or absent
Supported or not supported
Present or absent
Present or absent
Not present or 8-region
Present or absent
16-bit only or mostly 32-bit
Not supported
Present
Absent(1)
Not present
Absent
Instruction fetch width
32-bit
Note:ꢀ
1. All software run in Privileged mode only.
The ARM Cortex-M0+ core has the following two bus interfaces:
•
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory, which includes Flash and RAM.
•
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
11.1.2
Cortex-M0+ Peripherals
•
•
•
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the
processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Nested Vectored Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
DS40001882G-page 46
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
latency interrupt processing and efficient processing of late arriving interrupts. Refer to 11.2 Nested Vector
Interrupt Controller and the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
•
•
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (www.arm.com).
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to section 11.3 Micro Trace Buffer and the CoreSight MTB-M0+ Technical Reference Manual for
details (www.arm.com).
11.1.3
Cortex-M0+ Address Map
Table 11-2.ꢀCortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
System Timer (SysTick)
0xE000E010
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
System Control Block (SCB)
Micro Trace Buffer (MTB)
0xE000ED00
0x41006000 (see also Product Mapping)
11.1.4
I/O Interface
11.1.4.1 Overview
®
™
Because accesses to the AMBA AHB-Lite and the single cycle I/O interface can be made concurrently, the
Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O
accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information.
Related Links
23.5.10 CPU Local Bus
11.1.4.2 Description
Direct access to PORT registers.
11.2
Nested Vector Interrupt Controller
11.2.1
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM D21 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
11.2.2
Interrupt Line Mapping
Each of the 29 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral
can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
The Interrupt flag is set when the Interrupt condition occurs. Each interrupt in the peripheral can be individually
enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and
disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the Interrupt flag is set and the corresponding interrupt
is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt
request for each peripheral. An interrupt request will set the corresponding Interrupt Pending bit in the NVIC Interrupt
Pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be
enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC Interrupt Priority
registers IPR0-IPR7 provide a priority field for each interrupt.
DS40001882G-page 47
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SAM D21/DA1 Family
Processor And Architecture
Table 11-3.ꢀInterrupt Line Mapping
Peripheral Source
NVIC Line
EIC NMI – External Interrupt Controller
PM – Power Manager
NMI
0
SYSCTRL – System Control
1
WDT – Watchdog Timer
2
RTC – Real-Time Counter
3
EIC – External Interrupt Controller
NVMCTRL – Nonvolatile Memory Controller
DMAC - Direct Memory Access Controller
USB - Universal Serial Bus
4
5
6
7
EVSYS – Event System
8
SERCOM0 – Serial Communication Interface 0
SERCOM1 – Serial Communication Interface 1
SERCOM2 – Serial Communication Interface 2
SERCOM3 – Serial Communication Interface 3
SERCOM4 – Serial Communication Interface 4
SERCOM5 – Serial Communication Interface 5
TCC0 – Timer Counter for Control 0
TCC1 – Timer Counter for Control 1
TCC2 – Timer Counter for Control 2
TC3 – Timer Counter 3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
TC4 – Timer Counter 4
TC5 – Timer Counter 5
TC6 – Timer Counter 6
TC7 – Timer Counter 7
ADC – Analog-to-Digital Converter
AC – Analog Comparator
DAC – Digital-to-Analog Converter
PTC – Peripheral Touch Controller
I2S - Inter IC Sound
AC1 - Analog Comparator 1
TCC3 - Timer Counter for Control 3
DS40001882G-page 48
Complete Datasheet
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SAM D21/DA1 Family
Processor And Architecture
11.3
Micro Trace Buffer
11.3.1
Features
•
•
•
•
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
11.3.2
Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored
as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug
Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from
this information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor
PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during
exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution
trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control register is 1. There are various ways to set
the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for
more details on the trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can
be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop
tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer
overflows, then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has four programmable registers to control the behavior of the trace features:
•
•
•
•
POSITION: Contains the trace Write Pointer and the wrap bit,
MASTER: Contains the main trace enable bit and other trace control fields,
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto-discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
11.4
High-Speed Bus System
11.4.1
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different hosts to different clients
32-bit data bus
Operation at a one-to-one clock frequency with the bus hosts
DS40001882G-page 49
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.4.2
Configuration
High-Speed Bus CLIENTS
SRAM
0
1
2
3
Client ID
4
4
5
5
6
SRAM PORT ID
0
1
2
3
6
Host ID
CM0+
0
1
2
DSU
DMACData
MTB
USB
DMAC WB
DMAC Fetch
Table 11-4.ꢀBus Matrix Hosts
Bus Matrix Hosts
Host ID
CM0+ - Cortex M0+ Processor
DSU - Device Service Unit
0
1
2
DMAC - Direct Memory Access Controller - Data Access
Table 11-5.ꢀBus Matrix Clients
Bus Matrix Clients
Client ID
Internal Flash Memory
AHB-APB Bridge A
0
1
2
3
4
5
6
AHB-APB Bridge B
AHB-APB Bridge C
SRAM Port 4 - CM0+ Access
SRAM Port 5 - DMAC Data Access
SRAM Port 6 - DSU Access
DS40001882G-page 50
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
Table 11-6.ꢀSRAM Port Connection
SRAM Port Connection
Port ID
Connection Type
Direct
MTB - Micro Trace Buffer
0
1
2
3
4
5
6
USB - Universal Serial Bus
Direct
DMAC - Direct Memory Access Controller - Write-Back Access
DMAC - Direct Memory Access Controller - Fetch Access
CM0+ - Cortex M0+ Processor
Direct
Direct
Bus Matrix
Bus Matrix
Bus Matrix
DMAC - Direct Memory Access Controller - Data Access
DSU - Device Service Unit
11.4.3
SRAM Quality of Service
To ensure that hosts with latency requirements get sufficient priority when accessing RAM, the different hosts can be
configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each host accessing the RAM. For any access to
the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level
configuration is shown in the following table.
Table 11-7.ꢀQuality of Service
Value
00
Name
Description
DISABLE
LOW
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
01
10
MEDIUM
HIGH
11
Critical Latency
If a host is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access.
The priority order for concurrent accesses are decided by two factors. First the QoS level for the host and then a
static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static
priority.
The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.
The CPU QoS level can be written/read at address 0x41007120, bits [1:0]. Its reset value is 0x2.
Refer to different host QOSCTRL registers for configuring QoS for the other hosts (USB, DMAC).
11.5
AHB-APB Bridge
The AHB-APB bridge is an AHB client, providing an interface between the high-speed AHB domain and the low-
power APB domain. It is used to provide access to the Programmable Control registers of peripherals.
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:
•
•
•
•
Wait state support
Error reporting
Transaction protection
Sparse data transfer (byte, half-word and word)
Additional enhancements:
•
•
Address and data cycles merged into a single cycle
Sparse data transfer also apply to read access
DS40001882G-page 51
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
To operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See PM – Power Manager for
details.
Figure 11-1.ꢀAPB Write Access
T0
T1
T2
T3
T0
T1
T2
T3
T4
T5
PCLK
PADDR
PCLK
PADDR
Addr 1
Addr 1
PWRITE
PSEL
PWRITE
PSEL
PENABLE
PWDATA
PREADY
PENABLE
PWDATA
PREADY
Data 1
Data 1
No wait states
Wait states
Figure 11-2.ꢀAPB Read Access
T0
T1
T2
T3
T0
T1
T2
T3
T4
T5
PCLK
PADDR
PCLK
PADDR
Addr 1
Addr 1
PWRITE
PSEL
PWRITE
PSEL
PENABLE
PRDATA
PREADY
PENABLE
PRDATA
PREADY
Data 1
Data 1
No wait states
Wait states
Related Links
16. PM – Power Manager
9. Product Mapping
11.6
Peripheral Access Controller (PAC)
11.6.1
Overview
One PAC is associated with each AHB-APB bridge and the PAC can provide write protection for registers of each
peripheral connected on the same bridge.
The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager.
CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset. Refer to PM
– Power Manager for details. The PAC will continue to operate in any Sleep mode where the selected clock source is
running. Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral,
write-protection is ignored so that the debugger can update the register.
DS40001882G-page 52
Complete Datasheet
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SAM D21/DA1 Family
Processor And Architecture
Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify-
write operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the
register bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in
both registers (WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing
a one to a bit in the Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and
WPSET) and enable the write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will
return the same value when read.
If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will
return an access error (CPU exception).
The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double
write-protection or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in
WPSET[n] is detected, the PAC returns an error. This can be used to ensure that the application follows the intended
program flow by always following a write-protect with an unprotect, and vice versa. However, in applications where
a write-protected peripheral is used in several contexts, for example, interrupts, care should be taken so that either
the interrupt can not happen while the main application or other interrupt levels manipulate the write-protection status,
or when the interrupt handler needs to unprotect the peripheral, based on the current protection status, by reading
WPSET.
Related Links
16. PM – Power Manager
11.6.2
Register Description
Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register,
and the 8-bit halves of a 16-bit register can be accessed directly. Refer to the Product Mapping for PAC locations.
11.6.2.1 PAC0 Register Description
DS40001882G-page 53
Complete Datasheet
© 2021 Microchip Technology Inc.
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Processor And Architecture
11.6.2.1.1 Write Protect Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WPCLR
0x00
0x000000
–
Property:ꢀ
Bit
31
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
23
Access
Reset
Bit
15
7
Access
Reset
Bit
6
EIC
R/W
0
5
4
WDT
R/W
0
3
GCLK
R/W
0
2
SYSCTRL
R/W
1
PM
R/W
0
0
RTC
R/W
0
Access
Reset
0
Bit 6 – EIC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 5 – RTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 4 – WDTꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 3 – GCLK
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
DS40001882G-page 54
Complete Datasheet
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SAM D21/DA1 Family
Processor And Architecture
Bit 2 – SYSCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 1 – PM
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
DS40001882G-page 55
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.6.2.1.2 Write-Protect Set
Name:ꢀ
WPSET
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x04
0x000000
–
Bit
31
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
23
Access
Reset
Bit
15
7
Access
Reset
Bit
6
EIC
R/W
0
5
4
WDT
R/W
0
3
GCLK
R/W
0
2
SYSCTRL
R/W
1
PM
R/W
0
0
RTC
R/W
0
Access
Reset
0
Bit 6 – EIC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 5 – RTC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 4 – WDTꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 3 – GCLK
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
DS40001882G-page 56
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
Bit 2 – SYSCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 1 – PM
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
11.6.2.2 PAC1 Register Description
DS40001882G-page 57
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.6.2.2.1 Write Protect Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WPCLR
0x00
0x000002
–
Property:ꢀ
Bit
31
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
23
Access
Reset
Bit
15
7
Access
Reset
Bit
6
5
4
DMAC
R/W
0
3
PORT
R/W
0
2
NVMCTRL
R/W
1
0
MTB
R/W
0
USB
R/W
0
DSU
R/W
1
Access
Reset
0
Bit 6 – MTB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 5 – USB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 4 – DMACꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 3 – PORT
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
DS40001882G-page 58
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Processor And Architecture
Bit 2 – NVMCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
Bit 1 – DSU
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
1
Write-protection is disabled.
Write-protection is enabled.
DS40001882G-page 59
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.6.2.2.2 Write-Protect Set
Name:ꢀ
WPSET
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x04
0x000002
–
Bit
31
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
23
Access
Reset
Bit
15
7
Access
Reset
Bit
6
5
4
DMAC
R/W
0
3
PORT
R/W
0
2
NVMCTRL
R/W
1
0
MTB
R/W
0
USB
R/W
0
DSU
R/W
1
Access
Reset
0
Bit 6 – MTB
Writing a zero to these bits has no effect.
Writing a one to these bits will Set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 5 – USB
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 4 – DMACꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 3 – PORT
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
DS40001882G-page 60
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Processor And Architecture
Bit 2 – NVMCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 1 – DSU
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
11.6.2.3 PAC2 Register Description
DS40001882G-page 61
Complete Datasheet
© 2021 Microchip Technology Inc.
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Processor And Architecture
11.6.2.3.1 Write-Protect Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WPCLR
0x00
0x00800000
–
Property:ꢀ
Bit
31
23
30
22
29
28
27
26
25
24
TCC3
R/W
0
Access
Reset
Bit
21
AC1
R/W
0
20
I2S
R/W
0
19
PTC
R/W
0
18
DAC
R/W
0
17
AC
R/W
0
16
ADC
R/W
0
Access
Reset
Bit
15
TC7
R/W
0
14
TC6
R/W
0
13
TC5
R/W
0
12
TC4
R/W
0
11
TC3
R/W
0
10
TCC2
R/W
0
9
TCC1
R/W
0
8
TCC0
R/W
0
Access
Reset
Bit
7
6
5
4
3
2
1
EVSYS
R/W
0
0
SERCOM[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 24 – TCC3
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 21 – AC1
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 20 – I2S
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 19 – PTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
DS40001882G-page 62
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
Bit 18 – DACꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 17 – AC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 16 – ADC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 11, 12, 13, 14, 15 – TC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 8, 9, 10 – TCC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 7:2 – SERCOM[5:0]
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 1 – EVSYS
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
DS40001882G-page 63
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
11.6.2.3.2 Write-Protect Set
Name:ꢀ
WPSET
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x04
0x00800000
–
Bit
31
23
30
29
28
27
26
25
24
TCC3
R/W
0
Access
Reset
Bit
22
21
AC1
R/W
0
20
I2S
R/W
0
19
PTC
R/W
0
18
DAC
R/W
0
17
AC
R/W
0
16
ADC
R/W
0
Access
Reset
Bit
15
TC7
R/W
0
14
TC6
R/W
0
13
TC5
R/W
0
12
TC4
R/W
0
11
TC3
R/W
0
10
TCC2
R/W
0
9
TCC1
R/W
0
8
TCC0
R/W
0
Access
Reset
Bit
7
SERCOM5
R/W
6
SERCOM4
R/W
5
SERCOM3
R/W
4
SERCOM2
R/W
3
SERCOM1
R/W
2
SERCOM0
R/W
1
EVSYS
R/W
0
0
Access
Reset
0
0
0
0
0
0
Bit 24 – TCC3
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 21 – AC1
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 20 – I2S
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 19 – PTC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
DS40001882G-page 64
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Processor And Architecture
Bit 18 – DACꢀ
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 17 – AC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 16 – ADC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 11, 12, 13, 14, 15 – TC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 8, 9, 10 – TCC
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bits 2, 3, 4, 5, 6, 7 – SERCOM
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
Bit 1 – EVSYS
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write-Protect bit for the corresponding peripherals.
Value
Description
0
1
Write protection is disabled
Write protection is enabled
11.7
Register Access and Behavior
Write protected registers, enable protected registers, and registers in sync process should not be accessed. These
accesses are illegal, and an attempt to access these registers will result generation of hard fault exception.
DS40001882G-page 65
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripherals Configuration Summary
12.
Peripherals Configuration Summary
Table 12-1.ꢀPeripherals Configuration Summary
Periph.
Name
Base
IRQ AHB Clock
APB Clock
Generic Clock
PAC
Events
User
DMA
Index Enabled Index Enabled Index
Index Prot.
Generator
Index
Sleep
Address
Line
at Reset
at Reset
at Reset
Walking
AHB-APB
Bridge A
0x40000000
0
Y
PAC0
PM
0x40000000
0x40000400
0
1
2
Y
Y
Y
0
1
1
2
N
Y
Y
SYSCTRL 0x40000800
0: DFLL48M
reference
N
1: FDPLL96M clk source
2: FDPLL96M 32kHz
GCLK
WDT
RTC
0x40000C00
0x40001000
0x40001400
3
4
5
Y
Y
Y
3
4
5
N
N
N
Y
Y
2
3
3
4
1: CMP0/ALARM0
2: CMP1
3: OVF
4-11: PER0-7
EIC
0x40001800 NMI,
4
6
Y
5
6
N
12-27: EXTINT0-15
Y
AHB-APB
Bridge B
0x41000000
1
Y
PAC1
DSU
0x41000000
0x41002000
0
1
2
3
4
5
Y
Y
Y
Y
Y
Y
3
4
Y
Y
1
2
3
4
5
6
Y
N
N
N
N
N
NVMCTRL 0x41004000
5
PORT
DMAC
USB
0x41004400
0x41004800
0x41005000
0x41006000
0x42000000
6
7
5
6
Y
Y
0-3: CH0-3
30-33: CH0-3
6
Y
MTB
AHB-APB
Bridge C
2
Y
PAC2
0x42000000
0x42000400
0
1
2
N
N
N
EVSYS
8
9
7-18: one per CHANNEL
1
2
N
N
Y
Y
SERCOM0 0x42000800
20: CORE
19: SLOW
1: RX
2: TX
SERCOM1 0x42000C00 10
SERCOM2 0x42001000 11
SERCOM3 0x42001400 12
SERCOM4 0x42001800 13
SERCOM5 0x42001C00 14
3
4
5
6
7
8
N
N
N
N
N
N
21: CORE
19: SLOW
3
4
5
6
7
8
N
N
N
N
N
N
3: RX
4: TX
Y
Y
Y
Y
Y
Y
22: CORE
19: SLOW
5: RX
6: TX
23: CORE
19: SLOW
7: RX
8: TX
24: CORE
19: SLOW
9: RX
10: TX
25: CORE
19: SLOW
11: RX
12: TX
TCC0
TCC1
TCC2
0x42002000 15
0x42002400 16
0x42002800 17
26
26
27
4-5: EV0-1
6-9: MC0-3
34: OVF
35: TRG
13: OVF
14-17: MC0-3
36: CNT
37-40: MC0-3
9
N
N
9
N
N
10-11: EV0-1
12-13: MC0-1
41: OVF
42: TRG
18: OVF
Y
Y
19-20: MC0-1
43: CNT
44-45: MC0-1
10
10
14-15: EV0-1
16-17: MC0-1
46: OVF
47: TRG
21: OVF
22-23: MC0-1
48: CNT
49-50: MC0-1
TC3
TC4
0x42002C00 18
0x42003000 19
11
12
N
N
27
28
11
12
N
N
18: EV
19: EV
51: OVF
24: OVF
Y
Y
52-53: MC0-1
25-26: MC0-1
54: OVF
27: OVF
55-56: MCX0-1
28-29: MC0-1
DS40001882G-page 66
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripherals Configuration Summary
...........continued
Periph.
Name
Base
Address
IRQ AHB Clock
APB Clock
Generic Clock
PAC
Events
User
DMA
Index Enabled Index Enabled Index
Index Prot.
Generator
Index
Sleep
Line
at Reset
at Reset
at Reset
Walking
TC5
TC6
TC7
0x42003400 20
0x42003800 21
0x42003C00 22
13
14
15
N
28
29
29
13
14
15
N
20: EV
21: EV
22: EV
57: OVF
30: OVF
Y
Y
Y
58-59: MC0-1
31-32: MC0-1
N
N
N
N
60: OVF
33: OVF
61-62: MC0-1
34-35: MC0-1
63: OVF
36: OVF
64-65: MC0-1
37-38: MC0-1
ADC
AC
0x42004000 23
0x42004400 24
16
17
Y
N
30
16
17
N
N
23: START
24: SYNC
66: RESRDY
67: WINMON
39: RESRDY
Y
Y
31: DIG
32: ANA
25-26: SOC0-1
68-69: COMP0-1
70: WIN0
DAC
PTC
0x42004800 25
0x42004C00 26
18
19
N
N
33
34
18
19
N
N
27: START
71: EMPTY
40: EMPTY
Y
28: STCONV
72: EOC
73: WCOMP
I2S
0x42005000 27
0x42005400 28
20
21
N
N
35-36
20
21
N
N
41:42: RX
43:44: TX
Y
Y
AC1
31: DIG
32: ANA
25-26: SOC0-1
68-69: COMP0-1
70: WIN0
TCC3
0x42006000 29
22
N
37
24
N
31-32: EV0-1, 33-36: MC0-3
77: OVF, 78: TRG, 79 CNT, 80-83 MC
0x2D:OVF
0x2E: MC0
Y
0x2F: MC1
0x30: MC2
0x31: MC3
DS40001882G-page 67
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DSU - Device Service Unit
13.
DSU - Device Service Unit
13.1
Overview
The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access
Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level
services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device
identification as well as identification of other debug components within the system. Hence, it complies with the ARM
Peripheral Identification specification. The DSU also provides system services to applications that need memory
testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a
debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU
features will be limited or unavailable when the device is protected by the NVMCTRL security bit.
Related Links
13.11.6 System Services Availability when Accessed Externally and Device is Protected
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.2
Features
•
•
•
•
•
•
•
•
CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
ARM CoreSight™ compliant device identification
®
Two debug communications channels
Debug access port security filter
Onboard memory built-in self-test (MBIST)
13.3
Block Diagram
Figure 13-1.ꢀDSU Block Diagram
DSU
debugger_present
RESET
SWCLK
DEBUGGER PROBE
INTERFACE
cpu_reset_extension
CPU
DBG
DAP
NVMCTRL
DAP SECURITY FILTER
CORESIGHT ROM
AHB-AP
PORT
M
S
CRC-32
MBIST
SWDIO
HIGH-SPEED
BUS MATRIX
M
CHIP ERASE
DS40001882G-page 68
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DSU - Device Service Unit
13.4
Signal Description
The DSU uses three signals to function.
Signal Name
RESET
Type
Description
Digital Input
Digital Input
Digital I/O
External reset
SW clock
SWCLK
SWDIO
SW bidirectional data pin
Related Links
7. I/O Multiplexing and Considerations
13.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
13.5.1 I/O Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU
reset phase. For more information, refer to 13.6.3 Debugger Probe Detection. The Hot-Plugging feature depends on
the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the
Hot-Plugging feature is disabled until a power-reset or an external reset is performed.
13.5.2 Power Management
The DSU will continue to operate in Idle mode.
Related Links
16. PM – Power Manager
13.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Power Manager.
Refer to PM – Power Manager
Related Links
16. PM – Power Manager
13.5.4 DMA
Not applicable.
13.5.5 Interrupts
Not applicable.
13.5.6 Events
Not applicable.
13.5.7 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
DS40001882G-page 69
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DSU - Device Service Unit
Related Links
11.6 Peripheral Access Controller (PAC)
13.5.8 Analog Connections
Not applicable.
13.6
Debug Operation
13.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor
debug resources:
•
•
CPU reset extension
Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification.
13.6.2 CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is
released. This ensures that the CPU is not executing code at startup while a debugger is connects to the system.
The debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled
up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the
reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To
release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to
STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU reset extension when
the device is protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the
Status A register (STATUSA.PERR).
Figure 13-2.ꢀTypical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
pin
DSU CRSTEXT
Clear
CPU reset
extension
reset
CPU_STATE
running
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.6.3 Debugger Probe Detection
13.6.3.1 Cold Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU
reset extension is requested, as described above.
DS40001882G-page 70
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DSU - Device Service Unit
13.6.3.2 Hot Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible
under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK
falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its
default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is
disabled until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the
Hot-Plugging Enable bit of the Status B register (STATUSB.HPE).
Figure 13-3.ꢀHot-Plugging Detection Timing Diagram
SWCLK
RESET pin
reset
CPU_STATE
running
Hot-Plugging
The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once
detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons,
Hot-Plugging is not available when the device is protected by the NVMCTRL security bit.
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until
POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the
external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the
user must retry the procedure above until it gets connected to the device.
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.7
Chip Erase
Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security
bit. Therefore, all volatile memories, the Flash memory (including the EEPROM Emulation area) and the RWWEE
Emulation section will be erased. The Flash auxiliary rows, including the user row, will not be erased.
When the device is protected, the debugger must first reset the device in order to be detected. This ensures that
internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a
'1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected
by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the
Flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register
(STATUSA.DONE).
The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For
that reason, it is recommended to issue a Chip-Erase after a Cold-Plugging procedure to ensure that the device is in
a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold-Plugging procedure (refer to 13.6.3.1 Cold Plugging), and the device performs these actions:
1.1.
1.2.
Detects the debugger probe.
Holds the CPU in reset.
2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then:
2.1. Clears the system volatile memories.
DS40001882G-page 71
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SAM D21/DA1 Family
DSU - Device Service Unit
2.2.
2.3.
Erases the whole Flash array (including the EEPROM Emulation area, not including auxiliary rows)
and the RWWEE Emulation section.
Erases the lock row, removing the NVMCTRL security bit protection.
3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
4. Reset the device to let the NVMCTRL update the fuses.
13.8
Programming
Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL
security bit. The programming procedure is as follows:
1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state
until the input supply is above the POR threshold (refer to Powe-On Reset (POR) characteristics). The system
continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus
Clocks that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Make
sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset.
Related Links
37. Electrical Characteristics at 85℃
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.9
Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device
is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed
by issuing a Chip-Erase (refer to 13.7 Chip Erase). When the device is protected, read/write accesses using the
AHB-AP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase,
sensitive information is erased from volatile memory and Flash.
The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected,
then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response
that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on
www.arm.com).
The DSU is intended to be accessed either:
•
•
Internally from the CPU, without any limitation, even when the device is protected
Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external
accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
•
•
The first 0x100 bytes form the internal address range
The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000.
The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate
accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region
0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 13-1.
DS40001882G-page 72
Complete Datasheet
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SAM D21/DA1 Family
DSU - Device Service Unit
Figure 13-4.ꢀAPB Memory Mapping
0x0000
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
DSU operating
registers
0x00FF
0x0100
Mirrored
DSU operating
registers
0x01FF
External address range
(can be accessed from debug tools with some restrictions)
Empty
0x1000
DSU CoreSight
ROM
0x1FFF
Some features not activated by APB transactions are not available when the device is protected:
Table 13-1.ꢀFeature Availability Under Protection
Features
Availability when the device is protected
CPU Reset Extension
Clear CPU Reset Extension
Debugger Cold-Plugging
Debugger Hot-Plugging
Yes
No
Yes
No
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.10 Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be
identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device.
13.10.1 CoreSight Identification
®
™
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight
ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
DS40001882G-page 73
Complete Datasheet
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SAM D21/DA1 Family
DSU - Device Service Unit
Figure 13-5.ꢀConceptual 64-bit Peripheral ID
Table 13-2.ꢀConceptual 64-Bit Peripheral ID Bit Descriptions
Field
Size Description
Location
PID4
JEP-106 CC code 4
Continuation code: 0x0
Device ID: 0x1F
JEP-106 ID code
4KB count
RevAnd
7
PID1+PID2
4
Indicates that the CoreSight component is a ROM: 0x0
Not used; read as 0
PID4
4
PID3
CUSMOD
4
Not used; read as 0
PID3
PARTNUM
REVISION
12
4
Contains 0xCD0 to indicate that DSU is present
PID0+PID1
PID2
DSU revision (starts at 0x0 and increments by 1 at both major and
minor revisions). Identifies DSU identification method variants. If 0x0, this
indicates that device identification can be completed by reading the Device
Identification register (DID)
For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
13.10.2 Chip Identification Method
The DSU DID register identifies the device by implementing the following information:
•
•
•
•
Processor identification
Product family identification
Product series identification
Device select
13.11 Functional Description
13.11.1 Principle of Operation
The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the
Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured
first; then a command can be issued by writing the Control register. When a command is ongoing, other commands
are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be
set prior to issuing another one.
13.11.2 Basic Operation
13.11.2.1 Initialization
The module is enabled by enabling its clocks. For more details, refer to 13.5.3 Clocks. The DSU registers can be
PAC write-protected.
Related Links
11.6 Peripheral Access Controller (PAC)
DS40001882G-page 74
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DSU - Device Service Unit
13.11.2.2 Operation From a Debug Adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is
protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to return an error. Refer
to 13.9 Intellectual Property Protection.
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.11.2.3 Operation From the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU
registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 13.9 Intellectual
Property Protection.
13.11.3 32-bit Cyclic Redundancy Check CRC32
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area
(including Flash and AHB RAM).
When the CRC32 command is issued from:
•
•
The internal range, the CRC32 can be operated at any memory location
The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see
below)
Table 13-3.ꢀAMOD Bit Descriptions when Operating CRC32
AMOD[1:0] Short name External range restrictions
0
ARRAY
CRC32 is restricted to the full Flash array area (EEPROM Emulation area not included)
DATA forced to 0xFFFFFFFF before calculation (no seed)
1
EEPROM
Reserved
CRC32 of the whole EEPROM Emulation area DATA forced to 0xFFFFFFFF before
calculation (no seed)
2-3
-
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
13.11.3.1 Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and
the size of the memory range into the Length register (LENGTH). Both must be word-aligned.
The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of
separate memory blocks.
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for
subsequent CRC32 calculations.
The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register
(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST).
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.11.3.2 Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the
Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.
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Complete Datasheet
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SAM D21/DA1 Family
DSU - Device Service Unit
13.11.4 Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake
logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The
registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug
mode. This enables the user to build a custom debug protocol using only these registers.
The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected,
however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and
the CPU is held under Reset).
Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new
value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers.
They are automatically set on write and cleared on read.
Note:ꢀ The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly,
DCC0 and DCC1 must not be used while performing MBIST operations.
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
13.11.5 Testing of On-Board Memories MBIST
The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test).
This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external
address range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued
when the device is protected, a protection error is reported in the Protection Error bit in the Status A register
(STATUSA.PERR).
1. Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect
a wide range of memory defects, while still keeping a linear run time. The algorithm is:
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
Write entire memory to '0', in any order.
Bit by bit read '0', write '1', in descending order.
Bit by bit read '1', write '0', read '0', write '1', in ascending order.
Bit by bit read '1', write '0', in ascending order.
Bit by bit read '0', write '1', read '1', write '0', in ascending order.
Read '0' from entire memory, in ascending order.
The specific implementation used as a run time which depends on the CPU clock frequency and the number of
bytes tested in the RAM. The detected faults are:
– Address decoder faults
– Stuck-at faults
– Transition faults
– Coupling faults
– Linked Coupling faults
2. Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size
of the memory into the Length register.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a
subset of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by
writing a '1' to CTRL.SWRST.
3. Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are two different modes:
– ADDR.AMOD=0: exit-on-error (default)
DS40001882G-page 76
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SAM D21/DA1 Family
DSU - Device Service Unit
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both
cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read
the DATA and ADDR registers to locate the fault.
– ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only
STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in
STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the
fault.
4. Locating Faults
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected
error. The position of the failing bit can be found by reading the following registers:
– ADDR: Address of the word containing the failing bit
– DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Figure 13-6.ꢀDATA bits Description When MBIST Operation Returns an Error
Bit
31
30
29
28
27
26
25
17
24
Bit
Bit
Bit
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
16
8
9
phase
2
1
0
bit_index
•
•
bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table.
Table 13-4.ꢀMBIST Operation Phases
Phase
Test actions
0
1
2
3
4
5
6
7
Write all bits to zero. This phase cannot fail.
Read '0', write '1', increment address
Read '1', write '0'
Read '0', write '1', decrement address
Read '1', write '0', decrement address
Read '0', write '1'
Read '1', write '0', decrement address
Read all zeros. bit_index is not used
Table 13-5.ꢀAMOD Bit Descriptions for MBIST
AMOD[1:0]
0x0
Description
Exit on Error
Pause on Error
0x1
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DSU - Device Service Unit
...........continued
AMOD[1:0]
Description
0x2, 0x3
Reserved
Related Links
22. Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
9. Product Mapping
13.11.6 System Services Availability when Accessed Externally and Device is Protected
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x000-0x100 range.
Table 13-6.ꢀAvailable Features when Operated From The External Address Range and Device is Protected
Features
Availability From The External Address Range and
Device is Protected
Chip-Erase command and status
CRC32
Yes
Yes, only full array or full RWWEE Emulation
CoreSight Compliant Device identification
Debug communication channels
Testing of onboard memories (MBIST)
STATUSA.CRSTEXT clearing
Yes
Yes
No
No (STATUSA.PERR is set when attempting to do so)
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DSU - Device Service Unit
13.12 Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
CTRL
7:0
7:0
7:0
CE
MBIST
FAIL
CRC
BERR
DCCD0
SWRST
DONE
PROT
STATUSA
STATUSB
Reserved
PERR
HPE
CRSTEXT
DBGPRES
DCCD1
7:0
15:8
23:16
31:24
7:0
ADDR[5:0]
AMOD[1:0]
ADDR[13:6]
0x04
0x08
0x0C
0x10
0x14
0x18
ADDR
LENGTH
DATA
ADDR[21:14]
ADDR[29:22]
LENGTH[5:0]
15:8
23:16
31:24
7:0
LENGTH[13:6]
LENGTH[21:14]
LENGTH[29:22]
DATA[7:0]
15:8
23:16
31:24
7:0
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
15:8
23:16
31:24
7:0
DATA[15:8]
DCC0
DATA[23:16]
DATA[31:24]
DATA[7:0]
15:8
23:16
31:24
7:0
DATA[15:8]
DCC1
DATA[23:16]
DATA[31:24]
DEVSEL[7:0]
15:8
23:16
31:24
DIE[3:0]
REVISION[3:0]
DID
FAMILY[0]
SERIES[5:0]
PROCESSOR[3:0]
FAMILY[4:1]
0x1C
...
Reserved
ENTRY0
0x0FFF
7:0
15:8
23:16
31:24
7:0
FMT
EPRES
EPRES
ADDOFF[3:0]
ADDOFF[3:0]
0x1000
0x1004
0x1008
ADDOFF[11:4]
ADDOFF[19:12]
FMT
15:8
23:16
31:24
7:0
ENTRY1
ADDOFF[11:4]
ADDOFF[19:12]
END[7:0]
15:8
23:16
31:24
END[15:8]
END
END[23:16]
END[31:24]
0x100C
...
Reserved
MEMTYPE
0x1FCB
7:0
SMEMP
15:8
0x1FCC
0x1FD0
23:16
31:24
7:0
FKBC[3:0]
JEPCC[3:0]
15:8
PID4
23:16
31:24
DS40001882G-page 79
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SAM D21/DA1 Family
DSU - Device Service Unit
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x1FD4
...
Reserved
0x1FDF
7:0
15:8
23:16
31:24
7:0
PARTNBL[7:0]
0x1FE0
0x1FE4
0x1FE8
0x1FEC
0x1FF0
0x1FF4
0x1FF8
0x1FFC
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
JEPIDCL[3:0]
PARTNBH[3:0]
15:8
23:16
31:24
7:0
REVISION[3:0]
REVAND[3:0]
JEPU
JEPIDCH[2:0]
15:8
23:16
31:24
7:0
CUSMOD[3:0]
15:8
23:16
31:24
7:0
PREAMBLEB0[7:0]
15:8
23:16
31:24
7:0
CCLASS[3:0]
PREAMBLE[3:0]
15:8
23:16
31:24
7:0
PREAMBLEB2[7:0]
PREAMBLEB3[7:0]
15:8
23:16
31:24
7:0
15:8
23:16
31:24
13.13 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 13.5.7 Register Access Protection.
DS40001882G-page 80
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DSU - Device Service Unit
13.13.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x0000
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
CE
W
0
3
MBIST
W
2
CRC
W
1
0
SWRST
Access
Reset
W
0
0
0
Bit 4 – CEꢀChip-Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the Chip-Erase operation.
Bit 3 – MBISTꢀMemory Built-In Self-Test
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the memory BIST algorithm.
Bit 2 – CRCꢀ32-bit Cyclic Redundancy Check
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the cyclic redundancy check algorithm.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the module.
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DSU - Device Service Unit
13.13.2 Status A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUSA
0x0001
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
PERR
R/W
0
3
2
BERR
R/W
0
1
CRSTEXT
R/W
0
DONE
R/W
0
FAIL
R/W
0
Access
Reset
0
Bit 4 – PERRꢀProtection Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
Bit 3 – FAILꢀFailure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 2 – BERRꢀBus Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Bit 1 – CRSTEXTꢀCPU Reset Phase Extension
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
Bit 0 – DONEꢀDone
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
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DSU - Device Service Unit
13.13.3 Status B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUSB
0x0002
0x1X
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
HPE
R
3
2
1
0
PROT
R
DCCD1
DCCD0
DBGPRES
Access
Reset
R
0
R
0
R
0
1
0
Bit 4 – HPEꢀHot-Plugging Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a
power-reset or a external reset can set it again.
Bits 2, 3 – DCCDxꢀDebug Communication Channel x Dirty [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
Bit 1 – DBGPRESꢀDebugger Present
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
Bit 0 – PROTꢀProtected
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set at power-up when the device is protected.
This bit is never cleared.
DS40001882G-page 83
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.4 Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x0004
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDR[29:22]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
ADDR[21:14]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
ADDR[13:6]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
ADDR[5:0]
AMOD[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:2 – ADDR[29:0]ꢀAddress
Initial word start address needed for memory operations.
Bits 1:0 – AMOD[1:0]ꢀAccess Mode
The functionality of these bits is dependent on the operation mode.
Bit description when operating CRC32: refer to 13.11.3 32-bit Cyclic Redundancy Check CRC32
Bit description when testing onboard memories (MBIST): refer to 13.11.5 Testing of On-Board Memories MBIST
DS40001882G-page 84
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.5 Length
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
LENGTH
0x0008
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
LENGTH[29:22]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
LENGTH[21:14]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
LENGTH[13:6]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
LENGTH[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:2 – LENGTH[29:0]ꢀLength
Length in words needed for memory operations.
DS40001882G-page 85
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.6 Data
Name:ꢀ
DATA
Offset:ꢀ
Reset:ꢀ
0x000C
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0]ꢀData
Memory operation initial value or result value.
DS40001882G-page 86
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.7 Debug Communication Channel 0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DCC0
0x0010
0x00000000
-
Property:ꢀ
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0]ꢀData
Data register.
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.8 Debug Communication Channel 1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DCC1
0x0014
0x00000000
-
Property:ꢀ
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0]ꢀData
Data register.
DS40001882G-page 88
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.9 Device Identification
Name:ꢀ
Offset:ꢀ
DID
0x0018
Property:ꢀ PAC Write Protection
The information in this register is related to the Ordering Information.
Bit
31
30
29
28
27
26
25
24
PROCESSOR[3:0]
FAMILY[4:1]
Access
Reset
R
p
R
p
R
p
R
p
R
f
R
f
R
f
R
f
Bit
23
22
21
20
19
18
17
16
FAMILY[0]
SERIES[5:0]
Access
Reset
R
f
R
s
R
s
R
s
R
s
R
s
R
s
Bit
15
14
13
12
11
10
9
8
DIE[3:0]
REVISION[3:0]
Access
Reset
R
d
R
d
R
d
R
d
R
r
R
R
r
R
r
r
Bit
7
6
5
4
3
2
1
0
DEVSEL[7:0]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bits 31:28 – PROCESSOR[3:0]ꢀProcessor
The value of this field defines the processor used on the device. For this device, the value of this field is 0x1,
corresponding to the ARM Cortex-M0+ processor.
Bits 27:23 – FAMILY[4:0]ꢀProduct Family
The value of this field corresponds to the product family part of the ordering code. For this device, the value of this
field is 0x0, corresponding to the SAM D family of base line microcontrollers.
Bits 21:16 – SERIES[5:0]ꢀProduct Series
The value of this field corresponds to the product series part of the ordering code. For this device, the value of this
field is 0x01, corresponding to a product with the Cortex-M0+ processor with DMA and USB features.
Bits 15:12 – DIE[3:0]ꢀDie Number
Identifies the die family.
Bits 11:8 – REVISION[3:0]ꢀRevision Number
Identifies the die revision number. Refer the product family silicon errata and data sheet clarification document for
further information.
Note:ꢀ The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of
the die.
Bits 7:0 – DEVSEL[7:0]ꢀDevice Selection
This bit field identifies a device within a product family and product series. The value corresponds to the Flash
memory density, pin count and device variant parts of the ordering code. The Family Silicon Device Identification
table in the “SAM D21/DA1 Family Silicon Errata” document provides the link between DEVSEL and part number.
DS40001882G-page 89
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.10 CoreSight ROM Table Entry 0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ENTRY0
0x1000
0xXXXXX00X
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDOFF[19:12]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
20
19
18
17
16
ADDOFF[11:4]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
3
10
9
8
ADDOFF[3:0]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
2
1
FMT
R
0
EPRES
Access
Reset
R
x
1
Bits 31:12 – ADDOFF[19:0]ꢀAddress Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMTꢀFormat
Always reads as '1', indicating a 32-bit ROM table.
Bit 0 – EPRESꢀEntry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
DS40001882G-page 90
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.11 CoreSight ROM Table Entry 1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ENTRY1
0x1004
0xXXXXX00X
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDOFF[19:12]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
20
19
18
17
16
ADDOFF[11:4]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
3
10
9
8
ADDOFF[3:0]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
2
1
FMT
R
0
EPRES
Access
Reset
R
x
1
Bits 31:12 – ADDOFF[19:0]ꢀAddress Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMTꢀFormat
Always read as '1', indicating a 32-bit ROM table.
Bit 0 – EPRESꢀEntry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
DS40001882G-page 91
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DSU - Device Service Unit
13.13.12 CoreSight ROM Table End
Name:ꢀ
END
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1008
0x00000000
-
Bit
31
30
29
28
27
26
25
24
END[31:24]
END[23:16]
END[15:8]
END[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 31:0 – END[31:0]ꢀEnd Marker
Indicates the end of the CoreSight ROM table entries.
DS40001882G-page 92
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.13 CoreSight ROM Table Memory Type
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
MEMTYPE
0x1FCC
0x0000000x
-
Property:ꢀ
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
SMEMP
Access
Reset
R
x
Bit 0 – SMEMPꢀSystem Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a
debug adapter.
This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a
debug adapter.
DS40001882G-page 93
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.14 Peripheral Identification 4
Name:ꢀ
PID4
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FD0
0x00000000
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
FKBC[3:0]
JEPCC[3:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 7:4 – FKBC[3:0]ꢀ4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB block.
Bits 3:0 – JEPCC[3:0]ꢀJEP-106 Continuation Code
These bits will always return zero when read.
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DSU - Device Service Unit
13.13.15 Peripheral Identification 0
Name:ꢀ
PID0
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FE0
0x00000000
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
PARTNBL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 7:0 – PARTNBL[7:0]ꢀPart Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance.
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DSU - Device Service Unit
13.13.16 Peripheral Identification 1
Name:ꢀ
PID1
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FE4
0x000000FC
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
JEPIDCL[3:0]
PARTNBH[3:0]
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
Bits 7:4 – JEPIDCL[3:0]ꢀLow part of the JEP-106 Identity Code
These bits will always return 0xF when read (JEP-106 identity code is 0x1F).
Bits 3:0 – PARTNBH[3:0]ꢀPart Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
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DSU - Device Service Unit
13.13.17 Peripheral Identification 2
Name:ꢀ
PID2
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FE8
0x00000009
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
3
JEPU
R
1
0
REVISION[3:0]
JEPIDCH[2:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
1
1
Bits 7:4 – REVISION[3:0]ꢀRevision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
Bit 3 – JEPUꢀJEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
Bits 2:0 – JEPIDCH[2:0]ꢀJEP-106 Identity Code High
These bits will always return 0x1 when read, (JEP-106 identity code is 0x1F).
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DSU - Device Service Unit
13.13.18 Peripheral Identification 3
Name:ꢀ
PID3
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FEC
0x00000000
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
REVAND[3:0]
CUSMOD[3:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 7:4 – REVAND[3:0]ꢀRevision Number
These bits will always return 0x0 when read.
Bits 3:0 – CUSMOD[3:0]ꢀARM CUSMOD
These bits will always return 0x0 when read.
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DSU - Device Service Unit
13.13.19 Component Identification 0
Name:ꢀ
CID0
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FF0
0x0000000D
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
PREAMBLEB0[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
1
Bits 7:0 – PREAMBLEB0[7:0]ꢀPreamble Byte 0
These bits will always return 0x0000000D when read.
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DSU - Device Service Unit
13.13.20 Component Identification 1
Name:ꢀ
CID1
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FF4
0x00000010
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
CCLASS[3:0]
PREAMBLE[3:0]
Access
Reset
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
Bits 7:4 – CCLASS[3:0]ꢀComponent Class
These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the
ARM Debug Interface v5 Architecture Specification at http://www.arm.com).
Bits 3:0 – PREAMBLE[3:0]ꢀPreamble
These bits will always return 0x00 when read.
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.21 Component Identification 2
Name:ꢀ
CID2
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FF8
0x00000005
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
PREAMBLEB2[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
1
R
0
R
1
Bits 7:0 – PREAMBLEB2[7:0]ꢀPreamble Byte 2
These bits will always return 0x00000005 when read.
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SAM D21/DA1 Family
DSU - Device Service Unit
13.13.22 Component Identification 3
Name:ꢀ
CID3
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x1FFC
0x000000B1
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
PREAMBLEB3[7:0]
Access
Reset
R
1
R
0
R
1
R
1
R
0
R
0
R
0
R
1
Bits 7:0 – PREAMBLEB3[7:0]ꢀPreamble Byte 3
These bits will always return 0x000000B1 when read.
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SAM D21/DA1 Family
Clock System
14.
Clock System
This chapter summarizes the clock distribution and terminology in the SAM D21 device. It will not explain every detail
of its configuration. For in-depth documentation, see the respective peripherals descriptions and the Generic Clock
documentation.
Related Links
15. GCLK - Generic Clock Controller
14.1
Clock Distribution
Figure 14-1.ꢀClock distribution
PM
Synchronous Clock
Controller
GCLK
SYSCTRL
GCLK_MAIN
GCLK Multiplexer 0
(DFLL48M Reference)
XOSC
OSCULP32K
OSC32K
GCLK Generator 0
GCLK Generator 1
GCLK Generator x
GCLK Multiplexer 1
GCLK Multiplexer y
Peripheral 0
XOSC32K
OSC8M
Generic
Clocks
Peripheral z
DFLL48M
FDPLL96M
AHB/APB System Clocks
The clock system on the SAM D21 consists of:
•
Clock sources, controlled by SYSCTRL
– A clock source provides a time base that is used by other components, such as Generic Clock Generators.
Example clock sources are the internal 8MHz oscillator (OSC8M), External crystal oscillator (XOSC) and
the Digital frequency locked loop (DFLL48M).
•
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
•
Generic Clock Generators: These are programmable prescalers that can use any of the system clock
sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is
used by the Power Manager, which in turn generates synchronous clocks.
•
Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the Generic
Clock Multiplexer, and serve as clocks for the peripherals of the system. Multiple instances of a peripheral
will typically have a separate Generic Clock for each instance. Generic Clock 0 serves as the clock source
for the DFLL48M clock input (when multiplying another clock source).
•
Power Manager (PM)
•
The PM generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks
(APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock
masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus
clocks.
The next figure shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M
is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel
20. The Generic Clock 20, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0
interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM.
DS40001882G-page 103
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SAM D21/DA1 Family
Clock System
Figure 14-2.ꢀExample of SERCOM clock
PM
Synchronous Clock
Controller
CLK_SERCOM0_APB
GCLK
SYSCTRL
Generic Clock
Multiplexer 20
Generic Clock
DFLL48M
GCLK_SERCOM0_CORE
SERCOM 0
Generator 1
14.2
Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be in different clock domains, i.e. they are clocked from different clock sources
and/or with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the
peripheral includes a SYNCBUSY status register that can be used to check if a sync operation is in progress.
For a general description, see 14.3 Register Synchronization. Some peripherals have specific properties described
in their individual sub-chapter “Synchronization”.
In the datasheet, references to Synchronous Clocks are referring to the CPU and bus clocks, while asynchronous
clocks are generated by the Generic Clock Controller (GCLK).
14.3
Register Synchronization
There are two different register synchronization schemes implemented on this device: common synchronizer register
synchronization and distributed synchronizer register synchronization.
The modules using a common synchronizer register synchronization are: GCLK, WDT, RTC, EIC, TC, ADC, AC and
DAC.
The modules adopting a distributed synchronizer register synchronization are: SERCOM USART, SERCOM SPI,
SERCOM I2C, I2S, TCC, USB.
14.3.1 Common Synchronizer Register Synchronization
14.3.1.1 Overview
All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a
corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock
(GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in hardware,
so the synchronization process takes place even if the peripheral generic clock is running from the same clock source
and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are
synchronized when written. Some registers in the peripheral core are synchronized when read. Each individual
register description will have the properties "Read-Synchronized" and/or "Write-Synchronized" if a register is
synchronized.
As shown in the figure below, the common synchronizer is used for all registers in one peripheral. Therefore, status
register (STATUS) of each peripheral can be synchronized at a time.
DS40001882G-page 104
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SAM D21/DA1 Family
Clock System
Figure 14-3.ꢀSynchronization
Synchronous Domain
(CLK_APB)
Asynchronous Domain
(generic clock)
Non Synced reg
Write-Synced reg
INTFLAG
STATUS
SYNCBUSY
Write-Synced reg
R/W-Synced reg
READREQ
14.3.1.2 Write-Synchronization
Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The Synchronization Busy
bit in the Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when
the write-synchronization is complete. Refer to 14.3.1.8 Synchronization Delay for details on the synchronization
delay.
When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the
peripheral bus to stall until the synchronization is complete:
•
•
•
Writing a generic clock peripheral core register
Reading a read-synchronized peripheral core register
Reading the register that is being written (and thus triggered the synchronization)
Peripheral core registers without read-synchronization will remain static once they have been written and
synchronized, and can be read while the synchronization is ongoing without causing the peripheral bus to stall.
APB registers can also be read while the synchronization is ongoing without causing the peripheral bus to stall.
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Clock System
14.3.1.3 Read-Synchronization
Reading a read-synchronized peripheral core register will cause the peripheral bus to stall immediately until the
read-synchronization is complete. STATUS.SYNCBUSY will not be set. Refer to 14.3.1.8 Synchronization Delay
for details on the synchronization delay. Note that reading a read-synchronized peripheral core register while
STATUS.SYNCBUSY is one will cause the peripheral bus to stall twice; first because of the ongoing synchronization,
and then again because reading a read-synchronized core register will cause the peripheral bus to stall immediately.
14.3.1.4 Completion of synchronization
The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when
the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next
operation will be started once the previous write/read operation is synchronized and/or complete.
14.3.1.5 Read Request
The read request functionality is only available to peripherals that have the Read Request register (READREQ)
implemented. Refer to the register description of individual peripheral chapters for details.
To avoid forcing the peripheral bus to stall when reading read-synchronized Peripheral Core registers, the read
request mechanism can be used.
Basic Read Request
Writing a '1' to the Read Request bit in the Read Request register (READREQ.RREQ) will request
read synchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and
set STATUS.SYNCBUSY. When read synchronization is complete, STATUS.SYNCBUSY is cleared. The read-
synchronized value is then available for reading without delay until READREQ.RREQ is written to '1' again.
The address to use is the offset to the peripheral's base address of the register that should be synchronized.
Continuous Read Request
Writing a '1' to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous read
synchronization of the register specified in READREQ.ADDR. The latest value is always available for reading
without stalling the bus, as the synchronization mechanism is continuously synchronizing the given value.
READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ
bit is required to be set once the RCONT bit is set.
SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another
synchronization is attempted, that is by executing a write-operation of a Write-synchronized register), the read
request will be stopped, and will have to be manually restarted.
Note:ꢀ
The continuous read synchronization is paused in sleep modes where the generic clock is not running. This means
that a new read request is required if the value is needed immediately after exiting sleep.
14.3.1.6 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation
Ready interrupt (if available) cannot be used for Enable write-synchronization.
When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following
will cause the peripheral bus to stall until the enable synchronization is complete:
•
•
•
Writing a peripheral core register
Writing an APB register
Reading a read-synchronized peripheral core register
APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to
stall.
14.3.1.7 Software Reset Write-Synchronization
Writing a '1' to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
STATUS.SYNCBUSY. When writing a '1' to the CTRL.SWRST bit it will immediately read as '1'. CTRL.SWRST
and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the
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Clock System
CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software
Reset write-synchronization.
When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are '1'), attempt to do any of the
following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete:
•
•
•
Writing a peripheral core register
Writing an APB register
Reading a read-synchronized register
APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to
stall.
14.3.1.8 Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of:
5 × P + 2 × P < D < 6 × P + 3 × P
GCLK
APB
GCLK
APB
Where P
is the period of the generic clock and P
is the period of the peripheral bus clock. A normal peripheral
GCLK
APB
bus register access duration is 2 × P
.
APB
14.3.2 Distributed Synchronizer Register Synchronization
14.3.2.1 Overview
All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a
corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock
(GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in hardware,
so the synchronization process takes place even if the peripheral generic clock is running from the same clock source
and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are
synchronized when written. Some registers in the peripheral core are synchronized when read. Registers that need
synchronization has this denoted in each individual register description.
14.3.2.2 General Write synchronization
Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The respective bit in the
Synchronization Busy register (SYNCBUSY) will be set when the write-synchronization starts and cleared when the
write-synchronization is complete. Refer to 14.3.2.7 Synchronization Delay for details on the synchronization delay.
When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded,
and an error will be reported.
Example:
REGA, REGB are 8-bit peripheral core registers. REGC is 16-bit peripheral core register.
Offset
0x00
0x01
0x02
0x03
Register
REGA
REGB
REGC
Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after REGA (8-bit
access) was written, REGB (8-bit access) can be written immediately without error.
REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit
accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated.
A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at
different times because of independent write synchronization.
DS40001882G-page 107
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SAM D21/DA1 Family
Clock System
14.3.2.3 General read synchronization
Read-synchronized registers are synchronized when the register value is updated. During synchronization the
corresponding bit in SYNCBUSY will be set. Reading a read-synchronized register will return its value immediately
and the corresponding bit in SYNCBUSY will not be set.
14.3.2.4 Completion of synchronization
In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the
Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing
synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'.
14.3.2.5 Enable Write-Synchronization
Setting the Enable bit in a module's Control register (CTRL.ENABLE) will also trigger write-synchronization and set
SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. SYNCBUSY.ENABLE
will be cleared by hardware when the operation is complete. The Synchronisation Ready interrupt (if available)
cannot be used for Enable write-synchronization.
14.3.2.6 Software Reset Write-Synchronization
Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’. CTRL.SWRST
and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a '0' to
the CTRL.SWRST bit has no effect. The Ready interrupt (if available) cannot be used for Software Reset write-
synchronization.
14.3.2.7 Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of:
5 × P
+ 2 × P
< D < 6 × P
+ 3 × P
GCLK
APB
GCLK APB
Where P
is the period of the generic clock and P
is the period of the peripheral bus clock. A normal peripheral
GCLK
APB
bus register access duration is 2 × P
.
APB
14.4
Enabling a Peripheral
In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be
configured:
•
•
A running Clock Source.
A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the
Generator must be enabled.
•
•
The Generic Clock Multiplexer that provides the Generic Clock signal to the peripheral must be configured to
use a running Generic Clock Generator, and the Generic Clock must be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers
will read all 0’s and any writing attempts to the peripheral will be discarded.
14.5
Disabling a Peripheral
When disabling a peripheral and if a pin change interrupt is enabled on pins driven by the respective peripheral, a
wake condition may be generated. If this happen the interrupt flag will not be set. As a consequence the system will
not be able to identify the wake source. To avoid this, the interrupt enable register of the peripheral must be cleared
(or the Nested Vectored Interrupt Controller (NVIC) Enable for the peripheral must be cleared) before disabling the
peripheral.
DS40001882G-page 108
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SAM D21/DA1 Family
Clock System
14.6
On-demand, Clock Requests
Figure 14-4.ꢀClock request routing
Clock request
Clock request
Clock request
Generic Clock
Generator
Generic Clock
Multiplexer
Peripheral
DFLL48M
ENABLE
GENEN
CLKEN
ENABLE
RUNSTDBY
ONDEMAND
RUNSTDBY
RUNSTDBY
All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state unless a
peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as
the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until
requested again.
The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic
Clock Generator in-between are enabled. The time taken from a clock request being asserted to the clock source
being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in
the Generic Clock Generator. The total startup time Tstart from a clock request until the clock is available for the
peripheral is between:
Tstart_max = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods
Tstart_min = Clock source startup time + 1 × clock source period + 1 × divided clock source period
The time between the last active clock request stopped and the clock is shut down, Tstop, is between:
Tstop_min = 1 × divided clock source period + 1 × clock source period
Tstop_max = 2 × divided clock source periods + 2 × clock source periods
The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND bit located
in each clock source controller. Consequently, the clock will always run whatever the clock request status is. This has
the effect of removing the clock source startup time at the cost of power consumption.
The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits of the
modules, see Figure 14-4.
14.7
14.8
Power Consumption vs. Speed
When targeting for either a low-power or a fast acting system, some considerations have to be taken into account
due to the nature of the asynchronous clocking of the peripherals:
If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the
same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed,
and will take longer with a slower peripheral clock. This will cause worse response times and longer synchronization
delays.
Clocks after Reset
On any reset the synchronous clocks start to their initial state:
•
•
•
OSC8M is enabled and divided by 8
Generic Generator 0 uses OSC8M as source and generates GCLK_MAIN
CPU and BUS clocks are undivided
On a Power Reset, the GCLK module starts to its initial state:
All Generic Clock Generators are disabled except
•
DS40001882G-page 109
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SAM D21/DA1 Family
Clock System
– Generator 0 is using OSC8M as source without division and generates GCLK_MAIN
– Generator 2 uses OSCULP32K as source without division
All Generic Clocks are disabled except:
•
– WDT Generic Clock uses the Generator 2 as source
On a User Reset the GCLK module starts to its initial state, except for:
•
Generic Clocks that are write-locked , i.e., the according WRTLOCK is set to 1 prior to Reset or WDT Generic
Clock if the WDT Always-On at power on bit set in the NVM User Row
•
Generic Clock is dedicated to the RTC if the RTC Generic Clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by
a power reset.
DS40001882G-page 110
Complete Datasheet
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.
GCLK - Generic Clock Controller
15.1
Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic
Clock controller GCLK provides nine Generic Clock Generators that can provide a wide range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each Generator can
be divided. The outputs from the Generators are used as sources for the Generic Clock Multiplexers, which provide
the Generic Clock (GCLK_PERIPHERAL) to the peripheral modules, as shown in Generic Clock Controller Block
Diagram. The number of Peripheral Clocks depends on how many peripherals the device has.
Note:ꢀ The Generator 0 is always the direct source of the GCLK_MAIN signal.
15.2
15.3
Features
•
•
•
Provides Generic Clocks
Wide frequency range
Clock source for the generator can be changed on the fly
Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPHERAL) and the Main Clock (GCLK_MAIN) can be seen in
the figure below.
Figure 15-1.ꢀDevice Clocking Diagram
GENERIC CLOCK CONTROLLER
SYSCTRL
Generic Clock Generator
XOSC
OSCULP32K
Generic Clock Multiplexer
OSC32K
GCLK_PERIPHERAL
XOSC32K
OSC8M
Clock
Divider &
Masker
Clock
Gate
PERIPHERALS
DFLL48M
GCLK_IO
GCLK_MAIN
PM
The GCLK block diagram is shown in the next figure.
DS40001882G-page 111
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
Figure 15-2.ꢀGeneric Clock Controller Block Diagram(1)
Generic Clock Generator 0
GCLK_MAIN
GCLK_IO[0]
Clock Sources
GCLKGEN[0]
Clock
Divider &
Masker
(I/O output)
Generic Clock Multiplexer 0
GCLK_IO[0]
(I/O input)
GCLK_PERIPHERAL[0]
Clock
Gate
GCLK_IO[1]
(I/O output)
Generic Clock Generator 1
Generic Clock Multiplexer 1
Clock
Divider &
Masker
GCLKGEN[1]
GCLK_IO[1]
(I/O input)
GCLK_PERIPHERAL[1]
Clock
Gate
Generic Clock Generator n
GCLK_IO[n]
(I/O output)
Clock
Divider &
Masker
GCLKGEN[n]
Generic Clock Multiplexer m
GCLK_IO[n]
(I/O input)
GCLK_PERIPHERAL[m]
Clock
Gate
GCLKGEN[n:0]
Note:ꢀ 1. If GENCTRL.SRC=0x01(GCLKIN), the GCLK_IO is set as an input.
15.4
Signal Description
Table 15-1.ꢀSignal Description
Signal Name
Type
Description
GCLK_IO[7:0]
Digital I/O
Clock source for Generators when input
Generic Clock signal when output
Refer to PORT Function Multiplexing table in I/O Multiplexing and Considerations for details on the pin mapping for
this peripheral.
Note:ꢀ One signal can be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
15.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
15.5.1 I/O Lines
Using the GCLK I/O lines requires the I/O pins to be configured.
Related Links
23. PORT - I/O Pin Controller
15.5.2 Power Management
The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power Manager (PM)
section.
DS40001882G-page 112
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
Related Links
16. PM – Power Manager
15.5.3 Clocks
The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_GCLK_APB can be found in the Peripheral Clock Masking section of PM – Power Manager.
Related Links
16. PM – Power Manager
15.5.4 DMA
Not applicable.
15.5.5 Interrupts
Not applicable.
15.5.6 Events
Not applicable.
15.5.7 Debug Operation
Not applicable.
15.5.8 Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC).
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
15.5.9 Analog Connections
Not applicable.
15.6
Functional Description
15.6.1 Principle of Operation
The GCLK module is comprised of eight Generic Clock Generators (Generators) sourcing m Generic Clock
Multiplexers.
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator.
A generator output is used as input to one or more the Generic Clock Multiplexers to provide a peripheral
(GCLK_PERIPHERAL). A generic clock can act as the clock to one or several of peripherals.
15.6.2 Basic Operation
15.6.2.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be
configured as outlined by the following steps:
1. The Generic Clock Generator division factor must be set by performing a single 32-bit write to the Generic
Clock Generator Division register (GENDIV):
– The Generic Clock Generator that will be selected as the source of the generic clock by setting the ID bit
group (GENDIV.ID).
DS40001882G-page 113
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
– The division factor must be selected by the DIV bit group (GENDIV.DIV)
Note:ꢀ Refer to Generic Clock Generator Division register (GENDIV) for details.
2. The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock
Generator Control register (GENCTRL):
– The Generic Clock Generator will be selected as the source of the generic clock by the ID bit group
(GENCTRL.ID)
– The Generic Clock generator must be enabled (GENCTRL.GENEN=1)
Note:ꢀ Refer to Generic Clock Generator Control register (GENCTRL) for details.
3. The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register
(CLKCTRL):
– The Generic Clock that will be configured via the ID bit group (CLKCTRL.ID)
– The Generic Clock Generator used as the source of the generic clock by writing the GEN bit group
(CLKCTRL.GEN)
Note:ꢀ Refer to Generic Clock Control register (CLKCTRL) for details.
Related Links
15.8.5 GENDIV
15.8.4 GENCTRL
15.8.3 CLKCTRL
15.6.2.2 Enabling, Disabling and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by setting the Software Reset bit in the Control register (CTRL.SWRST) to 1. All registers in the
GCLK will be reset to their initial state, except for Generic Clocks Multiplexer and associated Generators that have
their Write Lock bit set to 1 (CLKCTRL.WRTLOCK). For further details, refer to 15.6.3.4 Configuration Lock.
15.6.2.3 Generic Clock Generator
Each Generator (GCLK_GEN) can be set to run from one of eight different clock sources except GCLKGEN[1], which
can be set to run from one of seven sources. GCLKGEN[1] is the only Generator that can be selected as source to
other Generators but can not act as source to itself.
Each generator GCLKGEN[x] can be connected to one specific pin GCLK_IO[x]. The GCLK_IO[x] can be set to act
as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x].
The selected source can be divided. Each Generator can be enabled or disabled independently.
Each GCLKGEN clock signal can then be used as clock source for Generic Clock Multiplexers. Each Generator
output is allocated to one or several Peripherals.
GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager.
Refer to PM-Power Manager for details on the synchronous clock generation.
Figure 15-3.ꢀGeneric Clock Generator
GCLKGENSRC
Clock Sources
0
GCLKGENSRC
GCLKGEN[x]
Clock
Gate
DIVIDER
1
GCLK_IO[x]
GENCTRL.GENEN
GENCTRL.DIVSEL
GENDIV.DIV
GENCTRL.SRC
Related Links
16. PM – Power Manager
DS40001882G-page 114
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.6.2.4 Enabling a Generic Clock Generator
A Generator is enabled by setting the Generic Clock Generator Enable bit in the Generic Clock Generator Control
register (GENCTRL.GENEN=1).
15.6.2.5 Disabling a Generic Clock Generator
A Generator is disabled by clearing GENCTRL.GENEN. When GENCTRL.GENEN=0, the GCLKGEN clock is
disabled and clock gated.
15.6.2.6 Selecting a Clock Source for the Generic Clock Generator
Each Generator can individually select a clock source by setting the Source Select bit group in GENCTRL
(GENCTRL.SRC).
Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source
B is not ready, the Generator will continue running with clock source A. As soon as clock source B is ready, however,
the generic clock generator will switch to it. During the switching operation, the Generator holds clock requests to
clock sources A and B and then releases the clock source A request when the switch is done.
The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL).
Only GCLKGEN[1] can be used as a common source for all other generators except Generator 1.
Note:ꢀ Before switching the Generic Clock Generator 0 (GCLKGEN0) from a clock source A to another clock source
B, enable the "ONDEMAND" feature of the clock source A to ensure a proper transition from clock source A to clock
source B.
15.6.2.7 Changing Clock Frequency
The selected source (GENCLKSRC) for a Generator can be divided by writing a division value in the Division Factor
bit group in the Generic Clock Generator Division register (GENDIV.DIV). How the actual division factor is calculated
is depending on the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it can be interpreted in two ways by the
integer divider.
Note:ꢀ The number of DIV bits for each Generator is device dependent.
15.6.2.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing the Improve Duty Cycle bit
in GENCTRL (GENCTRL.IDC=1) will result in a 50/50 duty cycle.
15.6.2.9 Generic Clock Output on I/O Pins
Each Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL is '1'
(GENCTRL.OE=1) and the Generator is enabled (GENCTRL.GENEN=1), the Generator requests its clock source
and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE=0, GCLK_IO is set according to the Output
Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.OOV) is zero, the output clock will be low when
generic clock generator is turned off. If GENCTRL.OOV=1, the output clock will be high when Generator is turned off.
In standby mode, if the clock is output (GENCTRL.OE=1), the clock on the GCLK_IO pin is frozen to the OOV value
if the Run In Standby bit in GENCTRL (GENCTRL.RUNSTDBY) is zero. If GENCTRL.RUNSTDBY=1, the GCLKGEN
clock is kept running and output to GCLK_IO.
DS40001882G-page 115
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.6.3 Generic Clock
Figure 15-4.ꢀGeneric Clock Multiplexer
GCLKGEN[0]
GCLKGEN[1]
GCLKGEN[2]
Clock
Gate
GCLK_PERIPHERAL
GCLKGEN[n]
CLKCTRL.CLKEN
CLKCTRL.GEN
15.6.3.1 Enabling a Generic Clock
Before a generic clock is enabled, one of the Generators must be selected as the source for the generic clock by
writing to CLKCTRL.GEN. The clock source selection is individually set for each generic clock.
When a Generator has been selected, the generic clock is enabled by setting the Clock Enable bit in
CLKCTRL (CLKCTRL.CLKEN=1). The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain.
CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete.
15.6.3.2 Disabling a Generic Clock
A generic clock is disabled by writing CLKCTRL.CLKEN=0. The SYNCBUSY bit will be cleared when this write-
synchronization is complete. CLKCTRL.CLKEN will stay in its previous state until the synchronization is complete.
The generic clock is gated when disabled.
15.6.3.3 Selecting a Clock Source for the Generic Clock
When changing a generic clock source by writing to CLKCTRL.GEN, the generic clock must be disabled before being
re-enabled with the new clock source setting. This prevents glitches during the transition:
1. Write CLKCTRL.CLKEN=0
2. Assert that CLKCTRL.CLKEN reads '0'
3. Change the source of the generic clock by writing CLKCTRL.GEN
4. Re-enable the generic clock by writing CLKCTRL.CLKEN=1
15.6.3.4 Configuration Lock
The generic clock configuration can be locked for further write accesses by setting the Write Lock bit in the CLKCTRL
register (CLKCTRL.WRTLOCK). All writes to the CLKCTRL register will be ignored. It can only be unlocked by a
Power Reset.
The Generator source of a locked generic clock are also locked, too: The corresponding GENCTRL and GENDIV are
locked, and can be unlocked only by a Power Reset.
There is one exception concerning the GCLKGEN[0]. As it is used as GCLK_MAIN, it can not be locked. It is reset by
any Reset and will start up in a known configuration. The software reset (CTRL.SWRST) can not unlock the registers.
15.6.4 Additional Features
15.6.4.1 Indirect Access
The Generic Clock Generator Control and Division registers (GENCTRL and GENDIV) and the Generic Clock Control
register (CLKCTRL) are indirectly addressed as shown in the next figure.
DS40001882G-page 116
Complete Datasheet
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
Figure 15-5.ꢀGCLK Indirect Access
User Interface
GENCTRL
GENDIV
Generic Clock Generator [i]
GENCTRL.ID=i
GENDIV.ID=i
GENCTRL
GENDIV
Generic Clock[j]
CLKCTRL
CLKCTRL.ID=j
CLKCTRL
Writing these registers is done by setting the corresponding ID bit group. To read a register, the user must write the
ID of the channel, i, in the corresponding register. The value of the register for the corresponding ID is available in the
user interface by a read access.
For example, the sequence to read the GENCTRL register of generic clock generator i is:
1. Do an 8-bit write of the i value to GENCTRL.ID
2. Read the value of GENCTRL
15.6.4.2 Generic Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That
means that the configuration of the Generators and generic clocks after Reset is device-dependent.
Refer to GENCTRL.ID for details on GENCTRL reset.
Refer to GENDIV.ID for details on GENDIV reset.
Refer to CLKCTRL.ID for details on CLKCTRL reset.
Related Links
15.8.5 GENDIV
15.8.4 GENCTRL
15.8.3 CLKCTRL
15.6.5 Sleep Mode Operation
15.6.5.1 Sleep Walking
The GCLK module supports the Sleep Walking feature. If the system is in a sleep mode where the Generic Clocks
are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock
Controller.
The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which
clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and
generic clock stages successively, and delivers the clock to the peripheral.
15.6.5.2 Run in Standby Mode
In standby mode, the GCLK can continuously output the generator output to GCLK_IO.
When set, the GCLK can continuously output the generator output to GCLK_IO.
Refer to 15.6.2.9 Generic Clock Output on I/O Pins for details.
15.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
DS40001882G-page 117
Complete Datasheet
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers are synchronized when written:
•
•
•
Generic Clock Generator Control register (GENCTRL)
Generic Clock Generator Division register (GENDIV)
Control register (CTRL)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 118
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
CTRL
7:0
7:0
SWRST
STATUS
SYNCBUSY
WRTLOCK
7:0
ID[5:0]
0x02
CLKCTRL
GENCTRL
15:8
7:0
CLKEN
GEN[3:0]
ID[3:0]
15:8
23:16
31:24
7:0
SRC[4:0]
OOV
0x04
RUNSTDBY
DIVSEL
OE
IDC
GENEN
ID[3:0]
15:8
23:16
31:24
DIV[7:0]
DIV[15:8]
0x08
GENDIV
15.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Refer to 15.5.8 Register Access Protection for details.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
Refer to 15.6.6 Synchronization for details.
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Complete Datasheet
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SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x0
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
SWRST
R/W
0
Access
Reset
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic
clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to GENCTRL.ID for details on GENCTRL reset.
Refer to GENDIV.ID for details on GENDIV reset.
Refer to CLKCTRL.ID for details on CLKCTRL reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
Description
0
1
There is no reset operation ongoing.
There is a reset operation ongoing.
DS40001882G-page 120
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.8.2 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x1
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
DS40001882G-page 121
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.8.3 Generic Clock Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CLKCTRL
0x2
0x0000
Property:ꢀ Write-Protected
Bit
15
WRTLOCK
R/W
14
CLKEN
R/W
0
13
5
12
4
11
10
9
8
GEN[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
6
3
2
1
0
ID[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – WRTLOCKꢀWrite Lock
When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic clock
generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can only be
unlocked by a Power Reset.
One exception to this is generic clock generator 0, which cannot be locked.
Value
Description
0
1
The generic clock and the associated generic clock generator and division factor are not locked
The generic clock and the associated generic clock generator and division factor are locked
Bit 14 – CLKENꢀClock Enable
This bit is used to enable and disable a generic clock.
Value
Description
0
1
The generic clock is disabled
The generic clock is enabled
Bits 11:8 – GEN[3:0]ꢀGeneric Clock Generator
These bits define the Generic Clock Generator which will be associated with the peripheral GCLK clock defined in the
CLKCTRL.ID.
Table 15-2.ꢀGeneric Clock Generator
GEN[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
GCLKGEN0
GCLKGEN1
GCLKGEN2
GCLKGEN3
GCLKGEN4
GCLKGEN5
GCLKGEN6
GCLKGEN7
GCLKGEN8
-
Generic clock generator 0
Generic clock generator 1
Generic clock generator 2
Generic clock generator 3
Generic clock generator 4
Generic clock generator 5
Generic clock generator 6
Generic clock generator 7
Generic clock generator 8
Reserved
0x8
0x9-0xF
Bits 5:0 – ID[5:0]ꢀGeneric Clock Selection ID
These bits select the peripheral GCLK clock which will be associated with the Generic Clock Generator defined in the
CLKCTRL.GEN. The third table below provides the ID number for each possible peripheral GCLK clock..
A Power Reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the
corresponding ID is zero and the ID is not the RTC, a user Reset will reset the CLKCTRL register for this ID.
After a Power Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the next table.
DS40001882G-page 122
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
Table 15-3.ꢀCLKCTRL Value after Power Reset for each Peripheral GCLK clock ID
Module Instance
Reset Value after Power Reset
CLKCTRL.GEN
CLKCTRL.CLKEN
0x00
0x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero
0x00
CLKCTRL.WRTLOCK
RTC (ID = 0x04)
WDT (ID = 0x03)
0x00
0x02
0x00
0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero
0x00
Others
0x00
After a user Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the table below.
Table 15-4.ꢀCLKCTRL Value after User Reset for each Peripheral GCLK clock ID
Module Instance Reset Value after a User Reset
CLKCTRL.GEN
CLCTRL.CLKEN
CLKCTRL.WRTLOCK
RTC (ID = 0x04) 0x00 if WRTLOCK=0 and
CLKEN=0
0x00 if WRTLOCK=0 and CLKEN=0
No change if WRTLOCK=1 or CLKEN=1
No change
No change if WRTLOCK=1
or CLKEN=1
WDT (ID = 0x03) 0x02 if WRTLOCK=0
No change if WRTLOCK=1
If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no change
No change
No change
Others
0x00 if WRTLOCK=0
0x00 if WRTLOCK=0
No change if WRTLOCK=1 No change if WRTLOCK=1
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Name
GCLK_DFLL48M_REF
GCLK_DPLL
GCLK_DPLL_32K
GCLK_WDT
GCLK_RTC
GCLK_EIC
GCLK_USB
GCLK_EVSYS_CHANNEL_0
GCLK_EVSYS_CHANNEL_1
GCLK_EVSYS_CHANNEL_2
GCLK_EVSYS_CHANNEL_3
GCLK_EVSYS_CHANNEL_4
GCLK_EVSYS_CHANNEL_5
GCLK_EVSYS_CHANNEL_6
GCLK_EVSYS_CHANNEL_7
GCLK_EVSYS_CHANNEL_8
GCLK_EVSYS_CHANNEL_9
GCLK_EVSYS_CHANNEL_10
GCLK_EVSYS_CHANNEL_11
GCLK_SERCOMx_SLOW
GCLK_SERCOM0_CORE
GCLK_SERCOM1_CORE
GCLK_SERCOM2_CORE
GCLK_SERCOM3_CORE
GCLK_SERCOM4_CORE
Description
DFLL48M Reference
FDPLL96M input clock source for reference
FDPLL96M 32 kHz clock for FDPLL96M internal lock timer
WDT
RTC
EIC
USB
EVSYS_CHANNEL_0
EVSYS_CHANNEL_1
EVSYS_CHANNEL_2
EVSYS_CHANNEL_3
EVSYS_CHANNEL_4
EVSYS_CHANNEL_5
EVSYS_CHANNEL_6
EVSYS_CHANNEL_7
EVSYS_CHANNEL_8
EVSYS_CHANNEL_9
EVSYS_CHANNEL_10
EVSYS_CHANNEL_11
SERCOMx_SLOW
SERCOM0_CORE
SERCOM1_CORE
SERCOM2_CORE
SERCOM3_CORE
SERCOM4_CORE
DS40001882G-page 123
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
Value
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26-0x3
F
Name
Description
SERCOM5_CORE
TCC0,TCC1
TCC2,TC3
TC4,TC5
TC6,TC7
ADC
AC_DIG, AC1_DIG
AC_ANA, AC1_ANA
DAC
GCLK_SERCOM5_CORE
GCLK_TCC0, GCLK_TCC1
GCLK_TCC2, GCLK_TC3
GCLK_TC4, GCLK_TC5
GCLK_TC6, GCLK_TC7
GCLK_ADC
GCLK_AC_DIG, GCLK_AC1_DIG
GCLK_AC_ANA, GCLK_AC1_ANA
GCLK_DAC
GCLK_PTC
GCLK_I2S_0
GCLK_I2S_1
GCLK_TCC3
PTC
I2S_0
I2S_1
TCC3
-
Reserved
DS40001882G-page 124
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.8.4 Generic Clock Generator Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
GENCTRL
0x4
0x00000000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
31
23
15
7
30
22
14
6
29
28
27
26
25
24
Access
Reset
Bit
21
RUNSTDBY
R/W
20
DIVSEL
R/W
0
19
OE
R/W
0
18
OOV
R/W
0
17
IDC
R/W
0
16
GENEN
R/W
0
Access
Reset
0
Bit
13
12
11
10
SRC[4:0]
R/W
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
5
4
3
2
1
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 21 – RUNSTDBYꢀRun in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if a
peripheral requires the clock.
Value
Description
0
The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be
dependent on the setting in GENCTRL.OOV.
1
The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby
mode.
Bit 20 – DIVSELꢀDivide Selection
This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock source
should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding generic clock
generator must be zero or one.
Value
Description
0
1
The generic clock generator equals the clock source divided by GENDIV.DIV.
The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).
Bit 19 – OEꢀOutput Enable
This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in
the GENCLK.SRC bit group.
Value
Description
0
The generic clock generator is not output.
1
The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding
GCLK_IO is selected as a source in the GENCLK.SRC bit group.
Bit 18 – OOVꢀOutput Off Value
This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit
group.
DS40001882G-page 125
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
Value
Description
0
1
The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero.
The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero.
Bit 17 – IDCꢀImprove Duty Cycle
This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used.
Value
Description
0
1
The generic clock generator duty cycle is not 50/50 for odd division factors.
The generic clock generator duty cycle is 50/50.
Bit 16 – GENENꢀGeneric Clock Generator Enable
This bit is used to enable and disable the generic clock generator.
Value
Description
0
1
The generic clock generator is disabled.
The generic clock generator is enabled.
Bits 12:8 – SRC[4:0]ꢀSource Select
These bits define the clock source to be used as the source for the generic clock generator, as shown in the table
below.
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09-0x1
F
Name
XOSC
GCLKIN
Description
XOSC oscillator output
Generator input pad
Generic clock generator 1 output
OSCULP32K oscillator output
OSC32K oscillator output
XOSC32K oscillator output
OSC8M oscillator output
DFLL48M output
GCLKGEN1
OSCULP32K
OSC32K
XOSC32K
OSC8M
DFLL48M
FDPLL96M
Reserved
FDPLL96M output
Reserved for future use
Bits 3:0 – ID[3:0]ꢀGeneric Clock Generator Selection
These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus
which generic clock generator is configured is shown in the next table.
A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source
of the RTC generic clock, a user reset will reset the GENCTRL for this ID.
After a power reset, the reset value of the GENCTRL register is as shown in the next table.
GCLK Generator ID
Reset Value after a Power Reset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x00010600
0x00000001
0x00010302
0x00000003
0x00000004
0x00000005
0x00000006
0x00000007
0x00000008
After a user reset, the reset value of the GENCTRL register is as shown in the table below.
GCLK Generator Reset Value after a User Reset
ID
0x00
0x00010600
DS40001882G-page 126
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
...........continued
GCLK Generator Reset Value after a User Reset
ID
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
Description
GCLKGEN0
GCLKGEN1
GCLKGEN2
GCLKGEN3
GCLKGEN4
GCLKGEN5
GCLKGEN6
GCLKGEN7
GCLKGEN8
Reserved
Generic clock generator 0
Generic clock generator 1
Generic clock generator 2
Generic clock generator 3
Generic clock generator 4
Generic clock generator 5
Generic clock generator 6
Generic clock generator 7
Generic clock generator 8
0x8
0x9-0xF
DS40001882G-page 127
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
15.8.5 Generic Clock Generator Division
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
GENDIV
0x8
0x00000000
Property:ꢀ Write-Synchronized
Bit
31
30
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
DIV[15:8]
DIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:8 – DIV[15:0]ꢀDivision Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has can
be seen in the next table. Writes to bits above the specified number will be ignored.
Generator
Division Factor Bits
Maximum Division Factor
Generic clock generator 0
Generic clock generator 1
Generic clock generators 2
Generic clock generators 3 - 8
8 division factor bits - DIV[7:0]
16 division factor bits - DIV[15:0]
5 division factor bits - DIV[4:0]
8 division factor bits - DIV[7:0]
512
131072
64
512
Bits 3:0 – ID[3:0]ꢀGeneric Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in the table below.
Values
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Generic clock generator 0
Generic clock generator 1
Generic clock generator 2
Generic clock generator 3
Generic clock generator 4
Generic clock generator 5
Generic clock generator 6
Generic clock generator 7
Generic clock generator 8
Reserved
0x8
0x9-0xF
A Power Reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source
of the RTC generic clock, a user Reset will reset the GENDIV register for this ID.
After a Power Reset, the Reset value of the GENDIV register is as shown in the table below.
DS40001882G-page 128
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
GCLK - Generic Clock Controller
GCLK Generator ID
Reset Value after a Power Reset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x00000000
0x00000001
0x00000002
0x00000003
0x00000004
0x00000005
0x00000006
0x00000007
0x00000008
After a user Reset, the Reset value of the GENDIV register is as shown in next table.
GCLK Generator Reset Value after a User Reset
ID
0x00
0x01
0x00000000
0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000002 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x02
0x03
0x04
0x05
0x06
0x07
0x08
DS40001882G-page 129
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PM – Power Manager
16.
PM – Power Manager
16.1
Overview
The Power Manager (PM) controls the reset, clock generation and sleep modes of the device.
Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides
synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous
system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx.
Any synchronous system clock can be changed at run-time during normal operation. The clock domains can run at
different speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while
maintaining high CPU performance. In addition, the clock can be masked for individual modules, enabling the user to
minimize power consumption.
Before entering the Stand-by Sleep mode the user must make sure that a significant amount of clocks and
peripherals are disabled, so that the voltage regulator is not overloaded. This is because during Stand-by Sleep
mode the internal voltage regulator will be in Low-Power mode.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop
unused modules in order to save power. In active mode, the CPU is executing application code. When the device
enters a Sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the Sleep mode. The application code decides which Sleep mode to enter and
when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a Sleep mode to
Active mode.
The PM also contains a reset controller to collect all possible reset sources. It issues a device reset and sets the
device to its initial state, and allows the reset source to be identified by software.
16.2
Features
•
•
•
Reset control
– Reset the microcontroller and set it to an initial state according to the reset source
– Multiple reset sources
•
•
Power reset sources: POR, BOD12, BOD33
User reset sources: External reset (RESET), Watchdog Timer reset, software reset
– Reset status register for reading the reset source from the application code
Clock control
– Controls CPU, AHB and APB system clocks
•
•
Multiple clock sources and division factor from GCLK
Clock prescaler with 1x to 128x division
– Safe run-time clock switching from GCLK
– Module-level clock gating through maskable peripheral clocks
Power management control
– Sleep modes: IDLE, STANDBY
– SleepWalking support on GCLK clocks
DS40001882G-page 130
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PM – Power Manager
16.3
Block Diagram
Figure 16-1.ꢀPM Block Diagram
POWER MANAGER
CLK_APB
CLK_AHB
CLK_CPU
SYNCHRONOUS
CLOCK CONTROLLER
PERIPHERALS
CPU
GCLK
SLEEP MODE
CONTROLLER
BOD12
BOD33
USER RESET
POWER RESET
POR
RESET
CONTROLLER
WDT
CPU
RESET
RESET SOURCES
16.4
Signal Description
Signal Name
Type
Description
External reset
RESET
Digital input
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
16.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
16.5.1 I/O Lines
Not applicable.
16.5.2 Power Management
Not applicable.
DS40001882G-page 131
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PM – Power Manager
16.5.3 Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_PM_APB can be found in Peripheral Clock Default State table in the Peripheral Clock Masking section. If this
clock is disabled in the Power Manager, it can only be re-enabled by a reset.
A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is
configured by default in the Generic Clock Controller, and can be reconfigured by the user if needed. Refer to
GCLK – Generic Clock Controller for details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
16.5.3.1 Main Clock
The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit
prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.
16.5.3.2 CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.
16.5.3.3 AHB Clock
The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is
always synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned
off. A clock gate is inserted from the common AHB clock to any AHB clock of a peripheral.
16.5.3.4 APBx Clocks
The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx
clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU
clock is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx
bus.
16.5.4 DMA
Not applicable.
16.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt
Controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
16.5.6 Events
Not applicable.
16.5.7 Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks
generated from the PM are kept running to allow the debugger accessing any modules. As a consequence, power
measurements are not possible in debug mode.
16.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
Interrupt Flag register (INTFLAG).
Reset Cause register (RCAUSE).
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to PAC – Peripheral Access
Controller for details.
DS40001882G-page 132
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PM – Power Manager
Related Links
11.6 Peripheral Access Controller (PAC)
16.5.9 Analog Connections
Not applicable.
16.6
Functional Description
16.6.1 Principle of Operation
16.6.1.1 Synchronous Clocks
The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the
synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of
the derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU ≥ fAPBx
.
The synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for
each module in each synchronous clock domain can be individually masked to avoid power consumption in inactive
modules. Depending on the sleep mode, some clock domains can be turned off (see Table 16-4).
16.6.1.2 Reset Controller
The Reset Controller collects the various reset sources and generates reset for the device. The device contains a
Power-on-Reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for
external reset circuitry to guarantee stable operation when powering up the device.
16.6.1.3 Sleep Mode Controller
In Active mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep
Mode Controller allows the user to choose between different sleep modes depending on application requirements, to
save power (see Table 16-4).
16.6.2 Basic Operation
16.6.2.1 Initialization
After a Power-on Reset (POR), the PM is enabled and the Reset Cause register indicates the POR source
(RCAUSE.POR). The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts
running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is in
the Active mode.
By default, only the necessary clocks are enabled (see Table 16-1).
16.6.2.2 Enabling, Disabling and Resetting
The PM module is always enabled and can not be reset.
16.6.2.3 Selecting the Main Clock Source
Refer to GCLK – Generic Clock Controller for details on how to configure the main clock source.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the
synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by
writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock
frequency determined by this equation:
f
main
CPUDIV
f
=
CPU
2
Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure
correct operation, frequencies must be selected so that fCPU ≥ fAPBx. Also, frequencies must never exceed the
specified maximum frequency for each clock domain.
DS40001882G-page 133
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PM – Power Manager
Note:ꢀ The AHB clock is always equal to the CPU clock.
CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and
APBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to
keep one or more clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the
required performance, while keeping the APBx frequency constant.
Figure 16-2.ꢀSynchronous Clock Selection and Prescaler
Sleep mode
Sleep Controller
APBCMASK
CLK_PERIPHERAL_APBC_n
CLK_PERIPHERAL_APBC_1
CLK_PERIPHERAL_APBC_0
Clock
gate
Clock
gate
CLK_APBC
APBCDIV
APBBDIV
APBADIV
APBBMASK
CLK_APBB
CLK_PERIPHERAL_APBB_n
CLK_PERIPHERAL_APBB_1
CLK_PERIPHERAL_APBB_0
Cc
Clock
gate
Clock
gate
APBAMASK
CLK_PERIPHERAL_APBA_n
CLK_PERIPHERAL_APBA_1
CLK_PERIPHERAL_APBA_0
Clock
CLK_APBA
Clock
gate
GCLK_MAIN
gate
GCLK
CLK_MAIN
AHBMASK
CLK_AHB
CLK_PERIPHERAL_AHB_n
CLK_PERIPHERAL_AHB_1
CLK_PERIPHERAL_AHB_0
Clock
gate
Clock
gate
CLK_CPU
Clock
gate
Prescaler
CPUDIV
16.6.2.5 Clock Ready Flag
There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read
as zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when
the new clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become
unstable or hang.
16.6.2.6 Peripheral Clock Masking
It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the
corresponding bit in the Clock Mask register (APBxMASK) to zero or one. Refer to the table below for the default
state of each of the peripheral clocks.
Table 16-1.ꢀPeripheral Clock Default State
Peripheral Clock
CLK_PAC0_APB
CLK_PM_APB
Default State
Enabled
Enabled
CLK_SYSCTRL_APB
CLK_GCLK_APB
CLK_WDT_APB
Enabled
Enabled
Enabled
DS40001882G-page 134
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PM – Power Manager
...........continued
Peripheral Clock
Default State
CLK_RTC_APB
CLK_EIC_APB
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
CLK_PAC1_APB
CLK_DSU_APB
CLK_NVMCTRL_APB
CLK_PORT_APB
CLK_HMATRIX_APB
CLK_PAC2_APB
CLK_SERCOMx_APB
CLK_TCx_APB
CLK_ADC_APB
CLK_ACx_APB
CLK_DAC_APB
CLK_PTC_APB
CLK_USB_APB
CLK_DMAC_APB
CLK_TCCx_APB
CLK_I2S_APB
When the APB clock for a module is not provided its registers cannot be read or written. The module can be
re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several
mask bits.
Note:ꢀ Clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for
the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching
off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will
make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.
16.6.2.7 Reset Controller
The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to
determine proper action.
There are two groups of reset sources:
•
•
Power Reset: Resets caused by an electrical issue.
User Reset: Resets caused by the application.
The table below lists the parts of the device that are reset, depending on the reset type.
DS40001882G-page 135
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PM – Power Manager
Table 16-2.ꢀEffects of the Different Reset Events
Power Reset
User Reset
POR, BOD12, BOD33 External Reset WDT Reset, SysResetReq
RTC
Y
N
N
All the 32kHz sources
WDT with ALWAYSON feature
Generic Clock with WRTLOCK feature
Debug logic
Others
Y
Y
Y
Y
N
Y
The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need
to be driven externally during normal operation.
The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller
Interface (SYSCTRL).
The WDT reset is generated by the Watchdog Timer.
The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the
®
®
SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM Cortex Technical Reference
Manual on http://www.arm.com).
Figure 16-3.ꢀReset Controller
RTC
RESET CONTROLLER
32kHz clock sources
WDT with ALWAYSON
Generic Clock with
WRTLOCK
BOD12
BOD33
POR
Debug Logic
RESET
WDT
CPU
Others
RCAUSE
RESET SOURCES
16.6.2.8 Sleep Mode Controller
Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register
(SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to
select the level of the sleep mode.
There are two main types of sleep mode:
•
IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the
IDLE argument. Regulator operates in normal mode.
DS40001882G-page 136
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SAM D21/DA1 Family
PM – Power Manager
•
STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator
operates in low-power mode. Before entering standby mode the user must make sure that a significant amount
of clocks and peripherals are disabled, so that the voltage regulator is not overloaded.
Table 16-3.ꢀSleep Mode Entry and Exit Table
Mode
Level
Mode Entry
Wake-Up Sources
IDLE
0
1
2
SCR.SLEEPDEEP = 0
SLEEP.IDLE=Level
WFI
Synchronous(2) (APB, AHB), asynchronous(1)
Synchronous (APB), asynchronous
Asynchronous
STANDBY
SCR.SLEEPDEEP = 1
WFI
Asynchronous
Notes:ꢀ
1. Asynchronous: interrupt generated on generic clock or external clock or external event.
2. Synchronous: interrupt generated on the APB clock.
Table 16-4.ꢀSleep Mode Overview
Sleep
Mode
CPU
AHB
APB
Oscillators
ONDEMAND = 0
RUNSTDBY=0
Run
Main
Regulator
Mode
RAM
Clock
Clock
Clock
Clock
Mode
ONDEMAND = 1
RUNSTDBY=0
Run if requested
Run if requested
Run if requested
Stop
RUNSTDBY=1
RUNSTDBY=1
Run if requested
Run if requested
Run if requested
Run if requested
Idle 0
Stop
Stop
Stop
Stop
Run
Stop
Stop
Stop
Run
Run
Stop
Stop
Run
Run
Run
Run
Run
Run
Run
Stop
Normal
Normal
Idle 1
Run
Normal
Normal
Idle 2
Run
Normal
Normal
Standby
Stop
Low power
Low power
16.6.2.8.1 IDLE Mode
The IDLE modes allow power optimization with the fastest wake-up time.
The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock
sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the bit settings of the mask
registers in the Power Manager (PM.AHBMASK, PM.APBxMASK).
Regulator operates in normal mode.
•
Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered
when the CPU exits the lowest priority ISR. This mechanism can be useful for applications that only require the
processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the IDLE
mode configuration bit group and must write a zero to the SCR.SLEEPDEEP bit.
•
Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is
not masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the
ACTIVE mode. The CPU and affected modules are restarted.
16.6.2.8.2 STANDBY Mode
The STANDBY mode allows achieving very low-power consumption.
In this mode, all clocks are stopped except those which are kept running if requested by a running module or have
the ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode. In this case, its generic clock
clock source will also be enabled.
The regulator and the RAM operate in Low-Power mode and the RAM content is retained.
A SLEEPONEXIT feature is also available.
•
Entering STANDBY mode: This mode is entered by executing the WFI instruction with the SCR.SLEEPDEEP bit
of the CPU is written to 1.
DS40001882G-page 137
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PM – Power Manager
•
Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake-up the system.
For example, a module running on a generic clock can trigger an interrupt. When the enabled asynchronous
wake-up event occurs and the system is woken up, the device will either execute the Interrupt Service Routine
or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of
the CPU.
16.6.3 SleepWalking
SleepWalking is the capability for a device to temporarily wake-up clocks for the peripheral to perform a task
without waking-up the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be
awakened by an interrupt (from a peripheral involved in SleepWalking) or enter into STANDBY sleep mode again.
In this device, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock
sources. Refer to On-demand, Clock Requests for more details.
Related Links
14.6 On-demand, Clock Requests
16.6.4 DMA Operation
Not applicable.
16.6.5 Interrupts
The peripheral has the following interrupt sources:
•
Clock Ready flag
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. Refer to Nested Vector Interrupt Controller for details.
If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG
register to determine which interrupt condition is present.
Related Links
11.2 Nested Vector Interrupt Controller
16.6.6 Events
Not applicable.
16.6.7 Sleep Mode Operation
In all IDLE sleep modes, the power manager is still running on the selected main clock.
In STANDDBY sleep mode, the power manager is frozen and is able to go back to ACTIVE mode upon any
asynchronous interrupt.
DS40001882G-page 138
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PM – Power Manager
16.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
...
CTRL
7:0
7:0
SLEEP
IDLE[1:0]
Reserved
0x07
0x08
0x09
0x0A
0x0B
0x0C
...
CPUSEL
APBASEL
APBBSEL
APBCSEL
7:0
7:0
7:0
7:0
CPUDIV[2:0]
APBADIV[2:0]
APBBDIV[2:0]
APBCDIV[2:0]
Reserved
0x13
7:0
15:8
23:16
31:24
7:0
USB
EIC
DMAC
RTC
NVMCTRL
WDT
DSU
GCLK
PORT
HPB2
HPB1
PM
HPB0
PAC0
PAC1
0x14
0x18
0x1C
0x20
AHBMASK
SYSCTRL
NVMCTRL
15:8
23:16
31:24
7:0
APBAMASK
APBBMASK
USB
DMAC
DSU
15:8
23:16
31:24
7:0
SERCOM5
TC7
SERCOM4
TC6
SERCOM3
TC5
SERCOM2
TC4
SERCOM1
TC3
SERCOM0
TCC2
EVSYS
TCC1
AC
PAC2
TCC0
ADC
15:8
23:16
31:24
APBCMASK
Reserved
AC1
I2S
PTC
DAC
TCC3
0x24
...
0x33
0x34
0x35
0x36
0x37
0x38
INTENCLR
INTENSET
INTFLAG
Reserved
RCAUSE
7:0
7:0
7:0
CKRDY
CKRDY
CKRDY
7:0
SYST
WDT
EXT
BOD33
BOD12
POR
16.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
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16.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
Access
Reset
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PM – Power Manager
16.8.2 Sleep Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SLEEP
0x01
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
IDLE[1:0]
Access
Reset
R/W
0
R/W
0
Bits 1:0 – IDLE[1:0]ꢀIdle Mode Configuration
These bits select the Idle mode configuration after a WFI instruction.
IDLE[1:0]
Name
Description
0x0
0x1
0x2
0x3
CPU
AHB
APB
The CPU clock domain is stopped
The CPU and AHB clock domains are stopped
The CPU, AHB and APB clock domains are stopped
Reserved
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PM – Power Manager
16.8.3 CPU Clock Select
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CPUSEL
0x08
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
CPUDIV[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 2:0 – CPUDIV[2:0]ꢀCPU Prescaler Selection
These bits define the division ratio of the main clock prescaler (2n).
CPUDIV[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
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16.8.4 APBA Clock Select
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBASEL
0x09
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
APBADIV[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 2:0 – APBADIV[2:0]ꢀAPBA Prescaler Selection
These bits define the division ratio of the APBA clock prescaler (2n).
APBADIV[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
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16.8.5 APBB Clock Select
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBBSEL
0x0A
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
APBBDIV[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 2:0 – APBBDIV[2:0]ꢀAPBB Prescaler Selection
These bits define the division ratio of the APBB clock prescaler (2n).
APBBDIV[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
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16.8.6 APBC Clock Select
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBCSEL
0x0B
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
APBCDIV[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 2:0 – APBCDIV[2:0]ꢀAPBC Prescaler Selection
These bits define the division ratio of the APBC clock prescaler (2n).
APBCDIV[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
DS40001882G-page 145
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PM – Power Manager
16.8.7 AHB Mask
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
AHBMASK
0x14
0x0000007F
Property:ꢀ Write-Protected
Bit
31
23
15
7
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
6
5
DMAC
R/W
1
4
NVMCTRL
R/W
3
2
HPB2
R/W
1
1
HPB1
R/W
1
0
HPB0
R/W
1
USB
R/W
1
DSU
R/W
1
Access
Reset
1
Bit 6 – USBꢀUSB AHB Clock Mask
Value
Description
0
1
The AHB clock for the USB is stopped.
The AHB clock for the USB is enabled.
Bit 5 – DMACꢀDMAC AHB Clock Mask
Value
Description
0
1
The AHB clock for the DMAC is stopped.
The AHB clock for the DMAC is enabled.
Bit 4 – NVMCTRLꢀNVMCTRL AHB Clock Mask
Value
Description
0
1
The AHB clock for the NVMCTRL is stopped.
The AHB clock for the NVMCTRL is enabled.
Bit 3 – DSUꢀDSU AHB Clock Mask
Value
Description
0
1
The AHB clock for the DSU is stopped.
The AHB clock for the DSU is enabled.
Bit 2 – HPB2ꢀHPB2 AHB Clock Mask
Value
Description
0
1
The AHB clock for the HPB2 is stopped.
The AHB clock for the HPB2 is enabled.
Bit 1 – HPB1ꢀHPB1 AHB Clock Mask
Value
Description
0
1
The AHB clock for the HPB1 is stopped.
The AHB clock for the HPB1 is enabled.
DS40001882G-page 146
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PM – Power Manager
Bit 0 – HPB0ꢀHPB0 AHB Clock Mask
Value
Description
0
1
The AHB clock for the HPB0 is stopped.
The AHB clock for the HPB0 is enabled.
DS40001882G-page 147
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PM – Power Manager
16.8.8 APBA Mask
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBAMASK
0x18
0x0000007F
Property:ꢀ Write-Protected
Bit
31
23
15
7
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
6
EIC
R/W
1
5
4
WDT
R/W
1
3
GCLK
R/W
1
2
SYSCTRL
R/W
1
PM
R/W
1
0
PAC0
R/W
1
RTC
R/W
1
Access
Reset
1
Bit 6 – EICꢀEIC APB Clock Enable
Value
Description
0
1
The APBA clock for the EIC is stopped.
The APBA clock for the EIC is enabled.
Bit 5 – RTCꢀRTC APB Clock Enable
Value
Description
0
1
The APBA clock for the RTC is stopped.
The APBA clock for the RTC is enabled.
Bit 4 – WDTꢀWDT APB Clock Enable
Value
Description
0
1
The APBA clock for the WDT is stopped.
The APBA clock for the WDT is enabled.
Bit 3 – GCLKꢀGCLK APB Clock Enable
Value
Description
0
1
The APBA clock for the GCLK is stopped.
The APBA clock for the GCLK is enabled.
Bit 2 – SYSCTRLꢀSYSCTRL APB Clock Enable
Value
Description
0
1
The APBA clock for the SYSCTRL is stopped.
The APBA clock for the SYSCTRL is enabled.
Bit 1 – PMꢀPM APB Clock Enable
Value
Description
0
1
The APBA clock for the PM is stopped.
The APBA clock for the PM is enabled.
DS40001882G-page 148
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SAM D21/DA1 Family
PM – Power Manager
Bit 0 – PAC0ꢀPAC0 APB Clock Enable
Value
Description
0
1
The APBA clock for the PAC0 is stopped.
The APBA clock for the PAC0 is enabled.
DS40001882G-page 149
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SAM D21/DA1 Family
PM – Power Manager
16.8.9 APBB Mask
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBBMASK
0x1C
0x0000007F
Property:ꢀ Write-Protected
Bit
31
23
15
7
30
22
14
6
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
5
4
DMAC
R/W
1
3
PORT
R/W
1
2
NVMCTRL
R/W
1
0
PAC1
R/W
1
USB
R/W
1
DSU
R/W
1
Access
Reset
1
Bit 5 – USBꢀUSB APB Clock Enable
Value
Description
0
1
The APBB clock for the USB is stopped.
The APBB clock for the USB is enabled.
Bit 4 – DMACꢀDMAC APB Clock Enable
Value
Description
0
1
The APBB clock for the DMAC is stopped.
The APBB clock for the DMAC is enabled.
Bit 3 – PORTꢀPORT APB Clock Enable
Value
Description
0
1
The APBB clock for the PORT is stopped.
The APBB clock for the PORT is enabled.
Bit 2 – NVMCTRLꢀNVMCTRL APB Clock Enable
Value
Description
0
1
The APBB clock for the NVMCTRL is stopped.
The APBB clock for the NVMCTRL is enabled.
Bit 1 – DSUꢀDSU APB Clock Enable
Value
Description
0
1
The APBB clock for the DSU is stopped.
The APBB clock for the DSU is enabled.
Bit 0 – PAC1ꢀPAC1 APB Clock Enable
Value
Description
0
1
The APBB clock for the PAC1 is stopped.
The APBB clock for the PAC1 is enabled.
DS40001882G-page 150
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SAM D21/DA1 Family
PM – Power Manager
16.8.10 APBC Mask
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
APBCMASK
0x20
0x00010000
Property:ꢀ Write-Protected
Bit
31
30
29
28
27
26
25
24
TCC3
R/W
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
AC1
R/W
0
20
I2S
R/W
0
19
PTC
R/W
0
18
DAC
R/W
0
17
AC
R/W
0
16
ADC
R/W
1
Access
Reset
R
0
R
0
Bit
15
TC7
R/W
0
14
TC6
R/W
0
13
TC5
R/W
0
12
TC4
R/W
0
11
TC3
R/W
0
10
TCC2
R/W
0
9
TCC1
R/W
0
8
TCC0
R/W
0
Access
Reset
Bit
7
SERCOM5
R/W
6
SERCOM4
R/W
5
SERCOM3
R/W
4
SERCOM2
R/W
3
SERCOM1
R/W
2
SERCOM0
R/W
1
EVSYS
R/W
0
0
PAC2
R/W
0
Access
Reset
0
0
0
0
0
0
Bit 24 – TCC3ꢀTCC2 APB Clock Enable
Value
Description
0
1
The APBC clock for the TCC3 is stopped
The APBC clock for the TCC3 is enabled
Bit 21 – AC1ꢀAC1 APB Clock Enable
Value
Description
0
1
The APBC clock for the AC1 is stopped
The APBC clock for the AC1 is enabled
Bit 20 – I2SꢀI2S APB Clock Enable
Value
Description
0
1
The APBC clock for the I2S is stopped
The APBC clock for the I2S is enabled
Bit 19 – PTCꢀPTC APB Clock Enable
Value
Description
0
1
The APBC clock for the PTC is stopped
The APBC clock for the PTC is enabled
Bit 18 – DACꢀDAC APB Clock Enable
Value
Description
0
1
The APBC clock for the DAC is stopped
The APBC clock for the DAC is enabled
Bit 17 – ACꢀAC APB Clock Enable
Value
Description
0
The APBC clock for the AC is stopped
DS40001882G-page 151
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SAM D21/DA1 Family
PM – Power Manager
Value
Description
1
The APBC clock for the AC is enabled
Bit 16 – ADCꢀADC APB Clock Enable
Value
Description
0
1
The APBC clock for the ADC is stopped
The APBC clock for the ADC is enabled
Bit 15 – TC7ꢀTC7 APB Clock Enable
Value
Description
0
1
The APBC clock for the TC7 is stopped
The APBC clock for the TC7 is enabled
Bit 14 – TC6ꢀTC6 APB Clock Enable
Value
Description
0
1
The APBC clock for the TC6 is stopped
The APBC clock for the TC6 is enabled
Bit 13 – TC5ꢀTC5 APB Clock Enable
Value
Description
0
1
The APBC clock for the TC5 is stopped
The APBC clock for the TC5 is enabled
Bit 12 – TC4ꢀTC4 APB Clock Enable
Value
Description
0
1
The APBC clock for the TC4 is stopped
The APBC clock for the TC4 is enabled
Bit 11 – TC3ꢀTC3 APB Clock Enable
Value
Description
0
1
The APBC clock for the TC3 is stopped
The APBC clock for the TC3 is enabled
Bit 10 – TCC2ꢀTCC2 APB Clock Enable
Value
Description
0
1
The APBC clock for the TCC2 is stopped
The APBC clock for the TCC2 is enabled
Bit 9 – TCC1ꢀTCC1 APB Clock Enable
Value
Description
0
1
The APBC clock for the TCC1 is stopped
The APBC clock for the TCC1 is enabled
Bit 8 – TCC0ꢀTCC0 APB Clock Enable
Value
Description
0
1
The APBC clock for the TCC0 is stopped
The APBC clock for the TCC0 is enabled
Bit 7 – SERCOM5ꢀSERCOM5 APB Clock Enable
Value
Description
0
1
The APBC clock for the SERCOM5 is stopped
The APBC clock for the SERCOM5 is enabled
Bit 6 – SERCOM4ꢀSERCOM4 APB Clock Enable
Value
Description
0
The APBC clock for the SERCOM4 is stopped
DS40001882G-page 152
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SAM D21/DA1 Family
PM – Power Manager
Value
Description
1
The APBC clock for the SERCOM4 is enabled
Bit 5 – SERCOM3ꢀSERCOM3 APB Clock Enable
Value
Description
0
1
The APBC clock for the SERCOM3 is stopped
The APBC clock for the SERCOM3 is enabled
Bit 4 – SERCOM2ꢀSERCOM2 APB Clock Enable
Value
Description
0
1
The APBC clock for the SERCOM2 is stopped
The APBC clock for the SERCOM2 is enabled
Bit 3 – SERCOM1ꢀSERCOM1 APB Clock Enable
Value
Description
0
1
The APBC clock for the SERCOM1 is stopped
The APBC clock for the SERCOM1 is enabled
Bit 2 – SERCOM0ꢀSERCOM0 APB Clock Enable
Value
Description
0
1
The APBC clock for the SERCOM0 is stopped
The APBC clock for the SERCOM0 is enabled
Bit 1 – EVSYSꢀEVSYS APB Clock Enable
Value
Description
0
1
The APBC clock for the EVSYS is stopped
The APBC clock for the EVSYS is enabled
Bit 0 – PAC2ꢀPAC2 APB Clock Enable
Value
Description
0
1
The APBC clock for the PAC2 is stopped
The APBC clock for the PAC2 is enabled
DS40001882G-page 153
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SAM D21/DA1 Family
PM – Power Manager
16.8.11 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x34
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
CKRDY
R/W
0
Access
Reset
Bit 0 – CKRDYꢀClock Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready
Interrupt flag is set.
DS40001882G-page 154
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SAM D21/DA1 Family
PM – Power Manager
16.8.12 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x35
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
CKRDY
R/W
0
Access
Reset
Bit 0 – CKRDYꢀClock Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
Value
Description
0
1
The Clock Ready interrupt is disabled.
The Clock Ready interrupt is enabled.
DS40001882G-page 155
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SAM D21/DA1 Family
PM – Power Manager
16.8.13 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x36
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
CKRDY
R/W
0
Access
Reset
Bit 0 – CKRDYꢀClock Ready
This flag is cleared by writing a one to the flag.
This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and
APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Clock Ready Interrupt flag.
DS40001882G-page 156
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SAM D21/DA1 Family
PM – Power Manager
16.8.14 Reset Cause
Name:ꢀ
RCAUSE
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x38
0x01
-
Bit
7
6
SYST
R
5
WDT
R
4
EXT
R
3
2
1
0
POR
R
BOD33
BOD12
Access
Reset
R
0
R
0
0
0
0
1
Bit 6 – SYSTꢀSystem Reset Request
This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more
details.
Bit 5 – WDTꢀWatchdog Reset
This flag is set if a Watchdog Timer reset occurs.
Bit 4 – EXTꢀExternal Reset
This flag is set if an external reset occurs.
Bit 2 – BOD33ꢀBrown Out 33 Detector Reset
This flag is set if a BOD33 reset occurs.
Bit 1 – BOD12ꢀBrown Out 12 Detector Reset
This flag is set if a BOD12 reset occurs.
Bit 0 – PORꢀPower On Reset
This flag is set if a POR occurs.
DS40001882G-page 157
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SAM D21/DA1 Family
SYSCTRL – System Controller
17.
SYSCTRL – System Controller
17.1
Overview
The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip
voltage regulator and voltage reference of the device.
Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals.
All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR). They can additionally
trigger interrupts upon status changes through the INTENSET (INTENSET), INTENCLR (INTENCLR) and INTFLAG
(INTFLAG) registers.
Additionally, BOD33 interrupts can be used to wake up the device from Stand-by mode upon a programmed brown-
out detection.
17.2
Features
•
0.4-32 MHz Crystal Oscillator (XOSC)
– Tunable gain control
– Programmable start-up time
– Crystal or external input clock on XIN I/O
32.768 kHz Crystal Oscillator (XOSC32K)
– Automatic or manual gain control
•
– Programmable start-up time
– Crystal or external input clock on XIN32 I/O
32.768 kHz High Accuracy Internal Oscillator (OSC32K)
– Frequency fine tuning
•
•
– Programmable start-up time
32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K)
– Ultra low-power, always-on oscillator
– Frequency fine tuning
– Calibration value loaded from Flash Factory Calibration at Reset
8 MHz Internal Oscillator (OSC8M)
•
•
•
– Fast start-up
– Output frequency fine tuning
– 4/2/1 MHz divided output frequencies available
– Calibration value loaded from Flash Factory Calibration at Reset
Digital Frequency Locked Loop (DFLL48M)
– Internal oscillator with no external components
– 48 MHz output frequency
– Operates standalone as a high-frequency programmable oscillator in Open-Loop mode
– Operates as an accurate frequency multiplier against a known frequency in Closed-Loop mode
Fractional Digital Phase-Locked Loop (FDPLL96M)
– 48 MHz to 96 MHz output clock frequency
– 32 kHz to 2 MHz input reference clock frequency range
– Three possible sources for the reference clock
– Adjustable proportional integral controller
– Fractional part used to achieve 1/16th of reference clock step
3.3V Brown-Out Detector (BOD33)
•
– Programmable threshold
DS40001882G-page 158
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
– Threshold value loaded from Flash User Calibration at start-up
– Triggers Resets or interrupts
– Hysteresis
•
•
Internal Voltage Regulator system (VREG)
– Operating modes:
•
•
Normal mode
Low-power mode
– With an internal non-configurable Brown-out Detector (BOD12)
Voltage Reference System (VREF)
– Bandgap voltage generator with programmable calibration value
– Temperature sensor
– Bandgap calibration value loaded from Flash Factory Calibration at start-up
17.3
Block Diagram
Figure 17-1.ꢀSYSCTRL Block Diagram
SYSCTRL
XOSC
XOSC32K
OSC32K
OSCILLATORS
OSCULP32K
CONTROL
OSC8M
DFLL48M
FDPLL96M
POWER
MONITOR
CONTROL
BOD33
VOLTAGE
REFERENCE
CONTROL
VOLTAGE
REFERENCE
SYSTEM
STATUS
(PCLKSR register)
INTERRUPTS
GENERATOR
Interrupts
17.4
Signal Description
Signal Name
XIN
Types
Description
Analog Input
Analog Output
Analog Input
Multipurpose Crystal Oscillator or external clock generator input
External Multipurpose Crystal Oscillator output
32kHz Crystal Oscillator or external clock generator input
XOUT
XIN32
DS40001882G-page 159
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SAM D21/DA1 Family
SYSCTRL – System Controller
...........continued
Signal Name
Types
Description
XOUT32
Analog Output
32kHz Crystal Oscillator output
The I/O lines are automatically selected when XOSC or XOSC32K are enabled. Refer to Oscillator Pinout.
Related Links
7. I/O Multiplexing and Considerations
17.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1 I/O Lines
I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration.
17.5.2 Power Management
The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The
SYSCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations
in the system without exiting sleep modes. Refer to PM – Power Manager on the different sleep modes.
Related Links
16. PM – Power Manager
17.5.3 Clocks
The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller
(GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M and
FDPLL96M.
The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the PM – Power Manager.
The clock used by BOD33 in Sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB).
Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the
user interface clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require
synchronization between the clock domains. Refer to 17.6.14 Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
17.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the
Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
17.5.5 Debug Operation
When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in
a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data
loss may result during debugging.
If debugger cold-plugging is detected by the system, BOD33 reset will be masked. The BOD resets keep running
under hot-plugging. This allows to correct a BOD33 user level too high for the available supply.
17.5.6 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
DS40001882G-page 160
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
•
Interrupt Flag Status and Clear register (INTFLAG)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
17.5.7 Analog Connections
When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz
crystal must be connected between the XIN and XOUT pins, along with any required load capacitors. For details on
recommended oscillator characteristics and capacitor load, refer to the Electrical Characteristics for details.
Related Links
37. Electrical Characteristics at 85℃
17.6
Functional Description
17.6.1 Principle of Operation
XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M, BOD33, and VREF are configured
through SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their
calibration values updated.
The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by
the SYSCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system
from Standby mode, provided the corresponding interrupt is enabled.
The oscillator must be enabled to run. The oscillator is enabled by writing a one to the ENABLE bit in the respective
oscillator control register, and disabled by writing a zero to the oscillator control register. In Idle mode, the default
operation of the oscillator is to run only when requested by a peripheral. In Standby mode, the default operation of
the oscillator is to stop. This behavior can be changed by the user, see below for details.
The behavior of the oscillators in the different sleep modes is shown in the table below.
Table 17-1.ꢀBehavior of the Oscillators
Oscillator
XOSC
Idle 0, 1, 2
Standby
Stop
Run on request
Run on request
Run on request
Run
XOSC32K
OSC32K
Stop
Stop
OSCULP32K
OSC8M
Run
Run on request
Run on request
Run on request
Stop
DFLL48M
FDPLL96M
Stop
Stop
To force an oscillator to always run in Idle mode, and not only when requested by a peripheral, the oscillator
ONDEMAND bit must be written to zero. The default value of this bit is one, and thus the default operation in Idle
mode is to run only when requested by a peripheral.
To force the oscillator to run in Standby mode, the RUNSTDBY bit must be written to one. The oscillator will then
run in Standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run
in Standby mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and
RUNSTDBY must be written to one.
The next table shows the behavior in the different sleep modes, depending on the settings of ONDEMAND and
RUNSTDBY.
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SAM D21/DA1 Family
SYSCTRL – System Controller
Table 17-2.ꢀBehavior in the different sleep modes
Sleep mode
Idle 0, 1, 2
Idle 0, 1, 2
Standby
ONDEMAND
RUNSTDBY
Behavior
0
1
0
0
1
1
X
X
0
1
0
1
Run
Run when requested by a peripheral
Stop
Standby
Run
Standby
Stop
Standby
Run when requested by a peripheral
Note:ꢀ This does not apply to the OSCULP32K oscillator, which is always running and cannot be disabled.
17.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation
The XOSC can operate in two different modes:
•
•
External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal
The XOSC can be used as a clock source for generic clock generators, as described in the GCLK – Generic Clock
Controller.
At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other
peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal
oscillator mode, the XIN and XOUT pins are controlled by the SYSCTRL, and GPIO functions are overridden on both
pins. When in external clock mode, only the XIN pin will be overridden and controlled by the SYSCTRL, while the
XOUT pin can still be used as a GPIO pin.
The XOSC is enabled by writing a one to the Enable bit in the External Multipurpose Crystal Oscillator Control
register (XOSC.ENABLE). To enable the XOSC as a crystal oscillator, a one must be written to the XTAL Enable bit
(XOSC.XTALEN). If XOSC.XTALEN is zero, external clock input will be enabled.
When in crystal oscillator mode (XOSC.XTALEN is one), the External Multipurpose Crystal Oscillator Gain
(XOSC.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal
Oscillator Automatic Amplitude Gain Control (XOSC.AMPGC) is one, the oscillator amplitude will be automatically
adjusted, and in most cases result in a lower power consumption.
The XOSC will behave differently in different sleep modes based on the settings of XOSC.RUNSTDBY,
XOSC.ONDEMAND and XOSC.ENABLE:
XOSC.RUNSTDBY XOSC.ONDEMAND XOSC.ENABLE Sleep Behavior
-
-
0
1
Disabled
0
0
Always run in IDLE sleep modes. Disabled in
STANDBY sleep mode.
0
1
1
Only run in IDLE sleep modes if requested by a
peripheral. Disabled in STANDBY sleep mode.
1
1
0
1
1
1
Always run in IDLE and STANDBY sleep modes.
Only run in IDLE or STANDBY sleep modes if
requested by a peripheral.
After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need
a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing
the Oscillator Start-Up Time bit group (XOSC.STARTUP) in the External Multipurpose Crystal Oscillator Control
register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to
the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Power and Clock Status register
(PCLKSR.XOSCRDY) is set when the user-selected start-up time is over. An interrupt is generated on a zero-to-one
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SYSCTRL – System Controller
transition on PCLKSR.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set
register (INTENSET.XOSCRDY) is set.
Note:ꢀ Do not enter standby mode when an oscillator is in start-up:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode.
Related Links
15. GCLK - Generic Clock Controller
17.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
The XOSC32K can operate in two different modes:
•
•
External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32
The XOSC32K can be used as a source for generic clock generators, as described in the GCLK – Generic Clock
Controller.
At Power-on Reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose
I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines
the GPIO usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO
functions are overridden on both pins. When in external clock mode, only the XIN32 pin will be overridden and
controlled by the SYSCTRL, while the XOUT32 pin can still be used as a GPIO pin.
The external clock or crystal oscillator is enabled by writing a one to the Enable bit (XOSC32K.ENABLE) in the 32kHz
External Crystal Oscillator Control register. To enable the XOSC32K as a crystal oscillator, a one must be written to
the XTAL Enable bit (XOSC32K.XTALEN). If XOSC32K.XTALEN is zero, external clock input will be enabled.
The oscillator is disabled by writing a zero to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal
Oscillator Control register while keeping the other bits unchanged. Writing to the XOSC32K.ENABLE bit while writing
to other bits may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been
enabled beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator
Start-Up Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register. The
SYSCTRL masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the
digital logic. The 32kHz External Crystal Oscillator Ready bit (PCLKSR.XOSC32KRDY) in the Power and Clock
Status register is set when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition
of PCLKSR.XOSC32KRDY if the 32kHz External Crystal Oscillator Ready bit (INTENSET.XOSC32KRDY) in the
Interrupt Enable Set Register is set.
As a crystal oscillator usually requires a very long start-up time (up to one second), the 32kHz External Crystal
Oscillator will keep running across resets, except for power-on reset (POR).
XOSC32K can provide two clock outputs when connected to a crystal. The XOSC32K has a 32.768kHz output
enabled by writing a one to the 32kHz External Crystal Oscillator 32kHz Output Enable bit (XOSC32K.EN32K) in the
32kHz External Crystal Oscillator Control register. XOSC32K.EN32K is only usable when XIN32 is connected to a
crystal, and not when an external digital clock is applied on XIN32.
Note:ꢀ Do not enter Standby mode when an oscillator is in start-up:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into Standby mode.
Related Links
15. GCLK - Generic Clock Controller
17.6.4 32 kHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed and low-power clock source.
The OSC32K can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock
Controller.
The OSC32K is disabled by default. The OSC32K is enabled by writing a one to the 32 kHz Internal Oscillator
Enable bit (OSC32K.ENABLE) in the 32 kHz Internal Oscillator Control register. It is disabled by writing a zero to
OSC32K.ENABLE. The OSC32K has a 32.768 kHz output enabled by writing a one to the 32 kHz Internal Oscillator
32 kHz Output Enable bit (OSC32K.EN32K). Both of the OSC32K.ENABLE and OSC32K.EN32K bits must be set for
DS40001882G-page 163
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SYSCTRL – System Controller
the clock to start. When the clock is stable, the PCLKSR.OSC32KRDY bit will go high and the clock will propagate in
the design.
The frequency of the OSC32K oscillator is controlled by the value in the 32 kHz Internal Oscillator Calibration bits
(OSC32K.CALIB) in the 32 kHz Internal Oscillator Control register. The OSC32K.CALIB value must be written by
the user. Flash Factory Calibration values are stored in the NVM Software Calibration Area (refer to NVM Software
Calibration Area Mapping). When writing to the Calibration bits, the user must wait for the PCLKSR.OSC32KRDY bit
to go high before the value is committed to the oscillator.
Related Links
15. GCLK - Generic Clock Controller
10.3.2 NVM Software Calibration Area Mapping
17.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factory-
calibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K
whenever the power requirements are prevalent over frequency stability and accuracy.
The OSCULP32K can be used as a source for the generic clock generators, as described in the GCLK – Generic
Clock Controller.
The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The
OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running.
The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal
Oscillator Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to
compensate for process variation, as described in the Electrical Characteristics. The calibration value can be
overridden by the user by writing to OSCULP32K.CALIB.
Related Links
37. Electrical Characteristics at 85℃
15. GCLK - Generic Clock Controller
17.6.6 8MHz Internal Oscillator (OSC8M) Operation
OSC8M is an internal oscillator operating in open-loop mode and generating an 8MHz frequency. The OSC8M is
factory-calibrated under typical voltage and temperature conditions.
OSC8M is the default clock source that is used after a power-on reset (POR). The OSC8M can be used as a source
for the generic clock generators, as described in the GCLK – Generic Clock Controller.
In order to enable OSC8M, the Oscillator Enable bit in the OSC8M Control register (OSC8M.ENABLE) must
be written to one. OSC8M will not be enabled until OSC8M.ENABLE is set. In order to disable OSC8M,
OSC8M.ENABLE must be written to zero. OSC8M will not be disabled until OSC8M is cleared.
The frequency of the OSC8M oscillator is controlled by the value in the calibration bits (OSC8M.CALIB) in the
OSC8M Control register. CALIB is automatically loaded from Flash Factory Calibration during start-up, and is used to
compensate for process variation, as described in the Electrical Characteristics.
The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB)
bit groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and
CALIB bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and
process dependent. Refer to the Electrical Characteristics for details.
OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the PM –
Power Manager.
Related Links
16. PM – Power Manager
37. Electrical Characteristics at 85℃
15. GCLK - Generic Clock Controller
DS40001882G-page 164
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.6.7 Digital Frequency Locked Loop (DFLL48M) Operation
The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency
clock with high accuracy can be used as the reference clock to get high accuracy on the output clock
(CLK_DFLL48M).
The DFLL48M can be used as a source for the generic clock generators, as described in the GCLK – Generic Clock
Controller.
Related Links
15. GCLK - Generic Clock Controller
17.6.7.1 Basic Operation
17.6.7.1.1 Open-Loop Operation
After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the
DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit
group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value
from NVM Software Calibration Area Mapping in DFLL.COARSE helps to output a frequency close to 48 MHz.
It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of
the DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be
used when PCLKSR.DFLLRDY is set after enabling the DFLL48M.
Related Links
10.3.2 NVM Software Calibration Area Mapping
17.6.7.1.2 Closed-Loop Operation
In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the
multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly
configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the
following way:
1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0
(GCLK_DFLL48M_REF). Refer to GCLK – Generic Clock Controller for details.
2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate
values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and
DFLLMUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output
frequency, but will typically result in longer lock times. A high value might give a large overshoot, but will
typically provide faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the
maximum value of DFLLVAL.COARSE and DFLLVAL.FINE, respectively.
3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier
register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the
maximum frequency of the DFLL.
4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL
Control register.
The frequency of CLK_DFLL48M (Fclkdfll48m) is given by:
F
= DFLLMUL ⋅ MUL × F
clkdfll48mref
clkdfll48m
where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and
DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified
frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for
Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce
the time needed to get a lock on Coarse.
Using "DFLL48M COARSE CAL" from NVM Software Calibration Area Mapping for DFLL.COARSE will start DFLL
with a frequency close to 48 MHz.
Following Software sequence should be followed while using the same.
1. load "DFLL48M COARSE CAL" from NVM User Row Mapping in DFLL.COARSE register
2. Set DFLLCTRL.BPLCKC bit
DS40001882G-page 165
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SYSCTRL – System Controller
3. Start DFLL close loop
This procedure will reduce DFLL Lock time to DFLL Fine lock time.
Related Links
15. GCLK - Generic Clock Controller
10.3.2 NVM Software Calibration Area Mapping
17.6.7.1.3 Frequency Locking
The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control
logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the
correct frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and
Clocks Status register will be set.
In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very
close to the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power
and Clocks Status register will be set.
Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or
INTENSET.DFLLOCKF are written to one.
CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status
register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the
Electrical Characteristics.
Related Links
37. Electrical Characteristics at 85℃
17.6.7.1.4 Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M
is in closed-loop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the
DFLL Multiplication Ratio Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on
CLK_DFLL48M compared to the target frequency is calculated as follows:
DIFF
ERROR =
MUL
17.6.7.1.5 Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner
will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that
DFLLVAL.FINE can change after every measurement of CLK_DFLL48M.
The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference
drifts or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status
register.
To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and
internal oscillator forbidden. The better choice is to use an XOSC32K.
17.6.7.1.6 Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)),
the DFLL Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set.
Detecting a stopped reference clock can take a long time, on the order of 217 CLK_DFLL48M cycles. When the
reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will
automatically resume if the CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition
on PCLKSR.DFLLRCS if the DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set
register is set.
17.6.7.2 Additional Features
17.6.7.2.1 Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up
to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
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SYSCTRL – System Controller
CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled
by writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill
cycles might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which
is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in
the DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but
the average output frequency is the same.
17.6.7.2.2 USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). This
mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit in DFLL Control register
(DFLLCTRL.USBCRM and DFLLCTRL.MODE).
Note:ꢀ In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined by the USB
bus activity, and have no valid meaning.
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic
clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should
be written to 0xBB80 to obtain a 48MHz clock.
In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored, and the value stored in the
DFLLVAL.COARSE will be used as final Coarse Value. The COARSE calibration value can be loaded from NVM
OTP row by software. The locking procedure will also go instantaneously to the fine lock search.
The DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The
DFLLCTRL.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.
17.6.7.2.3 Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit
(DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and
start running with the same configuration as before being disabled, even if the reference clock is not available. The
locks will not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any
frequency drift during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off,
the DFLL48M will lose all its locks, and needs to regain these through the full lock sequence.
17.6.7.2.4 Accuracy
There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum
accuracy when fine lock is achieved.
•
Fine resolution: The frequency step between two Fine values. This is relatively smaller for high output
frequencies.
•
Resolution of the measurement: If the resolution of the measured Fclkdfll48m is low, i.e., the ratio between the
CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a
frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of
32kHz or lower to avoid this issue for low target frequencies.
•
The accuracy of the reference clock.
17.6.8 Fractional Digital Phase-Locked Loop Controller (FDPLL96M) Operation
17.6.8.1 Overview
The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop
(DPLL). The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter
(TDC), a test mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional
multiplier of frequency N between the input and output frequency.
The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are
XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider. The
selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference
clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to GCLK
– Generic Clock Controller for details. If the GCLK_DPLL is selected as the source for the CLK_FDPLL96M_REF,
care must be taken to make sure the source for this GCLK is within the valid frequency range for the FDPLL96M.
DS40001882G-page 167
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SYSCTRL – System Controller
The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock
divider and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input
frequency range.
The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the
FDPLL96M internal control of the final clock gater CG.
The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock
must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to GCLK –
Generic Clock Controller for details.
Table 17-3.ꢀGeneric Clock Input for FDPLL96M
Generic Clock
FDPLL96M
FDPLL96M 32kHz clock
FDPLL96M
GCLK_DPLL_32K for internal lock timer
GCLK_DPLL for CLK_FDPLL96M_REF
Related Links
15. GCLK - Generic Clock Controller
17.6.8.2 Block Diagram
Figure 17-2.ꢀFDPLL96M Block Diagram
GCLK_DPLL_32K
User
Interface
XOSC32K
XOSC
CLK_FDPLL96M_REF
CK
CLK_FDPLL96M
Digital
Filter
DCO
TDC
GCLK_DPLL
÷N
17.6.8.3 Principle of Operation
The task of the FDPLL96M is to maintain coherence between the input reference clock signal
(CLK_FDPLL96M_REF) and the respective output frequency CK via phase comparison. The FDPLL96M supports
three independent sources of clocks; XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the
relationship between the reference clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M)
frequency is defined below.
LDRFRAC
f
= f
× LDR + 1 +
clk_fdpll96m
clk_fdpll96m_ref
16
Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fckrx is the
frequency of the selected reference clock and fck is the frequency of the FDPLL96M output clock. As previously
stated a clock divider exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is
defined below.
1
f
= f
×
clk_fdpll96m_ref
xosc
2 × DIV + 1
When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part
(DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is
activated. It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M.
Example (integer mode only): assuming fckr = 32kHz and fck = 48MHz, the multiplication ratio is 1500. It means that
LDR shall be set to 1499.
Example (fractional mode): assuming fckr = 32kHz and fck = 48.006MHz, the multiplication ratio is 1500.1875 (1500 +
3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
DS40001882G-page 168
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SYSCTRL – System Controller
17.6.8.4 Initialization, Enabling, Disabling and Resetting
The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE).
The FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output
clock CK is stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register
(DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is
linked with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency.
When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode, the clock gating cell is enabled
at the end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period,
but it allows saving several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is
discarded from the control of the clock gater generating the output clock CLK_FDPLL96M.
Table 17-4.ꢀCLK_FDPLL96M Behavior from Start-up to First Edge Detection.
WUF LTIME
CLK_FDPLL96M Behavior
0
0
1
0
Normal Mode: First Edge when lock is asserted
Not Equal To Zero
X
Lock Timer Timeout mode: First Edge when the timer downcounts to 0.
Wake Up Fast Mode: First Edge when CK is active (start-up time)
Table 17-5.ꢀCLK_FDPLL96M behavior after First Edge detection.
LBYPASS
CLK_FDPLL96M Behavior
0
1
Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
Figure 17-3.ꢀCK and CLK_FDPLL96M Off Mode to Running Mode
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
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SYSCTRL – System Controller
Figure 17-4.ꢀCK and CLK_FDPLL96M Off Mode to Running Mode when Wake-Up Fast is Activated
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
Figure 17-5.ꢀCK and CLK_FDPLL96M Running Mode to Off Mode
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
17.6.8.5 Reference Clock Switching
When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M,
modify the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again.
17.6.8.6 Loop Divider Ratio updates
The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop divider ratio
and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is
cleared and set again by hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the
Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge has been detected. The flag
is cleared when the software write a one to the interrupt flag bit location.
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SYSCTRL – System Controller
Figure 17-6.ꢀRATIOCTRL Register Update Operation
CKRx
LDR
mult0
mult1
LDRFRAC
CK
CLK_FDPLL96M
LOCK
LOCKL
17.6.8.7 Digital Filter Selection
The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability
and jitter. Nevertheless a software operation can override the filter setting using the DPLLCTRLB.FILTER field. The
DPLLCTRLB.LPEN field can be use to bypass the TDC module.
17.6.9 3.3V Brown-Out Detector Operation
The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes.
The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the
enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the
corresponding BOD33 register bit groups.
17.6.9.1 3.3V Brown-Out Detector (BOD33)
The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out
threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate
either an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection
status can be read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register.
At start-up or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to
NVM User Row Mapping for more details.
Related Links
10.3.1 NVM User Row Mapping
17.6.9.2 Continuous Mode
When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled,
the BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply
voltage.
Continuous mode is the default mode for BOD33.
17.6.9.3 Sampling Mode
The Sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks.
The BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until
the next sampling clock tick.
Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (Fclksampling) is controlled
by the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register.
F
clkprescaler
PSEL+1
F
=
clksampling
2
The prescaler signal (Fclkprescaler) is a 1 kHz clock, output from the32 kHz Ultra Low-Power Oscillator, OSCULP32K.
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SAM D21/DA1 Family
SYSCTRL – System Controller
As the Sampling mode clock is different from the APB clock domain, synchronization among the clocks is
necessary. The next figure shows a block diagram of the Sampling mode. The BOD33Synchronization Ready
bit (PCLKSR.B33SRDY) in the Power and Clocks Status register show the synchronization ready status of the
synchronizer. Writing attempts to the BOD33 register are ignored while PCLKSR.B33SRDY is zero.
Figure 17-7.ꢀSampling Mode Block Diagram
USER INTERFACE
REGISTERS
(APB clock domain)
PSEL
CEN
PRESCALER
(clk_prescaler
SYNCHRONIZER
CLK_SAMPLING
MODE
domain)
ENABLE
CLK_APB
CLK_PRESCALER
The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the
prescaler value. To change the prescaler value for the BOD33 during Sampling mode, the following steps need to be
taken:
1. Wait until the PCLKSR.B33SRDY bit is set.
2. Write the selected value to the BOD33.PSEL bit group.
17.6.9.4 Hysteresis
The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33
Hysteresis bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level.
17.6.10 Voltage Reference System Operation
The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature
sensor.
The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions.
At reset, the VREF.CAL register value is loaded from Flash Factory Calibration.
The temperature sensor can be used to get an absolute temperature in the temperature range of CMIN to CMAX
degrees Celsius. The sensor will output a linear voltage proportional to the temperature. The output voltage and
temperature range are located in the Electrical Characteristics. To calculate the temperature from a measured
voltage, the following formula can be used:
∆temperature
C
+ Vmes+ − Vout
MAX
MIN
∆voltage
Related Links
37. Electrical Characteristics at 85℃
17.6.10.1 User Control of the Voltage Reference System
To enable the temperature sensor, write a one to the Temperature Sensor Enable bit (VREF.TSEN) in the VREF
register. The temperature sensor is not available on the DA1 devices.
The temperature sensor can be redirected to the ADC for conversion.
The Bandgap Reference Voltage Generator output can also be routed to the ADC if the Bandgap Output Enable bit
(VREF.BGOUTEN) in the VREF register is set.
The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in
the VREF register. The default calibration value can be overridden by writing to the CALIB bit group.
DS40001882G-page 172
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.6.11 Voltage Regulator System Operation
The embedded Voltage Regulator (VREG) is an internal voltage regulator that provides the core logic supply
(VDDCORE).
17.6.12 DMA Operation
Not applicable.
17.6.13 Interrupts
The SYSCTRL has the following interrupt sources:
•
•
•
XOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSCRDY bit is
detected
XOSC32KRDY - 32kHz Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSC32KRDY bit is
detected
OSC32KRDY - 32kHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC32KRDY bit is
detected
•
•
•
•
•
•
OSC8MRDY - 8MHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC8MRDY bit is detected
DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected
DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected
DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected
DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is detected
DFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the PCLKSR.DFLLRCS bit is
detected
•
•
BOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected
BOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected. This is an
asynchronous interrupt and can be used to wake-up the device from any sleep mode.
•
•
•
B33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is detected
PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.
PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation
mode.
•
PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME
has elapsed since the start of the FDPLL96M.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG)
register for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note:ꢀ Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
17.6.14 Synchronization
Due to the multiple clock domains, values in the DFLL48M Control registers need to be synchronized to other
clock domains. The status of this synchronization can be read from the Power and Clocks Status register
(PCLKSR). Before writing to any of the DFLL48M Control registers, the user must check that the DFLL Ready
bit (PCLKSR.DFLLRDY) in PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and
CLK_DFLL48M is ready to be used. Any write to any of the DFLL48M Control registers while DFLLRDY is
DS40001882G-page 173
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SAM D21/DA1 Family
SYSCTRL – System Controller
zero will be ignored. An interrupt is generated on a zero-to-one transition of DFLLRDY if the DFLLRDY bit
(INTENSET.DFLLDY) in the Interrupt Enable Set register is set.
In order to read from any of the DFLL48M Configuration registers, the user must request a read synchronization
by writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If
DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until
the synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus.
The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the
peripheral bus. As a consequence, the Prescaler registers require synchronization when written or read. The
synchronization results in a delay from when the initialization of the write or read operation begins until the operation
is complete.
The write synchronization is triggered by a write to the BOD33 Control register. The Synchronization Ready bit
(PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write synchronization starts and set when the
write synchronization is complete. When the write synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt
to do any of the following will cause the peripheral bus to stall until the synchronization is complete:
•
•
Writing to the BOD33Control register
Reading the BOD33 Control register that was written
The user can poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupt to check when the synchronization
is complete. It is also possible to perform the next read/write operation and wait, as this next operation will be
completed after the ongoing read/write operation is synchronized.
DS40001882G-page 174
Complete Datasheet
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SAM D21/DA1 Family
SYSCTRL – System Controller
17.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
XOSC32KRD
Y
7:0
DFLLLCKC
DPLLLCKR
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY OSC32KRDY
XOSCRDY
15:8
23:16
31:24
B33SRDY
BOD33DET BOD33RDY
DPLLLTO
DFLLRCS
0x00
0x04
0x08
INTENCLR
DPLLLCKF
XOSC32KRD
7:0
DFLLLCKC
DPLLLCKR
DFLLLCKF
DFLLLCKF
DFLLLCKF
DFLLOOB
DFLLOOB
DFLLOOB
DFLLRDY
DFLLRDY
DFLLRDY
OSC8MRDY OSC32KRDY
XOSCRDY
Y
15:8
23:16
31:24
B33SRDY
BOD33DET BOD33RDY
DPLLLTO
DFLLRCS
INTENSET
INTFLAG
PCLKSR
DPLLLCKF
XOSC32KRD
7:0
DFLLLCKC
DPLLLCKR
OSC8MRDY OSC32KRDY
XOSCRDY
Y
15:8
23:16
31:24
B33SRDY
BOD33DET BOD33RDY
DPLLLTO
DFLLRCS
DPLLLCKF
XOSC32KRD
7:0
DFLLLCKC
DPLLLCKR
OSC8MRDY OSC32KRDY
XOSCRDY
Y
15:8
23:16
31:24
7:0
B33SRDY
AMPGC
EN32K
BOD33DET BOD33RDY
DPLLLTO
DFLLRCS
0x0C
0x10
DPLLLCKF
ONDEMAND RUNSTDBY
ONDEMAND RUNSTDBY
XTALEN
XTALEN
ENABLE
XOSC
15:8
STARTUP[3:0]
GAIN[2:0]
0x12
...
Reserved
XOSC32K
Reserved
0x13
7:0
AAMPEN
ENABLE
0x14
15:8
WRTLOCK
WRTLOCK
STARTUP[2:0]
0x16
...
0x17
7:0
15:8
23:16
31:24
7:0
ONDEMAND RUNSTDBY
WRTLOCK
EN32K
ENABLE
STARTUP[2:0]
0x18
OSC32K
CALIB[6:0]
0x1C
0x1D
...
OSCULP32K
Reserved
CALIB[4:0]
0x1F
7:0
15:8
23:16
31:24
7:0
ONDEMAND RUNSTDBY
ENABLE
PRESC[1:0]
0x20
OSC8M
CALIB[7:0]
FRANGE[1:0]
ONDEMAND
CALIB[11:8]
USBCRM
LLAW
STABLE
MODE
ENABLE
QLDIS
0x24
DFLLCTRL
Reserved
15:8
WAITLOCK
BPLCKC
CCDIS
0x26
...
0x27
7:0
15:8
23:16
31:24
7:0
FINE[7:0]
COARSE[5:0]
FINE[9:8]
0x28
DFLLVAL
DIFF[7:0]
DIFF[15:8]
MUL[7:0]
15:8
23:16
31:24
7:0
MUL[15:8]
FSTEP[7:0]
0x2C
0x30
DFLLMUL
CSTEP[5:0]
FSTEP[9:8]
DFLLSYNC
READREQ
DS40001882G-page 175
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SAM D21/DA1 Family
SYSCTRL – System Controller
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x31
...
Reserved
0x33
7:0
RUNSTDBY
ACTION[1:0]
HYST
ENABLE
CEN
15:8
PSEL[3:0]
MODE
0x34
BOD33
23:16
31:24
LEVEL[5:0]
0x38
...
Reserved
VREG
0x3B
7:0
RUNSTDBY
ENABLE
TSEN
0x3C
15:8
FORCELDO
0x3E
...
Reserved
0x3F
7:0
15:8
23:16
31:24
7:0
BGOUTEN
0x40
VREF
CALIB[7:0]
LDR[7:0]
CALIB[10:8]
ENABLE
0x44
0x45
...
DPLLCTRLA
Reserved
ONDEMAND RUNSTDBY
0x47
7:0
15:8
23:16
31:24
7:0
LDR[11:8]
LDRFRAC[3:0]
0x48
DPLLRATIO
REFCLK[1:0]
LBYPASS
DIV[7:0]
WUF
DIV
LPEN
FILTER[1:0]
LTIME[2:0]
15:8
23:16
31:24
7:0
0x4C
0x50
DPLLCTRLB
DPLLSTATUS
DIV[10:8]
CLKRDY
ENABLE
LOCK
17.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
DS40001882G-page 176
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.1 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x00
0x00000000
Property:ꢀ Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
DPLLLTO
R/W
16
DPLLLCKF
R/W
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
0
Bit
15
DPLLLCKR
R/W
14
13
12
11
B33SRDY
R/W
10
BOD33DET
R/W
9
8
DFLLRCS
R/W
BOD33RDY
Access
Reset
R
0
R
0
R
0
R/W
0
0
0
0
0
Bit
7
DFLLLCKC
R/W
6
DFLLLCKF
R/W
5
DFLLOOB
R/W
4
DFLLRDY
R/W
3
2
1
0
OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
Bit 17 – DPLLLTOꢀDPLL Lock Timeout Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout
interrupt.
Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Timeout Interrupt flag is set.
Bit 16 – DPLLLCKFꢀDPLL Lock Fall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Fall Interrupt flag is set.
Bit 15 – DPLLLCKRꢀDPLL Lock Rise Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise
interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Rise Interrupt flag is set.
Bit 11 – B33SRDYꢀBOD33 Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
DS40001882G-page 177
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33
Synchronization Ready interrupt.
Value
Description
0
1
The BOD33 Synchronization Ready interrupt is disabled.
The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the BOD33 Synchronization Ready Interrupt flag is set.
Bit 10 – BOD33DETꢀBOD33 Detection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection
interrupt.
Value
Description
0
The BOD33 Detection interrupt is disabled.
1
The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33
Detection Interrupt flag is set.
Bit 9 – BOD33RDYꢀBOD33 Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt.
Value
Description
0
The BOD33 Ready interrupt is disabled.
1
The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33
Ready Interrupt flag is set.
Bit 8 – DFLLRCSꢀDFLL Reference Clock Stopped Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL
Reference Clock Stopped interrupt.
Value
Description
0
1
The DFLL Reference Clock Stopped interrupt is disabled.
The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated
when the DFLL Reference Clock Stopped Interrupt flag is set.
Bit 7 – DFLLLCKCꢀDFLL Lock Coarse Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse
interrupt.
Value
Description
0
The DFLL Lock Coarse interrupt is disabled.
1
The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL
Lock Coarse Interrupt flag is set.
Bit 6 – DFLLLCKFꢀDFLL Lock Fine Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine
interrupt.
Value
Description
0
The DFLL Lock Fine interrupt is disabled.
1
The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL
Lock Fine Interrupt flag is set.
Bit 5 – DFLLOOBꢀDFLL Out Of Bounds Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of
Bounds interrupt.
Value
Description
0
The DFLL Out Of Bounds interrupt is disabled.
DS40001882G-page 178
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Value
Description
1
The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the
DFLL Out Of Bounds Interrupt flag is set.
Bit 4 – DFLLRDYꢀDFLL Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
Value
Description
0
The DFLL Ready interrupt is disabled.
1
The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready
Interrupt flag is set.
Bit 3 – OSC8MRDYꢀOSC8M Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt.
Value
Description
0
The OSC8M Ready interrupt is disabled.
1
The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M
Ready Interrupt flag is set.
Bit 2 – OSC32KRDYꢀOSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready
interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K
Ready Interrupt flag is set.
Bit 1 – XOSC32KRDYꢀXOSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready
interrupt.
Value
Description
0
1
The XOSC32K Ready interrupt is disabled.
The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the
XOSC32K Ready Interrupt flag is set.
Bit 0 – XOSCRDYꢀXOSC Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC
Ready Interrupt flag is set.
DS40001882G-page 179
Complete Datasheet
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SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.2 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x04
0x00000000
Property:ꢀ Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
DPLLLTO
R/W
16
DPLLLCKF
R/W
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
0
Bit
15
DPLLLCKR
R/W
14
13
12
11
B33SRDY
R/W
10
BOD33DET
R/W
9
8
DFLLRCS
R/W
BOD33RDY
Access
Reset
R
0
R
0
R
0
R/W
0
0
0
0
0
Bit
7
DFLLLCKC
R/W
6
DFLLLCKF
R/W
5
DFLLOOB
R/W
4
DFLLRDY
R/W
3
2
1
0
OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
Bit 17 – DPLLLTOꢀDPLL Lock Timeout Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout
interrupt.
Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Timeout Interrupt flag is set.
Bit 16 – DPLLLCKFꢀDPLL Lock Fall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Fall Interrupt flag is set.
Bit 15 – DPLLLCKRꢀDPLL Lock Rise Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL
Lock Rise Interrupt flag is set.
Bit 11 – B33SRDYꢀBOD33 Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33
Synchronization Ready interrupt.
DS40001882G-page 180
Complete Datasheet
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SAM D21/DA1 Family
SYSCTRL – System Controller
Value
Description
0
The BOD33 Synchronization Ready interrupt is disabled.
1
The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the BOD33 Synchronization Ready Interrupt flag is set.
Bit 10 – BOD33DETꢀBOD33 Detection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection
interrupt.
Value
Description
0
The BOD33 Detection interrupt is disabled.
1
The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33
Detection Interrupt flag is set.
Bit 9 – BOD33RDYꢀBOD33 Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt.
Value
Description
0
The BOD33 Ready interrupt is disabled.
1
The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33
Ready Interrupt flag is set.
Bit 8 – DFLLRCSꢀDFLL Reference Clock Stopped Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL
Reference Clock Stopped interrupt.
Value
Description
0
1
The DFLL Reference Clock Stopped interrupt is disabled.
The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated
when the DFLL Reference Clock Stopped Interrupt flag is set.
Bit 7 – DFLLLCKCꢀDFLL Lock Coarse Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse
interrupt.
Value
Description
0
The DFLL Lock Coarse interrupt is disabled.
1
The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL
Lock Coarse Interrupt flag is set.
Bit 6 – DFLLLCKFꢀDFLL Lock Fine Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine interrupt
and set the corresponding interrupt request.
Value
Description
0
The DFLL Lock Fine interrupt is disabled.
1
The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL
Lock Fine Interrupt flag is set.
Bit 5 – DFLLOOBꢀDFLL Out Of Bounds Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of Bounds
interrupt.
Value
Description
0
1
The DFLL Out Of Bounds interrupt is disabled.
The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the
DFLL Out Of Bounds Interrupt flag is set.
DS40001882G-page 181
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bit 4 – DFLLRDYꢀDFLL Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and set
the corresponding interrupt request.
Value
Description
0
The DFLL Ready interrupt is disabled.
1
The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready
Interrupt flag is set.
Bit 3 – OSC8MRDYꢀOSC8M Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt.
Value
Description
0
The OSC8M Ready interrupt is disabled.
1
The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M
Ready Interrupt flag is set.
Bit 2 – OSC32KRDYꢀOSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K
Ready Interrupt flag is set.
Bit 1 – XOSC32KRDYꢀXOSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready
interrupt.
Value
Description
0
1
The XOSC32K Ready interrupt is disabled.
The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the
XOSC32K Ready Interrupt flag is set.
Bit 0 – XOSCRDYꢀXOSC Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC
Ready Interrupt flag is set.
DS40001882G-page 182
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.3 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x08
0x00000000
-
Property:ꢀ
Note:ꢀ Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore
the user should clear those bits before using the corresponding interrupts.
Bit
31
30
29
28
27
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
DPLLLTO
R/W
16
DPLLLCKF
R/W
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
0
Bit
15
DPLLLCKR
R/W
14
13
12
11
B33SRDY
R/W
10
BOD33DET
R/W
9
8
DFLLRCS
R/W
BOD33RDY
Access
Reset
R
0
R
0
R
0
R/W
0
0
0
0
0
Bit
7
DFLLLCKC
R/W
6
DFLLLCKF
R/W
5
DFLLOOB
R/W
4
DFLLRDY
R/W
3
2
1
0
OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
Bit 17 – DPLLLTOꢀDPLL Lock Timeout
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO)
and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
Bit 16 – DPLLLCKFꢀDPLL Lock Fall
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF) and
will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Fall interrupt flag.
Bit 15 – DPLLLCKRꢀDPLL Lock Rise
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR) and
will generate an interrupt request if INTENSET.DPLLLCKR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Rise interrupt flag.
Bit 11 – B33SRDYꢀBOD33 Synchronization Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register
(PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag
DS40001882G-page 183
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bit 10 – BOD33DETꢀBOD33 Detection
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET)
and will generate an interrupt request if INTENSET.BOD33DET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Detection interrupt flag.
Bit 9 – BOD33RDYꢀBOD33 Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY) and
will generate an interrupt request if INTENSET.BOD33RDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Ready interrupt flag.
Bit 8 – DFLLRCSꢀDFLL Reference Clock Stopped
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register
(PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag.
Bit 7 – DFLLLCKCꢀDFLL Lock Coarse
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLLCKC)
and will generate an interrupt request if INTENSET.DFLLLCKC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Coarse interrupt flag.
Bit 6 – DFLLLCKFꢀDFLL Lock Fine
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF) and
will generate an interrupt request if INTENSET.DFLLLCKF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Fine interrupt flag.
Bit 5 – DFLLOOBꢀDFLL Out Of Bounds
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFLLOOB)
and will generate an interrupt request if INTENSET.DFLLOOB is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag.
Bit 4 – DFLLRDYꢀDFLL Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and will
generate an interrupt request if INTENSET.DFLLRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Ready interrupt flag.
Bit 3 – OSC8MRDYꢀOSC8M Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY) and
will generate an interrupt request if INTENSET.OSC8MRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC8M Ready interrupt flag.
Bit 2 – OSC32KRDYꢀOSC32K Ready
This flag is cleared by writing a one to it.
DS40001882G-page 184
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY)
and will generate an interrupt request if INTENSET.OSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC32K Ready interrupt flag.
Bit 1 – XOSC32KRDYꢀXOSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register (PCLKSR.XOSC32KRDY)
and will generate an interrupt request if INTENSET.XOSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC32K Ready interrupt flag.
Bit 0 – XOSCRDYꢀXOSC Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and
will generate an interrupt request if INTENSET.XOSCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC Ready interrupt flag.
DS40001882G-page 185
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.4 Power and Clocks Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PCLKSR
0x0C
0x00000000
-
Property:ꢀ
Bit
31
30
29
28
27
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
DPLLLCKR
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit 17 – DPLLLTOꢀDPLL Lock Timeout
Value
Description
0
1
DPLL Lock time-out not detected.
DPLL Lock time-out detected.
Bit 16 – DPLLLCKFꢀDPLL Lock Fall
Value
Description
0
1
DPLL Lock fall edge not detected.
DPLL Lock fall edge detected.
Bit 15 – DPLLLCKRꢀDPLL Lock Rise
Value
Description
0
1
DPLL Lock rise edge not detected.
DPLL Lock fall edge detected.
Bit 11 – B33SRDYꢀBOD33 Synchronization Ready
Value
Description
0
1
BOD33 synchronization is complete.
BOD33 synchronization is ongoing.
Bit 10 – BOD33DETꢀBOD33 Detection
Value
Description
0
No BOD33 detection.
1
BOD33 has detected that the I/O power supply is going below the BOD33 reference value.
Bit 9 – BOD33RDYꢀBOD33 Ready
Value
Description
0
BOD33 is not ready.
DS40001882G-page 186
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Value
Description
1
BOD33 is ready.
Bit 8 – DFLLRCSꢀDFLL Reference Clock Stopped
Value
Description
0
1
DFLL reference clock is running.
DFLL reference clock has stopped.
Bit 7 – DFLLLCKCꢀDFLL Lock Coarse
Value
Description
0
1
No DFLL coarse lock detected.
DFLL coarse lock detected.
Bit 6 – DFLLLCKFꢀDFLL Lock Fine
Value
Description
0
1
No DFLL fine lock detected.
DFLL fine lock detected.
Bit 5 – DFLLOOBꢀDFLL Out Of Bounds
Value
Description
0
1
No DFLL Out Of Bounds detected.
DFLL Out Of Bounds detected.
Bit 4 – DFLLRDYꢀDFLL Ready
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Value
Description
0
1
The Synchronization is ongoing.
The Synchronization is complete.
Bit 3 – OSC8MRDYꢀOSC8M Ready
Value
Description
0
OSC8M is not ready.
1
OSC8M is stable and ready to be used as a clock source.
Bit 2 – OSC32KRDYꢀOSC32K Ready
Value
Description
0
OSC32K is not ready.
1
OSC32K is stable and ready to be used as a clock source.
Bit 1 – XOSC32KRDYꢀXOSC32K Ready
Value
Description
0
XOSC32K is not ready.
1
XOSC32K is stable and ready to be used as a clock source.
Bit 0 – XOSCRDYꢀXOSC Ready
Value
Description
0
XOSC is not ready.
1
XOSC is stable and ready to be used as a clock source.
DS40001882G-page 187
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.5 External Multipurpose Crystal Oscillator (XOSC) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
XOSC
0x10
0x0080
Property:ꢀ Write-Protected
Bit
15
14
13
12
11
AMPGC
R/W
0
10
9
GAIN[2:0]
R/W
8
STARTUP[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
6
5
4
3
2
XTALEN
R/W
0
1
ENABLE
R/W
0
ONDEMAND
RUNSTDBY
Access
Reset
R/W
1
R/W
0
0
Bits 15:12 – STARTUP[3:0]ꢀStart-Up Time
These bits select start-up time for the oscillator according to the table below.
The OSCULP32K oscillator is used to clock the start-up counter.
STARTUP[3:0] Number of OSCULP32K
Clock Cycles
Number of XOSC Clock Approximate Equivalent Time(1)(2)(3)
Cycles
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
31 μs
61 μs
122 μs
244 μs
488 μs
977 μs
1953 μs
3906 μs
7813 μs
15625 μs
31250 μs
62500 μs
125000 μs
250000 μs
500000 μs
1000000 μs
Notes:ꢀ
1. Number of cycles for the start-up counter
2. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set.
3. Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the three XOSC
cycles.
Bit 11 – AMPGCꢀAutomatic Amplitude Gain Control
Note:ꢀ The configuration of the oscillator gain is mandatory even if AMPGC feature is enabled at startup.
Value
Description
0
The automatic amplitude gain control is disabled
1
The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during
Crystal Oscillator operation.
DS40001882G-page 188
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bits 10:8 – GAIN[2:0]ꢀOscillator Gain
These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might
vary based on capacitive load and crystal characteristics. These bits must be properly configured even when the
Automatic Amplitude Gain Control is active.
GAIN[2:0]
Recommended Max Frequency
0x0
2 MHz
0x1
4 MHz
0x2
8 MHz
0x3
0x4
0x5-0x7
16 MHz
30 MHz
Reserved
Bit 7 – ONDEMANDꢀOn Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock
requests.
In On Demand operation mode (i.e., if the XOSC.ONDEMAND bit has been previously written to one), the oscillator
will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In Standby Sleep mode, the On Demand operation is still active if the XOSC.RUNSTDBY bit is one. If
XOSC.RUNSTDBY is zero, the oscillator is disabled.
Value
Description
0
The oscillator is always on, if enabled
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBYꢀRun in Standby
This bit controls how the XOSC behaves during Standby Sleep mode:
Value
Description
0
The oscillator is disabled in Standby Sleep mode.
1
The oscillator is not stopped in Standby Sleep mode. If XOSC.ONDEMAND is one, the clock source
will be running when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock
source will always be running in Standby Sleep mode.
Bit 2 – XTALENꢀCrystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
Value
Description
0
1
External clock connected on XIN. XOUT can be used as general purpose I/O.
Crystal connected to XIN/XOUT
Bit 1 – ENABLEꢀOscillator Enable
Value
Description
0
1
The oscillator is disabled
The oscillator is enabled
DS40001882G-page 189
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.6 32kHz External Crystal Oscillator (XOSC32K) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
XOSC32K
0x14
0x0080
Property:ꢀ Write-Protected
Bit
15
14
13
12
WRTLOCK
R/W
11
10
9
8
STARTUP[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit
7
6
5
AAMPEN
R/W
4
3
EN32K
R/W
0
2
XTALEN
R/W
0
1
ENABLE
R/W
0
ONDEMAND
RUNSTDBY
Access
Reset
R/W
1
R/W
0
0
0
Bit 12 – WRTLOCKꢀWrite Lock
This bit locks the XOSC32K register for future writes to fix the XOSC32K configuration.
Value
Description
0
1
The XOSC32K configuration is not locked.
The XOSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0]ꢀOscillator Start-Up Time
These bits select the start-up time for the oscillator.
The OSCULP32K oscillator is used to clock the start-up counter.
Table 17-6.ꢀStart-Up Time for 32kHz External Crystal Oscillator
STARTUP[2:0] Number of OSCULP32K Clock Number of XOSC32K Clock Approximate Equivalent Time
Cycles
Cycles
(OSCULP = 32kHz)(1)(2)(3)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
1
32
3
3
3
3
3
3
3
3
122μs
1068μs
2048
4096
16384
32768
65536
131072
62592μs
125092μs
500092μs
1000092μs
2000092μs
4000092μs
Notes: 1. Number of cycles for the start-up counter.
2. Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set.
3. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles.
Bit 7 – ONDEMANDꢀOn Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only
be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the
oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the XOSC32K.RUNSTDBY bit is one. If
XOSC32K.RUNSTDBY is zero, the oscillator is disabled.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
DS40001882G-page 190
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bit 6 – RUNSTDBYꢀRun in Standby
This bit controls how the XOSC32K behaves during standby sleep mode:
Value
Description
0
The oscillator is disabled in standby sleep mode.
1
The oscillator is not stopped in standby sleep mode. If XOSC32K.ONDEMAND is one, the clock source
will be running when a peripheral is requesting the clock. If XOSC32K.ONDEMAND is zero, the clock
source will always be running in standby sleep mode.
Bit 5 – AAMPENꢀAutomatic Amplitude Control Enable
Value
Description
0
1
The automatic amplitude control for the crystal oscillator is disabled.
The automatic amplitude control for the crystal oscillator is enabled.
Bit 3 – EN32Kꢀ32kHz Output Enable
Value
Description
0
1
The 32kHz output is disabled.
The 32kHz output is enabled.
Bit 2 – XTALENꢀCrystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
Value
Description
0
1
External clock connected on XIN32. XOUT32 can be used as general-purpose I/O.
Crystal connected to XIN32/XOUT32.
Bit 1 – ENABLEꢀOscillator Enable
Value
Description
0
1
The oscillator is disabled.
The oscillator is enabled.
DS40001882G-page 191
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.7 32kHz Internal Oscillator (OSC32K) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OSC32K
0x18
0x003F0080
Property:ꢀ Write-Protected
Bit
31
23
15
30
29
21
28
20
27
26
18
25
17
24
16
Access
Reset
Bit
22
19
CALIB[6:0]
R/W
Access
Reset
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
Bit
14
13
12
WRTLOCK
R/W
11
10
9
8
STARTUP[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit
7
6
5
4
3
2
EN32K
R/W
0
1
ENABLE
R/W
0
ONDEMAND
RUNSTDBY
Access
Reset
R/W
1
R/W
0
0
Bits 22:16 – CALIB[6:0]ꢀOscillator Calibration
These bits control the oscillator calibration.
This value must be written by the user.
Factory calibration values can be loaded from the non-volatile memory.
Bit 12 – WRTLOCKꢀWrite Lock
This bit locks the OSC32K register for future writes to fix the OSC32K configuration.
Value
Description
0
1
The OSC32K configuration is not locked.
The OSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0]ꢀOscillator Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used as input clock to the startup counter.
Table 17-7.ꢀStart-Up Time for 32kHz Internal Oscillator
STARTUP[2:0]
Number of OSC32K clock cycles
Approximate Equivalent Time
(OSCULP= 32 kHz)(1)(2)(3)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
3
4
6
10
18
34
66
130
92μs
122μs
183μs
305μs
549μs
1038μs
2014μs
3967μs
Notes: 1. Number of cycles for the start-up counter.
DS40001882G-page 192
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
2. Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set.
3. Start-up time is n OSC32K cycles + 2 OSC32K cycles.
Bit 7 – ONDEMANDꢀOn Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, that is, if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the
oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC32K.RUNSTDBY bit is one. If
OSC32K.RUNSTDBY is zero, the oscillator is disabled.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBYꢀRun in Standby
This bit controls how the OSC32K behaves during Standby Sleep mode:
Value
Description
0
The oscillator is disabled in standby sleep mode.
1
The oscillator is not stopped in standby sleep mode. If OSC32K.ONDEMAND is one, the clock source
will be running when a peripheral is requesting the clock. If OSC32K.ONDEMAND is zero, the clock
source will always be running in standby sleep mode.
Bit 2 – EN32Kꢀ32 kHz Output Enable
Value
Description
0
1
The 32 kHz output is disabled.
The 32 kHz output is enabled.
Bit 1 – ENABLEꢀOscillator Enable
Value
Description
0
1
The oscillator is disabled.
The oscillator is enabled.
DS40001882G-page 193
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OSCULP32K
0x1C
0xXX
Property:ꢀ Write-Protected
Bit
7
WRTLOCK
R/W
6
5
4
3
2
CALIB[4:0]
R/W
1
0
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
0
x
Bit 7 – WRTLOCKꢀWrite Lock
This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration.
Value
Description
0
1
The OSCULP32K configuration is not locked.
The OSCULP32K configuration is locked.
Bits 4:0 – CALIB[4:0]ꢀOscillator Calibration
These bits control the oscillator calibration.
These bits are loaded from Flash Calibration at startup.
DS40001882G-page 194
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.9 8MHz Internal Oscillator (OSC8M) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OSC8M
0x20
0xXXXX0382
Property:ꢀ Write-Protected
Bit
31
30
29
21
28
20
27
26
25
24
FRANGE[1:0]
CALIB[11:8]
Access
Reset
R/W
x
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
19
18
17
16
CALIB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
Bit
15
14
13
12
11
10
9
8
PRESC[1:0]
Access
Reset
R/W
1
R/W
1
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
ENABLE
R/W
Access
Reset
R/W
1
R/W
0
1
Bits 31:30 – FRANGE[1:0]ꢀOscillator Frequency Range
These bits control the oscillator frequency range according to the table below. These bits are loaded from Flash
Calibration at startup.
FRANGE[1:0]
Description
0x0
0x1
0x2
0x3
4 to 6MHz
6 to 8MHz
8 to 11MHz
11 to 15MHz
Bits 27:16 – CALIB[11:0]ꢀOscillator Calibration
These bits control the oscillator calibration. The calibration field is split in two:
CALIB[11:6] is for temperature calibration
CALIB[5:0] is for overall process calibration
These bits are loaded from Flash Calibration at startup.
Bits 9:8 – PRESC[1:0]ꢀOscillator Prescaler
These bits select the oscillator prescaler factor setting according to the table below.
PRESC[1:0]
Description
0x0
0x1
0x2
0x3
1
2
4
8
Bit 7 – ONDEMANDꢀOn Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
DS40001882G-page 195
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator's clock source, the
oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC8M.RUNSTDBY bit is one. If
OSC8M.RUNSTDBY is zero, the oscillator is disabled.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBYꢀRun in Standby
This bit controls how the OSC8M behaves during standby sleep mode:
Value
Description
0
The oscillator is disabled in standby sleep mode.
1
The oscillator is not stopped in standby sleep mode. If OSC8M.ONDEMAND is one, the clock source
will be running when a peripheral is requesting the clock. If OSC8M.ONDEMAND is zero, the clock
source will always be running in standby sleep mode.
Bit 1 – ENABLEꢀOscillator Enable
The user must ensure that the OSC8M is fully disabled before enabling it, and that the OSC8M is fully enabled before
disabling it by reading OSC8M.ENABLE.
Value
Description
0
1
The oscillator is disabled or being enabled.
The oscillator is enabled or being disabled.
DS40001882G-page 196
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.10 DFLL48M Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DFLLCTRL
0x24
0x0080
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
14
6
13
12
11
WAITLOCK
R/W
10
BPLCKC
R/W
9
QLDIS
R/W
0
8
CCDIS
R/W
0
Access
Reset
0
0
Bit
7
5
USBCRM
R/W
4
LLAW
R/W
0
3
STABLE
R/W
0
2
MODE
R/W
0
1
ENABLE
R/W
0
ONDEMAND
Access
Reset
R/W
1
0
0
Bit 11 – WAITLOCKꢀWait Lock
This bit controls the DFLL output clock, depending on lock status:
Value
Description
0
1
Output clock before the DFLL is locked
Output clock when DFLL is locked
Bit 10 – BPLCKCꢀBypass Coarse Lock
This bit controls the coarse lock procedure:
Value
Description
0
1
Bypass coarse lock is disabled
Bypass coarse lock is enabled
Bit 9 – QLDISꢀQuick Lock Disable
Value
Description
0
1
Quick Lock is enabled
Quick Lock is disabled
Bit 8 – CCDISꢀChill Cycle Disable
Value
Description
0
1
Chill Cycle is enabled
Chill Cycle is disabled
Bit 7 – ONDEMANDꢀOn Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode (i.e., if the ONDEMAND bit has been previously written to one), the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the
oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In Standby Sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If
DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled.
Value
Description
0
The oscillator is always on, if enabled
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
The oscillator is disabled if no peripheral is requesting the clock source.
Bit 5 – USBCRMꢀUSB Clock Recovery Mode
Value
Description
0
USB Clock Recovery mode is disabled
DS40001882G-page 197
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Value
Description
1
USB Clock Recovery mode is enabled
Bit 4 – LLAWꢀLose Lock After Wake
Value
Description
0
1
Locks will not be lost after waking up from Sleep modes if the DFLL clock has been stopped
Locks will be lost after waking up from Sleep modes if the DFLL clock has been stopped
Bit 3 – STABLEꢀStable DFLL Frequency
Value
Description
0
1
FINE calibration tracks changes in output frequency
FINE calibration register value will be fixed after a fine lock
Bit 2 – MODEꢀOperating Mode Selection
Value
Description
0
1
The DFLL operates in open-loop operation
The DFLL operates in closed-loop operation
Bit 1 – ENABLEꢀDFLL Enable
Due to synchronization, there is a delay from updating the register until the peripheral is enabled/disabled. The value
written to DFLLCTRL.ENABLE will read back immediately after written.
Value
Description
0
1
The DFLL oscillator is disabled
The DFLL oscillator is enabled
DS40001882G-page 198
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.11 DFLL48M Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DFLLVAL
0x28
0x00000000
Property:ꢀ Read-Synchronized, Write-Protected
Bit
31
30
29
28
27
26
25
24
DIFF[15:8]
DIFF[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
COARSE[5:0]
FINE[9:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
FINE[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:16 – DIFF[15:0]ꢀMultiplication Ratio Difference
In closed-loop mode (DFLLCTRL.MODE is written to one), this bit group indicates the difference between the ideal
number of DFLL cycles and the counted number of cycles. This value is not updated in open-loop mode, and should
be considered invalid in that case.
Bits 15:10 – COARSE[5:0]ꢀCoarse Value
Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.
Bits 9:0 – FINE[9:0]ꢀFine Value
Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.
DS40001882G-page 199
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.12 DFLL48M Multiplier
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DFLLMUL
0x2C
0x00000000
Property:ꢀ Write-Protected
Bit
31
30
29
28
27
26
25
24
CSTEP[5:0]
FSTEP[9:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
FSTEP[7:0]
MUL[15:8]
MUL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:26 – CSTEP[5:0]ꢀCoarse Maximum Step
This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When
adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
Bits 25:16 – FSTEP[9:0]ꢀFine Maximum Step
This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjusting
to a new frequency, the expected output frequency overshoot depends on this step size.
Bits 15:0 – MUL[15:0]ꢀDFLL Multiply Factor
This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to
the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint.
DS40001882G-page 200
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.13 DFLL48M Synchronization
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DFLLSYNC
0x30
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
READREQ
Access
Reset
W
0
Bit 7 – READREQꢀRead Request
To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The updated
value is available in DFLLVAL when PCLKSR.DFLLRDY is set.
DS40001882G-page 201
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.14 3.3V Brown-Out Detector (BOD33) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BOD33
0x34
0x00XX00XX
Property:ꢀ Write-Protected, Write-Synchronized
Bit
31
23
15
30
22
14
29
28
27
19
26
18
25
17
24
16
Access
Reset
Bit
21
20
LEVEL[5:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
13
12
11
10
9
8
MODE
R/W
0
PSEL[3:0]
CEN
R/W
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
RUNSTDBY
ACTION[1:0]
HYST
R/W
x
Access
Reset
R/W
0
R/W
x
R/W
x
x
Bits 21:16 – LEVEL[5:0]ꢀBOD33 Threshold Level
This field sets the triggering voltage threshold for the BOD33. See the Electrical Characteristics for actual voltage
levels. Note that any change to the LEVEL field of the BOD33 register should be done when the BOD33 is disabled in
order to avoid spurious resets or interrupts.
These bits are loaded from Flash User Row at start-up. Refer to NVM User Row Mapping for more details.
Bits 15:12 – PSEL[3:0]ꢀPrescaler Select
Selects the prescaler divide-by output for the BOD33 sampling mode according to the table below. The input clock
comes from the OSCULP32K 1kHz output.
PSEL[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
DIV2
DIV4
DIV8
Divide clock by 2
Divide clock by 4
Divide clock by 8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1K
DIV2K
DIV4K
DIV8K
DIV16K
DIV32K
DIV64K
Divide clock by 16
Divide clock by 32
Divide clock by 64
Divide clock by 128
Divide clock by 256
Divide clock by 512
Divide clock by 1024
Divide clock by 2048
Divide clock by 4096
Divide clock by 8192
Divide clock by 16384
Divide clock by 32768
Divide clock by 65536
DS40001882G-page 202
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bit 9 – CENꢀClock Enable
Writing a zero to this bit will stop the BOD33 sampling clock.
Writing a one to this bit will start the BOD33 sampling clock.
Value
Description
0
1
The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable.
The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped.
Bit 8 – MODEꢀOperation Mode
Value
Description
0
1
The BOD33 operates in continuous mode.
The BOD33 operates in sampling mode.
Bit 6 – RUNSTDBYꢀRun in Standby
Value
Description
0
1
The BOD33 is disabled in standby sleep mode.
The BOD33 is enabled in standby sleep mode.
Bits 4:3 – ACTION[1:0]ꢀBOD33 Action
These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold.
These bits are loaded from Flash User Row at start-up.
ACTION[1:0]
Name
Description
0x0
0x1
0x2
0x3
NONE
RESET
INTERRUPT
No action
The BOD33 generates a reset
The BOD33 generates an interrupt
Reserved
Bit 2 – HYSTꢀHysteresis
This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage:
This bit is loaded from Flash User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
Description
0
1
No hysteresis.
Hysteresis enabled.
Bit 1 – ENABLEꢀEnable
This bit is loaded from Flash User Row at startup. Refer to NVM User Row Mapping for more details.
Value
Description
0
1
BOD33 is disabled.
BOD33 is enabled.
Related Links
37. Electrical Characteristics at 85℃
10.3.1 NVM User Row Mapping
DS40001882G-page 203
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.15 Voltage Regulator System (VREG) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
VREG
0x3C
0x0X02
Property:ꢀ Write-Protected
Bit
15
7
14
13
FORCELDO
R/W
12
4
11
3
10
2
9
8
0
Access
Reset
0
Bit
6
5
1
ENABLE
R/W
RUNSTDBY
Access
Reset
R/W
0
1
Bit 13 – FORCELDOꢀForce LDO Voltage Regulator
Value
Description
0
1
The voltage regulator is in low-power and low-drive configuration in Standby Sleep mode
The voltage regulator is in low-power and high-drive configuration in Standby Sleep mode
Bit 6 – RUNSTDBYꢀRun in Standby
Value
Description
0
1
The voltage regulator is in low-power configuration in Standby Sleep mode
The voltage regulator is in normal configuration in Standby Sleep mode
Bit 1 – ENABLE
Must be set to 1.
DS40001882G-page 204
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.16 Voltage References System (VREF) Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
VREF
0x40
0x0XXX0000
Property:ꢀ Write-Protected
Bit
31
30
29
21
28
20
27
19
26
25
CALIB[10:8]
R/W
24
Access
Reset
R/W
x
R/W
x
x
Bit
23
22
18
17
16
CALIB[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
BGOUTEN
R/W
1
TSEN
R/W
0
0
Access
Reset
0
Bits 26:16 – CALIB[10:0]ꢀBandgap Voltage Generator Calibration
These bits are used to calibrate the output level of the bandgap voltage reference. These bits are loaded from Flash
Calibration Row at start-up.
Bit 2 – BGOUTENꢀBandgap Output Enable
Value
Description
0
1
The bandgap output is not available as an ADC input channel
The bandgap output is routed to an ADC input channel
Bit 1 – TSENꢀTemperature Sensor Enable(1)
Value
Description
0
Temperature sensor is disabled
1
Temperature sensor is enabled and routed to an ADC input channel
Note:ꢀ 1. The TSEN bit is not available on the DA1 device.
DS40001882G-page 205
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.17 DPLL Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DPLLCTRLA
0x44
0x80
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
ONDEMAND
RUNSTDBY
Access
Reset
R/W
1
R/W
0
0
Bit 7 – ONDEMANDꢀOn Demand Clock Activation
Value
0
1
Description
The DPLL is always on when enabled.
The DPLL is activated only when a peripheral request the DPLL as a source clock. The
DPLLCTRLA.ENABLE bit must be one to validate that operation, otherwise the peripheral request
has no effect.
Bit 6 – RUNSTDBYꢀRun in Standby
Value
Description
0
1
The DPLL is disabled in standby sleep mode.
The DPLL is not stopped in standby sleep mode.
Bit 1 – ENABLEꢀDPLL Enable
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the
DPLLSTATUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
Value
Description
0
1
The DPLL is disabled.
The DPLL is enabled.
DS40001882G-page 206
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.18 DPLL Ratio Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DPLLRATIO
0x48
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
26
18
25
17
24
16
Access
Reset
Bit
LDRFRAC[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
11
10
9
8
LDR[11:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
3
2
1
0
LDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 19:16 – LDRFRAC[3:0]ꢀLoop Divider Ratio Fractional Part
Write this field with the fractional part of the frequency multiplier.
Bits 11:0 – LDR[11:0]ꢀLoop Divider Ratio
Write this field with the integer part of the frequency multiplier.
DS40001882G-page 207
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.19 DPLL Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DPLLCTRLB
0x4C
0x00000000
Property:ꢀ Write-Protected
Bit
31
30
29
21
28
20
27
19
26
25
DIV[10:8]
R/W
24
Access
Reset
R/W
0
R/W
0
0
Bit
23
22
18
17
16
DIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
LTIME[2:0]
R/W
8
LBYPASS
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit
7
6
5
4
3
WUF
R/W
0
2
LPEN
R/W
0
1
0
REFCLK[1:0]
FILTER[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 26:16 – DIV[10:0]ꢀClock Divider
These bits are used to set the XOSC clock source division factor. Refer to 17.6.8.3 Principle of Operation.
Bit 12 – LBYPASSꢀLock Bypass
Value
Description
0
1
Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
Bits 10:8 – LTIME[2:0]ꢀLock Time
These bits select Lock Timeout.
LTIME[2:0]
Name
Description
0x0
DEFAULT
No time-out
0x1-0x3
0x4
0x5
0x6
0x7
Reserved
8MS
9MS
10MS
11MS
Time-out if no lock within 8 ms
Time-out if no lock within 9 ms
Time-out if no lock within 10 ms
Time-out if no lock within 11 ms
Bits 5:4 – REFCLK[1:0]ꢀReference Clock Selection
These bits select the CLK_FDPLL96M_REF source.
REFCLK[1:0]
Name
Description
0x0
0x1
0x2
0x3
XOSC32
XOSC
GCLK_DPLL
XOSC32 clock reference
XOSC clock reference
GCLK_DPLL clock reference
Reserved
DS40001882G-page 208
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
Bit 3 – WUFꢀWake Up Fast
Value
Description
0
1
DPLL CK output is gated until complete startup time and lock time.
DPLL CK output is gated until startup time only.
Bit 2 – LPENꢀLow-Power Enable
Value
Description
0
The time to digital converter is selected.
1
The time to digital converter is not selected, this will improve power consumption but increase the
output jitter.
Bits 1:0 – FILTER[1:0]ꢀProportional Integral Filter Selection
These bits select the DPLL filter type.
FILTER[1:0]
Name
Description
0x0
0x1
0x2
0x3
DEFAULT
LBFILT
HBFILT
HDFILT
Default filter mode
Low bandwidth filter
High bandwidth filter
High damping filter
DS40001882G-page 209
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SYSCTRL – System Controller
17.8.20 DPLL Status
Name:ꢀ
DPLLSTATUS
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x50
0x00
-
Bit
7
6
5
4
3
DIV
R
2
1
0
LOCK
R
ENABLE
CLKRDY
Access
Reset
R
0
R
0
0
0
Bit 3 – DIVꢀDivider Enable
Value
Description
0
1
The reference clock divider is disabled.
The reference clock divider is enabled.
Bit 2 – ENABLEꢀDPLL Enable
Value
Description
0
1
The DPLL is disabled.
The DPLL is enabled.
Bit 1 – CLKRDYꢀOutput Clock Ready
Value
Description
0
1
The DPLL output clock is off
The DPLL output clock in on.
Bit 0 – LOCKꢀDPLL Lock Status
Value
Description
0
1
The DPLL Lock signal is cleared.
The DPLL Lock signal is asserted.
DS40001882G-page 210
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.
WDT – Watchdog Timer
18.1
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to
recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out
period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a
system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot (or window) inside the total time-out period during which
the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will
be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be
cleared frequently.
When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU-
independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main
clocks fail.
18.2
Features
•
•
•
•
Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation:
– Normal mode
– Window mode
•
•
Selectable time-out periods
– From 8 cycles to 16,000 cycles in normal mode
– From 16 cycles to 32,000 cycles in window mode
Always-on capability
18.3
Block Diagram
Figure 18-1.ꢀWDT Block Diagram
0xA5
0
CLEAR
GCLK_WDT
COUNT
PER/WINDOW/EWOFFSET
Early Warning Interrupt
Reset
DS40001882G-page 211
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.4
18.5
Signal Description
Not applicable.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
18.5.1 I/O Lines
Not applicable.
18.5.2 Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting sleep modes.
Related Links
16. PM – Power Manager
18.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power
Manager. Refer to PM – Power Manager for details.
A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the
Generic Clock Controller before using the WDT. Refer to GCLK – Generic Clock Controller for details. This generic
clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing certain
registers will require synchronization between the clock domains. Refer to Synchronization for further details.
GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the
ultralow- power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to
device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out
periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the Ultra Low Power
Internal 32kHz RC Oscillator (OSCULP32K) Characteristics.
GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher
power consumption.
Related Links
16. PM – Power Manager
15. GCLK - Generic Clock Controller
17.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
18.6.5 Synchronization
18.5.4 DMA
Not applicable.
18.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt
controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
18.5.6 Events
Not applicable.
DS40001882G-page 212
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.5.7 Debug Operation
When the CPU is halted in debug mode the WDT will halt normal operation.
18.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
Interrupt Flag Status and Clear register (INTFLAG)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Related Links
11.6 Peripheral Access Controller (PAC)
18.5.9 Analog Connections
Not applicable.
18.6
Functional Description
18.6.1 Principle of Operation
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from
error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a constantly running timer that
is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or
else, a system Reset is issued.
The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early
Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control
register (CTRL) and the Interrupt Enable register (handled by INTENCLR/SET) determine the mode of operation:
Table 18-1.ꢀWDT Operating Modes
CTRL.ENABLE
CTRL.WEN
INTENSET.EW
Mode
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Stopped
Normal
Normal with Early Warning interrupt
Window
Window with Early Warning interrupt
18.6.2 Basic Operation
18.6.2.1 Initialization
The following bits are enable-protected:
•
•
Window Mode Enable in the Control register (CTRL.WEN)
Always-On in the Control register (CTRL-ALWAYSON)
The following registers are enable-protected:
•
•
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL)
Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE=1) will be
discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete.
Enable-protection is denoted by the Enable-Protected property in the register description.
Initialization of the WDT can be done only while the WDT is disabled. The WDT is configured by defining the
required Time-Out Period bits in the Configuration register (CONFIG.PER). If window-mode operation is required, the
DS40001882G-page 213
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
Window Enable bit in the Control register (CTRL.WEN) must be written to one and the Window Period bits in the
Configuration register (CONFIG.WINDOW) must be defined.
Normal Mode
•
Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
Normal Mode with Early Warning interrupt
•
•
Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
•
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
Window Mode
•
•
•
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
Setting Window Enable bit in the Control register (CTRL.WEN).
Window Mode with Early Warning interrupt
•
•
•
•
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
Setting Window Enable bit in the Control register (CTRL.WEN).
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
•
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
18.6.2.2 Configurable Reset Values
After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. Refer to NVM User
Row Mapping for more details.
This encompasses the following bits and bit groups:
•
•
•
•
•
•
Enable bit in the Control register, CTRL.ENABLE
Always-On bit in the Control register, CTRL.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control register, CTRL.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW
Time-Out Period in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET
For more information about fuse locations, see NVM User Row Mapping.
Related Links
10.3.1 NVM User Row Mapping
18.6.2.3 Enabling and Disabling
The WDT is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled
by writing a '0' to CTRL.ENABLE.
The WDT can be disabled only if the Always-On bit in the Control register (CTRL.ALWAYSON) is '0'.
18.6.2.4 Normal Mode
In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by
writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, the WDT will issue a system
reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period.
The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing
any other value than 0xA5 to CLEAR will issue an immediate system reset.
There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s.
DS40001882G-page 214
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt
Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1'
to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW). If the Early Warning Interrupt
is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal mode, the Early Warning Offset
bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning
interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation.
Figure 18-2.ꢀNormal-Mode Operation
WDT Count
Timely WDT Clear
PER[3:0] = 1
WDT Timeout
System Reset
EWOFFSET[3:0] = 0
Early Warning Interrupt
t[ms]
5
10
15
20
25
30
35
TOWDT
18.6.2.5 Window Mode
In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing
0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal
time-out period (TOWDTW). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT
will issue a system reset. Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total
duration of the WDT time-out period is the sum of the two parameters. The closed window period is defined by the
Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window period is defined by the
Period bits in the Configuration register (CONFIG.PER).
By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the
Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by
writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. If the Early
Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window period, i.e.
after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation.
Figure 18-3.ꢀWindow-Mode Operation
WDT Count
Timely WDT Clear
PER[3:0] = 0
WDT Timeout
Early WDT Clear
WINDOW[3:0] = 0
Early Warning Interrupt
System Reset
t[ms]
5
10
15
20
25
30
35
TOWDTW
TOWDT
18.6.3 Additional Features
18.6.3.1 Always-On Mode
The Always-On mode is enabled by setting the Always-On bit in the Control register (CTRLA.ALWAYSON=1). When
the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once
written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning
Control (EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period
configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in
Always-On mode, but note that CONFIG.PER cannot be changed.
DS40001882G-page 215
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
The CTRL.ALWAYSON bit must never be set to one by software if any of the following conditions is true:
1. The GCLK_WDT is disabled
2. The clock generator for the GCLK_WDT is disabled
3. The source clock of the clock generator for the GCLK_WDT is disabled or off
The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt
can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be
changed.
Table 18-2.ꢀWDT Operating Modes With Always-On
WEN
Interrupt enable
Mode
0
0
1
1
0
1
0
1
Always-on and normal mode
Always-on and normal mode with Early Warning interrupt
Always-on and window mode
Always-on and window mode with Early Warning interrupt
18.6.4 Interrupts
The WDT has the following interrupt source:
•
Early Warning (EW)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See
the INTFLAG register description for details on how to clear interrupt flags.
The WDT has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note:ꢀ Interrupts must be globally enabled for interrupt requests to be generated.
The Early Warning interrupt behaves differently in normal mode and in window mode. In normal mode, the
Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning Control register
(EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt
is generated, relative to the start of the watchdog time-out period. For example, if the WDT is operating in normal
mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16
GCLK_WDT clock cycles from the start of the watchdog time-out period, and the watchdog time-out system reset is
generated 32 GCLK_WDT clock cycles from the start of the watchdog time-out period. The user must take caution
when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time
greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early
Warning interrupt. Thus, the Early Warning interrupt will never be generated.
In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical
application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer,
after which the system can perform other tasks or return to sleep mode.
18.6.5 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY='1', the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
DS40001882G-page 216
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
The following registers are synchronized when written:
•
•
Control register (CTRL)
Clear register (CLEAR)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 217
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
CTRL
CONFIG
EWCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
STATUS
CLEAR
7:0
7:0
7:0
ALWAYSON
WEN
ENABLE
WINDOW[3:0]
PER[3:0]
EWOFFSET[3:0]
7:0
7:0
7:0
7:0
7:0
EW
EW
EW
SYNCBUSY
CLEAR[7:0]
18.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
DS40001882G-page 218
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x0
N/A - Loaded from NVM User Row at start-up
Property:ꢀ Write-Protected, Enable-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
WEN
R/W
x
1
ENABLE
R/W
0
ALWAYSON
Access
Reset
R/W
x
x
Bit 7 – ALWAYSONꢀAlways-On
This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the
WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the
Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes
to these registers are not allowed. Writing a zero to this bit has no effect.
This bit is not enable-protected.
These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
Description
0
1
The WDT is enabled and disabled through the ENABLE bit.
The WDT is enabled and can only be disabled by a power-on reset (POR).
Bit 2 – WENꢀWatchdog Timer Window Mode Enable
The initial value of this bit is loaded from Flash Calibration.
This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
Description
0
1
Window mode is disabled (normal operation).
Window mode is enabled.
Bit 1 – ENABLEꢀEnable
This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
This bit is loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
Description
0
1
The WDT is disabled.
The WDT is enabled.
Related Links
10.3.1 NVM User Row Mapping
DS40001882G-page 219
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
WDT – Watchdog Timer
18.8.2 Configuration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CONFIG
0x1
N/A - Loaded from NVM User Row at startup
Property:ꢀ Write-Protected, Enable-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
WINDOW[3:0]
PER[3:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:4 – WINDOW[3:0]ꢀWindow Mode Time-Out Period
In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles.
These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
0x0
Description
8 clock cycles
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC-0xF
16 clock cycles
32 clock cycles
64 clock cycles
128 clock cycles
256 clocks cycles
512 clocks cycles
1024 clock cycles
2048 clock cycles
4096 clock cycles
8192 clock cycles
16384 clock cycles
Reserved
Bits 3:0 – PER[3:0]ꢀTime-Out Period
These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode
operation, these bits define the open window period.
These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.
Value
0x0
Description
8 clock cycles
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC-0xF
16 clock cycles
32 clock cycles
64 clock cycles
128 clock cycles
256 clocks cycles
512 clocks cycles
1024 clock cycles
2048 clock cycles
4096 clock cycles
8192 clock cycles
16384 clock cycles
Reserved
Related Links
10.3.1 NVM User Row Mapping
DS40001882G-page 220
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WDT – Watchdog Timer
18.8.3 Early Warning Interrupt Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EWCTRL
0x2
N/A - Loaded from NVM User Row at start-up
Property:ꢀ Write-Protected, Enable-Protected
Bit
7
6
5
4
3
2
1
0
EWOFFSET[3:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 3:0 – EWOFFSET[3:0]ꢀEarly Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period to
when the Early Warning interrupt is generated. These bits are loaded from NVM User Row at start-up. Refer to NVM
User Row Mapping for more details.
Value
0x0
Description
8 clock cycles
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC-0xF
16 clock cycles
32 clock cycles
64 clock cycles
128 clock cycles
256 clocks cycles
512 clocks cycles
1024 clock cycles
2048 clock cycles
4096 clock cycles
8192 clock cycles
16384 clock cycles
Reserved
Related Links
10.3.1 NVM User Row Mapping
DS40001882G-page 221
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SAM D21/DA1 Family
WDT – Watchdog Timer
18.8.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x4
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
EW
R/W
0
Access
Reset
Bit 0 – EWꢀEarly Warning Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Early Warning interrupt.
Value
Description
0
1
The Early Warning interrupt is disabled.
The Early Warning interrupt is enabled.
DS40001882G-page 222
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WDT – Watchdog Timer
18.8.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x5
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
EW
R/W
0
Access
Reset
Bit 0 – EWꢀEarly Warning Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Early Warning interrupt.
Value
Description
0
1
The Early Warning interrupt is disabled.
The Early Warning interrupt is enabled.
DS40001882G-page 223
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WDT – Watchdog Timer
18.8.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x6
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
EW
R/W
0
Access
Reset
Bit 0 – EWꢀEarly Warning
This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Early Warning interrupt flag.
DS40001882G-page 224
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WDT – Watchdog Timer
18.8.7 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x7
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
DS40001882G-page 225
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WDT – Watchdog Timer
18.8.8 Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CLEAR
0x8
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
CLEAR[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bits 7:0 – CLEAR[7:0]ꢀWatchdog Clear
Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing any
other value will issue an immediate system reset.
DS40001882G-page 226
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.
RTC – Real-Time Counter
19.1
Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs
continuously to keep track of time. The RTC can wake-up the device from Sleep modes using the alarm/compare
wake-up, periodic wake-up, or overflow wake-up mechanisms
The RTC can be clocked from several clock sources selectable through the Generic Clock module (GCLK). This
GCLK_RTC clock can then be divided with CTRLA.PRESCALER to achieve the required resolution.
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts
and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt
and peripheral event, and can be Reset on the occurrence of an alarm/compare match. This allows periodic
interrupts and peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and
time-out periods can be configured. With a 32.768 kHz clock source, the minimum counter tick interval is 30.5 µs, and
time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more
than 136 years.
19.2
Features
•
•
•
32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit Counter mode
– One 32-bit or two 16-bit compare values
Clock/Calendar mode
•
– Time in seconds, minutes and hours (12/24)
– Date in day of month, month and year
– Leap year correction
•
•
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events
– Optional clear on alarm/compare match
19.3
Block Diagram
Figure 19-1.ꢀRTC Block Diagram (Mode 0 — 32-Bit Counter)
0
MATCHCLR
CLK_RTC_CNT
GCLK_RTC
10-bit
Overflow
COUNT
Prescaler
32
=
Compare n
32
Periodic
Events
COMPn
DS40001882G-page 227
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SAM D21/DA1 Family
RTC – Real-Time Counter
Figure 19-2.ꢀRTC Block Diagram (Mode 1 — 16-Bit Counter)
0
GCLK_RTC
CLK_RTC_CNT
10-bit
COUNT
Prescaler
=
Overflow
16
16
Periodic
Events
PER
=
Compare n
16
COMPn
Figure 19-3.ꢀRTC Block Diagram (Mode 2 — Clock/Calendar)
0
MATCHCLR
GCLK_RTC
CLK_RTC_CNT
MASKn
10-bit
Prescaler
Overflow
CLOCK
32
Y/M/D H:M:S
Alarm n
=
32
Y/M/D H:M:S
Periodic
Events
ALARMn
19.4
19.5
Signal Description
Not applicable.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
19.5.1 I/O Lines
Not applicable.
19.5.2 Power Management
The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other
operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep
modes.
The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control register
(CTRL.SWRST=1).
Related Links
16. PM – Power Manager
19.5.3 Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_RTC_APB can be found in the Peripheral Clock Masking section.
DS40001882G-page 228
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SAM D21/DA1 Family
RTC – Real-Time Counter
A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic
Clock Controller before using the RTC. Refer to GCLK – Generic Clock Controller for details.
This generic clock is asynchronous to the user interface clock (CLK_RTC_APB). Due to this asynchronicity,
accessing certain registers will require synchronization between the clock domains. Refer to 19.6.8 Synchronization
for further details.
The RTC should not work with the Generic Clock Generator 0.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
19.5.4 DMA
Not applicable.
19.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupts requires the Interrupt
Controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
19.5.6 Events
The events are connected to the Event System.
Related Links
24. EVSYS – Event System
19.5.7 Debug Operation
When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue
operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.
19.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Read Request register (READREQ)
Status register (STATUS)
Debug register (DBGCTRL)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
19.5.9 Analog Connections
A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. For
details on recommended crystal characteristics and load capacitors, refer to Electrical Characteristics for details.
Related Links
37. Electrical Characteristics at 85℃
DS40001882G-page 229
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.6
Functional Description
19.6.1 Principle of Operation
The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a
specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit
counter depends on the RTC operating mode.
The RTC can function in one of these modes:
•
•
•
Mode 0 - COUNT32: RTC serves as 32-bit counter
Mode 1 - COUNT16: RTC serves as 16-bit counter
Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality
19.6.2 Basic Operation
19.6.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled
(CTRL.ENABLE=0):
•
•
•
•
Operating Mode bits in the Control register (CTRL.MODE)
Prescaler bits in the Control register (CTRL.PRESCALER)
Clear on Match bit in the Control register (CTRL.MATCHCLR)
Clock Representation bit in the Control register (CTRL.CLKREP)
The following register is enable-protected:
Event Control register (EVCTRL)
•
Any writes to these bits or registers when the RTC is enabled or being enabled (CTRL.ENABLE=1) will be discarded.
Writes to these bits or registers while the RTC is being disabled will be completed after the disabling is complete.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the RTC is enabled, it must be configured, as outlined by the following steps:
1. RTC operation mode must be selected by writing the Operating Mode bit group in the Control register
(CTRL.MODE)
2. Clock representation must be selected by writing the Clock Representation bit in the Control register
(CTRL.CLKREP)
3. Prescaler value must be selected by writing the Prescaler bit group in the Control register
(CTRL.PRESCALER)
The RTC prescaler divides the source clock for the RTC counter.
Note:ꢀ In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct
operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:
f
GCLK_RTC
PRESCALER
f
=
CLK_RTC_CNT
2
The frequency of the generic clock, GCLK_RTC, is given by fGCLK_RTC, and fCLK_RTC_CNT is the frequency of the
internal prescaled RTC clock, CLK_RTC_CNT.
19.6.2.2 Enabling, Disabling and Resetting
The RTC is enabled by setting the Enable bit in the Control register (CTRL.ENABLE=1). The RTC is disabled by
writing CTRL.ENABLE=0.
The RTC is reset by setting the Software Reset bit in the Control register (CTRL.SWRST=1). All registers in the RTC,
except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before
resetting it.
DS40001882G-page 230
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RTC – Real-Time Counter
19.6.3 Operating Modes
The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The
operating mode is selected by writing to the Operating Mode bit group in the Control register (CTRL.MODE).
19.6.3.1 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control register are zero (CTRL.MODE=00), the counter operates in 32-bit
Counter mode. The block diagram of this mode is shown in Figure 19-1. When the RTC is enabled, the counter will
increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of
0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and
Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match
occurs, the Compare 0interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the
next 0-to-1 transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is '1', the counter is cleared on the next counter
cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with
longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is '1', INTFLAG.CMP0
and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0.
19.6.3.2 16-Bit Counter (Mode 1)
When the RTC Operating Mode bits in the Control register (CTRL.MODE) are 1, the counter operates in 16-bit
Counter mode as shown in Figure 19-2. When the RTC is enabled, the counter will increment on every 0-to-1
transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value
of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the
Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0–1). When a compare
match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0–1) is
set on the next 0-to-1 transition of CLK_RTC_CNT.
19.6.3.3 Clock/Calendar (Mode 2)
When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in Figure 19-3. When the RTC is
enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC
prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time
is represented as:
•
•
•
Seconds
Minutes
Hours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control
register (CTRL.CLKREP). This bit can be changed only while the RTC is disabled.
Date is represented as:
•
•
•
Day as the numeric day of the month (starting at 1)
Month as the numeric month of the year (1 = January, 2 = February, etc.)
Year as a value counting the offset from a reference value that must be defined in software
The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the
reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59
December 31st of year 63, and then wrap to 00:00:00 January 1st of year 0. This will set the Overflow interrupt flag in
the Interrupt Flag Status and Clear registers (INTFLAG.OVF).
The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs,
the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next
0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a
DS40001882G-page 231
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RTC – Real-Time Counter
delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask
Selection bits in the Alarm
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register
(MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison
and which are ignored.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter
cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events
with longer periods than are possible with the prescaler events (see 19.6.9.1 Periodic Events). Note that when
CTRL.MATCHCLR is '1', INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match
with ALARM0.
19.6.4 DMA Operation
Not applicable.
19.6.5 Interrupts
The RTC has the following interrupt sources which are asynchronous interrupts and can wake-up the device from any
sleep mode.:
•
•
•
•
Overflow (INTFLAG.OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare n (INTFLAG.CMPn): Indicates a match between the counter value and the compare register.
Alarm n (INTFLAG.ALARMn): Indicates a match between the clock value and the alarm register.
Synchronization Ready (INTFLAG.SYNCRDY): Indicates an operation requires synchronization.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting
the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding
bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is
raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag
is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must
read the INTFLAG register to determine which interrupt condition is present.
Note:ꢀ Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector
Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
19.6.6 Events
The RTC can generate the following output events, which are generated in the same way as the corresponding
interrupts:
•
•
Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 19.6.9.1 Periodic Events for
details.
•
•
Compare n (CMPn): Indicates a match between the counter value and the compare register.
Alarm n (ALARMn): Indicates a match between the clock value and the alarm register.
Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for
details on configuring the event system.
Related Links
24. EVSYS – Event System
DS40001882G-page 232
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.6.7 Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be
used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting
the sleep mode.
An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly.
Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU will continue executing
right from the first instruction that followed the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the
event must be enabled and connected to an event channel with its interrupt enabled. See Event System for more
information.
Related Links
24. EVSYS – Event System
19.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the
Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY). If an
operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control register (CTRL.SWRST)
Enable bit in the Control register (CTRL.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
Counter Value register (COUNT)
Clock Value register (CLOCK)
Counter Period register (PER)
Compare n Value registers (COMPn)
Alarm n Value registers (ALARMn)
Frequency Correction register (FREQCORR)
Alarm n Mask register (MASKn)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
•
•
The Counter Value register (COUNT)
The Clock Value register (CLOCK)
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
19.6.9 Additional Features
19.6.9.1 Periodic Events
The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper
eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the eight Periodic Event Output
bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the
related bit in the prescaler, resulting in a periodic event frequency of:
DS40001882G-page 233
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
f
GCLK_RTC
f
=
PERIODIC
n + 3
2
fGCLK_RTC is the frequency of the internal prescaler clock, GCLK_RTC, and n is the position of the EVCTRL.PEREOn
bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is
shown in the figure below. Periodic events are independent of the prescaler setting used by the RTC counter, except
if CTRL.PRESCALER is zero. Then, no periodic events will be generated.
Figure 19-4.ꢀExample Periodic Events
GCLK_RTC
PEREO0
PEREO1
PEREO2
PEREO3
PEREO4
19.6.9.2 Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or
too-fast oscillator. Frequency correction requires that CTRL.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately
1 ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 4096
GCLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines
the number of times the adjustment is applied over 240 of these periods. The resulting correction is as follows:
Correction in ppm = (FREQCORR.VALUE / 4096 * 240) * 106ppm
This results in a resolution of 1.017 PPM.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A
positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce
counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events
from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the
previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction
value.
19.7
Register Summary
The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register
summary is presented for each of the three modes.
Table 19-1.ꢀMODE0 - Mode Register Summary
Offset
Name
Bit
Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
7:0
15:8
7:0
MATCHCLR
MODE[1:0]
ADDR[5:0]
ENABLE
PRESCALER[3:0]
SWRST
CTRL
READREQ
EVCTRL
15:8
7:0
RREQ
PEREO7
OVFEO
OVF
RCONT
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO0
CMP0
15:8
7:0
INTENCLR
INTENSET
INTFLAG
SYNCRDY
SYNCRDY
SYNCRDY
7:0
OVF
CMP0
7:0
OVF
CMP0
DS40001882G-page 234
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
RTC – Real-Time Counter
...........continued
Offset
Name
Bit
Pos.
0x09
0x0A
Reserved
STATUS
7:0
7:0
7:0
SYNCBUSY
SIGN
0x0B
0x0C
0x0D
...
DBGCTRL
DBGRUN
FREQCORR
VALUE[6:0]
Reserved
COUNT
0x0F
0x10
0x11
0x12
0x13
0x14
...
7:0
COUNT[7:0]
15:8
COUNT[15:8]
COUNT[23:16]
COUNT[31:24]
23:16
31:24
Reserved
COMP0
0x17
0x18
0x19
0x1A
0x1B
7:0
COMP[7:0]
COMP[15:8]
COMP[23:16]
COMP[31:24]
15:8
23:16
31:24
Table 19-2.ꢀMODE1 - Mode Register Summary
Offset
Name
Bit
Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
...
7:0
15:8
7:0
MODE[1:0]
ADDR[5:0]
ENABLE
PRESCALER[3:0]
SWRST
CTRL
READREQ
EVCTRL
15:8
7:0
RREQ
PEREO7
OVFEO
OVF
RCONT
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
CMPEO1
CMP1
PEREO0
CMPEO0
CMP0
15:8
7:0
INTENCLR
INTENSET
INTFLAG
SYNCRDY
SYNCRDY
SYNCRDY
7:0
OVF
CMP1
CMP0
7:0
OVF
CMP1
CMP0
Reserved
STATUS
7:0
7:0
7:0
SYNCBUSY
SIGN
DBGCTRL
FREQCORR
DBGRUN
VALUE[6:0]
Reserved
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
7:0
COUNT[7:0]
COUNT
15:8
COUNT[15:8]
Reserved
Reserved
7:0
PER[7:0]
PER
15:8
PER[15:8]
Reserved
Reserved
7:0
15:8
7:0
COMP[7:0]
COMP[15:8]
COMP[7:0]
COMP[15:8]
COMP0
COMP1
15:8
DS40001882G-page 235
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RTC – Real-Time Counter
Table 19-3.ꢀMODE2 - Mode Register Summary
Offset
Name
Bit
Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
...
7:0
15:8
7:0
MATCHCLR
CLKREP
MODE[1:0]
ADDR[5:0]
ENABLE
PRESCALER[3:0]
SWRST
CTRL
READREQ
EVCTRL
15:8
7:0
RREQ
PEREO7
OVFEO
OVF
RCONT
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
ALARMEO0
ALARM0
15:8
7:0
INTENCLR
INTENSET
INTFLAG
SYNCRDY
SYNCRDY
SYNCRDY
7:0
OVF
ALARM0
7:0
OVF
ALARM0
Reserved
STATUS
7:0
7:0
7:0
SYNCBUSY
SIGN
DBGCTRL
FREQCORR
DBGRUN
VALUE[6:0]
Reserved
0x0F
0x10
0x11
0x12
0x13
0x14
...
7:0
MINUTE[1:0]
SECOND[5:0]
15:8
HOUR[3:0]
MINUTE[5:2]
CLOCK
23:16
31:24
MONTH[1:0]
DAY[4:0]
HOUR[4]
MONTH[3:2]
YEAR[5:0]
Reserved
0x17
0x18
0x19
0x1A
0x1B
0x1C
7:0
15:8
23:16
31:24
7:0
MINUTE[1:0]
MONTH[1:0]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
ALARM0
MASK
DAY[4:0]
HOUR[4]
MONTH[3:2]
SEL[2:0]
YEAR[5:0]
19.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 236
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RTC – Real-Time Counter
19.8.1 Control - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x0000
Property:ꢀ Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
14
6
13
12
11
10
PRESCALER[3:0]
R/W R/W
9
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
7
5
4
3
2
1
ENABLE
R/W
0
MATCHCLR
MODE[1:0]
SWRST
Access
Reset
R/W
0
R/W
0
R/W
0
W
0
0
Bits 11:8 – PRESCALER[3:0]ꢀPrescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
PRESCALER[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB-0xF
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
CLK_RTC_CNT = GCLK_RTC/1
CLK_RTC_CNT = GCLK_RTC/2
CLK_RTC_CNT = GCLK_RTC/4
CLK_RTC_CNT = GCLK_RTC/8
CLK_RTC_CNT = GCLK_RTC/16
CLK_RTC_CNT = GCLK_RTC/32
CLK_RTC_CNT = GCLK_RTC/64
CLK_RTC_CNT = GCLK_RTC/128
CLK_RTC_CNT = GCLK_RTC/256
CLK_RTC_CNT = GCLK_RTC/512
CLK_RTC_CNT = GCLK_RTC/1024
Reserved
Bit 7 – MATCHCLRꢀClear on Match
This bit is valid only in Mode 0 and Mode 2.
This bit is not synchronized.
Value
Description
0
1
The counter is not cleared on a Compare/Alarm 0 match.
The counter is cleared on a Compare/Alarm 0 match.
Bits 3:2 – MODE[1:0]ꢀOperating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
MODE[1:0]
Name
Description
0x0
0x1
0x2
0x3
COUNT32
COUNT16
CLOCK
Mode 0: 32-bit Counter
Mode 1: 16-bit Counter
Mode 2: Clock/Calendar
Reserved
DS40001882G-page 237
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RTC – Real-Time Counter
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 238
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RTC – Real-Time Counter
19.8.2 Control - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x0000
Property:ꢀ Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
7
14
6
13
12
11
10
PRESCALER[3:0]
R/W R/W
9
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
5
4
3
2
1
ENABLE
R/W
0
MODE[1:0]
SWRST
Access
Reset
R/W
0
R/W
0
W
0
0
Bits 11:8 – PRESCALER[3:0]ꢀPrescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
PRESCALER[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB-0xF
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
CLK_RTC_CNT = GCLK_RTC/1
CLK_RTC_CNT = GCLK_RTC/2
CLK_RTC_CNT = GCLK_RTC/4
CLK_RTC_CNT = GCLK_RTC/8
CLK_RTC_CNT = GCLK_RTC/16
CLK_RTC_CNT = GCLK_RTC/32
CLK_RTC_CNT = GCLK_RTC/64
CLK_RTC_CNT = GCLK_RTC/128
CLK_RTC_CNT = GCLK_RTC/256
CLK_RTC_CNT = GCLK_RTC/512
CLK_RTC_CNT = GCLK_RTC/1024
Reserved
Bits 3:2 – MODE[1:0]ꢀOperating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
MODE[1:0]
Name
Description
0x0
0x1
0x2
0x3
COUNT32
COUNT16
CLOCK
Mode 0: 32-bit Counter
Mode 1: 16-bit Counter
Mode 2: Clock/Calendar
Reserved
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
DS40001882G-page 239
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RTC – Real-Time Counter
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 240
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RTC – Real-Time Counter
19.8.3 Control - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x0000
Property:ꢀ Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
PRESCALER[3:0]
R/W R/W
9
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
7
6
CLKREP
R/W
5
4
3
2
1
ENABLE
R/W
0
MATCHCLR
MODE[1:0]
SWRST
Access
Reset
R/W
0
R/W
0
R/W
0
W
0
0
0
Bits 11:8 – PRESCALER[3:0]ꢀPrescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
PRESCALER[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB-0xF
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
CLK_RTC_CNT = GCLK_RTC/1
CLK_RTC_CNT = GCLK_RTC/2
CLK_RTC_CNT = GCLK_RTC/4
CLK_RTC_CNT = GCLK_RTC/8
CLK_RTC_CNT = GCLK_RTC/16
CLK_RTC_CNT = GCLK_RTC/32
CLK_RTC_CNT = GCLK_RTC/64
CLK_RTC_CNT = GCLK_RTC/128
CLK_RTC_CNT = GCLK_RTC/256
CLK_RTC_CNT = GCLK_RTC/512
CLK_RTC_CNT = GCLK_RTC/1024
Reserved
Bit 7 – MATCHCLRꢀClear on Match
This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled.
This bit is not synchronized.
Value
Description
0
1
The counter is not cleared on a Compare/Alarm 0 match.
The counter is cleared on a Compare/Alarm 0 match.
Bit 6 – CLKREPꢀClock Representation
This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register.
This bit can be written only when the peripheral is disabled.
This bit is not synchronized.
Value
0
Description
24 Hour
1
12 Hour (AM/PM)
Bits 3:2 – MODE[1:0]ꢀOperating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
DS40001882G-page 241
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RTC – Real-Time Counter
MODE[1:0]
Name
Description
0x0
0x1
0x2
0x3
COUNT32
COUNT16
CLOCK
Mode 0: 32-bit Counter
Mode 1: 16-bit Counter
Mode 2: Clock/Calendar
Reserved
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 242
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RTC – Real-Time Counter
19.8.4 Read Request
Name:ꢀ
READREQ
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x02
0x0010
-
Bit
15
RREQ
W
14
13
5
12
4
11
3
10
2
9
1
8
0
RCONT
R/W
0
Access
Reset
0
Bit
7
6
ADDR[5:0]
Access
Reset
R
0
R
1
R
0
R
0
R
0
R
0
Bit 15 – RREQꢀRead Request
Writing a zero to this bit has no effect.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group
(READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
Bit 14 – RCONTꢀRead Continuously
Writing a zero to this bit disables continuous synchronization.
Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The
register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents
READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ bit is required to be set once
the RCONT bit is set.
This bit is cleared when an RTC register is written.
Note:ꢀ Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled
for a maximum of 6 APB + 6 RTC clock cycles (the time for the on-going read synchronization to complete).
Bits 5:0 – ADDR[5:0]ꢀAddress
These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK,
which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of
0x10.
DS40001882G-page 243
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RTC – Real-Time Counter
19.8.5 Event Control - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x04
0x0000
Property:ꢀ Enable-Protected, Write-Protected
Bit
15
OVFEO
R/W
0
14
13
12
11
10
9
8
CMPEO0
R/W
Access
Reset
0
Bit
7
PEREOx
R/W
6
PEREOx
R/W
5
PEREOx
R/W
4
PEREOx
R/W
3
PEREOx
R/W
2
PEREOx
R/W
1
PEREOx
R/W
0
PEREOx
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit 15 – OVFEOꢀOverflow Event Output Enable
Value
0
1
Description
Overflow event is disabled and will not be generated.
Overflow event is enabled and will be generated for every overflow.
Bit 8 – CMPEO0ꢀCompare 0 Event Output Enable
Value
Description
0
1
Compare 0 event is disabled and will not be generated.
Compare 0 event is enabled and will be generated for every compare match.
Bits 7,6,5,4,3,2,1,0 – PEREOx ꢀPeriodic Interval x Event Output Enable [x=7:0]
Value
Description
0
1
Periodic Interval x event is disabled and will not be generated.
Periodic Interval x event is enabled and will be generated.
DS40001882G-page 244
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RTC – Real-Time Counter
19.8.6 Event Control - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x04
0x0000
Property:ꢀ Enable-Protected, Write-Protected
Bit
15
OVFEO
R/W
0
14
13
12
11
10
9
CMPEOx
R/W
8
CMPEOx
R/W
Access
Reset
0
0
Bit
7
PEREOx
R/W
6
PEREOx
R/W
5
PEREOx
R/W
4
PEREOx
R/W
3
PEREOx
R/W
2
PEREOx
R/W
1
PEREOx
R/W
0
PEREOx
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit 15 – OVFEOꢀOverflow Event Output Enable
Value
0
1
Description
Overflow event is disabled and will not be generated.
Overflow event is enabled and will be generated for every overflow.
Bits 9,8 – CMPEOx ꢀCompare x Event Output Enable [x=1:0]
Value
Description
0
1
Compare x event is disabled and will not be generated.
Compare x event is enabled and will be generated for every compare match.
Bits 7,6,5,4,3,2,1,0 – PEREOx ꢀPeriodic Interval x Event Output Enable [x=7:0]
Value
Description
0
1
Periodic Interval x event is disabled and will not be generated.
Periodic Interval x event is enabled and will be generated.
DS40001882G-page 245
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RTC – Real-Time Counter
19.8.7 Event Control - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x04
0x0000
Property:ꢀ Enable-Protected, Write-Protected
Bit
15
OVFEO
R/W
0
14
13
12
11
10
9
8
ALARMEO0
Access
Reset
R/W
0
Bit
7
PEREOx
R/W
6
PEREOx
R/W
5
PEREOx
R/W
4
PEREOx
R/W
3
PEREOx
R/W
2
PEREOx
R/W
1
PEREOx
R/W
0
PEREOx
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit 15 – OVFEOꢀOverflow Event Output Enable
Value
0
1
Description
Overflow event is disabled and will not be generated.
Overflow event is enabled and will be generated for every overflow.
Bit 8 – ALARMEO0ꢀAlarm 0 Event Output Enable
Value
Description
0
1
Alarm 0 event is disabled and will not be generated.
Alarm 0 event is enabled and will be generated for every alarm.
Bits 7,6,5,4,3,2,1,0 – PEREOx ꢀPeriodic Interval x Event Output Enable [x=7:0]
Value
Description
0
1
Periodic Interval x event is disabled and will not be generated.
Periodic Interval x event is enabled and will be generated.
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RTC – Real-Time Counter
19.8.8 Interrupt Enable Clear - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x06
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
0
CMP0
R/W
0
OVF
R/W
0
Access
Reset
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow
interrupt flag is set.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
Synchronization Ready interrupt flag is set.
Bit 0 – CMP0ꢀCompare 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt.
Value
Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare x
interrupt flag is set.
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RTC – Real-Time Counter
19.8.9 Interrupt Enable Clear - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x06
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
CMPx
R/W
0
0
CMPx
R/W
0
OVF
R/W
0
Access
Reset
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow
interrupt flag is set.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
Synchronization Ready interrupt flag is set.
Bits 1,0 – CMPx ꢀCompare x Interrupt Enable [x=1:0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt.
Value
Description
0
The Compare x interrupt is disabled.
1
The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x
interrupt flag is set.
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RTC – Real-Time Counter
19.8.10 Interrupt Enable Clear - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x06
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
0
ALARM0
R/W
OVF
R/W
0
Access
Reset
0
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow
interrupt flag is set.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
Value
Description
0
1
The synchronization ready interrupt is disabled.
The synchronization ready interrupt is enabled, and an interrupt request will be generated when the
Synchronization Ready interrupt flag is set.
Bit 0 – ALARM0ꢀAlarm 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Alarm 0 interrupt.
Value
Description
0
The Alarm 0 interrupt is disabled.
1
The Alarm 0 interrupt is enabled, and an interrupt request will be generated when the Alarm 0 interrupt
flag is set.
DS40001882G-page 249
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.11 Interrupt Enable Set - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x07
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
0
CMP0
R/W
0
OVF
R/W
0
Access
Reset
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
Value
Description
0
1
The overflow interrupt is disabled.
The overflow interrupt is enabled.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready
interrupt.
Value
Description
0
1
The synchronization ready interrupt is disabled.
The synchronization ready interrupt is enabled.
Bit 0 – CMP0ꢀCompare 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
Value
Description
0
1
The compare 0 interrupt is disabled.
The compare 0 interrupt is enabled.
DS40001882G-page 250
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.12 Interrupt Enable Set - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x07
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
CMPx
R/W
0
0
CMPx
R/W
0
OVF
R/W
0
Access
Reset
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt.
Value
Description
0
1
The overflow interrupt is disabled.
The overflow interrupt is enabled.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready
interrupt.
Value
Description
0
1
The synchronization ready interrupt is disabled.
The synchronization ready interrupt is enabled.
Bits 1,0 – CMPx ꢀCompare x Interrupt Enable [x=1:0]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt.
Value
Description
0
1
The compare x interrupt is disabled.
The compare x interrupt is enabled.
DS40001882G-page 251
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.13 Interrupt Enable Set - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x07
0x00
Property:ꢀ Write-Protected
Bit
7
6
SYNCRDY
R/W
5
4
3
2
1
0
ALARM0
R/W
OVF
R/W
0
Access
Reset
0
0
Bit 7 – OVFꢀOverflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
Value
Description
0
1
The overflow interrupt is disabled.
The overflow interrupt is enabled.
Bit 6 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready
interrupt.
Value
Description
0
1
The synchronization ready interrupt is disabled.
The synchronization ready interrupt is enabled.
Bit 0 – ALARM0ꢀAlarm 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt.
Value
Description
0
1
The alarm 0 interrupt is disabled.
The alarm 0 interrupt is enabled.
DS40001882G-page 252
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.14 Interrupt Flag Status and Clear - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x08
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
CMP0
R/W
0
OVF
R/W
0
SYNCRDY
Access
Reset
R/W
0
Bit 7 – OVFꢀOverflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 6 – SYNCRDYꢀSynchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/
SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 0 – CMP0ꢀCompare 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
DS40001882G-page 253
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.15 Interrupt Flag Status and Clear - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x08
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
CMPx
R/W
0
0
CMPx
R/W
0
OVF
R/W
0
SYNCRDY
Access
Reset
R/W
0
Bit 7 – OVFꢀOverflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 6 – SYNCRDYꢀSynchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/
SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bits 1,0 – CMPx ꢀCompare x [x=1:0]
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition and an interrupt request
will be generated if INTENCLR/SET.CMPx is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare x interrupt flag.
DS40001882G-page 254
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.16 Interrupt Flag Status and Clear - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x08
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
ALARM0
R/W
OVF
R/W
0
SYNCRDY
Access
Reset
R/W
0
0
Bit 7 – OVFꢀOverflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 6 – SYNCRDYꢀSynchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/
SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 0 – ALARM0ꢀAlarm 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an interrupt
request will be generated if INTENCLR/SET.ALARM0 is also one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Alarm 0 interrupt flag.
DS40001882G-page 255
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.17 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0A
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
DS40001882G-page 256
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.18 Debug Control
Name:ꢀ
DBGCTRL
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x0B
0x00
-
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀRun During Debug
This bit is not reset by a software reset.
Writing a zero to this bit causes the RTC to halt during debug mode.
Writing a one to this bit allows the RTC to continue normal operation during debug mode.
DS40001882G-page 257
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.19 Frequency Correction
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FREQCORR
0x0C
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
SIGN
R/W
0
6
5
4
3
VALUE[6:0]
R/W
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – SIGNꢀCorrection Sign
Value
Description
0
1
The correction value is positive, i.e., frequency will be decreased.
The correction value is negative, i.e., frequency will be increased.
Bits 6:0 – VALUE[6:0]ꢀCorrection Value
These bits define the amount of correction applied to the RTC prescaler.
1–127: The RTC frequency is adjusted according to the value.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
DS40001882G-page 258
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.20 Counter Value - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x10
0x00000000
Property:ꢀ Read-Synchronized, Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COUNT[31:0]ꢀCounter Value
These bits define the value of the 32-bit RTC counter.
DS40001882G-page 259
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.21 Counter Value - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x10
0x0000
Property:ꢀ Read-Synchronized, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COUNT[15:0]ꢀCounter Value
These bits define the value of the 16-bit RTC counter.
DS40001882G-page 260
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.22 Clock Value - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CLOCK
0x10
0x00000000
Property:ꢀ Read-Synchronized, Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
YEAR[5:0]
MONTH[3:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
DAY[4:0]
R/W
18
17
16
HOUR[4]
R/W
MONTH[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
15
14
13
12
11
10
9
8
HOUR[3:0]
MINUTE[5:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
MINUTE[1:0]
SECOND[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:26 – YEAR[5:0]ꢀYear
The year offset with respect to the reference year (defined in software).
The year is considered a leap year if YEAR[1:0] is zero.
Bits 25:22 – MONTH[3:0]ꢀMonth
1 – January
2 – February
...
12 – December
Bits 21:17 – DAY[4:0]ꢀDay
Day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year.
Bits 16:12 – HOUR[4:0]ꢀHour
When CTRL.CLKREP is zero, the Hour bit group is in 24-hour format, with values 0-23. When CTRL.CLKREP is one,
HOUR[3:0] has values 1-12 and HOUR[4] represents AM (0) or PM (1).
Table 19-4.ꢀHour
HOUR[4:0]
CLOCK.HOUR[4]
CLOCK.HOUR[3:0]
Description
0
0x00 - 0x17
0x18 - 0x1F
0
Hour (0 - 23)
Reserved
Reserved
1
0x0
0x1 - 0xC
0xD - 0xF
0x0
AM Hour (1 - 12)
Reserved
Reserved
1
0x1 - 0xC
0xF - 0xF
PM Hour (1 - 12)
Reserved
DS40001882G-page 261
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SAM D21/DA1 Family
RTC – Real-Time Counter
Bits 11:6 – MINUTE[5:0]ꢀMinute
0 – 59.
Bits 5:0 – SECOND[5:0]ꢀSecond
0– 59.
DS40001882G-page 262
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.23 Counter Period - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PER
0x14
0x0000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PER[15:8]
PER[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PER[15:0]ꢀCounter Period
These bits define the value of the 16-bit RTC period.
DS40001882G-page 263
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RTC – Real-Time Counter
19.8.24 Compare n Value - MODE0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COMP
0x18
0x00000000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COMP[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
COMP[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
COMP[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COMP[31:0]ꢀCompare Value
The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle, and the counter value is cleared if CTRL.MATCHCLR is one.
DS40001882G-page 264
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.25 Compare n Value - MODE1
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COMPn
0x18+n*0x2 [n=0..1]
0x0000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COMP[15:8]
COMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COMP[15:0]ꢀCompare Value
The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle.
DS40001882G-page 265
Complete Datasheet
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SAM D21/DA1 Family
RTC – Real-Time Counter
19.8.26 Alarm 0 Value - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ALARM0
0x18
0x00000000
Property:ꢀ Write-Protected, Write-Synchronized
The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set
by MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one.
Bit
31
30
29
28
27
26
25
24
YEAR[5:0]
MONTH[3:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
DAY[4:0]
R/W
18
17
16
HOUR[4]
R/W
MONTH[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
15
14
13
12
11
10
9
8
HOUR[3:0]
MINUTE[5:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
MINUTE[1:0]
SECOND[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:26 – YEAR[5:0]ꢀYear
The alarm year. Years are only matched if MASKn.SEL is 6.
Bits 25:22 – MONTH[3:0]ꢀMonth
The alarm month. Months are matched only if MASKn.SEL is greater than 4.
Bits 21:17 – DAY[4:0]ꢀDay
The alarm day. Days are matched only if MASKn.SEL is greater than 3.
Bits 16:12 – HOUR[4:0]ꢀHour
The alarm hour. Hours are matched only if MASKn.SEL is greater than 2.
Bits 11:6 – MINUTE[5:0]ꢀMinute
The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1.
Bits 5:0 – SECOND[5:0]ꢀSecond
The alarm second. Seconds are matched only if MASKn.SEL is greater than 0.
DS40001882G-page 266
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RTC – Real-Time Counter
19.8.27 Alarm n Mask - MODE2
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
MASK
0x1C
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
SEL[2:0]
R/W
0
0
Access
Reset
R/W
0
R/W
0
Bits 2:0 – SEL[2:0]ꢀAlarm Mask Selection
These bits define which bit groups of Alarm n are valid.
SEL[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
OFF
SS
MMSS
HHMMSS
DDHHMMSS
MMDDHHMMSS
YYMMDDHHMMSS
Alarm Disabled
Match seconds only
Match seconds and minutes only
Match seconds, minutes, and hours only
Match seconds, minutes, hours, and days only
Match seconds, minutes, hours, days, and months only
Match seconds, minutes, hours, days, months, and years
Reserved
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DMAC – Direct Memory Access Controller
20.
DMAC – Direct Memory Access Controller
20.1
Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access (DMA) engine and a Cyclic
Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals and therefore,
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up
CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication
modules.
The DMA part of the DMAC has several DMA channels, which can receive different types of transfer triggers and
generate transfer requests from the DMA channels to the arbiter (Refer to the Block Diagram). The arbiter will select
one DMA channel at a time to act as the active channel. When an active channel has been selected, the fetch engine
of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel,
which will then execute the data transmission.
An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC
will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the
higher prioritized channel a start transfer as the new active channel. Once a DMA channel is done with its transfer,
interrupts and events can be generated optionally.
The DMAC has four bus interfaces:
•
•
•
The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be
started or continued.
•
The write-back bus is used to write the transfer descriptor back to SRAM.
All buses are AHB host interfaces except the AHB/APB Bridge bus, which is an APB client interface.
The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective
action, such as requesting the data to be sent again or simply not using the incorrect data.
20.2
Features
•
Data Transfer From:
– Peripheral-to-peripheral
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
•
Transfer Trigger Sources:
– Software
– Events from Event System
– Dedicated requests from peripherals
SRAM-based Transfer Descriptors:
– Single transfer using one descriptor
– Multi-buffer or Circular Buffer modes by linking multiple descriptors
Up to 12 Channels:
•
•
– Enable 12 independent transfers
– Automatic descriptor fetch for each channel
– Suspend/resume operation support for each channel
Flexible Arbitration Scheme:
•
– 4 configurable priority levels for each channel
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DMAC – Direct Memory Access Controller
– Fixed or round-robin priority scheme within each priority level
•
•
From 1 to 256KB Data Transfer in a Single Block Transfer
Multiple Addressing Modes:
– Static
– Configurable increment scheme
•
•
•
Optional Interrupt Generation:
– On block transfer complete
– On error detection
– On channel suspend
4 Event Inputs:
– One event input for each of the 4 least significant DMA channels
– Can be selected to trigger normal transfers, periodic transfers or conditional transfers
– Can be selected to suspend or resume channel operation
4 Event Outputs:
– One output event for each of the 4 least significant DMA channels
– Selectable generation on AHB, block, or transaction transfer complete
Error Management Supported by Write-back Function:
– Dedicated write-back memory section for each channel to store ongoing descriptor transfer
CRC Polynomial Software Selectable to:
– CRC-16 (CRC-CCITT)
•
•
®
– CRC-32 (IEEE 802.3)
20.3
Block Diagram
Figure 20-1.ꢀDMAC Block Diagram
CPU
M
HIGH SPEED
BUS MATRIX
S
SRAM
S
M
AHB/APB
Bridge
DMAC
HOST
Fetch
Engine
DMA Channels
Channel n
Interrupts
Events
Channel 1
Channel 0
Transfer
Triggers
Active
Channel
Interrupt /
Events
Arbiter
n
CRC
Engine
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DMAC – Direct Memory Access Controller
20.4
20.5
Signal Description
Not applicable.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
20.5.1 I/O Lines
Not applicable.
20.5.2 Power Management
The DMAC will continue to operate in IDLE 0 mode where the selected source clock is running. The DMAC’s
interrupts can be used to wake-up the device from Sleep modes. Events connected to the event system can trigger
other operations in the system without exiting Sleep modes. On hardware or software Reset, all registers are set to
their Reset value.
Related Links
16. PM – Power Manager
20.5.3 Clocks
The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Power Manager before using the
DMAC.
An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the
power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in Peripheral Clock
Masking.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be
divided by a prescaler and may run even when the module clock is turned off.
Related Links
16.6.2.6 Peripheral Clock Masking
20.5.4 DMA
Not applicable.
20.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt
controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
20.5.6 Events
Not applicable.
Related Links
24. EVSYS – Event System
20.5.7 Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue
operation during debugging. Refer to 20.8.6 DBGCTRL for details.
20.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
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DMAC – Direct Memory Access Controller
•
•
•
Interrupt Pending register (INTPEND)
Channel ID register (CHID)
Channel Interrupt Flag Status and Clear register (CHINTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
20.5.9 Analog Connections
Not applicable.
20.6
Functional Description
20.6.1 Principle of Operation
The DMAC consists of a DMA module and a CRC module.
20.6.1.1 DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data
transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers.
The following figure shows the relationship between the different transfer sizes:
Figure 20-2.ꢀDMA Transfer Sizes
Link Enabled
Link Enabled
Link Enabled
Beat transfer
Block transfer
DMA transaction
Burst transfer
•
•
Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit
group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. A burst transfer
is atomic, cannot be interrupted and the length of the burst is selected by writing the Burst Length bit group in
each Channel n Control A register (CHCTRLA.BURSTLEN).
•
•
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k
beats. A block transfer can be interrupted, in contrast to the burst transfer.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second
and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a
linked list.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM.
For further details on the transfer descriptor refer to 20.6.2.3 Transfer Descriptors.
The figure above shows several block transfers linked together, which are called linked descriptors. For further
information about linked descriptors, refer to 20.6.3.1 Linked Descriptors.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be
configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer
trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels
with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel.
The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer
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DMAC – Direct Memory Access Controller
descriptor. A current transaction can be interrupted by a higher prioritized channel after each burst transfer, but will
resume the block transfer when the according DMA channel is granted access as the active channel again.
For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an
optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA
channel will either be suspended or disabled.
20.6.1.2 CRC
The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE
802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 20.6.3.7 CRC Operation for
details.
20.6.2 Basic Operation
20.6.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is
disabled (CTRL.DMAENABLE=0):
•
•
Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR)
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
•
Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE=0):
•
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration
Level bit (CHCTRLB.LVL)
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
•
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE=0):
•
•
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the DMAC is enabled it must be configured, as outlined by the following steps:
•
•
•
The SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the Write-Back
Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be
configured, as outlined by the following steps:
•
DMA channel configurations
– The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
– Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
– Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
•
Transfer Descriptor
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DMAC – Direct Memory Access Controller
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
– The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
– Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
– Source address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register
– Destination address for the block transfer must be selected by writing the Block Transfer Destination
Address (DSTADDR) register
If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following
steps:
•
•
•
The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register
(CRCCTRL.CRCSRC)
The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control
register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the
CRC Control register (CRCCTRL.CRCBEATSIZE)
20.6.2.2 Enabling, Disabling, and Resetting
The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is
disabled by writing a '0' to CTRL.DMAENABLE.
A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1',
after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA
channel is disabled by writing a '0' to CHCTRLA.ENABLE.
The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is
disabled by writing a '0' to CTRL.CRCENABLE.
The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC
and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state.
A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register
(CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID
register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be
disabled in order for the reset to take effect.
20.6.2.3 Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be executed.
Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first
transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first
block transfer of a transaction.
All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address
(BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the
descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels.
As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below), all first transfer descriptors
must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their
channel number. For further details on linked descriptors, refer to 20.6.3.1 Linked Descriptors.
The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block
transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be
stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number.
The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors,
refer to 20.6.3.1 Linked Descriptors.
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DMAC – Direct Memory Access Controller
Figure 20-3.ꢀMemory Sections
0x00000000
DSTADDR
SRCADDR
DESCADDR
Channel 0 – Last Descriptor
BTCNT
BTCTRL
DESCADDR
DSTADDR
SRCADDR
DESCADDR
Channel 0 – Descriptor n-1
BTCNT
BTCTRL
Descriptor Section
Channel n – First Descriptor
DESCADDR
DSTADDR
SRCADDR
Channel 2 – First Descriptor
Channel 1 – First Descriptor
Channel 0 – First Descriptor
BASEADDR
BTCNT
BTCTRL
Write-Back Section
Undefined
Undefined
Undefined
Channel n Ongoing Descriptor
Channel 2 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 0 Ongoing Descriptor
WRBADDR
Undefined
Undefined
Device Memory Space
The size of the descriptor and write-back memory sections is dependent on the number of the most significant
enabled DMA channel m, as shown below:
Size = 128bits ⋅ m + 1
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share
memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same
transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having
descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency
from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced.
20.6.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request
to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of
channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers
(PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel
will be the next active channel. The active channel is the DMA channel being granted access to perform its
next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit
PENDCH.PENDCHx will be cleared. See also the following figure.
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DMAC – Direct Memory Access Controller
If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in the
Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted burst
transfers.
When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with
pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel
and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the
corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger,
suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending
channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it
will be added to the queue of pending channels again.
If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the
queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared.
Figure 20-4.ꢀArbiter Overview
Arbiter
Channel Pending
Priority
Channel Suspend
decoder
Channel 0
Channel Priority Level
Channel Burst Done
Burst Done
Active
Channel
Channel Pending
Channel Suspend
Transfer Request
Channel Number
Channel N
Channel Priority Level
Channel Burst Done
Active.LVLEXx
Level Enable
PRICTRLx.LVLPRI
CTRL.LVLENx
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in
the Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the
Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels
are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level
number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1).
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically:
Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in
the Priority Control 0 register (PRICTRL0.RRLVLENx).
When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as
shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being
granted access as the active channel. This can be avoided using a dynamic arbitration scheme.
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DMAC – Direct Memory Access Controller
Figure 20-5.ꢀStatic Priority Scheduling
Channel 0
Highest Priority
Lowest Channel
.
.
.
Channel x
Channel x+1
.
.
.
Lowest Priority
Channel N
Highest Channel
Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx.
The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of
the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to
a channel within the same priority level, as shown in Figure 20-6. The channel number of the last channel being
granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control
0 register (PRICTRL0.LVLPRIx) for the corresponding priority level.
Figure 20-6.ꢀDynamic (Round-Robin) Priority Scheduling
Channel x last acknowledge request
Channel 0
Channel (x+1) last acknowledge request
Channel 0
.
.
.
Channel x
Channel x
Lowest Priority
Highest Priority
Channel x+1
Channel x+1
Lowest Priority
Channel x+2
Highest Priority
.
.
.
Channel N
Channel N
20.6.2.5 Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its
corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as
the active channel.
Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the
transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal
memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor
memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back
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DMAC – Direct Memory Access Controller
memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source
address and write it to the current destination address. For further details on how the current source and destination
addresses are calculated, refer to the section on Addressing.
The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again,
the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a
burst transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will
perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the block
transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA
channel is fetched into the internal memory of the active channel.
When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will
be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional
interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated
if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register
(DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending
on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If
the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer
descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and
write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.
20.6.2.6 Transfer Triggers and Actions
A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the
DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a
peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B
(CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor
is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a
list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor
in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block
transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions
can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer
(CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0).
Figure 20-7 shows an example where triggers are used with two linked block descriptors.
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DMAC – Direct Memory Access Controller
Figure 20-7.ꢀTrigger Action and Transfers
Beat Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Block Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
BEAT
Block Transfer
BEAT
Data Transfer
Transaction Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
BEAT
Block Transfer
BEAT
Data Transfer
If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request
will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one
pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already
pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels
register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
20.6.2.7 Addressing
Each block transfer needs to have both a source address and a destination address defined. The source address
is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the
Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer,
or both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation
Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation
is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register
(BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block
Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation
will be the size of one beat.
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When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:
If BTCTRL.STEPSEL=1:
STEPSIZE
SRCADDR = SRCADDR
+ BTCNT ⋅ BEATSIZE + 1 ⋅ 2
START
If BTCTRL.STEPSEL=0:
SRCADDR = SRCADDR
+ BTCNT ⋅ BEATSIZE + 1
START
•
•
•
•
SRCADDRSTART is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
The following figure shows an example where DMA channel 0 is configured to increment the source address
by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the
source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the
destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0).
Figure 20-8.ꢀSource Address Increment
SRC Data Buffer
a
b
c
d
e
f
Incrementation for the destination address of a block transfer is enabled by setting the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the
incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step
size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat.
When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and
calculated as follows:
STEPSIZE
where BTCTRL.STEPSEL is zero
DSTADDR = DSTADDR
+ BTCNT • BEATSIZE + 1 • 2
+ BTCNT • BEATSIZE + 1
START
START
DSTADDR = DSTADDR
where BTCTRL.STEPSEL is one
•
•
•
•
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
The followiong figure shows an example where DMA channel 0 is configured to increment destination address
by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two
beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both
channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0).
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Figure 20-9.ꢀDestination Address Increment
DST Data Buffer
a
b
c
d
20.6.2.8 Error Handling
If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled
and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register
(CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not
be decremented and its current value is written-back in the write-back memory section before the channel is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA
fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation
is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register
(CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR)
is set. If enabled, the optional suspend interrupt is generated.
20.6.3 Additional Features
20.6.3.1 Linked Descriptors
A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of
several block transfers it is done with the help of linked descriptors.
Figure 20-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel
0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor
Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is
continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and
DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched
from SRAM, refer to section 20.6.2.5 Data Transmission.
20.6.3.1.1 Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with
DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of
the current last descriptor to the address of the newly created descriptor.
20.6.3.1.2 Modifying a Descriptor in a List
In order to add descriptors to a linked list, the following actions must be performed:
1. Enable the Suspend interrupt for the DMA channel.
2. Enable the DMA channel.
3. Reserve memory space in SRAM to configure a new descriptor.
4. Configure the new descriptor:
– Set the next descriptor address (DESCADDR)
– Set the destination address (DSTADDR)
– Set the source address (SRCADDR)
– Configure the block transfer control (BTCTRL) including
•
Optionally enable the Suspend block action
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•
Set the descriptor VALID bit
5. Clear the VALID bit for the existing list and for the descriptor which has to be updated.
6. Read DESCADDR from the Write-Back memory.
– If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR is wrong):
•
•
•
•
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1'
Optionally enable the Resume software command
– If the DMA is executing the same descriptor as the one which requires changes:
•
•
•
•
•
•
Set the Channel Suspend software command and wait for the Suspend interrupt
Update the next descriptor address (DESCRADDR) in the write-back memory
Clear the interrupt sources and set the Resume software command
Update the DESCADDR location of the descriptor from the List
Optionally clear the Suspend block action
Set the descriptor VALID bit to '1'
7. Go to step 4 if needed.
20.6.3.1.3 Adding a Descriptor Between Existing Descriptors
To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the
DMA must be identified.
1. If DMA is executing descriptor B, descriptor C cannot be inserted.
2. If DMA has not started to execute descriptor A, follow the steps:
2.1.
2.2.
2.3.
2.4.
Set the descriptor A VALID bit to '0'.
Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B.
Set the DESCADDR value of descriptor C to point to descriptor B.
Set the descriptor A VALID bit to '1'.
3. If DMA is executing descriptor A:
3.1.
3.2.
3.3.
Apply the software suspend command to the channel and
Perform steps 2.1 through 2.4.
Apply the software resume command to the channel.
20.6.3.2 Channel Suspend
The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the
Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the
channel operation is suspended and the suspend command is automatically cleared.
When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set
(CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated.
By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register
(BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer.
The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the
arbitration scheme.
If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and
the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set.
Note:ꢀ Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be
suspended, the internal suspend command will be ignored.
For more details on transfer descriptors, refer to section 20.6.2.3 Transfer Descriptors.
20.6.3.3 Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in the Command bit field
of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation
resumes from where it previously stopped when the Resume command is detected. When the Resume command is
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issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal
operation.
Figure 20-10.ꢀChannel Suspend/Resume Operation
CHENn
Descriptor 2
(suspend enabled)
Descriptor 0
(suspend disabled)
Descriptor 1
(suspend enabled)
Descriptor 3
(last)
Memory Descriptor
Channel
suspended
Fetch
Block
Block
Block
Block
Transfer 3
Transfer
Transfer 1
Transfer 0
Transfer 2
Resume Command
Suspend skipped
20.6.3.4 Event Input Actions
The event input actions are available only on the least significant DMA channels. For details on channels with event
input support, refer to the in the Event system documentation.
Before using event input actions, the event controller must be configured first according to the following table, and the
Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also
to 20.6.6 Events.
Table 20-1.ꢀEvent Input Action
Action
CHCTRLB.EVACT
NOACT
CHCTRLB.TRGSRC
-
None
Normal Transfer
TRIG
DISABLE
Conditional Transfer on Strobe
Conditional Transfer
Conditional Block Transfer
Channel Suspend
Channel Resume
Skip Next Block Suspend
TRIG
any peripheral
CTRIG
CBLOCK
SUSPEND
RESUME
SSKIP
Normal Transfer
The event input is used to trigger a beat or burst transfer on peripherals.
The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit
in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels
register (20.8.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event
trigger is lost.
The figure below shows an example where beat transfers are enabled by internal events.
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Figure 20-11.ꢀBeat Event Trigger Action
CHENn
Peripheral Trigger
Trigger Lost
Event
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Conditional Transfer on Strobe
The event input is used to trigger a transfer on peripherals with pending transfer requests. This event action is
intended to be used with peripheral triggers, e.g. for timed communication protocols or periodic transfers between
peripherals: only when the peripheral trigger coincides with the occurrence of a (possibly cyclic) event the transfer is
issued.
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when
the previous trigger action is completed (i.e. the channel is not pending) and when an active event is received. If the
peripheral trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When
both event and peripheral transfer trigger are active, both CHSTATUS.PEND and 20.8.13 PENDCH.PENDCHn are
set. A software trigger will now trigger a transfer.
The figure below shows an example where the peripheral beat transfer is started by a conditional strobe event action.
Figure 20-12.ꢀPeriodic Event with Beat Peripheral Triggers
Trigger Lost
Trigger Lost
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
Conditional Transfer
The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. For example,
this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and
the second peripheral is the source of the trigger.
Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally,
the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending Channel n Bit in the Pending
Channels register is set (20.8.13 PENDCH.PENDCHn), and the event is acknowledged. A software trigger will now
trigger a transfer.
The figure below shows an example where conditional event is enabled with peripheral beat trigger requests.
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Figure 20-13.ꢀConditional Event with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
BEAT
Conditional Block Transfer
The event input is used to trigger a conditional block transfer on peripherals.
Before starting transfers within a block, an event must be received. When received, the event is acknowledged when
the block transfer is completed. A software trigger will trigger a transfer.
The figure below shows an example where conditional event block transfer is started with peripheral beat trigger
requests.
Figure 20-14.ꢀConditional Block Transfer with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
Channel Suspend
The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB
access is completed. For further details on Channel Suspend, refer to 20.6.3.2 Channel Suspend.
Channel Resume
The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the
event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to
20.6.3.2 Channel Suspend.
Skip Next Block Suspend
This event can be used to skip the next block suspend action. If the channel is suspended before the event rises,
the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is
detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel
continues the operation (not suspended) and the event is acknowledged.
Related Links
24.8.3 USER
20.6.3.5 Event Output Selection
Event output selection is available only for the least significant DMA channels. The pulse width of an event output
from a channel is one AHB clock cycle.
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DMAC – Direct Memory Access Controller
The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control
B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in
the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer
(BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a
transaction is complete, the block event selection must be set in the last transfer descriptor only.
Figure 20-15 shows an example where the event output generation is enabled in the first block transfer, and disabled
in the second block.
Figure 20-15.ꢀEvent Output Generation
Beat Event Output
Block Transfer
Block Transfer
Data Transfer
Event Output
BEAT
BEAT
BEAT
BEAT
Block Event Output
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
Event Output
20.6.3.6 Aborting Transfers
Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is
also possible to abort all ongoing or pending transfers by disabling the DMAC.
When a DMA channel disable request or DMAC disable request is detected:
•
Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the
write-back memory section is updated. This prevents transfer corruption before the channel is disabled.
•
All other enabled channels will be disabled in the next clock cycle.
The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the
channel is disabled.
The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire
DMAC module is disabled.
20.6.3.7 CRC Operation
A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is commonly used
to determine whether the data during a transmission, or data present in data and program memories has been
corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can
be appended to the data and used as a checksum.
When the data is received, the device or application repeats the calculation: If the new CRC result does not match
the one calculated earlier, the block contains a data error. The application will then detect this and may take a
corrective action, such as requesting the data to be sent again or simply not using the incorrect data.
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The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32
(IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single
alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts.
•
CRC-16:
– Polynomial: x16+ x12+ x5+ 1
– Hex value: 0x1021
•
CRC-32:
– Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1
– Hex value: 0x04C11DB7
The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be
selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine
then takes data input from the selected source and generates a checksum based on these data. The checksum is
available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read
is bit reversed and complemented, as shown in Figure 20-16.
The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register
(CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as
data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface,
the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-,
or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN
register and the CRC engine will operate on the input data in a byte by byte manner.
Figure 20-16.ꢀCRC Generator Block Diagram
DMAC
Channels
CRCDATAIN
CRCCTRL
8
16
8
32
CRC-16
CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum
read
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CRC on CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a
DMA
data
DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data
passing through the DMA channel. The checksum is available for readout once the DMA transaction is
completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these
data through a DMA channel. If the latter is done, the destination register for the DMA data can be the
data input (CRCDATAIN) register in the CRC engine.
CRC using the I/O
interface
Before using the CRC engine with the I/O interface, the application must set the CRC Beat
Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer
type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to
the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU,
and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the
CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the
CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.
20.6.4 DMA Operation
Not applicable.
20.6.5 Interrupts
The DMAC channels have the following interrupt sources:
•
•
•
Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
20.6.2.5 Data Transmission for details.
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid
descriptor has been fetched. Refer to 20.6.2.8 Error Handling for details.
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
20.6.3.2 Channel Suspend and 20.6.2.5 Data Transmission for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status
and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and
disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or
the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt
requests are ORed together on system level to generate one combined interrupt request to the NVIC.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending
interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which
interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register
(INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note:ꢀ Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
11.2 Nested Vector Interrupt Controller
20.6.6 Events
The DMAC can generate the following output events:
•
Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat
transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for
details.
Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event
configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event.
The DMAC can take the following actions on an input event:
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•
•
•
•
•
•
•
Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Increase Priority (INCPRI): increase channel priority
Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event.
Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for
incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the
incoming events. For further details on event input actions, refer to Event Input Actions.
Note:ꢀ Event input and outputs are not available for every channel. Refer to the Features section for more
information.
Related Links
24. EVSYS – Event System
20.6.7 Sleep Mode Operation
The DMAC will continue to operate in IDLE 0 sleep mode. It does not perform transfers in IDLE 1 and IDLE 2
sleep modes, since the AHB clocks are stopped. In Standby Sleep mode, the DMAC will be internally disabled, but
maintains its current configuration.
20.6.8 Synchronization
Not applicable.
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20.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
7:0
CRCENABLE DMAENABLE
LVLENx2 LVLENx1
SWRST
0x00
0x02
CTRL
LVLENx3
LVLENx0
CRCPOLY[1:0]
CRCSRC[5:0]
CRCBEATSIZE[1:0]
CRCCTRL
15:8
7:0
CRCDATAIN[7:0]
15:8
23:16
31:24
7:0
CRCDATAIN[15:8]
CRCDATAIN[23:16]
CRCDATAIN[31:24]
CRCCHKSUM[7:0]
CRCCHKSUM[15:8]
CRCCHKSUM[23:16]
CRCCHKSUM[31:24]
0x04
0x08
CRCDATAIN
15:8
23:16
31:24
7:0
CRCCHKSUM
0x0C
0x0D
0x0E
0x0F
CRCSTATUS
DBGCTRL
QOSCTRL
Reserved
CRCZERO
CRCBUSY
DBGRUN
WRBQOS[1:0]
7:0
7:0
DQOS[1:0]
FQOS[1:0]
7:0
SWTRIGn[7:0]
15:8
SWTRIGn[11:8]
0x10
0x14
SWTRIGCTRL
PRICTRL0
23:16
31:24
7:0
RRLVLEN0
RRLVLEN1
RRLVLEN2
RRLVLEN3
LVLPRI0[3:0]
LVLPRI1[3:0]
LVLPRI2[3:0]
LVLPRI3[3:0]
15:8
23:16
31:24
0x18
...
Reserved
INTPEND
Reserved
0x1F
7:0
ID[3:0]
0x20
15:8
PEND
BUSY
FERR
SUSP
TCMPL
TERR
0x22
...
0x23
7:0
15:8
23:16
31:24
7:0
CHINTn[7:0]
CHINTn[11:8]
0x24
0x28
0x2C
0x30
0x34
0x38
INTSTATUS
BUSYCH
BUSYCHn[7:0]
15:8
23:16
31:24
7:0
BUSYCHn[11:8]
PENDCH7
ABUSY
PENDCH6
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH9
PENDCH0
PENDCH8
15:8
23:16
31:24
7:0
PENDCH11 PENDCH10
PENDCH
LVLEXx
BTCNT[7:0]
LVLEXx
ID[4:0]
LVLEXx
LVLEXx
15:8
23:16
31:24
7:0
ACTIVE
BTCNT[15:8]
BASEADDR[7:0]
BASEADDR[15:8]
BASEADDR[23:16]
BASEADDR[31:24]
WRBADDR[7:0]
15:8
23:16
31:24
7:0
BASEADDR
WRBADDR
15:8
23:16
31:24
WRBADDR[15:8]
WRBADDR[23:16]
WRBADDR[31:24]
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DMAC – Direct Memory Access Controller
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x3C
...
Reserved
CHID
0x3E
0x3F
7:0
7:0
ID[3:0]
0x40
0x41
...
CHCTRLA
ENABLE
SWRST
Reserved
0x43
7:0
LVL[1:0]
EVOE
EVIE
EVACT[2:0]
15:8
TRIGSRC[5:0]
0x44
CHCTRLB
Reserved
23:16
31:24
TRIGACT[1:0]
CMD[1:0]
0x48
...
0x4B
0x4C
0x4D
0x4E
0x4F
CHINTENCLR
CHINTENSET
CHINTFLAG
CHSTATUS
7:0
7:0
7:0
7:0
SUSP
SUSP
SUSP
FERR
TCMPL
TCMPL
TCMPL
BUSY
TERR
TERR
TERR
PEND
20.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 20.5.8 Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 290
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x00X0
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
12
11
LVLENx3
R/W
10
LVLENx2
R/W
9
LVLENx1
R/W
8
LVLENx0
R/W
Access
Reset
0
0
0
0
Bit
5
4
3
2
1
0
SWRST
R/W
0
CRCENABLE DMAENABLE
Access
Reset
R/W
0
R/W
0
Bits 8, 9, 10, 11 – LVLENxꢀPriority Level x Enable
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all
requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to the Arbitration section.
These bits are not enable-protected.
Value
Description
0
1
Transfer requests for Priority level x will not be handled.
Transfer requests for Priority level x will be handled.
Bit 2 – CRCENABLEꢀCRC Enable
Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS.
CRCBUSY). The bit is zero when the CRC is disabled.
Writing a '1' to this bit will enable the CRC calculation.
Value
Description
0
1
The CRC calculation is disabled.
The CRC calculation is enabled.
Bit 1 – DMAENABLEꢀDMA Enable
Setting this bit will enable the DMA module.
Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not
be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer
buffer will be empty once the ongoing burst transfer is completed.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are
'0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is
enabled, the Reset request will be ignored and the DMAC will return an access error.
Value
Description
0
1
There is no Reset operation ongoing.
A Reset operation is ongoing.
DS40001882G-page 291
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.2 CRC Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CRCCTRL
0x02
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
12
11
10
9
8
CRCSRC[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
5
4
3
2
1
0
CRCPOLY[1:0]
CRCBEATSIZE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:8 – CRCSRC[5:0]ꢀCRC Input Source
These bits select the input source for generating the CRC, as shown in the table below. The selected source is
locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot
be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY Status bit. CRC generation
complete is generated and signaled from the selected source when used with the DMA channel.
Value
0x00
0x01
0x02-0x1
F
Name
NOACT
IO
-
Description
No action
I/O interface
Reserved
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
CHN
CHN
CHN
CHN
CHN
CHN
CHN
CHN
CHN
CHN
CHN
CHN
DMA channel 0
DMA channel 1
DMA channel 2
DMA channel 3
DMA channel 4
DMA channel 5
DMA channel 6
DMA channel 7
DMA channel 8
DMA channel 9
DMA channel 10
DMA channel 11
Bits 3:2 – CRCPOLY[1:0]ꢀCRC Polynomial Type
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as
shown in the table below.
Value
0x0
0x1
Name
CRC16
CRC32
Description
CRC-16 (CRC-CCITT)
CRC32 (IEEE 802.3)
Reserved
0x2-0x3
Bits 1:0 – CRCBEATSIZE[1:0]ꢀCRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface.
Value
0x0
0x1
0x2
0x3
Name
BYTE
HWORD
WORD
Description
8-bit bus transfer
16-bit bus transfer
32-bit bus transfer
Reserved
DS40001882G-page 292
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.3 CRC Data Input
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CRCDATAIN
0x04
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
CRCDATAIN[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
CRCDATAIN[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
CRCDATAIN[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
CRCDATAIN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CRCDATAIN[31:0]ꢀCRC Data Input
These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1)
clock cycles after the CRCDATAIN register is written.
DS40001882G-page 293
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.4 CRC Checksum
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CRCCHKSUM
0x08
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero
by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write
this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.)
and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set
(i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content.
Bit
31
30
29
28
27
26
25
24
CRCCHKSUM[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
CRCCHKSUM[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
CRCCHKSUM[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
CRCCHKSUM[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CRCCHKSUM[31:0]ꢀCRC Checksum
These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled.
DS40001882G-page 294
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.5 CRC Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CRCSTATUS
0x0C
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CRCBUSY
R/W
CRCZERO
Access
Reset
R
0
0
Bit 1 – CRCZEROꢀCRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum
should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little
endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read
out different versions of the checksum.
Bit 0 – CRCBUSYꢀCRC Module Busy
This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is
set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled.
This register bit cannot be cleared by the application when the CRC is used with a DMA channel.
This bit is set when a source configuration is selected and as long as the source is using the CRC module.
DS40001882G-page 295
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.6 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x0D
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀDebug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The DMAC is halted when the CPU is halted by an external debugger.
1
The DMAC continues normal operation when the CPU is halted by an external debugger.
DS40001882G-page 296
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.7 Quality of Service Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
QOSCTRL
0x0E
0x15
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DQOS[1:0]
FQOS[1:0]
WRBQOS[1:0]
Access
Reset
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
Bits 5:4 – DQOS[1:0]ꢀData Transfer Quality of Service
These bits define the memory priority access during the data transfer operation.
DQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
Bits 3:2 – FQOS[1:0]ꢀFetch Quality of Service
These bits define the memory priority access during the fetch operation.
FQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
Bits 1:0 – WRBQOS[1:0]ꢀWrite-Back Quality of Service
These bits define the memory priority access during the write-back operation.
WRBQOS[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
LOW
MEDIUM
HIGH
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
Related Links
11.4.3 SRAM Quality of Service
DS40001882G-page 297
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.8 Software Trigger Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SWTRIGCTRL
0x10
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
SWTRIGn[11:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
3
2
1
0
SWTRIGn[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – SWTRIGn[11:0]ꢀChannel n Software Trigger [n = 11..0]
This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the
corresponding channel is either set, or by writing a '1' to it.
This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit.
Writing a '0' to this bit will clear the bit.
Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x.
CHSTATUS.PEND will be set and SWTRIGn will remain cleared.
DS40001882G-page 298
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.9 Priority Control 0
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PRICTRL0
0x14
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
RRLVLEN3
R/W
30
22
14
6
29
21
13
5
28
20
12
4
27
26
25
24
LVLPRI3[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
23
RRLVLEN2
R/W
19
18
17
16
LVLPRI2[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
15
RRLVLEN1
R/W
11
10
9
8
LVLPRI1[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
RRLVLEN0
R/W
3
2
1
0
LVLPRI0[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 31 – RRLVLEN3ꢀLevel 3 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration
schemes, refer to 20.6.2.4 Arbitration.
Value
Description
0
1
Static arbitration scheme for channels with level 3 priority.
Round-robin arbitration scheme for channels with level 3 priority.
Bits 27:24 – LVLPRI3[3:0]ꢀLevel 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0').
Bit 23 – RRLVLEN2ꢀLevel 2 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration
schemes, refer to 20.6.2.4 Arbitration.
Value
Description
0
1
Static arbitration scheme for channels with level 2 priority.
Round-robin arbitration scheme for channels with level 2 priority.
Bits 19:16 – LVLPRI2[3:0]ꢀLevel 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0').
DS40001882G-page 299
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
Bit 15 – RRLVLEN1ꢀLevel 1 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to 20.6.2.4 Arbitration.
Value
Description
0
1
Static arbitration scheme for channels with level 1 priority.
Round-robin arbitration scheme for channels with level 1 priority.
Bits 11:8 – LVLPRI1[3:0]ꢀLevel 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0').
Bit 7 – RRLVLEN0ꢀLevel 0 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to 20.6.2.4 Arbitration.
Value
Description
0
1
Static arbitration scheme for channels with level 0 priority.
Round-robin arbitration scheme for channels with level 0 priority.
Bits 3:0 – LVLPRI0[3:0]ꢀLevel 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel
number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is
non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0').
DS40001882G-page 300
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.10 Interrupt Pending
Name:ꢀ
INTPEND
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x20
0x0000
-
This register allows the user to identify the lowest DMA channel with pending interrupt.
Bit
15
PEND
R
14
BUSY
R
13
FERR
R
12
11
10
SUSP
R/W
0
9
TCMPL
R/W
0
8
TERR
R/W
0
Access
Reset
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 15 – PENDꢀPending
This bit will read '1' when the channel selected by Channel ID field (ID) is pending.
Bit 14 – BUSYꢀBusy
This bit will read '1' when the channel selected by Channel ID field (ID) is busy.
Bit 13 – FERRꢀFetch Error
This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
Bit 10 – SUSPꢀChannel Suspend
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag.
Bit 9 – TCMPLꢀTransfer Complete
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
Bit 8 – TERRꢀTransfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
Bits 3:0 – ID[3:0]ꢀChannel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer
Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel
(with channel number less than the current one) with pending interrupts is detected, or when the application clears
the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will
always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
DS40001882G-page 301
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.11 Interrupt Status
Name:ꢀ
INTSTATUS
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x24
0x00000000
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
CHINTn[11:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
3
2
1
0
CHINTn[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 11:0 – CHINTn[11:0]ꢀChannel n Pending Interrupt [n=11..0]
This bit is set when Channel n has a pending interrupt/the interrupt request is received.
This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are cleared.
DS40001882G-page 302
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.12 Busy Channels
Name:ꢀ
BUSYCH
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x28
0x00000000
-
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
BUSYCHn[11:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
3
2
1
0
BUSYCHn[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 11:0 – BUSYCHn[11:0]ꢀBusy Channel n [x=11..0]
This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for DMA channel
n is detected, or when DMA channel n is disabled.
This bit is set when DMA channel n starts a DMA transfer.
DS40001882G-page 303
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.13 Pending Channels
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PENDCH
0x2C
0x00000000
-
Property:ꢀ
Bit
31
23
15
30
22
14
29
21
13
28
20
12
27
19
26
18
25
17
24
16
Access
Reset
Bit
Access
Reset
Bit
11
10
9
8
PENDCH11
PENDCH10
PENDCH9
PENDCH8
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
PENDCH7
PENDCH6
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – PENDCHꢀPending Channel n [n=11..0]
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started,
when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action
settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel n.
Related Links
20.8.19 CHCTRLB
DS40001882G-page 304
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.14 Active Channel and Levels
Name:ꢀ
ACTIVE
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x30
0x00000000
-
Bit
31
30
29
28
27
26
25
24
BTCNT[15:8]
BTCNT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
ID[4:0]
R
9
8
ABUSY
Access
Reset
R
0
R
0
R
0
R
0
R
0
0
Bit
7
6
5
4
3
2
1
0
LVLEXx
LVLEXx
LVLEXx
LVLEXx
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:16 – BTCNT[15:0]ꢀActive Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
Bit 15 – ABUSYꢀActive Channel Busy
This bit is cleared when the active transfer count is written back in the write-back memory section.
This bit is set when the next descriptor transfer count is read from the write-back memory section.
Bits 12:8 – ID[4:0]ꢀActive Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated each time the
arbiter grants a new channel transfer access request.
Bits 3,2,1,0 – LVLEXxꢀLevel x Channel Trigger Request Executing [x=3..0]
This bit is set when a level-x channel trigger request is executing or pending.
This bit is cleared when no request is pending or being executed.
DS40001882G-page 305
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.15 Descriptor Memory Section Base Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BASEADDR
0x34
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
BASEADDR[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
BASEADDR[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
BASEADDR[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
BASEADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – BASEADDR[31:0]ꢀDescriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 64-bit aligned.
DS40001882G-page 306
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.16 Write-Back Memory Section Base Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WRBADDR
0x38
0x00000000
Property:ꢀ PAC Write Protection, Enable-Protected
Bit
31
30
29
28
WRBADDR[31:24]
R/W R/W
27
26
25
24
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
23
22
21
20
WRBADDR[23:16]
R/W R/W
19
18
17
16
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
15
14
13
12
11
10
9
8
WRBADDR[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
WRBADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – WRBADDR[31:0]ꢀWrite-Back Memory Base Address
These bits store the Write-Back memory base address. The value must be 64-bit aligned.
DS40001882G-page 307
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.17 Channel ID
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHID
0x3F
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 3:0 – ID[3:0]ꢀChannel ID
These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a
channel register, the channel ID bit group must be written first.
DS40001882G-page 308
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.18 Channel Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHCTRLA
0x40
0x00
Property:ꢀ PAC Write-Protection, Enable-Protected
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
0
Bit 1 – ENABLEꢀChannel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is
empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer
is completed.
Writing a '1' to this bit will enable the DMA channel.
This bit is not enable-protected.
Value
Description
0
1
DMA channel is disabled.
DMA channel is enabled.
Bit 0 – SWRSTꢀChannel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the channel is
disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared
when the reset is completed.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 309
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.19 Channel Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHCTRLB
0x44
0x00000000
Property:ꢀ PAC Write Protection, Enable-Protected
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
31
30
29
21
13
28
20
12
27
19
11
26
18
10
25
24
CMD[1:0]
Access
Reset
R/W
0
R/W
0
Bit
23
22
17
16
TRIGACT[1:0]
Access
Reset
R/W
0
R/W
0
Bit
15
7
14
6
9
8
TRIGSRC[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
5
4
EVOE
R/W
0
3
EVIE
R/W
0
2
1
0
LVL[1:0]
EVACT[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 25:24 – CMD[1:0]ꢀSoftware Command
These bits define the software commands. Refer to 20.6.3.2 Channel Suspend and 20.6.3.3 Channel Resume and
Next Suspend Skip.
These bits are not enable-protected.
CMD[1:0]
Name
Description
0x0
0x1
0x2
0x3
NOACT
SUSPEND
RESUME
-
No action
Channel suspend operation
Channel resume operation
Reserved
Bits 23:22 – TRIGACT[1:0]ꢀTrigger Action
These bits define the trigger action used for a transfer.
TRIGACT[1:0]
Name
Description
0x0
0x1
0x2
0x3
BLOCK
-
BEAT
TRANSACTION
One trigger required for each block transfer
Reserved
One trigger required for each beat transfer
One trigger required for each transaction
Bits 13:8 – TRIGSRC[5:0]ꢀTrigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger
modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
Value
0x00
0x01
0x02
0x03
Name
DISABLE
SERCOM0 RX
SERCOM0 TX
SERCOM1 RX
Description
Only software/event triggers
SERCOM0 RX Trigger
SERCOM0 TX Trigger
SERCOM1 RX Trigger
DS40001882G-page 310
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
Value
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Name
Description
SERCOM1 TX Trigger
SERCOM2 RX Trigger
SERCOM2 TX Trigger
SERCOM3 RX Trigger
SERCOM3 TX Trigger
SERCOM4 RX Trigger
SERCOM4 TX Trigger
SERCOM1 TX
SERCOM2 RX
SERCOM2 TX
SERCOM3 RX
SERCOM3 TX
SERCOM4 RX
SERCOM4 TX
SERCOM5 RX
SERCOM5 TX
TCC0 OVF
TCC0 MC0
TCC0 MC1
TCC0 MC2
TCC0 MC3
TCC1 OVF
TCC1 MC0
TCC1 MC1
TCC2 OVF
TCC2 MC0
TCC2 MC1
TC3 OVF
TC3 MC0
TC3 MC1
TC4 OVF
TC4 MC0
TC4 MC1
TC5 OVF
TC5 MC0
TC5 MC1
TC6 OVF
TC6 MC0
TC6 MC1
TC7 OVF
TC7 MC0
TC7 MC1
ADC RESRDY
DAC EMPTY
I2S RX 0
SERCOM5 RX Trigger
SERCOM5 TX Trigger
TCC0 Overflow Trigger
TCC0 Match/Compare 0 Trigger
TCC0 Match/Compare 1 Trigger
TCC0 Match/Compare 2 Trigger
TCC0 Match/Compare 3 Trigger
TCC1 Overflow Trigger
TCC1 Match/Compare 0 Trigger
TCC1 Match/Compare 1 Trigger
TCC2 Overflow Trigger
TCC2 Match/Compare 0 Trigger
TCC2 Match/Compare 1 Trigger
TC3 Overflow Trigger
TC3 Match/Compare 0 Trigger
TC3 Match/Compare 1 Trigger
TC4 Overflow Trigger
TC4 Match/Compare 0 Trigger
TC4 Match/Compare 1 Trigger
TC5 Overflow Trigger
TC5 Match/Compare 0 Trigger
TC5 Match/Compare 1 Trigger
TC6 Overflow Trigger
TC6 Match/Compare 0 Trigger
TC6 Match/Compare 1 Trigger
TC7 Overflow Trigger
TC7 Match/Compare 0 Trigger
TC7 Match/Compare 1 Trigger
ADC Result Ready Trigger
DAC Empty Trigger
I2S RX 0 Trigger
I2S RX 1 Trigger
I2S TX 0 Trigger
I2S TX 1 Trigger
I2S RX 1
I2S TX 0
I2S TX 0
OVF
TCC3 MC0
TCC3 MC1
TCC3 MC2
TCC3 MC3
TCC3 Overflow Trigger
TCC3 Match/Compare 0 Trigger
TCC3 Match/Compare 1 Trigger
Match/Compare 2 Trigger
Match/Compare 3 Trigger
Bits 6:5 – LVL[1:0]ꢀChannel Arbitration Level
These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For
further details on arbitration schemes, refer to 20.6.2.4 Arbitration.
These bits are not enable-protected.
TRIGACT[1:0]
Name
Description
0x0
0x1
LVL0
LVL1
Channel Priority Level 0
Channel Priority Level 1
DS40001882G-page 311
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
...........continued
TRIGACT[1:0]
Name
Description
0x2
0x3
LVL2
LVL3
Channel Priority Level 2
Channel Priority Level 3
Bit 4 – EVOEꢀChannel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined
in the descriptor Event Output Selection (BTCTRL.EVOSEL).
This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event
Generator Selection of the Event System for details.
Value
Description
0
1
Channel event generation is disabled
Channel event generation is enabled
Bit 3 – EVIEꢀChannel Event Input Enable
This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event
Generator Selection of the Event System for details.
Value
Description
0
1
Channel event action will not be executed on any incoming event
Channel event action will be executed on any incoming event
Bits 2:0 – EVACT[2:0]ꢀEvent Input Action
These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in
CHCTRLB register of the channel is set.
These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and
Event Generator Selection of the Event System for details.
EVACT[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
NOACT
TRIG
No action
Normal Transfer and Conditional Transfer on Strobe trigger
Conditional transfer trigger
Conditional block transfer
Channel suspend operation
Channel resume operation
Skip next block suspend action
Reserved
CTRIG
CBLOCK
SUSPEND
RESUME
SSKIP
-
Related Links
24.8.3 USER
24.8.2 CHANNEL
DS40001882G-page 312
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.20 Channel Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHINTENCLR
0x4C
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Access
Reset
Bit 2 – SUSPꢀChannel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
Value
Description
0
1
The Channel Suspend interrupt is disabled.
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPLꢀChannel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
Value
Description
0
The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag
will not be set when a block transfer is completed.
The Channel Transfer Complete interrupt is enabled.
1
Bit 0 – TERRꢀChannel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer
Error interrupt.
Value
Description
0
1
The Channel Transfer Error interrupt is disabled.
The Channel Transfer Error interrupt is enabled.
DS40001882G-page 313
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.21 Channel Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHINTENSET
0x4D
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Access
Reset
Bit 2 – SUSPꢀChannel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend
interrupt.
Value
Description
0
1
The Channel Suspend interrupt is disabled.
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPLꢀChannel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel
Transfer Complete interrupt.
Value
Description
0
1
The Channel Transfer Complete interrupt is disabled.
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERRꢀChannel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer
Error interrupt.
Value
Description
0
1
The Channel Transfer Error interrupt is disabled.
The Channel Transfer Error interrupt is enabled.
DS40001882G-page 314
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.22 Channel Interrupt Flag Status and Clear
Name:ꢀ
CHINTFLAG
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x4E
0x00
-
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
2
SUSP
R/W
0
1
TCMPL
R/W
0
0
TERR
R/W
0
Access
Reset
Bit 2 – SUSPꢀChannel Suspend
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer with suspend block action is completed, when a software suspend command is
executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to CHCTRLB.CMD.
For details on available event input actions, refer to CHCTRLB.EVACT.
For details on available block actions, refer to BTCTRL.BLOCKACT.
Bit 1 – TCMPLꢀChannel Transfer Complete
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
Bit 0 – TERRꢀChannel Transfer Error
This flag is cleared by writing a '1' to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
DS40001882G-page 315
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.8.23 Channel Status
Name:ꢀ
CHSTATUS
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x4F
0x00
-
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit
7
6
5
4
3
2
FERR
R
1
BUSY
R
0
PEND
R
Access
Reset
0
0
0
Bit 2 – FERRꢀChannel Fetch Error
This bit is cleared when a software resume command is executed.
This bit is set when an invalid descriptor is fetched.
Bit 1 – BUSYꢀChannel Busy
This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
Bit 0 – PENDꢀChannel Pending
This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is
disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received.
DS40001882G-page 316
Complete Datasheet
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SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.9
Register Summary - SRAM
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
7:0
BLOCKACT[1:0]
STEPSEL DSTINC
EVOSEL[1:0]
SRCINC
VALID
0x00
0x02
BTCTRL
STEPSIZE[2:0]
BEATSIZE[1:0]
BTCNT[7:0]
BTCNT[15:8]
BTCNT
15:8
7:0
SRCADDR[7:0]
SRCADDR[15:8]
SRCADDR[23:16]
SRCADDR[31:24]
DSTADDR[7:0]
15:8
23:16
31:24
7:0
0x04
0x08
0x0C
SRCADDR
15:8
23:16
31:24
7:0
DSTADDR[15:8]
DSTADDR[23:16]
DSTADDR[31:24]
DESCADDR[7:0]
DESCADDR[15:8]
DESCADDR[23:16]
DESCADDR[31:24]
DSTADDR
15:8
23:16
31:24
DESCADDR
20.10 Register Description - SRAM
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 20.5.8 Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 317
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.10.1 Block Transfer Control
Name:ꢀ
BTCTRL
Offset:ꢀ
Property:ꢀ
0x00
-
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
15
14
13
12
11
10
9
8
0
STEPSIZE[2:0]
STEPSEL
DSTINC
SRCINC
BEATSIZE[1:0]
Access
Reset
Bit
7
6
5
4
3
2
1
BLOCKACT[1:0]
EVOSEL[1:0]
VALID
Access
Reset
Bits 15:13 – STEPSIZE[2:0]ꢀAddress Increment Step Size
These bits select the address increment step size. The setting apply to source or destination address, depending on
STEPSEL setting.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
X1
X2
X4
X8
X16
X32
X64
X128
Description
Next ADDR = ADDR + (Beat size in byte) * 1
Next ADDR = ADDR + (Beat size in byte) * 2
Next ADDR = ADDR + (Beat size in byte) * 4
Next ADDR = ADDR + (Beat size in byte) * 8
Next ADDR = ADDR + (Beat size in byte) * 16
Next ADDR = ADDR + (Beat size in byte) * 32
Next ADDR = ADDR + (Beat size in byte) * 64
Next ADDR = ADDR + (Beat size in byte) * 128
Bit 12 – STEPSELꢀStep Selection
This bit selects if source or destination addresses are using the step size settings.
Value
0x0
0x1
Name
DST
SRC
Description
Step size settings apply to the destination address
Step size settings apply to the source address
Bit 11 – DSTINCꢀDestination Address Increment Enable
Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the
data transfer.
Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is
incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register.
Value
Description
0
1
The Destination Address Increment is disabled.
The Destination Address Increment is enabled.
Bit 10 – SRCINCꢀSource Address Increment Enable
Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data
transfer.
Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented
by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.
Value
Description
0
1
The Source Address Increment is disabled.
The Source Address Increment is enabled.
DS40001882G-page 318
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
Bits 9:8 – BEATSIZE[1:0]ꢀBeat Size
These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to
both read and write accesses.
Value
0x0
0x1
0x2
other
Name
BYTE
HWORD
WORD
Description
8-bit bus transfer
16-bit bus transfer
32-bit bus transfer
Reserved
Bits 4:3 – BLOCKACT[1:0]ꢀBlock Action
These bits define what actions the DMAC should take after a block transfer has completed.
BLOCKACT[1:0] Name
Description
0x0
0x1
NOACT
INT
Channel will be disabled if it is the last block transfer in the transaction
Channel will be disabled if it is the last block transfer in the transaction and block
interrupt
0x2
0x3
SUSPEND Channel suspend operation is completed
BOTH Both channel suspend operation and block interrupt
Bits 2:1 – EVOSEL[1:0]ꢀEvent Output Selection
These bits define the event output selection.
EVOSEL[1:0]
Name
Description
0x0
0x1
0x2
0x3
DISABLE
BLOCK
Event generation disabled
Event strobe when block transfer complete
Reserved
BEAT
Event strobe when beat transfer complete
Bit 0 – VALIDꢀDescriptor Valid
Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching
the corresponding descriptor.
The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected
during the block transfer, or when the block transfer is completed.
Value
Description
0
1
The descriptor is not valid.
The descriptor is valid.
DS40001882G-page 319
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.10.2 Block Transfer Count
Name:ꢀ
Offset:ꢀ
Property:ꢀ
BTCNT
0x02
-
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
15
14
13
12
11
10
9
8
0
BTCNT[15:8]
Access
Reset
Bit
7
6
5
4
3
2
1
BTCNT[7:0]
Access
Reset
Bits 15:0 – BTCNT[15:0]ꢀBlock Transfer Count
This bit group holds the 16-bit block transfer count.
During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is
written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority,
is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by
software.
DS40001882G-page 320
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.10.3 Block Transfer Source Address
Name:ꢀ
SRCADDR
Offset:ꢀ
Property:ꢀ
0x04
-
The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
30
29
28
27
26
25
24
SRCADDR[31:24]
Access
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SRCADDR[23:16]
Access
Reset
0
0
0
0
0
0
0
9
0
8
Bit
15
14
13
12
11
10
SRCADDR[15:8]
Access
Reset
0
7
0
6
0
5
0
0
0
2
0
1
0
0
Bit
4
3
SRCADDR[7:0]
Access
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – SRCADDR[31:0]ꢀTransfer Source Address
This bit field holds the block transfer source address.
When source address incrementation is disabled (BTCTRL.SRCINC=0), SRCADDR corresponds to the last beat
transfer address in the block transfer.
When source address incrementation is enabled (BTCTRL.SRCINC=1), SRCADDR is calculated as follows:
If BTCTRL.STEPSEL = 1:
STEPSIZE
SRCADDR = SRCADDR
+ BTCNT ⋅ BEATSIZE + 1 ⋅ 2
START
If BTCTRL.STEPSEL= 0:
SRCADDR = SRCADDR
+ BTCNT ⋅ BEATSIZE + 1
START
•
•
•
•
SRCADDRSTART is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
DS40001882G-page 321
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.10.4 Block Transfer Destination Address
Name:ꢀ
DSTADDR
Offset:ꢀ
Property:ꢀ
0x08
-
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
30
29
28
27
26
25
24
DSTADDR[31:24]
Access
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DSTADDR[23:16]
Access
Reset
0
0
0
0
0
0
0
9
0
8
Bit
15
14
13
12
11
10
DSTADDR[15:8]
Access
Reset
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Bit
DSTADDR[7:0]
Access
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – DSTADDR[31:0]ꢀTransfer Destination Address
This bit field holds the block transfer destination address.
When destination address incrementation is disabled (BTCTRL.DSTINC = 0), DSTADDR corresponds to the last beat
transfer address in the block transfer.
When destination address incrementation is enabled (BTCTRL.DSTINC = 1), DSTADDR is calculated as follows:
If BTCTRL.STEPSEL = 1:
DSTADDR = DSTADDR
+ BTCNT • BEATSIZE + 1
START
If BTCTRL.STEPSEL = 0:
DSTADDR = DSTADDR
STEPSIZE
+ BTCNT • BEATSIZE + 1 • 2
START
•
•
•
•
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
DS40001882G-page 322
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DMAC – Direct Memory Access Controller
20.10.5 Next Descriptor Address
Name:ꢀ
DESCADDR
Offset:ꢀ
Property:ꢀ
0x0C
-
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
DESCADDR[31:24]
Access
Reset
Bit
20
19
DESCADDR[23:16]
Access
Reset
Bit
12
11
DESCADDR[15:8]
Access
Reset
Bit
4
3
1
0
DESCADDR[7:0]
Access
Reset
Bits 31:0 – DESCADDR[31:0]ꢀNext Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 64-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer
descriptor.
DS40001882G-page 323
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
21.
EIC – External Interrupt Controller
21.1
Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can
be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each
external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous
in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also
generate an event.
A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts,
but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.
21.2
Features
•
•
•
•
•
•
•
Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation from EXTINTx
21.3
Block Diagram
Figure 21-1.ꢀEIC Block Diagram
SENSEx[2:0]
FILTENx
intreq_extint
inwake_extint
evt_extint
Interrupt
Wake
EXTINTx
Edge/Level
Detection
Filter
Event
NMISENSE[2:0]
NMIFILTEN
Filter
intreq_nmi
Interrupt
Wake
NMI
Edge/Level
Detection
inwake_nmi
21.4
Signal Description
Signal Name
EXTINT[15..0]
NMI
Type
Description
External interrupt pin
Non-maskable interrupt pin
Digital Input
Digital Input
One signal may be available on several pins.
DS40001882G-page 324
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
Related Links
7. I/O Multiplexing and Considerations
21.5
Product Dependencies
In order to use this EIC, other parts of the system must be configured correctly, as described below.
21.5.1 I/O Lines
Using the EIC’s I/O lines requires the I/O pins to be configured.
Related Links
23. PORT - I/O Pin Controller
21.5.2 Power Management
All interrupts are available down to STANDBY sleep mode, but the EIC can be configured to automatically mask
some interrupts in order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other
operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
21.5.3 Clocks
The EIC bus clock (CLK_EIC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_EIC_APB can be found in the Peripheral Clock Masking section in PM – Power Manager.
A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and enabled in the
Generic Clock Controller before using the peripheral. Refer to GCLK – Generic Clock Controller.
This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to
certain registers will require synchronization between the clock domains. Refer to 21.6.9 Synchronization for further
details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
21.5.4 DMA
Not applicable.
21.5.5 Interrupts
There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for non-maskable
interrupt (NMI).
The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the
interrupt controller to be configured first.
The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be
configured.
Related Links
11.2 Nested Vector Interrupt Controller
21.5.6 Events
The events are connected to the Event System. Using the events requires the Event System to be configured first.
Related Links
24. EVSYS – Event System
DS40001882G-page 325
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
21.5.7 Debug Operation
When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may
result during debugging.
21.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
21.5.9 Analog Connections
Not applicable.
21.6
Functional Description
21.6.1 Principle of Operation
The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to the Event
System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by GCLK_EIC
21.6.2 Basic Operation
21.6.2.1 Initialization
The EIC must be initialized in the following order:
1. Enable CLK_EIC_APB
2. If edge detection or filtering is required, GCLK_EIC must be enabled
3. Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy)
4. Enable the EIC
To use NMI, GCLK_EIC must be enabled after EIC configuration (NMICTRL).
21.6.2.2 Enabling, Disabling and Resetting
The EIC is enabled by writing a '1' the Enable bit in the Control register (CTRL.ENABLE). The EIC is disabled by
writing CTRL.ENABLE to '0'.
The EIC is reset by setting the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EIC will
be reset to their initial state, and the EIC will be disabled.
Refer to the CTRL register description for details.
21.6.3 External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or
level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the
Config n register (CONFIGn.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag
Status and Clear register (INTFLAG) is set when the interrupt condition is met.
When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new
interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set
immediately if the EXTINTx pin still matches the interrupt condition.
DS40001882G-page 326
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC. Filtering is enabled if bit Filter
Enable x in the Configuration n register (CONFIGn.FILTENx) is written to '1'. The majority vote filter samples the
external pin three times with GCLK_EIC and outputs the value when two or more samples are equal.
Table 21-1.ꢀMajority Vote Filter
Samples [0, 1, 2]
[0,0,0]
Filter Output
0
0
0
1
0
1
1
1
[0,0,1]
[0,1,0]
[0,1,1]
[1,0,0]
[1,0,1]
[1,1,0]
[1,1,1]
When an external interrupt is configured for level detection, or if filtering is disabled, detection is made
asynchronously, and GCLK_EIC is not required.
If filtering or edge detection is enabled, the EIC automatically requests the GCLK_EIC to operate (GCLK_EIC must
be enabled in the GCLK module, see GCLK – Generic Clock Controller for details). If level detection is enabled,
GCLK_EIC is not required, but interrupt and events can still be generated.
When an external interrupt is configured for level detection and when filtering is disabled, detection is done
asynchronously. Asynchronuous detection does not require GCLK_EIC, but interrupt and events can still be
generated. If filtering or edge detection is enabled, the EIC automatically requests GCLK_EIC to operate. GCLK_EIC
must be enabled in the GCLK module.
Figure 21-2.ꢀInterrupt Detections
GCLK_EIC
CLK_EIC_APB
EXTINTx
intreq_extint[x]
(level detection / no filter)
No interrupt
No interrupt
intreq_extint[x]
(level detection / filter)
intreq_extint[x]
(edge detection / no filter)
intreq_extint[x]
(edge detection / filter)
clear INTFLAG.EXTINT[x]
The detection delay depends on the detection mode.
Table 21-2.ꢀInterrupt Latency
Detection mode
Level without filter
Level with filter
Edge without filter
Edge with filter
Latency (worst case)
Three CLK_EIC_APB periods
Four GCLK_EIC periods + Three CLK_EIC_APB periods
Four GCLK_EIC periods + Three CLK_EIC_APB periods
Six GCLK_EIC periods + Three CLK_EIC_APB periods
DS40001882G-page 327
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
Related Links
15. GCLK - Generic Clock Controller
21.6.4 Additional Features
21.6.4.1 Non-Maskable Interrupt (NMI)
The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with
the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in
the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a '1' to the NMI Filter Enable bit
(NMICTRL.NMIFILTEN).
If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K.
NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled.
When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request
when set.
21.6.5 DMA Operation
Not applicable.
21.6.6 Interrupts
The EIC has the following interrupt sources:
•
•
External interrupt pins (EXTINTx). See 21.6.2 Basic Operation.
Non-maskable interrupt pin (NMI). See 21.6.4 Additional Features.
Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be
individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled
by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the
INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt request line for each external
interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine
which interrupt condition is present.
Notes:ꢀ
1. Interrupts must be globally enabled for interrupt requests to be generated.
2. If an external interrupts (EXTINT) is common on two or more I/O pins, only one will be active (the first one
programmed).
Related Links
7.1 Multiplexed Signals
11. Processor And Architecture
21.6.7 Events
The EIC can generate the following output events:
External event from pin (EXTINTx).
•
Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this
bit disables the corresponding output event. Refer to Event System for details on configuring the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the corresponding event is
generated, if enabled.
Related Links
24. EVSYS – Event System
DS40001882G-page 328
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
21.6.8 Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration
in CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from
pin EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin
EXTINTx.
Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended.
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration
in CONFIGn register, and the corresponding bit in the Interrupt Enable Set register (INTENSET) is written to '1'.
WAKEUP.WAKEUPEN[x]=1 can enable the wake-up from pin EXTINTx.
Figure 21-3.ꢀWake-Up Operation Example (High-Level Detection, No Filter, WAKEUPEN[x]=1)
CLK_EIC_APB
EXTINTx
intwake_extint[x]
intreq_extint[x]
wake from sleep mode
clear INTFLAG.EXTINT[x]
21.6.9 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is
stalled.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control register (CTRL.SWRST)
Enable bit in the Control register (CTRL.ENABLE)
Related Links
14.3 Register Synchronization
DS40001882G-page 329
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EIC – External Interrupt Controller
21.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
CTRL
7:0
7:0
ENABLE
SWRST
STATUS
NMICTRL
NMIFLAG
SYNCBUSY
7:0
NMIFILTEN
NMISENSE[2:0]
7:0
NMI
7:0
EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8
15:8
23:16
31:24
7:0
0x04
0x08
0x0C
0x10
EVCTRL
INTENCLR
INTENSET
INTFLAG
EXTINT7
EXTINT6
EXTINT5
EXTINT4
EXTINT3
EXTINT2
EXTINT1
EXTINT9
EXTINT0
EXTINT8
15:8
23:16
31:24
7:0
EXTINT15
EXTINT14
EXTINT13
EXTINT12
EXTINT11
EXTINT10
EXTINT7
EXTINT6
EXTINT5
EXTINT4
EXTINT3
EXTINT2
EXTINT1
EXTINT9
EXTINT0
EXTINT8
15:8
23:16
31:24
7:0
EXTINT15
EXTINT14
EXTINT13
EXTINT12
EXTINT11
EXTINT10
EXTINT7
EXTINT6
EXTINT5
EXTINT4
EXTINT3
EXTINT2
EXTINT1
EXTINT9
EXTINT0
EXTINT8
15:8
23:16
31:24
7:0
EXTINT15
EXTINT14
EXTINT13
EXTINT12
EXTINT11
EXTINT10
WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0
WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1 WAKEUPEN1
WAKEUPEN9 WAKEUPEN8
15:8
5
4
3
2
1
0
0x14
WAKEUP
23:16
31:24
7:0
FILTEN1
FILTEN3
FILTEN5
FILTEN7
FILTEN1
FILTEN3
FILTEN5
FILTEN7
SENSE1[2:0]
SENSE3[2:0]
SENSE5[2:0]
SENSE7[2:0]
SENSE1[2:0]
SENSE3[2:0]
SENSE5[2:0]
SENSE7[2:0]
FILTEN0
FILTEN2
FILTEN4
FILTEN6
FILTEN0
FILTEN2
FILTEN4
FILTEN6
SENSE0[2:0]
SENSE2[2:0]
SENSE4[2:0]
SENSE6[2:0]
SENSE0[2:0]
SENSE2[2:0]
SENSE4[2:0]
SENSE6[2:0]
15:8
0x18
0x1C
CONFIG0
CONFIG1
23:16
31:24
7:0
15:8
23:16
31:24
21.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
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EIC – External Interrupt Controller
21.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
Access
Reset
0
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
Value
Description
0
1
The EIC is disabled.
The EIC is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write operation
will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
Description
0
1
There is no ongoing reset operation.
The reset operation is ongoing.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.2 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x01
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.3 Non-Maskable Interrupt Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
NMICTRL
0x02
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
NMIFILTEN
R/W
2
1
0
NMISENSE[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit 3 – NMIFILTENꢀNon-Maskable Interrupt Filter Enable
Value
Description
0
1
NMI filter is disabled.
NMI filter is enabled.
Bits 2:0 – NMISENSE[2:0]ꢀNon-Maskable Interrupt Sense
These bits define on which edge or level the NMI triggers.
NMISENSE[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6-0x7
NONE
RISE
FALL
BOTH
HIGH
LOW
No detection
Rising-edge detection
Falling-edge detection
Both-edges detection
High-level detection
Low-level detection
Reserved
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.4 Non-Maskable Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
NMIFLAG
0x03
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
NMI
R/W
0
Access
Reset
Bit 0 – NMIꢀNon-Maskable Interrupt
This flag is cleared by writing a one to it.
This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the non-maskable interrupt flag.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.5 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x04
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
15
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
Access
Reset
Bit
Access
Reset
Bit
8
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9
EXTINTEO8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
EXTINTEO7
EXTINTEO6
EXTINTEO5
EXTINTEO4
EXTINTEO3
EXTINTEO2
EXTINTEO1
EXTINTEO0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEOx ꢀExternal Interrupt x Event Output Enable
[x=15..0]
These bits indicate whether the event associated with the EXTINTx pin is enabled or not to generated for every
detection.
Value
Description
0
1
Event from pin EXTINTx is disabled.
Event from pin EXTINTx is enabled.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.6 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x08
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
30
22
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
Access
Reset
Bit
15
EXTINT15
R/W
14
EXTINT14
R/W
13
EXTINT13
R/W
12
EXTINT12
R/W
11
EXTINT11
R/W
10
EXTINT10
R/W
9
EXTINT9
R/W
8
EXTINT8
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit
7
EXTINT7
R/W
6
EXTINT6
R/W
5
EXTINT5
R/W
4
EXTINT4
R/W
3
EXTINT3
R/W
2
EXTINT2
R/W
1
EXTINT1
R/W
0
EXTINT0
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx ꢀExternal Interrupt x Enable [x=15..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the External Interrupt x Enable bit, which disables the external interrupt.
Value
Description
0
1
The external interrupt x is disabled.
The external interrupt x is enabled.
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EIC – External Interrupt Controller
21.8.7 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x0C
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
30
22
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
Access
Reset
Bit
15
EXTINT15
R/W
14
EXTINT14
R/W
13
EXTINT13
R/W
12
EXTINT12
R/W
11
EXTINT11
R/W
10
EXTINT10
R/W
9
EXTINT9
R/W
8
EXTINT8
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit
7
EXTINT7
R/W
6
EXTINT6
R/W
5
EXTINT5
R/W
4
EXTINT4
R/W
3
EXTINT3
R/W
2
EXTINT2
R/W
1
EXTINT1
R/W
0
EXTINT0
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx ꢀExternal Interrupt x Enable [x=15..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the External Interrupt x Enable bit, which enables the external interrupt.
Value
Description
0
1
The external interrupt x is disabled.
The external interrupt x is enabled.
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EIC – External Interrupt Controller
21.8.8 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x10
0x00000000
-
Property:ꢀ
Bit
31
23
30
22
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
Access
Reset
Bit
15
EXTINT15
R/W
14
EXTINT14
R/W
13
EXTINT13
R/W
12
EXTINT12
R/W
11
EXTINT11
R/W
10
EXTINT10
R/W
9
EXTINT9
R/W
8
EXTINT8
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit
7
EXTINT7
R/W
6
EXTINT6
R/W
5
EXTINT5
R/W
4
EXTINT4
R/W
3
EXTINT3
R/W
2
EXTINT2
R/W
1
EXTINT1
R/W
0
EXTINT0
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx ꢀExternal Interrupt x [x=15..0]
This flag is cleared by writing a one to it.
This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt
request if INTENCLR/SET.EXTINT[x] is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the External Interrupt x flag.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.9 Wake-Up Enable
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WAKEUP
0x14
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
15
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10 WAKEUPEN9 WAKEUPEN8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – WAKEUPENx ꢀExternal Interrupt x Wake-up Enable [x=15..0]
This bit enables or disables wake-up from Sleep modes when the EXTINTx pin matches the external interrupt sense
configuration.
Value
Description
0
1
Wake-up from the EXTINTx pin is disabled.
Wake-up from the EXTINTx pin is enabled.
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SAM D21/DA1 Family
EIC – External Interrupt Controller
21.8.10 Configuration n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CONFIGn
0x18 + n*0x04 [n=0..1]
0x00000000
Property:ꢀ Write-Protected
Bit
31
FILTEN7
RW
30
29
28
27
FILTEN6
RW
26
25
24
SENSE7[2:0]
SENSE6[2:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
0
Bit
23
FILTEN5
RW
22
21
20
19
FILTEN4
RW
18
17
16
SENSE5[2:0]
SENSE4[2:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
0
Bit
15
FILTEN3
RW
14
13
12
11
FILTEN2
RW
10
9
8
SENSE3[2:0]
SENSE2[2:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
0
Bit
7
FILTEN1
RW
6
5
4
3
FILTEN0
RW
2
1
0
SENSE1[2:0]
SENSE0[2:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
0
0
Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENxꢀFilter x Enable [x=7..0]
0:
1:
Filter is disabled for EXTINT[n*8+x] input.
Filter is enabled for EXTINT[n*8+x] input.
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSExꢀInput Sense x Configuration [x=7..0]
SENSEx[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6-0x7
NONE
RISE
FALL
BOTH
HIGH
LOW
No detection
Rising-edge detection
Falling-edge detection
Both-edges detection
High-level detection
Low-level detection
Reserved
Notes:ꢀ
1. FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG0 register belong to External
Interrupt 7 to 0.
2. FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG1 register belong to External
Interrupt 15 to 8.
DS40001882G-page 340
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SAM D21/DA1 Family
Nonvolatile Memory Controller (NVMCTRL)
22.
Nonvolatile Memory Controller (NVMCTRL)
22.1
Overview
Non-volatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with
power off. It embeds a main array and a separate smaller Read While Write EEPROM Emulation array (RWWEE
Emulation) that can be programmed while reading the main array (RWWEE stands for Read (the main array) while
Write (the EEPROM Emulation)). The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for
system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB
interface is used for commands and configuration.
22.2
Features
•
•
•
•
•
•
•
•
•
•
•
32-bit AHB interface for reads and writes
Read-While-Write DATA Flash
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states for read optimization
16 regions can be individually protected or unprotected
Additional protection for bootloader
Supports device protection through a security bit
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache
Note:ꢀ A register with property "Enable-Protected" may contain bits that are not enable-protected.
22.3
Block Diagram
Figure 22-1.ꢀBlock Diagram
NVMCTRL
AHB
NVM Block
Cache
main array
NVM Interface
APB
Command and
Control
RWWEE array
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SAM D21/DA1 Family
Nonvolatile Memory Controller (NVMCTRL)
22.4
22.5
Signal Description
Not applicable.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described in the following
sections.
22.5.1 Power Management
The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The
NVMCTRL interrupts can be used to wake up the device from sleep modes.
The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This
is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the 22.8.2 CTRLB. SLEEPPRM
register description for more details. The NVM block goes into low-power mode automatically when the device enters
STANDBY mode regardless of SLEEPPRM. The NVM Page Buffer is lost when the NVM goes into low power mode
therefore a write command must be issued prior entering the NVM low power mode. NVMCTRL SLEEPPRM can be
disabled to avoid such loss when the CPU goes into sleep except if the device goes into STANDBY mode for which
there is no way to retain the Page Buffer.
Related Links
16. PM – Power Manager
22.5.2 Clocks
Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB)
and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable
number of wait states can be used to optimize performance. When changing the AHB bus frequency, the user
must ensure that the NVM Controller is configured with the proper number of wait states. Refer to the Electrical
Characteristics for the exact number of wait states to be used for a particular frequency range.
Related Links
37. Electrical Characteristics at 85℃
22.5.3 Interrupts
The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt
requires the interrupt controller to be programmed first.
22.5.4 Debug Operation
When an external debugger forces the CPU into debug mode, the peripheral continues normal operation.
Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See
the section on the NVMCTRL 22.6.6 Security Bit for details.
22.5.5 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Related Links
11.6 Peripheral Access Controller (PAC)
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SAM D21/DA1 Family
Nonvolatile Memory Controller (NVMCTRL)
22.5.6 Analog Connections
Not applicable.
22.6
Functional Description
22.6.1 Principle of Operation
The NVM Controller is a client on the AHB and APB buses. It responds to commands, read requests and write
requests, based on user configuration.
22.6.1.1 Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM
Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any
need for user configuration.
22.6.2 Memory Organization
Refer to the Physical Memory Map for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row Organization
figure. The NVM has a row-erase granularity, while the write granularity is by page. In other words, a single row erase
will erase all four pages in the row, while four write operations are used to write the complete row.
Figure 22-2.ꢀNVM Row Organization
Row n
Page (n*4) + 3
Page (n*4) + 2
Page (n*4) + 1
Page (n*4) + 0
The NVM block contains a calibration and auxiliary space plus a dedicated RWWEE Emulation address space that
are memory mapped. Refer to the NVM Organization figure below for details.
The calibration and auxiliary space contains factory calibration and system configuration information. These spaces
can be read from the AHB bus in the same way as the main NVM main address space.
In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM Emulation
section can be allocated at the end of the NVM main address space.
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Nonvolatile Memory Controller (NVMCTRL)
Figure 22-3.ꢀNVM Memory Organization
Calibration and
Auxillary Space
NVM Base Address + 0x00800000
RWWEE
Address Space
NVM Base Address + 0x00400000
NVM Base Address + NVM Size
NVM Main
Address Space
NVM Base Address
The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT
fuses, and the upper rows can be allocated to EEPROM Emulation, as shown in the figure below.
The boot loader section is protected by the lock bit(s) corresponding to this address space and by the
BOOTPROT[2:0] fuse. The EEPROM Emulation rows can be written regardless of the region lock status.
The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated to the
EEPROM Emulation are given in EEPROM Size.
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SAM D21/DA1 Family
Nonvolatile Memory Controller (NVMCTRL)
Figure 22-4.ꢀEEPROM Emulation and Boot Loader Allocation
Related Links
10.2 Physical Memory Map
22.6.3 Region Lock Bits
The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash memory size,
and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the
region. After production, all regions will be unlocked.
Table 22-1.ꢀRegion Size
Memory Size [KB]
Region Size [KB]
256
128
64
16
8
4
32
2
To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these
commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be
written by software, or the automatically loaded value from a write operation can be used. The new setting will stay
in effect until the next Reset, or until the setting is changed again using the Lock and Unlock commands. The current
status of the lock can be determined by reading the LOCK register.
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Nonvolatile Memory Controller (NVMCTRL)
To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be
written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset.
Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical
Memory Map for calibration and auxiliary space address mapping.
Related Links
10.2 Physical Memory Map
22.6.4 Command and Data Interface
The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the
AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space or
the RWWEE address space directly, while other operations such as manual page writes and row erases must be
performed by issuing commands through the NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command
is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while
INTFLAG.READY is low will be ignored.
The CTRLB register must be used to control the power reduction mode, read wait states, and the write mode.
22.6.4.1 NVM Read
Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address
space or auxiliary address space directly. Read data is available after the configured number of read wait states
(CTRLB.RWS) set in the NVM Controller.
The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero
and one wait states are shown in the following figure.
Reading the NVM main address space while a programming or erase operation is ongoing on the NVM main array
results in an AHB bus stall until the end of the operation. Reading the NVM main array does not stall the bus when
the RWWEE array is being programmed or erased.
Figure 22-5.ꢀRead Wait State Examples
0 Wait States
AHB Command
Rd 0
Rd 1
Idle
AHB Client Ready
AHB Client Data
Data 1
Data 0
1 Wait States
Rd 0
Rd 1
Idle
AHB Command
AHB Client Ready
AHB Client Data
Data 0
Data 1
22.6.4.2 RWWEE Read
Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the RWWEE address
space directly.
Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is
twice as long in case of full-Word-size access.
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Nonvolatile Memory Controller (NVMCTRL)
It is not possible to read the RWWEE area while the NVM main array is being written or erased, whereas the
RWWEE area can be written or erased while the main array is being read.
The RWWEE address space is not cached, therefore it is recommended to limit access to this area for performance
and power consumption considerations.
22.6.4.3 NVM Write
The NVM Controller requires that an erase must be done before programming. The entire NVM main address space
and the RWWEE address space can be erased by a debugger Chip Erase command. Alternatively, rows can be
individually erased by the Erase Row command or the RWWEE Erase Row command to erase the NVM main
address space or the RWWEE address space, respectively.
After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or
erase sequences. Locking is performed on a per-region basis, and so, locking a region will lock all pages inside the
region.
Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The
page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits.
8-bit writes to the page buffer are not allowed and will cause a system exception.
Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block via the AHB
bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR
register. After the page buffer has been loaded with the required number of bytes, the page can be written to the
NVM main array or the RWWEE array by setting CTRLA.CMD to 'Write Page' or 'RWWEE Write Page', respectively,
and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has
been loaded or not. Before writing the page to memory, the accessed row must be erased.
Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write
operation to the page addressed by ADDR when the last location of the page is written.
Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will
be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in
memory is to be written.
22.6.4.3.1 Procedure for Manual Page Writes (CTRLB.MANW=1)
The row to be written to must be erased before the write command is given.
•
•
•
Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access through the
AHB will be stalled
22.6.4.3.2 Procedure for Automatic Page Writes (CTRLB.MANW=0)
The row to be written to must be erased before the last write to the page buffer is performed.
Note that partially written pages must be written with a manual write.
•
Write to the page buffer by addressing the NVM main address space directly.
When the last location in the page buffer is written, the page is automatically written to NVM main address
space.
•
INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.
22.6.4.4 Page Buffer Clear
The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been written and it
is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.
22.6.4.5 Erase Row
Before a page can be written, the row containing that page must be erased. The Erase Row command can be used
to erase the desired row in the NVM main address space. The RWWEE Erase Row can be used to erase the desired
row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides in a region that is locked, the erase will
not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.
22.6.4.5.1 Procedure for Erase Row
•
Write the address of the row to erase to ADDR. Any address within the row can be used.
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Nonvolatile Memory Controller (NVMCTRL)
•
Issue an Erase Row command.
Note:ꢀ The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
22.6.4.6 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section 22.6.3 Region Lock Bits.
22.6.4.7 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the Set and Clear Power
Reduction Mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction
Mode bit in the Status register (STATUS.PRM) is set.
22.6.5 NVM User Configuration
The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the device for
calibration and auxiliary space address mapping.
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write-protected.
Table 22-2.ꢀBoot Loader Size
BOOTPROT [2:0]
Rows Protected by BOOTPROT
Boot Loader Size in Bytes
0x7(1)
0x6
0x5
0x4
0x3
0x2
0x1
0x0
None
2
0
512
4
1024
2048
4096
8192
16384
32768
8
16
32
64
128
Note:ꢀ
1. Default value is 0x7.
The EEPROM[2:0] bits indicate the EEPROM Emulation size, see the table below. The EEPROM Emulation resides
in the upper rows of the NVM main address space and is writable, regardless of the region lock status. Note that it is
different from the RWWEE Emulation section residing outside of the main Flash.
Table 22-3.ꢀEEPROM Emulation Size
EEPROM[2:0]
Rows Allocated to EEPROM Emulation
EEPROM Emulation Size in Bytes
7
6
5
4
3
2
1
0
None
1
0
256
2
512
4
1024
2048
4096
8192
16384
8
16
32
64
Related Links
10.2 Physical Memory Map
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Nonvolatile Memory Controller (NVMCTRL)
22.6.6 Security Bit
The security bit allows the entire chip to be locked from external access for code security. The security bit can be
written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a
debugger Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked.
In order to increase the security level it is recommended to enable the internal BOD33 when the security bit is set.
Related Links
13. DSU - Device Service Unit
22.6.7 Cache
The NVM Controller cache reduces the device power consumption and improves system performance when wait
states are required. Only the NVM main array address space is cached. It is a direct-mapped cache that implements
8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache Disable bit in the
Control B register (CTRLB.CACHEDIS).
The cache can be configured to three different modes using the Read Mode bit group in the Control B register
(CTRLB.READMODE).
The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines
(CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache lines.
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Nonvolatile Memory Controller (NVMCTRL)
22.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
CMD[6:0]
0x00
CTRLA
15:8
CMDEX[7:0]
0x02
...
Reserved
CTRLB
0x03
7:0
15:8
23:16
31:24
7:0
MANW
RWS[3:0]
CACHEDIS
SLEEPPRM[1:0]
READMODE[1:0]
0x04
0x08
NVMP[7:0]
15:8
23:16
31:24
7:0
NVMP[15:8]
PARAM
RWWEEP[3:0]
PSZ[2:0]
RWWEEP[11:4]
0x0C
0x0D
...
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
ERROR
ERROR
ERROR
LOAD
READY
READY
READY
0x0F
0x10
0x11
...
7:0
7:0
0x13
0x14
0x15
...
0x17
7:0
NVME
LOCKE
PROGE
PRM
SB
0x18
STATUS
15:8
0x1A
...
Reserved
0x1B
7:0
15:8
23:16
31:24
7:0
ADDR[7:0]
ADDR[15:8]
0x1C
0x20
ADDR
LOCK
ADDR[21:16]
LOCK[7:0]
15:8
LOCK[15:8]
22.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
CMDEX[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
CMD[6:0]
R/W
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 15:8 – CMDEX[7:0]ꢀCommand Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value
different from the key value is tried, the write will not be performed and the Programming Error bit in the Status
register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same
cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when
the NVM block and the AHB bus are idle.
INTFLAG.READY must be '1' when the command is issued.
Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.
Note:ꢀ The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
Bits 6:0 – CMD[6:0]ꢀCommand
These bits define the command to be executed when the CMDEX key is written.
CMD[6:0] Group
Configuration
Description
0x00-0x01
0x02
-
Reserved
ER
Erase Row - Erases the row addressed by the ADDR register in the NVM main
array.
0x03
0x04
-
Reserved
WP
Write Page - Writes the contents of the page buffer to the page addressed by
the ADDR register.
0x05
0x06
EAR
WAP
Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register.
This command can be given only when the Security bit is not set and only to the
User Configuration Row.
Write Auxiliary Page - Writes the contents of the page buffer to the page
addressed by the ADDR register. This command can be given only when the
Security bit is not set and only to the User Configuration Row.
0x07-0x0E -
0x0F
0x1A-0x19 -
Reserved
Reserved
Reserved
-
0x1A
RWWEEER
RWWEE Erase Row - Erases the row addressed by the ADDR register in the
RWWEE array.
0x1B
0x1C
-
Reserved
RWWEEWP
RWWEE Write Page - Writes the contents of the page buffer to the page
addressed by the ADDR register in the RWWEE array.
0x1D-0x3F -
Reserved
0x40
LR
Lock Region - Locks the region containing the address location in the ADDR
register.
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Nonvolatile Memory Controller (NVMCTRL)
...........continued
CMD[6:0] Group
Description
Configuration
0x41
UR
Unlock Region - Unlocks the region containing the address location in the ADDR
register.
0x42
0x43
0x44
0x45
SPRM
CPRM
PBC
Sets the Power Reduction mode.
Clears the Power Reduction mode.
Page Buffer Clear - Clears the page buffer.
Set Security Bit - Sets the Security bit by writing 0x00 to the first byte in the
SSB
lockbit row.
0x46
0x47
INVALL
LDR
Invalidates all cache lines.
Lock Data Region - Locks the data region containing the address location in the
ADDR register.
When the security extension is enabled, only secure access can lock secure
regions.
0x48
UDR
-
Unlock Data Region - Unlocks the data region containing the address location in
the ADDR register.
When the security extension is enabled, only secure access can unlock secure
regions.
0x47-0x7F
Reserved
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Nonvolatile Memory Controller (NVMCTRL)
22.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x00000080
Property:ꢀ PAC Write-Protection
Bit
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
25
17
24
16
Access
Reset
Bit
18
CACHEDIS
R/W
READMODE[1:0]
Access
Reset
R/W
0
R/W
0
0
Bit
10
9
8
SLEEPPRM[1:0]
Access
Reset
R/W
0
R/W
0
Bit
7
MANW
R/W
1
2
1
0
RWS[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 18 – CACHEDISꢀCache Disable
This bit is used to disable the cache.
Value
Description
0
1
The cache is enabled
The cache is disabled
Bits 17:16 – READMODE[1:0]ꢀNVMCTRL Read Mode
Value
Name
Description
0x0
NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache
miss. Gives the best system performance.
0x1
0x2
0x3
LOW_POWER
DETERMINISTIC
Reserved
Reduces power consumption of the cache system, but inserts a wait state each
time there is a cache miss. This mode may not be relevant if CPU performance
is required, as the application will be stalled and may lead to increased run
time.
The cache system ensures that a cache hit or miss takes the same amount
of time, determined by the number of programmed Flash wait states. This
mode can be used for real-time applications that require deterministic execution
timings.
Bits 9:8 – SLEEPPRM[1:0]ꢀPower Reduction Mode during Sleep
Indicates the Power Reduction Mode during sleep.
Value
Name
Description
0x0
WAKEUPACCESS
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode upon first access.
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode when exiting sleep.
0x1
WAKEUPINSTANT
0x2
0x3
Reserved
DISABLED
Auto power reduction disabled.
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Nonvolatile Memory Controller (NVMCTRL)
Bit 7 – MANWꢀManual Write
Note that reset value of this bit is '1'.
Value
Description
0
Writing to the last word in the page buffer will initiate a write operation to the page addressed by the
last write operation. This includes writes to memory and auxiliary rows.
1
Write commands must be issued through the CTRLA.CMD register.
Bits 4:1 – RWS[3:0]ꢀNVM Read Wait States
These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1' indicates one wait
state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system
frequency.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.3 NVM Parameter
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PARAM
0x08
0x000XXXXX
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
RWWEEP[11:4]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
11
18
17
16
RWWEEP[3:0]
PSZ[2:0]
Access
Reset
R
0
R
0
R
0
R
0
R
x
R
x
R
x
Bit
15
14
13
12
10
9
8
NVMP[15:8]
NVMP[7:0]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bits 31:20 – RWWEEP[11:0]ꢀRead While Write EEPROM Emulation area Pages
Indicates the number of pages in the RWW EEPROM Emulation address space.
Bits 18:16 – PSZ[2:0]ꢀPage Size
Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in the table.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
8
16
32
64
128
256
512
1024
Description
8 bytes
16 bytes
32 bytes
64 bytes
128 bytes
256 bytes
512 bytes
1024 bytes
Bits 15:0 – NVMP[15:0]ꢀNVM Pages
Indicates the number of pages in the NVM main address space.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x0C
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
R/W
0
Access
Reset
Bit 1 – ERRORꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READYꢀNVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x10
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
R/W
0
Access
Reset
Bit 1 – ERRORꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READYꢀNVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x14
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
ERROR
R/W
0
0
READY
Access
Reset
R
0
Bit 1 – ERRORꢀError
This flag is set on the occurrence of an NVME, LOCKE or PROGE error.
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
1
No errors have been received since the last clear.
At least one error has occurred since the last clear.
Bit 0 – READYꢀNVM Ready
Value
Description
0
1
The NVM controller is busy programming or erasing.
The NVM controller is ready to accept a new command.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.7 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x18
0x0X00
–
Property:ꢀ
Bit
15
7
14
6
13
5
12
11
10
9
8
SB
R
Access
Reset
x
Bit
4
NVME
R/W
0
3
LOCKE
R/W
0
2
PROGE
R/W
0
1
LOAD
R/W
0
0
PRM
R
Access
Reset
0
Bit 8 – SBꢀSecurity Bit Status
Value
Description
0
1
The Security bit is inactive.
The Security bit is active.
Bit 4 – NVMEꢀNVM Error
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No programming or erase errors have been received from the NVM controller since this bit was last
cleared.
1
At least one error has been registered from the NVM Controller since this bit was last cleared.
Bit 3 – LOCKEꢀLock Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
1
No programming of any locked lock region has happened since this bit was last cleared.
Programming of at least one locked lock region has happened since this bit was last cleared.
Bit 2 – PROGEꢀProgramming Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No invalid commands or bad keywords were written in the NVM Command register since this bit was
last cleared.
1
An invalid command and/or a bad keyword was/were written in the NVM Command register since this
bit was last cleared.
Bit 1 – LOADꢀNVM Page Buffer Active Loading
This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load
has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is
given.
This bit can be cleared by writing a '1' to its bit location.
Bit 0 – PRMꢀPower Reduction Mode
This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two
ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly.
PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM
and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
Value
Description
0
NVM is not in power reduction mode.
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Nonvolatile Memory Controller (NVMCTRL)
Value
Description
1
NVM is in power reduction mode.
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Nonvolatile Memory Controller (NVMCTRL)
22.8.8 Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x1C
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
23
15
30
22
14
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
ADDR[21:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
13
12
11
10
9
8
ADDR[15:8]
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 21:0 – ADDR[21:0]ꢀNVM Address
ADDR drives the hardware half-word offset from the start address of the corresponding NVM section when a
command is executed using CMDEX. This register is also automatically updated when writing to the page buffer. The
effective address for the operation is Start address of the section + 2*ADDR.
Example:
For erasing the 3rd row in the Flash memory, spanning from 0x00000200 to 0x000002FF, ADDR must be written with
the half-word offset address of any half-word within this range, that is any value between 0x100 and 0x17F.
For erasing the 5th row in the RWWEE memory, spanning from 0x00400400 to 0x004004FF, ADDR should be written
with the half-word offset address of any half-word within this range, that is any value between 0x200 and 0x27F.
DS40001882G-page 361
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Nonvolatile Memory Controller (NVMCTRL)
22.8.9 Lock Section
Name:ꢀ
LOCK
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x20
0xXXXX
–
Bit
15
14
13
12
11
10
9
8
LOCK[15:8]
LOCK[7:0]
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Bits 15:0 – LOCK[15:0]ꢀRegion Lock Bits
To set or clear these bits, the CMD register must be used.
Default state after erase will be unlocked (0xFFFF).
Default state after reset will be loaded from the NVM User Row.
Value
Description
0
1
The corresponding lock region is locked.
The corresponding lock region is not locked.
DS40001882G-page 362
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SAM D21/DA1 Family
PORT - I/O Pin Controller
23.
PORT - I/O Pin Controller
23.1
Overview
The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups,
collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and
controlled individually or as a group. The number of PORT groups on a device may depend on the package/number
of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an
embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with
highly configurable driver and pull settings.
All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output
value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state
of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write.
The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output
®
Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM
single-cycle I/O port) .
23.2
Features
•
•
•
•
Selectable input and output configuration for each individual pin
Software-controlled multiplexing of peripheral functions on I/O pins
Flexible pin configuration through a dedicated Pin Configuration register
Configurable output driver and pull settings:
– Totem-pole (push-pull)
– Pull configuration
– Driver strength
•
Configurable input buffer and pull settings:
– Internal pull-up or pull-down
– Input sampling criteria
– Input buffer can be disabled if not needed for lower power consumption
– Read-Modify-Write support for output value (OUTCLR/OUTSET/OUTGL) and pin direction (DIRCLR/
DIRSET/DIRTGL)
DS40001882G-page 363
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.3
Block Diagram
Figure 23-1.ꢀPORT Block Diagram
PORT
Peripheral Mux Select
Control
and
Port Line
Bundles
Status
Pad Line
Bundles
I/O
IP Line Bundles
PADS
Analog Pad
Connections
PERIPHERALS
Digital Controls of Analog Blocks
ANALOG
BLOCKS
23.4
Signal Description
Table 23-1.ꢀSignal description for PORT
Signal name
Type
Description
Pxy
Digital I/O
General-purpose I/O pin y in group x
Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
23.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly as follows.
23.5.1 I/O Lines
The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is used:
Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit number y=00,
01, …31. Examples: A24, C03.
PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device uniquely.
Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be routed
internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral has control over
the output state of the pad, as well as the ability to read the current physical pad state. Refer to I/O Multiplexing and
Considerations for details.
Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented.
DS40001882G-page 364
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
Related Links
7. I/O Multiplexing and Considerations
23.5.2 Power Management
During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
The PORT peripheral will continue operating in any sleep mode where its source clock is running.
23.5.3 Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_PORT_APB can be found in the Peripheral Clock Masking section in PM – Power Manager.
The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to access the
registers of PORT through the high-speed matrix and the AHB/APB bridge.
The PORT also requires an AHB clock for CPU IOBUS accesses to the PORT. That AHB clock is the internal PORT
clock.
The priority of IOBUS accesses is higher than APB accesses. One clock cycle latency can be observed on the APB
access in case of concurrent PORT accesses.
Related Links
16.6.2.6 Peripheral Clock Masking
23.5.4 DMA
Not applicable.
23.5.5 Interrupts
Not applicable.
23.5.6 Events
Not applicable.
23.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation.
23.5.8 Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC).
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
23.5.9 Analog Connections
Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However,
selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad.
23.5.10 CPU Local Bus
The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus
interface, which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes.
This bus is generally used for low latency operation. The Data Direction (DIR) and Data Output Value (OUT) registers
can be read, written, set, cleared or be toggled using this bus, and the Data Input Value (IN) registers can be read.
Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to
continuous sampling of all pins that need to be read via the IOBUS in order to prevent stale data from being read.
Note:ꢀ Refer to the Product Mapping chapter for the IOBUS address.
DS40001882G-page 365
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.6
Functional Description
Figure 23-2.ꢀOverview of the PORT
PORT
PAD
PULLEN
DRIVE
PULLENx
DRIVEx
VDDIO
Pull
Resistor
PG
OUT
OE
OUTx
DIRx
PAD
VDD
NG
INEN
IN
INENx
INx
Q
D
Q
D
R
R
Synchronizer
Input to Other Modules Analog Input/Output
23.6.1 Principle of Operation
Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers
in PORT are duplicated for each PORT group, with increasing base addresses. The number of PORT groups may
depend on the package/number of pins.
Figure 23-3.ꢀOverview of the peripheral functions multiplexing
PORT bit y
PORTMUX
Port y Peripheral
Mux Enable
Port y PINCFG
PMUXEN
Port y Line Bundle
Port y
Data+Config
0
Port y PMUX Select
Port y
PMUX[3:0]
PAD y
Pad y
Line Bundle
Periph Signal 0
Periph Signal 1
0
1
1
Peripheral Signals to
be muxed to Pad y
Periph Signal 15
15
The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the
Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the Output
state.
The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the
corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an
input pin.
DS40001882G-page 366
Complete Datasheet
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SAM D21/DA1 Family
PORT - I/O Pin Controller
When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in
OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be
set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the pin number within the group.
The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce
power consumption, these input synchronizers can be clocked only when system requires reading the input value, as
specified in the SAMPLING field of the Control register (CTRL). The value of the pin can always be read, whether the
pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0',
the input value will not be sampled.
In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to
enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn)
registers select the peripheral function for the corresponding pin. This will override the connection between the PORT
and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.
23.6.2 Basic Operation
23.6.2.1 Initialization
After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers
disabled, even if there is no clock running.
However, specific pins, such as those used for connection to a debugger, may be configured differently, as required
by their special function.
23.6.2.2 Operation
Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers,
with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc...).
Within that set of registers, the pin index is y, from 0 to 31.
Refer to I/O Multiplexing and Considerations for details on available pin configuration and PORT groups.
Configuring Pins as Output
To use pin Pxy as an output, write bit y of the DIR register to '1'. This can also be done by writing bit y in the DIRSET
register to '1' - this will avoid disturbing the configuration of other pins in that group. The y bit in the OUT register must
be written to the desired output value.
Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit in OUTCLR
to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT.
Configuring Pins as Input
To use pin Pxy as an input, bit y in the DIR register must be written to '0'. This can also be done by writing bit y in the
DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group. The input value can be
read from bit y in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy.INEN) is written to '1'
to enable the pin's input buffer.
By default, the input synchronizer is clocked only when an input read is requested. This will delay the read operation
by two cycles of the PORT clock. To remove the delay, the input synchronizers for each PORT group of eight pins
can be configured to be always active, but this will increase power consumption. This is enabled by writing '1' to the
corresponding SAMPLINGn bit field of the CTRL register, see CTRL.SAMPLING for details.
Using Alternative Peripheral Functions
To use pin Pxy as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy register
must be '1'. The PINCFGy register for pin Pxy is at byte offset (PINCFG0 + y).
The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/
PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled.
Related Links
7. I/O Multiplexing and Considerations
DS40001882G-page 367
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.6.3 I/O Pin Configuration
The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole
or pull configuration.
As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of
pin direction and pin values are avoided.
The I/O pin configurations are described further in this chapter, and summarized in Table 23-2.
23.6.3.1 Pin Configurations Summary
Table 23-2.ꢀPin Configurations Summary
DIR
0
INEN
PULLEN
OUT
X
Configuration
0
0
0
1
1
1
0
1
0
1
1
0
1
1
X
X
Reset or analog I/O: all digital disabled
Pull-down; input buffer disabled
Pull-up; input buffer disabled
Input
0
0
0
1
0
X
0
0
Input with pull-down
0
1
Input with pull-up
1
X
Output; input buffer disabled
Output; input buffer enabled
1
X
23.6.3.2 Input Configuration
Figure 23-4.ꢀI/O configuration - Standard Input
PULLEN INEN DIR
PULLEN
0
0
1
DIR
OUT
IN
INEN
Figure 23-5.ꢀI/O Configuration - Input with Pull
PULLEN INEN DIR
PULLEN
0
1
1
DIR
OUT
IN
INEN
Note:ꢀ When pull is enabled, the pull value is defined by the OUT value.
23.6.3.3 Totem-Pole Output
When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit
setting in the OUT register. In this configuration there is no current limitation for sink or source other than what the pin
is capable of. If the pin is configured for input, the pin will float if no external pull is connected.
Note:ꢀ Enabling the output driver will automatically disable pull.
DS40001882G-page 368
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SAM D21/DA1 Family
PORT - I/O Pin Controller
Figure 23-6.ꢀI/O Configuration - Totem-Pole Output with Disabled Input
PULLEN INEN DIR
PULLEN
1
0
0
DIR
OUT
IN
INEN
Figure 23-7.ꢀI/O Configuration - Totem-Pole Output with Enabled Input
PULLEN INEN DIR
PULLEN
1
0
1
DIR
OUT
IN
INEN
Figure 23-8.ꢀI/O Configuration - Output with Pull
PULLEN INEN DIR
PULLEN
0
1
0
DIR
OUT
IN
INEN
23.6.3.4 Digital Functionality Disabled
Neither Input nor Output functionality are enabled.
Figure 23-9.ꢀI/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled
PULLEN INEN DIR
PULLEN
0
0
0
DIR
OUT
IN
INEN
23.6.4 PORT Access Priority
The PORT is accessed by different systems:
®
®
•
•
The ARM CPU through the ARM single-cycle I/O port (IOBUS)
®
The ARM CPU through the high-speed matrix and the AHB/APB bridge (APB)
The following priority is adopted:
DS40001882G-page 369
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
®
1. ARM CPU IOBUS (No wait tolerated)
2. APB
DS40001882G-page 370
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.7
Register Summary
The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the
PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register
address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address
offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
23:16
31:24
7:0
DIR[7:0]
DIR[15:8]
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
DIR
DIR[23:16]
DIR[31:24]
DIRCLR[7:0]
15:8
23:16
31:24
7:0
DIRCLR[15:8]
DIRCLR[23:16]
DIRCLR[31:24]
DIRSET[7:0]
DIRCLR
DIRSET
DIRTGL
OUT
15:8
23:16
31:24
7:0
DIRSET[15:8]
DIRSET[23:16]
DIRSET[31:24]
DIRTGL[7:0]
15:8
23:16
31:24
7:0
DIRTGL[15:8]
DIRTGL[23:16]
DIRTGL[31:24]
OUT[7:0]
15:8
23:16
31:24
7:0
OUT[15:8]
OUT[23:16]
OUT[31:24]
OUTCLR[7:0]
OUTCLR[15:8]
OUTCLR[23:16]
OUTCLR[31:24]
OUTSET[7:0]
OUTSET[15:8]
OUTSET[23:16]
OUTSET[31:24]
OUTTGL[7:0]
OUTTGL[15:8]
OUTTGL[23:16]
OUTTGL[31:24]
IN[7:0]
15:8
23:16
31:24
7:0
OUTCLR
OUTSET
OUTTGL
IN
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
IN[15:8]
IN[23:16]
IN[31:24]
SAMPLING[7:0]
SAMPLING[15:8]
SAMPLING[23:16]
SAMPLING[31:24]
PINMASK[7:0]
PINMASK[15:8]
15:8
23:16
31:24
7:0
CTRL
15:8
23:16
31:24
WRCONFIG
DRVSTR
PULLEN
INEN
PMUXEN
HWSEL
WRPINCFG
WRPMUX
PMUX[3:0]
0x2C
...
Reserved
PMUX0
0x2F
0x30
...
7:0
PMUXO[3:0]
PMUXE[3:0]
PMUXE[3:0]
0x3F
0x40
...
PMUX15
PINCFG0
7:0
7:0
PMUXO[3:0]
DRVSTR
PULLEN
INEN
PMUXEN
DS40001882G-page 371
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
...........continued
Offset
Name
PINCFG31
Bit Pos.
7
6
5
4
3
2
1
0
0x5F
7:0
DRVSTR
PULLEN
INEN
PMUXEN
23.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 23.5.8 Register Access Protection.
DS40001882G-page 372
Complete Datasheet
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SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.1 Data Direction
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DIR
0x00
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated
without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear
(DIRCLR) and Data Direction Set (DIRSET) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
DIR[31:24]
DIR[23:16]
DIR[15:8]
DIR[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIR[31:0]ꢀPort Data Direction
These bits set the data direction for the individual I/O pins in the PORT group.
Value
Description
0
1
The corresponding I/O pin in the PORT group is configured as an input.
The corresponding I/O pin in the PORT group is configured as an output.
DS40001882G-page 373
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PORT - I/O Pin Controller
23.8.2 Data Direction Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DIRCLR
0x04
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Set (DIRSET) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
DIRCLR[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
DIRCLR[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
DIRCLR[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
DIRCLR[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRCLR[31:0]ꢀPort Data Direction Clear
Writing a '0' to a bit has no effect.
Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.
Value
Description
0
1
The corresponding I/O pin in the PORT group will keep its configuration.
The corresponding I/O pin in the PORT group is configured as input.
DS40001882G-page 374
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.3 Data Direction Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DIRSET
0x08
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Clear (DIRCLR) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
DIRSET[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
DIRSET[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
DIRSET[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
DIRSET[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRSET[31:0]ꢀPort Data Direction Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output.
Value
Description
0
1
The corresponding I/O pin in the PORT group will keep its configuration.
The corresponding I/O pin in the PORT group is configured as an output.
DS40001882G-page 375
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.4 Data Direction Toggle
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DIRTGL
0x0C
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and
Data Direction Clear (DIRCLR) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
DIRTGL[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
DIRTGL[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
DIRTGL[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
DIRTGL[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – DIRTGL[31:0]ꢀPort Data Direction Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin.
Value
Description
0
1
The corresponding I/O pin in the PORT group will keep its configuration.
The direction of the corresponding I/O pin is toggled.
DS40001882G-page 376
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.5 Data Output Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OUT
0x10
0x00000000
Property:ꢀ PAC Write-Protection
This register sets the data output drive value for the individual I/O pins in the PORT.
This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear
(OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
OUT[31:24]
OUT[23:16]
OUT[15:8]
OUT[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – OUT[31:0]ꢀPORT Data Output Value
For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive level.
For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable bit in the
Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction.
Value
Description
0
1
The I/O pin output is driven low, or the input is connected to an internal pull-down.
The I/O pin output is driven high, or the input is connected to an internal pull-up.
DS40001882G-page 377
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.6 Data Output Value Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OUTCLR
0x14
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Set (OUTSET) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
OUTCLR[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
OUTCLR[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
OUTCLR[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
OUTCLR[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTCLR[31:0]ꢀPORT Data Output Value Clear
Writing '0' to a bit has no effect.
Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the Data
Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and with pull enabled
via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the input pull direction to an
internal pull-down.
Value
Description
0
1
The corresponding I/O pin in the PORT group will keep its configuration.
The corresponding I/O pin output is driven low, or the input is connected to an internal pull-down.
DS40001882G-page 378
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.7 Data Output Value Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OUTSET
0x18
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
OUTSET[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
OUTSET[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
OUTSET[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
OUTSET[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTSET[31:0]ꢀPORT Data Output Value Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins
configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register
(DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal
pull-up.
Value
Description
0
1
The corresponding I/O pin in the group will keep its configuration.
The corresponding I/O pin output is driven high, or the input is connected to an internal pull-up.
DS40001882G-page 379
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.8 Data Output Value Toggle
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OUTTGL
0x1C
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set
(OUTSET) and Data Output Value Clear (OUTCLR) registers.
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
OUTTGL[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
OUTTGL[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
OUTTGL[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
OUTTGL[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – OUTTGL[31:0]ꢀPORT Data Output Value Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins
configured as outputs via the Data Direction register (DIR). For pins configured as inputs via Data Direction register
(DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input pull direction.
Value
Description
0
1
The corresponding I/O pin in the PORT group will keep its configuration.
The corresponding OUT bit value is toggled.
DS40001882G-page 380
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.9 Data Input Value
Name:ꢀ
IN
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x20
0x00000000
-
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
IN[31:24]
IN[23:16]
IN[15:8]
IN[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 31:0 – IN[31:0]ꢀPORT Data Input Value
These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin.
These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin.
DS40001882G-page 381
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.10 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x24
0x00000000
Property:ꢀ PAC Write-Protection
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit
31
30
29
28
27
26
25
24
SAMPLING[31:24]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
23
22
21
20
19
18
17
16
SAMPLING[23:16]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
SAMPLING[15:8]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
7
6
5
4
3
2
1
0
SAMPLING[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 31:0 – SAMPLING[31:0]ꢀInput Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data
Direction register (DIR).
The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request
continuous sampling, all pins in that eight pin sub-group will be continuously sampled.
Value
Description
0
1
On demand sampling of I/O pin is enabled.
Continuous sampling of I/O pin is enabled.
DS40001882G-page 382
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.11 Write Configuration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WRCONFIG
0x28
0x00000000
Property:ꢀ PAC Write-Protection, Write-Only
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
This Write-only register is used to configure several pins simultaneously with the same configuration and peripheral
multiplexing.
To avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this
register always returns zero.
Bit
31
HWSEL
W
30
29
21
13
28
27
26
25
24
WRPINCFG
WRPMUX
PMUX[3:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
0
Bit
23
22
20
19
18
17
INEN
W
16
DRVSTR
PULLEN
PMUXEN
Access
Reset
W
0
W
0
W
0
0
Bit
15
14
12
11
10
9
8
PINMASK[15:8]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
PINMASK[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit 31 – HWSELꢀHalf-Word Select
This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.
This bit will always read as zero.
Value
Description
0
1
The lower 16 pins of the PORT group will be configured.
The upper 16 pins of the PORT group will be configured.
Bit 30 – WRPINCFGꢀWrite PINCFG
This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for
all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR,
WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.
This bit will always read as zero.
Value
Description
0
1
The PINCFGy registers of the selected pins will not be updated.
The PINCFGy registers of the selected pins will be updated.
DS40001882G-page 383
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
Bit 28 – WRPMUXꢀWrite PMUX
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not
for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX
value.
This bit will always read as zero.
Value
Description
0
1
The PMUXn registers of the selected pins will not be updated.
The PMUXn registers of the selected pins will be updated.
Bits 27:24 – PMUX[3:0]ꢀPeripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by
the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.
These bits will always read as zero.
Bit 22 – DRVSTRꢀOutput Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 18 – PULLENꢀPull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 17 – INENꢀInput Enable
This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and
WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 16 – PMUXENꢀPeripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bits 15:0 – PINMASK[15:0]ꢀPin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.
These bits will always read as zero.
Value
Description
0
1
The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
The configuration of the corresponding I/O pin in the half-word PORT group will be updated.
DS40001882G-page 384
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.12 Peripheral Multiplexing n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PMUX
0x30 + n*0x01 [n=0..15]
0x00
Property:ꢀ PAC Write-Protection
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The
n denotes the number of the set of I/O lines.
Bit
7
6
5
4
3
2
1
0
PMUXO[3:0]
PMUXE[3:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7:4 – PMUXO[3:0]ꢀPeripheral Multiplexing for Odd-Numbered Pin
These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and
Considerations.
PMUXO[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
A
B
C
D
E
F
G
H
I
Peripheral function A selected
Peripheral function B selected
Peripheral function C selected
Peripheral function D selected
Peripheral function E selected
Peripheral function F selected
Peripheral function G selected
Peripheral function H selected
Peripheral function I selected
Reserved
0x9-0xF
-
Bits 3:0 – PMUXE[3:0]ꢀPeripheral Multiplexing for Even-Numbered Pin
These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and
Considerations.
PMUXE[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
A
B
C
D
E
F
G
H
I
Peripheral function A selected
Peripheral function B selected
Peripheral function C selected
Peripheral function D selected
Peripheral function E selected
Peripheral function F selected
Peripheral function G selected
Peripheral function H selected
Peripheral function I selected
DS40001882G-page 385
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
...........continued
PMUXE[3:0]
0x9-0xF
Name
Description
-
Reserved
Related Links
7. I/O Multiplexing and Considerations
DS40001882G-page 386
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
PORT - I/O Pin Controller
23.8.13 Pin Configuration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PINCFG
0x40 + n*0x01 [n=0..31]
0x00
Property:ꢀ PAC Write-Protection
Tip:ꢀ The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
Bit
7
6
DRVSTR
RW
5
4
3
2
PULLEN
RW
1
INEN
RW
0
0
PMUXEN
RW
Access
Reset
0
0
0
Bit 6 – DRVSTRꢀOutput Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
Value
Description
0
1
Pin drive strength is set to normal drive strength.
Pin drive strength is set to stronger drive strength.
Bit 2 – PULLENꢀPull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
Value
0
Description
Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1
Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of
external input.
Bit 1 – INENꢀInput Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the Physical Pin state when the
pin is configured as either an input or output.
Value
Description
0
1
Input buffer for the I/O pin is disabled, and the input value will not be sampled.
Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
Bit 0 – PMUXENꢀPeripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to
enable or disable alternative peripheral control over an I/O pin direction and output drive value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output
drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored. Writing
'1' to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the Physical Pin state
may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set.
Value
Description
0
The peripheral multiplexer selection is disabled, and the PORT registers control the direction and
output drive value.
1
The peripheral multiplexer selection is enabled, and the selected peripheral function controls the
direction and output drive value.
DS40001882G-page 387
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.
EVSYS – Event System
24.1
Overview
The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals.
Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
respond to events are called event users. Peripherals that generate events are called event generators. A peripheral
can have one or more event generators and can have one or more event users.
Communication is made without CPU intervention and without consuming system resources such as bus or RAM
bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based
system.
24.2
Features
•
12 configurable event channels:
– Can be connected to any event generator
– Can provide a pure asynchronous, resynchronized, or synchronous path
74 Event Generators
•
•
•
•
•
•
•
29 Event Users
Configurable Edge Detector
Peripherals can be Event Generators, Event Users, or both
SleepWalking and interrupt for operation in sleep modes
Software Event Generation
Each Event User can choose which channel to respond to, and several Event Users can share the same
channel and therefore answer to the same event
24.3
Block Diagram
Figure 24-1.ꢀEvent System Block Diagram
EVSYS
EVENT
CHANNELS
USER
MUX
PERIPHERALS
GENERATOR
EVENTS
PERIPHERALS
USERS EVENTS
CLOCK REQUESTS
GCLK
24.4
Signal Description
Not applicable.
DS40001882G-page 388
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
24.5.1 I/O Lines
Not applicable.
24.5.2 Power Management
The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel
and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the different sleep modes.
In all sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS clock.
Some event generators can generate an event when their clocks are stopped.
Related Links
16. PM – Power Manager
24.5.3 Clocks
The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and the default
state of CLK_EVSYS_APB can be found in Peripheral Clock Masking.
Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for event
detection and propagation for each channel. These clocks must be configured and enabled in the generic clock
controller before using the EVSYS. Refer to GCLK - Generic Clock Controller for details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
24.5.4 DMA
Not applicable.
24.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires the interrupt
controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
24.5.6 Events
Not applicable.
24.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging.
24.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
Interrupt Flag Status and Clear register (INTFLAG)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
24.5.9 Analog Connections
Not applicable.
DS40001882G-page 389
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.6
Functional Description
24.6.1 Principle of Operation
The Event System consists of several channels which route the internal events from peripherals (generators) to other
internal peripherals or IO pins (users). Each event generator can be selected as source for multiple channels, but a
channel cannot be set to use multiple event generators at the same time.
24.6.2 Basic Operation
24.6.2.1 Initialization
Before enabling events routing within the system, the User Multiplexer (USER) and Channel (CHANNEL) register
must be configured. The User Multiplexer (USER) must be configured first.
Configure the User Multiplexer (USER) register:
1. The channel to be connected to a user is written to the Channel bit group (USER.CHANNEL)
2. The user to connect the channel is written to the User bit group (USER.USER)
Configure the Channel (CHANNEL) register:
1. The channel to be configured is written to the Channel Selection bit group (CHANNEL.CHANNEL)
2. The path to be used is written to the Path Selection bit group (CHANNEL.PATH)
3. The type of edge detection to use on the channel is written to the Edge Selection bit group
(CHANNEL.EDGSEL)
4. The event generator to be used is written to the Event Generator bit group (CHANNEL.EVGEN)
24.6.2.2 Enabling, Disabling and Resetting
The EVSYS is always enabled.
The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control register (CTRL.SWRST). All registers in
the EVSYS will be reset to their initial state and all ongoing events will be canceled. Refer to CTRL.SWRST register
for details.
24.6.2.3 User Multiplexer Setup
The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is dedicated
to one event user. A user multiplexer receives all event channels output and must be configured to select one of
these channels, as shown in the next figure. The channel is selected with the Channel bit group in the USER register
(USER.CHANNEL). The user multiplexer must always be configured before the channel. A full list of selectable users
can be found in the User Multiplexer register (USER) description. Refer to UserList for details.
To configure a user multiplexer, the USER register must be written in a single 16-bit write. It is possible to read
out the configuration of a user by first selecting the user by writing to USER.USER using an 8-bit write and then
performing a read of the 16-bit USER register.
DS40001882G-page 390
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
Figure 24-2.ꢀUser MUX
CHANNEL_EVT_0
CHANNEL_EVT_1
CHANNEL_EVT_m
USER
MUX
USER.CHANNEL
USER_EVT_y
USER_EVT_z
USER_EVT_x
PERIPHERAL A
PERIPHERAL B
24.6.2.4 Channel Setup
An event channel can select one event from a list of event generators. Depending on configuration, the selected
event could be synchronized, resynchronized or asynchronously sent to the users. When synchronization or
resynchronization is required, the channel includes an internal edge detector, allowing the Event System to generate
internal events when rising, falling or both edges are detected on the selected event generator. An event channel
is able to generate internal events for the specific software commands. All these configurations are available in the
Channel register (CHANNEL).
To configure a channel, the Channel register must be written in a single 32-bit write. It is possible to read out the
configuration of a channel by first selecting the channel by writing to CHANNEL.CHANNEL using a, 8-bit write, and
then performing a read of the CHANNEL register.
24.6.2.5 Channel Path
There are three different ways to propagate the event provided by an event generator:
•
•
•
Asynchronous path
Synchronous path
Resynchronized path
DS40001882G-page 391
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
Figure 24-3.ꢀChannel
The path is selected by writing to the Path Selection bit group in the Channel register (CHANNEL.PATH).
24.6.2.5.1 Asynchronous Path
When using the asynchronous path, the events are propagated from the event generator to the event user without
intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory,
meaning that an event will be propagated to the user without any clock latency.
When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel Status
register (CHSTATUS) is always zero. No edge detection is available; this must be handled in the event user. When
the event generator and the event user share the same generic clock, using the asynchronous path will propagate
the event with the least amount of latency.
24.6.2.5.2 Synchronous Path
The synchronous path should be used when the event generator and the event channel share the same generator for
the generic clock and also if event user supports synchronous path. If event user doesn't support synchronous path,
asynchronous path has to be selected. If they do not share the same clock, a logic change from the event generator
to the event channel might not be detected in the channel, which means that the event will not be propagated to the
event user. For details on generic clock generators, refer to GCLK - Generic Clock Controller.
When using the synchronous path, the channel is able to generate interrupts. The channel status bits in the Channel
Status register (CHSTATUS) are also updated and available for use.
If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in
SleepWalking mode and request the configured generic clock only when an event is to be propagated through
the channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel.
Related Links
15. GCLK - Generic Clock Controller
24.6.2.5.3 Resynchronized Path
The resynchronized path should be used when the event generator and the event channel do not share the same
generic clock generator. When the resynchronized path is used, resynchronization of the event from the event
generator is done in the channel. For details on generic clock generators, refer to GCLK - Generic Clock Controller.
When the resynchronized path is used, the channel is able to generate interrupts. The channel status bits in the
Channel Status register (CHSTATUS) are also updated and available for use.
DS40001882G-page 392
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
If the Generic Clocks Request bit in the Control register is zero (CTRL.GCLKREQ=0), the channel operates in
SleepWalking mode and requests the configured generic clock only when an event is to be propagated through the
channel. If CTRL.GCLKREQ=1 , the generic clock will always be on for the configured channel.
Related Links
15. GCLK - Generic Clock Controller
24.6.2.6 Edge Detection
When synchronous or resynchronized paths are used, edge detection must be used. The event system can perform
edge detection in three different ways:
•
•
•
Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges
Edge detection is selected by writing to the Edge Selection bit group in the Channel register (CHANNEL.EDGSEL).
If the generator event is a pulse, both edges cannot be selected. Use the rising edge or falling edge detection
methods, depending on the generator event default level.
24.6.2.7 Event Generators
Each event channel can receive the events form all event generators. All event generators are listed in the statement
of CHANNEL.EVGEN. For details on event generation, refer to the corresponding module chapter. The channel event
generator is selected by the Event Generator bit group in the Channel register (CHANNEL.EVGEN). By default, the
channels are not connected to any event generators (ie, CHANNEL.EVGEN = 0)
24.6.2.8 Channel Status
The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or
resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:
•
The CHSTATUS.CHBUSYn bit will be set when an event on the corresponding channel n has not been handled
by all event users connected to that channel.
•
The CHSTATUS.USRRDYn bit will be set when all event users connected to the corresponding channel are
ready to handle incoming events on that channel.
24.6.2.9 Software Event
A software event can be initiated on a channel by setting the Software Event bit in the Channel register
(CHANNEL.SWEVT) to ‘1’ at the same time as writing the Channel bits (CHANNEL.CHANNEL). This will generate a
software event on the selected channel.
The software event can be used for application debugging, and functions like any event generator. To use
the software event, the event path must be configured to either a synchronous path or resynchronized path
(CHANNEL.PATH = 0x0 or 0x1), edge detection must be configured to rising-edge detection (CHANNEL.EDGSEL=
0x1) and the Generic Clock Request bit must be set to '1' (CTRL.GCLKREQ=0x1).
24.6.3 Interrupts
The EVSYS has the following interrupt sources:
•
•
Overrun Channel n (OVRn): for details, refer to The Overrun Channel n Interrupt section.
Event Detected Channel n (EVDn): for details, refer to The Event Detected Channel n Interrupt section.
These interrupts events are asynchronous wake-up sources. See Sleep Mode Controller.
Each interrupt source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The
flag is set when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the
corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding
bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set
and the corresponding interrupt is enabled. The interrupt event works until the interrupt flag is cleared, the interrupt is
disabled, or the Event System is reset. See INTFLAG for details on how to clear interrupt flags.
All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The event user must read the
INTFLAG register to determine what the interrupt condition is.
DS40001882G-page 393
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
16.6.1.3 Sleep Mode Controller
24.6.3.1 The Overrun Channel n Interrupt
The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.OVR) will be set,
and the optional interrupt will be generated in the following cases:
•
•
One or more event users on channel n is not ready when there is a new event.
An event occurs when the previous event on channel m has not been handled by all event users connected to
that channel.
The flag will only be set when using resynchronized paths. In the case of asynchronous path, the CHINTFLAGn.OVR
is always read as zero.
Related Links
11.2 Nested Vector Interrupt Controller
24.6.3.2 The Event Detected Channel n Interrupt
The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register (CHINTFLAGn.EVD) is set
when an event coming from the event generator configured on channel n is detected.
The flag will only be set when using a resynchronized path. In the case of asynchronous path, the CHINTFLAGn.EVD
is always zero.
Related Links
11.2 Nested Vector Interrupt Controller
24.6.4 Sleep Mode Operation
The EVSYS can generate interrupts to wake up the device from any sleep mode.
Some event generators can generate an event when the system clock is stopped. The generic clock
(GCLK_EVSYS_CHANNELx) for this channel will be restarted if the channel uses a synchronized path or a
resynchronized path, without waking the system from sleep. The clock remains active only as long as necessary
to handle the event. After the event has been handled, the clock will be turned off and the system will remain in the
original sleep mode. This is known as SleepWalking. When an asynchronous path is used, there is no need for the
clock to be activated for the event to be propagated to the user.
On a software reset, all registers are set to their reset values and any ongoing events are canceled.
24.7
Register Summary
Table 24-1.ꢀEvent System Register Summary
Offset
Name
Bit
Pos.
0x00
0x01
...
CTRL
7:0
GCLKREQ
SWRST
SWEVT
Reserved
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
7:0
15:8
23:16
31:24
7:0
CHANNEL[3:0]
CHANNEL
EVGEN[6:0]
EDGSEL[1:0]
USER[4:0]
CHANNEL[4:0]
PATH[1:0]
USER
15:8
Reserved
DS40001882G-page 394
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
...........continued
Offset
Name
Bit
Pos.
0x0B
0x0C
0x0D
Reserved
7:0
15:8
23:16
31:24
7:0
USRRDY7
CHBUSY7
USRRDY6
CHBUSY6
USRRDY5
CHBUSY5
USRRDY4
CHBUSY4
USRRDY3
CHBUSY3
USRRDY2
CHBUSY2
USRRDY1
CHBUSY1
USRRDY9
CHBUSY9
OVR1
USRRDY0
CHBUSY0
USRRDY8
CHBUSY8
OVR0
CHSTATUS
INTENCLR
INTENSET
INTFLAG
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
USRRDY11 USRRDY10
CHBUSY11 CHBUSY10
OVR7
EVD7
OVR6
EVD6
OVR5
EVD5
OVR4
EVD4
OVR3
EVD3
OVR2
EVD2
15:8
23:16
31:24
7:0
EVD1
EVD0
OVR11
EVD11
OVR3
EVD3
OVR10
EVD10
OVR2
EVD2
OVR9
OVR8
EVD9
EVD8
OVR7
EVD7
OVR6
EVD6
OVR5
EVD5
OVR4
EVD4
OVR1
OVR0
15:8
23:16
31:24
7:0
EVD1
EVD0
OVR11
EVD11
OVR3
EVD3
OVR10
EVD10
OVR2
EVD2
OVR9
OVR8
EVD9
EVD8
OVR7
EVD7
OVR6
EVD6
OVR5
EVD5
OVR4
EVD4
OVR1
OVR0
15:8
23:16
31:24
EVD1
EVD0
OVR11
EVD11
OVR10
EVD10
OVR9
OVR8
EVD9
EVD8
24.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
Refer to 24.5.8 Register Access Protection.
DS40001882G-page 395
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.1 Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL
0x00
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
GCLKREQ
R/W
3
2
1
0
SWRST
Access
Reset
W
0
0
Bit 4 – GCLKREQꢀGeneric Clock Requests
This bit is used to determine whether the generic clocks used for the different channels should be on all the time or
only when an event needs the generic clock. Events propagated through asynchronous paths will not need a generic
clock.
Value
Description
0
1
Generic clock is requested and turned on only if an event is detected.
Generic clock for a channel is always on.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the EVSYS to their initial state.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Note:ꢀ Before applying a Software Reset it is recommended to disable the event generators.
DS40001882G-page 396
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.2 Channel
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CHANNEL
0x04
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
15
7
30
29
21
28
20
27
26
25
24
EDGSEL[1:0]
PATH[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
22
19
EVGEN[6:0]
R/W
18
17
16
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
14
13
12
11
10
9
8
SWEVT
R/W
0
Access
Reset
Bit
6
5
4
3
2
1
0
CHANNEL[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 27:26 – EDGSEL[1:0]ꢀEdge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
EDGSEL[1:0] Name
Description
0x0
0x1
NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path
RISING_EDGE
FALLING_EDGE
BOTH_EDGES
Event detection only on the rising edge of the signal from the event generator
when using the resynchronized or synchronous path
Event detection only on the falling edge of the signal from the event generator
when using the resynchronized or synchronous path
Event detection on rising and falling edges of the signal from the event
generator when using the resynchronized or synchronous path
0x2
0x3
Bits 25:24 – PATH[1:0]ꢀPath Selection
These bits are used to choose the path to be used by the selected channel.
The path choice can be limited by the channel source.
PATH[1:0]
Name
Description
0x0
0x1
0x2
0x3
SYNCHRONOUS
RESYNCHRONIZED
ASYNCHRONOUS
Synchronous path
Resynchronized path
Asynchronous path
Reserved
Bits 22:16 – EVGEN[6:0]ꢀEvent Generator Selection
These bits are used to choose which event generator to connect to the selected channel.
Value
Event Generator
Description
0x00
0x01
NONE
RTC CMP0
No event generator selected
Compare 0 (mode 0 and 1) or Alarm 0 (mode 2)
DS40001882G-page 397
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
...........continued
Value
Event Generator
Description
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
RTC CMP1
RTC OVF
RTC PER0
RTC PER1
RTC PER2
RTC PER3
RTC PER4
RTC PER5
RTC PER6
Compare 1
Overflow
Period 0
Period 1
Period 2
Period 3
Period 4
Period 5
Period 6
Period 7
RTC PER7
EIC EXTINT0
EIC EXTINT1
EIC EXTINT2
EIC EXTINT3
EIC EXTINT4
EIC EXTINT5
EIC EXTINT6
EIC EXTINT7
EIC EXTINT8
EIC EXTINT9
EIC EXTINT10
EIC EXTINT11
EIC EXTINT12
EIC EXTINT13
EIC EXTINT14
EIC EXTINT15
Reserved
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
Reserved
DMAC CH0
DMAC CH1
DMAC CH2
DMAC CH3
TCC0 OVF
TCC0 TRG
TCC0 CNT
TCC0_MCX0
TCC0_MCX1
TCC0_MCX2
TCC0_MCX3
TCC1 OVF
TCC1 TRG
TCC1 CNT
TCC1_MCX0
TCC1_MCX1
TCC2 OVF
TCC2 TRG
TCC2 CNT
TCC2_MCX0
TCC2_MCX1
TC3 OVF
Channel 0
Channel 1
Channel 2
Channel 3
Overflow
Trig
Counter
Match/Capture 0
Match/Capture 1
Match/Capture 2
Match/Capture 3
Overflow
Trig
Counter
Match/Capture 0
Match/Capture 1
Overflow
Trig
Counter
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
TC3 MC0
TC3 MC1
TC4 OVF
DS40001882G-page 398
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
...........continued
Value
Event Generator
Description
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54-0x7F
TC4 MC0
TC4 MC1
TC5 OVF
TC5 MC0
TC5 MC1
TC6 OVF
TC6 MC0
TC6 MC1
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Overflow/Underflow
Match/Capture 0
Match/Capture 1
Result Ready
Window Monitor
Comparator 0
Comparator 1
Window 0
Data Buffer Empty
End of Conversion
Window Comparator
Comparator 2
Comparator 3
Window 1
TC7 OVF
TC7 MC0
TC7 MC1
ADC RESRDY
ADC WINMON
AC COMP0
AC COMP1
AC WIN0
DAC EMPTY
PTC EOC
PTC WCOMP
AC COMP2
AC COMP3
AC WIN1
TCC3 OVF
TCC3 TRG
TCC3 CNT
TCC3_MCX0
TCC3_MCX1
TCC3_MCX2
TCC3_MCX3
Reserved
Overflow
Trigger
Counter
Match/Capture 0
Match/Capture 1
Match/Capture 2
Match/Capture 3
Reserved
Bit 8 – SWEVTꢀSoftware Event
This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group.
This bit has the same behavior similar to an event.
This bit must be written together with CHANNEL.CHANNEL using a 16-bit write.
Writing a zero to this bit has no effect.
Writing a one to this bit will trigger a software event for the corresponding channel.
This bit will always return zero when read.
Bits 3:0 – CHANNEL[3:0]ꢀChannel Selection
These bits are used to select the channel to be set up or read from.
DS40001882G-page 399
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.3 User Multiplexer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
USER
0x08
0x0000
Property:ꢀ Write-Protected
Bit
15
7
14
6
13
5
12
11
10
9
8
CHANNEL[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
4
3
2
1
0
USER[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 12:8 – CHANNEL[4:0]ꢀChannel Event Selection
These bits are used to select the channel to connect to the event user.
Note that to select channel n, the value (n+1) must be written to the USER.CHANNEL bit group.
CHANNEL[4:0]
Channel Number
0x0
0x1-0xC
0xD-0xFF
No Channel Output Selected
Channel n-1 selected
Reserved
Bits 7:0 – USER[7:0]ꢀUser Multiplexer Selection
These bits select the event user to be configured with a channel, or the event user to read the channel value from.
Table 24-2.ꢀUser Multiplexer Selection
USER[7:0] User Multiplexer Description
Path Type
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
DMAC CH0
DMAC CH1
DMAC CH2
DMAC CH3
TCC0 EV0
TCC0 EV1
TCC0 MC0
TCC0 MC1
TCC0 MC2
TCC0 MC3
TCC1 EV0
TCC1 EV1
TCC1 MC0
TCC1 MC1
TCC2 EV0
TCC2 EV1
TCC2 MC0
TCC2 MC1
TC3
Channel 0
Channel 1
Channel 2
Channel 3
Resynchronized path only
Resynchronized path only
Resynchronized path only
Resynchronized path only
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Match/Capture 0
Match/Capture 1
Match/Capture 2
Match/Capture 3
Match/Capture 0
Match/Capture 1
Match/Capture 0
Match/Capture 1
TC4
TC5
TC6
TC7
ADC START
ADC start conversion Asynchronous path only
DS40001882G-page 400
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
...........continued
USER[7:0] User Multiplexer Description
Path Type
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
ADC SYNC
AC COMP0
AC COMP1
DAC START
PTC STCONV
AC COMP2
AC COMP3
TCC3 EV0
TCC3 EV1
TCC3 MC0
TCC3 MC1
TCC3 MC2
TCC3 MC3
Flush ADC
Start comparator 0
Start comparator 1
DAC start conversion Asynchronous path only
PTC start conversion Asynchronous path only
Start Comparator 2
Start Comparator 3
Match/Capture 1
Match/Capture 2
Match/Capture 0
Match/Capture 1
Match/Capture 2
Match/Capture 3
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous path only
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Asynchronous, synchronous and resynchronized paths
Reserved
0x25- 0x3F Reserved
DS40001882G-page 401
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.4 Channel Status
Name:ꢀ
CHSTATUS
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x0C
0x000F00FF
-
Bit
31
23
30
29
21
28
20
27
26
25
24
CHBUSY11
CHBUSY10
CHBUSY9
CHBUSY8
Access
Reset
R
0
R
0
R
0
R
0
Bit
22
19
18
17
16
USRRDY11
USRRDY10
USRRDY9
USRRDY8
Access
Reset
R
1
R
1
R
1
R
1
Bit
15
14
13
12
11
10
9
8
CHBUSY7
CHBUSY6
CHBUSY5
CHBUSY4
CHBUSY3
CHBUSY2
CHBUSY1
CHBUSY0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
USRRDY7
USRRDY6
USRRDY5
USRRDY4
USRRDY3
USRRDY2
USRRDY1
USRRDY0
Access
Reset
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
Bits 24, 25, 26, 27 – CHBUSYn ꢀChannel n Busy
This bit is cleared when channel n is idle
This bit is set if an event on channel n has not been handled by all event users connected to channel n.
Bits 16, 17, 18, 19 – USRRDYn ꢀChannel n User Ready
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events on channel n.
Bits 8, 9, 10, 11, 12, 13, 14, 15 – CHBUSYn ꢀChannel n Busy
This bit is cleared when channel n is idle
This bit is set if an event on channel n has not been handled by all event users connected to channel n.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – USRRDYn ꢀChannel n User Ready
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events on channel n.
DS40001882G-page 402
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.5 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x10
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
30
22
29
21
28
20
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
Access
Reset
Bit
19
OVR11
R/W
0
18
OVR10
R/W
0
17
OVR9
R/W
0
16
OVR8
R/W
0
Access
Reset
Bit
15
EVD7
R/W
0
14
EVD6
R/W
0
13
EVD5
R/W
0
12
EVD4
R/W
0
11
EVD3
R/W
0
10
EVD2
R/W
0
9
EVD1
R/W
0
8
EVD0
R/W
0
Access
Reset
Bit
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bits 24, 25, 26, 27 – EVDn ꢀChannel n Event Detection Interrupt Enable [n=11..8]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event
Detected Channel n interrupt.
Value
Description
0
1
The Event Detected Channel n interrupt is disabled.
The Event Detected Channel n interrupt is enabled.
Bits 16, 17, 18, 19 – OVRn ꢀChannel n Overrun Interrupt Enable [n=11..8]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n
interrupt.
Value
Description
0
1
The Overrun Channel n interrupt is disabled.
The Overrun Channel n interrupt is enabled.
Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn ꢀChannel n Event Detection Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event
Detected Channel n interrupt.
Value
Description
0
1
The Event Detected Channel n interrupt is disabled.
The Event Detected Channel n interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn ꢀChannel n Overrun Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n
interrupt.
DS40001882G-page 403
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
Value
Description
0
1
The Overrun Channel n interrupt is disabled.
The Overrun Channel n interrupt is enabled.
DS40001882G-page 404
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.6 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x14
0x00000000
Property:ꢀ Write-Protected
Bit
31
23
30
22
29
21
28
20
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
Access
Reset
Bit
19
OVR11
R/W
0
18
OVR10
R/W
0
17
OVR9
R/W
0
16
OVR8
R/W
0
Access
Reset
Bit
15
EVD7
R/W
0
14
EVD6
R/W
0
13
EVD5
R/W
0
12
EVD4
R/W
0
11
EVD3
R/W
0
10
EVD2
R/W
0
9
EVD1
R/W
0
8
EVD0
R/W
0
Access
Reset
Bit
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bits 24, 25, 26, 27 – EVDn ꢀChannel n Event Detection Interrupt Enable [n=11..8]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected
Channel n interrupt.
Value
Description
0
1
The Event Detected Channel n interrupt is disabled.
The Event Detected Channel n interrupt is enabled.
Bits 16, 17, 18, 19 – OVRnꢀChannel n Overrun Interrupt Enable [n=11..8]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n
interrupt.
Value
Description
0
1
The Overrun Channel n interrupt is disabled.
The Overrun Channel n interrupt is enabled.
Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn ꢀChannel n Event Detection Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected
Channel n interrupt.
Value
Description
0
1
The Event Detected Channel n interrupt is disabled.
The Event Detected Channel n interrupt is enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRnꢀChannel n Overrun Interrupt Enable [n=7..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n
interrupt.
DS40001882G-page 405
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
Value
Description
0
1
The Overrun Channel n interrupt is disabled.
The Overrun Channel n interrupt is enabled.
DS40001882G-page 406
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
EVSYS – Event System
24.8.7 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00000000
-
Property:ꢀ
Bit
31
23
30
22
29
21
28
20
27
EVD11
R/W
0
26
EVD10
R/W
0
25
EVD9
R/W
0
24
EVD8
R/W
0
Access
Reset
Bit
19
OVR11
R/W
0
18
OVR10
R/W
0
17
OVR9
R/W
0
16
OVR8
R/W
0
Access
Reset
Bit
15
EVD7
R/W
0
14
EVD6
R/W
0
13
EVD5
R/W
0
12
EVD4
R/W
0
11
EVD3
R/W
0
10
EVD2
R/W
0
9
EVD1
R/W
0
8
EVD0
R/W
0
Access
Reset
Bit
7
OVR7
R/W
0
6
OVR6
R/W
0
5
OVR5
R/W
0
4
OVR4
R/W
0
3
OVR3
R/W
0
2
OVR2
R/W
0
1
OVR1
R/W
0
0
OVR0
R/W
0
Access
Reset
Bits 24, 25, 26, 27 – EVDn ꢀChannel n Event Detection [n=11..8]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an
interrupt request will be generated if INTENCLR/SET.EVDn is one.
When the event channel path is asynchronous, the EVDn Interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
Bits 16, 17, 18, 19 – OVRn ꢀChannel n Overrun [n=11..8]
This flag is set on the next CLK_EVSYS cycle after an Overrun Channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRn is one.
When the event channel path is asynchronous, the OVRn Interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt flag.
Bits 8, 9, 10, 11, 12, 13, 14, 15 – EVDn ꢀChannel n Event Detection [n=7..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an
interrupt request will be generated if INTENCLR/SET.EVDn is one.
When the event channel path is asynchronous, the EVDn Interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – OVRn ꢀChannel n Overrun [n=7..0]
This flag is set on the next CLK_EVSYS cycle after an Overrun Channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRn is one.
When the event channel path is asynchronous, the OVRn Interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt flag.
DS40001882G-page 407
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
25.
SERCOM – Serial Communication Interface
25.1
Overview
There are up to six instances of the serial communication interface (SERCOM) peripheral.
A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM
is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.
The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching
functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to
be operated in all Sleep modes.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
25.2
Features
•
Interface for Configuring into one of the following (selected by CTRLA.MODE[2:0]):
– Inter-Integrated Circuit (I2C) two-wire serial interface
™
– System Management Bus (SMBus ) compatible
– Serial Peripheral Interface (SPI)
– Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Single Transmit Buffer and Double Receive Buffer
Baud-rate Generator
•
•
•
•
•
Address Match/mask Logic
Operational in all Sleep modes with an External Clock Source
Can be used with DMA
See the Related Links for full feature lists of the interface configurations.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
DS40001882G-page 408
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
25.3
Block Diagram
Figure 25-1.ꢀSERCOM Block Diagram
SERCOM
Register Interface
CONTROL/STATUS
BAUD/ADDR
TX/RX DATA
Mode Specific
Serial Engine
Mode n
Mode 1
Baud Rate
Generator
Transmitter
PAD[3:0]
Mode 0
Address
Match
Receiver
25.4
25.5
Signal Description
See the respective SERCOM mode chapters for details.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
25.5.1 I/O Lines
Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT).
The SERCOM has four internal pads, PAD[3:0], and the signals from I2C, SPI and USART are routed through these
SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes.
Refer to the mode specific chapters for details.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
23. PORT - I/O Pin Controller
26.3 Block Diagram
25.5.2 Power Management
The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts
can be configured to wake the device from Sleep modes.
Related Links
16. PM – Power Manager
DS40001882G-page 409
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
25.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to
Peripheral Clock Masking for details and default status of this clock.
The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core
clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a host. The slow clock
(GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details.
These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM.
The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity,
writing to certain registers will require synchronization between the clock domains. Refer to 25.6.8 Synchronization
for details.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
25.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the
SERCOM DMA requests are used.
Related Links
20. DMAC – Direct Memory Access Controller
25.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured before the
SERCOM interrupts are used.
Related Links
11.2 Nested Vector Interrupt Controller
25.5.6 Events
Not applicable.
25.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control
(DBGCTRL) register for details.
25.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
•
•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
25.5.9 Analog Connections
Not applicable.
DS40001882G-page 410
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
25.6
Functional Description
25.6.1 Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 25-2. Labels in capital letters are synchronous
to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the
GCLK_SERCOMx_CORE clock or an external clock.
Figure 25-2.ꢀSERCOM Serial Engine
Transmitter
Address Match
ADDR/ADDRMASK
BAUD
TX DATA
Selectable
Internal Clk
(GCLK)
Baud Rate Generator
1/- /2- /16
Ext Clk
TX Shift Register
RX Shift Register
Receiver
Equal
Status
STATUS
RX Buffer
RX DATA
Baud Rate Generator
The transmitter consists of a single write buffer and a shift register.
The receiver consists of a one-level (I2C), two-level (USART, SPI) receive buffer and a shift register.
The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.
Address matching logic is included for SPI and I2C operation.
25.6.2 Basic Operation
25.6.2.1 Initialization
The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register
(CTRLA.MODE) as shown in the table below.
Table 25-1.ꢀSERCOM Modes
CTRLA.MODE
Description
0x0
USART with external clock
USART with internal clock
SPI in client operation
SPI in host operation
I2C client operation
I2C host operation
0x1
0x2
0x3
0x4
0x5
0x6-0x7
Reserved
For further initialization information, see the respective SERCOM mode chapters:
DS40001882G-page 411
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
25.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
25.6.2.3 Clock Generation – Baud-Rate Generator
The baud-rate generator, as shown in Figure 25-3, generates internal clocks for asynchronous and synchronous
communication. The output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud
reference frequency (fref). The baud reference clock is the serial engine clock, and it can be internal or external.
For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1 (divide-
by-1) output is used while receiving.
For synchronous communication, the /2 (divide-by-2) output is used.
This functionality is automatically configured, depending on the selected operating mode.
Figure 25-3.ꢀBaud Rate Generator
Selectable
Internal Clk
(GCLK)
Baud Rate Generator
1
0
fref
Base
Period
/2
/8
Ext Clk
CTRLA.MODE[0]
/1
/2
/16
0
1
Tx Clk
1
0
CTRLA.MODE
1
0
Rx Clk
Clock
Recovery
Table 25-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating
mode.
For asynchronous operation, there is one mode: arithmetic mode, the BAUD register value is 16 bits (0 to 65,535).
For synchronous operation, the BAUD register value is 8 bits (0 to 255).
Table 25-2.ꢀBaud Rate Equations
Operating Mode
Condition
Baud Rate (Bits Per Second)
BAUD Register Value Calculation
Asynchronous
Arithmetic
f
f
f
ref
ref
BAUD
BAUD
65536
BAUD = 65536 ⋅ 1 − S ⋅
f
≤
≤
f
=
=
1 −
BAUD
BAUD
BAUD
BAUD
f
16
16
ref
Asynchronous
Fractional
f
f
f
ref
ref
ref
FP
f
f
BAUD =
−
FP
8
S
8
S ⋅ f
BAUD
S ⋅ BAUD +
DS40001882G-page 412
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
...........continued
Operating Mode
Condition
Baud Rate (Bits Per Second)
BAUD Register Value Calculation
Synchronous
f
f
f
ref
ref
ref
f
≤
f
=
BAUD =
− 1
BAUD
BAUD
2
2 ⋅ f
2 ⋅ BAUD + 1
BAUD
S - Number of samples per bit, which can be 16, 8, or 3.
The Asynchronous Fractional option is used for auto-baud detection.
The baud rate error is represented by the following formula:
ExpectedBaudRate
Error = 1 −
ActualBaudRate
25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD register
can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a single frame is more
granular. The BAUD register values that will affect the average frequency over a single frame lead to an integer
increase in the cycles per frame (CPF)
f
ref
CPF =
D + S
f
BAUD
where
•
•
D represent the data bits per frame
S represent the sum of start and first stop bits, if present.
Table 25-3 shows the BAUD register value versus baud frequency fBAUD at a serial engine frequency of 48MHz. This
assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits).
Table 25-3.ꢀBAUD Register Value vs. Baud Frequency
BAUD Register Value
0 – 406
Serial Engine CPF
fBAUD at 48MHz Serial Engine Frequency (fREF)
160
3MHz
407 – 808
809 – 1205
...
161
2.981MHz
2.963MHz
...
162
...
65206
31775
31871
31969
15.11kHz
15.06kHz
15.01kHz
65207
65208
25.6.3 Additional Features
25.6.3.1 Address Match and Mask
The SERCOM address match and mask feature is capable of matching either one address, two unique addresses, or
a range of addresses with a mask, based on the mode selected. The match uses seven or eight bits, depending on
the mode.
25.6.3.1.1 Address With Mask
An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the Address
Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not
included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will match a single unique address, while
writing ADDR.ADDRMASK to 'all ones' will result in all addresses being accepted.
DS40001882G-page 413
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
Figure 25-4.ꢀAddress With Mask
ADDR
Match
ADDRMASK
==
rx shift register
25.6.3.1.2 Two Unique Addresses
The two addresses written to ADDR and ADDRMASK will cause a match.
Figure 25-5.ꢀTwo Unique Addresses
ADDR
==
Match
rx shift register
==
ADDRMASK
25.6.3.1.3 Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match.
ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper
limit and ADDR.ADDRMASK acting as the lower limit.
Figure 25-6.ꢀAddress Range
ADDRMASK
rx shift register
ADDR
Match
==
25.6.4 DMA Operation
The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral. Refer to the
Functional Description sections of the respective SERCOM mode.
Related Links
26. SERCOM USART
27. SERCOM SPI – SERCOM Serial Peripheral Interface
28. SERCOM I2C – Inter-Integrated Circuit
25.6.5 Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
Each interrupt source has its own interrupt flag.
The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is
met.
Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SERCOM is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
DS40001882G-page 414
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM – Serial Communication Interface
The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG register to
determine which interrupt condition is present.
Note:ꢀ Interrupts must be globally enabled for interrupt requests.
Related Links
11.2 Nested Vector Interrupt Controller
25.6.6 Events
Not applicable.
25.6.7 Sleep Mode Operation
The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external
or generated by the internal baud-rate generator.
The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode
chapters for details.
25.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 415
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
26.
SERCOM USART
26.1
Overview
The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in
the Serial Communication Interface (SERCOM).
The USART uses the SERCOM transmitter and receiver, see 26.3 Block Diagram. Labels in uppercase letters are
synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to
run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The
write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive
buffer and a shift register. Status information of the received data is available for error checking. Data and clock
recovery units ensure robust synchronization and noise filtering during asynchronous data reception.
Related Links
25. SERCOM – Serial Communication Interface
26.2
USART Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex Operation
Asynchronous (with Clock Reconstruction) or Synchronous Operation
Internal or External Clock source for Asynchronous and Synchronous Operation
Baud-rate Generator
Supports Serial Frames with 5, 6, 7, 8 or 9 Data bits and 1 or 2 Stop bits
Odd or Even Parity Generation and Parity Check
Selectable LSB- or MSB-first Data Transfer
Buffer Overflow and Frame Error Detection
Noise Filtering, Including False Start bit Detection and Digital Low-pass Filter
Collision Detection
Can Operate in all Sleep modes
Operation at Speeds up to Half the System Clock for Internally Generated Clocks
Operation at Speeds up to the System Clock for Externally Generated Clocks
RTS and CTS Flow Control
IrDA Modulation and Demodulation up to 115.2kbps
Start-of-frame detection
Can work with DMA
Related Links
25.2 Features
DS40001882G-page 416
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
26.3
Block Diagram
Figure 26-1.ꢀUSART Block Diagram
BAUD
TX DATA
GCLK
(internal)
Baud Rate Generator
/1 - /2 - /16
CTRLA.MODE
TX Shift Register
RX Shift Register
TxD
RxD
XCK
CTRLA.MODE
Status
RX Buffer
RX DATA
STATUS
26.4
Signal Description
Table 26-1.ꢀSERCOM USART Signals
Signal Name
Type
Description
General SERCOM pins
PAD[3:0]
Digital I/O
One signal can be mapped to one of several pins.
Related Links
7. I/O Multiplexing and Considerations
26.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 I/O Lines
Using the USART’s I/O lines requires the I/O pins to be configured using the I/O Pin Controller (PORT).
When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O pins according
to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output pins. PORT Control
bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/disabling of a pull
down only (it is not possible to enable/disable a pull up). If the receiver or transmitter is disabled, these pins can be
used for other purposes.
The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the CTRLA
register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in the
following table.
Table 26-2.ꢀUSART Pin Configuration
Pin
Pin Configuration
Output
TxD
RxD
Input
DS40001882G-page 417
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
...........continued
Pin
Pin Configuration
XCK
Output or input
Related Links
23. PORT - I/O Pin Controller
26.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes.
Related Links
16. PM – Power Manager
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to
Peripheral Clock Masking for details and default status of this clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be
configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to GCLK - Generic
Clock Controller for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain registers
will require synchronization to the clock domains. Refer to Synchronization for further details.
Related Links
26.6.6 Synchronization
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
26.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this
peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.
Related Links
20. DMAC – Direct Memory Access Controller
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
26.5.6 Events
Not applicable.
26.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control
(DBGCTRL) register for details.
Related Links
26.8.11 DBGCTRL
26.5.8 Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
DS40001882G-page 418
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
PAC Write-Protection is not available for the following registers:
•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register
description.
Write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
26.5.9 Analog Connections
Not applicable.
26.6
Functional Description
26.6.1 Principle of Operation
The USART uses the following lines for data transfer:
RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation
USART data transfer is frame based. A serial frame consists of:
•
•
•
•
•
•
•
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits
A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the
data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can follow immediately,
or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats.
Brackets denote optional bits.
Figure 26-2.ꢀFrame Formats
Frame
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
[St/IDL]
St
Start bit. Signal is always low.
n, [n]
[P]
Data bits. 0 to [5..9]
Parity bit. Either odd or even.
Sp, [Sp]
Stop bit. Signal is always high.
IDLE No frame is transferred on the communication line. Signal is always high in this state.
DS40001882G-page 419
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
26.6.2 Basic Operation
26.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the USART is disabled
(CTRL.ENABLE=0):
•
•
•
Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
Baud register (BAUD)
When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be
discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the USART is enabled, it must be configured by these steps:
1. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register
(CTRLA.MODE).
2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication
Mode bit in the CTRLA register (CTRLA.CMODE).
3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO).
4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register
(CTRLA.TXPO).
5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size.
6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data
transmission.
7. To use parity mode:
7.1.
7.2.
Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM).
Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity.
8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE).
9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the
CTRLB register (CTRLB.RXEN and CTRLB.TXEN).
26.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
26.6.2.3 Clock Generation and Selection
For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated
internally by the SERCOM baud-rate generator or supplied externally through the XCK line.
The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A register
(CTRLA.CMODE), the asynchronous mode is selected by writing a zero to CTRLA.CMODE.
The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A register
(CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE.
The SERCOM baud-rate generator is configured as in the figure below.
In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used.
In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock Generation
– Baud-Rate Generator for details on configuring the baud rate.
DS40001882G-page 420
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
Figure 26-3.ꢀClock Generation
XCKInternal Clk
Baud Rate Generator
(GCLK)
1
0
Base
Period
/2
/8
/1
/2
/8
CTRLA.MODE[0]
0
1
Tx Clk
CTRLA.CMODE
1
0
XCK
1
0
Rx Clk
Related Links
25.6.2.3 Clock Generation – Baud-Rate Generator
25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
26.6.2.3.1 Synchronous Clock Operation
In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either
as input or output. The dependency between clock edges, data sampling, and data change is the same for internal
and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the
TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD
sampling, and which is used for TxD change:
When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling edge of
XCK.
When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of
XCK.
Figure 26-4.ꢀSynchronous Mode XCK Timing
Change
XCK
CTRLA.CPOL=1
RxD / TxD
Sample
Sample
Change
XCK
CTRLA.CPOL=0
RxD / TxD
When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock.
This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the
system frequency.
26.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O
address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading
the DATA register will return the contents of the RxDATA register.
DS40001882G-page 421
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM USART
26.6.2.5 Data Transmission
Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be
moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is
loaded with data, the data frame will be transmitted.
When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the
Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the
optional interrupt will be generated.
The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the
register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set.
26.6.2.5.1 Disabling the Transmitter
The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN).
Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is
no data in the transmit shift register and TxDATA to transmit.
26.6.2.6 Data Reception
The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according
to the baud rate or XCK clock, and shifted into the receive Shift register until the first Stop bit of a frame is received.
The second Stop bit will be ignored by the receiver.
When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents
of the Shift register will be moved into the two-level receive buffer. Then, the Receive Complete Interrupt flag in the
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt can be generated.
The received data can be read from the DATA register when the Receive Complete Interrupt flag is set.
26.6.2.6.1 Disabling the Receiver
Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the
two-level receive buffer, and data from ongoing receptions will be lost.
26.6.2.6.2 Error Bits
The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow
(BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared
by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in
the Control A register (CTRLA.IBON):
When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the
receive FIFO by reading RxDATA, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared.
When CTRLA.IBON=0, the Buffer Overflow condition travels with data through the receive FIFO. After the received
data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC.
26.6.2.6.3 Asynchronous Data Reception
The USART includes a clock recovery and data recovery unit for handling asynchronous data reception.
The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the internally
generated baud-rate clock.
The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise
immunity of the receiver.
26.6.2.6.4 Asynchronous Operational Range
The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate clock, the
rate of the incoming frames, and the frame size (in number of bits). In addition, the operational range of the receiver
is depending on the difference between the received bit rate and the internally generated baud rate. If the baud rate
of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not
be able to synchronize the frames to the start bit.
There are two possible sources for a mismatch in baud rate: First, the reference clock will always have some minor
instability. Second, the baud-rate generator cannot always do an exact division of the reference clock frequency to
DS40001882G-page 422
Complete Datasheet
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SAM D21/DA1 Family
SERCOM USART
get the baud rate desired. In this case, the BAUD register value should be set to give the lowest possible error. Refer
to Clock Generation – Baud-Rate Generator for details.
Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below.
Table 26-3.ꢀAsynchronous Receiver Error for 16-fold Oversampling
D
RSLOW [%] RFAST [%] Max. total error [%]
Recommended max. Rx error [%]
(Data bits+Parity)
5
94.12
94.92
95.52
96.00
96.39
96.70
107.69
106.67
105.88
105.26
104.76
104.35
+5.88/-7.69
+5.08/-6.67
+4.48/-5.88
+4.00/-5.26
+3.61/-4.76
+3.30/-4.35
±2.5
±2.0
±2.0
±2.0
±1.5
±1.5
6
7
8
9
10
The following equations calculate the ratio of the incoming data rate and internal receiver baud rate:
D + 1 S
S − 1 + D ⋅ S + S
D + 2 S
R
=
,
R
=
SLOW
FAST
D + 1 S + S
F
M
•
•
•
•
•
•
RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
D is the sum of character size and parity size (D = 5 to 10 bits)
S is the number of samples per bit (S = 16, 8 or 3)
SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0.
The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total
error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure:
Figure 26-5.ꢀUSART Rx Error Calculation
SERCOM Receiver error acceptance
+
from RSLOW and RFAST formulas
Baud Generator offset error
Clock source error
depends on BAUD register value
Error Max (%)
Baud Rate
Recommended max. Rx Error (%)
Error Min (%)
The recommendation values in the table above accommodate errors of the clock source and the baud generator. The
following figure gives an example for a baud rate of 3Mbps:
DS40001882G-page 423
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SAM D21/DA1 Family
SERCOM USART
Figure 26-6.ꢀUSART Rx Error Calculation Example
SERCOM Receiver error acceptance
sampling = x16
data bits = 10
parity = 0
start bit = stop bit = 1
+
No baud generator offset error
Accepted
Receiver Error
+
Fbaud(3Mbps) = 48MHz *1(BAUD=0) /16
DFLL source at 3MHz
Transmitter Error*
+/-0.3%
Error Max 3.3%
Error Max 3.3%
Error Max 3.0%
Baud Rate 3Mbps
Error Min -4.05%
Error Min -4.35%
Error Min -4.35%
Recommended
max. Rx Error +/-1.5%
(example)
security margin
*Transmitter Error depends on the external transmitter used in the application.
It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example).
Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error.
Related Links
25.6.2.3 Clock Generation – Baud-Rate Generator
25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
26.6.3 Additional Features
26.6.3.1 Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A
register (CTRLA.FORM).
If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd
number of bits that are '1', making the total number of '1' even.
If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even
number of bits that are '0', making the total number of '1' odd.
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in
the Status register (STATUS.PERR) is set.
26.6.3.2 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the
RTS and CTS pins with the remote device, as shown in the figure below.
Figure 26-7.ꢀConnection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
CTS
RTS
TXD
RTS
CTS
Hardware handshaking is only available in the following configuration:
•
•
•
USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2).
When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies
the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to
CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be
set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full.
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SAM D21/DA1 Family
SERCOM USART
Figure 26-8.ꢀReceiver Behavior when Operating with Hardware Handshaking
RXD
RXEN
RTS
Rx FIFO Full
The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if
STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting.
Figure 26-9.ꢀTransmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
26.6.3.3 IrDA Modulation and Demodulation
Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation
work in the following configuration:
•
•
•
IrDA encoding enabled (CTRLB.ENC=1),
Asynchronous mode (CTRLA.CMODE=0),
and 16x sample rate (CTRLA.SAMPR[0]=0).
During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate period, as
illustrated in the figure below.
Figure 26-10.ꢀIrDA Transmit Encoding
1 baud clock
TXD
IrDA encoded TXD
3/16 baud clock
The reception decoder has two main functions.
The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start
of each zero pulse.
The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set by
configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is
transferred to the receiver.
Note:ꢀ Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted
as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit.
Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates
that the pulse width should be at least 20 SE clock cycles. When using BAUD=0xE666 or 160 SE
cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case
the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is
rejected since it does not meet the minimum requirement of 2/16 baud clock.
Figure 26-11.ꢀIrDA Receive Decoding
1.5
2
2.5
0
0.5
1
Baud clock
IrDA encoded RXD
RXD
20 SE clock cycles
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SAM D21/DA1 Family
SERCOM USART
26.6.3.4 Break Character Detection and Auto-Baud
Break character detection and auto-baud are available in this configuration:
•
•
•
Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0),
and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any
time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a
Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects
the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized.
If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with
the Error interrupt flag (INTFLAG.ERROR), and the baud rate is unchanged.
After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then
incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this
moment, the 13 most significant bits of the counter (value divided by 8) give the new clock divider (BAUD.BAUD),
and the 3 least significant bits of this value (the remainder) give the new Fractional Part (BAUD.FP).
When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are
updated after a synchronization delay. After the Break and Sync Fields are received, multiple characters of data can
be received.
26.6.3.5 Collision Detection
When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can
be detected after selecting the Collision Detection Enable bit in the CTRLB register (CTRLB.COLDEN=1). To detect
collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1).
Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as
shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on
RxD without triggering a collision.
Figure 26-12.ꢀCollision Checking
8-bit character, single stop bit
TXD
RXD
Collision checked
The next figure shows the conditions for a collision detection. In this case, the start bit and the first data bit
are received with the same value as transmitted. The second received data bit is found to be different than the
transmitted bit at the detection point, which indicates a collision.
Figure 26-13.ꢀCollision Detected
Collision checked and ok
Tri-state
TXD
RXD
TXEN
Collision detected
When a collision is detected, the USART follows this sequence:
1. Abort the current transfer.
2. Flush the transmit buffer.
3. Disable transmitter (CTRLB.TXEN=0)
– This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB)
will be set until this is complete.
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– After disabling, the TxD pin will be tri-stated.
4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR).
5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring that the
CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
26.6.3.6 Loop-Back Mode
For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO)
to use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available
externally.
26.6.3.7 Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the
internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in
relation to the fast startup internal oscillator start-up time. Refer to Electrical Characteristics for details. The start-up
time of this oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing ‘1’
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE).
If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start
interrupt is generated immediately when a start is detected.
When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal
Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the
Receive Complete interrupt is generated.
Related Links
37. Electrical Characteristics at 85℃
26.6.3.8 Sample Adjustment
In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on
majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control
A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples
3-4-5 are used for 8x oversampling.
26.6.4 DMA, Interrupts and Events
Table 26-4.ꢀModule Request for SERCOM USART
Condition
Request
DMA
Interrupt
Event
Data Register Empty (DRE)
Receive Complete (RXC)
Yes
Yes
NA
(request cleared when data is written)
Yes
Yes
(request cleared when data is read)
Transmit Complete (TXC)
Receive Start (RXS)
NA
NA
NA
NA
NA
Yes
Yes
Yes
Yes
Yes
Clear to Send Input Change (CTSIC)
Receive Break (RXBRK)
Error (ERROR)
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26.6.4.1 DMA Operation
The USART generates the following DMA requests:
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
•
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
26.6.4.2 Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device
from any sleep mode:
•
•
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
Received Break (RXBRK)
Error (ERROR)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing
'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
26.6.4.3 Events
Not applicable.
26.6.5 Sleep Mode Operation
The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A register
(CTRLA.RUNSTDBY):
•
•
•
•
Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep modes. Any
interrupt can wake up the device.
External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s) can wake
up the device.
Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer was
completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing transfer was
completed. All reception will be dropped.
26.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
DS40001882G-page 428
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SAM D21/DA1 Family
SERCOM USART
•
Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note:ꢀ CTRLB.RXEN is write-synchronized somewhat differently. See also 26.8.2 CTRLB for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 429
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SAM D21/DA1 Family
SERCOM USART
26.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
IBON
15:8
SAMPR[2:0]
0x00
0x04
CTRLA
23:16
31:24
7:0
SAMPA[1:0]
RXPO[1:0]
TXPO[1:0]
DORD
CPOL
CMODE
FORM[3:0]
SBMODE
CHSIZE[2:0]
SFDE
15:8
PMODE
ENC
COLDEN
TXEN
CTRLB
23:16
31:24
RXEN
0x08
...
Reserved
0x0B
7:0
15:8
7:0
BAUD[7:0]
0x0C
BAUD
RXPL
BAUD[15:8]
RXPL[7:0]
0x0E
0x0F
...
Reserved
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
7:0
7:0
7:0
ERROR
ERROR
ERROR
RXBRK
RXBRK
RXBRK
COLL
CTSIC
RXS
RXS
RXS
CTS
RXC
RXC
TXC
TXC
DRE
DRE
CTSIC
CTSIC
ISF
RXC
TXC
DRE
7:0
15:8
7:0
TXE
BUFOVF
CTRLB
FERR
ENABLE
PERR
SWRST
0x1A
STATUS
15:8
23:16
31:24
0x1C
SYNCBUSY
0x20
...
Reserved
DATA
0x27
7:0
DATA[7:0]
0x28
15:8
DATA[8]
0x2A
...
Reserved
0x2F
0x30
DBGCTRL
7:0
DBGSTOP
26.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
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SERCOM USART
26.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
DORD
R/W
0
29
CPOL
R/W
0
28
CMODE
R/W
27
26
25
24
FORM[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
23
22
21
20
19
18
10
2
17
16
SAMPA[1:0]
RXPO[1:0]
TXPO[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
SAMPR[2:0]
R/W
13
12
11
9
8
IBON
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bit
7
6
5
4
3
MODE[2:0]
R/W
1
0
SWRST
R/W
0
RUNSTDBY
ENABLE
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
Bit 30 – DORDꢀData Order
This bit selects the data order when a character is shifted out from the Data register.
This bit is not synchronized.
Value
Description
0
1
MSB is transmitted first.
LSB is transmitted first.
Bit 29 – CPOLꢀClock Polarity
This bit selects the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
CPOL
TxD Change
RxD Sample
0x0
0x1
Rising XCK edge
Falling XCK edge
Falling XCK edge
Rising XCK edge
Bit 28 – CMODEꢀCommunication Mode
This bit selects asynchronous or synchronous communication.
This bit is not synchronized.
Value
Description
0
1
Asynchronous communication.
Synchronous communication.
Bits 27:24 – FORM[3:0]ꢀFrame Format
These bits define the frame format.
These bits are not synchronized.
FORM[3:0]
Description
0x0
0x1
USART frame
USART frame with parity
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SERCOM USART
...........continued
FORM[3:0]
Description
0x2-0x3
0x4
0x5
Reserved
Auto-baud - break detection and auto-baud.
Auto-baud - break detection and auto-baud with parity
Reserved
0x6-0xF
Bits 23:22 – SAMPA[1:0]ꢀSample Adjustment
These bits define the sample adjustment.
These bits are not synchronized.
SAMPA[1:0] 16x Over-sampling (CTRLA.SAMPR=0 or 1)
8x Over-sampling (CTRLA.SAMPR=2 or 3)
0x0
0x1
0x2
0x3
7-8-9
3-4-5
4-5-6
5-6-7
6-7-8
9-10-11
11-12-13
13-14-15
Bits 21:20 – RXPO[1:0]ꢀReceive Data Pinout
These bits define the receive data (RxD) pin configuration.
These bits are not synchronized.
RXPO[1:0]
Name
Description
0x0
0x1
0x2
0x3
PAD[0]
PAD[1]
PAD[2]
PAD[3]
SERCOM PAD[0] is used for data reception
SERCOM PAD[1] is used for data reception
SERCOM PAD[2] is used for data reception
SERCOM PAD[3] is used for data reception
Bits 17:16 – TXPO[1:0]ꢀTransmit Data Pinout
These bits define the transmit data (TxD) and XCK pin configurations.
This bit is not synchronized.
TXPO TxD Pin Location
XCK Pin Location (When Applicable)
RTS
CTS
0x0
0x1
0x2
0x3
SERCOM PAD[0]
SERCOM PAD[2]
SERCOM PAD[0]
Reserved
SERCOM PAD[1]
SERCOM PAD[3]
N/A
N/A
N/A
N/A
N/A
SERCOM PAD[2]
SERCOM PAD[3]
Bits 15:13 – SAMPR[2:0]ꢀSample Rate
These bits select the sample rate.
These bits are not synchronized.
SAMPR[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5-0x7
16x over-sampling using arithmetic baud rate generation.
16x over-sampling using fractional baud rate generation.
8x over-sampling using arithmetic baud rate generation.
8x over-sampling using fractional baud rate generation.
3x over-sampling using arithmetic baud rate generation.
Reserved
Bit 8 – IBONꢀImmediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
Value
Description
0
1
STATUS.BUFOVF is asserted when it occurs in the data stream.
STATUS.BUFOVF is asserted immediately upon buffer overflow.
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SAM D21/DA1 Family
SERCOM USART
Bit 7 – RUNSTDBYꢀRun In Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
RUNSTDBY External Clock
Internal Clock
0x0
External clock is disconnected when Generic clock is disabled when ongoing transfer is finished.
ongoing transfer is finished. All
reception is dropped.
The device will not wake up on either Receive Start or Transfer
Complete interrupt unless the appropriate ONDEMAND bits are
set in the clocking chain.
0x1
Wake on Receive Start or Receive
Complete interrupt.
Generic clock is enabled in all sleep modes. Any interrupt can
wake up the device.
Bits 4:2 – MODE[2:0]ꢀOperating Mode
These bits select the USART serial communication interface of the SERCOM.
These bits are not synchronized.
Value
0x0
0x1
Description
USART with external clock
USART with internal clock
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation
is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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SERCOM USART
26.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
23
15
7
30
22
14
29
28
20
12
4
27
19
11
3
26
18
25
24
Access
Reset
Bit
21
17
RXEN
R/W
0
16
TXEN
R/W
0
Access
Reset
Bit
13
PMODE
R/W
10
ENC
R/W
0
9
SFDE
R/W
0
8
COLDEN
R/W
Access
Reset
0
0
Bit
6
SBMODE
R/W
5
2
1
0
CHSIZE[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit 17 – RXENꢀReceiver Enable
Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the
FERR, PERR and BUFOVF bits in the STATUS register.
Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART
is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the
receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
1
The receiver is disabled or being enabled.
The receiver is enabled or will be enabled when the USART is enabled.
Bit 16 – TXENꢀTransmitter Enable
Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until
ongoing and pending transmissions are completed.
Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is
enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is
enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'.
Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the
transmitter is enabled, and CTRLB.TXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
1
The transmitter is disabled or being enabled.
The transmitter is enabled or will be enabled when the USART is enabled.
Bit 13 – PMODEꢀParity Mode
This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will automatically
generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value
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SERCOM USART
for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will
be set.
This bit is not synchronized.
Value
0
1
Description
Even parity.
Odd parity.
Bit 10 – ENCꢀEncoding Format
This bit selects the data encoding format.
This bit is not synchronized.
Value
Description
0
1
Data is not encoded.
Data is IrDA encoded.
Bit 9 – SFDEꢀStart of Frame Detection Enable
This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD
line.
This bit is not synchronized.
SFDE INTENSET.RXS INTENSET.RXC Description
0
1
1
X
0
0
X
0
1
Start-of-frame detection disabled.
Reserved
Start-of-frame detection enabled. RXC wakes up the device from all
sleep modes.
1
1
1
1
0
1
Start-of-frame detection enabled. RXS wakes up the device from all
sleep modes.
Start-of-frame detection enabled. Both RXC and RXS wake up the
device from all sleep modes.
Bit 8 – COLDENꢀCollision Detection Enable
This bit enables collision detection.
This bit is not synchronized.
Value
Description
0
1
Collision detection is not enabled.
Collision detection is enabled.
Bit 6 – SBMODEꢀStop Bit Mode
This bit selects the number of stop bits transmitted.
This bit is not synchronized.
Value
0
1
Description
One stop bit.
Two stop bits.
Bits 2:0 – CHSIZE[2:0]ꢀCharacter Size
These bits select the number of bits in a character.
These bits are not synchronized.
CHSIZE[2:0]
Description
0x0
8 bits
0x1
9 bits
0x2-0x4
0x5
Reserved
5 bits
0x6
6 bits
0x7
7 bits
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SERCOM USART
26.8.3 Baud
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BAUD
0x0C
0x0000
Property:ꢀ Enable-Protected, PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
BAUD[15:8]
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BAUD[15:0]ꢀBaud Value
Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0):
These bits control the clock generation, as described in the SERCOM Baud Rate section.
If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0] Fractional
Part:
•
Bits 15:13 - FP[2:0]: Fractional Part
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator
section.
•
Bits 12:0 - BAUD[12:0]: Baud Value
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator
section.
Related Links
25.6.2.3 Clock Generation – Baud-Rate Generator
25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection
DS40001882G-page 436
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SERCOM USART
26.8.4 Receive Pulse Length Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
RXPL
0x0E
0x00
Property:ꢀ Enable-Protected, PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
RXPL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – RXPL[7:0]ꢀReceive Pulse Length
When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is
required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period SE
.
per
PULSE ≥ RXPL + 2 ⋅ SE
per
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26.8.5 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
2
1
0
RXS
R/W
0
RXC
R/W
0
TXC
R/W
0
DRE
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 5 – RXBRKꢀReceive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt.
Value
Description
0
1
Receive Break interrupt is disabled.
Receive Break interrupt is enabled.
Bit 4 – CTSICꢀClear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send
Input Change interrupt.
Value
Description
0
1
Clear To Send Input Change interrupt is disabled.
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXSꢀReceive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
Value
Description
0
1
Receive Start interrupt is disabled.
Receive Start interrupt is enabled.
Bit 2 – RXCꢀReceive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
Value
Description
0
1
Receive Complete interrupt is disabled.
Receive Complete interrupt is enabled.
Bit 1 – TXCꢀTransmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
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SERCOM USART
Value
Description
0
1
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DREꢀData Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty
interrupt.
Value
Description
0
1
Data Register Empty interrupt is disabled.
Data Register Empty interrupt is enabled.
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26.8.6 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x16
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
2
1
0
RXS
R/W
0
RXC
R/W
0
TXC
R/W
0
DRE
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 5 – RXBRKꢀReceive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt.
Value
Description
0
1
Receive Break interrupt is disabled.
Receive Break interrupt is enabled.
Bit 4 – CTSICꢀClear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send
Input Change interrupt.
Value
Description
0
1
Clear To Send Input Change interrupt is disabled.
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXSꢀReceive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt.
Value
Description
0
1
Receive Start interrupt is disabled.
Receive Start interrupt is enabled.
Bit 2 – RXCꢀReceive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
Value
Description
0
1
Receive Complete interrupt is disabled.
Receive Complete interrupt is enabled.
Bit 1 – TXCꢀTransmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
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Value
Description
0
1
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DREꢀData Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty
interrupt.
Value
Description
0
1
Data Register Empty interrupt is disabled.
Data Register Empty interrupt is enabled.
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SERCOM USART
26.8.7 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00
-
Property:ꢀ
Bit
7
ERROR
R/W
0
6
5
RXBRK
R/W
0
4
CTSIC
R/W
0
3
2
RXC
R
1
0
DRE
R
RXS
R/W
0
TXC
R/W
0
Access
Reset
0
0
Bit 7 – ERRORꢀError
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 5 – RXBRKꢀReceive Break
This flag is cleared by writing '1' to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 4 – CTSICꢀClear to Send Input Change
This flag is cleared by writing a '1' to it.
This flag is set when a change is detected on the CTS pin.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – RXSꢀReceive Start
This flag is cleared by writing '1' to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is '1').
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start interrupt flag.
Bit 2 – RXCꢀReceive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXCꢀTransmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in
DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DREꢀData Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
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26.8.8 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x1A
0x0000
-
Property:ꢀ
Bit
15
7
14
13
12
11
10
9
8
Access
Reset
Bit
6
5
COLL
R/W
0
4
ISF
R/W
0
3
CTS
R
2
BUFOVF
R/W
1
FERR
R/W
0
0
PERR
R/W
0
TXE
R/W
0
Access
Reset
0
0
Bit 6 – TXEꢀTransmitter Empty
This bit will always read back as zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 5 – COLLꢀCollision Detected
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 4 – ISFꢀInconsistent Sync Field
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is
received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 3 – CTSꢀClear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 2 – BUFOVFꢀBuffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full,
there is a new character waiting in the receive shift register and a new start bit is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 1 – FERRꢀFrame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
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Bit 0 – PERRꢀParity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5) and a parity error is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
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SERCOM USART
26.8.9 Synchronization Busy
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SYNCBUSY
0x1C
0x00000000
-
Property:ꢀ
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
1
0
CTRLB
ENABLE
SWRST
Access
Reset
R
0
R
0
R
0
Bit 2 – CTRLBꢀCTRLB Synchronization Busy
Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the
SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is
asserted, an APB error will be generated.
Value
Description
0
1
CTRLB synchronization is not busy.
CTRLB synchronization is busy.
Bit 1 – ENABLEꢀSERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
1
Enable synchronization is not busy.
Enable synchronization is busy.
Bit 0 – SWRSTꢀSoftware Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
1
SWRST synchronization is not busy.
SWRST synchronization is busy.
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SERCOM USART
26.8.10 Data
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATA
0x28
0x0000
-
Property:ꢀ
Bit
15
7
14
13
5
12
4
11
3
10
2
9
1
8
DATA[8]
R/W
0
Access
Reset
Bit
6
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 8:0 – DATA[8:0]ꢀData
Reading these bits will return the contents of the Receive Data register. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status
bits in STATUS should be read before reading the DATA value in order to get any corresponding error.
Writing these bits will write the Transmit Data register. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
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26.8.11 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x30
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
R/W
Access
Reset
0
Bit 0 – DBGSTOPꢀDebug Stop Mode
This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger.
Value
Description
0
1
The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
The baud-rate generator is halted when the CPU is halted by an external debugger.
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SERCOM SPI – SERCOM Serial Peripheral Interface
27.
SERCOM SPI – SERCOM Serial Peripheral Interface
27.1
Overview
The Serial Peripheral Interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM).
The SPI uses the SERCOM transmitter and receiver configured as shown in 27.3 Block Diagram. Each side, host
and client, depicts a separate SPI containing a Shift register, a transmit buffer and a two-level receive buffer. In
addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address
match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while
labels in lowercase letters are synchronous to the SCK clock.
Related Links
25. SERCOM – Serial Communication Interface
27.2
Features
SERCOM SPI includes the following features:
•
•
•
•
•
•
•
Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
One-level transmit buffer, two-level receive buffer
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Host operation:
(1)
– Serial clock speed, fSCK=1/tSCK
– 8-bit clock generator
– Hardware controlled SS
Client Operation:
•
(1)
– Serial clock speed, fSCK=1/tSSCK
– Optional 8-bit address match operation
– Operation in all sleep modes
– Wake on SS transition
1. For tSCK and tSSCK values, refer to SPI Timing Characteristics.
Related Links
37.16.2 SERCOM in SPI Mode Timing
25. SERCOM – Serial Communication Interface
25.2 Features
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SERCOM SPI – SERCOM Serial Peripheral Interface
27.3
Block Diagram
Figure 27-1.ꢀFull-Duplex SPI Host Client Interconnection
Host
Client
BAUD
Tx DATA
Tx DATA
ADDR/ADDRMASK
SCK
SS
MISO
MOSI
baud rate generator
shift register
shift register
rx buffer
rx buffer
==
Address Match
Rx DATA
Rx DATA
27.4
Signal Description
Table 27-1.ꢀSERCOM SPI Signals
Signal Name
Type
Digital I/O
Description
General SERCOM pins
PAD[3:0]
One signal can be mapped to one of several pins.
Related Links
7. I/O Multiplexing and Considerations
27.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1 I/O Lines
In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT).
When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O
pins according to the table below. PORT Control bit PINCFGn.DRVSTR is still effective for the SERCOM output
pins. PORT Control bit PINCFGn.PULLEN is still effective on the SERCOM input pins, but is limited to the enabling/
disabling of a pull down only (it is not possible to enable/disable a pull up). If the receiver is disabled, the data input
pin can be used for other purposes. In Host mode, the SPI Select line (SS) is hardware controlled when the Host SPI
Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'.
Table 27-2.ꢀSPI Pin Configuration
Pin
Host SPI
Client SPI
Input
MOSI
MISO
SCK
SS
Output
Input
Output
Input
Output
Output (CTRLB.MSSEN=1)
Input
The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register
(CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above.
Related Links
23. PORT - I/O Pin Controller
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes.
Related Links
16. PM – Power Manager
27.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to
Peripheral Clock Masking for details and default status of this clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled
in the Generic Clock Controller before using the SPI.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain registers will
require synchronization to the clock domains.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
27.6.6 Synchronization
27.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this
peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.
Related Links
20. DMAC – Direct Memory Access Controller
27.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
27.5.6 Events
Not applicable.
27.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control
(DBGCTRL) register for details.
27.5.8 Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register
description.
Write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
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SERCOM SPI – SERCOM Serial Peripheral Interface
27.5.9 Analog Connections
Not applicable.
27.6
Functional Description
27.6.1 Principle of Operation
The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device
and peripheral devices.
The SPI can operate as host or client. As host, the SPI initiates and controls all data transactions. The SPI is single
buffered for transmitting and double buffered for receiving.
When transmitting data, the Data register can be loaded with the next character to be transmitted during the current
transmission.
When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character.
The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or more
characters. The character size is configurable, and can be either 8 or 9 bits.
Figure 27-2.ꢀSPI Transaction Format
Transaction
Character
MOSI/MISO
SS
Character 0
Character 1
Character 2
The SPI host must pull the SPI select line (SS) of the desired client low to initiate a transaction if multiple clients are
connected to the bus. The SPI select line can be wired low if there is only one SPI client on the bus. The host and
client prepare data to send via their respective Shift registers, and the host generates the serial clock on the SCK
line.
Data is always shifted from host to client on the Host Output Client Input line (MOSI); data is shifted from client to
host on the Host Input Client Output line (MISO).
Each time character is shifted out from the host, a character will be shifted out from the client simultaneously. To
signal the end of a transaction, the host will pull the SS line high.
27.6.2 Basic Operation
27.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is disabled
(CTRL.ENABLE=0):
•
•
•
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Baud register (BAUD)
Address register (ADDR)
When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be discarded.
When the SPI is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the Enable-Protection property in the register description.
Initialize the SPI by following these steps:
1. Select SPI mode in host/client operation in the Operating Mode bit group in the CTRLA register
(CTRLA.MODE= 0x2 or 0x3 ).
2. Select Transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL
and CTRLA.CPHA) if desired.
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SERCOM SPI – SERCOM Serial Peripheral Interface
3. Select the Frame Format value in the CTRLA register (CTRLA.FORM).
4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver.
5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the
transmitter.
6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE).
7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction.
8. If the SPI is used in Host mode:
8.1.
8.2.
Select the desired baud rate by writing to the Baud register (BAUD).
If Hardware SS control is required, write '1' to the Host SPI Select Enable bit in CTRLB register
(CTRLB.MSSEN).
9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).
27.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
27.6.2.3 Clock Generation
In the SPI host operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the SERCOM Baud
Rate Generator (BRG).
In SPI mode, the BRG is set to Synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK
and clocking the Shift register. Refer to Clock Generation – Baud-Rate Generator for more details.
In SPI client operation (CTRLA.MODE is 0x2), the clock is provided by an external host on the SCK pin. This clock is
used to clock the SPI Shift register.
Related Links
25.6.2.3 Clock Generation – Baud-Rate Generator
27.6.2.4 Data Register
The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address,
referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data register. Reading the
DATA register will return the contents of the Receive Data register.
27.6.2.5 SPI Transfer Modes
There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer modes are
shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure).
SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed
by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite
edges of the SCK signal. This ensures sufficient time for the data signals to stabilize.
Table 27-3.ꢀSPI Transfer Modes
Mode
CPOL
CPHA
Leading Edge
Rising, sample
Rising, setup
Falling, sample
Falling, setup
Trailing Edge
Falling, setup
Falling, sample
Rising, setup
Rising, sample
0
1
2
3
0
0
1
1
0
1
0
1
Note:ꢀ
Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
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SERCOM SPI – SERCOM Serial Peripheral Interface
Figure 27-3.ꢀSPI Transfer Modes
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
27.6.2.6 Transferring Data
27.6.2.6.1 Host
In host mode (CTRLA.MODE=0x3), when Host SPI Enable Select (CTRLB.MSSEN) is ‘1’, hardware will control the
SS line.
When Host SPI Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be
assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line
low.
When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the
content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status
and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA.
Each time one character is shifted out from the host, another character will be shifted in from the client
simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred
to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And
the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The
received data can be retrieved by reading DATA.
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SERCOM SPI – SERCOM Serial Peripheral Interface
When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt
flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished,
the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to '0', the
software must pull the SS line high.
27.6.2.6.2 Client
In Client mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the
SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag
in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When SS is pulled low and SCK is running, the client will sample and shift out data according to the Transaction
mode set. When the content of TxDATA has been loaded into the Shift register, INTFLAG.DRE will be set, and new
data can be written to DATA.
Similar to the host, the client will receive one character for each character transmitted. A character will be transferred
into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can
be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set.
When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.TXC) will be set.
After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the
Shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction
will not be the content of DATA. This can be avoided by using the preloading feature. Refer to 27.6.3.2 Preloading of
the Client Shift Register.
When transmitting several characters in one SPI transaction, the data has to be written into DATA register with
at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously
received character will be transmitted.
Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
27.6.2.7 Receiver Error Bit
The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register
(STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit is also automatically
cleared when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the immediate buffer overflow notification bit in the
Control A register (CTRLA.IBON):
If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the
receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG.RXC) goes low.
If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the received data is
read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.
27.6.3 Additional Features
27.6.3.1 Address Recognition
When the SPI is configured for client operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is
0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address
match.
If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in Sleep
mode, an address match can wake-up the device in order to process the transaction.
If there is no match, the complete transaction is ignored.
If a 9-bit frame format is selected, only the lower 8 bits of the Shift register are checked against the Address register
(ADDR).
Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode.
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SERCOM SPI – SERCOM Serial Peripheral Interface
Related Links
25.6.3.1 Address Match and Mask
27.6.3.2 Preloading of the Client Shift Register
When starting a transaction, the client will first transmit the contents of the shift register before loading new data from
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since
the last reset) or the last character in the previous transmission.
Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a dummy
character when starting a transaction. If the shift register is not preloaded, the current contents of the shift register will
be shifted out.
Only one data character will be preloaded into the shift register while the synchronized SS signal is high. If the next
character is written to DATA before SS is pulled low, the second character will be stored in DATA until transfer begins.
For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling edge, as in
Timing Using Preloading. See also the Electrical Characteristics chapters for timing details.
Preloading is enabled by writing '1' to the Client Data Preload Enable bit in the CTRLB register (CTRLB.PLOADEN).
Figure 27-4.ꢀTiming Using Preloading
Required SS-to-SCK time
using PRELOADEN
SS
SS synchronized
to system domain
SCK
Synchronization
to system domain
MISO to SCK
setup time
Related Links
37. Electrical Characteristics at 85℃
27.6.3.3 Host with Several Clients
Host with multiple clients in parallel is only available when Host SPI Select Enable (CTRLB.MSSEN) is set to zero
and hardware SS control is disabled. If the bus consists of several SPI clients, a SPI host can use general purpose
I/O pins to control the SS line to each of the clients on the bus, as shown in the following figure. In this configuration,
the single selected SPI client will drive the tri-state MISO line.
Figure 27-5.ꢀMultiple Clients in Parallel
MOSI
MISO
SCK
MOSI
MISO
SCK
SS
shift register
shift register
SS[0]
SPI Client 0
SPI Host
MOSI
MISO
SCK
SS
SS[n-1]
shift register
SPI Client n-1
Another configuration is multiple clients in series, as shown in the following figure. In this configuration, all n attached
clients are connected in series. A common SS line is provided to all clients, enabling them simultaneously. The host
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SERCOM SPI – SERCOM Serial Peripheral Interface
must shift n characters for a complete transaction. Depending on the Host SPI Select Enable bit (CTRLB.MSSEN),
the SS line can be controlled either by hardware or user software and normal GPIO.
Figure 27-6.ꢀMultiple Clients in Series
MOSI
MISO
SCK
SS
MOSI
MISO
SCK
SS
shift register
shift register
SPI Client 0
SPI Host
MOSI
MISO
SCK
SS
shift register
SPI Client n-1
27.6.3.4 Loop-Back Mode
For loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the
same data pins for transmit and receive. The loop-back is through the pad, so the signal is also available externally.
27.6.3.5 Hardware Controlled SS
In Host mode, a single SS chip select can be controlled by hardware by writing the Host SPI Select Enable
(CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle before
transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back
frames are transmitted, the SS pin will always be driven high for a minimum of one baud cycle between frames.
In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI Transfer mode.
Figure 27-7.ꢀHardware Controlled SS
T
T
T
T
T
SS
SCK
T = 1 to 2 baud cycles
When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.
27.6.3.6 SPI Select Low Detection
In Client mode, the SPI can wake the CPU when the SPI Select (SS) goes low. When the SPI Select Low Detect is
enabled (CTRLB.SSDE=1), a high-to-low transition will set the SPI Select Low Interrupt flag (INTFLAG.SSL) and the
device will wake-up if applicable.
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SERCOM SPI – SERCOM Serial Peripheral Interface
27.6.4 DMA, Interrupts, and Events
Table 27-4.ꢀModule Request for SERCOM SPI
Condition
Request
DMA
Interrupt
Event
Data Register Empty (DRE)
Receive Complete (RXC)
Yes
Yes
NA
(request cleared when data is written)
Yes
Yes
(request cleared when data is read)
Transmit Complete (TXC)
SPI Select low (SSL)
Error (ERROR)
NA
NA
NA
Yes
Yes
Yes
27.6.4.1 DMA Operation
The SPI generates the following DMA requests:
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
•
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
27.6.4.2 Interrupts
The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from
any Sleep mode:
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
SPI Select Low (SSL)
Error (ERROR)
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing
'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). The current state of enabled interrupts can be
read from INTENSET or INTENCLR.
An interrupt request is generated when the Interrupt flag is set and if the corresponding interrupt is enabled. The
interrupt request remains active until either the Interrupt flag is cleared, the interrupt is disabled, or the SPI is reset.
For details on clearing Interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
27.6.4.3 Events
Not applicable.
27.6.5 Sleep Mode Operation
The behavior in Sleep mode is depending on the host/client configuration and the Run In Standby bit in the Control A
register (CTRLA.RUNSTDBY):
•
Host operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOMx_CORE will continue to run in
Idle Sleep mode and in Standby Sleep mode. Any interrupt can wake-up the device.
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SERCOM SPI – SERCOM Serial Peripheral Interface
•
Host operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is
finished. Any interrupt can wake up the device.
•
•
Client operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake-up the device.
Client operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.
27.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Note:ꢀ CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB register for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
IBON
15:8
0x00
0x04
CTRLA
23:16
31:24
7:0
DIPO[1:0]
DOPO[1:0]
DORD
CPOL
CPHA
FORM[3:0]
PLOADEN
CHSIZE[2:0]
SSDE
15:8
AMODE[1:0]
MSSEN
CTRLB
23:16
31:24
RXEN
0x08
...
Reserved
BAUD
0x0B
0x0C
0x0D
...
7:0
BAUD[7:0]
Reserved
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
7:0
7:0
7:0
ERROR
ERROR
ERROR
SSL
SSL
SSL
RXC
RXC
TXC
TXC
TXC
DRE
DRE
DRE
RXC
7:0
15:8
7:0
BUFOVF
CTRLB
0x1A
STATUS
ENABLE
SWRST
15:8
23:16
31:24
0x1C
SYNCBUSY
0x20
...
Reserved
0x23
7:0
15:8
23:16
31:24
7:0
ADDR[7:0]
0x24
ADDR
DATA
ADDRMASK[7:0]
DATA[7:0]
0x28
15:8
DATA[8]
0x2A
...
Reserved
0x2F
0x30
DBGCTRL
7:0
DBGSTOP
27.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Refer to 27.6.6 Synchronization
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
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SERCOM SPI – SERCOM Serial Peripheral Interface
Refer to 27.5.8 Register Access Protection.
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27.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
23
15
30
DORD
R/W
0
29
CPOL
R/W
0
28
CPHA
R/W
0
27
26
25
24
FORM[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
22
14
6
21
20
19
18
10
2
17
16
DIPO[1:0]
DOPO[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
13
12
11
9
8
IBON
R/W
0
Access
Reset
Bit
7
5
4
3
MODE[2:0]
R/W
1
0
SWRST
R/W
0
RUNSTDBY
ENABLE
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
Bit 30 – DORDꢀData Order
This bit selects the data order when a character is shifted out from the shift register.
This bit is not synchronized.
Value
Description
0
1
MSB is transferred first.
LSB is transferred first.
Bit 29 – CPOLꢀClock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
This bit is not synchronized.
Value
Description
0
SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a
falling edge.
1
SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a
rising edge.
Bit 28 – CPHAꢀClock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
This bit is not synchronized.
Mode
CPOL
CPHA
Leading Edge
Trailing Edge
0x0
0x1
0x2
0x3
0
0
1
1
0
1
0
1
Rising, sample
Rising, change
Falling, sample
Falling, change
Falling, change
Falling, sample
Rising, change
Rising, sample
Value
Description
0
1
The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
DS40001882G-page 461
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
Bits 27:24 – FORM[3:0]ꢀFrame Format
This bit field selects the various frame formats supported by the SPI in client mode. When the 'SPI frame with
address' format is selected, the first byte received is checked against the ADDR register.
FORM[3:0]
Name
Description
0x0
SPI
SPI frame
0x1
-
Reserved
0x2
0x3-0xF
SPI_ADDR
-
SPI frame with address
Reserved
Bits 21:20 – DIPO[1:0]ꢀData In Pinout
These bits define the data in (DI) pad configurations.
In host operation, DI is MISO.
In client operation, DI is MOSI.
These bits are not synchronized.
DIPO[1:0]
Name
Description
0x0
0x1
0x2
0x3
PAD[0]
PAD[1]
PAD[2]
PAD[3]
SERCOM PAD[0] is used as data input
SERCOM PAD[1] is used as data input
SERCOM PAD[2] is used as data input
SERCOM PAD[3] is used as data input
Bits 17:16 – DOPO[1:0]ꢀData Out Pinout
This bit defines the available pad configurations for data out (DO), the serial clock (SCK) and the SPI select (SS). In
Client operation, the SPI Select line (SS) is controlled by DOPO. In host operation, the SPI Select line (SS) is either
controlled by DOPO when CTRLB.MSSEN = 1, or by a GPIO driven by the application when CTRLB.MSSEN = 0.
In host operation, DO is MOSI.
In client operation, DO is MISO.
These bits are not synchronized.
DOPO DO
SCK
Client SS Host SS (MSSEN = 1)
Host SS (MSSEN = 0)
0x0
0x1
0x2
0x3
PAD[0] PAD[1] PAD[2]
PAD[2] PAD[3] PAD[1]
PAD[3] PAD[1] PAD[2]
PAD[0] PAD[3] PAD[1]
PAD[2]
PAD[1]
PAD[2]
PAD[1]
Any GPIO configured by the application
Any GPIO configured by the application
Any GPIO configured by the application
Any GPIO configured by the application
Bit 8 – IBONꢀImmediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs.
This bit is not synchronized.
Value
Description
0
1
STATUS.BUFOVF is set when it occurs in the data stream.
STATUS.BUFOVF is set immediately upon buffer overflow.
Bit 7 – RUNSTDBYꢀRun In Standby
This bit defines the functionality in standby sleep mode.
These bits are not synchronized.
RUNSTDBY Client
Host
0x0
Disabled. All reception is dropped, including
the ongoing transaction.
Ongoing transaction continues, wake on
Receive Complete interrupt.
Generic clock is disabled when ongoing transaction
is finished. All interrupts can wake up the device.
Generic clock is enabled while in sleep modes. All
interrupts can wake up the device.
0x1
Bits 4:2 – MODE[2:0]ꢀOperating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.
0x2: SPI client operation
0x3: SPI host operation
DS40001882G-page 462
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
These bits are not synchronized.
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled.
The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation
is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY. SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 463
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
23
15
30
22
14
29
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
Access
Reset
Bit
21
17
RXEN
R/W
0
Access
Reset
Bit
13
MSSEN
R/W
0
9
SSDE
R/W
0
AMODE[1:0]
Access
Reset
R/W
0
R/W
0
Bit
7
6
PLOADEN
R/W
5
1
0
CHSIZE[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit 17 – RXENꢀReceiver Enable
Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing
receptions will be lost and STATUS.BUFOVF will be cleared.
Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled,
CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the
receiver is enabled CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the
receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
1
The receiver is disabled or being enabled.
The receiver is enabled or it will be enabled when SPI is enabled.
Bits 15:14 – AMODE[1:0]ꢀAddress Mode
These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are
unused in Host mode.
These bits are not synchronized.
AMODE[1:0] Name
Description
0x0
0x1
0x2
MASK
ADDRMASK is used as a mask to the ADDR register
2_ADDRS The client responds to the two unique addresses in ADDR and ADDRMASK
RANGE
The client responds to the range of addresses between and including ADDR and
ADDRMASK. ADDR is the upper limit
Reserved
0x3
-
Bit 13 – MSSENꢀHost SPI Select Enable
This bit enables hardware SPI Select (SS) control.
This bit is not synchronized.
DS40001882G-page 464
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
Value
Description
0
1
Hardware SS control is disabled.
Hardware SS control is enabled.
Bit 9 – SSDEꢀSPI Select Low Detect Enable
This bit enables wake-up when the SPI Select (SS) pin transitions from high to low.
This bit is not synchronized.
Value
Description
0
1
SS low detector is disabled.
SS low detector is enabled.
Bit 6 – PLOADENꢀClient Data Preload Enable
Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is
high when DATA is written, it will be transferred immediately to the Shift register.
This bit is not synchronized.
Bits 2:0 – CHSIZE[2:0]ꢀCharacter Size
These bits are not synchronized.
CHSIZE[2:0]
Name
Description
0x0
0x1
0x2-0x7
8BIT
9BIT
-
8 bits
9 bits
Reserved
DS40001882G-page 465
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.3 Baud Rate
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BAUD
0x0C
0x00
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
2
1
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0]ꢀBaud Register
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator.
Related Links
25.6.2.3 Clock Generation – Baud-Rate Generator
DS40001882G-page 466
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
ERROR
R/W
0
6
5
4
3
2
1
0
SSL
R/W
0
RXC
R/W
0
TXC
R/W
0
DRE
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 3 – SSLꢀSPI Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the SPI Select Low Interrupt Enable bit, which disables the SPI Select Low interrupt.
Value
Description
0
1
SPI Select Low interrupt is disabled.
SPI Select Low interrupt is enabled.
Bit 2 – RXCꢀReceive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
Value
Description
0
1
Receive Complete interrupt is disabled.
Receive Complete interrupt is enabled.
Bit 1 – TXCꢀTransmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete
interrupt.
Value
Description
0
1
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DREꢀData Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty
interrupt.
Value
Description
0
1
Data Register Empty interrupt is disabled.
Data Register Empty interrupt is enabled.
DS40001882G-page 467
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x16
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
ERROR
R/W
0
6
5
4
3
2
1
0
SSL
R/W
0
RXC
R/W
0
TXC
R/W
0
DRE
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 3 – SSLꢀSPI Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the SPI Select Low Interrupt Enable bit, which enables the SPI Select Low interrupt.
Value
Description
0
1
SPI Select Low interrupt is disabled.
SPI Select Low interrupt is enabled.
Bit 2 – RXCꢀReceive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
Value
Description
0
1
Receive Complete interrupt is disabled.
Receive Complete interrupt is enabled.
Bit 1 – TXCꢀTransmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
Value
Description
0
1
Transmit Complete interrupt is disabled.
Transmit Complete interrupt is enabled.
Bit 0 – DREꢀData Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty
interrupt.
Value
Description
0
1
Data Register Empty interrupt is disabled.
Data Register Empty interrupt is enabled.
DS40001882G-page 468
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00
-
Property:ꢀ
Bit
7
ERROR
R/W
0
6
5
4
3
2
RXC
R
1
0
DRE
R
SSL
R/W
0
TXC
R/W
0
Access
Reset
0
0
Bit 7 – ERRORꢀError
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding Status flags in the STATUS
register. The BUFOVF error will set this Interrupt flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – SSLꢀSPI Select Low
This flag is cleared by writing '1' to it.
This bit is set when a high to low transition is detected on the SS pin in Client mode and SPI Select Low Detect
(CTRLB.SSDE) is enabled.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – RXCꢀReceive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data
received in a transaction will be an address.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXCꢀTransmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
In Host mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In Client mode, this flag is set when the SS pin is pulled high. If address matching is enabled, this flag is only set if
the transaction was initiated with an address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DREꢀData Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready for new data to transmit.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
DS40001882G-page 469
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.7 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x1A
0x0000
–
Property:ꢀ
Bit
15
7
14
13
5
12
4
11
3
10
9
1
8
0
Access
Reset
Bit
6
2
BUFOVF
R/W
Access
Reset
0
Bit 2 – BUFOVFꢀBuffer Overflow
Reading this bit before reading DATA will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling.
When set, the corresponding RxDATA will be zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Value
Description
0
1
No Buffer Overflow has occurred.
A Buffer Overflow has occurred.
DS40001882G-page 470
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.8 Synchronization Busy
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SYNCBUSY
0x1C
0x00000000
-
Property:ꢀ
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
1
0
CTRLB
ENABLE
SWRST
Access
Reset
R
0
R
0
R
0
Bit 2 – CTRLBꢀCTRLB Synchronization Busy
Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization is indicated
by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB=1, an APB
error will be generated.
Value
Description
0
1
CTRLB synchronization is not busy.
CTRLB synchronization is busy.
Bit 1 – ENABLEꢀSERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing synchronization is
indicated by SYNCBUSY.ENABLE=1 until synchronization is complete.
Value
Description
0
1
Enable synchronization is not busy.
Enable synchronization is busy.
Bit 0 – SWRSTꢀSoftware Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated by
SYNCBUSY.SWRST=1 until synchronization is complete.
Value
Description
0
1
SWRST synchronization is not busy.
SWRST synchronization is busy.
DS40001882G-page 471
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.9 Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x24
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
21
20
ADDRMASK[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:16 – ADDRMASK[7:0]ꢀAddress Mask
These bits hold the address mask when the transaction format with address is used (CTRLA.FORM,
CTRLB.AMODE).
Bits 7:0 – ADDR[7:0]ꢀAddress
These bits hold the address when the transaction format with address is used (CTRLA.FORM, CTRLB.AMODE).
DS40001882G-page 472
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.10 Data
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATA
0x28
0x0000
–
Property:ꢀ
Bit
15
7
14
13
5
12
4
11
3
10
2
9
1
8
DATA[8]
R/W
0
Access
Reset
Bit
6
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 8:0 – DATA[8:0]ꢀData
Reading these bits will return the contents of the receive data buffer. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set.
Writing these bits will write the transmit data buffer. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
DS40001882G-page 473
Complete Datasheet
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SAM D21/DA1 Family
SERCOM SPI – SERCOM Serial Peripheral Interface
27.8.11 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x30
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
R/W
Access
Reset
0
Bit 0 – DBGSTOPꢀDebug Stop Mode
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
1
The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
The baud-rate generator is halted when the CPU is halted by an external debugger.
DS40001882G-page 474
Complete Datasheet
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SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
28.
SERCOM I2C – Inter-Integrated Circuit
28.1
Overview
The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication interface
(SERCOM).
The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 28-1. Labels in capital
letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
A SERCOM instance can be configured to be either an I2C host or an I2C client. Both host and client have an
interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C host uses the SERCOM
baud-rate generator, while the I2C client uses the SERCOM address match logic.
Related Links
25. SERCOM – Serial Communication Interface
28.2
Features
SERCOM I2C includes the following features:
•
•
•
•
•
•
•
•
Host or Client Operation
Can be used with DMA
Philips I2C Compatible
SMBus Compatible
™
PMBus Compatible
Support of 100 kHz and 400 kHz, 1 MHz and 3.4 MHz I2C mode
4-Wire Operation Supported
Physical interface includes:
– Slew-rate limited outputs
– Filtered inputs
•
Client Operation:
– Operation in all Sleep modes
– Wake-up on address match
– 7-bit and 10-bit Address match in hardware for:
–
•
•
•
Unique address and/or 7-bit general call address
Address range
Two unique addresses can be used with DMA
Related Links
25.2 Features
DS40001882G-page 475
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
28.3
Block Diagram
Figure 28-1.ꢀI2C Single-Host Single-Client Interconnection
Host
Client
BAUD
TxDATA
TxDATA
ADDR/ADDRMASK
SCL
SDA
0
0
0
SCL hold low
baud rate generator
SCL hold low
shift register
RxDATA
shift register
0
RxDATA
==
28.4
Signal Description
Signal Name
PAD[0]
Type
Description
Digital I/O
Digital I/O
Digital I/O
Digital I/O
SDA
SCL
PAD[1]
PAD[2]
SDA_OUT (4-wire operation)
SCL_OUT (4-wire operation)
PAD[3]
One signal can be mapped on several pins.
Not all the pins are I2C pins. Refer to Table 7-5. SERCOM Pins Supporting I2C for additional information .
Related Links
7. I/O Multiplexing and Considerations
28.6.3.3 4-Wire Mode
28.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
28.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT).
When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins. If the receiver
or transmitter is disabled, these pins can be used for other purposes.
Related Links
23. PORT - I/O Pin Controller
28.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes.
Related Links
16. PM – Power Manager
DS40001882G-page 476
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
28.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to
Peripheral Clock Masking for details and default status of this clock.
Two generic clocks are used by SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW. The core clock
(GCLK_SERCOMx_CORE) can clock the I2C when working as a host. The slow clock (GCLK_SERCOM_SLOW)
is required only for certain functions, e.g. SMBus timing. These two clocks must be configured and enabled in the
Generic Clock Controller (GCLK) before using the I2C.
These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to
certain registers will require synchronization between the clock domains. Refer to 28.6.6 Synchronization for further
details.
Related Links
15. GCLK - Generic Clock Controller
16. PM – Power Manager
16.6.2.6 Peripheral Clock Masking
28.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this
peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.
Related Links
20. DMAC – Direct Memory Access Controller
28.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
28.5.6 Events
Not applicable.
28.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging - refer to the Debug Control
(DBGCTRL) register for details.
28.5.8 Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
•
•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register
description.
Write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
DS40001882G-page 477
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
28.5.9 Analog Connections
Not applicable.
28.6
Functional Description
28.6.1 Principle of Operation
The I2C interface uses two physical lines for communication:
•
•
Serial Data Line (SDA) for data transfer
Serial Clock Line (SCL) for the bus clock
A transaction starts with the I2C host sending the Start condition, followed by a 7-bit address and a direction bit (read
or write to/from the client).
The addressed I2C client will then Acknowledge (ACK) the address, and data packet transactions can begin. Every
9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or
not.
If a data packet is Not Acknowledged (NACK), whether by the I2C client or host, the I2C host takes action by either
terminating the transaction by sending the Stop condition, or by sending a repeated start to transfer more data.
The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains the
transaction symbols. These symbols will be used in the following descriptions.
Figure 28-2.ꢀTransaction Diagram Symbols
Bus Driver
Special Bus Conditions
Host driving bus
START condition
S
Sr
P
Client driving bus
repeated START condition
STOP condition
Either Host or Client driving bus
Data Package Direction
Acknowledge
Host Read
Acknowledge (ACK)
R
A
'1'
'0'
Host Write
Not Acknowledge (NACK)
W
A
'0'
'1'
DS40001882G-page 478
Complete Datasheet
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SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
Figure 28-3.ꢀBasic I2C Transaction Diagram
SDA
SCL
6..0
7..0
DATA
7..0
S
ADDRESS
R/W
ACK
ACK
DATA
ACK/NACK
P
S
ADDRESS
R/W
A
DATA
A
DATA
A/A
P
Direction
Address Packet
Data Packet #0
Transaction
Data Packet #1
28.6.2 Basic Operation
28.6.2.1 Initialization
The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled
(CTRLA.ENABLE is ‘0’):
•
•
•
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
Baud register (BAUD)
Address register (ADDR) in client operation.
When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the
I2C is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the I2C is enabled it must be configured as outlined by the following steps:
1. Select I2C Host or Client mode by writing 0x4 (Client mode) or 0x5 (Host mode) to the Operating Mode bits in
the CTRLA register (CTRLA.MODE).
2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD).
3. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register
(CTRLB.SMEN).
4. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUTEN).
5. In Host mode:
5.1.
Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register
(CTRLA.INACTOUT).
5.2.
Write the Baud Rate register (BAUD) to generate the desired baud rate.
In Client mode:
5.1.
Configure the address match configuration by writing the Address Mode value in the CTRLB register
(CTRLB.AMODE).
5.2.
Set the Address and Address Mask value in the Address register (ADDR.ADDR and
ADDR.ADDRMASK) according to the address configuration.
28.6.2.2 Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by
writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral
to their initial states, except the DBGCTRL register, and the peripheral is disabled.
DS40001882G-page 479
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
28.6.2.3 I2C Bus State Logic
The Bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in
all Sleep modes with running GCLK_SERCOM_x clocks. The start and stop detectors and the bit counter are
all essential in the process of determining the current Bus state. The Bus state is determined according to Bus
State Diagram. Software can get the current Bus state by reading the Host Bus State bits in the Status register
(STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary.
Figure 28-4.ꢀBus State Diagram
RESET
UNKNOWN
(0b00)
Timeout or Stop Condition
Start Condition
IDLE
(0b01)
BUSY
(0b11)
Timeout or Stop Condition
Stop Condition
Write ADDR to generate
Start Condition
Lost Arbitration
OWNER
(0b10)
Write ADDR to generate
Repeated Start Condition
The Bus state machine is active when the I2C host is enabled.
After the I2C host has been enabled, the Bus state is UNKNOWN (0b00). From the UNKNOWN state, the bus will
transition to IDLE (0b01) by either:
•
•
•
Forcing by writing 0b01 to STATUS.BUSSTATE
A Stop condition is detected on the bus
If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a time-out occurs.
Note:ꢀ Once a known Bus state is established, the Bus state logic will not re-enter the UNKNOWN state.
When the bus is IDLE it is ready for a new transaction. If a Start condition is issued on the bus by another I2C host
in a multi-host setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either when a Stop condition is
detected, or when a time-out occurs (inactive bus time-out needs to be configured).
If a Start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR)
while IDLE, the OWNER state (0b10) is entered. If the complete transaction was performed without interference, i.e.,
arbitration was not lost, the I2C host can issue a Stop condition, which will change the Bus state back to IDLE.
However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the Bus state
becomes BUSY until a Stop condition is detected. A repeated Start condition will change the Bus state only if
arbitration is lost while issuing a repeated start.
Note:ꢀ Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this state by a
software Reset (CTRLA.SWRST='1').
Related Links
28.10.1 CTRLA
DS40001882G-page 480
Complete Datasheet
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SERCOM I2C – Inter-Integrated Circuit
28.6.2.4 I2C Host Operation
The I2C host is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by
automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of
operations, and a Special Smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN).
The I2C host has two interrupt strategies.
When SCL Clock Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the Acknowledge bit . In this
mode the I2C host operates according to the following figure. The circles labeled "Mn" (M1, M2..) indicate the nodes
the bus logic can jump to, based on software or hardware interaction.
This diagram is used as reference for the description of the I2C host operation throughout the document.
Figure 28-5.ꢀI2C Host Behavioral Diagram (SCLSM=0)
APPLICATION
HOST BUS INTERRUPT + SCL HOLD
M1
M2
P
M3
S
M4
ADDRESS
BUSY
IDLE
R/W BUSY
SW
SW
SW
SW
BUSY
M1
M2
M3
Wait for
IDLE
R/W
W
A
A
P
IDLE
SW
Sr
BUSY
A/A
M4
DATA
CLIENT BUS INTERRUPT + SCL HOLD
Software interaction
SW
A
BUSY
SW
M4
M2
M3
The host provides data on the bus
A/A
P
IDLE
Addressed client provides data on the bus
A/A Sr
A/A
R
A
DATA
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as shown in the following figure.
This strategy can be used when it is not necessary to check DATA before acknowledging.
Note:ꢀ I2C High-speed (Hs) mode requires CTRLA.SCLSM=1.
DS40001882G-page 481
Complete Datasheet
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SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
Figure 28-6.ꢀ I2C Host Behavioral Diagram (SCLSM=1)
APPLICATION
Host Bus INTERRUPT + SCL HOLD
M1
M2
P
M3
S
M4
BUSY
IDLE
R/W BUSY
BUSY
ADDRESS
SW
SW
SW
SW
M1
M2
M3
Wait for
IDLE
R/W
W
A
A
P
IDLE
SW
Sr
BUSY
A/A
M4
DATA
Client Bus INTERRUPT + SCL HOLD
Software interaction
SW
BUSY
SW
M4
M2
M3
The host provides data on the bus
P
IDLE
Addressed client provides data on the bus
Sr
A/A
R
A
DATA
28.6.2.4.1 Host Clock Generation
The SERCOM peripheral supports several I2C bidirectional modes:
•
•
•
•
Standard mode (Sm) up to 100 kHz
Fast mode (Fm) up to 400 kHz
Fast mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode,
and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).
Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
In I2C Sm, Fm, and Fm+ mode, the Host clock (SCL) frequency is determined as described in this section:
The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE
)
and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be
considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been
detected.
DS40001882G-page 482
Complete Datasheet
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SERCOM I2C – Inter-Integrated Circuit
Figure 28-7.ꢀSCL Timing
P
TRISE
S
TLOW
Sr
SCL
THIGH
TFALL
TBUF
SDA
TSU;STO
THD;STA
TSU;STA
The following parameters are timed using the SCL low time period TLOW. This comes from the Host Baud Rate Low
bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Host Baud Rate bit group
in the Baud Rate register (BAUD.BAUD) determines it.
•
•
•
•
•
•
•
•
TLOW – Low period of SCL clock
TSU;STO – Set-up time for stop condition
TBUF – Bus free time between stop and start conditions
THD;STA – Hold time (repeated) start condition
TSU;STA – Set-up time for repeated start condition
THIGH is timed using the SCL high time count from BAUD.BAUD
TRISE is determined by the bus impedance; for internal pull-ups.
TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero.
The SCL frequency is given by:
1
f
=
SCL
T
+ T
+ T
LOW
HIGH RISE
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the
following formula will give the SCL frequency:
f
GCLK
f
=
SCL
10 + 2BAUD + f
⋅ T
GCLK RISE
When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:
f
GCLK
f
=
SCL
10 + BAUD + BAUDLOW + f
⋅ T
GCLK RISE
The following formulas can determine the SCL TLOW and THIGH times:
BAUDLOW + 5
T
=
=
LOW
f
GCLK
BAUD + 5
T
HIGH
f
GCLK
Note:ꢀ The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be
set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.
Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA
register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA
write and IF clear must be controlled by software.
Note:ꢀ When timing is controlled by user, the Smart Mode cannot be enabled.
Related Links
37. Electrical Characteristics at 85℃
DS40001882G-page 483
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
Host Clock Generation (High-Speed Mode)
For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by
the GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register
(BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and SCL low. In
this case the following formula determines the SCL frequency.
f
GCLK
f
=
SCL
2 + 2 ⋅ HS BAUD
When HSBAUDLOW is non-zero, the following formula determines the SCL frequency.
f
GCLK
f
=
SCL
2 + HS BAUD + HSBAUDLOW
Note:ꢀ The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD should be
set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be non-zero.
28.6.2.4.2 Transmitting Address Packets
The I2C host starts a bus transaction by writing the I2C client address to ADDR.ADDR and the direction bit, as
described in 28.6.1 Principle of Operation. If the bus is busy, the I2C host will wait until the bus becomes idle before
continuing the operation. When the bus is idle, the I2C host will issue a start condition on the bus. The I2C host
will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been
transmitted by the I2C host, one of four cases will arise according to arbitration and transfer direction.
Case 1: Arbitration lost or bus error during address packet transmission
If arbitration was lost during transmission of the address packet, the Host on Bus bit in the Interrupt Flag Status and
Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set.
Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C host
is no longer allowed to execute any operation on the bus until the bus is idle again. A bus error will behave similarly
to the Arbitration Lost condition. In this case, the MB Interrupt flag and Host Bus Error bit in the Status register
(STATUS.BUSERR) are both set in addition to STATUS.ARBLOST.
The Host Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last
successfully received acknowledge or not acknowledge indication.
In this case, software will typically inform the application code of the condition and then clear the Interrupt flag before
exiting the interrupt routine. No other flags have to be cleared at this moment, because all flags will be cleared
automatically the next time the ADDR.ADDR register is written.
Case 2: Address packet transmit complete – No ACK received
If there is no I2C client device responding to the address packet, then the INTFLAG.MB Interrupt flag and
STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus.
The missing ACK response can indicate that the I2C client is busy with other tasks or sleeping. Therefore, it is not
able to respond. In this event, the next step can be either issuing a Stop condition (recommended) or resending the
address packet by a repeated Start condition. When using SMBus logic, the client must ACK the address. If there is
no response, it means that the client is not available on the bus.
Case 3: Address packet transmit complete – Write packet, Host on Bus set
If the I2C host receives an acknowledge response from the I2C client, INTFLAG.MB will be set and STATUS.RXNACK
will be cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the
I2C operation to continue:
•
•
Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
Transmit a new address packet by writing ADDR.ADDR. A repeated Start condition will automatically be inserted
before the address packet.
•
Issue a Stop condition, consequently terminating the transaction.
Case 4: Address packet transmit complete – Read packet, Client on Bus set
DS40001882G-page 484
Complete Datasheet
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SERCOM I2C – Inter-Integrated Circuit
If the I2C host receives an ACK from the I2C client, the I2C host proceeds to receive the next byte of data from the I2C
client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be
set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the
I2C operation to continue:
•
Let the I2C host continue to read data by acknowledging the data received. ACK can be sent by software, or
automatically in Smart mode.
•
•
Transmit a new address packet.
Terminate the transaction by issuing a Stop condition.
Note:ꢀ An ACK or NACK will be automatically transmitted if Smart mode is enabled. The Acknowledge Action bit in
the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
28.6.2.4.3 Transmitting Data Packets
When an address packet with direction Host Write (see Figure 28-3) was transmitted successfully , INTFLAG.MB will
be set. The I2C host will start transmitting data via the I2C bus by writing to DATA.DATA, and monitor continuously for
packet collisions.
If a collision is detected, the I2C host will lose arbitration and STATUS.ARBLOST will be set. If the transmit
was successful, the I2C host will receive an ACK bit from the I2C client, and STATUS.RXNACK will be cleared.
INTFLAG.MB will be set in both cases, regardless of arbitration outcome.
It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning of the
I2C Host on Bus interrupt. This can be done as there is no difference between handling address and data packet
arbitration.
STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can
commence. The I2C host is not allowed to continue transmitting data packets if a NACK is received from the I2C
client.
28.6.2.4.4 Receiving Data Packets (SCLSM=0)
When INTFLAG.SB is set, the I2C host will already have received one data packet. The I2C host must respond
by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the
transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a
change in arbitration. Handling of lost arbitration is the same as for data bit transmission.
28.6.2.4.5 Receiving Data Packets (SCLSM=1)
When INTFLAG.SB is set, the I2C host will already have received one data packet and transmitted an ACK or NACK,
depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct value for the next ACK bit,
and the transaction can continue by reading DATA and issuing a command if not in the Smart mode.
28.6.2.4.6 High-Speed Mode
High-speed transfers are a multi-step process, see High Speed Transfer.
First, a host code (0b00001nnn, where 'nnn' is a unique host code) is transmitted in Full-speed mode, followed by a
NACK since no client should acknowledge. Arbitration is performed only during the Full-speed Host Code phase. The
host code is transmitted by writing the host code to the Address register (ADDR.ADDR) and writing the High-speed
bit (ADDR.HS) to '0'.
After the host code and NACK have been transmitted, the host write interrupt will be asserted. In the meanwhile,
the client address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now in High-speed mode,
the host will generate a repeated start, followed by the client address with RW-direction. The bus will remain in
High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to
'1', along with the new address ADDR.ADDR to be transmitted.
DS40001882G-page 485
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
Figure 28-8.ꢀHigh Speed Transfer
F/S-mode
Hs-mode
F/S-mode
Host Code
S
R/W
A
DATA
A/A
P
A
Sr
ADDRESS
Hs-mode continues
N Data Packets
Sr
ADDRESS
Transmitting in High-speed mode requires the I2C host to be configured in High-speed mode (CTRLA.SPEED=0x2)
and the SCL Clock Stretch mode (CTRLA.SCLSM) bit set to '1'.
28.6.2.4.7 10-Bit Addressing
When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register
(ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be transmitted,
see 10-bit Address Transmission for a Read Transaction. The addressed client acknowledges the two address bytes,
and the transaction continues. Regardless of whether the transaction is a read or write, the host must start by
sending the 10-bit address with the direction bit (ADDR.ADDR[0]) being zero.
If the host receives a NACK after the first byte, the Write Interrupt flag will be raised and the STATUS.RXNACK bit
will be set. If the first byte is acknowledged by one or more clients, then the host will proceed to transmit the second
address byte and the host will first see the Write Interrupt flag after the second byte is transmitted. If the transaction
direction is read-from-client, the 10-bit address transmission must be followed by a repeated start and the first 7 bits
of the address with the read/write bit equal to '1'.
Figure 28-9.ꢀ10-bit Address Transmission for a Read Transaction
MB INTERRUPT
1
S
W
S
W
A
addr[7:0]
A
Sr
R
A
11110 addr[9:8]
11110 addr[9:8]
This implies the following procedure for a 10-bit read operation:
1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit
(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR).
2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'.
ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR).
3. Proceed to transmit data.
28.6.2.5 I2C Client Operation
The I2C client is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by
automatic handling of most events. The software driver complexity and code size are reduced by auto-triggering of
operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN).
The I2C client has two interrupt strategies.
When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit. In this
mode, the I2C client operates according to the following figure. The circles labeled "Sn" (S1, S2..) indicate the nodes
the bus logic can jump to, based on software or hardware interaction.
This diagram is used as reference for the description of the I2C client operation throughout the document.
DS40001882G-page 486
Complete Datasheet
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SAM D21/DA1 Family
SERCOM I2C – Inter-Integrated Circuit
Figure 28-10.ꢀI2C Client Behavioral Diagram (SCLSM=0)
AMATCH INTERRUPT
DRDY INTERRUPT
P
S2
S3
A
A
Sr
S1
S2
S3
S
S1
S1
S
W
S
W
ADDRESS
R
DATA
A/A
P
S2
S3
A
A
Sr
PREC INTERRUPT
S
W
S
W
W
DATA
A/A
Interrupt on STOP
Condition Enabled
S
W
S
W
Software interaction
The host provides data on the bus
Addressed client provides data on the bus
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in the following
figure. This strategy can be used when it is not necessary to check DATA before acknowledging. For host reads, an
address and data interrupt will be issued simultaneously after the address acknowledge. However, for host writes, the
first data interrupt will be seen after the first data byte has been received by the client and the acknowledge bit has
been sent to the host.
Note:ꢀ For I2C High-speed mode (Hs), SCLSM=1 is required.
Figure 28-11.ꢀI2C Client Behavioral Diagram (SCLSM=1)
AMATCH INTERRUPT (+ DRDY INTERRUPT in Host Read mode)
DRDY INTERRUPT
P
S2
S3
Sr
S1
S2
S3
S
S
W
A/A
ADDRESS
R
DATA
A/A
P
S2
S3
Sr
PREC INTERRUPT
S
W
S
W
A/A
W
DATA
A/A
Interrupt on STOP
Condition Enabled
S
W
S
W
Software interaction
The host provides data on the bus
Addressed client provides data on the bus
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SERCOM I2C – Inter-Integrated Circuit
28.6.2.5.1 Receiving Address Packets (SCLSM=0)
When CTRLA.SCLSM=0, the I2C client stretches the SCL line according to Figure 28-10. When the I2C client is
properly configured, it will wait for a Start condition.
When a Start condition is detected, the successive address packet will be received and checked by the address
match logic. If the received address is not a match, the packet will be rejected, and the I2C client will wait for
a new Start condition. If the received address is a match, the Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) will be set.
SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL
low, the software has unlimited time to respond.
The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed
to the I2C client had a packet collision. A collision causes the SDA and SCL lines to be released without any
notification to software. Therefore, the next AMATCH interrupt is the first indication of the previous packet’s collision.
Collisions are intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C host, one of two cases will arise based on transfer direction.
Case 1: Address packet accepted – Read flag set
The STATUS.DIR bit is ‘1’, indicating an I2C host read operation. The SCL line is forced low, stretching the bus clock.
If an ACK is sent, I2C client hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY),
indicating data are needed for transmit. If a NACK is sent, the I2C client will wait for a new Start condition and
address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C client
Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read and write operations
as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to INTFLAG.AMATCH will also cause an
ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Case 2: Address packet accepted – Write flag set
The STATUS.DIR bit is cleared, indicating an I2C host write operation. The SCL line is forced low, stretching the bus
clock. If an ACK is sent, the I2C client will wait for data to be received. Data, repeated start or stop can be received.
If a NACK is sent, the I2C client will wait for a new Start condition and address match. Typically, software will
immediately acknowledge the address packet by sending an ACK/NACK. The I2C client command CTRLB.CMD = 3
can be used for both read and write operation as the command execution is dependent on STATUS.DIR.
Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
28.6.2.5.2 Receiving Address Packets (SCLSM=1)
When SCLSM=1, the I2C client will stretch the SCL line only after an ACK, see Client Behavioral Diagram
(SCLSM=1). When the I2C client is properly configured, it will wait for a Start condition to be detected.
When a Start condition is detected, the successive address packet will be received and checked by the address
match logic.
If the received address is not a match, the packet will be rejected and the I2C client will wait for a new Start condition.
If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B register
(CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set.
SCL will be stretched until the I2C client clears INTFLAG.AMATCH. As the I2C client holds the clock by forcing SCL
low, the software is given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the I2C client
had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software.
The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are intended
to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C host, INTFLAG.AMATCH be set to ‘1’ to clear it.
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SERCOM I2C – Inter-Integrated Circuit
28.6.2.5.3 Receiving and Transmitting Data Packets
After the I2C client has received an address packet, it will respond according to the direction either by waiting for the
data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is
received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C client will send an acknowledge according
to CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY Interrupt flag is set. If NACK is received,
indicated by STATUS.RXNACK=1, the I2C client must expect a stop or a repeated start to be received. The I2C client
must release the data line to allow the I2C host to generate a stop or repeated start. Upon detecting a Stop condition,
the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C client will return to IDLE
state.
28.6.2.5.4 High-Speed Mode
When the I2C client is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1, switching
between Full-speed and High-speed modes is automatic. When the client recognizes a START followed by a host
code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit
(STATUS.HS). The client will then remain in High-speed mode until a STOP is received.
28.6.2.5.5 10-Bit Addressing
When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will be checked
against the 10-bit client address recognition. The first byte of the address will always be acknowledged, and the
second byte will raise the address Interrupt flag, see 10-bit Addressing.
If the transaction is a write, then the 10-bit address will be followed by N data bytes.
If the operation is a read, the 10-bit address will be followed by a repeated START and reception of '11110
ADDR[9:8] 1', and the second address interrupt will be received with the DIR bit set. The client matches on the
second address as it was addressed by the previous 10-bit address.
Figure 28-12.ꢀ10-bit Addressing
AMATCH INTERRUPT
AMATCH INTERRUPT
S
W
S
W
S
W
A
addr[7:0]
Sr
R
11110 addr[9:8]
11110 addr[9:8]
A
28.6.2.5.6 PMBus Group Command
When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit addressing is used,
INTFLAG.PREC will be set if the client has been addressed since the last STOP condition. When CTRLB.GCMD=0,
a STOP condition without address match will not be set INTFLAG.PREC.
The group command protocol is used to send commands to more than one device. The commands are sent in one
continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the clients
addressed during the group command, they all begin executing the command they received.
The following figure shows an example where this client, bearing ADDRESS 1, is addressed after a repeated START
condition. There can be multiple clients addressed before and after this client. Eventually, at the end of the group
command, a single STOP is generated by the host. At this point a STOP interrupt is asserted.
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SERCOM I2C – Inter-Integrated Circuit
Figure 28-13.ꢀPMBus Group Command Example
Command/Data
n Bytes
A
A
S
ADDRESS 0
W
AMATCH INTERRUPT
DRDY INTERRUPT
Command/Data
ADDRESS 1
(this client)
S
W
S
A
n Bytes
A
Sr
Sr
W
W
PREC INTERRUPT
Command/Data
S
W
n Bytes
A
A
P
ADDRESS 2
W
28.6.3 Additional Features
28.6.3.1 SMBus
The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out,
host extend time-out, and client extend time-out. This allows for SMBus functionality These time-outs are driven by
the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and
must be configured to use a 32KHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold time.
•
•
•
TTIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by
CTRLA.LOWTOUTEN.
TLOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a
client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
TLOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time
by the host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by
CTRLA.MEXTTOEN.
28.6.3.2 Smart Mode
The I2C interface has a smart mode that simplifies application code and minimizes the user interaction needed to
adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK or NACK (based on
the content of CTRLB.ACKACT) as soon as DATA.DATA is read.
28.6.3.3 4-Wire Mode
Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode operation. In this
mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tri-state driver is needed when
connecting to an I2C bus.
Figure 28-14.ꢀI2C Pad Interface
SCL_OUT/
SDA_OUT
SCL_OUT/
SDA_OUT
pad
PINOUT
I2C
Driver
SCL/SDA
pad
SCL_IN/
SDA_IN
PINOUT
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SERCOM I2C – Inter-Integrated Circuit
28.6.3.4 Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When
quick command is enabled, the corresponding Interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after
the client acknowledges the address. At this point, the software can either issue a Stop command or a repeated start
by writing CTRLB.CMD or ADDR.ADDR.
28.6.4 DMA, Interrupts and Events
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually enabled by writing
‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the
Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request is active until the Interrupt flag is
cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG (Client) or INTFLAG (Host) register for details
on how to clear Interrupt flags.
Table 28-1.ꢀModule Request for SERCOM I2C Client
Condition
Request
DMA
Interrupt
Event
Data needed for transmit (TX) (Client Yes
NA
Transmit mode)
(request cleared
when data is
written)
Data received (RX) (Client Receive
mode)
Yes
(request cleared
when data is read)
Data Ready (DRDY)
Address Match (AMATCH)
Stop received (PREC)
Error (ERROR)
Yes
Yes
Yes
Yes
Table 28-2.ꢀModule Request for SERCOM I2C Host
Condition
Request
DMA
Interrupt
Event
Data needed for transmit (TX) (Host
Transmit mode)
Yes
NA
(request cleared
when data is
written)
Data needed for transmit (RX) (Host
Transmit mode)
Yes
(request cleared
when data is read)
Host on Bus (MB)
Stop received (SB)
Error (ERROR)
Yes
Yes
Yes
28.6.4.1 DMA Operation
Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.
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28.6.4.1.1 Client DMA
When using the I2C client with DMA, an address match will cause the address Interrupt flag
(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through
DMA.
The I2C client generates the following requests:
•
Write data received (RX): The request is set when host write data is received. The request is cleared when
DATA is read.
•
Read data needed for transmit (TX): The request is set when data is needed for a host read operation. The
request is cleared when DATA is written.
28.6.4.1.2 Host DMA
When using the I2C host with DMA, the ADDR register must be written with the desired address (ADDR.ADDR),
transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1
along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is
then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for host reads) and a STOP.
If a NACK is received by the client for a host write transaction before ADDR.LEN bytes, a STOP will be automatically
generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt.
The I2C host generates the following requests:
•
Read data received (RX): The request is set when host read data is received. The request is cleared when
DATA is read.
•
Write data needed for transmit (TX): The request is set when data is needed for a host write operation. The
request is cleared when DATA is written.
28.6.4.2 Interrupts
The I2C client has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device
from any Sleep mode:
•
•
•
•
Error (ERROR)
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC)
The I2C host has the following interrupt sources. These are asynchronous interrupts. They can wake-up the device
from any Sleep mode:
•
•
•
Error (ERROR)
Client on Bus (SB)
Host on Bus (MB)
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the Interrupt condition is meet. Each interrupt can be individually enabled by writing
‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR).
The status of enabled interrupts can be read from either INTENSET or INTENCLR. An interrupt request is generated
when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request active until the
Interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG register for details on how to
clear Interrupt flags.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
28.6.4.3 Events
Not applicable.
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SERCOM I2C – Inter-Integrated Circuit
28.6.5 Sleep Mode Operation
I2C Host Operation
The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the
Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in Standby Sleep mode. Any
interrupt can wake-up the device.
If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished. Any
interrupt can wake-up the device.
I2C Client Operation
Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake-up the device.
When CTRLA.RUNSTDBY=0, all receptions will be dropped.
28.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Command bits in CTRLB register (CTRLB.CMD)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in host operation.
The following registers are synchronized when written:
Data (DATA) when in host operation
•
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
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28.7
Register Summary - I2C Client
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
15:8
0x00
0x04
CTRLA
23:16
31:24
7:0
SEXTTOEN
SDAHOLD[1:0]
PINOUT
LOWTOUTEN
SCLSM
SPEED[1:0]
15:8
AMODE[1:0]
AACKEN
ACKACT
GCMD
SMEN
CTRLB
23:16
31:24
CMD[1:0]
0x08
...
Reserved
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
7:0
7:0
7:0
ERROR
ERROR
DRDY
DRDY
DRDY
AMATCH
AMATCH
AMATCH
PREC
PREC
ERROR
PREC
7:0
15:8
7:0
CLKHOLD
LOWTOUT
SR
DIR
RXNACK
HS
COLL
BUSERR
SWRST
0x1A
STATUS
SEXTTOUT
ENABLE
15:8
23:16
31:24
0x1C
SYNCBUSY
0x20
...
Reserved
0x23
7:0
15:8
23:16
31:24
7:0
ADDR[6:0]
GENCEN
TENBITEN
ADDR[9:7]
0x24
0x28
ADDR
DATA
ADDRMASK[6:0]
ADDRMASK[9:7]
DATA[7:0]
15:8
28.8
Register Description - I2C Client
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
28.6.6 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
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28.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
SCLSM
R/W
0
26
18
10
2
25
24
LOWTOUTEN
SPEED[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit
23
SEXTTOEN
R/W
22
14
6
21
20
19
17
16
SDAHOLD[1:0]
PINOUT
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bit
15
13
5
12
11
9
8
Access
Reset
Bit
7
4
3
MODE[2:0]
R/W
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
Bit 30 – LOWTOUTENꢀSCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the client will release its clock hold, if
enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.
This bit is not synchronized.
Value
Description
0
1
Time-out disabled.
Time-out enabled.
Bit 27 – SCLSMꢀSCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
Value
Description
0
1
SCL stretch according to Figure 28-10
SCL stretch only after ACK bit according to Figure 28-11
Bits 25:24 – SPEED[1:0]ꢀTransfer Speed
These bits define bus speed.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Description
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
Fast-mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs-mode) up to 3.4 MHz
Reserved
Bit 23 – SEXTTOENꢀClient SCL Low Extend Time-Out
This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the
initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any
interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a
STOP is received.
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This bit is not synchronized.
Value
Description
0
1
Time-out disabled
Time-out enabled
Bits 21:20 – SDAHOLD[1:0]ꢀSDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
75
450
600
Description
Disabled
50-100ns hold time
300-600ns hold time
400-800ns hold time
Bit 16 – PINOUTꢀPin Usage
This bit sets the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value
Description
0
1
4-wire operation disabled
4-wire operation enabled
Bit 7 – RUNSTDBYꢀRun in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value
Description
0
1
Disabled – All reception is dropped.
Wake on address match, if enabled.
Bits 4:2 – MODE[2:0]ꢀOperating Mode
These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM.
These bits are not synchronized.
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled.
The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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SERCOM I2C – Inter-Integrated Circuit
28.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
23
15
30
22
14
29
21
13
5
28
20
12
4
27
19
11
3
26
25
17
24
16
Access
Reset
Bit
18
ACKACT
R/W
CMD[1:0]
Access
Reset
W
0
W
0
0
Bit
10
AACKEN
R/W
9
GCMD
R/W
0
8
SMEN
R/W
0
AMODE[1:0]
Access
Reset
R/W
0
R/W
0
0
Bit
7
6
2
1
0
Access
Reset
Bit 18 – ACKACTꢀAcknowledge Action
This bit defines the client's acknowledge behavior after an address or data byte is received from the host.
The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled
(CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
ACKACT shall not be updated more than once between each peripheral interrupts request.
This bit is not enable-protected.
Value
0
Description
Send ACK
1
Send NACK
Bits 17:16 – CMD[1:0]ꢀCommand
This bit field triggers the client operation as the below. The CMD bits are strobe bits, and always read as zero.
The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to
STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a
command is given.
This bit is not enable-protected.
Table 28-3.ꢀCommand Description
CMD[1:0] DIR
Action
0x0
0x1
0x2
X
X
(No action)
(Reserved)
Used to complete a transaction in response to a data interrupt (DRDY)
0 (Host write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition
1 (Host read) Wait for any start (S/Sr) condition
DS40001882G-page 497
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SERCOM I2C – Inter-Integrated Circuit
...........continued
CMD[1:0] DIR
Action
0x3
Used in response to an address interrupt (AMATCH)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute acknowledge action succeeded by client data interrupt
Used in response to a data interrupt (DRDY)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute a byte read operation followed by ACK/NACK reception
Bits 15:14 – AMODE[1:0]ꢀAddress Mode
These bits set the addressing mode.
Value
Name
Description
0x0
MASK
The client responds to the address written in ADDR.ADDR masked by the value in
ADDR.ADDRMASK.
See SERCOM – Serial Communication Interface for additional information.
0x1
0x2
2_ADDRS The client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.
RANGE
The client responds to the range of addresses between and including ADDR.ADDR and
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
Reserved.
0x3
-
Bit 10 – AACKENꢀAutomatic Acknowledge Enable
This bit enables the address to be automatically acknowledged if there is an address match.
Value
Description
0
1
Automatic acknowledge is disabled.
Automatic acknowledge is enabled.
Bit 9 – GCMDꢀPMBus Group Command
This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC)
will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the
bus.
Value
Description
0
1
Group command is disabled.
Group command is enabled.
Bit 8 – SMENꢀSmart Mode Enable
When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.
Value
Description
0
1
Smart mode is disabled.
Smart mode is enabled.
Related Links
25. SERCOM – Serial Communication Interface
DS40001882G-page 498
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28.8.3 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
PREC
R/W
0
Access
Reset
0
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 2 – DRDYꢀData Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
Value
Description
0
1
The Data Ready interrupt is disabled.
The Data Ready interrupt is enabled.
Bit 1 – AMATCHꢀAddress Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt.
Value
Description
0
1
The Address Match interrupt is disabled.
The Address Match interrupt is enabled.
Bit 0 – PRECꢀStop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.
Value
Description
0
1
The Stop Received interrupt is disabled.
The Stop Received interrupt is enabled.
DS40001882G-page 499
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28.8.4 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x16
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
PREC
R/W
0
Access
Reset
0
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 2 – DRDYꢀData Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt.
Value
Description
0
1
The Data Ready interrupt is disabled.
The Data Ready interrupt is enabled.
Bit 1 – AMATCHꢀAddress Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.
Value
Description
0
1
The Address Match interrupt is disabled.
The Address Match interrupt is enabled.
Bit 0 – PRECꢀStop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt.
Value
Description
0
1
The Stop Received interrupt is disabled.
The Stop Received interrupt is enabled.
DS40001882G-page 500
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28.8.5 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00
-
Property:ꢀ
Bit
7
ERROR
R/W
0
6
5
4
3
2
DRDY
R/W
0
1
AMATCH
R/W
0
PREC
R/W
0
Access
Reset
0
Bit 7 – ERRORꢀError
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – DRDYꢀData Ready
This flag is set when a I2C client byte transmission or reception is successfully completed.
The flag is cleared by hardware when either:
•
•
•
Writing to the DATA register.
Reading the DATA register with Smart mode enabled.
Writing a valid command to the CMD register.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready Interrupt flag.
Bit 1 – AMATCHꢀAddress Match
This flag is set when the I2C client address match logic detects that a valid address has been received.
The flag is cleared by hardware when CTRL.CMD is written.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt flag. When cleared, an ACK/NACK will be sent according to
CTRLB.ACKACT.
Bit 0 – PRECꢀStop Received
This flag is set when a Stop condition is detected for a transaction being processed. A Stop condition detected
between a bus host and another client will not set this flag, unless the PMBus Group Command is enabled in the
Control B register (CTRLB.GCMD=1).
This flag is cleared by hardware after a command is issued on the next address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt flag.
DS40001882G-page 501
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28.8.6 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x1A
0x0000
-
Property:ꢀ
Bit
15
14
13
5
12
11
10
HS
R/W
0
9
SEXTTOUT
R/W
8
Access
Reset
0
Bit
7
6
4
SR
R
3
DIR
R
2
1
COLL
R/W
0
0
BUSERR
R/W
CLKHOLD
LOWTOUT
RXNACK
Access
Reset
R
0
R/W
0
R
0
0
0
0
Bit 10 – HSꢀHigh-speed
This bit is set if the client detects a START followed by a Host Code transmission.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
Bit 9 – SEXTTOUTꢀClient SCL Low Extend Time-Out
This bit is set if a client SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or
when INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
1
No SCL low extend time-out has occurred.
SCL low extend time-out has occurred.
Bit 7 – CLKHOLDꢀClock Hold
The client Clock Hold bit (STATUS.CLKHOLD) is set when the client is holding the SCL line low, stretching
the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or
INTFLAG.AMATCH is set.
This bit is automatically cleared when the corresponding interrupt is also cleared.
Bit 6 – LOWTOUTꢀSCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or
when INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
1
No SCL low time-out has occurred.
SCL low time-out has occurred.
Bit 4 – SRꢀRepeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
This flag is only valid while the INTFLAG.AMATCH flag is one.
Value
Description
0
1
Start condition on last address match
Repeated start condition on last address match
DS40001882G-page 502
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Bit 3 – DIRꢀRead / Write Direction
The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a host.
Value
Description
0
1
Host write operation is in progress.
Host read operation is in progress.
Bit 2 – RXNACKꢀReceived Not Acknowledge
This bit indicates whether the last data packet sent was acknowledged or not.
Value
Description
0
1
Host responded with ACK.
Host responded with NACK.
Bit 1 – COLLꢀTransmit Collision
If set, the I2C client was not able to transmit a high data or NACK bit, the I2C client will immediately release the SDA
and SCL lines and wait for the next packet addressed to it.
This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations
indicates that there has been a protocol violation, and should be treated as a bus error.
Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent
correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD), or INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
1
No collision detected on last data byte sent.
Collision detected on last data byte sent.
Bit 0 – BUSERRꢀBus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of
bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on
the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a
time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR.
This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD) or INTFLAG.AMATCH is cleared.
Writing a '1' to this bit will clear the status.
Writing a '0' to this bit has no effect.
Value
Description
0
1
No bus error detected.
Bus error detected.
DS40001882G-page 503
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28.8.7 Synchronization Busy
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SYNCBUSY
0x1C
0x00000000
-
Property:ꢀ
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
1
0
ENABLE
SWRST
Access
Reset
R
0
R
0
Bit 1 – ENABLEꢀSERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
1
Enable synchronization is not busy.
Enable synchronization is busy.
Bit 0 – SWRSTꢀSoftware Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
1
SWRST synchronization is not busy.
SWRST synchronization is busy.
DS40001882G-page 504
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28.8.8 Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x24
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
19
26
25
24
ADDRMASK[9:7]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
18
17
16
ADDRMASK[6:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
TENBITEN
R/W
14
13
12
11
10
9
ADDR[9:7]
R/W
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
7
6
5
4
ADDR[6:0]
R/W
3
2
1
0
GENCEN
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bits 26:17 – ADDRMASK[9:0]ꢀAddress Mask
These bits act as a second address match register, an address mask register or the lower limit of an address range,
depending on the CTRLB.AMODE setting.
Bit 15 – TENBITENꢀTen Bit Addressing Enable
Value
Description
0
1
10-bit address recognition disabled.
10-bit address recognition enabled.
Bits 10:1 – ADDR[9:0]ꢀAddress
These bits contain the I2C client address used by the client address match logic to determine if a host has addressed
the client.
When using 7-bit addressing, the client address is represented by ADDR[6:0].
When using 10-bit addressing (ADDR.TENBITEN=1), the client address is represented by ADDR[9:0]
When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate
whether it is a read or a write transaction.
Bit 0 – GENCENꢀGeneral Call Address Enable
A general call address is an address consisting of all-zeroes, including the direction bit (host write).
Value
Description
0
1
General call address recognition disabled.
General call address recognition enabled.
DS40001882G-page 505
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SERCOM I2C – Inter-Integrated Circuit
28.8.9 Data
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATA
0x28
0x0000
-
Property:ꢀ
Bit
15
7
14
13
5
12
4
11
3
10
2
9
1
8
0
Access
Reset
Bit
6
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0]ꢀData
The client data register I/O location (DATA.DATA) provides access to the host transmit and receive data buffers.
Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the client
(STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been
received.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
DS40001882G-page 506
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28.9
Register Summary - I2C Host
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
15:8
0x00
0x04
CTRLA
23:16
31:24
7:0
SEXTTOEN MEXTTOEN
LOWTOUTEN
SDAHOLD[1:0]
INACTOUT[1:0]
PINOUT
SCLSM
SPEED[1:0]
15:8
QCEN
SMEN
CTRLB
Reserved
BAUD
23:16
31:24
ACKACT
CMD[1:0]
0x08
...
0x0B
7:0
BAUD[7:0]
15:8
BAUDLOW[7:0]
HSBAUD[7:0]
0x0C
23:16
31:24
HSBAUDLOW[7:0]
0x10
...
Reserved
0x13
0x14
0x15
0x16
0x17
0x18
0x19
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
7:0
7:0
7:0
ERROR
ERROR
ERROR
SB
SB
MB
MB
SB
MB
7:0
15:8
7:0
CLKHOLD
LOWTOUT
BUSSTATE[1:0]
RXNACK
LENERR
SYSOP
ARBLOST
BUSERR
0x1A
STATUS
SEXTTOUT MEXTTOUT
ENABLE
SWRST
15:8
23:16
31:24
0x1C
SYNCBUSY
0x20
...
Reserved
0x23
7:0
15:8
23:16
31:24
7:0
ADDR[7:0]
LEN[7:0]
TENBITEN
HS
LENEN
ADDR[10:8]
0x24
ADDR
DATA
DATA[7:0]
0x28
15:8
0x2A
...
Reserved
0x2F
0x30
DBGCTRL
7:0
DBGSTOP
28.10 Register Description - I2C Host
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 28.5.8 Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
28.6.6 Synchronization.
DS40001882G-page 507
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Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 508
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28.10.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
SCLSM
R/W
0
26
18
10
2
25
24
LOWTOUTEN
INACTOUT[1:0]
SPEED[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
SEXTTOEN
R/W
22
MEXTTOEN
R/W
21
20
19
17
16
SDAHOLD[1:0]
PINOUT
R/W
0
Access
Reset
R/W
0
R/W
0
0
0
Bit
15
14
13
5
12
11
9
8
Access
Reset
Bit
7
6
4
3
MODE[2:0]
R/W
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
Bit 30 – LOWTOUTENꢀSCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the host will release its clock hold, if
enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and
STATUS.BUSERR status bits will be set.
This bit is not synchronized.
Value
Description
0
1
Time-out disabled.
Time-out enabled.
Bits 29:28 – INACTOUT[1:0]ꢀInactive Time-Out
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic
will be set to idle. An inactive bus arise when either an I2C host or client is holding the SCL low.
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Calculated time-out periods are based on a 100kHz baud rate.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
55US
105US
205US
Description
Disabled
5-6 SCL cycle time-out (50-60µs)
10-11 SCL cycle time-out (100-110µs)
20-21 SCL cycle time-out (200-210µs)
Bit 27 – SCLSMꢀSCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
Value
Description
0
1
SCL stretch according to Figure 28-5.
SCL stretch only after ACK bit, Figure 28-6.
DS40001882G-page 509
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SERCOM I2C – Inter-Integrated Circuit
Bits 25:24 – SPEED[1:0]ꢀTransfer Speed
These bits define bus speed.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Description
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
Fast-mode Plus (Fm+) up to 1 MHz
High-speed mode (Hs-mode) up to 3.4 MHz
Reserved
Bit 23 – SEXTTOENꢀClient SCL Low Extend Time-Out
This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the
initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP
will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set.
This bit is not synchronized.
Value
Description
0
1
Time-out disabled
Time-out enabled
Bit 22 – MEXTTOENꢀHost SCL Low Extend Time-Out
This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from
START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will be set.
This bit is not synchronized.
Value
Description
0
1
Time-out disabled
Time-out enabled
Bits 21:20 – SDAHOLD[1:0]ꢀSDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
DIS
75NS
450NS
600NS
Description
Disabled
50-100ns hold time
300-600ns hold time
400-800ns hold time
Bit 16 – PINOUTꢀPin Usage
This bit set the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value
Description
0
1
4-wire operation disabled.
4-wire operation enabled.
Bit 7 – RUNSTDBYꢀRun in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value
0
1
Description
GCLK_SERCOMx_CORE is disabled and the I2C host will not operate in standby sleep mode.
GCLK_SERCOMx_CORE is enabled in all sleep modes.
Bits 4:2 – MODE[2:0]ꢀOperating Mode
These bits must be written to 0x5 to select the I2C host serial communication interface of the SERCOM.
These bits are not synchronized.
DS40001882G-page 510
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Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled.
The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is not enable-protected.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will
be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register
will return the reset value of the register.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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SERCOM I2C – Inter-Integrated Circuit
28.10.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
25
17
24
16
Access
Reset
Bit
18
ACKACT
R/W
CMD[1:0]
Access
Reset
W
0
W
0
0
Bit
10
9
QCEN
R/W
0
8
SMEN
R/W
0
Access
Reset
Bit
2
1
0
Access
Reset
Bit 18 – ACKACTꢀAcknowledge Action
This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The
acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled
(CTRLB.SMEN is written to one), when DATA.DATA is read.
This bit is not enable-protected.
This bit is not write-synchronized.
Value
0
1
Description
Send ACK.
Send NACK.
Bits 17:16 – CMD[1:0]ꢀCommand
Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as
zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in
a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and
then the acknowledge action will be updated before the command is triggered.
Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt
flag (INTFLAG.MB) is '1'.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in
ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a
repeated start followed by transmission of the new address.
Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).
Table 28-4.ꢀCommand Description
CMD[1:0]
Direction
Action
0x0
0x1
0x2
X
X
(No action)
Execute acknowledge action succeeded by repeated Start
No operation
Execute acknowledge action succeeded by a byte read operation
Execute acknowledge action succeeded by issuing a Stop condition
0 (Write)
1 (Read)
X
0x3
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These bits are not enable-protected.
Bit 9 – QCENꢀQuick Command Enable
This bit is not write-synchronized.
Value
Description
0
1
Quick Command is disabled.
Quick Command is enabled.
Bit 8 – SMENꢀSmart Mode Enable
When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
This bit is not write-synchronized.
Value
Description
0
1
Smart mode is disabled.
Smart mode is enabled.
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SERCOM I2C – Inter-Integrated Circuit
28.10.3 Baud Rate
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BAUD
0x0C
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
HSBAUDLOW[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
HSBAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
BAUDLOW[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:24 – HSBAUDLOW[7:0]ꢀHigh Speed Host Baud Rate Low
HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to
HSBAUDLOW = f ⋅ T − 1
GCLK LOW
HSBAUDLOW equal to zero: The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is
timed by the BAUD register.
Bits 23:16 – HSBAUD[7:0]ꢀHigh Speed Host Baud Rate
This bit field indicates the SCL high time in High-speed mode according to the following formula. When
HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by
the BAUD register.
HSBAUD = f
⋅ T
− 1
GCLK HIGH
Bits 15:8 – BAUDLOW[7:0]ꢀHost Baud Rate Low
If this bit field is non-zero, the SCL low time will be described by the value written.
For more information on how to calculate the frequency, see SERCOM 25.6.2.3 Clock Generation – Baud-Rate
Generator.
Bits 7:0 – BAUD[7:0]ꢀHost Baud Rate
This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD
will be used to generate both high and low periods of the SCL.
For more information on how to calculate the frequency, see SERCOM 25.6.2.3 Clock Generation – Baud-Rate
Generator.
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SERCOM I2C – Inter-Integrated Circuit
28.10.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 1 – SBꢀClient on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Client on Bus Interrupt Enable bit, which disables the Client on Bus interrupt.
Value
Description
0
1
The Client on Bus interrupt is disabled.
The Client on Bus interrupt is enabled.
Bit 0 – MBꢀHost on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Host on Bus Interrupt Enable bit, which disables the Host on Bus interrupt.
Value
Description
0
1
The Host on Bus interrupt is disabled.
The Host on Bus interrupt is enabled.
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28.10.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x16
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Access
Reset
Bit 7 – ERRORꢀError Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
Error interrupt is disabled.
Error interrupt is enabled.
Bit 1 – SBꢀClient on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.
Value
Description
0
1
The Client on Bus interrupt is disabled.
The Client on Bus interrupt is enabled.
Bit 0 – MBꢀHost on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.
Value
Description
0
1
The Host on Bus interrupt is disabled.
The Host on Bus interrupt is enabled.
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SERCOM I2C – Inter-Integrated Circuit
28.10.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00
-
Property:ꢀ
Bit
7
ERROR
R/W
0
6
5
4
3
2
1
SB
R/W
0
0
MB
R/W
0
Access
Reset
Bit 7 – ERRORꢀError
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS
register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 1 – SBꢀClient on Bus
The Client on Bus flag (SB) is set when a byte is successfully received in Host Read mode, for example, no
arbitration lost or bus error occurred during the operation. When this flag is set, the host forces the SCL line low,
stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions:
•
•
•
•
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the
above actions is performed.
Writing '0' to this bit has no effect.
Bit 0 – MBꢀHost on Bus
This flag is set when a byte is transmitted in Host Write mode. The flag is set regardless of the occurrence of a bus
error or an Arbitration Lost condition. MB is also set when arbitration is lost during sending of NACK in Host Read
mode, or when issuing a Start condition if the bus state is unknown. When this flag is set and arbitration is not lost,
the host forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared
on one of the following actions:
•
•
•
•
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when Smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the
above actions is performed.
Writing '0' to this bit has no effect.
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SERCOM I2C – Inter-Integrated Circuit
28.10.7 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x1A
0x0000
Property:ꢀ Write-Synchronized
Bit
15
14
13
5
12
4
11
3
10
LENERR
R/W
9
SEXTTOUT
R/W
8
MEXTTOUT
Access
Reset
R/W
0
0
0
Bit
7
6
LOWTOUT
R/W
2
1
ARBLOST
R/W
0
BUSERR
R/W
CLKHOLD
BUSSTATE[1:0]
RXNACK
Access
Reset
R
0
R/W
0
R/W
0
R
0
0
0
0
Bit 10 – LENERRꢀTransaction Length Error
This bit is set when automatic length is used for a DMA transaction and the client sends a NACK before ADDR.LEN
bytes have been written by the host.
Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR
register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 9 – SEXTTOUTꢀClient SCL Low Extend Time-Out
This bit is set if a client SCL low extend time-out occurs.
This bit is automatically cleared when writing to the ADDR register.
Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the SEXTTOUT
flag to be cleared by this method.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 8 – MEXTTOUTꢀHost SCL Low Extend Time-Out
This bit is set if a Host SCL low time-out occurs.
Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when writing to the
ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 7 – CLKHOLDꢀClock Hold
This bit is set when the host is holding the SCL line low, stretching the I2C clock. Software should consider this bit
when INTFLAG.SB or INTFLAG.MB is set.
This bit is cleared when the corresponding Interrupt flag is cleared and the next operation is given.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Bit 6 – LOWTOUTꢀSCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bits 5:4 – BUSSTATE[1:0]ꢀBus State
These bits indicate the current I2C Bus state.
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When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus state cannot
be forced into any other state.
Writing BUSSTATE to idle will set SYNCBUSY.SYSOP.
Value
0x0
Name
Description
UNKNOWN The Bus state is unknown to the I2C host and will wait for a Stop condition to be detected
or wait to be forced into an Idle state by software
0x1
0x2
0x3
IDLE
OWNER
BUSY
The Bus state is waiting for a transaction to be initialized
The I2C host is the current owner of the bus
Some other I2C host owns the bus
Bit 2 – RXNACKꢀReceived Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Value
Description
0
1
Client responded with ACK.
Client responded with NACK.
Bit 1 – ARBLOSTꢀArbitration Lost
This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a Start or Repeated
Start condition on the bus. The Host on Bus Interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
This bit is not write-synchronized.
Bit 0 – BUSERRꢀBus Error
This bit indicates that an illegal Bus condition has occurred on the bus, regardless of bus ownership. An illegal Bus
condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A Start
condition directly followed by a Stop condition is one example of a protocol violation. If a time-out occurs during a
frame, this is also considered a protocol violation, and will set BUSERR.
If the I2C host is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in
addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
This bit is not write-synchronized.
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SERCOM I2C – Inter-Integrated Circuit
28.10.8 Synchronization Busy
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SYNCBUSY
0x1C
0x00000000
Bit
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
1
0
SYSOP
ENABLE
SWRST
Access
Reset
R
0
R
0
R
0
Bit 2 – SYSOPꢀSystem Operation Synchronization Busy
Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization.
When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete.
Value
Description
0
1
System operation synchronization is not busy.
System operation synchronization is busy.
Bit 1 – ENABLEꢀSERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Value
Description
0
1
Enable synchronization is not busy.
Enable synchronization is busy.
Bit 0 – SWRSTꢀSoftware Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will
be set until synchronization is complete.
Value
Description
0
1
SWRST synchronization is not busy.
SWRST synchronization is busy.
DS40001882G-page 520
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SERCOM I2C – Inter-Integrated Circuit
28.10.9 Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x24
0x0000
Property:ꢀ Write-Synchronized
Bit
31
30
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
LEN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
TENBITEN
R/W
14
HS
R/W
0
13
LENEN
R/W
0
12
11
10
9
ADDR[10:8]
R/W
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:16 – LEN[7:0]ꢀTransaction Length
These bits define the transaction length of a DMA transaction from 0 to 255 bytes. The Transfer Length Enable
(LENEN) bit must be written to '1' in order to use DMA.
Bit 15 – TENBITENꢀTen Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
Value
Description
0
1
10-bit addressing disabled.
10-bit addressing enabled.
Bit 14 – HSꢀHigh Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
Value
Description
0
1
High-speed transfer disabled.
High-speed transfer enabled.
Bit 13 – LENENꢀTransfer Length Enable
Value
Description
0
1
Automatic transfer length disabled.
Automatic transfer length enabled.
Bits 10:0 – ADDR[10:0]ꢀAddress
When ADDR is written, the consecutive operation will depend on the bus state:
UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
BUSY: The I2C host will await further operation until the bus becomes IDLE.
IDLE: The I2C host will issue a start condition followed by the address written in ADDR. If the address is
acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
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OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is
performed while INTFLAG.MB or INTFLAG.SB is set.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the host logic to perform any bus protocol related operations.
The I2C host control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for read.
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28.10.10 Data
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATA
0x28
0x0000
Property:ꢀ Write-Synchronized, Read-Synchronized (1)
Bit
15
7
14
6
13
12
11
3
10
2
9
1
8
0
Access
Reset
Bit
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0]ꢀData
The host data register I/O location (DATA) provides access to the host transmit and receive data buffers. Reading
valid data or writing data to be transmitted can be successfully done only when SCL is held low by the host
(STATUS.CLKHOLD is set). An exception is reading the last data byte after the stop condition has been sent.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Note:ꢀ
1. Writing DATA.DATA always requires synchronization.
Reading DATA.DATA only requires synchronization when Smart mode is enabled.
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SERCOM I2C – Inter-Integrated Circuit
28.10.11 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x30
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
R/W
Access
Reset
0
Bit 0 – DBGSTOPꢀDebug Stop Mode
This bit controls functionality when the CPU is halted by an external debugger.
Value
Description
0
1
The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
The baud-rate generator is halted when the CPU is halted by an external debugger.
DS40001882G-page 524
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I2S - Inter-IC Sound Controller
29.
I2S - Inter-IC Sound Controller
29.1
Overview
The Inter-IC Sound Controller (I2S) provides bidirectional, synchronous and digital audio link with external audio
devices.
This controller is compliant with the Inter-IC Sound (I2S) bus specification. It supports TDM interface with external
multi-slot audio codecs. It also supports Pulse Density Modulation (PDM) interface with external MEMS microphones.
The I2S consists of two Clock Units and two Serializers, that can be enabled separately, to provide Host, Client, or
controller modes, and operate as Receiver or Transmitter.
The pins associated with I2S peripheral are SDm, FSn, SCKn, and MCKn pins, where n=[0,1] denotes the Clock Unit
and m=[0,1] is the Serializers instance.
FSn is referred to as Word Select in standard I2S mode operation and as Frame Sync in TDM mode. Peripheral
DMAC channels, separate for each Serializer, allow a continuous high bitrate data transfer without processor
intervention to the following:
•
•
•
•
•
Audio codecs in Host, Client, or Controller mode
Stereo DAC or ADC through dedicated I2S serial interface
Multi-slot or multiple stereo DACs or ADCs, using the TDM format
Mono or stereo MEMS microphones, using the PDM interface
1-channel burst transfer with non-periodic Frame Sync
Each Serializer supports using either a single DMAC channel for all data channels, or two separate DMAC channels
for different data channels.
The I2S supports 8-bit and 16-bit compact stereo format. This helps in reducing the required DMA bandwidth by
transferring the left and right samples within the same data word.
Usually, an external audio codec or digital signal processor (DSP) requires a clock which is a multiple of the sampling
frequency fs (for example, 384×fs). The I2S peripheral in Host Mode and Controller mode is capable of outputting an
output clock ranging from 16×fs to 1024×fs on the Host Clock pin (MCKn).
29.2
Features
•
•
•
Compliant with Inter-IC Sound (I2S) bus specification
2 independent Serializers configurable as receiver or as transmitter
Supported data formats:
– 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
– 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data
transfers
•
Supported data frame formats:
– 2-channel I2S with Word Select
– 1- to 8-slot Time Division Multiplexed (TDM) with Frame Sync and individually enabled slots
– 1- or 2-channel Pulse Density Modulation (PDM) reception for MEMS microphones
– 1-channel burst transfer with non-periodic Frame Sync
•
•
2 independent Clock Units handling either the same clock or separate clocks for the Serializers:
– Suitable for a wide range of sample frequencies fs, including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and
192kHz
– 16×fs to 1024×fs Host Clock generated for external audio CODECs
Host, client, and controller modes:
– Host: Data received/transmitted based on internally-generated clocks. Output Serial Clock on SCKn pin,
Host Clock on MCKn pin, and Frame Sync Clock on FSn pin
DS40001882G-page 525
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I2S - Inter-IC Sound Controller
– Client: Data received/transmitted based on external clocks on Serial Clock pin (SCKn) or Host Clock pin
(MCKn)
– Controller: Only output internally generated Host clock (MCKn), Serial Clock (SCKn), and Frame Sync
Clock (FSn)
•
•
Individual enabling and disabling of Clock Units and Serializers
DMA interfaces for each Serializer receiver or transmitter to reduce processor overhead:
– Either one DMA channel for all data slots or
– One DMA channel per data channel in stereo
•
Smart Data Holding register management to avoid data slots mix after overrun or underrun
29.3
Block Diagram
Figure 29-1.ꢀI2S Block Diagram
29.4
Signal Description
Table 29-1.ꢀHost Mode
Pin Name
MCKn
SCKn
FSn
Pin Description
Type
Host Clock for Clock Unit n
Input/Output
Input/Output
Input/Output
Input/Output
Serial Clock for Clock Unit n
I2S Word Select or TDM Frame Sync for Clock Unit n
Serial Data Input or Output for Serializer m
SDm
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I2S - Inter-IC Sound Controller
Table 29-2.ꢀClient Mode
Pin Name
MCKn
SCKn
FSn
Pin Description
Type
Host Clock
Input
Serial Clock for Clock Unit n
I2S Word Select or TDM Frame Sync
Serial Data Input or Output for Serializer m
Input
Input
SDm
Input/Output
Table 29-3.ꢀController Mode
Pin Name
MCKn
SCKn
FSn
Pin Description
Type
Host Clock for Clock Unit n
Serial Clock for Clock Unit n
I2S Word Select or TDM Frame Sync
Not Applicable
Output
Output
Output
SDm
Not Applicable
Note:ꢀ One signal can be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
29.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
29.5.1 I/O Lines
Using the I2S I/O lines requires the I/O pins to be configured.
The I2S pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller to assign the
desired I2S pins to their peripheral function. If the I2S I/O lines are not used by the application, they can be used for
other purposes by the I/O Controller. It is required to enable only the I2S inputs and outputs actually in use.
Related Links
23. PORT - I/O Pin Controller
29.5.2 Power Management
The I2S will continue to operate in any sleep mode where the selected source clocks are running.
29.5.3 Clocks
The clock for the I2S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is disabled at
reset, and can be enabled in the Power Manager. It is recommended to disable the I2S before disabling the clock, to
avoid freezing the I2S in an undefined state.
There are two generic clocks, GCLK_I2S_0 and GCLK_I2S_1, connected to the I2S peripheral, one for each I2S
clock unit. The generic clocks (GCLK_I2S_n, n=0..1) can be set to a wide range of frequencies and clock sources.
The GCLK_I2S_n must be enabled and configured before use.
The GCLK_I2S_n clocks must be enabled and configured before triggering Software Reset, so that the logic in all
clock domains can be reset.
The generic clocks are only used in Host mode and Controller mode. In Host mode, the clock from a single clock unit
can be used for both Serializers to handle synchronous transfers, or a separate clock from different clock units can
be used for each Serializer to handle transfers on non-related clocks.
Related Links
15. GCLK - Generic Clock Controller
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I2S - Inter-IC Sound Controller
29.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the I2S DMA requests requires the DMA
Controller to be configured first.
Related Links
20. DMAC – Direct Memory Access Controller
29.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using I2S interrupts requires the interrupt controller
to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
29.5.6 Events
Not applicable.
29.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging.
29.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
DATAm
INTFLAG
SYNCBUSY
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
29.5.9 Analog Connections
Not applicable.
29.6
Functional Description
29.6.1 Principle of Operation
The I2S uses three or four communication lines for synchronous data transfer:
•
•
•
•
SDm for receiving or transmitting in Serializer m (m=0..1)
SCKn for the serial clock in Clock Unit n (n=0..1)
FSn for the frame synchronization or I2S word select, identifying the beginning of each frame
Optionally, MCKn to output an oversampling clock to an external codec
I2S data transfer is frame based, where a serial frame:
•
•
Starts with the frame synchronization active edge, and
Consists of 1 to 8 data slots, that are 8-, 16-, 24-, or 32-bit wide.
Each data slot is used to transfer one data sample of 8, 16, 18, 20, 24 or 32 bits.
Frame based data transfer is described in the following figure:
DS40001882G-page 528
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I2S - Inter-IC Sound Controller
Figure 29-2.ꢀData Format: Frames, Slot, Bits and Clocks
I2S supports multiple data formats such as:
•
•
32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data
transfers
In mono format, Transmit mode, data written to the left channel is duplicated to the right output channel. In mono
format, Receiver mode, data received from the right channel is ignored and data received from the left channel is
duplicated in to the right channel.
In mono format, TDM Transmit mode with more than two slots, data written to the even-numbered slots is duplicated
in to the following odd-numbered slot.
In mono format, TDM Receiver mode with more than two slots, data received from the even-numbered slots is
duplicated in to the following odd-numbered slot.
Mono format can be enabled by writing a '1' to the MONO bit in the Serializer m Control register
(SERCTRLm.MONO).
I2S support different data frame formats:
•
•
•
•
2-channel I2S with Word Select
1- to 8-slot Time Division Multiplexed (TDM) with Frame Sync and individually enabled slots
1- or 2-channel Pulse Density Modulation (PDM) reception for MEMS microphones
1-channel burst transfer with non-periodic Frame Sync
In 2 channel I2S mode, number of slots configured is one or two and successive data words corresponds to left and
right channel. Left and right channel are identified by polarity of Word Select signal (FSn signal). Each frame consists
of one or two data word(s). In the case of compact stereo format, the number of slots can be one. When 32-bit slot
size is used, the number of slots can be two.
In TDM format, number slots can be configured up to 8 slots. If 4 slots are configured, each frame consists of 4 data
words.
In PDM format, continuous 1-bit data samples are available on the SDI line for each SCKn rising and SCKn falling
edge as in case of a MEMS microphone with PDM interface.
DS40001882G-page 529
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I2S - Inter-IC Sound Controller
1-channel burst transfer with non-periodic Frame Sync mode is useful typically for passing control non-auto data as in
case of DSP. In Burst mode, a single Data transfer starts at each Frame Sync pulse, and these pulses are 1-bit wide
and occur only when a Data transfer is requested.
Sections 29.6.4 I2S Format - Reception and Transmission Sequence with Word Select, 29.6.5 TDM Format -
Reception and Transmission Sequence and 29.7 I2S Application Examples describe more about frame/data formats
and register settings required for different I2S applications.
Figure 29-3.ꢀI2S Functional Block Diagram
29.6.1.1 Initialization
The I2S features two Clock Units, and two Serializers configurable as Receiver or Transmitter. The two Serializers
can either share the same Clock Unit or use separate Clock Units.
Before enabling the I2S, the following registers must be configured:
•
•
Clock Control registers (CLKCTRLn)
Serializer Control registers (SERCTRLm)
In Host mode, one of the generic clocks for the I2S must also be configured to operate at the required frequency, as
described in 29.6.1 Principle of Operation.
•
•
•
•
fs is the sampling frequency that defines the frame period
CLKCTRLn.NBSLOTS defines the number of slots in each frame
CLKCTRLn.SLOTSIZE defines the number of bits in each slot
SCKn frequency must be fSCKn = fs × number_of_slots × number_of_bits_per_slot)
Once the configuration has been written, the I2S Clock Units and Serializers can be enabled by writing a '1' to the
CKENn and SERENm bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled
alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if
Serializers are enabled.
The Clock Units and the Serializers can be disabled independently by writing a '0' to CTRLA.CKENn or
CTRLA.SERENm, respectively. Once requested to stop, they will only stop when the pending transmit frames will be
completed, if any. When requested to stop, the ongoing reception of the current slot will be completed and then the
Serializer will be stopped.
Example 29-1.ꢀExample Requirements: fs=48kHz, MCKn=384×fs
If a 384×fs MCKn Host Clock is required (i.e. 18.432 MHz), the I2S generic clock could
run at 18.432 MHz with a Host Clock Output Division Factor of 1 (selected by writing
CLKCTRLn.MCKOUTDIV=0x0) in order to obtain the desired MCKn frequency.
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When using 6 slots per frame (CLKCTRLn.NBSLOTS=0x5) and 32-bit slots
(CLKCTRLn.SLOTSIZE=0x3), the desired SCKn frequency is
fSCKn = 48 kHz × 6 × 32 = 9.216 MHz
This frequency can be achieved by dividing the I2S generic clock output of 18.432 MHz by factor 2:
Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and output the desired SCKn
frequency of 9.216 MHz to the SCKn pin.
If MCKn is not required, the generic clock could be set to 9.216 MHz and
CLKCTRLn.MCKDIV=0x0.
29.6.2 Basic Operation
The Receiver can be operated by reading the Data Holding register (DATAm), whenever the Receive Ready m bit in
the Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set. Successive values read from DATAm register
will correspond to the samples from the left and right audio channels. In TDM mode, the successive values read from
DATAm register correspond to the first slot to the last slot. For instance, if I2S is configured in TDM mode with 4 slots
in a frame, then successive values written to DATAm register correspond to first, second, third, and fourth slot. The
number of slots in TDM is configured in CLKCTRLn.NBSLOTS.
The Transmitter can be operated by writing to the Data Holding register (DATAm), whenever the Transmit Ready m
bit in the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set. Successive values written to DATAm
register should correspond to the samples from the left and right audio channels. In TDM mode, the successive
values written to DATAm register correspond to the first, second, third, slot to the last slot. The number of slots in
TDM is configured in CLKCTRLn.NBSLOTS.
The Receive Ready and Transmit Ready bits can be polled by reading the INTFLAG register.
The processor load can be reduced by enabling interrupt-driven operation. The RXRDYm and/or TXRDYm interrupt
requests can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable register (INTENSET). The
interrupt service routine associated to the I2S interrupt request will then be executed whenever Receive Ready or
Transmit Ready status bits are set.
The processor load can be reduced further by enabling DMA-driven operation. Then, the DMA channels support up
to four trigger sources from the I2S peripheral. These four trigger sources in DMAC channel are
•
•
•
•
I2S RX 0,
I2S RX 1,
I2S TX 0, and
I2S TX 1.
For further reference, these are called I2S_DMAC_ID_RX_m and I2S_DMAC_ID_TX_m triggers (m=0..1). By using
these trigger sources, one DMA data transfer will be executed whenever the Receive Ready or Transmit Ready
status bits are set.
29.6.2.1 Host Clock, Serial Clock, and Frame Sync Generation
The generation of clocks in the I2S is described in the next figure.
DS40001882G-page 531
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I2S - Inter-IC Sound Controller
Figure 29-4.ꢀI2S Clocks
Generation
29.6.2.1.1 Client Mode
In Client mode, the Serial Clock and Frame Sync (Word Select in I2S mode and Frame Sync in TDM mode) are
driven by an external host. SCKn and FSn pins are inputs and no generic clock is required by the I2S.
29.6.2.1.2 Host Mode and Controller Mode
In Host Mode, the Host Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are generated by
the I2S controller. The user can configure the Host Clock, Serial Clock, and Word Select Frame Sync signal (Word
Select in I2S mode and Frame Sync in TDM mode) using the Clock Unit n Control register (CLKCTRLn). MCKn,
SCKn, and FSn pins are outputs and a generic clock is used to derive the I2S clocks.
In some applications, audio CODECs connected to the I2S pins may require a Host Clock signal with a frequency
multiple of the audio sample frequency fs, such as 256×fs.
In Controller mode, only the Clock generation unit needs to be configured by writing to the CTRLA and CLKCTRLn
registers, where parameters such as clock division factors, Number of slots, Slot size, Frame Sync signal, clock
enable are selected.
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29.6.2.1.3 MCKn Clock Frequency
When the I2S is in Host mode, writing a '1' to CLKCTRLn.MCKEN will output GCLK_I2S_n as Host
Clock to the MCKn pin. The Host Clock to MCKn pin can be divided by writing to CLKCTRLn.MCKSEL
and CLKCTRLn.MCKOUTDIV. The Host Clock (MCKn) frequency is GCLK_I2S_n frequency divided by
(MCLKOUTDIV+1).
f GCLK_I2S_n
f MCKn =
MCKOUTDIV+1
29.6.2.1.4 SCKn Clock Frequency
When the Serial Clock (SCKn) is generated from GCLK_I2S_n and both CLKCTRLn.MCKSEL and
CLKCTRLn.SCKSEL are zero, the Serial Clock (SCKn) frequency is GCLK_I2S_n frequency divided by (MCKDIV+1).
i.e.
f GCLK_I2S_n
f SCKn =
MCKDIV+1
29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs
Based on sampling frequency fs, the SCKn frequency requirement can be calculated:
f
= fs × total_number_of_bits_per_frame
,
•
•
SCKn frequency:
SCKn
Where total_number_of_bits_per_frame = number_of_slots × number_of_bits_per_slots.
•
The number of slots is selected by writing to the Number of Slots in Frame bit field in the Clock Unit n Control
(CLKCTRLn) register: number_of_slots = NBSLOTS + 1.
•
•
The number of bits per slot (8, 16, 24, or 32 bit) is selected by writing to the Slot Size bit field in CLKCTRLn: .
Consequently, f
= 8 × fs × NBSLOTS + 1 × SLOTSIZE + 1 .
SCKn
The clock frequencies f
and f
are derived from the generic clock frequency f
:
SCKn
MCKn
GCLK_I2S_n
f
= f
×
CLKCTRLn.MCKDIV + 1
GCLK_I2S_n
SCKn
•
= 8 × fs × NBSLOTS + 1 × SLOTSIZE + 1 × MCKDIV + 1
, and
f
= f
× MCKOUTDIV + 1
.
MCKn
•
GCLK_I2S_n
Substituting the right hand sides of the two last equations yields:
f
GCLK_I2S_n
f
=
=
MCKn
MCKn
MCKOUTDIV+1
8 ⋅ SLOTSIZE+1 ⋅ NBSLOTS+1 ⋅ MCKDIV+1
f
MCKOUTDIV+1
If a Host Clock output is not required, the GCLK_I2S generic clock can be configured as SCKn by writing a '0'to
CLKCTRLn.MCKDIV. Alternatively, if the frequency of the generic clock is a multiple of the required SCKn frequency,
the MCKn-to-SCKn divider can be used with the ratio defined by writing the CLKCTRLn.MCKDIV field.
The FSn pin is used as Word Select in I2S format and as Frame Synchronization in TDM format, as described in
29.6.4 I2S Format - Reception and Transmission Sequence with Word Select and 29.6.5 TDM Format - Reception
and Transmission Sequence, respectively.
29.6.2.2 Data Holding Registers
For each Serializer m, the I2S user interface includes a Data m register (DATAm). They are used to access data
samples for all data slots.
29.6.2.2.1 Data Reception Mode
In receiver mode, the DATAm registers store the received data.
When a new data word is available in the DATAm register, the Receive Ready bit (RXRDYm) in the Interrupt Flag
Status and Clear register (INTFLAG) is set. Reading the DATAm register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous data word has been
read from the DATAm register. Then, the Receive Overrun bit in INTFLAG will be set (INTFLAG.RXORm). This
interrupt can be cleared by writing a '1' to it.
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29.6.2.2.2 Data Transmission Mode
In Transmitter mode, the DATAm registers contain the data to be transmitted.
when DATAm is empty, the Transmit Ready bit in the Interrupt Flag Status and Clear register is set
(INTFLAG.TXRDYm). Writing to DATAm will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to DATAm.
Then, the Transmit Underrun bit in INTFLAG will be set (INTFLAG.TXURm). This interrupt can be cleared by writing
a '1' to it. The Transmit Data when Underrun bit in the Serializer n Control register (SERCTRLm.TXSAME) configures
whether a zero data word is transmitted in case of underrun (SERCTRLm.TXSAME=0), or the previous data word for
the current transmit slot number is transmitted again (SERCTRLm.TXSAME=1).
29.6.3 Host, Controller, and Client Modes
In Host and Controller modes, the I2S provides the Serial Clock, a Word Select/Frame Sync signal and optionally a
Host Clock.
In Controller mode, the I2S Serializers are disabled. Only the clocks are enabled and output for external receivers
and/or transmitters.
In Client mode, the I2S receives the Serial Clock and the Word Select/Frame Sync Signal from an external host.
SCKn and FSn pins are inputs.
29.6.4 I2S Format - Reception and Transmission Sequence with Word Select
As specified in the I2S protocol, data bits are left-adjusted in the Word Select slot, with the MSB transmitted first,
starting one clock period after the transition on the Word Select line.
Figure 29-5.ꢀI2S Reception and Transmission Sequence
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The
Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right
channel.
In I2S format, typical configurations are described below. These configurations do not list all necessary settings,
but only basic ones. Other configuration settings are to be done as per requirement such as clock and DMA
configurations.
Case 1: I2S 16-bit compact stereo
•
•
•
•
•
Slot size configured as 16 bits (CLKCTRL0.SLOTSIZE = 0x1)
Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
Data size configured as 16-bit compact stereo (SERCTRL0.DATASIZE = 0x05)
Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01)
Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)
Case 2: I2S 24-bit stereo Transmitterwith 24-bit slot
•
•
•
•
Slot size configured as 24 bits (CLKCTRL0.SLOTSIZE = 0x2)
Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)
Data size configured as 24 bits (SERCTRL0.DATASIZE = 0x01)
Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01)
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•
Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)
In both cases, it will ensure that Word select signal is 'low level' for the left channel and 'high level' for the right
channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the Data Word Size bit
group in the Serializer Control mregister (SERCTRLm.DATASIZE).
If the slot allows for more data bits than the number of bits specified in the respective DATASIZE field, additional
bits are appended to the transmitted or received data word as specified in the SERCTRLm.EXTEND field. If the slot
allows less data bits than programmed, the extra bits are not transmitted, or received data word is extended based on
the EXTEND field value.
29.6.5 TDM Format - Reception and Transmission Sequence
In Time Division Multiplexed (TDM) format, the number of data slots sent or received within each frame will be
(CLKCTRLn.NBSLOTS + 1).
By configuring the CLKCTRLn register (CLKCTRLn.FSWIDTH and CLKCTRLn.FSINV), the Frame Sync pulse width
and polarity can be modified.
By configuring SERCTRLm, data bits can be left-adjusted or right-adjusted in the slot. It can also configure the
data transmission/reception with either the MSB or the LSB transmitted/received first and starting the transmission/
reception either at the transition of the FSn pin or one clock period after.
Figure 29-6.ꢀTDM Format Reception and Transmission Sequence
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The FSn
pin provides a frame synchronization signal, at the beginning of slot 0. The delay between the frame start and the first
data bit is defined by writing the CLKCTRLn.BITDELAY field.
The Frame Sync pulse can be either one SCKn period (BIT), one slot (SLOT), or one half frame (HALF). This
selection is done by writing the CLKCTRLn.FSWIDTH field.
The number of slots is selected by writing the CLKCTRLn.NBSLOTS field.
The number of bits in each slot is selected by writing the CLKCTRLn.SLOTSIZE field.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the DATASIZE field in
the Serializer Control register (SERCTRLm).
If the slot allows more data bits than the number of bits specified in the SERCTRLmDATASIZE bit field, additional bits
are appended to the transmitted or received data word as specified in the SERCTRLmEXTEND bit field. If the slot
allows less data bits than programmed, the extra bits are not transmitted, or received data word is extended based on
the EXTEND field value.
29.6.6 PDM Reception
In Pulse Density Modulation (PDM) reception mode, continuous 1-bit data samples are available on the SDI line on
each SCKn rising edge, for example, by a MEMS microphone with PDM interface. When using two channel PDM
microphones, the second one (right channel) is configured to output data on each SCKn falling edge.
For one PDM microphone, the I2S controller must be configured in normal Receive mode with one slot and 16-bit or
32-bit data size, so that 16 or 32 samples of the microphone are stored into each data word.
For two PDM microphones, the I2S controller must be configured in PDM2 mode with one slot and 32-bit data size.
The Serializer will store 16 samples of each microphone in one half of the data word, with left microphone bits in
lower half and right microphone bits in upper half, like in compact stereo format.
Based on oversampling frequency requirement from PDM microphone, the SCKn frequency must be configured in
the I2S controller.
DS40001882G-page 535
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
A microphone that requires a sampling frequency of fs = 48 kHz and an oversampling frequency of
fo=64 × fs would require an SCKn frequency of 3.072 MHz.
After selecting a proper frequency for GCLK_I2S_n and according Host Clock Division Factor in the Clock Unit n
Control register (CLKCTRLn.MCKDIV), SCKn must be selected as per required frequency.
In PDM mode, only the clock and data line (SCKn and SDIn) pins are used.
To configure PDM2 mode, set SLOTSIZE = 0x01 (16-bits), NBSLOTS = 0x01 (2 slots) and SERCTRL0.DATASIZE =
0x00 (32-bit).
29.6.7 Data Formatting Unit
To allow more flexibility, data words received by Serializer m will be formatted by the Receive Formatting Unit before
being stored into the Data Holding register (RXDATA). The data words written into TXDATA register will be formatted
by the Transmit Formatting Unit before transmission by Serializer m .
The formatting options are defined in SERCTRLm:
•
•
•
•
SLOTADJ for left or right justification in the slot
BITREV for bit reversal
WORDADJ for left or right justification in the data word
EXTEND for extension to the word size
29.6.8 DMA, Interrupts and Events
Table 29-4.ꢀModule Request for I2S
Condition
DMA request DMA request is cleared
Interrupt
request
Event input/
output
Receive Ready
YES
When data is read
YES
YES
YES
YES
Transmit Ready (Buffer empty) YES
Receive Overrun
When data is written
Transmit Underrun
29.6.8.1 DMA Operation
Each Serializer can be connected either to one single DMAC channel or to one DMAC channel per data slot in stereo
mode. This is selected by writing the SERCTRLm.DMA bit:
Table 29-5.ꢀI2C DMA Request Generation
SERCTRLm.DMA
Mode
Slot Parity
all
DMA Request Trigger
I2S_DMAC_ID_RX_m
I2S_DMAC_ID_TX_m
I2S_DMAC_ID_RX_0
I2S_DMAC_ID_RX_1
I2S_DMAC_ID_TX_0
I2S_DMAC_ID_TX_1
0
Receiver
Transmitter
Receiver
all
1
even
odd
Transmitter
even
odd
The DMAC reads from the DATAm register and writes to the DATAm register for all data slots, successively.
The DMAC transfers may use 32-, 16- or or 8-bit transactions according to the value of the SERCTRLm.DATASIZE
field. 8-bit compact stereo uses 16-bit and 16-bit compact stereo uses 32-bit transactions.
29.6.8.2 Interrupts
The I2S has the following interrupt sources:
DS40001882G-page 536
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I2S - Inter-IC Sound Controller
•
•
•
•
Receive Ready (RXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Receive Overrun (RXORm): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Transmit Ready (TXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Transmit Underrun (TXURm): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the I2S is reset. See INTFLAG register for details on how to
clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one
combined interrupt request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read
the INTFLAG register to determine which interrupt condition is present.
Note:ꢀ Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
29.6.8.3 Events
Not applicable.
29.6.9 Sleep Mode Operation
The I2S continues to operate in all sleep modes that still provide its clocks.
29.6.10 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is '1', a peripheral
bus error is generated.
The following bits are synchronized when written:
•
•
•
•
Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to '1' while
synchronization is in progress.
Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to '1' while synchronization is
in progress.
Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1' while
synchronization is in progress.
Serializer x Enable bits in the Control A register (CTRLA.SERENx). SYNCBUSY.SERENx is set to '1' while
synchronization is in progress.
The following registers require synchronization when read or written:
•
Data n registers (DATAn), Read-Synchronized when Serializer n is in Rx mode or Write-Synchronized when in
Tx mode. SYNCBUSY.DATAn is set to '1' while synchronization is in progress.
Synchronization is denoted by the Read-Synchronized or Write-Synchronized property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 537
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I2S - Inter-IC Sound Controller
29.6.11 Loop-Back Mode
For debugging purposes, the I2S can be configured to loop back the Transmitter to the Receiver. Writing a '1' to
the Loop-Back Test Mode bit in the Serializer m Control register (SERCTRLm.RXLOOP) configures SDm as input
and the remaining SD as output. Both SD will be connected internally, so the transmitted data is also received. For
instance, writing SERCTRL0.RXLOOP=1 will connect SD1 output to SD0 input, or writing SERCTRL1.RXLOOP=1
will connect SD0 output to SD1 input.
RXLOOP=1 will connect the Transmitter output of the other Serializer to the Receiver input of the current Serializer.
For the Loop-back Mode to work, the current Serializer must be configured as receiver and the other Serializer as
transmitter.
Writing SERCTRLm.RXLOOP=0 will restore normal behavior and connection between Serializer m and SDm pin
input.
As for other changes to the Serializer configuration, Serializer m must be disabled before writing the SERCTRLm
register to update SERCTRLm.RXLOOP.
29.7
I2S Application Examples
The I2S can support several serial communication modes used in audio or high-speed serial links. Some standard
applications are shown in the following figures.
Note:ꢀ The following examples are not a complete list of serial link applications supported by the I2S.
Figure 29-7.ꢀAudio Application Block Diagram
Serial Clock
SCKn
Word Select
EXTERNAL
I2S
FSn
I2S
RECEIVER
Serial Data Out
SDOm
Serial Clock
Word Select
Serial Data Out
MSB
LSB
MSB
Right Channel
Left Channel
DS40001882G-page 538
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
Figure 29-8.ꢀTime Slot Application Block Diagram
Host Clock
MCKn
Serial Clock
SCKn
EXTERNAL
AUDIO
CODEC
for First
Time Slot
Frame Sync
I2S
FSn
SDO
SDI
Serial Data Out
Serial Data In
EXTERNAL
AUDIO
CODEC
for Second
Time Slot
Serial Clock
Frame Sync
First Time Slot
Dstart
Second Time Slot
Dend
Serial Data Out
Serial Data In
Figure 29-9.ꢀCodec Application Block Diagram
Host Clock
MCKn
Serial Clock
SCKn
EXTERNAL
AUDIO
CODEC
Frame Sync
I2S
FSn
Serial Data Out
SDO
Serial Data In
SDI
Serial Clock
Frame Sync
Serial Data Out
Serial Data In
First Time Slot
Dstart
Dend
DS40001882G-page 539
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I2S - Inter-IC Sound Controller
Figure 29-10.ꢀPDM Microphones Application Block Diagram
MCKn
64 fs Serial Clock
SCKn
I2S
EXTERNAL PDM
MICROPHONE
for Left
FSn
Channel
Serial Data In
SDI
L/RSEL
VDD
EXTERNAL PDM
MICROPHONE
for Right
Channel
L/RSEL
GND
Serial Clock
Right Left Right Left Right Left Right Left Right
Serial Data In
DS40001882G-page 540
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I2S - Inter-IC Sound Controller
29.8
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
...
CTRLA
7:0
SEREN1
SEREN0
CKEN1
CKEN0
ENABLE
SWRST
Reserved
0x03
7:0
15:8
23:16
31:24
7:0
BITDELAY
FSWIDTH[1:0]
NBSLOTS[2:0]
FSINV
SLOTSIZE[1:0]
SCKSEL
SCKSEL
FSSEL
0x04
CLKCTRL0
MCKDIV[4:0]
MCKOUTINV SCKOUTINV FSOUTINV
BITDELAY FSWIDTH[1:0]
MCKEN
MCKSEL
MCKOUTDIV[4:0]
NBSLOTS[2:0]
SLOTSIZE[1:0]
15:8
23:16
31:24
7:0
FSINV
FSSEL
0x08
0x0C
CLKCTRL1
MCKDIV[4:0]
MCKEN
MCKSEL
MCKOUTINV SCKOUTINV FSOUTINV
MCKOUTDIV[4:0]
RXOR1
TXUR1
RXOR0
TXUR0
RXRDY1
TXRDY1
RXRDY0
TXRDY0
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
SYNCBUSY
Reserved
15:8
0x0E
...
0x0F
7:0
RXOR1
TXUR1
RXOR0
TXUR0
RXRDY1
TXRDY1
RXRDY0
TXRDY0
0x10
15:8
0x12
...
0x13
7:0
RXOR1
TXUR1
RXOR0
TXUR0
RXRDY1
TXRDY1
RXRDY0
TXRDY0
0x14
15:8
0x16
...
0x17
7:0
SEREN1
SEREN0
CKEN1
CKEN0
ENABLE
DATA1
SWRST
DATA0
0x18
15:8
0x1A
...
0x1F
7:0
SLOTADJ
BITREV
CLKSEL
EXTEND[1:0]
TXSAME
WORDADJ
SLOTDIS4
TXDEFAULT[1:0]
SERMODE[1:0]
15:8
DATASIZE[2:0]
SLOTDIS1
DMA
0x20
0x24
SERCTRL0
23:16
31:24
7:0
SLOTDIS7
SLOTDIS6
SLOTDIS5
SLOTDIS3
SLOTDIS2
RXLOOP
SLOTDIS0
MONO
SLOTADJ
BITREV
CLKSEL
TXSAME
WORDADJ
SLOTDIS4
TXDEFAULT[1:0]
SERMODE[1:0]
15:8
EXTEND[1:0]
DATASIZE[2:0]
SLOTDIS1
DMA
SERCTRL1
Reserved
DATA0
23:16
31:24
SLOTDIS7
SLOTDIS6
SLOTDIS5
SLOTDIS3
SLOTDIS2
RXLOOP
SLOTDIS0
MONO
0x28
...
0x2F
7:0
15:8
23:16
31:24
7:0
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
0x30
0x34
0x34
15:8
23:16
31:24
7:0
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
DATA1
15:8
23:16
31:24
DATA[15:8]
DATA[23:16]
DATA[31:24]
RXDATA
DS40001882G-page 541
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
29.9
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
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29.9.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
SEREN1
R/W
4
SEREN0
R/W
3
CKEN1
R/W
0
2
CKEN0
R/W
0
1
ENABLE
R/W
0
SWRST
R/W
0
Access
Reset
0
0
0
Bits 4, 5 – SERENx ꢀSerializer x Enable [x=1..0]
Writing a '0' to this bit will disable the Serializer x.
Writing a '1' to this bit will enable the Serializer x.
Value
Description
0
1
The Serializer x is disabled.
The Serializer x is enabled.
Bits 2, 3 – CKENx ꢀClock Unit x Enable [x=1..0]
Writing a '0' to this bit will disable the Clock Unit x.
Writing a '1' to this bit will enable the Clock Unit x.
Value
Description
0
1
The Clock Unit x is disabled.
The Clock Unit x is enabled.
Bit 1 – ENABLEꢀEnable
Writing a '0' to this bit will disable the module.
Writing a '1' to this bit will enable the module.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers to their initial state, and the peripheral will be disabled.
Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
The I2S generic clocks must be enabled before triggering Software Reset, hence the logic in all clock domains can be
reset.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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29.9.2 Clock Unit n Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CLKCTRLn
0x04 + n*0x04 [n=0..1]
0x00000000
Property:ꢀ Enable-Protected, PAC Write-Protection
Bit
31
30
29
FSOUTINV
R/W
28
27
26
25
24
MCKOUTINV SCKOUTINV
MCKOUTDIV[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
23
22
21
20
19
18
MCKEN
R/W
0
17
16
MCKSEL
R/W
MCKDIV[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
15
14
13
12
SCKSEL
R/W
11
FSINV
R/W
0
10
9
8
FSSEL
R/W
0
Access
Reset
0
Bit
7
BITDELAY
R/W
6
5
4
3
2
1
0
FSWIDTH[1:0]
NBSLOTS[2:0]
SLOTSIZE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 31 – MCKOUTINVꢀHost Clock Output Invert
Value
Description
0
The Host Clock n is output without inversion.
1
The Host Clock n is inverted before being output.
Bit 30 – SCKOUTINVꢀSerial Clock Output Invert
Value
Description
0
1
The Serial Clock n is output without inversion.
The Serial Clock n is inverted before being output.
Bit 29 – FSOUTINVꢀFrame Sync Output Invert
Value
Description
0
1
The Frame Sync n is output without inversion.
The Frame Sync n is inverted before being output.
Bits 28:24 – MCKOUTDIV[4:0]ꢀHost Clock Output Division Factor
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Host Clock n output.
Bits 23:19 – MCKDIV[4:0]ꢀHost Clock Division Factor
The Host Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.
Bit 18 – MCKENꢀHost Clock Enable
Value
Description
0
1
The Host Clock n division and output is disabled.
The Host Clock n division and output is enabled.
Bit 16 – MCKSELꢀHost Clock Select
This field selects the source of the Host Clock n.
DS40001882G-page 544
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I2S - Inter-IC Sound Controller
MCKSEL
Name
Description
0x0
0x1
GCLK
MCKPIN
GCLK_I2S_n is used as Host Clock n source
MCKn input pin is used as Host Clock n source
Bit 12 – SCKSELꢀSerial Clock Select
This field selects the source of the Serial Clock n.
SCKSEL
Name
Description
0x0
0x1
MCKDIV
SCKPIN
Divided Host Clock n is used as Serial Clock n source
SCKn input pin is used as Serial Clock n source
Bit 11 – FSINVꢀFrame Sync Invert
Value
Description
0
1
The Frame Sync n is used without inversion.
The Frame Sync n is inverted before being used.
Bit 8 – FSSELꢀFrame Sync Select
This field selects the source of the Frame Sync n.
FSSEL
Name
Description
0x0
0x1
SCKDIV
FSPIN
Divided Serial Clock n is used as Frame Sync n source
FSn input pin is used as Frame Sync n source
Bit 7 – BITDELAYꢀData Delay from Frame Sync
BITDELAY
Name
Description
0x0
0x1
LJ
I2S
Left Justified (0 Bit Delay)
I2S (1 Bit Delay)
Bits 6:5 – FSWIDTH[1:0]ꢀFrame Sync Width
This field selects the duration of the Frame Sync output pulses.
When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic Frame Sync
pulses and Data samples.
In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only
when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not supported in the Burst
mode.
FSWIDTH[1:0] Name Description
0x0
0x1
0x2
0x3
SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
HALF
BIT
Frame Sync Pulse is half a Frame wide
Frame Sync Pulse is 1 Bit wide
BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data
sample, only when Data transfer is requested
Bits 4:2 – NBSLOTS[2:0]ꢀNumber of Slots in Frame
Each Frame for Clock Unit n is composed of (NBSLOTS + 1) Slots.
Bits 1:0 – SLOTSIZE[1:0]ꢀSlot Size
Each Slot for Clock Unit n is composed of a number of bits specified by SLOTSIZE.
SLOTSIZE[1:0]
Name
Description
0x0
0x1
0x2
0x3
8
8-bit Slot for Clock Unit n
16-bit Slot for Clock Unit n
24-bit Slot for Clock Unit n
32-bit Slot for Clock Unit n
16
24
32
DS40001882G-page 545
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I2S - Inter-IC Sound Controller
29.9.3 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x0C
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
7
14
6
13
TXUR1
R/W
0
12
TXUR0
R/W
0
11
3
10
2
9
TXRDY1
R/W
8
TXRDY0
R/W
Access
Reset
0
0
Bit
5
RXOR1
R/W
0
4
RXOR0
R/W
0
1
RXRDY1
R/W
0
RXRDY0
R/W
Access
Reset
0
0
Bits 12, 13 – TXURx ꢀTransmit Underrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Underrun x Interrupt Enable bit, which disables the Transmit Underrun x
interrupt.
Value
Description
0
1
The Transmit Underrun x interrupt is disabled.
The Transmit Underrun x interrupt is enabled.
Bits 8, 9 – TXRDYx ꢀTransmit Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Ready x Interrupt Enable bit, which disables the Transmit Ready x
interrupt.
Value
Description
0
1
The Transmit Ready x interrupt is disabled.
The Transmit Ready x interrupt is enabled.
Bits 4, 5 – RXORx ꢀReceive Overrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Overrun x Interrupt Enable bit, which disables the Receive Overrun x
interrupt.
Value
Description
0
1
The Receive Overrun x interrupt is disabled.
The Receive Overrun x interrupt is enabled.
Bits 0, 1 – RXRDYx ꢀReceive Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive Ready x
interrupt.
Value
Description
0
1
The Receive Ready x interrupt is disabled.
The Receive Ready x interrupt is enabled.
DS40001882G-page 546
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I2S - Inter-IC Sound Controller
29.9.4 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x10
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
7
14
6
13
TXUR1
R/W
0
12
TXUR0
R/W
0
11
3
10
2
9
TXRDY1
R/W
8
TXRDY0
R/W
Access
Reset
0
0
Bit
5
RXOR1
R/W
0
4
RXOR0
R/W
0
1
RXRDY1
R/W
0
RXRDY0
R/W
Access
Reset
0
0
Bits 12, 13 – TXURx ꢀTransmit Underrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Transmit Underrun Interrupt Enable bit, which enables the Transmit Underrun
interrupt.
Value
Description
0
1
The Transmit Underrun interrupt is disabled.
The Transmit Underrun interrupt is enabled.
Bits 8, 9 – TXRDYx ꢀTransmit Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Transmit Ready Interrupt Enable bit, which enables the Transmit Ready interrupt.
Value
Description
0
1
The Transmit Ready interrupt is disabled.
The Transmit Ready interrupt is enabled.
Bits 4, 5 – RXORx ꢀReceive Overrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Receive Overrun Interrupt Enable bit, which enables the Receive Overrun interrupt.
Value
Description
0
1
The Receive Overrun interrupt is disabled.
The Receive Overrun interrupt is enabled.
Bits 0, 1 – RXRDYx ꢀReceive Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Receive Ready Interrupt Enable bit, which enables the Receive Ready interrupt.
Value
Description
0
1
The Receive Ready interrupt is disabled.
The Receive Ready interrupt is enabled.
DS40001882G-page 547
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I2S - Inter-IC Sound Controller
29.9.5 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x14
0x0000
-
Property:ꢀ
Bit
15
7
14
6
13
TXUR1
R/W
0
12
TXUR0
R/W
0
11
3
10
2
9
TXRDY1
R/W
8
TXRDY0
R/W
Access
Reset
0
0
Bit
5
RXOR1
R/W
0
4
RXOR0
R/W
0
1
RXRDY1
R/W
0
RXRDY0
R/W
Access
Reset
0
0
Bits 12, 13 – TXURx ꢀTransmit Underrun x [x=1..0]
This flag is cleared by writing a '1' to it.
This flag is set when a Transmit Underrun condition occurs in Sequencer x, and will generate an interrupt request if
INTENCLR/SET.TXURx is set to '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Underrun x interrupt flag.
Bits 8, 9 – TXRDYx ꢀTransmit Ready x [x=1..0]
This flag is cleared by writing to DATAx register or writing a '1' to it.
This flag is set when Sequencer x is ready to accept a new data word to be transmitted, and will generate an interrupt
request if INTENCLR/SET.TXRDYx is set to '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Ready x interrupt flag.
Bits 4, 5 – RXORx ꢀReceive Overrun x [x=1..0]
This flag is cleared by writing a '1' to it.
This flag is set when a Receive Overrun condition occurs in Sequencer x, and will generate an interrupt request if
INTENCLR/SET.RXORx is set to '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Overrun x interrupt flag.
Bits 0, 1 – RXRDYx ꢀReceive Ready x [x=1..0]
This flag is cleared by reading from DATAx register or writing a '1' to it.
This flag is set when a Sequencer x has received a new data word, and will generate an interrupt request if
INTENCLR/SET.RXRDYx is set to '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Ready x interrupt flag.
DS40001882G-page 548
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
29.9.6 Synchronization Busy
Name:ꢀ
SYNCBUSY
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x18
0x0000
-
Bit
15
7
14
13
12
11
10
9
8
DATA1
DATA0
Access
Reset
R
0
R
0
Bit
6
5
4
3
2
1
0
SEREN1
SEREN0
CKEN1
CKEN0
ENABLE
SWRST
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bits 8, 9 – DATAx ꢀData x Synchronization Status [x=1..0]
Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is
complete.
Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains is started.
Bits 4, 5 – SERENx ꢀSerializer x Enable Synchronization Status [x=1..0]
Bit SERENx is cleared when the synchronization of the CTRLA.SERENx bit between the clock domains is complete.
Bit SERENx is set when the synchronization of the CTRLA.SERENx bit between the clock domains is started.
Bits 2, 3 – CKENx ꢀClock Unit x Enable Synchronization Status [x=1..0]
Bit CKENx is cleared when the synchronization of the CTRLA.CKENx bit between the clock domains is complete.
Bit CKENx is set when the synchronization of the CTRLA.CKENx bit between the clock domains is started.
Bit 1 – ENABLEꢀEnable Synchronization Status
This bit is cleared when the synchronization of the CTRLA.ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.ENABLE bit between the clock domains is started.
Bit 0 – SWRSTꢀSoftware Reset Synchronization Status
This bit is cleared when the synchronization of the CTRLA.SWRST bit between the clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST bit between the clock domains is started.
DS40001882G-page 549
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
29.9.7 Serializer n Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SERCTRLn
0x20 + n*0x04 [n=0..1]
0x00000000
Property:ꢀ Enable-Protected, PAC Write-Protection
Bit
31
30
29
28
27
26
RXLOOP
R/W
25
DMA
R/W
0
24
MONO
R/W
0
Access
Reset
0
Bit
23
SLOTDIS7
R/W
22
SLOTDIS6
R/W
21
SLOTDIS5
R/W
20
SLOTDIS4
R/W
19
SLOTDIS3
R/W
18
SLOTDIS2
R/W
17
SLOTDIS1
R/W
16
SLOTDIS0
R/W
Access
Reset
0
0
0
0
0
0
0
0
Bit
15
BITREV
R/W
0
14
13
12
WORDADJ
R/W
11
10
9
8
EXTEND[1:0]
DATASIZE[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
SLOTADJ
R/W
6
5
CLKSEL
R/W
0
4
TXSAME
R/W
3
2
1
0
TXDEFAULT[1:0]
SERMODE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit 26 – RXLOOPꢀLoop-back Test Mode
This bit enables a loop-back test mode:
Value
0
Description
Each Receiver uses its SDn pin as input (default mode).
1
Receiver uses as input the transmitter output of the other Serializer in the pair: e.g. SD1 for SD0 or
SD0 for SD1.
Bit 25 – DMAꢀSingle or Multiple DMA Channels
This bit selects whether even- and odd-numbered slots use separate DMA channels or the same DMA channel.
DMA
Name
Description
0x0
0x1
SINGLE
MULTIPLE
Single DMA channel
One DMA channel per data channel
Bit 24 – MONOꢀMono Mode.
MONO
Name
Description
0x0
0x1
STEREO
MONO
Normal mode
Left channel data is duplicated to right channel
Bits 16, 17, 18, 19, 20, 21, 22, 23 – SLOTDISx ꢀSlot x Disabled for this Serializer [x=7..0]
This field allows disabling some slots in each transmit frame:
Value
Description
0
Slot x is used for data transfer.
1
Slot x is not used for data transfer and will be output as specified in the TXDEFAULT field.
Bit 15 – BITREVꢀData Formatting Bit Reverse
This bit allows changing the order of data bits in the word in the Formatting Unit.
DS40001882G-page 550
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
BITREV
Name
Description
0x0
0x1
MSBIT
LSBIT
Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
Transfer Data Least Significant Bit (LSB) first
Bits 14:13 – EXTEND[1:0]ꢀData Formatting Bit Extension
This field defines the bit value used to extend data samples in the Formatting Unit.
EXTEND[1:0]
Name
Description
0x0
0x1
0x2
0x3
ZERO
ONE
MSBIT
LSBIT
Extend with zeros
Extend with ones
Extend with Most Significant Bit
Extend with Least Significant Bit
Bit 12 – WORDADJꢀData Word Formatting Adjust
This field defines left or right adjustment of data samples in the word in the Formatting Unit. for details.
WORDADJ
Name
Description
0x0
0x1
RIGHT
LEFT
Data is right adjusted in word
Data is left adjusted in word
Bits 10:8 – DATASIZE[2:0]ꢀData Word Size
This field defines the number of bits in each data sample. For 8-bit compact stereo, two 8-bit data samples are
packed in bits 15 to 0 of the DATAm register. For 16-bit compact stereo, two 16-bit data samples are packed in bits
31 to 0 of the DATAm register.
DATASIZE[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
32
24
20
18
16
16C
8
32 bits
24 bits
20 bits
18 bits
16 bits
16 bits compact stereo
8 bits
8C
8 bits compact stereo
Bit 7 – SLOTADJꢀData Slot Formatting Adjust
This field defines left or right adjustment of data samples in the slot.
SLOTADJ
Name
Description
0x0
0x1
RIGHT
LEFT
Data is right adjusted in slot
Data is left adjusted in slot
Bit 5 – CLKSELꢀClock Unit Selection.
CLKSEL
Name
Description
0x0
0x1
CLK0
CLK1
Use Clock Unit 0
Use Clock Unit 1
Bit 4 – TXSAMEꢀTransmit Data when Underrun.
TXSAME
Name
Description
0x0
0x1
ZERO
SAME
Zero data transmitted in case of underrun
Last data transmitted in case of underrun
Bits 3:2 – TXDEFAULT[1:0]ꢀLine Default Line when Slot Disabled
This field defines the default value driven on the SDn output pin during all disabled Slots.
DS40001882G-page 551
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
TXDEFAULT[1:0]
Name
Description
0x0
0x1
0x2
0x3
ZERO
ONE
Output Default Value is 0
Output Default Value is 1
Reserved
HIZ
Output Default Value is high impedance
Bits 1:0 – SERMODE[1:0]ꢀSerializer Mode.
SERMODE[1:0]
Name
Description
0x0
0x1
0x2
0x3
RX
TX
PDM2
Receive
Transmit
Receive one PDM data on each serial clock edge
Reserved
DS40001882G-page 552
Complete Datasheet
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SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
29.9.8 Data Holding m
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATAm
0x30 + m*0x04 [m=0..1]
0x00000000
Property:ꢀ Read-Synchronized, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0]ꢀSample Data
This register is used to transfer data to or from Serializer n.
Data samples written to DATAn register will be sent to Serializer n for transmission, through the Transmit Formatting
Unit that will apply the formatting specified in the SERCTRLn register.
Data samples received by Serializer n will be available for reading from DATAn register, through the Receive
Formatting Unit, according to formatting information for Serializer n in the SERCTRLn register.
DS40001882G-page 553
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
I2S - Inter-IC Sound Controller
29.9.9 Rx Data
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
RXDATA
0x34
0x00000000
Property:ꢀ Read-Synchronized
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0]ꢀSample Data
This register is used to transfer data from the Rx Serializer.
Data samples received by Rx Serializer will be available for reading from RXDATA register, through the Receive
Formatting Unit, according to formatting information for Rx Serializer in the RXCTRL register.
DS40001882G-page 554
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.
TC – Timer/Counter
30.1
Overview
The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to
count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels,
can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform
waveform generation, such as frequency generation and pulse-width modulation (PWM).
30.2
Features
•
Selectable configuration
– Up to five 16-bit Timer/Counters (TC), each configurable as:
•
•
•
8-bit TC with two compare/capture channels
16-bit TC with two compare/capture channels
32-bit TC with two compare/capture channels, by using two TCs
•
•
Waveform generation
– Frequency generation
– Single-slope pulse-width modulation
Input capture
– Event capture
– Frequency capture
– Pulse-width capture
•
•
One input event
Interrupts/output events on:
– Counter overflow/underflow
– Compare match or capture
Internal prescaler
•
•
Can be used with DMA and to trigger DMA transactions
DS40001882G-page 555
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.3
Block Diagram
Figure 30-1.ꢀTimer/Counter Block Diagram
BASE COUNTER
PER
PRESCALER
count
OVF/UNF
(INT Req.)
COUNTER
COUNT
clear
load
CONTROL
LOGIC
direction
ERR
(INT Req.)
Top
=
Zero
= 0
Compare / Capture
CONTROL
LOGIC
WOx Out
WAVEFORM
GENERATION
CC0
match
MCx
=
(INT Req.)
30.4
Signal Description
Signal Name
Type
Description
Waveform output
WO[1:0]
Digital output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
DS40001882G-page 556
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
Related Links
7. I/O Multiplexing and Considerations
30.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
30.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT).
Related Links
23. PORT - I/O Pin Controller
30.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes.
Related Links
16. PM – Power Manager
30.5.3 Clocks
The TC bus clock (CLK_TCx_APB, where x represents the specific TC instance number) can be enabled and
disabled in the Power Manager, and the default state of CLK_TCx_APB can be found in the Peripheral Clock
Masking section in “PM – Power Manager”.
The different TC instances are paired, even and odd, starting from TC3, and use the same generic clock,
GCLK_TCx. This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx clocks.
This generic clock is asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to 30.6.6 Synchronization for further
details.
Related Links
16.6.2.6 Peripheral Clock Masking
30.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this
peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.
Related Links
20. DMAC – Direct Memory Access Controller
30.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
30.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
24. EVSYS – Event System
30.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be forced to
continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details.
DS40001882G-page 557
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
•
•
•
Interrupt Flag register (INTFLAG)
Status register (STATUS)
Read Request register (READREQ)
Count register (COUNT)
Period register (PER)
Compare/Capture Value registers (CCx)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
30.5.9 Analog Connections
Not applicable.
30.6
Functional Description
30.6.1 Principle of Operation
The following definitions are used throughout the documentation:
Table 30-1.ꢀTimer/Counter Definitions
Name
Description
TOP
The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in Waveform Output Operations.
ZERO
MAX
The counter is ZERO when it contains all zeroes
The counter reaches MAX when it contains all ones
UPDATE
The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
Timer
Counter
CC
The timer/counter clock control is handled by an internal source
The clock control is handled externally (e.g. counting external events)
For compare operations, the CC are referred to as “compare channels”
For capture operations, the CC are referred to as “capture channels.”
The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCx clock, which
may be divided by the prescaler.
The counter value is passed to the CCx where it can be either compared to user-defined values or captured.
The compare and capture registers (CCx) and counter register (COUNT) can be configured as 8-, 16- or 32-bit
registers, with according MAX values. Mode settings determine the maximum range of the counter.
In 8-bit mode, Period Value (PER) is also available. The counter range and the operating frequency determine the
maximum time resolution achievable with the TC peripheral.
The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the
TOP or ZERO value to determine whether the counter has reached that value. On a comparison match the TC can
request DMA transactions, or generate interrupts or events for the Event System. On a comparison match the TC can
request DMA transactions, or generate interrupts or events for the Event System.
DS40001882G-page 558
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SAM D21/DA1 Family
TC – Timer/Counter
In compare operation, the counter value is continuously compared to the values in the CCx registers. In case of a
match the TC can request DMA transactions, or generate interrupts or events for the Event System. In waveform
generator mode, these comparisons are used to set the waveform period or pulse width.
Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture
selectable edges from an internal event from Event System.
30.6.2 Basic Operation
30.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is disabled
(CTRLA.ENABLE =0):
•
Control A register (CTRLA), except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but
not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected"
property in the register description. The following bits are enable-protected:
•
Event Action bits in the Event Control register (EVCTRL.EVACT)
Before enabling the TC, the peripheral must be configured by the following steps:
1. Enable the TC bus clock (CLK_TCx_APB).
2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register (CTRLA.MODE). The
default mode is 16-bit.
3. Select one wave generation operation in the Waveform Generation Operation bit group in the Control A
register (CTRLA.WAVEGEN).
4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register
(CTRLA.PRESCALER).
– If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter
Synchronization bit group in the Control A register (CTRLA.PRESYNC).
5. Select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
6. If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter
Direction bit in the Control B register (CTRLBSET.DIR).
7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in
the Control C register (CTRLC.CPTEN).
8. If desired, enable inversion of the waveform output or IO pin input signal for individual channels via the
Waveform Output Invert Enable bit group in the Control C register (CTRLC.INVEN).
30.6.2.2 Enabling, Disabling and Resetting
The TC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disbled by
writing a zero to CTRLA.ENABLE.
The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer to the CTRLA register
for details.
The TC should be disabled before the TC is reset in order to avoid undefined behavior.
30.6.2.3 Prescaler Selection
The GCLK_TCx is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the
prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on
the next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register
description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
DS40001882G-page 559
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SAM D21/DA1 Family
TC – Timer/Counter
Note:ꢀ When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT.
Figure 30-2.ꢀPrescaler
PRESCALER
EVACT
GCLK_TC /
{1,2,4,8,64,256,1024}
GCLK_TC
Prescaler
CLK_TC_CNT
COUNT
EVENT
30.6.2.4 Counter Mode
The Counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default, the
counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:
•
COUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can
be used as the top value for waveform generation.
•
•
COUNT16: 16-bit is the default Counter mode. There is no dedicated Period register in this mode.
COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC4 is paired with TC5, and TC6 is
paired with TC7. TC3 does not support 32-bit resolution.
When paired, the TC peripherals are configured using the registers of the even-numbered TC (TC4 or TC6
respectively). The odd-numbered partner (TC5 or TC7 respectively) will act as client, and the Client bit in the Status
register (STATUS.SLAVE) will be set. The register values of a client will not reflect the registers of the 32-bit counter.
Writing to any of the Client registers will not affect the 32-bit counter. Normal access to the client COUNT and CCx
registers is not allowed.
30.6.2.5 Counter Operations
The counter can be set to count up or down. When the counter is counting up and the top value is reached, the
counter will wrap around to zero on the next clock cycle. When counting down, the counter will wrap around to the top
value when zero is reached. In one-shot mode, the counter will stop counting after a wraparound occurs.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero the counter
is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for each tick (clock or event)
until it reaches TOP or ZERO. When it is counting up and TOP is reached, the counter will be set to zero at the
next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF) will
be set. It is also possible to generate an event on overflow or underflow when the Overflow/Underflow Event Output
Enable bit in the Event Control register (EVCTRL.OVFEO) is one.
It is possible to change the counter value (by writing directly in the COUNT register) even when the counter is
running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on the counting direction
set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been written to it, or the TC has been
stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of
the counter can also be changed during normal operation. See also the figure below.
DS40001882G-page 560
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
Figure 30-3.ꢀCounter Operation
MAX
Direction Change
COUNT written
Period (T)
"reload" update
"clear" update
TOP
COUNT
ZERO
DIR
30.6.2.5.1 Stop Command and Event Action
A Stop command can be issued from software by using Command bits in the Control B Set register
(CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will retain its
current value. All waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP).
30.6.2.5.2 Re-Trigger Command and Event Action
A re-trigger command can be issued from software by writing the Command bits in the Control B Set register
(CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event
Control register (EVCTRL.EVACT = 0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the
counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command is detected while the counter
is stopped, the counter will resume counting from the current value in the COUNT register.
Note:ꢀ When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the
next incoming event and restart on corresponding following event.
30.6.2.5.3 Count Event Action
The TC can count events. When an event is received, the counter increases or decreases the value, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be selected by the Event Action
bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT).
30.6.2.5.4 Start Event Action
The TC can start counting operation on an event when previously stopped. In this configuration, the event has no
effect if the counter is already counting. When the peripheral is enabled, the counter operation starts when the event
is received or when a re-trigger software command is applied.
The Start TC on Event action can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT=0x3, START).
30.6.2.6 Compare Operations
By default, the Compare/Capture channel is configured for compare operations.
When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter value is
continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
30.6.2.6.1 Waveform Output Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform available on
the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register
(CTRLA.WAVEGEN).
2. Optionally invert the waveform output by writing the corresponding Waveform Output Invert Enable bit in the
Control C register (CTRLC.INVx).
DS40001882G-page 561
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
3. Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one
transition of CLK_TC_CNT (see the next figure). An interrupt/and or event can be generated on comparison match
when INTENSET.MCx=1 and/or EVCTRL.MCEOx=1.
There are four waveform configurations for the Waveform Generation Operation bit group in the Control A register
(CTRLA.WAVEGEN) . This will influence how the waveform is generated and impose restrictions on the top value.
The configurations are:
•
•
•
•
Normal frequency (NFRQ)
Match frequency (MFRQ)
Normal pulse-width modulation (NPWM)
Match pulse-width modulation (MPWM)
When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit counter
mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16-
and 32-bit counter mode, TOP is fixed to the maximum (MAX) value of the counter.
Related Links
23. PORT - I/O Pin Controller
30.6.2.6.2 Frequency Operation
Normal Frequency Generation (NFRQ)
For Normal Frequency Generation, the period time (T) is controlled by the period register (PER) for 8-bit counter
mode and MAX for 16- and 32-bit mode. The waveform generation output (WO[x]) is toggled on each compare match
between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (INTFLAG.MCx) will be
set.
Figure 30-4.ꢀNormal Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
"reload" update
"clear" update
"match"
TOP
CCx
COUNT
ZERO
WO[x]
Match Frequency Generation (MFRQ)
For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0]
toggles on each update condition.
DS40001882G-page 562
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
Figure 30-5.ꢀMatch Frequency Operation
Direction Change
COUNT Written
Period (T)
MAX
CC0
"reload" update
"clear" update
COUNT
ZERO
WO[0]
30.6.2.6.3 PWM Operation
Normal Pulse-Width Modulation Operation (NPWM)
NPWM uses single-slope PWM generation.
For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls the duty
cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between
the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When
down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on
compare match between COUNT and CCx register values.
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
log(TOP+1)
R
=
PWM_SS
log(2)
The PWM frequency (fPWM_SS) depends on TOP value and the peripheral clock frequency (fGCLK_TC), and can be
calculated by the following equation:
f
GCLK_TC
f
=
PWM_SS
N(TOP+1)
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Match Pulse-Width Modulation Operation (MPWM)
In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On every overflow/underflow, a
one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure).
Figure 30-6.ꢀMatch PWM Operation
CCx=Zero
CCx=TOP
Period(T)
"clear" update
" match"
MAX
CC0
COUNT
CC1
ZERO
WO[1]
The table below shows the update counter and overflow event/interrupt generation conditions in different operation
modes.
DS40001882G-page 563
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
Table 30-2.ꢀCounter Update and Overflow Event/interrupt Conditions in TC
Name
Operation
TOP
Update
Output Waveform
OVFIF/Event
On Match
Toggle
On Update
Up
Down
ZERO
ZERO
ZERO
ZERO
NFRQ
MFRQ
NPWM
MPWM
Normal Frequency
Match Frequency
Single-slope PWM
Single-slope PWM
PER
CC0
PER
CC0
TOP/ ZERO
TOP/ ZERO
TOP/ ZERO
TOP/ ZERO
Stable
Stable
TOP
TOP
TOP
TOP
Toggle
See description above.
Toggle Toggle
30.6.2.6.4 Changing the Top Value
The counter period is changed by writing a new TOP value to the Period register (PER or CC0, depending on the
waveform generation mode). If a new TOP value is written when the counter value is close to zero and counting
down, the counter can be reloaded with the previous TOP value, due to synchronization delays. Then, the counter
will count one extra cycle before the new TOP value is used.
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written
to TOP, COUNT will wrap before a compare match.
A counter wraparound can occur in any operation mode when up-counting without buffering, see the figure below.
Figure 30-7.ꢀChanging the Top value with Up-Counting Operation
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
Figure 30-8.ꢀChanging the Top Value with Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
DS40001882G-page 564
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SAM D21/DA1 Family
TC – Timer/Counter
30.6.2.7 Capture Operations
To enable and use capture operations, the event line into the TC must be enabled using the TC Event Input bit in
the Event Control register (EVCTRL.TCEI). The capture channels to be used must also be enabled in the Capture
Channel x Enable bit group in the Control C register (CTRLC.CPTENx) before capture can be performed.
To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control C register
(CTRLC.CAPTENx) must be written to '1'.
Note:ꢀ The RETRIGGER, COUNT and START event actions are available only on an event from the Event System.
30.6.2.7.1 Event Capture Action
The compare/capture channels can be used as input capture channels to capture events from the Event System and
give them a timestamp. The following figure shows four capture events for one capture channel.
Figure 30-9.ꢀInput Capture Timing
events
TOP
COUNT
ZERO
Capture 0
Capture 1
Capture 2
Capture 3
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
30.6.2.7.2 Period and Pulse-Width (PPW) Capture Action
The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure
the pulse width and period and to characterize the frequency f and duty cycle of an input signal:
1
T
t
p
f =
dutyCycle =
T
Selecting PWP (pulse-width, period) in the Event Action bit group in the Event Control register (EVCTRL.EVACT)
enables the TC to perform one capture action on the rising edge and the other one on the falling edge. The period
T will be captured into CC1 and the pulse width tp in CC0. EVCTRL.EVACT=PPW (period and pulse-width)offers
identical functionality, but will capture T into CC0 and tp into CC1.
The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select whether the
wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV=1, the wraparound will happen on
the falling edge.
To fully characterize the frequency and duty cycle of the input signal, activate capture on CC0 and CC1 by writing
0x3 to the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). When only one of these
measurements is required, the second channel can be used for other purposes.
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
DS40001882G-page 565
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
Figure 30-10.ꢀPWP Capture
Period (T)
Pulsewitdh (tp)
external signal
events
MAX
"capture"
COUNT
ZERO
CC0
CC1
CC0
CC1
30.6.3 Additional Features
30.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition.
When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is automatically set and the
waveform outputs are set to zero.
One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC will count
until an overflow or underflow occurs and stops counting operation. The one-shot operation can be restarted
by a re-trigger software command, a re-trigger event, or a start event. When the counter restarts its operation,
STATUS.STOP is automatically cleared.
30.6.4 DMA, Interrupts and Events
Table 30-3.ꢀModule Request for TC
Condition
Interrupt
request
Event output
YES
Event input
DMA request
YES
DMA request is
cleared
Overflow /
Underflow
YES
Cleared on next
clock cycle
Channel
Compare Match
or Capture
YES
YES
YES1
For compare
channel –
Cleared on next
clock cycle.
For capture
channel – cleared
when CCx
register is read
Capture Overflow YES
Error
Synchronization YES
Ready
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SAM D21/DA1 Family
TC – Timer/Counter
...........continued
Condition
Interrupt
request
Event output
Event input
DMA request
DMA request is
cleared
Start Counter
YES
YES
Retrigger
Counter
Increment /
Decrement
counter
YES
Simple Capture
Period Capture
YES
YES
YES
Pulse Width
Capture
Note: 1. Two DMA requests lines are available, one for each compare/capture channel.
30.6.4.1 DMA Operation
The TC can generate the following DMA requests:
•
Overflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The request is
cleared on next clock cycle.
•
Channel Match or Capture (MCx): for a compare channel, the request is set on each compare match detection
and cleared on next clock cycle. For a capture channel, the request is set when valid data is present in CCx
register, and cleared when CCx register is read.
When using the TC with the DMA OVF request, the new value will be transferred to the register after the update
condition. This means that the value is updated after the DMA and synchronization delay, and if the COUNT value
has reached the new value before PER or CCx is updated, a match will not happen.
When using the TC with the DMA MCx request and updating CCx with a value that is lower than the current COUNT
when down-counting, or higher than the current COUNT when up-counting, this value could cause a new compare
match before the counter overflows. This will trigger the next DMA transfer, update CCx again, and the previous
value is disregarded from the output signal WO[x].
30.6.4.2 Interrupts
The TC has the following interrupt sources:
•
•
•
•
Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
Capture Overflow Error (ERR)
Synchronization Ready (SYNCRDY)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset. on
how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
DS40001882G-page 567
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.6.4.3 Events
The TC can generate the following output events:
•
•
Overflow/Underflow (OVF)
Match or Capture (MC)
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output
event. The output event is disabled by writing EVCTRL.MCEOx=0.
One of the following event actions can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT):
•
•
•
•
•
Start TC (START)
Re-trigger TC (RETRIGGER)
Increment or decrement counter (depends on counter direction)
Count on event (COUNT)
Capture Period (PPW and PWP)
Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC.
Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous event inputs. For further
details on how configuring the asynchronous events, refer to EVSYS - Event System.
Related Links
24. EVSYS – Event System
30.6.5 Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from
any sleep mode or perform actions through the Event System.
30.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when written:
•
•
•
•
•
•
Control B Clear register (CTRLBCLR)
Control B Set register (CTRLBSET)
Control C register (CTRLC)
Count Value register (COUNT)
Period Value register (PER)
Compare/Capture Value registers (CCx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
•
•
•
•
•
•
Control B Clear register (CTRLBCLR)
Control B Set register (CTRLBSET)
Control C register (CTRLC)
Count Value register (COUNT)
Period Value register (PER)
Compare/Capture Value registers (CCx)
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
DS40001882G-page 568
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
Related Links
14.3 Register Synchronization
DS40001882G-page 569
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.7
Register Summary for 8-bit Registers
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
7:0
WAVEGEN[1:0]
PRESCSYNC[1:0]
MODE[1:0]
ENABLE
SWRST
0x00
0x02
CTRLA
RUNSTDBY
PRESCALER[2:0]
ADDR[4:0]
READREQ
15:8
7:0
RREQ
RCONT
0x04
0x05
0x06
0x07
0x08
0x09
CTRLBCLR
CTRLBSET
CTRLC
CMD[1:0]
CMD[1:0]
ONESHOT
ONESHOT
DIR
DIR
7:0
7:0
CPTEN1
CPTEN0
INVEN1
INVEN0
Reserved
DBGCTRL
Reserved
7:0
DBGRUN
7:0
15:8
7:0
7:0
7:0
7:0
7:0
TCEI
TCINV
EVACT[2:0]
0x0A
EVCTRL
MCEO1
MC1
MCEO0
MC0
OVFEO
OVF
0x0C
0x0D
0x0E
0x0F
0x10
0x11
...
INTENCLR
INTENSET
INTFLAG
STATUS
SYNCRDY
SYNCRDY
SYNCRDY
STOP
ERR
ERR
ERR
MC1
MC0
OVF
MC1
MC0
OVF
SYNCBUSY
COUNT
COUNT[7:0]
Reserved
PER
0x13
0x14
0x15
...
7:0
PER[7:0]
Reserved
0x17
0x18
0x19
CC0
CC1
7:0
7:0
CC[7:0]
CC[7:0]
30.8
Register Description for 8-bit Registers
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 30.5.8 Register Access Protection
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
30.6.6 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 570
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Write-Synchronized, Enable-Protected
Bit
15
7
14
13
PRESCSYNC[1:0]
R/W R/W
12
11
RUNSTDBY
R/W
10
9
8
PRESCALER[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
0
Bit
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
WAVEGEN[1:0]
MODE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 13:12 – PRESCSYNC[1:0]ꢀPrescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
-
Bit 11 – RUNSTDBYꢀRun in Standby
This bit is used to keep the TC running in Standby mode.
This bit is not synchronized.
Value
Description
0
1
The TC is halted in standby.
The TC continues to run in standby.
Bits 10:8 – PRESCALER[2:0]ꢀPrescaler
These bits select the counter prescaler factor.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bits 6:5 – WAVEGEN[1:0]ꢀWaveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output
Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes
differ can also be seen from “Waveform Output Operations”.
These bits are not synchronized.
DS40001882G-page 571
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
Table 30-4.ꢀWaveform Generation Operation
Value
Name
Operation
Top Value
Waveform
Output on
Match
Waveform
Output on
Wraparound
0x0
0x1
0x2
NFRQ
MFRQ
NPWM
Normal frequency PER(1)/Max
Match frequency CC0
Normal PWM
Toggle
Toggle
Clear when
counting up Set
when counting
down
No action
No action
Set when
counting up Clear
when counting
down
PER(1)/Max
0x3
MPWM
Match PWM
CC0
Clear when
counting up Set
when counting
down
Set when
counting up Clear
when counting
down
Note:ꢀ
1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and
32-bit mode it is the maximum value.
Bits 3:2 – MODE[1:0]ꢀTimer Counter Mode
These bits select the Counter mode.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
Description
COUNT16
COUNT8
COUNT32
-
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the
SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is
complete.
This bit is not enable protected.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 572
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.2 Read Request
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
READREQ
0x02
0x0000
Bit
15
14
13
5
12
4
11
3
10
9
1
8
0
RREQ
RCONT
R/W
0
Access
Reset
W
0
Bit
7
6
2
ADDR[4:0]
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 15 – RREQꢀRead Request
Writing a zero to this bit has no effect.
This bit will always read as zero.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
Bit 14 – RCONTꢀRead Continuously
When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will
be synchronized automatically every time the register is updated.
READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ
bit is required to be set once the RCONT bit is set.
Note:ꢀ Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled
for a maximum of 6 APB + 6 TC clock cycles (the time for the on-going read synchronization to complete).
Value
Description
0
1
Continuous synchronization is disabled.
Continuous synchronization is enabled.
Bits 4:0 – ADDR[4:0]ꢀAddress
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
DS40001882G-page 573
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.3 Control B Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBCLR
0x04
0x00
Property:ꢀ PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Table 30-5.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 574
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.4 Control B Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBSET
0x05
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to one of these bits will set a command.
Table 30-6.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will make the counter count down.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 575
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.5 Control C
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLC
0x06
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
Bit
7
6
5
CPTEN1
R/W
4
CPTEN0
R/W
3
2
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Access
Reset
0
0
Bits 4, 5 – CPTENxꢀCapture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bits 0, 1 – INVENxꢀWaveform Output x Inversion Enable
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
DS40001882G-page 576
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.6 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x08
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀDebug Run Mode
This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
1
The TC is halted when the device is halted in Debug mode.
The TC continues normal operation when the device is halted in Debug mode.
DS40001882G-page 577
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.7 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x0A
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
3
10
2
9
8
OVFEO
R/W
0
Access
Reset
Bit
5
TCEI
R/W
0
4
TCINV
R/W
0
1
EVACT[2:0]
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bits 12, 13 – MCEOxꢀMatch or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEOꢀOverflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
1
Overflow/Underflow event is disabled and will not be generated.
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEIꢀTC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
1
Incoming events are disabled.
Incoming events are enabled.
Bit 4 – TCINVꢀTC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
1
Input event source is not inverted.
Input event source is inverted.
Bits 2:0 – EVACT[2:0]ꢀEvent Action
These bits define the event action the TC will perform on an event.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
COUNT
START
-
PPW
PWP
-
Description
Event action disabled
Start, restart or retrigger TC on event
Count on event
Start TC on event
Reserved
Period captured in CC0, pulse width in CC1
Period captured in CC1, pulse width in CC0
Reserved
DS40001882G-page 578
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.8 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x0C
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 579
Complete Datasheet
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SAM D21/DA1 Family
TC – Timer/Counter
30.8.9 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x0D
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 580
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.10 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x0E
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or
Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x Interrupt flag
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
Interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error Interrupt flag.
Bit 0 – OVFꢀOverflow Interrupt Flag
This flag is set on the next CLK_TC_CNT cycle after an Overflow condition occurs, and will generate an interrupt
request if INTENCLR.OVF or INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow Interrupt flag.
DS40001882G-page 581
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.11 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0F
0x08
-
Property:ꢀ
Bit
7
6
5
4
3
STOP
R
2
1
0
SYNCBUSY
Access
Reset
R
0
1
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 3 – STOPꢀStop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
1
Counter is running.
Counter is stopped.
DS40001882G-page 582
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.12 Counter Value, 8-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x10
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – COUNT[7:0]ꢀ Counter Value
These bits contain the current counter value.
DS40001882G-page 583
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.13 Period Value, 8-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PER
0x14
0xFF
Property:ꢀ Write-Synchronized
Bit
7
6
5
4
3
2
1
0
PER[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Bits 7:0 – PER[7:0]ꢀPeriod Value
These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE
condition.
DS40001882G-page 584
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.8.14 Channel x Compare/Capture Value, 8-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CCx
0x18 + x*0x01 [x=0..1]
0x00
Property:ꢀ Write-Synchronized
Bit
7
6
5
4
3
2
1
0
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CC[7:0]ꢀChannel x Compare/Capture Value
These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (CTRLA.WAVEGEN), the CC0 register is used as a period register.
DS40001882G-page 585
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.9
Register Summary for 16-bit Registers
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
7:0
WAVEGEN[1:0]
PRESCSYNC[1:0]
MODE[1:0]
ENABLE
SWRST
0x00
0x02
CTRLA
RUNSTDBY
PRESCALER[2:0]
ADDR[4:0]
READREQ
15:8
7:0
RREQ
RCONT
0x04
0x05
0x06
0x07
0x08
0x09
CTRLBCLR
CTRLBSET
CTRLC
CMD[1:0]
CMD[1:0]
ONESHOT
ONESHOT
DIR
DIR
7:0
7:0
CPTEN1
CPTEN0
INVEN1
INVEN0
Reserved
DBGCTRL
Reserved
7:0
DBGRUN
7:0
15:8
7:0
TCEI
TCINV
EVACT[2:0]
0x0A
EVCTRL
MCEO1
MC1
MCEO0
MC0
OVFEO
OVF
0x0C
0x0D
0x0E
0x0F
INTENCLR
INTENSET
INTFLAG
STATUS
SYNCRDY
SYNCRDY
SYNCRDY
STOP
ERR
ERR
ERR
7:0
MC1
MC0
OVF
7:0
MC1
MC0
OVF
7:0
SYNCBUSY
7:0
COUNT[7:0]
0x10
COUNT
15:8
COUNT[15:8]
0x12
...
Reserved
0x17
7:0
15:8
7:0
CC[7:0]
CC[15:8]
CC[7:0]
0x18
0x1A
CC0
CC1
15:8
CC[15:8]
30.10 Register Description for 16-bit Registers
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 30.5.8 Register Access Protection
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
30.6.6 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 586
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Write-Synchronized, Enable-Protected
Bit
15
7
14
13
PRESCSYNC[1:0]
R/W R/W
12
11
RUNSTDBY
R/W
10
9
8
PRESCALER[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
0
Bit
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
WAVEGEN[1:0]
MODE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 13:12 – PRESCSYNC[1:0]ꢀPrescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
-
Bit 11 – RUNSTDBYꢀRun in Standby
This bit is used to keep the TC running in Standby mode.
This bit is not synchronized.
Value
Description
0
1
The TC is halted in standby.
The TC continues to run in standby.
Bits 10:8 – PRESCALER[2:0]ꢀPrescaler
These bits select the counter prescaler factor.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bits 6:5 – WAVEGEN[1:0]ꢀWaveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output
Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes
differ can also be seen from “Waveform Output Operations”.
These bits are not synchronized.
DS40001882G-page 587
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
Table 30-7.ꢀWaveform Generation Operation
Value
Name
Operation
Top Value
Waveform
Output on
Match
Waveform
Output on
Wraparound
0x0
0x1
0x2
NFRQ
MFRQ
NPWM
Normal frequency PER(1)/Max
Match frequency CC0
Normal PWM
Toggle
Toggle
Clear when
counting up Set
when counting
down
No action
No action
Set when
counting up Clear
when counting
down
PER(1)/Max
0x3
MPWM
Match PWM
CC0
Clear when
counting up Set
when counting
down
Set when
counting up Clear
when counting
down
Note:ꢀ
1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and
32-bit mode it is the maximum value.
Bits 3:2 – MODE[1:0]ꢀTimer Counter Mode
These bits select the Counter mode.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
Description
COUNT16
COUNT8
COUNT32
-
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the
SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is
complete.
This bit is not enable protected.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 588
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.2 Read Request
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
READREQ
0x02
0x0000
Bit
15
14
13
5
12
4
11
3
10
9
1
8
0
RREQ
RCONT
R/W
0
Access
Reset
W
0
Bit
7
6
2
ADDR[4:0]
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 15 – RREQꢀRead Request
Writing a zero to this bit has no effect.
This bit will always read as zero.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
Bit 14 – RCONTꢀRead Continuously
When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will
be synchronized automatically every time the register is updated.
READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ
bit is required to be set once the RCONT bit is set.
Note:ꢀ Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled
for a maximum of 6 APB + 6 TC clock cycles (the time for the on-going read synchronization to complete).
Value
Description
0
1
Continuous synchronization is disabled.
Continuous synchronization is enabled.
Bits 4:0 – ADDR[4:0]ꢀAddress
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
DS40001882G-page 589
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.3 Control B Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBCLR
0x04
0x00
Property:ꢀ PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Table 30-8.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 590
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.4 Control B Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBSET
0x05
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to one of these bits will set a command.
Table 30-9.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will make the counter count down.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 591
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.5 Control C
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLC
0x06
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
Bit
7
6
5
CPTEN1
R/W
4
CPTEN0
R/W
3
2
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Access
Reset
0
0
Bits 4, 5 – CPTENxꢀCapture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bits 0, 1 – INVENxꢀWaveform Output x Inversion Enable
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
DS40001882G-page 592
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.6 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x08
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀDebug Run Mode
This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
1
The TC is halted when the device is halted in Debug mode.
The TC continues normal operation when the device is halted in Debug mode.
DS40001882G-page 593
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.7 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x0A
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
3
10
2
9
8
OVFEO
R/W
0
Access
Reset
Bit
5
TCEI
R/W
0
4
TCINV
R/W
0
1
EVACT[2:0]
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bits 12, 13 – MCEOxꢀMatch or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEOꢀOverflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
1
Overflow/Underflow event is disabled and will not be generated.
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEIꢀTC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
1
Incoming events are disabled.
Incoming events are enabled.
Bit 4 – TCINVꢀTC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
1
Input event source is not inverted.
Input event source is inverted.
Bits 2:0 – EVACT[2:0]ꢀEvent Action
These bits define the event action the TC will perform on an event.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
COUNT
START
-
PPW
PWP
-
Description
Event action disabled
Start, restart or retrigger TC on event
Count on event
Start TC on event
Reserved
Period captured in CC0, pulse width in CC1
Period captured in CC1, pulse width in CC0
Reserved
DS40001882G-page 594
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.8 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x0C
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 595
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.9 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x0D
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 596
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.10 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x0E
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or
Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x Interrupt flag
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
Interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error Interrupt flag.
Bit 0 – OVFꢀOverflow Interrupt Flag
This flag is set on the next CLK_TC_CNT cycle after an Overflow condition occurs, and will generate an interrupt
request if INTENCLR.OVF or INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow Interrupt flag.
DS40001882G-page 597
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.11 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0F
0x08
-
Property:ꢀ
Bit
7
6
5
4
3
STOP
R
2
1
0
SYNCBUSY
Access
Reset
R
0
1
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 3 – STOPꢀStop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
1
Counter is running.
Counter is stopped.
DS40001882G-page 598
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.12 Counter Value, 16-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x10
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – COUNT[15:0]ꢀ Counter Value
These bits contain the current counter value.
DS40001882G-page 599
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.10.13 Channel x Compare/Capture Value, 16-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CCx
0x18 + x*0x02 [x=0..1]
0x0000
Property:ꢀ Write-Synchronized
Bit
15
14
13
12
11
10
9
8
CC[15:8]
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CC[15:0]ꢀChannel x Compare/Capture Value
These bits contain the compare/capture value in 16-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (CTRLA.WAVEGEN), the CC0 register is used as a period register.
DS40001882G-page 600
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.11 Register Summary for 32-bit Registers
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
7:0
WAVEGEN[1:0]
PRESCSYNC[1:0]
MODE[1:0]
ENABLE
SWRST
0x00
CTRLA
RUNSTDBY
PRESCALER[2:0]
ADDR[4:0]
0x02
READREQ
15:8
7:0
RREQ
RCONT
0x04
0x05
0x06
0x07
0x08
0x09
CTRLBCLR
CTRLBSET
CTRLC
CMD[1:0]
CMD[1:0]
ONESHOT
ONESHOT
DIR
DIR
7:0
7:0
CPTEN1
CPTEN0
INVEN1
INVEN0
Reserved
DBGCTRL
Reserved
7:0
DBGRUN
7:0
15:8
7:0
TCEI
TCINV
EVACT[2:0]
0x0A
EVCTRL
MCEO1
MC1
MCEO0
MC0
OVFEO
OVF
0x0C
0x0D
0x0E
0x0F
INTENCLR
INTENSET
INTFLAG
STATUS
SYNCRDY
SYNCRDY
SYNCRDY
STOP
ERR
ERR
ERR
7:0
MC1
MC0
OVF
7:0
MC1
MC0
OVF
7:0
SYNCBUSY
SLAVE
7:0
COUNT[7:0]
15:8
23:16
31:24
COUNT[15:8]
COUNT[23:16]
COUNT[31:24]
0x10
COUNT
Reserved
CC0
0x14
...
0x17
7:0
CC[7:0]
CC[15:8]
CC[23:16]
CC[31:24]
CC[7:0]
15:8
0x18
0x1C
23:16
31:24
7:0
15:8
CC[15:8]
CC[23:16]
CC[31:24]
CC1
23:16
31:24
30.12 Register Description for 32-bit Registers
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 30.5.8 Register Access Protection
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
30.6.6 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 601
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Write-Synchronized, Enable-Protected
Bit
15
7
14
13
PRESCSYNC[1:0]
R/W R/W
12
11
RUNSTDBY
R/W
10
9
8
PRESCALER[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
0
0
Bit
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
WAVEGEN[1:0]
MODE[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 13:12 – PRESCSYNC[1:0]ꢀPrescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next prescaled
GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
GCLK
PRESC
Description
Reload or reset the counter on next generic clock
Reload or reset the counter on next prescaler clock
RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
Reserved
-
Bit 11 – RUNSTDBYꢀRun in Standby
This bit is used to keep the TC running in Standby mode.
This bit is not synchronized.
Value
Description
0
1
The TC is halted in standby.
The TC continues to run in standby.
Bits 10:8 – PRESCALER[2:0]ꢀPrescaler
These bits select the counter prescaler factor.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TC
Prescaler: GCLK_TC/2
Prescaler: GCLK_TC/4
Prescaler: GCLK_TC/8
Prescaler: GCLK_TC/16
Prescaler: GCLK_TC/64
Prescaler: GCLK_TC/256
Prescaler: GCLK_TC/1024
Bits 6:5 – WAVEGEN[1:0]ꢀWaveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output
Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes
differ can also be seen from “Waveform Output Operations”.
These bits are not synchronized.
DS40001882G-page 602
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
Table 30-10.ꢀWaveform Generation Operation
Value
Name
Operation
Top Value
Waveform
Output on
Match
Waveform
Output on
Wraparound
0x0
0x1
0x2
NFRQ
MFRQ
NPWM
Normal frequency PER(1)/Max
Match frequency CC0
Normal PWM
Toggle
Toggle
Clear when
counting up Set
when counting
down
No action
No action
Set when
counting up Clear
when counting
down
PER(1)/Max
0x3
MPWM
Match PWM
CC0
Clear when
counting up Set
when counting
down
Set when
counting up Clear
when counting
down
Note:ꢀ
1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and
32-bit mode it is the maximum value.
Bits 3:2 – MODE[1:0]ꢀTimer Counter Mode
These bits select the Counter mode.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
Description
COUNT16
COUNT8
COUNT32
-
Counter in 16-bit mode
Counter in 8-bit mode
Counter in 32-bit mode
Reserved
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately, and the ENABLE Synchronization Busy bit in the
SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is
complete.
This bit is not enable protected.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable protected.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 603
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.2 Read Request
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
READREQ
0x02
0x0000
Bit
15
14
13
5
12
4
11
3
10
9
1
8
0
RREQ
RCONT
R/W
0
Access
Reset
W
0
Bit
7
6
2
ADDR[4:0]
R/W
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 15 – RREQꢀRead Request
Writing a zero to this bit has no effect.
This bit will always read as zero.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
Bit 14 – RCONTꢀRead Continuously
When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will
be synchronized automatically every time the register is updated.
READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous read mode, RREQ
bit is required to be set once the RCONT bit is set.
Note:ꢀ Once the continuous synchronization is enabled, the first write in the COUNT/CLOCK register will be stalled
for a maximum of 6 APB + 6 TC clock cycles (the time for the on-going read synchronization to complete).
Value
Description
0
1
Continuous synchronization is disabled.
Continuous synchronization is enabled.
Bits 4:0 – ADDR[4:0]ꢀAddress
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
DS40001882G-page 604
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.3 Control B Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBCLR
0x04
0x00
Property:ꢀ PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Table 30-11.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 605
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.4 Control B Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBSET
0x05
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Bit
7
6
5
4
3
2
ONESHOT
R/W
1
0
DIR
R/W
0
CMD[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – CMD[1:0]ꢀCommand
These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC
clock cycle. When a command has been executed, the CMD bit group will be read back as zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to one of these bits will set a command.
Table 30-12.ꢀCommand
Value
Name
Description
0x0
0x1
0x2
0x3
NONE
RETRIGGER
STOP
-
No action
Force a start, restart or retrigger
Force a stop
Reserved
Bit 2 – ONESHOTꢀOne-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will enable one-shot operation.
Value
Description
0
1
The TC will wrap around and continue counting on an Overflow/Underflow condition.
The TC will wrap around and stop on the next Underflow/Overflow condition.
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will make the counter count down.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 606
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.5 Control C
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLC
0x06
0x00
Property:ꢀ PAC Write-Protection, Read-synchronized, Write-Synchronized
Bit
7
6
5
CPTEN1
R/W
4
CPTEN0
R/W
3
2
1
INVEN1
R/W
0
0
INVEN0
R/W
0
Access
Reset
0
0
Bits 4, 5 – CPTENxꢀCapture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bits 0, 1 – INVENxꢀWaveform Output x Inversion Enable
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
DS40001882G-page 607
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.6 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x08
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀDebug Run Mode
This bit is not affected by a software Reset, and should not be changed by software while the TC is enabled.
Value
Description
0
1
The TC is halted when the device is halted in Debug mode.
The TC continues normal operation when the device is halted in Debug mode.
DS40001882G-page 608
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.7 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x0A
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
MCEO1
R/W
0
12
MCEO0
R/W
0
11
3
10
2
9
8
OVFEO
R/W
0
Access
Reset
Bit
5
TCEI
R/W
0
4
TCINV
R/W
0
1
EVACT[2:0]
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bits 12, 13 – MCEOxꢀMatch or Capture Channel x Event Output Enable [x = 1..0]
These bits enable the generation of an event for every match or capture on channel x.
Value
Description
0
Match/Capture event on channel x is disabled and will not be generated.
1
Match/Capture event on channel x is enabled and will be generated for every compare/capture.
Bit 8 – OVFEOꢀOverflow/Underflow Event Output Enable
This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter
overflows/underflows.
Value
Description
0
1
Overflow/Underflow event is disabled and will not be generated.
Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
Bit 5 – TCEIꢀTC Event Enable
This bit is used to enable asynchronous input events to the TC.
Value
Description
0
1
Incoming events are disabled.
Incoming events are enabled.
Bit 4 – TCINVꢀTC Inverted Event Input Polarity
This bit inverts the asynchronous input event source.
Value
Description
0
1
Input event source is not inverted.
Input event source is inverted.
Bits 2:0 – EVACT[2:0]ꢀEvent Action
These bits define the event action the TC will perform on an event.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
COUNT
START
-
PPW
PWP
-
Description
Event action disabled
Start, restart or retrigger TC on event
Count on event
Start TC on event
Reserved
Period captured in CC0, pulse width in CC1
Period captured in CC1, pulse width in CC0
Reserved
DS40001882G-page 609
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.8 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x0C
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 610
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.9 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x0D
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x Interrupt Enable [x = 1..0]
Writing a '0' to these bits has no effect.
Writing a '1' to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the
Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 611
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.10 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x0E
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
SYNCRDY
R/W
2
1
0
MC1
R/W
0
MC0
R/W
0
ERR
R/W
0
OVF
R/W
0
Access
Reset
0
Bits 4, 5 – MCxꢀMatch or Capture Channel x [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value. This
flag is set on the next CLK_TC_CNT cycle, and will generate an interrupt request if the corresponding Match or
Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is '1'.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x Interrupt flag
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the
Synchronization Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – ERRꢀError Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x
Interrupt flag is set, in which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error Interrupt flag.
Bit 0 – OVFꢀOverflow Interrupt Flag
This flag is set on the next CLK_TC_CNT cycle after an Overflow condition occurs, and will generate an interrupt
request if INTENCLR.OVF or INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow Interrupt flag.
DS40001882G-page 612
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.11 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0F
0x08
-
Property:ꢀ
Bit
7
6
5
4
3
STOP
R
2
1
0
SYNCBUSY
SLAVE
Access
Reset
R
0
R
0
1
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 4 – SLAVEꢀClient Status Flag
This bit is only available in 32-bit mode on the client TC (i.e., TC5 and/or TC7). The bit is set when the associated
host TC (TC4 and TC6, respectively) is set to run in 32-bit mode.
Bit 3 – STOPꢀStop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
Value
Description
0
1
Counter is running.
Counter is stopped.
DS40001882G-page 613
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.12 Counter Value, 32-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x10
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COUNT[31:0]ꢀ Counter Value
These bits contain the current counter value.
DS40001882G-page 614
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TC – Timer/Counter
30.12.13 Channel x Compare/Capture Value, 32-bit Mode
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CCx
0x18 + x*0x04 [x=0..1]
0x00000000
Property:ꢀ Write-Synchronized
Bit
31
30
29
28
27
26
25
24
CC[31:24]
CC[23:16]
CC[15:8]
CC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CC[31:0]ꢀChannel x Compare/Capture Value
These bits contain the compare/capture value in 32-bit TC mode. In Match frequency (MFRQ) or Match PWM
(MPWM) waveform operation (CTRLA.WAVEGEN), the CC0 register is used as a period register.
DS40001882G-page 615
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.
TCC – Timer/Counter for Control Applications
31.1
Overview
The device provides three instances of the Timer/Counter for Control applications (TCC) peripheral, TCC[2:0].
Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can
be set to count events or clock pulses. The counter together with the compare/capture channels can be configured
to time stamp input events, allowing capture of frequency and pulse-width. It can also perform waveform generation
such as frequency generation and pulse-width modulation.
Waveform extensions are featured for motor control, ballast, LED, H-bridge, power converters, and other types of
power control applications. They allow for low- and high-side output with optional dead-time insertion. Waveform
extensions can also generate a synchronized bit pattern across the waveform output pins. The fault options enable
fault protection for safe and deterministic handling, disabling and/or shut down of external drivers.
Figure 31-1 shows all features in TCC.
Note:ꢀ The TCC configurations, such as channel numbers and features, may be reduced for some of the TCC
instances.
Related Links
7.2.5 TCC Configurations
31.2
Features
•
•
•
•
Up to four compare/capture channels (CC) with:
– Double buffered period setting
– Double buffered compare or capture channel
– Circular buffer on period and compare channel registers
Waveform generation:
– Frequency generation
– Single-slope pulse-width modulation (PWM)
– Dual-slope pulse-width modulation with half-cycle reload capability
Input capture:
– Event capture
– Frequency capture
– Pulse-width capture
Waveform extensions:
– Configurable distribution of compare channels outputs across port pins
– Low- and high-side output with programmable dead-time insertion
– Waveform swap option with double buffer support
– Pattern generation with double buffer support
– Dithering support
•
Fault protection for safe disabling of drivers:
– Two recoverable fault sources
– Two non-recoverable fault sources
– Debugger can be source of non-recoverable fault
Input events:
•
•
– Two input events (EVx) for counter
– One input event (MCx) for each channel
Output events:
– Three output events (Count, Re-Trigger and Overflow) available for counter
DS40001882G-page 616
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
– One Compare Match/Input Capture event output for each channel
•
•
Interrupts:
– Overflow and Re-Trigger interrupt
– Compare Match/Input Capture interrupt
– Interrupt on fault detection
Can be used with DMA and can trigger DMA transactions
31.3
Block Diagram
Figure 31-1.ꢀTimer/Counter for Control Applications - Block Diagram
Base Counter
BV
PERB
PER
Prescaler
"count"
"clear"
"load"
(INT/Event/DMA Req.)
(INT Req.)
OVF
ERR
Counter
Control Logic
COUNT
"direction"
"TCCx_EV0" (TCE0)
"TCCx_EV1" (TCE1)
TOP
=
"TCCx_MCx" Event
System
BOTTOM
= 0
evtn"
WO[7]
WO[6]
WO[5]
WO[4]
WO[3]
WO[2]
WO[1]
WO[0]
Compare/Capture
(Unit x = {0,1,…,3})
"capture"
Control Logic
BV
CCBx
CCx
Waveform
Generation
"match"
=
MCx (INT/Event/DMA Req.)
31.4
Signal Description
Pin Name
Type
Description
TCCx/WO[0]
TCCx/WO[1]
…
Digital output
Compare channel 0 waveform output
Compare channel 1 waveform output
...
Digital output
...
TCCx/WO[WO_NUM-1]
Digital output
Compare channel n waveform output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
DS40001882G-page 617
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
31.5.1 I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT).
Related Links
23. PORT - I/O Pin Controller
31.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes.
31.5.3 Clocks
The TCC bus clocks (CLK_TCCx_APB) can be enabled and disabled in the Power Manager module. The default
state of CLK_TCCx_APB can be found in the Peripheral Clock Masking section (see the Related Links below).
A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the
generic clock controller before using the TCC. Note that TCC0 and TCC1 share a peripheral clock generator.
The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity,
writing certain registers will require synchronization between the clock domains. Refer to 31.6.6 Synchronization for
further details.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
31.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this
peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details.
Related Links
20. DMAC – Direct Memory Access Controller
31.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
31.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
24. EVSYS – Event System
31.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be forced to
continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details.
Refer to 31.8.8 DBGCTRL register for details.
31.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
DS40001882G-page 618
Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
•
•
•
•
•
•
•
Interrupt Flag register (INTFLAG)
Status register (STATUS)
Period and Period Buffer registers (PER, PERB)
Compare/Capture and Compare/Capture Buffer registers (CCx, CCBx)
Control Waveform register (WAVE)
Control Waveform Buffer register (WAVEB)
Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTB)
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
31.5.9 Analog Connections
Not applicable.
31.6
Functional Description
31.6.1 Principle of Operation
The following definitions are used throughout the documentation:
Table 31-1.ꢀTimer/Counter for Control Applications - Definitions
Name
Description
TOP
The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in 31.6.2.5.1 Waveform Output Generation Operations.
ZERO
MAX
The counter reaches ZERO when it contains all zeroes.
The counter reaches maximum when it contains all ones.
UPDATE
The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
Timer
Counter
CC
The timer/counter clock control is handled by an internal source.
The clock control is handled externally (e.g., counting external events).
For compare operations, the CC are referred to as "compare channels."
For capture operations, the CC are referred to as "capture channels."
Each TCC instance has up to four compare/capture channels (CCx).
The counter register (COUNT), period registers with buffer (PER and PERB), and compare and capture registers with
buffers (CCx and CCBx) are 16- or 24-bit registers, depending on each TCC instance. Each buffer register has a
buffer valid (BUFV) flag that indicates when the buffer contains a new value.
Under normal operation, the counter value is continuously compared to the TOP or ZERO value to determine
whether the counter has reached TOP or ZERO. In either case, the TCC can generate interrupt requests, request
DMA transactions, or generate events for the Event System. In waveform generator mode, these comparisons are
used to set the waveform period or pulse width.
A prescaled generic clock (GCLK_TCCx) and events from the event system can be used to control the counter. The
event system is also used as a source to the input capture.
The Recoverable Fault Unit enables event controlled waveforms by acting directly on the generated waveforms of
the TCC compare channels output. These events can restart, halt the timer/counter period, shorten the output pulse
active time, or disable waveform output as long as the fault condition is present. This can typically be used for current
sensing regulation, and zero-crossing and demagnetization re-triggering.
DS40001882G-page 619
Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
The MCE0 and MCE1 asynchronous event sources are shared with the Recoverable Fault Unit. Only asynchronous
events are used internally when fault unit extension is enabled. For further details on how to configure asynchronous
events routing, refer to EVSYS – Event System.
Recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches,
by using digital filtering, input blanking, and qualification options. See also 31.6.3.5 Recoverable Faults.
In order to support applications with different types of motor control, ballast, LED, H-bridge, power converter, and
other types of power switching applications, the following independent units are implemented in some of the TCC
instances as optional and successive units:
•
•
•
•
•
Recoverable faults and non-recoverable faults
Output matrix
Dead-time insertion
Swap
Pattern generation
See also Figure 31-1.
The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different
configurations, each optimized for different application types. The Dead-Time Insertion (DTI) unit splits the four lower
OTMX outputs into two non-overlapping signals: the non-inverted low side (LS) and inverted high side (HS) of the
waveform output with optional dead-time insertion between LS and HS switching. The SWAP unit can swap the LS
and HS pin outputs, and can be used for fast decay motor control.
The pattern generation unit can be used to generate synchronized waveforms with constant logic level on TCC
UPDATE conditions. This is useful for easy stepper motor and full bridge control.
The non-recoverable fault module enables event controlled fault protection by acting directly on the generated
waveforms of the timer/counter compare channel outputs. When a non-recoverable fault condition is detected, the
output waveforms are forced to a preconfigured value that is safe for the application. This is typically used for instant
and predictable shut down and disabling high current or voltage drives.
The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The events can be
optionally filtered. If the filter options are not used, the non-recoverable faults provide an immediate asynchronous
action on waveform output, even for cases where the clock is not present. For further details on how to configure
asynchronous events routing, refer to section EVSYS – Event System.
Related Links
24. EVSYS – Event System
31.6.2 Basic Operation
31.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TCC is
disabled(CTRLA.ENABLE=0):
•
Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
•
•
•
•
Recoverable Fault n Control registers (FCTRLA and FCTRLB)
Waveform Extension Control register (WEXCTRL)
Drive Control register (DRVCTRL)
Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1',
but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected”
property in the register description.
Before the TCC is enabled, it must be configured as outlined by the following steps:
1. Enable the TCC bus clock (CLK_TCCx_APB).
2. If Capture mode is required, enable the channel in capture mode by writing a '1' to the Capture Enable bit in
the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
DS40001882G-page 620
Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER).
2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC).
3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register
(CTRLBSET.DIR) to '1'.
4. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN).
5. Select the Waveform Output Polarity in the WAVE register (WAVE.POL).
6. The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit
group in the Driver register (DRVCTRL.INVEN).
31.6.2.2 Enabling, Disabling, and Resetting
The TCC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled
by writing a zero to CTRLA.ENABLE.
The TCC is reset by writing '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers
in the TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. Refer to Control A
(31.8.1 CTRLA) register for details.
The TCC should be disabled before the TCC is reset to avoid undefined behavior.
31.6.2.3 Prescaler Selection
The GCLK_TCCx clock is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output of the
prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on the
next GCLK_TCC clock pulse or the next prescaled clock pulse. For further details, refer to the Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) descriptions.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register
description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note:ꢀ When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TCC_COUNT.
Figure 31-2.ꢀPrescaler
PRESCALER
EVACT 0/1
GCLK_TCC
PRESCALER
GCLK_TCC /
{1,2,4,8,64,256,1024 }
COUNT
TCCx EV0/1
CLK_TCC_COUNT
31.6.2.4 Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC
clock input (CLK_TCC_COUNT). A counter clear or reload mark the end of current counter cycle and the start of a
new one.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If the bit is zero, it's counting
up and one if counting down.
The counter will count up or down for each tick (clock or event) until it reaches TOP or ZERO. When it's counting
up and TOP is reached, the counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in
the Interrupt Flag Status and Clear register (INTFLAG.OVF) will be set. When down-counting, the counter is reloaded
with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set.
INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow occurrence
(i.e. a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B register is set
(CTRLBSET.ONESHOT). The One-Shot feature is explained in the Additional Features section.
DS40001882G-page 621
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-3.ꢀCounter Operation
Direction Change
COUNT written
MAX
"reload" update
"clear" update
TOP
COUNT
ZERO
DIR
It is possible to change the counter value (by writing directly in the COUNT register) even when the counter
is running. The COUNT value will always be ZERO or TOP, depending on direction set by CTRLBSET.DIR or
CTRLBCLR.DIR, when starting the TCC, unless a different value has been written to it, or the TCC has been stopped
at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the
counter can also be changed during normal operation. See also Figure 31-3.
Stop Command
A stop command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD=0x2, STOP).
When a stop is detected while the counter is running, the counter will maintain its current value. If the waveform
generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and
Non- Recoverable State x Output Value bit in the Driver Control register (DRVCTRL.NREx and DRVCTRL.NRVx),
and the Stop bit in the Status register is set (STATUS.STOP).
Pause Event Action
A pause command can be issued when the stop event action is configured in the Input Event Action 1 bits in Event
Control register (EVCTRL.EVACT1=0x3, STOP).
When a pause is detected, the counter can stop immediatly maintaining its current value and all waveforms keep
their current state, as long as a start event action is detected: Input Event Action 0 bits in Event Control register
(EVCTRL.EVACT0=0x3, START).
Re-Trigger Command and Event Action
A re-trigger command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD=0x1, RETRIGGER), or from event when the re-trigger event action is configured in the Input
Event 0/1 Action bits in Event Control register (EVCTRL.EVACTn=0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on
the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). The Re-Trigger bit in the Interrupt Flag Status and Clear
register will be set (INTFLAG.TRG). It is also possible to generate an event by writing a '1' to the Re-Trigger Event
Output Enable bit in the Event Control register (EVCTRL.TRGEO). If the re-trigger command is detected when the
counter is stopped, the counter will resume counting operation from the value in COUNT.
Note:ꢀ
When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACTn=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on
the next incoming event and restart on corresponding following event.
Start Event Action
The start action can be selected in the Event Control register (EVCTRL.EVACT0=0x3, START) and can start the
counting operation when previously stopped. The event has no effect if the counter is already counting. When the
module is enabled, the counter operation starts when the event is received or when a re-trigger software command is
applied.
DS40001882G-page 622
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Note:ꢀ
When a start event action is configured in the Event Action bits in the Event Control register (EVCTRL.EVACT0=0x3,
START), enabling the counter will not start the counter. The counter will start on the next incoming event, but it will
not restart on subsequent events.
Count Event Action
The TCC can count events. When an event is received, the counter increases or decreases the value, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR).
The count event action is selected by the Event Action 0 bit group in the Event Control register
(EVCTRL.EVACT0=0x5, COUNT).
Direction Event Action
The direction event action can be selected in the Event Control register (EVCTRL.EVACT1=0x2, DIR). When this
event is used, the asynchronous event path specified in the event system must be configured or selected. The
direction event action can be used to control the direction of the counter operation, depending on external events
level. When received, the event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the
direction bit value is updated accordingly.
Increment Event Action
The increment event action can be selected in the Event Control register (EVCTRL.EVACT0=0x4, INC) and can
change the counter state when an event is received. When the TCE0 event (TCCx_EV0) is received, the counter
increments, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Decrement Event Action
The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1=0x4, DEC) and can
change the counter state when an event is received. When the TCE1 (TCCx_EV1) event is received, the counter
decrements, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Non-recoverable Fault Event Action
Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACTn=0x7, FAULT). When
received, the counter will be stopped and the output of the compare channels is overridden according to the
Driver Control register settings (DRVCTRL.NREx and DRVCTRL.NRVx). TCE0 and TCE1 must be configured as
asynchronous events.
Event Action Off
If the event action is disabled (EVCTRL.EVACTn=0x0, OFF), enabling the counter will also start the counter.
Related Links
31.6.3.1 One-Shot Operation
31.6.2.5 Compare Operations
By default, the Compare/Capture channel is configured for compare operations. To perform capture operations, it
must be re-configured.
When using the TCC with the Compare/Capture Value registers (CCx) for compare operations, the counter value is
continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
The Channel x Compare/Capture Buffer Value (CCBx) registers provide double buffer capability. The double
buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force
update command (CTRLBSET.CMD=0x3, UPDATE). For further details, refer to 31.6.2.6 Double Buffering. The
synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
31.6.2.5.1 Waveform Output Generation Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform available on
the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register
(WAVE.WAVEGEN).
2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in
the Driver Control register (DRVCTRL.INVENx).
DS40001882G-page 623
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
3. Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one
transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on
the same condition if Match/Capture occurs, i.e. INTENSET.MCx and/or EVCTRL.MCEOx is '1'. Both interrupt and
event can be generated simultaneously. The same condition generates a DMA request.
There are seven waveform configurations for the Waveform Generation Operation bit group in the Waveform register
(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The
configurations are:
•
•
•
•
•
•
•
Normal Frequency (NFRQ)
Match Frequency (MFRQ)
Normal Pulse-Width Modulation (NPWM)
Dual-slope, interrupt/event at TOP (DSTOP)
Dual-slope, interrupt/event at ZERO (DSBOTTOM)
Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform
operations, the TOP value is defined by the Period (PER) register value.
For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other
waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.
The table below shows the update counter and overflow event/interrupt generation conditions in different operation
modes.
Table 31-2.ꢀCounter Update and Overflow Event/interrupt Conditions
Name
Operation
TOP
Update
Output Waveform
On Match On Update
OVFIF/Event
Up
Down
NFRQ
Normal
Frequency
PER
CC0
TOP/ ZERO Toggle
Stable
TOP
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
–
MFRQ
Match
Frequency
TOP/ ZERO Toggle
Stable
TOP
NPWM
Single-slope PER
PWM
TOP/ ZERO See section 'Output Polarity' TOP
below
DSCRITICAL
DSBOTTOM
DSBOTH
DSTOP
Dual-slope
PWM
PER
PER
PER
PER
ZERO
-
Dual-slope
PWM
ZERO
-
Dual-slope
PWM
TOP(1)
ZERO
&
TOP
TOP
Dual-slope
PWM
ZERO
1. The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel.
Related Links
31.6.3.2 Circular Buffer
23. PORT - I/O Pin Controller
DS40001882G-page 624
Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.6.2.5.2 Normal Frequency (NFRQ)
For Normal Frequency generation, the period time (T) is controlled by the period register (PER). The waveform
generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding
Match or Capture Channel x Interrupt Flag (EVCTRL.MCEOx) will be set.
Figure 31-4.ꢀNormal Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
"reload" update
"clear" update
"match"
TOP
CCx
COUNT
ZERO
WO[x]
31.6.2.5.3 Match Frequency (MFRQ)
For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on
each update condition.
Figure 31-5.ꢀMatch Frequency Operation
Direction Change
COUNT Written
MAX
CC0
"reload" update
"clear" update
COUNT
ZERO
WO[0]
31.6.2.5.4 Normal Pulse-Width Modulation (NPWM)
NPWM uses single-slope PWM generation.
31.6.2.5.5 Single-Slope PWM Operation
For single-slope PWM generation, the period time (T) is controlled by Top value, and CCx controls the duty cycle of
the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT
and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting,
the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match
between COUNT and CCx register values.
DS40001882G-page 625
Complete Datasheet
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TCC – Timer/Counter for Control Applications
Figure 31-6.ꢀSingle-Slope PWM Operation
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CCx
ZERO
WO[x]
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
log(TOP+1)
R
=
PWM_SS
log(2)
The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and
can be calculated by the following equation:
f
GCLK_TCC
f
=
PWM_SS
N(TOP+1)
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
31.6.2.5.6 Dual-Slope PWM Generation
For dual-slope PWM generation, the period setting (TOP) is controlled by PER, while CCx control the duty cycle of
the generated waveform output. The figure below shows how the counter repeatedly counts from ZERO to PER and
then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared
on compare match when down-counting. An interrupt and/or event is generated on TOP (when counting upwards)
and/or ZERO (when counting up or down).
In DSBOTH operation, the circular buffer must be enabled to enable the update condition on TOP.
Figure 31-7.ꢀDual-Slope Pulse Width Modulation
CCx=ZERO
CCx=TOP
"update"
"match"
MAX
TOP
CCx
COUNT
ZERO
WO[x]
Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation.
The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
log(PER+1)
R
=
.
PWM_DS
log(2)
The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCC, and
can be calculated by the following equation:
f
GCLK_TCC
f
=
PWM_DS
2N ⋅ PER
DS40001882G-page 626
Complete Datasheet
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TCC – Timer/Counter for Control Applications
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC
clock frequency (fGCLK_TCC) when TOP is set to 0x00000001 and no prescaling is used.
The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency
(fGCLK_TCC), and can be calculated by the following equation:
2N ⋅ TOP − CCx
P
=
PWM_DS
f
GCLK_TCC
N represents the prescaler divider used.
Note:ꢀ In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB bit defines
the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0, falling if CCx[MSB] = 1.)
Related Links
31.6.3.2 Circular Buffer
31.6.2.5.7 Dual-Slope Critical PWM Generation
Critical mode generation allows generation of non-aligned centered pulses. In this mode, the period time is controlled
by PER while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2) control
the generated waveform output edge during down-counting.
Figure 31-8.ꢀDual-Slope Critical Pulse Width Modulation (N=CC_NUM)
"reload" update
"match"
MAX
CCx
CC(x+N/2)
CCx
CC(x+N/2)
CCx
CC(x+N/2)
TOP
COUNT
ZERO
WO[x]
31.6.2.5.8 Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM
operation, it is possible to invert the pulse edge alignment individually on start or end of a PWM cycle for each
compare channels. The table below shows the waveform output set/clear conditions, depending on the settings of
timer/counter, direction, and polarity.
Table 31-3.ꢀWaveform Generation Set/Clear Conditions
Waveform Generation
operation
DIR POLx Waveform Generation Output Update
Set
Clear
Single-Slope PWM
Dual-Slope PWM
0
1
x
0
1
0
1
0
Timer/counter matches TOP
Timer/counter matches CC
Timer/counter matches CC
Timer/counter matches ZERO
Timer/counter matches CCx
Timer/counter matches TOP
Timer/counter matches ZERO
Timer/counter matches CC
Timer/counter matches CC when
counting up
Timer/counter matches CC when
counting down
1
Timer/counter matches CC when
counting down
Timer/counter matches CC when
counting up
DS40001882G-page 627
Complete Datasheet
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TCC – Timer/Counter for Control Applications
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.
31.6.2.6 Double Buffering
The Pattern (PATT), Waveform (WAVE), Period (PER) and Compare Channels (CCx) registers are all double
buffered. Each buffer register has a buffer valid (PATTBV, WAVEBV, PERBV and CCBVx) bit in the STATUS register,
which indicates that the buffer register contains a valid value that can be copied into the corresponding register. .
When the buffer valid flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register is set to
'0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers will be copied into the
corresponding register under hardware UPDATE conditions, then the buffer valid flags bit in the STATUS register are
automatically cleared by hardware.
Note:ꢀ Software update command (CTRLBSET.CMD=0x3) act independently of LUPD value.
A compare register is double buffered as in the following figure.
Figure 31-9.ꢀCompare Channel Double Buffering
"APB write enable"
"data write"
CCBx
CCx
BV
UPDATE
COUNT
"match"
=
Both the registers (PATT/WAVE/PER/CCx) and corresponding buffer registers (PATTB/WAVEBV/PERB/CCBx) are
available in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled
by writing a '1' to CTRLSET.LUPD.
Note:ꢀ In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double buffering is
enabled (CTRLBCLR.LUPD=1), PERB register is continuously copied into the PER independently of update
conditions.
Changing the Period
The counter period can be changed by writing a new Top value to the Period register (PER or CC0, depending on the
waveform generation mode), any period update on registers (PER or CCx) is effective after the synchronization delay,
whatever double buffering enabling is.
DS40001882G-page 628
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TCC – Timer/Counter for Control Applications
Figure 31-10.ꢀUnbuffered Single-Slope Up-Counting Operation
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
Figure 31-11.ꢀUnbuffered Single-Slope Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
A counter wraparound can occur in any operation mode when up-counting without buffering, see Figure 31-10.
COUNT and TOP are continuously compared, so when a new value that is lower than the current COUNT is written
to TOP, COUNT will wrap before a compare match.
Figure 31-12.ꢀUnbuffered Dual-Slope Operation
Counter Wraparound
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct
operation. The period register is always updated on the update condition, as shown in Figure 31-13. This prevents
wraparound and the generation of odd waveforms.
DS40001882G-page 629
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TCC – Timer/Counter for Control Applications
Figure 31-13.ꢀChanging the Period Using Buffering
MAX
"reload" update
"write"
COUNT
ZERO
New value written to
PERB that is higher than
current COUNT
New value written to
PER is updated with
PERB that is lower
PERB value.
than current COUNT
31.6.2.7 Capture Operations
To enable and use capture operations, the Match or Capture Channel x Event Input Enable bit in the Event Control
register (EVCTRL.MCEIx) must be written to '1'. The capture channels to be used must also be enabled in the
Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx) before capturing can be performed.
Event Capture Action
The compare/capture channels can be used as input capture channels to capture events from the Event System, and
give them a timestamp. The following figure shows four capture events for one capture channel.
Figure 31-14.ꢀInput Capture Timing
events
MAX
COUNT
ZERO
Capture 0
Capture 1
Capture 2
Capture 3
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any
content in CCBx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate
the optional interrupt, event or DMA request. CCBx register value can't be read, all captured data must be read from
CCx register.
DS40001882G-page 630
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TCC – Timer/Counter for Control Applications
Figure 31-15.ꢀCapture Double Buffering
"capture"
COUNT
CCBx
CCx
EN
EN
BV
IF
"INT/DMA
request"
data read
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Buffer Valid flag (STATUS.CCBV) is still set, the new timestamp will not be stored and INTFLAG.ERR will be
set.
Period and Pulse-Width (PPW) Capture Action
The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to
measure the pulse-width and period and to characterize the frequency f and dutyCycle of an input signal:
t
p
1
T
f =
,
dutyCycle =
T
Figure 31-16.ꢀPWP Capture
Period (T)
external
signal /event
capture times
MAX
"capture"
COUNT
ZERO
CC0
CC1
CC0
CC1
Selecting PWP or PPW in the Timer/Counter Event Input 1 Action bit group in the Event Control register
(EVCTRL.EVACT1) enables the TCC to perform one capture action on the rising edge and the other one on the
falling edge. When using PPW (period and pulse-width) event action, period T will be captured into CC0 and the
pulse-width tp into CC1. The PWP (Pulse-width and Period) event action offers the same functionality, but T will be
captured into CC1 and tp into CC0.
The Timer/Counter Event x Invert Enable bit in Event Control register (EVCTRL.TCEINVx) is used for event source
x to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCEINVx=1, the
wraparound will happen on the falling edge.
The corresponding capture is done only if the channel is enabled in capture mode (CTRLA.CPTENx=1). If not, the
capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these
channel is required, the other channel can be used for other purposes.
DS40001882G-page 631
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TCC – Timer/Counter for Control Applications
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
INTFLAG.MCx is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
Note:ꢀ When up-counting (CTRLBSET.DIR=0), counter values lower than 1 cannot be captured in Capture Minimum
mode (FCTRLn.CAPTURE=CAPTMIN). To capture the full range including value 0, the TCC must be configured in
down-counting mode (CTRLBSET.DIR=0).
Note:ꢀ In dual-slope PWM operation, and when TOP is lower than MAX/2, the CCx MSB captures the CTRLB.DIR
state to identify the ramp on which the capture has been done. For rising ramps CCx[MSB] is zero, for falling ramps
CCx[MSB]=1.
31.6.3 Additional Features
31.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition.
When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is set and the waveform outputs are
set to the value defined by DRVCTRL.NREx and DRVCTRL.NRVx.
One-shot operation can be enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT) and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TCC will count
until an overflow or underflow occurs and stop counting. The one-shot operation can be restarted by a re-trigger
software command, a re-trigger event or a start event. When the counter restarts its operation, STATUS.STOP is
automatically cleared.
31.6.3.2 Circular Buffer
The Period register (PER) and the compare channels register (CC0 to CC3) support circular buffer operation. When
circular buffer operation is enabled, the PER or CCx values are copied into the corresponding buffer registers at each
update condition. Circular buffering is dedicated to RAMP2, RAMP2A, and DSBOTH operations.
Figure 31-17.ꢀCircular Buffer on Channel 0
"data write"
"write enable"
UPDATE
BV
CCB0
CC0
CIRCC0EN
UPDATE
COUNT
"match"
=
31.6.3.3 Dithering Operation
The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame.
Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the
accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare
match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither
patterns.
Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register
(CTRLA.RESOLUTION):
•
•
•
DITH4 enable dithering every 16 PWM frames
DITH5 enable dithering every 32 PWM frames
DITH6 enable dithering every 64 PWM frames
DS40001882G-page 632
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
The DITHERCY bits of COUNT, PER and CCx define the number of extra cycles to add into the frame (DITHERCY
bits from the respective COUNT, PER or CCx registers). The remaining bits of COUNT, PER, CCx define the
compare value itself.
The pseudo code, giving the extra cycles insertion regarding the cycle is:
int extra_cycle(resolution, dithercy, cycle){
int MASK;
int value
switch (resolution){
DITH4: MASK = 0x0f;
DITH5: MASK = 0x1f;
DITH6: MASK = 0x3f;
}
value = cycle * dithercy;
if (((MASK & value) + dithercy) > MASK)
return 1;
return 0;
}
Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.
DITH4 mode:
DITHERCY
16
1
PwmPeriod =
+ PER
f
GCLK_TCC
Note:ꢀ If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register correspond to the
DITHERCY value, rest of the bits corresponds to PER/CCx or COUNT value.
DITH5 mode:
DITHERCY
32
1
PwmPeriod =
DITH6 mode:
PwmPeriod =
+ PER
+ PER
f
GCLK_TCC
DITHERCY
64
1
f
GCLK_TCC
Dithering on Pulse Width
Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula.
DITH4 mode:
DITHERCY
16
1
PwmPulseWidtℎ =
DITH5 mode:
+ CCx
+ CCx
+ CCx
f
f
f
GCLK_TCC
DITHERCY
32
1
PwmPulseWidtℎ =
DITH6 mode:
GCLK_TCC
DITHERCY
64
1
PwmPulseWidtℎ =
GCLK_TCC
Note:ꢀ The PWM period will remain static in this case.
31.6.3.4 Ramp Operations
Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM
generation. The ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register
(WAVE.RAMP).
DS40001882G-page 633
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TCC – Timer/Counter for Control Applications
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull SMPS
topologies, where two consecutive timer/counter cycles are interleaved, see Figure 31-18. In cycle A, odd channel
output is disabled, and in cycle B, even channel output is disabled. The ramp index changes after each update, but
can be software modified using the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled by the PER register value. The PER value can be different on each ramp by
the Circular Period buffer option in the Wave register (WAVE.CIPEREN=1). This mode uses a two-channel TCC to
generate two output signals, or one output signal with another CC channel enabled in capture mode.
Figure 31-18.ꢀRAMP2 Standard Operation
"clear" update
"match"
Ramp
A
B
A
B
Retrigger
on
TOP(B)
TOP(B)
TOP(A)
CIPEREN = 1
FaultA
CC1
CC1
COUNT
CC0
CC0
ZERO
WO[0]
WO[1]
POL0 = 1
POL1 = 1
Keep on FaultB
FaultA input
FaultB input
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the
corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs.
Channel 1 can be used in capture mode.
DS40001882G-page 634
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TCC – Timer/Counter for Control Applications
Figure 31-19.ꢀRAMP2 Alternate Operation
"clear" update
"match"
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP(B)
TOP(B)
TOP(A)
CIPEREN = 1
CICCEN0 = 1
CC0(B)
CC0(B)
COUNT
CC0(A)
CC0(A)
ZERO
WO[0]
WO[1]
POL0 = 1
Keep on FaultB
FaultA input
FaultB input
Critical RAMP2 (RAMP2C) Operation
Critical RAMP2 operation provides a way to cover RAMP2 operation requirements without the update constraint
associated with the use of circular buffers. In this mode, CC0 is controlling the period of ramp A and PER is
controlling the period of ramp B. When using more than two channels, WO[0] output is controlled by CC2 (HIGH) and
CC0 (LOW). On TCC with 2 channels, a pulse on WO[0] will last the entire period of ramp A, if WAVE.POL0=0.
Figure 31-20.ꢀRAMP2 Critical Operation With More Than 2 Channels
"clear" update
"match"
Ramp
A
B
A
B
Retrigger
on
TOP
TOP
CC0
FaultA
CC1
CC1
COUNT
CC2
CC2
ZERO
WO[0]
WO[1]
POL2 = 1
POL1 = 1
Keep on FaultB
FaultA input
FaultB input
DS40001882G-page 635
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TCC – Timer/Counter for Control Applications
Figure 31-21.ꢀRAMP2 Critical Operation With 2 Channels
"clear" update
"match"
Ramp
A
B
A
B
Retrigger
on
TOP
TOP
CC0
FaultA
CC1
CC1
COUNT
ZERO
WO[0]
WO[1]
POL0 = 0
POL1 = 1
Keep on FaultB
FaultA input
FaultB input
31.6.3.5 Recoverable Faults
Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable
fault actions on the compare channels CC0 and CC1 of the TCC. The compare channels' outputs can be clamped to
inactive state either as long as the fault condition is present, or from the first valid fault condition detection on until the
end of the timer/counter cycle.
Fault Inputs
The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs,
respectively. Event system channels connected to these fault inputs must be configured as asynchronous. The TCC
must work in a PWM mode.
Fault Filtering
There are three filters available for each input Fault A and Fault B. They are configured by the corresponding
Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can either be used
independently or in any combination.
Input
Filtering
By default, the event detection is asynchronous. When the event occurs, the fault system will
immediately and asynchronously perform the selected fault action on the compare channel output,
also in device power modes where the clock is not available. To avoid false fault detection on external
events (e.g. due to a glitch on an I/O port) a digital filter can be enabled and configured by the Fault
B Filter Value bits in the Fault n Configuration registers (FCTRLn.FILTERVAL). If the event width is
less than FILTERVAL (in clock cycles), the event will be discarded. A valid event will be delayed by
FILTERVAL clock cycles.
Fault
This ignores any fault input for a certain time just after a selected waveform output edge. This can be
Blanking used to prevent false fault triggering due to signal bouncing, as shown in the figure below. Blanking
can be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the
Recoverable Fault n Configuration register (FCTRLn.BLANK). The desired duration of the blanking
must be written to the Fault n Blanking Time bits (FCTRLn.BLANKVAL).
The blanking time tbis calculated by
1 + BLANKVAL
t =
b
f
GCLK_TCCx_PRESC
Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx
.
DS40001882G-page 636
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TCC – Timer/Counter for Control Applications
The maximum blanking time (FCTRLn.BLANKVAL=
255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For fGCLK_TCCx=1MHz, the
maximum blanking time is either 170µs (no prescaling) or 10.9ms (prescaling enabled).
Figure 31-22.ꢀFault Blanking in RAMP1 Operation with Inverted Polarity
"clear" update
"match"
TOP
"Fault input enabled"
"Fault input disabled"
"Fault discarded"
-
CC0
x
COUNT
ZERO
CMP0
FCTRLA.BLANKVAL = 0
FCTRLA.BLANKVAL > 0
FCTRLA.BLANKVAL > 0
FaultA Blanking
FaultA Input
-
-
x
x x x
WO[0]
Fault
Qualification
This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n
Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled
(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output
has an inactive level, as shown in the figures below.
Figure 31-23.ꢀFault Qualification in RAMP1 Operation
MAX
TOP
"clear" update
"match"
"Fault input enabled"
"Fault input disabled"
"Fault discarded"
CC0
CC1
COUNT
-
x
ZERO
-
-
-
-
-
x x
-
x x x
Fault A Input Qual
Fault Input A
x
x
x
x
Fault B Input Qual
Fault Input B
-
-
-
-
-
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x x
x x
DS40001882G-page 637
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TCC – Timer/Counter for Control Applications
Figure 31-24.ꢀFault Qualification in RAMP2 Operation with Inverted Polarity
Cycle
MAX
TOP
"clear" update
"match"
"Fault input enabled"
"Fault input disabled"
"Fault discarded"
COUNT
CC0
CC1
-
x
ZERO
Fault A Input Qual
Fault Input A
-
-
-
x
x
x
x
x
x
x
x
x
x
x
x
Fault B Input Qual
Fault Input B
-
-
-
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually
exclusive; hence two or more actions can be enabled at the same time to achieve a result that is a combination of
fault actions.
Keep
Action
This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register
(FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as
long as the fault condition is present. The clamp will be released on the start of the first cycle after the
fault condition is no longer present, see next Figure.
Figure 31-25.ꢀWaveform Generation with Fault Qualification and Keep Action
MAX
TOP
"clear" update
"match"
"Fault input enabled"
"Fault input disabled"
"Fault discarded"
COUNT
CC0
-
x
ZERO
Fault A Input Qual
Fault Input A
WO[0]
-
-
-
-
-
x
x
x
x
KEEP
KEEP
Restart This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
Action
(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a
new cycle, see Figure 31-26. In Ramp 1 mode, when the new cycle starts, the compare outputs will be
clamped to inactive level as long as the fault condition is present.
Note:ꢀ For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change
automatically, see Figure 31-27. Fault A and Fault B are qualified only during the cycle A and cycle
B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A.
DS40001882G-page 638
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TCC – Timer/Counter for Control Applications
Figure 31-26.ꢀWaveform Generation in RAMP1 mode with Restart Action
MAX
TOP
"clear" update
"match"
CC0
CC1
COUNT
ZERO
Restart
Restart
Fault Input A
WO[0]
WO[1]
Figure 31-27.ꢀWaveform Generation in RAMP2 mode with Restart Action
Cycle
"clear" update
"match"
CCx=ZERO
CCx=TOP
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B
Restart
Fault Input A
WO[0]
WO[1]
Capture Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control
Action
register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is
captured when the fault occurs. These capture operations are available:
•
•
•
CAPT - the equivalent to a standard capture operation, for further details refer to 31.6.2.7 Capture
Operations
CAPTMIN - gets the minimum time stamped value: on each new local minimum captured value, an
event or interrupt is issued.
CAPTMAX - gets the maximum time stamped value: on each new local maximum captured value,
an event or interrupt (IT) is issued, see Figure 31-28.
•
•
•
LOCMIN - notifies by event or interrupt when a local minimum captured value is detected.
LOCMAX - notifies by event or interrupt when a local maximum captured value is detected.
DERIV0 - notifies by event or interrupt when a local extreme captured value is detected, see Figure
31-29.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see
Figure 31-28. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time,
see Figure 31-29.
DS40001882G-page 639
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TCC – Timer/Counter for Control Applications
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding
CCx register value to a value different from zero (for CAPTMIN) top (for CAPTMAX). If the CCx
register initial value is zero (for CAPTMIN) top (for CAPTMAX), no captures will be performed using the
corresponding channel.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt
flag is set only when the captured value is above or equal (for LOCMIN) or below or equal (for
LOCMAX) to the previous captured value. So interrupt flag is set when a new relative local Minimum
(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR
function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each
new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the
counter value is lower (for CAPTMIN) or higher (for CAPMAX) than the last captured value. The MCx
interrupt flag is set only when on capture event time, the counter value is higher or equal (for CAPTMIN)
or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is
set when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel
capture counter value. In other modes, an interrupt is only generated on an extreme captured value.
Figure 31-28.ꢀCapture Action “CAPTMAX”
TOP
CC0
"clear" update
COUNT
ZERO
FaultA Input
CC0 Event/
Interrupt
Figure 31-29.ꢀCapture Action “DERIV0”
TOP
"update"
"match"
COUNT
CC0
ZERO
WO[0]
FaultA Input
CC0 Event/
Interrupt
Hardware
This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Halt Action Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is
extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where
both restart action and hardware halt action are enabled for Fault A. The compare channel 0 output
DS40001882G-page 640
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TCC – Timer/Counter for Control Applications
is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. As the restart action is enabled
in this example, the timer/counter is restarted after the fault condition is no longer present.
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart Actions') shows
a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the
fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index
will automatically change.
Figure 31-30.ꢀWaveform Generation with Halt and Restart Actions
MAX
"clear" update
TOP
"match"
CC0
COUNT
HALT
ZERO
Restart
Restart
Fault Input A
WO[0]
Figure 31-31.ꢀWaveform Generation with Fault Qualification, Halt, and Restart Actions
MAX
TOP
"update"
"match"
COUNT
CC0
HALT
ZERO
Resume
Fault A Input Qual
Fault Input A
WO[0]
-
-
-
-
-
x
x
x
KEEP
Software
This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
Halt Action
configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but
in order to restart the timer/counter, the corresponding fault condition must not be present anymore,
and the corresponding FAULT n bit in the STATUS register must be cleared by software.
DS40001882G-page 641
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-32.ꢀWaveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
MAX
"update"
TOP
"match"
COUNT
CC0
HALT
ZERO
Restart
Restart
Fault A Input Qual
Fault Input A
Software Clear
WO[0]
-
-
-
-
x
x
NO
KEEP
KEEP
FCTRLA.KEEP = 1
FCTRLA.KEEP = 0
31.6.3.6 Non-Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver
Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0 and EV1) actions are
enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1).
To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using
Non-Recoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). Therefore, the
event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles.
When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written
to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug
operation.
In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing
CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the
respective interrupt (UFS) are generated.
31.6.3.7 Waveform Extension
Figure 31-33 shows a schematic diagram of actions of the four optional units that follow the recoverable fault stage
on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern Generation. The DTI and
SWAP units can be seen as a four port pair slices:
•
•
Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
•
Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
DS40001882G-page 642
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-33.ꢀWaveform Extension Stage Details
WEX
PORTS
OTMX
DTI
SWAP
PATTERN
OTMX[x+WO_NUM/2]
PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
INV[x+WO_NUM/2]
LS
DTIx
HS
PGO[x+WO_NUM/2]
SWAPx
OTMX
DTIxEN
PGO[x]
INV[x]
P[x]
OTMX[x]
PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in Table
31-4.
Table 31-4.ꢀOutput Matrix Channel Pin Routing Configuration
Value
0x0
OTMX[x]
CC3
CC3
CC1
CC0
CC1
CC2
CC0
CC0
CC1
CC1
CC1
CC0
CC1
CC0
CC0
CC0
CC1
CC2
CC0
CC0
CC1
CC1
CC1
CC0
CC1
CC0
CC0
CC0
CC0
0x1
CC1
0x2
CC0
0x3
CC1
Notes on Table 31-4:
•
•
Configuration 0x0 is the default configuration. The channel location is the default one, and channels are
distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output
OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated
to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the
number of output locations to the lower channels than the default configuration. This can be used, for example,
to control the four transistors of a full bridge using only two compare channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible
drive of a full bridge in all quadrant configurations.
•
•
Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other
outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED
strings, with a boost stage.
Ta•ble 31-5.ꢀExample: four compare channels on four outputs
Value
0x0
OTMX[3]
CC3
OTMX[2]
CC2
OTMX[1]
CC1
OTMX[0]
CC0
0x1
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC0
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side
(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures
that the LS and HS will never switch simultaneously.
DS40001882G-page 643
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 31-34 shows the block diagram of one DTI generator. The four channels have a common register which
controls the dead time, which is independent of high side and low side setting.
Figure 31-34.ꢀDead-Time Generator Block Diagram
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
= 0
"DTLS"
(To PORT)
OTMX output
D
Q
"DTHS"
(To PORT)
Edge Detect
As shown in Figure 31-35, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it
reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When
the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the
output changes from high to low (negative edge) it reloads the DTHS register.
Figure 31-35.ꢀDead-Time Generator Timing Diagram
"dti_cnt"
T
tP
tDTILS
tDTIHS
"OTMX output"
"DTLS"
"DTHS"
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC),
stepper motors, and full bridge control. See also Figure 31-36.
DS40001882G-page 644
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-36.ꢀPattern Generator Block Diagram
COUNT
UPDATE
SWAP output
BV
PGEB[7:0]
PGE[7:0]
BV
PGVB[7:0]
PGV[7:0]
EN
EN
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition
set by the timer/counter waveform generation operation. If synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
31.6.4 DMA, Interrupts, and Events
Table 31-6.ꢀModule Requests for TCC
Condition
Interrupt
request
Event
output
Event input DMA
request
DMA request is cleared
Overflow / Underflow
Yes
Yes
Yes
Yes(1)
Yes(3)
On DMA acknowledge
Channel Compare Match or Yes
Capture
Yes(2)
For circular buffering: on
DMA acknowledge
For capture channel:
when CCx register is
read
Retrigger
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Count
Capture Overflow Error
Debug Fault State
Recoverable Faults
Non-Recoverable Faults
TCCx Event 0 input
TCCx Event 1 input
Yes(4)
Yes(5)
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
DS40001882G-page 645
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
– re-trigger counter
– control counter direction
– stop the counter
– decrement the counter
– perform period and pulse width capture
– generate non-recoverable fault
5. On event input, either action can be executed:
– re-trigger counter
– increment or decrement counter depending on direction
– start the counter
– increment or decrement counter based on direction
– increment counter regardless of direction
– generate non-recoverable fault
31.6.4.1 DMA Operation
The TCC can generate the following DMA requests:
Counter
overflow
(OVF)
If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the
TCC generates a DMA request on each cycle when an update condition (overflow, underflow or
re-trigger) is detected.
When an update condition (overflow, underflow or re-trigger) is detected while CTRLA.DMAOS=1,
the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to
the Control B register (CTRLBSET.CMD=DMAOS).
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel
A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is cleared by
Match (MCx) hardware on DMA acknowledge.
When CTRLA.DMAOS=1, the DMA requests are not generated.
Channel
Capture
(MCx)
For a capture channel, the request is set when valid data is present in the CCx register, and cleared
once the CCx register is read.
In this operation mode, the CTRLA.DMAOS bit value is ignored.
DMA Operation with Circular Buffer
When circular buffer operation is enabled, the buffer registers must be written in a correct order and synchronized to
the update times of the timer. The DMA triggers of the TCC provide a way to ensure a safe and correct update of
circular buffers.
Note:ꢀ Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only.
DMA Operation with Circular Buffer in RAMP2 and RAMP2A Mode
When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of ramp B.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A with an
effective DMA transfer on previous ramp B (DMA acknowledge).
The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC trigger.
The update of all circular buffer values for ramp B, can be done through a second DMA channel triggered by the
overflow DMA request.
DS40001882G-page 646
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-37.ꢀDMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
Ramp
Cycle
A
A
B
B
A
B
N-1
N
N-2
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req
DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase
with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When
down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA
request.
Figure 31-38.ꢀDMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N
N-2
N-1
New Parameter Set
Old Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
DMA_CCx_req
DMA Channel i
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
31.6.4.2 Interrupts
The TCC has the following interrupt sources:
•
•
•
•
•
Overflow/Underflow (OVF)
Retrigger (TRG)
Count (CNT) - refer also to description of EVCTRL.CNTSEL.
Capture Overflow Error (ERR)
Non-Recoverable Update Fault (UFS)
DS40001882G-page 647
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
•
•
•
•
Debug Fault State (DFS)
Recoverable Faults (FAULTn)
Non-recoverable Faults (FAULTx)
Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode
Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the TCC is reset. See 31.8.12 INTFLAG for details on how to clear
interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
16.6.2.8 Sleep Mode Controller
16.6.2.8.1 IDLE Mode
16.6.2.8.2 STANDBY Mode
31.6.4.3 Events
The TCC can generate the following output events:
•
•
•
•
Overflow/Underflow (OVF)
Trigger (TRG)
Counter (CNT) For further details, refer to EVCTRL.CNTSEL description.
Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the
corresponding output event. Refer also to EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
•
•
Capture event
Generate a recoverable or non-recoverable fault
The TCC can take the following actions on counter Event 1 (TCCx EV1):
•
•
•
•
•
•
Counter re-trigger
Counter direction control
Stop the counter
Decrement the counter on event
Period and pulse width capture
Non-recoverable fault
The TCC can take the following actions on counter Event 0 (TCCx EV0):
•
•
•
Counter re-trigger
Count on event (increment or decrement, depending on counter direction)
Counter start - start counting on the event rising edge. Further events will not restart the counter; the counter will
keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction.
•
•
Counter increment on event. This will increment the counter, irrespective of the counter direction.
Count during active state of an asynchronous event (increment or decrement, depending on counter direction).
In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as
the event is active.
•
Non-recoverable fault
DS40001882G-page 648
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and EVCTRL.EVACT1).
For further details, refer to EVCTRL.
Writing a '1' ('0') to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables
(disables) the corresponding action on input event.
Note:ꢀ When several events are connected to the TCC, the enabled action will apply for each of the incoming events.
Refer to EVSYS – Event System for details on how to configure the event system.
Related Links
24. EVSYS – Event System
31.6.5 Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be '1'. The MODULE can in any sleep mode wake up the device using
interrupts or perform actions through the Event System.
31.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Status register (STATUS)
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Count Value register (COUNT)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBx)
The following registers are synchronized when read:
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Count Value register (COUNT): synchronization is done on demand through READSYNC command
(CTRLBSET.CMD)
•
•
•
•
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 649
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
23:16
31:24
7:0
RESOLUTION[1:0]
ENABLE
SWRST
ALOCK
PRESCYNC[1:0]
RUNSTDBY
CPTEN3
PRESCALER[2:0]
0x00
CTRLA
CPTEN2
ONESHOT
ONESHOT
CPTEN1
LUPD
CPTEN0
DIR
0x04
0x05
0x06
...
CTRLBCLR
CTRLBSET
CMD[2:0]
CMD[2:0]
IDXCMD[1:0]
IDXCMD[1:0]
7:0
LUPD
DIR
Reserved
0x07
7:0
15:8
23:16
31:24
7:0
PER
WAVE
CCB3
PATT
CCB2
COUNT
CCB1
STATUS
CTRLB
CC2
ENABLE
CC1
SWRST
CC0
CC3
0x08
0x0C
0x10
0x14
0x18
SYNCBUSY
CCB0
PERB
WAVEB
PATTB
RESTART
RESTART
BLANK[1:0]
CAPTURE[2:0]
QUAL
KEEP
SRC[1:0]
15:8
23:16
31:24
7:0
CHSEL[1:0]
HALT[1:0]
FCTRLA
FCTRLB
BLANKVAL[7:0]
FILTERVAL[3:0]
BLANK[1:0]
QUAL
KEEP
CHSEL[1:0]
SRC[1:0]
HALT[1:0]
15:8
23:16
31:24
7:0
CAPTURE[2:0]
BLANKVAL[7:0]
FILTERVAL[3:0]
OTMX[1:0]
15:8
23:16
31:24
7:0
DTIEN3
DTLS[7:0]
DTHS[7:0]
DTIEN2
DTIEN1
DTIEN0
WEXCTRL
NRE7
NRV7
NRE6
NRV6
NRE5
NRV5
NRE4
NRE3
NRV3
NRE2
NRV2
NRE1
NRV1
NRE0
NRV0
15:8
23:16
31:24
NRV4
DRVCTRL
Reserved
INVEN7
INVEN6
INVEN5
INVEN4
INVEN3
INVEN2
INVEN1
INVEN0
FILTERVAL1[3:0]
FILTERVAL0[3:0]
0x1C
...
0x1D
0x1E
0x1F
DBGCTRL
Reserved
7:0
FDDBD
DBGRUN
7:0
15:8
23:16
31:24
7:0
CNTSEL[1:0]
EVACT1[2:0]
TCINV0
EVACT0[2:0]
TRGEO
MCEI1
TCEI1
FAULT1
FAULT1
FAULT1
TCEI0
FAULT0
FAULT0
FAULT0
TCINV1
FAULTB
FAULTB
FAULTB
CNTEO
MCEI2
MCEO2
CNT
OVFEO
MCEI0
MCEO0
OVF
0x20
0x24
0x28
0x2C
0x30
EVCTRL
INTENCLR
INTENSET
INTFLAG
STATUS
MCEI3
MCEO3
ERR
MCEO1
TRG
15:8
23:16
31:24
7:0
FAULTA
FAULTA
FAULTA
FAULTA
DFS
UFS
MC3
MC2
MC1
TRG
MC1
TRG
MC1
MC0
OVF
MC0
OVF
MC0
ERR
DFS
MC3
CNT
UFS
MC2
15:8
23:16
31:24
7:0
ERR
DFS
MC3
CNT
UFS
MC2
15:8
23:16
31:24
7:0
PERBV
FAULT1
WAVEBV
FAULT0
PATTBV
FAULTB
DFS
FAULT1IN
CCBV3
CMP3
UFS
FAULT0IN
CCBV2
CMP2
IDX
FAULTBIN
CCBV1
CMP1
STOP
FAULTAIN
CCBV0
CMP0
15:8
23:16
31:24
DS40001882G-page 650
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
23:16
31:24
7:0
COUNT[7:0]
COUNT[15:8]
0x34
COUNT
COUNT[23:16]
PGE7
PGV7
PGE6
PGV6
PGE5
PGV5
PGE4
PGV4
PGE3
PGV3
PGE2
PGV2
PGE1
PGV1
PGE0
PGV0
0x38
PATT
15:8
0x3A
...
Reserved
0x3B
7:0
15:8
23:16
31:24
7:0
CIPEREN
RAMP[1:0]
WAVEGEN[2:0]
CICCEN1
POL1
CICCEN3
POL3
CICCEN2
POL2
CICCEN0
POL0
0x3C
0x40
0x44
0x48
0x4C
0x50
WAVE
PER
CC0
CC1
CC2
CC3
SWAP3
SWAP2
SWAP1
SWAP0
PER[1:0]
DITHER[5:0]
15:8
23:16
31:24
7:0
PER[9:2]
PER[17:10]
CC[1:0]
CC[1:0]
CC[1:0]
CC[1:0]
DITHER[5:0]
DITHER[5:0]
DITHER[5:0]
DITHER[5:0]
15:8
23:16
31:24
7:0
CC[9:2]
CC[17:10]
15:8
23:16
31:24
7:0
CC[9:2]
CC[17:10]
15:8
23:16
31:24
7:0
CC[9:2]
CC[17:10]
15:8
23:16
31:24
CC[9:2]
CC[17:10]
0x54
...
Reserved
PATTB
0x63
7:0
PGEB7
PGVB7
PGEB6
PGVB6
PGEB5
PGVB5
PGEB4
PGVB4
PGEB3
PGEB2
PGVB2
PGEB1
PGVB1
PGEB0
PGVB0
0x64
15:8
PGVB3
0x66
...
Reserved
0x67
7:0
15:8
23:16
31:24
7:0
CIPERENB
RAMPB[1:0]
WAVEGENB[2:0]
CICCENB1
POLB1
CICCENB3
POLB3
CICCENB2
POLB2
CICCENB0
POLB0
0x68
0x6C
0x70
0x74
WAVEB
PERB
CCB0
CCB1
SWAPB 3
SWAPB 2
SWAPB 1
SWAPB 0
PERB[1:0]
DITHERB[5:0]
15:8
23:16
31:24
7:0
PERB[9:2]
PERB[17:10]
CCB[1:0]
CCB[1:0]
DITHERB[5:0]
DITHERB[5:0]
15:8
23:16
31:24
7:0
CCB[9:2]
CCB[17:10]
15:8
23:16
31:24
CCB[9:2]
CCB[17:10]
DS40001882G-page 651
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
CCB[1:0]
CCB[1:0]
DITHERB[5:0]
15:8
CCB[9:2]
0x78
0x7C
CCB2
23:16
31:24
7:0
CCB[17:10]
DITHERB[5:0]
15:8
CCB[9:2]
CCB3
23:16
31:24
CCB[17:10]
31.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 652
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
Bit
31
23
15
7
30
22
29
21
13
28
20
12
27
CPTEN3
R/W
26
CPTEN2
R/W
25
CPTEN1
R/W
24
CPTEN0
R/W
Access
Reset
0
0
0
0
Bit
19
18
17
16
Access
Reset
Bit
14
ALOCK
R/W
0
11
RUNSTDBY
R/W
10
9
8
PRESCYNC[1:0]
PRESCALER[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
RESOLUTION[1:0]
Access
Reset
R/W
0
R/W
0
0
Bits 24, 25, 26, 27 – CPTENꢀCapture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bit 14 – ALOCKꢀAuto Lock
This bit is not synchronized.
Value
Description
0
The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow, and
re-trigger events
1
CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.
Bits 13:12 – PRESCYNC[1:0]ꢀPrescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on
the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.
These bits are not synchronized.
Value
Name
Description
Counter Reloaded
Prescaler
0x0
0x1
GCLK
PRESC
Reload or reset Counter on next GCLK
Reload or reset Counter on next
prescaler clock
-
-
0x2
0x3
RESYNC
Reserved
Reload or reset Counter on next GCLK Reset prescaler counter
Bit 11 – RUNSTDBYꢀRun in Standby
This bit is used to keep the TCC running in standby mode.
This bit is not synchronized.
DS40001882G-page 653
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Description
0
1
The TCC is halted in standby.
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0]ꢀPrescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TCC
Prescaler: GCLK_TCC/2
Prescaler: GCLK_TCC/4
Prescaler: GCLK_TCC/8
Prescaler: GCLK_TCC/16
Prescaler: GCLK_TCC/64
Prescaler: GCLK_TCC/256
Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0]ꢀDithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Table 31-7.ꢀDithering
Value
Name
Description
0x0
0x1
NONE
DITH4
The dithering is disabled.
Dithering is done every 16 PWM frames. PER[3:0] and
CCx[3:0] contain dithering pattern selection.
Dithering is done every 32 PWM frames. PER[4:0] and
CCx[4:0] contain dithering pattern selection.
Dithering is done every 64 PWM frames. PER[5:0] and
CCx[5:0] contain dithering pattern selection.
0x2
0x3
DITH5
DITH6
Bit 1 – ENABLEꢀEnable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
1
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 654
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.2 Control B Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBCLR
0x04
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Bit
7
6
CMD[2:0]
R/W
5
4
3
2
ONESHOT
R/W
1
LUPD
R/W
0
0
DIR
R/W
0
IDXCMD[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bits 7:5 – CMD[2:0]ꢀTCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
0x0
0x1
0x2
0x3
0x4
0x5
Name
NONE
Description
No action
RETRIGGER
STOP
UPDATE
READSYNC
DMAOS
Clear start, restart or retrigger
Force stop
Force update of double buffered registers
Force COUNT read synchronization
One-shot DMA trigger
Bits 4:3 – IDXCMD[1:0]ꢀRamp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing zero to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
SET
CLEAR
HOLD
Description
DISABLE Command disabled: IDX toggles between cycles A and B
Set IDX: cycle B will be forced in the next cycle
Clear IDX: cycle A will be forced in next cycle
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOTꢀOne-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on
the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value
Description
0
1
The TCC will update the counter value on overflow/underflow condition and continue operation.
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPDꢀLock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is enabled.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the registers updates on hardware UPDATE condition.
DS40001882G-page 655
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Description
0
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
1
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 656
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.3 Control B Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLBSET
0x05
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBCLR) register.
Bit
7
6
CMD[2:0]
R/W
5
4
3
2
ONESHOT
R/W
1
LUPD
R/W
0
0
DIR
R/W
0
IDXCMD[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bits 7:5 – CMD[2:0]ꢀTCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has
been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect
Writing a valid value to this bit group will set the associated command.
Value
0x0
0x1
0x2
0x3
0x4
0x5
Name
NONE
Description
No action
RETRIGGER
STOP
UPDATE
READSYNC
DMAOS
Force start, restart or retrigger
Force stop
Force update of double buffered registers
Force a read synchronization of COUNT
One-shot DMA trigger
Bits 4:3 – IDXCMD[1:0]ꢀRamp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
SET
CLEAR
HOLD
Description
Command disabled: IDX toggles between cycles A and B
Set IDX: cycle B will be forced in the next cycle
Clear IDX: cycle A will be forced in next cycle
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOTꢀOne-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next
overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value
Description
0
The TCC will count continuously.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPDꢀLock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled.
Disabling the update ensures that all buffer registers are valid before an hardware update is performed. After all the
buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
DS40001882G-page 657
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will disable the registers updates on hardware UPDATE condition.
Value
Description
0
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into CCx, PER,
PGV, PGO and SWAPx registers on hardware update condition.
1
Bit 0 – DIRꢀCounter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
1
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
DS40001882G-page 658
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.4 Synchronization Busy
Name:ꢀ
SYNCBUSY
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x08
0x00000000
-
Bit
31
23
15
30
29
28
27
26
25
24
Access
Reset
Bit
22
CCB3
R
21
CCB2
R
20
CCB1
R
19
CCB0
R
18
PERB
R
17
16
PATTB
R
WAVEB
Access
Reset
R
0
0
0
0
0
0
0
Bit
14
13
12
11
CC3
R
10
CC2
R
9
CC1
R
8
CC0
R
Access
Reset
0
0
0
0
Bit
7
PER
R
6
WAVE
R
5
PATT
R
4
3
2
1
0
COUNT
STATUS
CTRLB
ENABLE
SWRST
Access
Reset
R
0
R
0
R
0
R
0
R
0
0
0
0
Bits 19, 20, 21, 22 – CCBꢀCompare/Capture Buffer Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Buffer Channel x register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Buffer Channel x register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
Bit 18 – PERBꢀPER Buffer Synchronization Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
Bit 17 – WAVEBꢀWAVE Buffer Synchronization Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
This bit is set when the synchronization of WAVEB register between clock domains is started.
Bit 16 – PATTBꢀPATT Buffer Synchronization Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
Bits 8, 9, 10, 11 – CCꢀCompare/Capture Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
DS40001882G-page 659
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bit 7 – PERꢀPER Synchronization Busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
Bit 6 – WAVEꢀWAVE Synchronization Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
Bit 5 – PATTꢀPATT Synchronization Busy
This bit is cleared when the synchronization of PATTERN register between the clock domains is complete.
This bit is set when the synchronization of PATTERN register between clock domains is started.
Bit 4 – COUNTꢀCOUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
Bit 3 – STATUSꢀSTATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
Bit 2 – CTRLBꢀCTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
Bit 1 – ENABLEꢀENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRSTꢀSWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
DS40001882G-page 660
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.5 Fault Control A and B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FCTRLn
0x0C + n*0x04 [n=0..1]
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
FILTERVAL[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
BLANKVAL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
CAPTURE[2:0]
CHSEL[1:0]
HALT[1:0]
SRC[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
RESTART
R/W
6
5
4
QUAL
R/W
0
3
2
1
0
BLANK[1:0]
KEEP
R/W
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 27:24 – FILTERVAL[3:0]ꢀRecoverable Fault n Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx
event is used as synchronous event.
Bits 23:16 – BLANKVAL[7:0]ꢀRecoverable Fault n Blanking Value
These bits determine the duration of the blanking of the fault input source. Activation and edge selection of the blank
filtering are done by the BLANK bits (FCTRLn.BLANK).
When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCC periods after the
detection of the waveform edge.
Bits 14:12 – CAPTURE[2:0]ꢀRecoverable Fault n Capture Action
These bits select the capture and Fault n interrupt/event conditions.
Table 31-8.ꢀFault n Capture Action
Value
Name
Description
0x0
0x1
DISABLE Capture on valid recoverable Fault n is disabled
CAPT
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value.
0x2
0x3
CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
0x4
0x5
LOCMIN
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection.
LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection.
DS40001882G-page 661
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Value
Name
Description
0x6
DERIV0
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
0x7 CAPTMARK Capture with ramp index as MSB value.
Bits 11:10 – CHSEL[1:0]ꢀRecoverable Fault n Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
CC0
CC1
CC2
CC3
Description
Capture value stored into CC0
Capture value stored into CC1
Capture value stored into CC2
Capture value stored into CC3
Bits 9:8 – HALT[1:0]ꢀRecoverable Fault n Halt Operation
These bits select the halt action for recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
HW
SW
NR
Description
Halt action disabled
Hardware halt action
Software halt action
Non-recoverable fault
Bit 7 – RESTARTꢀRecoverable Fault n Restart
Setting this bit enables restart action for Fault n.
Value
Description
0
1
Fault n restart action is disabled.
Fault n restart action is enabled.
Bits 6:5 – BLANK[1:0]ꢀRecoverable Fault n Blanking Operation
These bits, select the blanking start point for recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
START
RISE
FALL
BOTH
Description
Blanking applied from start of the Ramp period
Blanking applied from rising edge of the waveform output
Blanking applied from falling edge of the waveform output
Blanking applied from each toggle of the waveform output
Bit 4 – QUALꢀRecoverable Fault n Qualification
Setting this bit enables the recoverable Fault n input qualification.
Value
Description
0
1
The recoverable Fault n input is not disabled on CMPx value condition.
The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0).
Bit 3 – KEEPꢀRecoverable Fault n Keep
Setting this bit enables the Fault n keep action.
Value
Description
0
1
The Fault n state is released as soon as the recoverable Fault n is released.
The Fault n state is released at the end of TCC cycle.
Bits 1:0 – SRC[1:0]ꢀRecoverable Fault n Source
These bits select the TCC event input for recoverable Fault n.
Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when
used as a recoverable Fault n input.
Value
0x0
0x1
Name
Description
Fault input disabled
MCEx (x=0,1) event input
Inverted MCEx (x=0,1) event input
DISABLE
ENABLE
INVERT
0x2
DS40001882G-page 662
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Name
Description
0x3
ALTFAULT
Alternate fault (A or B) state at the end of the previous period.
DS40001882G-page 663
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.6 Waveform Extension Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WEXCTRL
0x14
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
DTHS[7:0]
DTLS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
DTIEN2
R/W
0
9
DTIEN1
R/W
0
8
DTIEN0
R/W
0
DTIEN3
R/W
0
Access
Reset
Bit
7
6
5
4
3
2
1
0
OTMX[1:0]
Access
Reset
R/W
0
R/W
0
Bits 31:24 – DTHS[7:0]ꢀDead-Time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
Bits 23:16 – DTLS[7:0]ꢀDead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
Bits 8, 9, 10, 11 – DTIENxꢀDead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
Value
Description
0
No dead-time insertion override.
1
Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
Bits 1:0 – OTMX[1:0]ꢀOutput Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to
31.6.3.7 Waveform Extension.
DS40001882G-page 664
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.7 Driver Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DRVCTRL
0x18
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
FILTERVAL1[3:0]
FILTERVAL0[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
INVEN7
R/W
0
22
INVEN6
R/W
0
21
INVEN5
R/W
0
20
INVEN4
R/W
0
19
INVEN3
R/W
0
18
INVEN2
R/W
0
17
INVEN1
R/W
0
16
INVEN0
R/W
0
Access
Reset
Bit
15
NRV7
R/W
0
14
NRV6
R/W
0
13
NRV5
R/W
0
12
NRV4
R/W
0
11
NRV3
R/W
0
10
NRV2
R/W
0
9
NRV1
R/W
0
8
NRV0
R/W
0
Access
Reset
Bit
7
NRE7
R/W
0
6
NRE6
R/W
0
5
NRE5
R/W
0
4
NRE4
R/W
0
3
NRE3
R/W
0
2
NRE2
R/W
0
1
NRE1
R/W
0
0
NRE0
R/W
0
Access
Reset
Bits 31:28 – FILTERVAL1[3:0]ꢀNon-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0]ꢀNon-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVENxꢀWaveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRVxꢀNRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – NRExꢀNon-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Value
Description
0
1
Non-recoverable fault tri-state the output.
Non-recoverable faults set the output to NRVx level.
DS40001882G-page 665
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.8 Debug control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x1E
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
FDDBD
R/W
0
1
0
DBGRUN
R/W
Access
Reset
0
Bit 2 – FDDBDꢀFault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled. When this bit is written to ‘1’,
OCD break request from the OCD system will trigger non-recoverable fault. When this bit is set, OCD fault protection
is enabled and OCD break request from the OCD system will trigger a non-recoverable fault.
Value
Description
0
1
No faults are generated when TCC is halted in debug mode.
A non recoverable fault is generated and FAULTD flag is set when TCC is halted in debug mode.
Bit 0 – DBGRUNꢀDebug Running State
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
Value
Description
0
1
The TCC is halted when the device is halted in debug mode.
The TCC continues normal operation when the device is halted in debug mode.
DS40001882G-page 666
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.9 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x20
0x00000000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
31
23
30
22
29
28
27
MCEO3
R/W
0
26
MCEO2
R/W
0
25
MCEO1
R/W
0
24
MCEO0
R/W
0
Access
Reset
Bit
21
20
19
MCEI3
R/W
0
18
MCEI2
R/W
0
17
MCEI1
R/W
0
16
MCEI0
R/W
0
Access
Reset
Bit
15
TCEI1
R/W
0
14
TCEI0
R/W
0
13
TCINV1
R/W
0
12
TCINV0
R/W
0
11
10
CNTEO
R/W
0
9
TRGEO
R/W
0
8
OVFEO
R/W
0
Access
Reset
Bit
7
6
5
4
3
2
1
0
CNTSEL[1:0]
EVACT1[2:0]
EVACT0[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – MCEOxꢀMatch or Capture Channel x Event Output Enable
These bits control if the match/capture event on channel x is enabled and will be generated for every match or
capture.
Value
Description
0
1
Match/capture x event is disabled and will not be generated.
Match/capture x event is enabled and will be generated for every compare/capture on channel x.
Bits 16, 17, 18, 19 – MCEIxꢀMatch or Capture Channel x Event Input Enable
These bits indicate if the match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value
Description
0
1
Incoming events are disabled.
Incoming events are enabled.
Bits 14, 15 – TCEIxꢀTimer/Counter Event Input x Enable
This bit is used to enable input event x to the TCC.
Value
Description
0
1
Incoming event x is disabled.
Incoming event x is enabled.
Bits 12, 13 – TCINVxꢀTimer/Counter Event x Invert Enable
This bit inverts the event x input.
Value
Description
0
1
Input event source x is not inverted.
Input event source x is inverted.
Bit 10 – CNTEOꢀTimer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of
counter cycle depending of CNTSEL[1:0] settings.
DS40001882G-page 667
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Description
0
Counter cycle output event is disabled and will not be generated.
1
Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Bit 9 – TRGEOꢀRetrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter
retriggers operation.
Value
Description
0
1
Counter retrigger event is disabled and will not be generated.
Counter retrigger event is enabled and will be generated for every counter retrigger.
Bit 8 – OVFEOꢀOverflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter
reaches the TOP or the ZERO value.
Value
Description
0
1
Overflow/underflow counter event is disabled and will not be generated.
Overflow/underflow counter event is enabled and will be generated for every counter overflow/
underflow.
Bits 7:6 – CNTSEL[1:0]ꢀTimer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
Value
0x0
0x1
0x2
0x3
Name
BEGIN
END
Description
An interrupt/event is generated at begin of each counter cycle
An interrupt/event is generated at end of each counter cycle
BETWEEN An interrupt/event is generated between each counter cycle.
BOUNDARY An interrupt/event is generated at begin of first counter cycle, and end of last counter
cycle.
Bits 5:3 – EVACT1[2:0]ꢀTimer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCE1 event input.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
DIR (asynch)
STOP
DEC
PPW
PWP
FAULT
Description
Event action disabled.
Start, restart or re-trigger TC on event
Direction control
Stop TC on event
Decrement TC on event
Period captured into CC0 Pulse Width on CC1
Period captured into CC1 Pulse Width on CC0
Non-recoverable Fault
Bits 2:0 – EVACT0[2:0]ꢀTimer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCE0 event input 0.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
Description
Event action disabled.
Start, restart or re-trigger TC on event
Count on event.
RETRIGGER
COUNTEV
START
INC
COUNT (async)
-
Start TC on event
Increment TC on EVENT
Count on active state of asynchronous event
Reserved
FAULT
Non-recoverable Fault
DS40001882G-page 668
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.10 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x24
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
31
23
30
22
29
28
27
26
25
24
Access
Reset
Bit
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
Access
Reset
Bit
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
Access
Reset
0
Bit
7
6
5
4
3
2
1
0
ERR
R/W
0
CNT
R/W
0
TRG
R/W
0
OVF
R/W
0
Access
Reset
Bits 16, 17, 18, 19 – MCxꢀMatch or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1ꢀNon-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
1
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0ꢀNon-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
1
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTBꢀRecoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
DS40001882G-page 669
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable
Fault B interrupt.
Value
Description
0
1
The Recoverable Fault B interrupt is disabled.
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTAꢀRecoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable
Fault A interrupt.
Value
Description
0
1
The Recoverable Fault A interrupt is disabled.
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFSꢀNon-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault
State interrupt.
Value
Description
0
1
The Debug Fault State interrupt is disabled.
The Debug Fault State interrupt is enabled.
Bit 10 – UFSꢀNon-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the
Non-Recoverable Update Fault interrupt.
Note:ꢀ This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
Description
0
1
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 2 – CNTꢀCounter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
Value
Description
0
1
The Counter interrupt is disabled.
The Counter interrupt is enabled.
Bit 1 – TRGꢀRetrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
Value
Description
0
1
The Retrigger interrupt is disabled.
The Retrigger interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt
request.
DS40001882G-page 670
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Description
0
1
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
DS40001882G-page 671
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.11 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x28
0x00000000
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
31
23
30
22
29
28
27
26
25
24
Access
Reset
Bit
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
Access
Reset
Bit
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
Access
Reset
0
Bit
7
6
5
4
3
2
1
0
ERR
R/W
0
CNT
R/W
0
TRG
R/W
0
OVF
R/W
0
Access
Reset
Bits 16, 17, 18, 19 – MCxꢀMatch or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
1
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1ꢀNon-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the Non-
Recoverable Fault x interrupt.
Value
Description
0
1
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0ꢀNon-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
1
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTBꢀRecoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
DS40001882G-page 672
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable
Fault B interrupt.
Value
Description
0
1
The Recoverable Fault B interrupt is disabled.
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTAꢀRecoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable
Fault A interrupt.
Value
Description
0
1
The Recoverable Fault A interrupt is disabled.
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFSꢀNon-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
Value
Description
0
1
The Debug Fault State interrupt is disabled.
The Debug Fault State interrupt is enabled.
Bit 10 – UFSꢀNon-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which enables the
Non-Recoverable Update Fault interrupt.
Note:ꢀ This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
Description
0
1
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERRꢀError Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.
Value
Description
0
1
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 2 – CNTꢀCounter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
Value
Description
0
1
The Counter interrupt is disabled.
The Counter interrupt is enabled.
Bit 1 – TRGꢀRetrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.
Value
Description
0
1
The Retrigger interrupt is disabled.
The Retrigger interrupt is enabled.
Bit 0 – OVFꢀOverflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
DS40001882G-page 673
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
Description
1
The Overflow interrupt is enabled.
DS40001882G-page 674
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.12 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x2C
0x00000000
-
Property:ꢀ
Bit
31
23
30
22
29
21
28
20
27
26
25
24
Access
Reset
Bit
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
Access
Reset
Bit
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
Access
Reset
0
Bit
7
6
5
4
3
2
1
0
ERR
R/W
0
CNT
R/W
0
TRG
R/W
0
OVF
R/W
0
Access
Reset
Bits 16, 17, 18, 19 – MCxꢀMatch or Capture Channel x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register
contain a valid capture value.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
Bit 15 – FAULT1ꢀNon-Recoverable Fault x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault x interrupt flag.
Bit 14 – FAULT0ꢀNon-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
1
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTBꢀRecoverable Fault B Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 12 – FAULTAꢀRecoverable Fault A Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
DS40001882G-page 675
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bit 11 – DFSꢀNon-Recoverable Debug Fault State Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Debug Fault State interrupt flag.
Bit 10 – UFSꢀNon-Recoverable Update Fault
This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD).
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Update Fault interrupt flag.
Note:ꢀ This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Bit 3 – ERRꢀError Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the error interrupt flag.
Bit 2 – CNTꢀCounter Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CNT interrupt flag.
Bit 1 – TRGꢀRetrigger Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the re-trigger interrupt flag.
Bit 0 – OVFꢀOverflow Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
DS40001882G-page 676
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.13 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x30
0x00000001
-
Property:ꢀ
Bit
31
23
30
22
29
21
28
20
27
CMP3
R/W
0
26
CMP2
R/W
0
25
CMP1
R/W
0
24
CMP0
R/W
0
Access
Reset
Bit
19
CCBV3
R/W
0
18
CCBV2
R/W
0
17
CCBV1
R/W
0
16
CCBV0
R/W
0
Access
Reset
Bit
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
12
FAULTA
R/W
0
11
10
9
8
FAULT1IN
FAULT0IN
FAULTBIN
FAULTAIN
Access
Reset
R
0
R
0
R
0
R
0
0
Bit
7
PERBV
R/W
0
6
WAVEBV
R/W
5
PATTBV
R/W
0
4
3
2
1
IDX
R
0
STOP
R
DFS
R/W
0
UFS
R/W
0
Access
Reset
0
0
1
Bits 24, 25, 26, 27 – CMPxꢀChannel x Compare Value
This bit reflects the channel x output compare value.
Value
Description
0
1
Channel compare output value is 0.
Channel compare output value is 1.
Bits 16, 17, 18, 19 – CCBVxꢀChannel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBx register. The bit
is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or automatically on an
UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automatically
cleared when the CCx register is read.
Bits 14, 15 – FAULTxꢀNon-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEx bit. For
further details on timer/counter commands, refer to available commands description (31.8.3 CTRLBSET.CMD).
Bit 13 – FAULTBꢀRecoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the
corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will
release the timer/counter.
Bit 12 – FAULTAꢀRecoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
DS40001882G-page 677
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
This bit can be clear by hardware when Fault A action is resumed, or by writing a '1' to this bit when the
corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing this bit will
release the timer/counter.
Bit 11 – FAULT1INꢀNon-Recoverable Fault 1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
Bit 10 – FAULT0INꢀNon-Recoverable Fault 0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
Bit 9 – FAULTBINꢀRecoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
Bit 8 – FAULTAINꢀRecoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
Bit 7 – PERBVꢀPeriod Buffer Valid
This bit is set when a new value is written to the PERB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 6 – WAVEBVꢀWaveform Control Buffer Valid
This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 5 – PATTBVꢀPattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 3 – DFSꢀDebug Fault State
This bit is set by hardware in Debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by writing a '1' to
this bit and when the TCC is not in Debug mode.
When the bit is set, the counter is halted and the Waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
Bit 2 – UFSꢀNon-recoverable Update Fault State
This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit
is cleared by writing a one to this bit.
When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers.
Bit 1 – IDXꢀRamp Index
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit always reads zero. For details on ramp operations, refer to 31.6.3.4 Ramp Operations.
Bit 0 – STOPꢀStop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot
operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value
Description
0
1
Counter is running.
Counter is stopped.
DS40001882G-page 678
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.14 Counter Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COUNT
0x34
0x00000000
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note:ꢀ Prior to any read access, this register must be synchronized by user by writing the according TCC Command
value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – COUNT[23:0]ꢀCounter Value
These bits hold the value of the counter register.
Note:ꢀ When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note:ꢀ This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0 (depicted)
23:4
23:5
23:6
DS40001882G-page 679
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.15 Pattern
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PATT
0x38
0x0000
Property:ꢀ Write-Synchronized
Bit
15
PGV7
R/W
0
14
PGV6
R/W
0
13
PGV5
R/W
0
12
PGV4
R/W
0
11
PGV3
R/W
0
10
PGV2
R/W
0
9
PGV1
R/W
0
8
PGV0
R/W
0
Access
Reset
Bit
7
PGE7
R/W
0
6
PGE6
R/W
0
5
PGE5
R/W
0
4
PGE4
R/W
0
3
PGE3
R/W
0
2
PGE2
R/W
0
1
PGE1
R/W
0
0
PGE0
R/W
0
Access
Reset
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVꢀPattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEꢀPattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override
the corresponding SWAP output with the corresponding PGVn value.
DS40001882G-page 680
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.16 Waveform
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WAVE
0x3C
0x00000000
Property:ꢀ Write-Synchronized
Bit
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
SWAP3
R/W
0
26
SWAP2
R/W
0
25
SWAP1
R/W
0
24
SWAP0
R/W
0
Access
Reset
Bit
19
POL3
R/W
0
18
POL2
R/W
0
17
POL1
R/W
0
16
POL0
R/W
0
Access
Reset
Bit
11
CICCEN3
R/W
10
CICCEN2
R/W
9
CICCEN1
R/W
8
CICCEN0
R/W
Access
Reset
0
0
0
0
Bit
7
CIPEREN
R/W
3
2
1
0
RAMP[1:0]
WAVEGEN[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 24, 25, 26, 27 – SWAPꢀSwap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
Bits 16, 17, 18, 19 – POLꢀChannel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value
Name
Description
0
(single-slope PWM waveform
generation)
Compare output is initialized to ~DIR and set to DIR when TCC
counter matches CCx value
1
0
1
(single-slope PWM waveform
generation)
(dual-slope PWM waveform
generation)
(dual-slope PWM waveform
generation)
Compare output is initialized to DIR and set to ~DIR when TCC
counter matches CCx value.
Compare output is set to ~DIR when TCC counter matches CCx
value
Compare output is set to DIR when TCC counter matches CCx
value.
Bits 8, 9, 10, 11 – CICCENꢀCircular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is
copied-back into the CCx register on UPDATE condition.
Bit 7 – CIPERENꢀCircular Period Enable
Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back
into the PERB register on UPDATE condition.
Bits 5:4 – RAMP[1:0]ꢀRamp Operation
These bits select Ramp operation (RAMP). These bits are not synchronized.
Value
0x0
0x1
Name
RAMP1
RAMP2A
Description
RAMP1 operation
Alternative RAMP2 operation
DS40001882G-page 681
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0x2
Name
RAMP2
Description
RAMP2 operation
0x3
RAMP2C. This bit is only available in variant L devices. Refer to
Critical RAMP2 operation
Configuration Summary for more information.
0x4
-
Reserved
Bits 2:0 – WAVEGEN[2:0]ꢀWaveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if frequency or
PWM waveform generation should be used. These bits are not synchronized.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
NFRQ
Normal Frequency
Match Frequency
Normal PWM
-
PER TOP/Zero
CC0 TOP/Zero
PER TOP/Zero
Toggle
Toggle
Set
Stable
Stable
Clear
-
TOP
TOP
TOP
-
Zero
Zero
Zero
-
MFRQ
NPWM
Reserved
DSCRITICAL
DSBOTTOM
DSBOTH
DSTOP
-
-
-
Dual-slope PWM
Dual-slope PWM
Dual-slope PWM
Dual-slope PWM
PER Zero
~DIR
~DIR
~DIR
~DIR
Stable
Stable
Stable
Stable
–
Zero
Zero
Zero
–
PER Zero
–
PER TOP & Zero
PER Zero
TOP
TOP
DS40001882G-page 682
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.17 Period Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PER
0x40
0xFFFFFFFF
Property:ꢀ Write-Synchronized
Bit
31
30
29
21
28
20
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
PER[17:10]
PER[9:2]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit
7
6
5
4
3
2
1
0
PER[1:0]
DITHER[5:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 23:6 – PER[17:0]ꢀPeriod Value
These bits hold the value of the period buffer register.
Note:ꢀ When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note:ꢀ This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0]ꢀDithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note:ꢀ This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
-
3:0
4:0
5:0 (depicted)
DS40001882G-page 683
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.18 Compare/Capture Channel x
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CC
0x44 + n*0x04 [n=0..3]
0x00000000
Property:ꢀ Write-Synchronized, Read-Synchronized
The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of
operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the
comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBx register when an UPDATE condition
occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
CC[17:10]
CC[9:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
CC[1:0]
DITHER[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:6 – CC[17:0]ꢀChannel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note:ꢀ When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note:ꢀ This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0]ꢀDithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
DS40001882G-page 684
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Note:ꢀ This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
-
3:0
4:0
5:0 (depicted)
DS40001882G-page 685
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.19 Pattern Buffer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PATTB
0x64
0x0000
Property:ꢀ Write-Synchronized, Read-Synchronized
Bit
15
PGVB7
R/W
0
14
PGVB6
R/W
0
13
PGVB5
R/W
0
12
PGVB4
R/W
0
11
PGVB3
R/W
0
10
PGVB2
R/W
0
9
PGVB1
R/W
0
8
PGVB0
R/W
0
Access
Reset
Bit
7
PGEB7
R/W
0
6
PGEB6
R/W
0
5
PGEB5
R/W
0
4
PGEB4
R/W
0
3
PGEB3
R/W
0
2
PGEB2
R/W
0
1
PGEB1
R/W
0
0
PGEB0
R/W
0
Access
Reset
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVBꢀPattern Generation Output Value Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the
PGV register on an UPDATE condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEBꢀPattern Generation Output Enable Buffer
This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into
the PGE register at an UPDATE condition.
DS40001882G-page 686
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.20 Waveform Buffer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WAVEB
0x68
0x00000000
Property:ꢀ Write-Synchronized, Read-Synchronized
Bit
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
SWAPB 3
R/W
26
SWAPB 2
R/W
25
SWAPB 1
R/W
24
SWAPB 0
R/W
Access
Reset
0
0
0
0
Bit
19
POLB3
R/W
0
18
POLB2
R/W
0
17
POLB1
R/W
0
16
POLB0
R/W
0
Access
Reset
Bit
11
CICCENB3
R/W
10
CICCENB2
R/W
9
CICCENB1
R/W
8
CICCENB0
R/W
Access
Reset
0
0
0
0
Bit
7
CIPERENB
R/W
3
2
1
0
RAMPB[1:0]
WAVEGENB[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 24, 25, 26, 27 – SWAPB ꢀSwap DTI output pair x Buffer
These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content in these bits
is copied to the corresponding SWAPx bits on an UPDATE condition.
Bits 16, 17, 18, 19 – POLBꢀChannel Polarity x Buffer
These register bits are the buffer bits for POLx register bits. If double buffering is used, valid content in these bits is
copied to the corresponding POBx bits on an UPDATE condition.
Bits 8, 9, 10, 11 – CICCENBꢀCircular CCx Buffer Enable
These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content in these bits
is copied to the corresponding CICCENx bits on a UPDATE condition.
Bit 7 – CIPERENBꢀCircular Period Enable Buffer
This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this bit is copied
to the corresponding CIPEREN bit on a UPDATE condition.
Bits 5:4 – RAMPB[1:0]ꢀRamp Operation Buffer
These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in these bits is
copied to the corresponding RAMP bits on a UPDATE condition.
Value
0x0
0x1
0x2
0x3
Name
RAMP1
RAMP2A
RAMP2
Description
RAMP1 operation
Alternative RAMP2 operation
RAMP2 operation
Critical RAMP2 operation
RAMP2C. This bit is only available in variant L devices. Refer to
Configuration Summary for more information.
0x4
-
Reserved
DS40001882G-page 687
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bits 2:0 – WAVEGENB[2:0]ꢀWaveform Generation Operation Buffer
These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content in these
bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
NFRQ
Normal Frequency
Match Frequency
Normal PWM
-
PER TOP/Zero
CC0 TOP/Zero
PER TOP/Zero
Toggle
Toggle
Set
Stable
Stable
Clear
-
TOP
TOP
TOP
-
Zero
Zero
Zero
-
MFRQ
NPWM
Reserved
DSCRITICAL
DSBOTTOM
DSBOTH
DSTOP
-
-
-
Dual-slope PWM
Dual-slope PWM
Dual-slope PWM
Dual-slope PWM
PER Zero
~DIR
~DIR
~DIR
~DIR
Stable
Stable
Stable
Stable
–
Zero
Zero
Zero
–
PER Zero
–
PER TOP & Zero
PER Zero
TOP
TOP
DS40001882G-page 688
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.21 Period Buffer Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PERB
0x6C
0xFFFFFFFF
Property:ꢀ Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
21
20
PERB[17:10]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit
15
14
13
12
11
10
9
8
PERB[9:2]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit
7
6
5
4
3
2
1
0
PERB[1:0]
DITHERB[5:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 23:6 – PERB[17:0]ꢀPeriod Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
Note:ꢀ When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note:ꢀ This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERB[5:0]ꢀDithering Buffer Cycle Number
These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is
copied to the PER.DITHER bits on an UPDATE condition.
Note:ꢀ This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
-
3:0
4:0
5:0 (depicted)
DS40001882G-page 689
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.22 Channel x Compare/Capture Buffer Value
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CCB
0x70 + n*0x04 [n=0..3]
0x00000000
Property:ꢀ Write-Synchronized, Read-Synchronized
CCBx is copied into CCx at TCC update time
Bit
31
30
29
28
27
19
26
18
25
17
24
16
Access
Reset
Bit
23
22
21
20
CCB[17:10]
CCB[9:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
CCB[1:0]
DITHERB[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:6 – CCB[17:0]ꢀChannel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer
for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the
corresponding CCBVx status bit.
Note:ꢀ When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note:ꢀ This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERB[5:0]ꢀDithering Buffer Cycle Number
These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits value is
copied to the CCx.DITHER bits on an UPDATE condition.
Note:ꢀ This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
-
3:0
4:0
5:0 (depicted)
DS40001882G-page 690
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.
USB – Universal Serial Bus
32.1
Overview
The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification
supporting both device and embedded host modes.
The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output
endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control,
interrupt, bulk or isochronous. The USB host mode supports up to 8 pipes. The maximum data payload size is
selectable up to 1023 bytes.
Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations used
for the endpoint configurations and data buffers is fully configurable. The amount of memory allocated is dynamic
according to the number of endpoints in use, and the configuration of these. The USB module has a built-in Direct
Memory Access (DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No
CPU or DMA Controller resources are required.
To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the input and
output endpoint with the same address are used in the same direction. The CPU or DMA Controller can then
read/write one data buffer while the USB module writes/reads from the other buffer. This gives double buffered
communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without any software intervention. This reduces the number of interrupts and software intervention
needed for USB transfers.
For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle
and a suspend condition is given. Upon bus resume, the USB module can wake the microcontroller from any sleep
mode.
32.2
Features
•
•
•
•
•
•
•
•
Compatible with the USB 2.1 specification
USB Embedded Host and Device mode
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Supports Link Power Management (LPM-L1) protocol
On-chip transceivers with built-in pull-ups and pull-downs
On-Chip USB serial resistors
1kHz SOF clock available on external pin
Device mode
– Supports 8 IN endpoints and 8 OUT endpoints
– No endpoint size limitations
– Built-in DMA with multi-packet and dual bank for all endpoints
– Supports feedback endpoint
– Supports crystal less clock
•
Host mode
– Supports 8 physical pipes
– No pipe size limitations
– Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree
– Built-in DMA with multi-packet support and dual bank for all pipes
– Supports feedback endpoint
– Supports the USB 2.0 Phase-locked SOFs feature
DS40001882G-page 691
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.3
USB Block Diagram
Figure 32-1.ꢀLS/FS Implementation: USB Block Diagram
USB
SRAM Controller
dedicated bus
AHB Client
AHB Host
User
Interface
APB
device-wide bus
DM
USB 2.0
Core
DP
USB interrupts
SOF 1kHz
NVIC
GCLK_USB
GCLK
System clock domain USB clock domain
32.4
Signal Description
Pin Name
DM
Pin Description
Type
Data -: Differential Data Line - Port
Data +: Differential Data Line + Port
SOF Output
Input/Output
Input/Output
Output
DP
SOF 1kHZ
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
32.5
Product Dependencies
In order to use this peripheral module, other parts of the system must be configured correctly, as described below.
32.5.1 I/O Lines
The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to
assign the USB pins to their peripheral functions.
A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to assign the 1kHz
SOF clock to the peripheral function. The SOF clock is available for device and host mode.
32.5.2 Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes.
DS40001882G-page 692
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
Related Links
16. PM – Power Manager
32.5.3 Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Main Clock module, MCLK, and the default
state of CLK_USB_AHB can be found in the Peripheral Clock Masking.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic
Clock Controller before using the USB.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow
the USB data rate at 12 Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8 MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter
specifications. If crystal-less operation is used in USB device mode, refer to USB Clock Recovery Module.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
15.6.6 Synchronization
32.5.4 DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.
32.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
32.5.6 Events
Not applicable.
32.5.7 Debug Operation
When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB peripheral is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
32.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
•
Device Interrupt Flag (INTFLAG) register
Endpoint Interrupt Flag (EPINTFLAG) register
Host Interrupt Flag (INTFLAG) register
Pipe Interrupt Flag (PINTFLAG) register
Note:ꢀ Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
32.5.9 Analog Connections
Not applicable.
DS40001882G-page 693
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.5.10 Calibration
The output drivers for the DP/DM USB line interface can be fine tuned with calibration values from production
tests. The calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register (PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software
Calibration Area Mapping for further details.
For additional information on Pad Calibration, refer to the Pad Calibration (PADCAL) register.
Related Links
10.3.2 NVM Software Calibration Area Mapping
32.6
Functional Description
32.6.1 USB General Operation
32.6.1.1 Initialization
After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in either device
mode or host mode (CTRLA.MODE).
Figure 32-2.ꢀGeneral States
HW RESET | CTRLA.SWRST
Any state
Idle
CTRLA.ENABLE = 1
CTRLA.MODE
= 0
CTRLA.ENABLE = 0
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE = 1
Device
Host
After a hardware reset, the USB is in the idle state. In this state:
•
•
•
•
The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset.
The module clock is stopped in order to minimize power consumption.
The USB pad is in suspend mode.
The internal states and registers of the device and host are reset.
DS40001882G-page 694
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration values from
the NVM Software Calibration Area.
The USB is enabled by writing a '1' to CTRLA.ENABLE. The USB is disabled by writing a '0' to CTRLA.ENABLE.
The USB is reset by writing a '1' to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the USB will
be reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for details.
The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in the Control
A register (CTRLA.MODE) and the Speed Configuration field in the Control B register (CTRLB.SPDCONF). These
values are taken into account once the USB has been enabled by writing a '1' to CTRLA.ENABLE.
After writing a '1' to CTRLA.ENABLE, the USB enters device mode or host mode (according to CTRLA.MODE).
The USB can be disabled at any time by writing a '0' to CTRLA.ENABLE.
Refer to 32.6.2 USB Device Operations for the basic operation of the device mode.
Refer to 32.6.3 Host Operations for the basic operation of the host mode.
Related Links
10.3.2 NVM Software Calibration Area Mapping
32.6.2 USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more details on
general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1.
32.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach
bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be
written to the CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device address zero.
On successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device.
All further transactions will be directed to this device address. This address should be configured in the Device
Address field in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN)
should be written to one to accept communications directed to this address. DADD.ADDEN is automatically cleared
on receiving a USB reset.
32.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly
through the AHB host (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. For additional information,
refer to Endpoint Description Structure.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field
in the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be
initialized to known values before using the endpoint, so that the USB controller does not read random values from
the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported
to the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for
endpoint transfers.
The RAM Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
•
•
•
•
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
DS40001882G-page 695
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as
multiple packets without software intervention. This reduces the number of interrupts and software intervention
required to manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions
described below unless otherwise noted in this section.
The application software provides the size and address of the RAM buffer to be proceeded by the USB module for
a specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software
intervention.
Figure 32-3.ꢀMulti-Packet Feature - Reduction of CPU Overhead
Data Payload
Without Multi-packet support
Transfer Complete Interrupt
&
Data Processing
Maximum Endpoint size
With Multi-packet support
32.6.2.4 USB Reset
The USB bus reset is initiated by a connected host and managed by hardware.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
•
•
Device Endpoint Configuration (EPCFG) register - except for Endpoint 0
Device Frame Number (FNUM) register
Device Address (DADD) register
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
Endpoint Interrupt Summary (EPINTSMRY) register
Upstream resume bit in the Control B register (CTRLB.UPRSM)
At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register (INTFLAG.EORST).
32.6.2.5 Start-of-Frame
When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame Number
field in the Device Frame Number register (FNUM.FNUM), and the Start-of-Frame interrupt bit in the Device Interrupt
Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag
(FNUM.FNCERR) in the FNUM register is set.
32.6.2.6 Management of SETUP Transactions
When a SETUP token is detected and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the addressed endpoint
is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If the
EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token packet.
When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the
addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is
detected, the USB module returns to idle and waits for the next token packet.
DS40001882G-page 696
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint Interrupt
Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status
register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address
(ADDR). If the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the
PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff
and CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the
next token packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is
the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number
of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC
data is written to the data buffer. If the number of received data is equal or less than the data payload specified by
PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY)
are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable
bit is set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
32.6.2.7 Management of OUT Transactions
Figure 32-4.ꢀOUT Transfer: Data Packet Host to USB Device
Memory Map
HOST
I/O Register
USB I/O Registers
Internal RAM
BULK OUT
EPT 2
BULK OUT
EPT 3
BULK OUT
EPT 1
USB Module
DESCADD
USB Endpoints
Descriptor Table
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
ENDPOINT 1 DATA
ENDPOINT 3 DATA
DP
USB Buffers
DM
time
ENDPOINT 2 DATA
When an OUT token is detected, and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to
idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns
to idle and waits for the next token packet.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor, and waits
for a DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is detected, the USB module
returns to idle and waits for the next token packet.
DS40001882G-page 697
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not isochronous,
a STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in EPINTFLAG
(EPINTFLAG.STALL0) is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types
the PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the incoming data is discarded, and an
ACK handshake is returned to the host.
If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the endpoint is not isochronous, a
NAK handshake is returned to the host.
The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of
received data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the remainders of the received
data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. If a bit-stuff or CRC error is
detected in the packet, the USB module returns to idle and waits for the next token packet.
If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received data bytes,
excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and CRC Error bit in the
Device Bank Status register (STATUS_BK.CRCERR) is set for the addressed endpoint.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and
the number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE no CRC data bytes are written to the data
buffer. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one,
only the first CRC data byte is written to the data buffer If the number of received data is equal or less than the data
payload specified by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and EPSTATUS.DTGLOUT
is toggled if the endpoint is not isochronous. The flag Transmit Complete 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRCPT0) is set for the addressed endpoint.
32.6.2.8 Multi-Packet Transfers for OUT Endpoint
The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal operation. Since
PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when setting up a new transfer.
The total number of bytes to be received must be written to PCKSIZE.MULTI_PACKET_SIZE. This value must be
a multiple of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the
application.
EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management
are as for normal operation.
If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE
after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous.
If the updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction),
EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set.
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USB – Universal Serial Bus
32.6.2.9 Management of IN Transactions
Figure 32-5.ꢀIN Transfer: Data Packet USB Device to Host After Request from Host
Memory Map
I/O Register
HOST
USB I/O Registers
CPU
Internal RAM
ENDPOINT 2 DATA
USB Module
DESCADD
EPT 2
EPT 3
EPT 1
USB Endpoints
Descriptor Table
D
D
A
T
A
1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
A
T
A
0
ENDPOINT 3 DATA
ENDPOINT 1 DATA
DP
DM
USB Buffers
I
I
I
N
T
O
K
E
N
N
T
O
K
E
N
N
T
O
K
E
N
EPT 2
EPT 3
EPT 1
time
When an IN token is detected, and if the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of the
addressed endpoint and if not, the packet is discarded and the USB module returns to idle and waits for the next
token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input endpoint. If the
EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned
to the host and EPINTFLAG.STALL1 is set.
If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK
handshake is returned to the host.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data
pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous.
For non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on the state of EPSTATUS.DTGLIN.
When the number of data bytes specified in endpoint PCKSIZE.BYTE_COUNT is sent, the CRC is appended and
sent to the host.
For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set.
For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK
handshake is not received within 16 bit times, the USB module returns to idle and waits for the next token packet.
If an ACK handshake is successfully received EPSTATUS.BK1RDY is cleared, EPINTFLAG.TRCPT1 is set and
EPSTATUS.DTGLIN is toggled.
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USB – Universal Serial Bus
32.6.2.10 Multi-Packet Transfers for IN Endpoint
The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation. The
Multi-packet size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes that are sent, and
must be written to zero when setting up a new transfer.
When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are fetched. If
PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint PCKSIZE.SIZE, endpoint
BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are transmitted, otherwise PCKSIZE.SIZE
number of bytes are transmitted. If endpoint PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet
sent will be zero-length if the AUTOZLP bit is set.
If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be incremented
by the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be toggled when
the transaction has completed. If a short packet was sent (i.e. the last transaction), MULTI_PACKET_SIZE is
incremented by the data payload. EPSTATUS.BK0/1RDY will be cleared and EPINTFLAG.TRCPT0/1 will be set.
32.6.2.11 Ping-Pong Operation
When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers (banks)
for a given endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in
EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be configured as
dual bank. The data buffer, data address pointer and byte counter from the enabled endpoint are used as Bank 0,
while the matching registers from the disabled endpoint are used as Bank 1.
Figure 32-6.ꢀPing-Pong Overview
Endpoint
single bank
Without Ping Pong
t
Endpoint
dual bank
Bank0
Bank1
With Ping Pong
t
USB data packet
Available time for data processing by CPU
to avoid NACK
The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and
is updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0
or EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY
and EPSTATUS.BK1RDY) are set. The EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled
endpoint direction only.
32.6.2.12 Feedback Operation
Feedback endpoints are endpoints with same the address but in different directions. This is usually used in explicit
feedback mechanism in USB Audio, where a feedback endpoint is associated to one or more isochronous data
endpoints to which it provides feedback service. The feedback endpoint always has the opposite direction from the
data endpoint.
The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback endpoint has the
same endpoint number as the first (lower) data endpoint. A feedback endpoint can be created by configuring an
endpoint with different endpoint size (PCKSIZE.SIZE) and different endpoint type (EPCFG.EPTYPE0/1) for the IN
and OUT direction.
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Example Configuration for Feedback Operation:
•
•
Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64.
Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512.
32.6.2.13 Suspend State and Pad Behavior
The following figure, Pad Behavior, illustrates the behavior of the USB pad in Device mode.
Figure 32-7.ꢀPad Behavior
CTRLA.ENABLE = 1
CTRLB.DETACH = 0
Idle
|
| INTFLAG.SUSPEND = 0
CTRLA.ENABLE = 0
CTRLB.DETACH = 1
|
| INTFLAG.SUSPEND = 1
Active
In Idle state, the pad is in Low Power Consumption mode.
In Active state, the pad is active.
The following figure, Pad Events, illustrates the pad events leading to a PAD state change.
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Figure 32-8.ꢀPad Events
Suspend detected
Cleared on Wakeup
Wakeup detected
Cleared by software to acknowledge the interrupt
Idle
Active
Active
The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend
state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a
non-idle state sets the Wake Up Interrupt bit (INTFLAG.WAKEUP) and wakes the USB pad.
The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It returns to the
Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero.
32.6.2.14 Remote Wakeup
The remote wakeup request (also known as upstream resume) is the only request the device may send on its own
initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host.
First, the USB must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only be sent
after INTFLAG.SUSPEND has been set.
The user may then write a one to the Remote Wakeup bit (CTRLB.UPRSM) to send an Upstream Resume to the host
initiating the wakeup. This will automatically be done by the controller after 5 ms of inactivity on the USB bus.
When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared.
The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume.
In case of a rebroadcast resume initiated by the host, the End of Resume bit (INTFLAG.EORSM) flag is set when the
rebroadcast resume is completed.
In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the
CTRLB.UPRSM is cleared and the upstream resume request is ignored.
32.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in response
by the controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG) register is updated
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in the bank 0 of the addressed endpoint's descriptor. It contains information such as the Best Effort Service
Latency (BESL), the Remote Wake bit (bRemoteWake), and the Link State parameter (bLinkState). Usually, the
LPM transaction uses only the endpoint number 0.
If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power Management
Interrupt bit (INTFLAG.LPMSUSP) bit which indicates that the USB transceiver is suspended, reducing power
consumption. This suspend occurs 9 microseconds after the LPM transaction according to the specification.
To further reduce consumption, it is recommended to stop the USB clock while the device is suspended.
The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected sleep mode
complies with the host latency constraint, refer to the BESL parameter in EXTREG register.
Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section
32.6.2.13 Suspend State and Pad Behavior) except that the remote wakeup duration initiated by USB is shorter
to comply with the Link Power Management specification.
If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag
(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet Interrupt Enable
bit (INTENCLR/SET.LPMNYET) is set.
If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored.
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32.6.2.16 USB Device Interrupt
Figure 32-9.ꢀDevice Interrupt
EPINTFLAG7.STALL
EPINTENSET7.STALL0/STALL1
EPINTENSET7.TRFAIL1
EPINTFLAG7.TRFAIL1
EPINTFLAG7.TRFAIL0
EPINTSMRY
EPINTENSET7.TRFAIL0
ENDPOINT7 EPINTFLAG7.RXSTP
EPINTFLAG7.TRCPT1
EPINT7
EPINT6
EPINTENSET7.RXSTP
EPINTENSET7.TRCPT1
EPINTENSET7.TRCPT0
EPINTFLAG7.TRCPT0
USB EndPoint
Interrupt
EPINTFLAG0.STALL
EPINTENSET0.STALL0/STALL1
EPINTENSET0.TRFAIL1
EPINTFLAG0.TRFAIL1
EPINTFLAG0.TRFAIL0
EPINT1
EPINT0
EPINTENSET0.TRFAIL0
EPINTFLAG0.RXSTP
ENDPOINT0
EPINTENSET0.RXSTP
EPINTENSET0.TRCPT1
EPINTENSET0.TRCPT0
EPINTFLAG0.TRCPT1
EPINTFLAG0.TRCPT0
USB
Interrupt
INTFLAG.LPMSUSP
INTENSET.LPMSUSP
INTFLAG.LPMNYET
INTFLAG.RAMACER
INTENSET.DDISC
INTENSET.RAMACER
INTENSET.UPRSM
INTENSET.EORSM
INTENSET.WAKEUP
INTENSET.EORST
INTENSET.SOF
INTFLAG.UPRSM
INTFLAG
INTFLAG.EORSM
USB Device Interrupt
INTFLAG.WAKEUP
INTFLAG.EORST
*
INTFLAG.SOF
INTFLAGA.MSOF
INTENSET.MSOF
INTFLAG.SUSPEND
INTENSET.SUSPEND
*
Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
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USB – Universal Serial Bus
32.6.3 Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more details on
general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
32.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit (CTRLB.VBUSOK) register when the VBUS is
available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is zero and
even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK will allow
host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE)
register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the
speed of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using the
STATUS.LINESTATE registers.
The Device Connection Interrupt bit (INTFLAG.DCONN) is set if a device connection is detected.
The Device Disconnection Interrupt bit (INTFLAG.DDISC) is set if a device disconnection is detected.
32.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to
"Universal Serial Bus Specification revision 2.1." for more information.
32.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit (CTRLB.BUSRESET). When the
USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all pipes will
be disabled.
If the bus was previously in a suspended state (i.e., the Start of Frame Generation Enable bit (CTRLB.SOFE) is
zero), the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt
flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB
reset.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
All Host Pipe Configuration register (PCFG)
Host Frame Number register (FNUM)
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Host Start-of-Frame Control register (HSOFC)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the
current speed according to the capability of the peripheral.
32.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB
host (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be written
in the Descriptor Address register (DESCADD) by the user. Refer to Pipe Description Structure.
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host
Pipe Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before
using the pipe, so that the USB controller does not read the random values from the RAM.
The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the
device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the
data buffer used for pipe transfers.
The Pipe Bank bit (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported for Control
pipes.
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The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
•
•
•
•
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
32.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n). Pipes are
enabled by writing the Type of the Pipe bit (PCFG.PTYPE) to a value different than 0x0 (disabled).
When a pipe is enabled, the Pipe Freeze bit in the Pipe Status register (PSTATUS.FREEZE) is set. This allows the
user to complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending a GET_DESCRIPTOR USB
request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0),
which the user should use to reconfigure the size of the default control pipe.
32.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns a new
address to the device. The host controller has to send a USB reset to the device and a SET_ADDRESS(addr)
SETUP request with the new address to be used by the device. Once this SETUP transaction is complete, the user
writes the new address to the Pipe Device Address field in the Host Control Pipe register (CTRL_PIPE.PDADDR) in
Pipe descriptor. All following requests by this pipe will be performed using this new address.
32.6.3.7 Suspend and Wakeup
Setting CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames on the USB
bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by setting their
PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all pipes will be inactive. The
user should wait at least 1 complete frame before entering the suspend mode to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the host detects
a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state corresponds to an Upstream
Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG (INTFLAG.UPRSM) is set and the
user must generate a Downstream Resume within 1 ms and for at least 20 ms. It is required to first write a one
to the Send USB Resume bit in CTRLB (CTRLB.RESUME) to respond to the upstream resume with a downstream
resume. Alternatively, the host can resume from a suspend state by sending a Downstream Resume on the USB
bus (CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is
automatically set and the host enters again the active state.
32.6.3.8 Phase-locked SOFs
To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the
USB connection is not in the active state. This does not apply for the disconnected/connected/reset states. It applies
for active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms when the USB connection is in active
state and an integer number of milli-seconds across idle/suspend/resume states.
To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the GCLK_USB is
interrupted, the period of the emitted Start-of-Frame will be erratic.
32.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
•
•
•
SETUP
Data (IN or OUT)
Status (IN or OUT)
The user has to change the pipe token according to each stage using the Pipe Token field in PCFG
(PCFG.PTOKEN).
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For control pipes only, the token is assigned a specific initial data toggle sequence:
•
•
•
SETUP: Data0
IN: Data1
OUT: Data1
32.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN request reception from the host. All the received data from
the device to the host will be stored in the bank provided the bank is empty. The pipe and its descriptor in RAM must
be configured.
The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in PSTATUS
(PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB transfer.
The USB will perform IN requests as long as the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero).
When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be set and
trigger an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set.
PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing a one to the
PINTFLAG.TRCPT0/1 of the addressed pipe.
The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read.
To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear the
PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN transaction will switch to
the next bank. Another IN request will be performed by the host as long as the PSTATUS.BK0/1RDY bit for that bank
is set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be updated accordingly.
The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at
Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and
PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and
PSTATUS.BK0/1 are used.
32.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the bank is filled.
The pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the USB to send
the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the next bank if the OUT pipe is
part of a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
32.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing
of any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in
particular PCFG, and PSTATUS.
32.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit
Fail bit in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in PINTENCLR/
SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register (PINTSMRY) to
find out the pipe which triggered the interrupt. Then the user must check the origin of the interrupt’s bank by
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looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user
knows that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new
transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this
occurs when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is
successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
32.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the
interrupt. Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK
for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to
determine the origin of the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted
packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
32.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is
set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the
Error Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s)
as defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to Host Control Pipe and
Host Status Pipe registers.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the
STATUS_PIPE.ERCNT is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
32.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK and PCKSIZE.SIZE are irrelevant in this configuration. The
user should also set the EXTREG.VARIABLE in the descriptor as described in the EXTREG Register.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is
set. The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference
document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1
SLEEP state, the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.
If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be transmitted
again until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX in the pipe descriptor.
If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is updated in the
pipe descriptor.
All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the PSTATUS.PFREEZE
bit, freezing the pipe before a succeeding operation. The user should unfreeze the pipe to start a new LPM
transaction.
To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or a L1
RESUME by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1 RESUME, the K
STATE duration is given by the BESL bit field in the EXTREG.VARIABLE field. Refer to the EXTREG Register.
When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an UPSTREAM
RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM). The host should proceed
then to a L1 RESUME as described above.
After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation.
DS40001882G-page 708
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.6.3.17 Host Interrupt
Figure 32-10.ꢀHost Interrupt
PINTFLAG7.STALL
PINTENSET.STALL
PINTENSET.PERR
PINTFLAG7.PERR
PINTFLAG7.TRFAIL
PINTFLAG7.TXSTP
PINTFLAG7.TRCPT1
PINTFLAG7.TRCPT0
PINTSMRY
PINTENSET.TRFAIL
PINTENSET.TXSTP
PINTENSET.TRCPT1
PINTENSET.TRCPT0
PIPE7
PINT7
PINT6
USB PIPE
Interrupt
PINTFLAG0.STALL
PINTFLAG0.PERR
PINTENSET.STALL
PINTENSET.PERR
PINTFLAG0.TRFAIL
PINTFLAG0.TXSTP
PINTFLAG0.TRCPT1
PINTFLAG0.TRCPT0
PINT1
PINT0
PINTENSET.TRFAIL
PINTENSET.TXSTP
PINTENSET.TRCPT1
PINTENSET.TRCPT0
PIPE0
USB
Interrupt
INTFLAG.DDISC *
INTFLAG.DCONN *
INTFLAG.RAMACER
INTFLAG.UPRSM
INTFLAG.DNRSM
INTFLAG.WAKEUP *
INTFLAG.RST
INTENSET.DDISC
INTENSET.DCONN
INTENSET.RAMACER
INTENSET.UPRSM
INTENSET.DNRSM
INTENSET.WAKEUP
INTENSET.RST
INTFLAGA
USB Host Interrupt
INTFLAG.HSOF
INTENSET.HSOF
*
Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
DS40001882G-page 709
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.7
Communication Device Host Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
...
CTRLA
Reserved
7:0
MODE
RUNSTDBY
ENABLE
SWRST
SYNCBUSY
QOSCTRL
7:0
7:0
ENABLE
SWRST
DQOS[1:0]
CQOS[1:0]
Reserved
FSMSTATUS
Reserved
0x0C
0x0D
0x0E
...
7:0
FSMSTATE[6:0]
0x23
7:0
15:8
23:16
31:24
7:0
DESCADD[7:0]
DESCADD[15:8]
DESCADD[23:16]
DESCADD[31:24]
0x24
0x28
DESCADD
PADCAL
TRANSN[1:0]
TRANSP[4:0]
15:8
TRIM[2:0]
TRANSN[4:2]
32.8
Communication Device Host Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 710
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronised
Bit
7
MODE
R/W
0
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
0
Bit 7 – MODEꢀOperating Mode
This bit defines the operating mode of the USB.
Value
Description
0
1
USB Device mode
USB Host mode
Bit 2 – RUNSTDBYꢀRun in Standby Mode
This bit is Enable-Protected.
Value
Description
0
1
USB clock is stopped in standby mode.
USB clock is running in standby mode
Bit 1 – ENABLEꢀEnable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is Write-Synchronized.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a '1' to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
DS40001882G-page 711
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.2 Synchronization Busy
Name:ꢀ
SYNCBUSY
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x02
0x00
-
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
Access
Reset
R
0
R
0
Bit 1 – ENABLEꢀSynchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Bit 0 – SWRSTꢀSynchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.
DS40001882G-page 712
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.3 QOS Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
QOSCTRL
0x03
0x000x0F
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DQOS[1:0]
CQOS[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 3:2 – DQOS[1:0]ꢀData Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM
Quality of Service.
Bits 1:0 – CQOS[1:0]ꢀConfiguration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration operation. Refer to
SRAM Quality of Service.
DS40001882G-page 713
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.4 Finite State Machine Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FSMSTATUS
0x0D
0xXXXX
Property:ꢀ Read only
Bit
7
6
5
4
3
2
1
0
FSMSTATE[6:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Bits 6:0 – FSMSTATE[6:0]ꢀFine State Machine Status
These bits indicate the state of the finite state machine of the USB controller.
Value
0x01
0x02
0x04
0x08
0x10
0x20
0x40
Others
Name
OFF (L3)
ON (L0)
SUSPEND (L2)
SLEEP (L1)
DNRESUME
UPRESUME
RESET
Description
Corresponds to the powered-off, disconnected, and disabled state.
Corresponds to the Idle and Active states.
Down Stream Resume.
Up Stream Resume.
USB lines Reset.
Reserved
DS40001882G-page 714
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.5 Descriptor Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DESCADD
0x24
0x00000000
Property:ꢀ PAC Write-Protection
Bit
31
30
29
28
DESCADD[31:24]
R/W R/W
27
26
25
24
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
23
22
21
20
DESCADD[23:16]
R/W R/W
19
18
17
16
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
15
14
13
12
11
10
9
8
DESCADD[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
DESCADD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DESCADD[31:0]ꢀDescriptor Address Value
These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be written
to zero.
DS40001882G-page 715
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.6 Pad Calibration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PADCAL
0x28
0x0000
Property:ꢀ PAC Write-Protection
The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register by software, before enabling the USB, to achieve the specified accuracy.
Refer to NVM Software Calibration Area Mapping for further details.
Refer to for further details.
Bit
15
14
13
TRIM[2:0]
R/W
12
11
10
9
8
TRANSN[4:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
6
5
4
3
2
1
0
TRANSN[1:0]
TRANSP[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:12 – TRIM[2:0]ꢀTrim bits for DP/DM
These bits calibrate the matching of rise/fall of DP/DM.
Bits 10:6 – TRANSN[4:0]ꢀTrimmable Output Driver Impedance N
These bits calibrate the NMOS output impedance of DP/DM drivers.
Bits 4:0 – TRANSP[4:0]ꢀTrimmable Output Driver Impedance P
These bits calibrate the PMOS output impedance of DP/DM drivers.
DS40001882G-page 716
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.9
Device Registers - Common -Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
...
Reserved
0x07
7:0
15:8
7:0
TSTPCKT
ADDEN
TSTK
TSTJ
NREPLY
SPDCONF[1:0]
LPMHDSK[1:0]
DADD[6:0]
UPRSM
GNAK
DETACH
0x08
CTRLB
OPMODE2
0x0A
0x0B
0x0C
0x0D
...
DADD
Reserved
STATUS
7:0
LINESTATE[1:0]
SPEED[1:0]
Reserved
FNUM
0x0F
7:0
FNUM[4:0]
EORSM
EORSM
EORSM
EPINT5
MFNUM[2:0]
0x10
15:8
FNCERR
FNUM[10:5]
0x12
...
Reserved
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
EPINTSMRY
0x13
7:0
RAMACER
UPRSM
UPRSM
UPRSM
EPINT6
WAKEUP
WAKEUP
WAKEUP
EPINT4
EORST
SOF
SOF
MSOF
SUSPEND
LPMNYET
0x14
15:8
LPMSUSP
0x16
...
0x17
7:0
RAMACER
RAMACER
EPINT7
EORST
EORST
EPINT3
MSOF
SUSPEND
LPMNYET
0x18
15:8
LPMSUSP
0x1A
...
0x1B
7:0
SOF
MSOF
SUSPEND
LPMNYET
0x1C
15:8
LPMSUSP
0x1E
...
0x1F
7:0
EPINT2
EPINT1
EPINT0
0x20
15:8
32.10 Device Registers - Common
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description
DS40001882G-page 717
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.1 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x08
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
14
13
12
11
10
9
GNAK
R/W
0
8
OPMODE2
R/W
LPMHDSK[1:0]
Access
Reset
R/W
0
R/W
0
0
Bit
7
TSTPCKT
R/W
6
TSTK
R/W
0
5
TSTJ
R/W
0
4
3
2
1
UPRSM
R/W
0
0
DETACH
R/W
NREPLY
SPDCONF[1:0]
Access
Reset
R
0
R/W
0
R/W
0
0
0
Bits 11:10 – LPMHDSK[1:0]ꢀLink Power Management Handshake
These bits select the Link Power Management Handshake configuration.
Value
0x0
0x1
0x2
0x3
Description
No handshake. LPM is not supported.
ACK
NYET
Reserved
Bit 9 – GNAKꢀGlobal NAK
This bit configures the operating mode of the NAK.
This bit is not synchronized.
Value
Description
0
The handshake packet reports the status of the USB transaction
1
A NAK handshake is answered for each USB transaction regardless of the current endpoint memory
bank status
Bit 8 – OPMODE2ꢀSpecific Operational Mode
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver is in the “disabled bit stuffing and NRZI encoding” operational mode for test
purpose.
Bit 7 – TSTPCKTꢀTest Packet Mode
Value
Description
0
1
The UTMI transceiver is in normal operation Mode.
The UTMI transceiver generates test packets for test purpose.
Bit 6 – TSTKꢀTest Mode K
Value
Description
0
1
The UTMI transceiver is in normal operation Mode.
The UTMI transceiver generates high speed K state for test purpose.
Bit 5 – TSTJꢀTest Mode J
Value
Description
0
1
The UTMI transceiver is in normal operation Mode.
The UTMI transceiver generates high speed J state for test purpose.
Bit 4 – NREPLYꢀNo reply excepted SETUP Token
This bit is cleared by hardware when receiving a SETUP packet.
DS40001882G-page 718
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SAM D21/DA1 Family
USB – Universal Serial Bus
This bit has no effect for any other endpoint but endpoint 0.
Value
Description
0
Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the
USB2.0 standard.
1
Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP.
Bits 3:2 – SPDCONF[1:0]ꢀSpeed Configuration
These bits select the speed configuration.
Value
0x0
0x1
0x2
0x3
Description
FS: Full-speed
LS: Low-speed
HS: High-speed capable
HSTM: High-speed Test Mode (force High-speed mode for test mode)
Bit 1 – UPRSMꢀUpstream Resume
This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.
Value
Description
0
Writing a zero to this bit has no effect.
1
Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
Bit 0 – DETACHꢀDetach
Value
Description
0
1
The device is attached to the USB bus so that communications may occur.
It is the default value at reset. The internal device pull-ups are disabled, removing the device from the
USB bus.
DS40001882G-page 719
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.2 Device Address
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DADD
0x0A
0x00
Property:ꢀ PAC Write-Protection
Bit
7
ADDEN
R/W
0
6
5
4
3
DADD[6:0]
R/W
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – ADDENꢀDevice Address Enable
This bit is cleared when a USB reset is received.
Value
Description
0
Writing a zero will deactivate the DADD field (USB device address) and return the device to default
address 0.
1
Writing a one will activate the DADD field (USB device address).
Bits 6:0 – DADD[6:0]ꢀDevice Address
These bits define the device address. The DADD register is reset when a USB reset is received.
DS40001882G-page 720
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.3 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0C
0x40
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
LINESTATE[1:0]
SPEED[1:0]
Access
Reset
R
R
1
R/W
0
R/W
1
0
Bits 7:6 – LINESTATE[1:0]ꢀUSB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0]ꢀSpeed Status
These bits define the current speed used of the device.
SPEED[1:0]
SPEED STATUS
Full-speed mode
Low-speed mode
High-speed mode
Reserved
0x0
0x1
0x2
0x3
DS40001882G-page 721
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.4 Device Frame Number
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FNUM
0x10
0x0000
Property:ꢀ Read only
Bit
15
FNCERR
R/W
14
6
13
12
11
10
9
8
FNUM[10:5]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit
7
5
FNUM[4:0]
R/W
4
3
2
1
0
MFNUM[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 15 – FNCERRꢀFrame Number CRC Error
This bit is cleared upon receiving a USB reset.
This bit is set when a corrupted frame number (or micro-frame number) is received.
This bit and the SOF (or MSOF) interrupt bit are updated at the same time.
Bits 13:3 – FNUM[10:0]ꢀFrame Number
These bits are cleared upon receiving a USB reset.
These bits are updated with the frame number information as provided from the last SOF packet even if a corrupted
SOF is received.
Bits 2:0 – MFNUM[2:0]ꢀMicro Frame Number
These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF interrupt).
These bits are updated with the micro-frame number information as provided from the last MSOF packet even if a
corrupted MSOF is received.
DS40001882G-page 722
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.5 Device Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x0000
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
8
LPMNYET
R/W
Access
Reset
0
0
Bit
7
RAMACER
R/W
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
3
EORST
R/W
0
2
1
MSOF
R/W
0
0
SUSPEND
R/W
SOF
R/W
0
Access
Reset
0
0
0
Bit 9 – LPMSUSPꢀLink Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
1
The Link Power Management Suspend interrupt is disabled.
The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated
when the Link Power Management Suspend interrupt Flag is set.
Bit 8 – LPMNYETꢀLink Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
1
The Link Power Management Not Yet interrupt is disabled.
The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated
when the Link Power Management Not Yet interrupt Flag is set.
Bit 7 – RAMACERꢀRAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSMꢀUpstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
1
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
DS40001882G-page 723
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 5 – EORSMꢀEnd Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End Of Resume interrupt is disabled.
1
The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of
Resume interrupt Flag is set.
Bit 4 – WAKEUPꢀWake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – EORSTꢀEnd of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End of Reset interrupt is disabled.
1
The End of Reset interrupt is enabled and an interrupt request will be generated when the End of
Reset interrupt Flag is set.
Bit 2 – SOFꢀStart-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Start-of-Frame interrupt is disabled.
1
The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-
Frame interrupt Flag is set.
Bit 1 – MSOFꢀMicro Start-of-Frame Interrupt Enable in High Speed Mode
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Micro Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Micro Start-of-Frame interrupt is disabled.
1
The Micro Start-of-Frame interrupt is enabled and an interrupt request will be generated when the
Micro Start-of-Frame Access interrupt Flag is set.
Bit 0 – SUSPENDꢀSuspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Suspend interrupt is disabled.
1
The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend
interrupt Flag is set.
DS40001882G-page 724
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.6 Device Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x18
0x0000
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
8
LPMNYET
R/W
Access
Reset
0
0
Bit
7
RAMACER
R/W
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
3
EORST
R/W
0
2
1
MSOF
R/W
0
0
SUSPEND
R/W
SOF
R/W
0
Access
Reset
0
0
0
Bit 9 – LPMSUSPꢀLink Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding
interrupt request.
Value
Description
0
1
The Link Power Management Suspend interrupt is disabled.
The Link Power Management Suspend interrupt is enabled.
Bit 8 – LPMNYETꢀLink Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding
interrupt request.
Value
Description
0
1
The Link Power Management Not Yet interrupt is disabled.
The Link Power Management Not Yet interrupt is enabled.
Bit 7 – RAMACERꢀRAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled.
Bit 6 – UPRSMꢀUpstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled.
Bit 5 – EORSMꢀEnd Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt
request.
Value
Description
0
1
The End Of Resume interrupt is disabled.
The End Of Resume interrupt is enabled.
DS40001882G-page 725
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 4 – WAKEUPꢀWake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The Wake Up interrupt is disabled.
The Wake Up interrupt is enabled.
Bit 3 – EORSTꢀEnd of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The End of Reset interrupt is disabled.
The End of Reset interrupt is enabled.
Bit 2 – SOFꢀStart-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The Start-of-Frame interrupt is disabled.
The Start-of-Frame interrupt is enabled.
Bit 1 – MSOFꢀMicro Start-of-Frame Interrupt Enable in High Speed Mode
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Micro Start-of-Frame interrupt Enable bit and enable the corresponding interrupt
request.
Value
Description
0
1
The Micro Start-of-Frame interrupt is disabled.
The Micro Start-of-Frame interrupt is enabled
Bit 0 – SUSPENDꢀSuspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
1
The Suspend interrupt is disabled.
The Suspend interrupt is enabled.
DS40001882G-page 726
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.7 Device Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x01C
0x0000
-
Property:ꢀ
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
8
LPMNYET
R/W
Access
Reset
0
0
Bit
7
RAMACER
R/W
6
5
EORSM
R/W
0
4
WAKEUP
R/W
3
EORST
R/W
0
2
1
MSOF
R/W
0
0
SUSPEND
R/W
UPRSM
SOF
R/W
0
Access
Reset
R/W
0
0
0
0
Bit 9 – LPMSUSPꢀLink Power Management Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK handshake) and
has entered the Suspended state and will generate an interrupt if INTENCLR/SET.LPMSUSP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMSUSP Interrupt Flag.
Bit 8 – LPMNYETꢀLink Power Management Not Yet Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake is NYET)
and will generate an interrupt if INTENCLR/SET.LPMNYET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMNYET Interrupt Flag.
Bit 7 – RAMACERꢀRAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an interrupt if
INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSMꢀUpstream Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an interrupt if
INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – EORSMꢀEnd Of Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will generate an
interrupt if INTENCLR/SET.EORSM is one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUPꢀWake Up Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an interrupt if
INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
DS40001882G-page 727
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 3 – EORSTꢀEnd of Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “End of Reset” has been detected and will generate an interrupt if INTENCLR/
SET.EORST is one.
Writing a zero to this bit has no effect.
Bit 2 – SOFꢀStart-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Start-of-Frame” has been detected (every 1 ms) and will generate an interrupt if
INTENCLR/SET.SOF is one.
The FNUM is updated.
Writing a zero to this bit has no effect.
Bit 1 – MSOFꢀMicro Start-of-Frame Interrupt Flag in High Speed Mode
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Micro Start-of-Frame” has been detected (every 125 us) and will generate an interrupt if
INTENCLR/SET.MSOF is one.
The MFNUM register is updated.The FNUM register is unchanged.
Writing a zero to this bit has no effect.
Bit 0 – SUSPENDꢀSuspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms) and will
generate an interrupt if INTENCLR/SET.SUSPEND is one.
Writing a zero to this bit has no effect.
DS40001882G-page 728
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.8 Endpoint Interrupt Summary
Name:ꢀ
EPINTSMRY
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x20
0x0000
-
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
EPINT7
EPINT6
EPINT5
EPINT4
EPINT3
EPINT2
EPINT1
EPINT0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINTꢀEndPoint Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. Refer to the EPINTFLAGn register in the
Device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.
DS40001882G-page 729
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.11 Device Endpoint Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
...
Reserved
EPCFGn
Reserved
0xFF
0x0100
0x0101
...
7:0
NYETDIS
EPTYPE1[2:0]
EPTYPE0[2:0]
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
EPSTATUSCLRn
EPSTATUSSETn
EPSTATUSn
7:0
7:0
7:0
7:0
7:0
7:0
BK1RDY
BK1RDY
BK1RDY
BK0RDY
BK0RDY
BK0RDY
STALL1
STALL1
STALL1
STALLRQ1
STALLRQ1
STALLRQ1
STALL0
STALLRQ0
STALLRQ0
STALLRQ0
RXSTP
CURBK
CURBK
CURBK
TRFAIL0
TRFAIL0
TRFAIL0
DTGLIN
DTGLIN
DTGLIN
TRCPT1
TRCPT1
TRCPT1
DTGLOUT
DTGLOUT
DTGLOUT
TRCPT0
EPINTFLAGn
TRFAIL1
TRFAIL1
TRFAIL1
EPINTENCLRn
EPINTENSETn
STALL0
RXSTP
TRCPT0
STALL0
RXSTP
TRCPT0
32.12 Device Endpoint Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description
DS40001882G-page 730
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.1 Device Endpoint Configuration register n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPCFGn
0x100
0x00
Property:ꢀ PAC Write-Protection
Bit
7
NYETDIS
R/W
6
5
4
3
2
1
0
EPTYPE1[2:0]
EPTYPE0[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – NYETDISꢀNYET token disable
Value
Description
0
Disable the “NYETDIS” feature: In high-speed, handshake will be handled according to the USB2.0
standard.
1
Enable the “NYETDIS” feature: An ack handshake will be sent instead of an NYET handshake in
high-speed mode.
Bits 6:4 – EPTYPE1[2:0]ꢀEndpoint Type for IN direction
These bits contains the endpoint type for IN direction.
Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Bank1 is disabled.
Bank1 is enabled and configured as Control IN.
Bank1 is enabled and configured as Isochronous IN.
Bank1 is enabled and configured as Bulk IN.
Bank1 is enabled and configured as Interrupt IN.
Bank1 is enabled and configured as Dual-Bank OUT
(Endpoint type is the same as the one defined in EPTYPE0)
Reserved
0x6-0x7
Bits 2:0 – EPTYPE0[2:0]ꢀEndpoint Type for OUT direction
These bits contains the endpoint type for OUT direction.
Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged.
Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Bank0 is disabled.
Bank0 is enabled and configured as Control SETUP / Control OUT.
Bank0 is enabled and configured as Isochronous OUT.
Bank0 is enabled and configured as Bulk OUT.
Bank0 is enabled and configured as Interrupt OUT.
Bank0 is enabled and configured as Dual Bank IN
(Endpoint type is the same as the one defined in EPTYPE1)
Reserved
0x6-0x7
DS40001882G-page 731
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.2 EndPoint Status Clear n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPSTATUSCLRn
0x104
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
CURBK
W
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
DTGLIN
DTGLOUT
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
0
Bit 7 – BK1RDYꢀBank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDYꢀBank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1ꢀSTALL bank 1 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0ꢀSTALL bank 0 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBKꢀCurrent Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
Bit 1 – DTGLINꢀData Toggle IN Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUTꢀData Toggle OUT Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
DS40001882G-page 732
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.3 EndPoint Status Set n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPSTATUSSETn
0x105
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
CURBK
W
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
DTGLIN
DTGLOUT
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
0
Bit 7 – BK1RDYꢀBank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDYꢀBank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1ꢀSTALL Request bank 1 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0ꢀSTALL Request bank 0 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBKꢀCurrent Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.CURBK bit.
Bit 1 – DTGLINꢀData Toggle IN Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUTꢀData Toggle OUT Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the EPSTATUS.DTGLOUT bit.
DS40001882G-page 733
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.4 EndPoint Status n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPSTATUSn
0x106
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
Access
Reset
R
0
R
0
R
0
R
2
R
0
R
0
R
0
Bit 7 – BK1RDYꢀBank 1 is ready
For Control/OUT direction Endpoints, the bank is empty.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
Value
0
Description
The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in.
1
The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
Bit 6 – BK0RDYꢀBank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
Value
Description
0
The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For
Control/OUT direction Endpoints, the bank is empty.
The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
1
Bits 4, 5 – STALLRQꢀSTALL bank x request
Writing a zero to the bit EPSTATUSCLR.STALLRQ will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
Value
Description
0
Disable STALLRQx feature.
1
Enable STALLRQx feature: a STALL handshake will be sent to the host in regards to bank x.
Bit 2 – CURBKꢀCurrent Bank
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Writing a one to the bit EPSTATUSSET.CURBK will set this bit.
Value
Description
0
1
The bank0 is the bank that will be used in the next single/multi USB packet.
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 1 – DTGLINꢀData Toggle IN Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit.
Value
Description
0
1
The PID of the next expected IN transaction will be zero: data 0.
The PID of the next expected IN transaction will be one: data 1.
Bit 0 – DTGLOUTꢀData Toggle OUT Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit.
DS40001882G-page 734
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
Value
Description
0
1
The PID of the next expected OUT transaction will be zero: data 0.
The PID of the next expected OUR transaction will be one: data 1.
DS40001882G-page 735
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.5 Device EndPoint Interrupt Flag n
Name:ꢀ
EPINTFLAGn
Offset:ꢀ
Reset:ꢀ
Property:ꢀ
0x107
0x00
-
Bit
7
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
2
TRFAIL0
R/W
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
0
2
Bits 5, 6 – STALLꢀTransmit Stall x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one.
EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – RXSTPꢀReceived Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the RXSTP Interrupt Flag.
Bits 2, 3 – TRFAILꢀTransfer Fail x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is one.
EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is
"0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPTꢀTransfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT is one.
EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
DS40001882G-page 736
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.6 Device EndPoint Interrupt Enable n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPINTENCLRn
0x108
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Bit
7
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
2
TRFAIL0
R/W
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
0
2
Bits 5, 6 – STALLꢀTransmit STALL x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the Transmit
Stall x Interrupt Flag is set.
Bit 4 – RXSTPꢀReceived Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled and an interrupt request will be generated when the Received
Setup Interrupt Flag is set.
Bits 2, 3 – TRFAILꢀTransfer Fail x Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail bank x interrupt is disabled.
1
The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Fail x Interrupt Flag is set.
Bits 0, 1 – TRCPTꢀTransfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
1
The Transfer Complete bank x interrupt is disabled.
The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete x Interrupt Flag is set.
DS40001882G-page 737
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.7 Device Interrupt EndPoint Set n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EPINTENSETn
0x109
0x0000
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by
USB reset or when EPEN[n] is zero.
Bit
7
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
2
TRFAIL0
R/W
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
0
2
Bits 5, 6 – STALLꢀTransmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
Value
Description
0
1
The Transmit Stall x interrupt is disabled.
The Transmit Stall x interrupt is enabled.
Bit 4 – RXSTPꢀReceived Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value
Description
0
1
The Received Setup interrupt is disabled.
The Received Setup interrupt is enabled.
Bits 2, 3 – TRFAILꢀTransfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
1
The Transfer Fail interrupt is disabled.
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPTꢀTransfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
Value
Description
0
1
The Transfer Complete bank x interrupt is disabled.
The Transfer Complete bank x interrupt is enabled.
DS40001882G-page 738
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.13 Endpoint Descriptor Structure
Data Buffers
EPn BK1
EPn BK0
Endpoint
descriptors
Reserved
STATUS_BK
Reserved
Bank1
Bank0
PCKSIZE
(2 x 0xn0) + 0x10
ADDR
Reserved
STATUS_BK
EXTREG
PCKSIZE
ADDR
2 x 0xn0
Reserved
STATUS_BK
Reserved
PCKSIZE
ADDR
+0x01B
+0x01A
+0x018
+0x014
+0x010
+0x00B
+0x00A
+0x008
+0x004
+0x000
Bank1
Bank0
Reserved
STATUS_BK
EXTREG
PCKSIZE
ADDR
DESCADD
DS40001882G-page 739
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.14 Device Endpoint RAM Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
23:16
31:24
7:0
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
0x00
ADDR
BYTE_COUNT[7:0]
BYTE_COUNT[13:8]
15:8
23:16
31:24
7:0
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
0x04
PCKSIZE
MULTI_PACKET_SIZE[9:2]
SIZE[2:0]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[3:0]
0x08
0x0A
EXTREG
15:8
7:0
VARIABLE[10:4]
STATUS_BK
ERRORFLOW CRCERR
32.15 Device Endpoint RAM Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 740
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.1 Address of Data Buffer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x00
0xXXXXXXX
Property:ꢀ NA
Old address offset 0x00 and 0x10
Bit
31
30
29
28
27
26
25
24
ADDR[31:24]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
23
22
21
20
19
18
17
16
ADDR[23:16]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
15
14
13
12
11
10
9
8
ADDR[15:8]
ADDR[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bits 31:0 – ADDR[31:0]ꢀData Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM. The two least significant bits must
be zero to ensure the start address is 32-bit aligned.
DS40001882G-page 741
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.2 Packet Size
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PCKSIZE
0x04
0xXXXXXXXX
Property:ꢀ NA
Original offset 0x04 & 0x14
Bit
31
AUTO_ZLP
R/W
30
29
SIZE[2:0]
R/W
28
27
26
25
24
MULTI_PACKET_SIZE[13:10]
Access
Reset
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
x
0
Bit
23
22
21
20
19
18
17
16
MULTI_PACKET_SIZE[9:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
MULTI_PACKET_SIZE[1:0]
BYTE_COUNT[13:8]
Access
Reset
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
BYTE_COUNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
Bit 31 – AUTO_ZLPꢀAutomatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the endpoint.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints only. When
disabled the handshake should be managed by firmware.
Value
Description
0
1
Automatic Zero Length Packet is disabled.
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0]ꢀEndpoint size
These bits contains the maximum packet size of the endpoint.
Value
Description
0x0
8 Byte
0x1
16 Byte
0x2
32 Byte
0x3
0x4
0x5
0x6
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1023 Byte(1)
0x7
Note:ꢀ 1. For isochronous endpoint only.
Bits 27:14 – MULTI_PACKET_SIZE[13:0]ꢀMultiple Packet Size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be
written to zero when setting up a new transfer.
For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
DS40001882G-page 742
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bits 13:0 – BYTE_COUNT[13:0]ꢀByte Count
These bits define the 14-bit value that is used for the byte count.
For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or
SETUP transaction.
DS40001882G-page 743
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.3 Extended Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EXTREG
0x08
0xXXXXXXX
Property:ꢀ NA
Bit
15
14
13
12
11
10
9
8
VARIABLE[10:4]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
VARIABLE[3:0]
SUBPID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
x
Bits 14:4 – VARIABLE[10:0]ꢀVariable field send with extended token
These bits define the VARIABLE field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the VARIABLE field should be read as described below.
VARIABLES
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
bLinkState (1)
BESL (2)
bRemoteWake (1)
Reserved
VARIABLE[10:9]
1. For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
2. For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0]ꢀSUBPID field send with extended token
These bits define the SUBPID field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
DS40001882G-page 744
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.4 Device Status Bank
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS_BK
0x0A
0xXXXXXXX
Property:ꢀ NA
Original offset 0x0A & 0x1A
Bit
7
6
5
4
3
2
1
0
CRCERR
R/W
ERRORFLOW
Access
Reset
R/W
x
x
Bit 1 – ERRORFLOWꢀError Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
Value
Description
0
1
No Error Flow detected.
A Error Flow has been detected.
Bit 0 – CRCERRꢀCRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
0.2.5 Host Registers - Common
Value
Description
0
1
No CRC Error.
CRC Error detected.
DS40001882G-page 745
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.16 Host Registers - Common - Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
...
Reserved
0x07
AUTORESUM
E
7:0
TSTK
TSTJ
SPDCONF[1:0]
RESUME
0x08
CTRLB
15:8
7:0
L1RESUME
VBUSOK
BUSRESET
SOFE
0x0A
0x0B
0x0C
0x0D
...
HSOFC
Reserved
STATUS
FLENCE
FLENC[3:0]
7:0
LINESTATE[1:0]
SPEED[1:0]
Reserved
0x0F
7:0
15:8
7:0
FNUM[4:0]
DNRSM
MFNUM[2:0]
DDISC
0x10
FNUM
FNUM[10:5]
0x12
0x13
FLENHIGH
Reserved
FLENHIGH[7:0]
7:0
RAMACER
RAMACER
RAMACER
EPINT7
UPRSM
UPRSM
UPRSM
EPINT6
WAKEUP
WAKEUP
WAKEUP
EPINT4
RST
HSOF
HSOF
HSOF
EPINT2
0x14
INTENCLR
Reserved
INTENSET
Reserved
INTFLAG
Reserved
PINTSMRY
15:8
DCONN
DCONN
0x16
...
0x17
7:0
DNRSM
DNRSM
EPINT5
RST
RST
0x18
15:8
DDISC
0x1A
...
0x1B
7:0
0x1C
15:8
DDISC
DCONN
EPINT0
0x1E
...
0x1F
7:0
EPINT3
EPINT1
0x20
15:8
32.17 Host Registers - Common - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 746
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.1 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x08
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
7
14
13
12
11
L1RESUME
R/W
10
VBUSOK
R/W
9
8
SOFE
R/W
0
BUSRESET
Access
Reset
R/W
0
0
0
Bit
6
TSTK
R/W
0
5
TSTJ
R/W
0
4
3
2
1
RESUME
R/W
0
AUTORESUME
SPDCONF[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
0
Bit 11 – L1RESUMEꢀSend USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation is
enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits field also
known as BESL (See LPM ECN).See the EXTREG Register.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
Bit 10 – VBUSOKꢀVBUS is OK
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST
is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
Value
Description
0
1
The USB module is notified that the VBUS on the USB line is not powered.
The USB module is notified that the VBUS on the USB line is powered.
Bit 9 – BUSRESETꢀSend USB Reset
Value
Description
0
Reset generation is disabled. It is written to zero when the USB reset is completed or when a device
disconnection is detected. Writing zero has no effect.
Generates a USB Reset on the USB bus.
1
Bit 8 – SOFEꢀStart-of-Frame Generation Enable
Value
Description
0
1
The SOF generation is disabled and the USB bus is in suspend state.
Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is
automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume
(INTFLAG.DNRSM) or at the end of L1 resume.
Bit 6 – TSTKꢀTest mode K
Value
Description
0
1
The UTMI transceiver is in normal operation Mode
The UTMI transceiver generates high speed K state for test purposes.
Bit 5 – TSTJꢀTest mode J
Value
Description
0
1
The UTMI transceiver is in normal operation Mode
The UTMI transceiver generates high speed J state for test purposes.
Bit 4 – AUTORESUMEꢀAuto Resume Enable
DS40001882G-page 747
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
Value
Description
0
1
The Auto Resume is disabled.
Enable Auto Resume
Bits 3:2 – SPDCONF[1:0]ꢀSpeed Configuration for Host
These bits select the host speed configuration as shown below
Value
0x0
0x1
0x2
0x3
Description
Low, Full and High Speed capable
Reserved
Reserved
Low and Full Speed capable
Bit 1 – RESUMEꢀSend USB Resume
Writing 0 to this bit has no effect.
1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
DS40001882G-page 748
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.2 Host Start-of-Frame Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
HSOFC
0x0A
0x00
Property:ꢀ PAC Write-Protection
During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is
recommended to check the register value, and write this register again if necessary. This register is cleared upon a
USB reset.
Bit
7
FLENCE
R/W
6
5
4
3
2
1
0
FLENC[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – FLENCEꢀFrame Length Control Enable
When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note:ꢀ In Low Speed mode, FLENCE must be '0'.
FLENCE Frame Timing
Internal Frame Length Down-Counter Load Value
0
0
Internal Frame Length (Full Speed)
11999 (1ms frame rate at 12MHz)
59999 (1ms frame rate at 60MHz)
7499 (0.125ms micro-frame rate at 60MHz)
FLENC[3:0]
Internal Frame Length in Low and Full speed
Internal Frame Length in High speed
Beginning of Frame
1
Internal Frame Length with Frame correction
11999 + FLENC[3:0] at all speeds.
Value
Description
0
Start-of-Frame is generated every 1ms.
1
Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
Bits 3:0 – FLENC[3:0]ꢀFrame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is
'1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.
DS40001882G-page 749
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.3 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x0C
0x00
Property:ꢀ Read only
Bit
7
6
5
4
3
2
1
0
LINESTATE[1:0]
SPEED[1:0]
Access
Reset
R
0
R
0
R/W
0
R/W
0
Bits 7:6 – LINESTATE[1:0]ꢀUSB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0]ꢀSpeed Status
These bits define the current speed used by the host.
SPEED[1:0]
Speed Status
0x0
0x1
0x2
0x3
Full-speed mode
Low-speed mode High-speed mode
Low-speed mode
Reserved
DS40001882G-page 750
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.4 Host Frame Number
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FNUM
0x10
0x0000
Property:ꢀ PAC Write-Protection
Bit
15
7
14
6
13
12
11
10
9
8
FNUM[10:5]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
5
FNUM[4:0]
R/W
4
3
2
1
0
MFNUM[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 13:3 – FNUM[10:0]ꢀFrame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the FNUM
field takes its new value and the MFNUM bits are cleared.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
Bits 2:0 – MFNUM[2:0]ꢀMicro Frame Number
These bits are tied to zero when operating in full-speed mode.
These bits contains the current Micro Frame number (can vary from 0 to 7) updated every 125 us.
DS40001882G-page 751
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.5 Host Frame Length
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
FLENHIGH
0x12
0x00
Property:ꢀ Read-Only
Bit
7
6
5
4
3
2
1
0
FLENHIGH[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 7:0 – FLENHIGH[7:0]ꢀFrame Length
These bits contains the 8 high-order bits of the internal frame counter.
Table 32-1.ꢀCounter Description vs. Speed
Host Register
Description
STATUS.SPEED
Full Speed
Full Speed
High Speed
With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF generation every
1 ms.
With a USB clock running at 60MHz, counter length is 60000 to ensure a SOF generation every
1 ms.
With a USB clock running at 60MHz, counter length is 7500 to ensure a SOF generation every
125 μs.
DS40001882G-page 752
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.6 Host Interrupt Enable Register Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x14
0x0000
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
Access
Reset
Bit
7
RAMACER
R/W
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
3
2
HSOF
R/W
0
1
0
RST
R/W
0
Access
Reset
0
0
Bit 9 – DDISCꢀDevice Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding
interrupt request.
Value
Description
0
1
The Device Disconnection interrupt is disabled.
The Device Disconnection interrupt is enabled and an interrupt request will be generated when the
Device Disconnection interrupt Flag is set.
Bit 8 – DCONNꢀDevice Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled and an interrupt request will be generated when the Device
Connection interrupt Flag is set.
Bit 7 – RAMACERꢀRAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSMꢀUpstream Resume from Device Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
1
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
DS40001882G-page 753
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USB – Universal Serial Bus
Bit 5 – DNRSMꢀDown Resume Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Down Resume interrupt is disabled.
1
The Down Resume interrupt is enabled and an interrupt request will be generated when the Down
Resume interrupt Flag is set.
Bit 4 – WAKEUPꢀWake Up Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – RSTꢀBUS Reset Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Bus Reset interrupt is disabled.
1
The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset
interrupt Flag is set.
Bit 2 – HSOFꢀHost Start-of-Frame Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Host Start-of-Frame interrupt is disabled.
1
The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host
Start-of-Frame interrupt Flag is set.
DS40001882G-page 754
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.7 Host Interrupt Enable Register Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x18
0x0000
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
Access
Reset
Bit
7
RAMACER
R/W
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
3
2
HSOF
R/W
0
1
0
RST
R/W
0
Access
Reset
0
0
Bit 9 – DDISCꢀDevice Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
Value
Description
0
1
The Device Disconnection interrupt is disabled.
The Device Disconnection interrupt is enabled.
Bit 8 – DCONNꢀDevice Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
Value
Description
0
1
The Device Connection interrupt is disabled.
The Device Connection interrupt is enabled.
Bit 7 – RAMACERꢀRAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
Value
Description
0
1
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled.
Bit 6 – UPRSMꢀUpstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
Value
Description
0
1
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled.
Bit 5 – DNRSMꢀDown Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
Value
Description
0
1
The Down Resume interrupt is disabled.
The Down Resume interrupt is enabled.
Bit 4 – WAKEUPꢀWake Up Interrupt Enable
Writing a zero to this bit has no effect.
DS40001882G-page 755
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Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request.
Value
Description
0
1
The WakeUp interrupt is disabled.
The WakeUp interrupt is enabled.
Bit 3 – RSTꢀBus Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
Value
Description
0
1
The Bus Reset interrupt is disabled.
The Bus Reset interrupt is enabled.
Bit 2 – HSOFꢀHost Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt.
Value
Description
0
1
The Host Start-of-Frame interrupt is disabled.
The Host Start-of-Frame interrupt is enabled.
DS40001882G-page 756
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.8 Host Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x1C
0x0000
-
Property:ꢀ
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
Access
Reset
Bit
7
RAMACER
R/W
6
5
DNRSM
R/W
0
4
WAKEUP
R/W
3
2
HSOF
R/W
0
1
0
UPRSM
RST
R/W
0
Access
Reset
R/W
0
0
0
Bit 9 – DDISCꢀDevice Disconnection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the device has been removed from the USB Bus and will generate an interrupt if INTENCLR/
SET.DDISC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DDISC Interrupt Flag.
Bit 8 – DCONNꢀDevice Connection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if INTENCLR/
SET.DCONN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DCONN Interrupt Flag.
Bit 7 – RAMACERꢀRAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if INTENCLR/
SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSMꢀUpstream Resume from the Device Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has received an Upstream Resume signal from the Device and will generate an
interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – DNRSMꢀDown Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/SET.DRSM is
one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUPꢀWake Up Interrupt Flag
This flag is cleared by writing a one.
This flag is set when:
l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected.
l The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected.
l The host controller is in operational state (VBUSOK is one) and an device connection is detected.
In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one.
DS40001882G-page 757
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SAM D21/DA1 Family
USB – Universal Serial Bus
Writing a zero to this bit has no effect.
Bit 3 – RSTꢀBus Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Bus “Reset” has been sent to the Device and will generate an interrupt if INTENCLR/SET.RST
is one.
Writing a zero to this bit has no effect.
Bit 2 – HSOFꢀHost Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Host Start-of-Frame” in Full Speed or a keep-alive in Low Speed has been sent (every 1
ms) and will generate an interrupt if INTENCLR/SET.HSOF is one.
The value of the FNUM register is updated.
Writing a zero to this bit has no effect.
DS40001882G-page 758
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.9 Pipe Interrupt Summary
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PINTSMRY
0x20
0x0000
Property:ꢀ Read-only
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
EPINT7
EPINT6
EPINT5
EPINT4
EPINT3
EPINT2
EPINT1
EPINT0
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINT
The flag EPINTn is set when an interrupt is triggered by the pipe n. See the PINTFLAG register in the Host Pipe
Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.
DS40001882G-page 759
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.18 Host Registers - Pipe - Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
...
Reserved
PCFGn
0xFF
0x0100
0x0101
...
7:0
PTYPE[2:0]
BK
PTOKEN[1:0]
Reserved
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
BINTERVAL
PSTATUSCLR
PSTATUSSET
PSTATUS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BINTERVAL[7:0]
PFREEZE
BK1RDY
BK1RDY
BK1RDY
BK0RDY
BK0RDY
BK0RDY
CURBK
CURBK
CURBK
TRFAIL
TRFAIL
TRFAIL
DTGL
DTGL
PFREEZE
PFREEZE
TXSTP
DTGL
PINTFLAG
STALL
STALL
STALL
PERR
PERR
PERR
TRCPT1
TRCPT1
TRCPT1
TRCPT0
TRCPT0
TRCPT0
PINTENCLR
PINTENSET
TXSTP
TXSTP
32.19 Host Registers - Pipe - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description
DS40001882G-page 760
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.1 Host Pipe n Configuration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PCFGn
0x100
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
PTYPE[2:0]
R/W
3
2
BK
R/W
0
1
0
PTOKEN[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 5:3 – PTYPE[2:0]ꢀType of the Pipe
These bits contains the pipe type.
PTYPE[2:0]
Description
0x0
Pipe is disabled
0x1
0x2
0x3
0x4
0x5
0x06-0x7
Pipe is enabled and configured as CONTROL
Pipe is enabled and configured as ISO
Pipe is enabled and configured as BULK
Pipe is enabled and configured as INTERRUPT
Pipe is enabled and configured as EXTENDED
Reserved
These bits are cleared upon sending a USB reset.
Bit 2 – BKꢀPipe Bank
This bit selects the number of banks for the pipe.
For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out transactions.
This bit is cleared when a USB reset is sent.
BK (1)
Description
0x0
0x1
Single-bank endpoint
Dual-bank endpoint
1. Bank field is ignored when PTYPE is configured as EXTENDED.
Value
Description
0
1
A single bank is used for the pipe.
A dual bank is used for the pipe.
Bits 1:0 – PTOKEN[1:0]ꢀPipe Token
These bits contains the pipe token.
PTOKEN[1:0](1)
Description
0x0
0x1
0x2
0x3
SETUP(2)
IN
OUT
Reserved
1. PTOKEN field is ignored when PTYPE is configured as EXTENDED.
2. Available only when PTYPE is configured as CONTROL
Theses bits are cleared upon sending a USB reset.
DS40001882G-page 761
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.2 Interval for the Bulk-Out/Ping Transaction
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
BINTERVAL
0x103
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BINTERVAL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BINTERVAL[7:0]ꢀBINTERVAL
These bits contains the Ping/Bulk-out period.
These bits are cleared when a USB reset is sent or when PEN[n] is zero.
BINTERVAL Description
=0
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the peripheral
One OUT token is sent every BINTERVAL frame until it is acked by the peripheral
PCFGn.PINGEN BINTERVAL Description
0
0
1
1
=0
>0
=0
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the
peripheral
One OUT token is sent every BINTERVAL micro frame until it is acked by the
peripheral
Multiple consecutive PING token is sent in the same frame until it is acked by the
peripheral
One PING token is sent every BINTERVAL frame until it is acked by the peripheral
Depending from the type of pipe the desired period is defined as:
PTYPE
Description
Interrupt
1 ms to 255 ms
Isochronous
Bulk or control
EXT LPM
2^(Binterval) * 1 ms
1 ms to 255 ms
bInterval ignored. Always 1 ms when a NYET is received.
DS40001882G-page 762
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32.19.3 Pipe Status Clear n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PSTATUSCLR
0x104
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
CURBK
W
1
0
DTGL
W
BK1RDY
BK0RDY
PFREEZE
Access
Reset
W
0
W
0
W
0
0
0
Bit 7 – BK1RDYꢀBank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK1RDY bit.
Bit 6 – BK0RDYꢀBank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK0RDY bit.
Bit 4 – PFREEZEꢀPipe Freeze Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.PFREEZE bit.
Bit 2 – CURBKꢀCurrent Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.CURBK bit.
Bit 0 – DTGLꢀData Toggle Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.DTGL bit.
DS40001882G-page 763
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USB – Universal Serial Bus
32.19.4 Pipe Status Set Register n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PSTATUSSET
0x105
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
CURBK
W
1
0
DTGL
W
BK1RDY
BK0RDY
PFREEZE
Access
Reset
W
0
W
0
W
0
0
0
Bit 7 – BK1RDYꢀBank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK1RDY.
Bit 6 – BK0RDYꢀBank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK0RDY.
Bit 4 – PFREEZEꢀPipe Freeze Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.PFREEZE bit.
Bit 2 – CURBKꢀCurrent Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.CURBK bit.
Bit 0 – DTGLꢀData Toggle Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.DTGL bit.
DS40001882G-page 764
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.5 Pipe Status Register n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PSTATUS
0x106
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DTGL
R
BK1RDY
BK0RDY
PFREEZE
CURBK
Access
Reset
R
0
R
0
R
0
R
0
0
Bit 7 – BK1RDYꢀBank 1 is ready
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
Value
Description
0
1
The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 6 – BK0RDYꢀBank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
Value
Description
0
The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill
in.
1
The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 4 – PFREEZEꢀPipe Freeze
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
This bit is also set by the hardware:
•
•
•
•
When a STALL handshake has been received.
After a PIPE has been enabled (rising of bit PEN.N).
When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
When a pipe transfer was completed with a pipe error. See the PINTFLAG register.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly
completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
Value
Description
0
The Pipe operates in normal operation.
1
The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Bit 2 – CURBKꢀCurrent Bank
Value
Description
0
1
The bank0 is the bank that will be used in the next single/multi USB packet.
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 0 – DTGLꢀData Toggle Sequence
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
Value
Description
0
The PID of the next expected transaction will be zero: data 0.
DS40001882G-page 765
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USB – Universal Serial Bus
Value
Description
1
The PID of the next expected transaction will be one: data 1.
DS40001882G-page 766
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USB – Universal Serial Bus
32.19.6 Host Pipe Interrupt Flag Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PINTFLAG
0x107
0x00
Property:ꢀ
-
Bit
7
6
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
Bit 5 – STALLꢀSTALL Received Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – TXSTPꢀTransmitted Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TXSTP Interrupt Flag.
Bit 3 – PERRꢀPipe Error Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the PERR Interrupt Flag.
Bit 2 – TRFAILꢀTransfer Fail Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPTꢀTransfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT is one.
PINTFLAG.TRCPT is set for a single bank IN/OUT pipe or a double bank IN/OUT pipe when current bank is 0.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT Interrupt Flag.
DS40001882G-page 767
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.7 Host Pipe Interrupt Clear Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PINTENCLR
0x108
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
Bit 5 – STALLꢀReceived Stall Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The received Stall interrupt is disabled.
1
The received Stall interrupt is enabled and an interrupt request will be generated when the received
Stall interrupt Flag is set.
Bit 4 – TXSTPꢀTransmitted Setup Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
1
The Transmitted Setup interrupt is disabled.
The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the
Transmitted Setup interrupt Flag is set.
Bit 3 – PERRꢀPipe Error Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error
interrupt Flag is set.
Bit 2 – TRFAILꢀTransfer Fail Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail
interrupt Flag is set.
Bits 0, 1 – TRCPTꢀTransfer Complete Bank x interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Complete Bank x interrupt is disabled.
DS40001882G-page 768
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SAM D21/DA1 Family
USB – Universal Serial Bus
Value
Description
1
The Transfer Complete Bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete interrupt x Flag is set.
DS40001882G-page 769
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.8 Host Interrupt Pipe Set Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PINTENSET
0x109
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
TRCPT0
R/W
Access
Reset
0
2
Bit 5 – STALLꢀStall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value
Description
0
1
The Stall interrupt is disabled.
The Stall interrupt is enabled.
Bit 4 – TXSTPꢀTransmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value
Description
0
1
The Transmitted Setup interrupt is disabled.
The Transmitted Setup interrupt is enabled.
Bit 3 – PERRꢀPipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value
Description
0
1
The Pipe Error interrupt is disabled.
The Pipe Error interrupt is enabled.
Bit 2 – TRFAILꢀTransfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
1
The Transfer Fail interrupt is disabled.
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPTꢀTransfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x.
0.2.7 Host Registers - Pipe RAM
Value
Description
0
1
The Transfer Complete x interrupt is disabled.
The Transfer Complete x interrupt is enabled.
DS40001882G-page 770
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.20 Pipe Descriptor Structure
Data Buffers
Pn BK1
Pn BK0
Pipe descriptors
Reserved
STATUS_PIPE
CTRL_BK
Bank1
Reserved
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS_PIPE
CTRL_PIPE
STATUS_BK
EXTREG
Bank0
PCKSIZE
ADDR
2 x 0xn0
Reserved
STATUS_PIPE
CTRL_BK
Reserved
+0x01F
+0x01E
+0x01C
+0x01A
+0x018
+0x014
+0x010
+0x00F
+0x00E
+0x00C
+0x00A
+0x008
+0x004
+0x000
Bank1
Reserved
PCKSIZE
ADDR
Reserved
STATUS_PIPE
CTRL_PIPE
STATUS_BK
EXTREG
Bank0
PCKSIZE
ADDR
DESCADD
DS40001882G-page 771
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.21 Host Registers - Pipe RAM - Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
23:16
31:24
7:0
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
0x00
ADDR
15:8
23:16
31:24
7:0
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
BYTE_COUNT[5:0]
0x04
0x08
PCKSIZE
EXTREG
MULTI_PACKET_SIZE[9:2]
SIZE[2:0]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[3:0]
15:8
7:0
VARIABLE[10:4]
0x0A
0x0B
STATUS_BK
Reserved
ERRORFLOW CRCERR
7:0
15:8
7:0
PDADDR[6:0]
0x0C
0x0E
CTRL_PIPE
PERMAX[3:0]
ERCNT[2:0]
PEPNUM[3:0]
PIDER DAPIDER
CRC16ER
TOUTER
DTGLER
STATUS_PIPE
15:8
32.22 Host Registers - Pipe RAM - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-
Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 772
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.1 Address of the Data Buffer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
ADDR
0x00
0xxxxxxxx
Property:ꢀ NA
Original offset 0x00 & 0x10
Bit
31
30
29
28
27
26
25
24
ADDR[31:24]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
ADDR[23:16]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
ADDR[15:8]
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
Bits 31:0 – ADDR[31:0]ꢀData Pointer Address Value
These bits define the data pointer address as an absolute double word address in RAM. The two least significant bits
must be zero to ensure the descriptor is 32-bit aligned.
DS40001882G-page 773
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.2 Packet Size
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
PCKSIZE
0x04
0xXXXXXXX
Property:ꢀ NA
Original offset 0x04 & 0x14
Bit
31
AUTO_ZLP
R/W
30
29
SIZE[2:0]
R/W
28
27
26
25
24
MULTI_PACKET_SIZE[13:10]
Access
Reset
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
x
0
Bit
23
22
21
20
19
18
17
16
MULTI_PACKET_SIZE[9:2]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
15
14
13
12
11
10
9
8
MULTI_PACKET_SIZE[1:0]
BYTE_COUNT[5:0]
Access
Reset
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bit 31 – AUTO_ZLPꢀAutomatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the pipe.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes only. When
disabled the handshake should be managed by firmware.
Value
Description
0
1
Automatic Zero Length Packet is disabled.
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0]ꢀPipe size
These bits contains the size of the pipe.
Theses bits are cleared upon sending a USB reset.
SIZE[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
8 Byte
16 Byte
32 Byte
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1024 Byte in HS mode(1)
1023 Byte in FS mode(1)
Note:ꢀ
1. For Isochronous pipe only.
Bits 27:14 – MULTI_PACKET_SIZE[13:0]ꢀMulti Packet IN or OUT size
These bits define the 14-bit value that is used for multi-packet transfers.
DS40001882G-page 774
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SAM D21/DA1 Family
USB – Universal Serial Bus
For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written
to zero when setting up a new transfer.
For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
Bits 13:8 – BYTE_COUNT[5:0]ꢀByte Count
These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP transaction for an
OUT pipe, or of the number of bytes to be received in the next IN transaction for an input pipe.
DS40001882G-page 775
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.3 Extended Register
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EXTREG
0x08
0xXXXXXXX
Property:ꢀ NA
Bit
15
14
13
12
11
10
9
8
VARIABLE[10:4]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
VARIABLE[3:0]
SUBPID[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
x
Bits 14:4 – VARIABLE[10:0]ꢀVariable field send with extended token
These bits define the VARIABLE field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum.”
To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described below.
VARIABLE
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
bLinkState(1)
BESL (See LPM ECN)(2)
bRemoteWake(1)
Reserved
VARIABLE[10:9]
Notes:ꢀ
1. For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
2. For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0]ꢀSUBPID field send with extended token
These bits define the SUBPID field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in “Table
2.2 SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum”.
DS40001882G-page 776
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.4 Host Status Bank
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS_BK
0x0A
0xXXXXXXX
Property:ꢀ NA
Original offset 0x0A & 0x1A
Bit
7
6
5
4
3
2
1
0
CRCERR
R/W
ERRORFLOW
Access
Reset
R/W
x
x
Bit 1 – ERRORFLOWꢀError Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
Value
Description
0
1
No Error Flow detected.
A Error Flow has been detected.
Bit 0 – CRCERRꢀCRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Value
Description
0
1
No CRC Error.
CRC Error detected.
DS40001882G-page 777
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.5 Host Control Pipe
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRL_PIPE
0x0C
0xXXXX
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
11
10
PEPNUM[3:0]
9
8
PERMAX[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
x
R/W
0
R/W
0
R/W
0
R/W
x
Bit
7
6
5
4
3
2
1
0
PDADDR[6:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
Bits 15:12 – PERMAX[3:0]ꢀPipe Error Max Number
These bits define the maximum number of error for this Pipe before freezing the pipe automatically.
Bits 11:8 – PEPNUM[3:0]ꢀPipe EndPoint Number
These bits define the number of endpoint for this Pipe.
Bits 6:0 – PDADDR[6:0]ꢀPipe Device Address
These bits define the Device Address for this pipe.
DS40001882G-page 778
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.6 Host Status Pipe
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS_PIPE
0x0E
0xXXXXXXX
Property:ꢀ PAC Write-Protection, Write-Synchronized, Read-Synchronized
Original offset 0x0E & 0x1E
Bit
15
7
14
13
5
12
11
10
9
8
Access
Reset
Bit
6
4
CRC16ER
R/W
3
TOUTER
R/W
2
PIDER
R/W
x
1
DAPIDER
R/W
0
DTGLER
R/W
ERCNT[2:0]
Access
Reset
R/W
0
R/W
0
R/W
x
x
x
x
x
Bits 7:5 – ERCNT[2:0]ꢀPipe Error Counter
These bits define the number of errors detected on the pipe.
Bit 4 – CRC16ERꢀCRC16 ERROR
This bit defines the CRC16 Error Status.
This bit is set when a CRC 16 error has been detected during a IN transactions.
Value
Description
0
1
No CRC 16 Error detected.
A CRC 16 error has been detected.
Bit 3 – TOUTERꢀTIME OUT ERROR
This bit defines the Time Out Error Status.
This bit is set when a Time Out error has been detected during a USB transaction.
Value
Description
0
1
No Time Out Error detected.
A Time Out error has been detected.
Bit 2 – PIDERꢀPID ERROR
This bit defines the PID Error Status.
This bit is set when a PID error has been detected during a USB transaction.
Value
Description
0
1
No PID Error detected.
A PID error has been detected.
Bit 1 – DAPIDERꢀData PID ERROR
This bit defines the PID Error Status.
This bit is set when a Data PID error has been detected during a USB transaction.
Value
Description
0
1
No Data PID Error detected.
A Data PID error has been detected.
Bit 0 – DTGLERꢀData Toggle Error
This bit defines the Data Toggle Error Status.
This bit is set when a Data Toggle Error has been detected.
Value
Description
0
1
No Data Toggle Error.
Data Toggle Error detected.
DS40001882G-page 779
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.
ADC – Analog-to-Digital Converter
33.1
Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution,
and is capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended
measurements can be performed. An optional gain stage is available to increase the dynamic range. In addition,
several internal signal inputs are available. The ADC can provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used.
An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the scaled I/O
and core voltages can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software
intervention required.
The ADC may be configured for 8-, 10- or 12-bit results, reducing the conversion time. ADC conversion results
are provided left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
33.2
Features
•
•
•
8-, 10- or 12-bit resolution
Up to 350,000 samples per second (350ksps)
Differential and single-ended inputs
– Up to 32 analog input
– 25 positive and 10 negative, including internal and external
Five internal inputs
•
– Bandgap
– Temperature sensor
– DAC
– Scaled core supply
– Scaled I/O supply
•
•
•
•
1/2x to 16x gain
Single, continuous and pin-scan conversion options
Windowing monitor with selectable channel
Conversion range:
– Vref [1v to VDDANA - 0.6V]
– ADCx * GAIN [0V to -Vref
]
•
Built-in internal reference and external reference options
– Four bits for reference selection
•
•
•
•
•
Event-triggered conversion for accurate timing (one event input)
Optional DMA transfer of conversion result
Hardware gain and offset compensation
Averaging and oversampling with decimation to support, up to 16-bit result
Selectable sampling time
DS40001882G-page 780
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.3
Block Diagram
Figure 33-1.ꢀADC Block Diagram
WINCTRL
WINLT
CTRLA
AVGCTRL
SAMPCTRL
EVCTRL
WINUT
INPUTCTRL
OFFSETCORR
GAINCORR
SWTRIG
ADC0
...
ADCn
INT.SIG
POST
PROCESSING
RESULT
ADC
ADC0
...
ADCn
INT.SIG
INT1V
INTVCC0/1
VREFA
CTRLB
VREFB
PRESCALER
REFCTRL
Note:ꢀ INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.
33.4
Signal Description
Signal Name
VREFA
Type
Description
Analog input
Analog input
Analog input
External reference voltage A
External reference voltage B
Analog input channels
VREFB
ADC[19..0](1)
Note:ꢀ Refer to Configuration Summary for details on exact number of analog input channels.
Note:ꢀ Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can
be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
2. Configuration Summary
33.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
DS40001882G-page 781
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.5.1 I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Related Links
23. PORT - I/O Pin Controller
33.5.2 Power Management
The ADC will continue to operate in any Sleep mode where the selected source clock is running. The ADC’s
interrupts, except the OVERRUN interrupt, can be used to wake up the device from sleep modes. Events connected
to the event system can trigger other operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
33.5.3 Clocks
The ADC bus clock (CLK_APB_ADCx) can be enabled in the Main Clock, which also defines the default state.
The ADC requires a generic clock (GCLK_ADC). This clock must be configured and enabled in the Generic Clock
Controller (GCLK) before using the ADC.
A generic clock is asynchronous to the bus clock. Due to this asynchronicity, writes to certain registers will require
synchronization between the clock domains. Refer to Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
33.5.4 DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the ADC DMA requests requires the DMA
Controller to be configured first.
Related Links
20. DMAC – Direct Memory Access Controller
33.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt
controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
33.5.6 Events
The events are connected to the Event System.
Related Links
24. EVSYS – Event System
33.5.7 Debug Operation
When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue
operation during debugging.
33.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following register:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
DS40001882G-page 782
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
33.5.9 Analog Connections
I/O-pins AIN0 to AIN19 as well as the VREFA/VREFB reference voltage pin are analog inputs to the ADC.
33.5.10 Calibration
The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM Software
Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
Related Links
10.3.2 NVM Software Calibration Area Mapping
33.6
Functional Description
33.6.1 Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce
the conversion time.
The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input values can
be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also configure
whether the conversion should be single-ended or differential.
33.6.2 Basic Operation
33.6.2.1 Initialization
Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference
must be configured. The first conversion after the reference is changed must not be used. All other configuration
registers must be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System
Controller (SYSCTRL). Refer to SYSCTRL – System Controller for more details.
When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A
(CTRLA.ENABLE).
Related Links
17. SYSCTRL – System Controller
33.6.2.2 Enabling, Disabling and Reset
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing CTRLA.ENABLE=0. The ADC is reset by writing a '1' to the Software Reset bit in the Control A register
(CTRLA.SWRST). All registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be
disabled.
The ADC must be disabled before it is reset.
33.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx frequency and
the clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in 33.6.2.1 Initialization.
Data conversion can be started either manually by setting the Start bit in the Software Trigger register
(SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the conversions. A free-running
mode can be used to continuously convert an input channel. When using free-running mode the first conversion must
be started, while subsequent conversions will start automatically at the end of previous conversions.
The automatic trigger can be configured to trigger on many different conditions.
DS40001882G-page 783
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ADC – Analog-to-Digital Converter
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the previous
conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as soon as it is available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN). When the RESRDY interrupt flag is set, the new
result has been synchronized to the RESULT register.
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set register
(INTENSET) must be written to '1'.
33.6.3 Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings.
Figure 33-2.ꢀADC Prescaler
GCLK_ADC
9-BIT PRESCALER
CTRLB.PRESCALER[2:0]
CLK_ADC
The propagation delay of an ADC measurement depends on the selected mode and is given by:
•
Single-shot mode:
Resolution
2
1 +
+ DelayGain
PropagationDelay =
f
CLK+ − ADC
•
Free-running mode:
Resolution
2
+ DelayGain
PropagationDelay =
f
CLK+ − ADC
Table 33-1.ꢀDelay Gain
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0] Free-running mode
Differential Mode Single-Ended
Single shot mode
Name
Differential mode Single-Ended
mode
Mode
1X
2X
4X
8X
16X
0x0
0x1
0x2
0x3
0x4
0
0
1
1
2
0
1
1
2
2
0
1
0.5
1
1.5
2
1.5
2
2.5
3
DS40001882G-page 784
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© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
...........continued
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0] Free-running mode
Single shot mode
Name
Differential Mode Single-Ended
Mode
Differential mode Single-Ended
mode
Reserved 0x5 ... 0xE
Reserved
0
Reserved
1
Reserved
0.5
Reserved
1.5
DIV2
0xF
33.6.4 ADC Resolution
The ADC supports 8-bit, 10-bit or 12-bit resolution. Resolution can be changed by writing the Resolution bit group in
the Control B register (CTRLB.RESSEL). By default, the ADC resolution is set to 12 bits.
33.6.5 Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended:
•
If the positive input may go below the negative input, the differential mode should be used in order to get
correct results.
•
If the positive input is always positive, the single-ended conversion should be used in order to have full 12-bit
resolution in the conversion.
The negative input must be connected to ground. This ground could be the internal GND, IOGND or an external
ground connected to a pin. Refer to the Control B (CTRLB) register for selection details.
If the positive input may go below the negative input, creating some negative results, the differential mode should
be used in order to get correct results. The differential mode is enabled by setting DIFFMODE bit in the Control B
register (CTRLB.DIFFMODE). Both conversion types could be run in single mode or in free-running mode. When the
free-running mode is selected, an ADC input will continuously sample the input and performs a new conversion. The
INTFLAG.RESRDY bit will be set at the end of each conversion.
Related Links
33.8.5 CTRLB
33.6.5.1 Conversion Timing
The following figure shows the ADC timing for one single conversion. A conversion starts after the software or event
start are synchronized with the GCLK_ADC clock. The input channel is sampled in the first half CLK_ADC period.
Figure 33-3.ꢀADC Timing for One Conversion in Differential Mode without Gain
1
2
3
4
5
6
7
8
CLK_ADC
START
SAMPLE
INT
MSB
10
9
8
7
6
5
4
3
2
1
LSB
Converting Bit
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion.
DS40001882G-page 785
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Figure 33-4.ꢀADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling
Time
1
2
3
4
5
6
7
8
9
10
11
CLK_ADC
START
SAMPLE
INT
MSB
10
9
8
7
6
5
4
3
2
1
LSB
Converting Bit
Figure 33-5.ꢀADC Timing for Free Running in Differential Mode without Gain
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
CLK_ADC
START
SAMPLE
INT
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
Converting Bit
Figure 33-6.ꢀADC Timing for One Conversion in Single-Ended Mode without Gain
1
2
3
4
5
6
7
8
9
10
11
CLK_ADC
START
SAMPLE
AMPLIFY
INT
MSB
10
9
8
7
6
5
4
3
2
1
LSB
Converting Bit
Figure 33-7.ꢀADC Timing for Free Running in Single-Ended Mode without Gain
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
CLK_ADC
START
SAMPLE
AMPLIFY
INT
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
1
0
11 10
Converting Bit
DS40001882G-page 786
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ADC – Analog-to-Digital Converter
33.6.6 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by the Number of Samples to be Collected field in the Average Control register (AVGCTRL.SAMPLENUM).
When accumulating more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To
avoid overflow, the result is right shifted automatically to fit within the available register size. The number of automatic
right shifts is specified in the table below.
Note:ꢀ To perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control B
register (CTRLB.RESSEL) must be set.
Table 33-2.ꢀAccumulation
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result Precision
Number of
Automatic
Right Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
13 bits
14 bits
15 bits
16 bits
17 bits
18 bits
19 bits
20 bits
21 bits
22 bits
12 bits
0
0
0
0
0
1
2
3
4
5
6
12 bits
13 bits
14 bits
15 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
12 bits
0
2
0x1
0
4
0x2
0
8
0x3
0
16
0x4
0
32
0x5
2
64
0x6
4
128
256
512
1024
Reserved
0x7
8
0x8
16
32
64
0
0x9
0xA
0xB - 0xF
33.6.7 Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This feature is
suitable when operating in noisy conditions.
Averaging is done by accumulating m samples, as described in 33.6.6 Accumulation, and dividing the result by m.
The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by
writing to AVGCTRL.SAMPLENUM.
The division is obtained by a combination of the automatic right shift described above, and an additional right shift
that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES).
Note:ꢀ To perform the averaging of two or more samples, the Conversion Result Resolution field in the Control B
register (CTRLB.RESSEL) must be set to '1'.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1
.
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 33-3.ꢀAveraging
Number of
Accumulated
Samples
AVGCTRL.
Intermediate
Result
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number of
Final Result
Precision
Automatic
Division
Factor
SAMPLENUM
Precision
Right
Shifts
1
0x0
12 bits
0
1
0x0
12 bits
0
DS40001882G-page 787
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
...........continued
Number of
Accumulated
Samples
AVGCTRL.
Intermediate
Result
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number of
Final Result
Precision
Automatic
Division
Factor
SAMPLENUM
Precision
Right
Shifts
2
0x1
13
14
15
16
17
18
19
20
21
22
0
0
0
0
1
2
3
4
5
6
2
0x1
0x2
0x3
0x4
0x4
0x4
0x4
0x4
0x4
0x4
0x0
1
2
3
4
5
6
7
8
9
10
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
12 bits
0
4
0x2
4
0
8
0x3
8
0
16
0x4
16
16
16
16
16
16
16
0
32
0x5
2
64
0x6
4
128
256
512
1024
Reserved
0x7
8
0x8
16
32
64
0
0x9
0xA
0xB-0xF
33.6.8 Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits, for the cost of
reduced effective sampling rate.
To increase the resolution by n bits, 4n samples must be accumulated. The result must then be right-shifted by n bits.
This right-shift is a combination of the automatic right-shift and the value written to AVGCTRL.ADJRES. To obtain the
correct resolution, the ADJRES must be configured as described in the table below. This method will result in n bit
extra LSB resolution.
Table 33-4.ꢀConfiguration Required for Oversampling and Decimation
Result
Resolution
Number of
Samples to
Average
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits
14 bits
15 bits
16 bits
41 = 4
0x2
0x4
0x6
0x8
0
0
2
4
0x1
0x2
0x1
0x0
42 = 16
43 = 64
44 = 256
33.6.9 Window Monitor
The window monitor feature allows the conversion result in the RESULT register to be compared to predefined
threshold values. The window mode is selected by setting the Window Monitor Mode bits in the Window Monitor
Control register (WINCTRL.WINMODE[2:0]). Threshold values must be written in the Window Monitor Lower
Threshold register (WINLT) and Window Monitor Upper Threshold register (WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated
as unsigned values. The significant WINLT and WINUT bits are given by the precision selected in the Conversion
Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means that e.g. in 8-bit mode, only the
eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit,
even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
33.6.10 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC.
DS40001882G-page 788
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ADC – Analog-to-Digital Converter
The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero
input voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset
correction value is subtracted from the converted data before writing to the Result register (RESULT).
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after
compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR).
To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register (CTRLB.CORREN) must
be set.
Offset and gain error compensation results are both calculated according to:
Result = Conversion value+ − OFFSETCORR ⋅ GAINCORR
The correction will introduce a latency of 13 CLK_ADC clock cycles. In Free-running mode this latency is introduced
on the first conversion only because the duration is always less than the propagation delay. In Single Conversion
mode this latency is introduced for each conversion.
Figure 33-8.ꢀ ADC Timing Correction Enabled
START
CONV0
CONV1
CONV2
CONV3
CORR0
CORR1
CORR2
CORR3
33.6.11 DMA Operation
The ADC generates the following DMA request:
•
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared
when the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
33.6.12 Interrupts
The ADC has the following interrupt sources:
•
•
•
Result Conversion Ready: RESRDY
Window Monitor: WINMON
Overrun: OVERRUN
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the ADC is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which
interrupt condition is present.
Related Links
11.2 Nested Vector Interrupt Controller
DS40001882G-page 789
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ADC – Analog-to-Digital Converter
33.6.13 Events
The ADC can generate the following output events:
•
•
Result Ready (RESRDY): Generated when the conversion is complete and the result is available.
Window Monitor (WINMON): Generated when the window monitor condition match.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring
the event system.
The peripheral can take the following actions on an input event:
•
•
Start conversion (START): Start a conversion.
Conversion flush (FLUSH): Flush the conversion.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input
event. Clearing this bit disables the corresponding action on input event.
Note:ꢀ If several events are connected to the ADC, the enabled action will be taken on any of the incoming events.
The events must be correctly routed in the Event System.
Related Links
24. EVSYS – Event System
33.6.14 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC
during standby sleep mode. When CTRLA.RUNSTDBY=0, the ADC is disabled during sleep, but maintains its
current configuration. When CTRLA.RUNSTDBY=1, the ADC continues to operate during sleep. Note that when
CTRLA.RUNSTDBY=0, the analog blocks are powered off for the lowest power consumption. This necessitates a
start-up time delay when the system returns from sleep.
When CTRLA.RUNSTDBY=1, any enabled ADC interrupt source can wake up the CPU, except the OVERRUN
interrupt.. While the CPU is sleeping, ADC conversion can only be triggered by events.
33.6.15 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
Control B (CTRLB)
Software Trigger (SWTRIG)
Window Monitor Control (WINCTRL)
Input Control (INPUTCTRL)
Window Upper/Lower Threshold (WINUT/WINLT)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
•
•
Software Trigger (SWTRIG)
Input Control (INPUTCTRL)
DS40001882G-page 790
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ADC – Analog-to-Digital Converter
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
DS40001882G-page 791
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ADC – Analog-to-Digital Converter
33.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
CTRLA
REFCTRL
AVGCTRL
SAMPCTRL
7:0
7:0
7:0
7:0
7:0
15:8
RUNSTDBY
ENABLE
SWRST
REFCOMP
REFSEL[3:0]
SAMPLENUM[3:0]
SAMPLEN[5:0]
ADJRES[2:0]
RESSEL[1:0]
CORREN
FREERUN
LEFTADJ
DIFFMODE
0x04
CTRLB
PRESCALER[2:0]
WINMODE[2:0]
START
0x06
...
Reserved
WINCTRL
Reserved
SWTRIG
Reserved
0x07
0x08
0x09
...
7:0
7:0
0x0B
0x0C
0x0D
...
FLUSH
0x0F
7:0
15:8
23:16
31:24
7:0
MUXPOS[4:0]
MUXNEG[4:0]
0x10
INPUTCTRL
INPUTOFFSET[3:0]
WINMONEO RESRDYEO
INPUTSCAN[3:0]
GAIN[3:0]
SYNCEI
0x14
0x15
0x16
0x17
0x18
0x19
EVCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
STATUS
STARTEI
7:0
7:0
SYNCRDY
SYNCRDY
SYNCRDY
WINMON
WINMON
WINMON
OVERRUN
OVERRUN
OVERRUN
RESRDY
RESRDY
RESRDY
7:0
7:0
SYNCBUSY
7:0
RESULT[7:0]
0x1A
0x1C
RESULT
WINLT
15:8
7:0
RESULT[15:8]
WINLT[7:0]
15:8
WINLT[15:8]
0x1E
...
Reserved
WINUT
0x1F
7:0
WINUT[7:0]
0x20
15:8
WINUT[15:8]
0x22
...
Reserved
0x23
7:0
15:8
7:0
GAINCORR[7:0]
OFFSETCORR[7:0]
LINEARITY_CAL[7:0]
0x24
0x26
GAINCORR
GAINCORR[11:8]
OFFSETCORR[11:8]
BIAS_CAL[2:0]
OFFSETCORR
15:8
7:0
0x28
0x2A
CALIB
15:8
7:0
DBGCTRL
DBGRUN
33.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted
by the Write-Protected property in each individual register description.
DS40001882G-page 792
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ADC – Analog-to-Digital Converter
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-
Synchronized or the Read-Synchronized property in each individual register description.
Some registers are enable-protected, meaning they can be written only when the ADC is disabled. Enable-protection
is denoted by the Enable-Protected property in each individual register description.
DS40001882G-page 793
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ADC – Analog-to-Digital Converter
33.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
0
Bit 2 – RUNSTDBYꢀRun in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
Value
Description
0
1
The ADC is halted during standby sleep mode.
The ADC continues normal operation during standby sleep mode.
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
Value
Description
0
1
The ADC is disabled.
The ADC is enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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ADC – Analog-to-Digital Converter
33.8.2 Reference Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
REFCTRL
0x01
0x00
Property:ꢀ Write-Protected
Bit
7
REFCOMP
R/W
6
5
4
3
2
1
0
REFSEL[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – REFCOMPꢀReference Buffer Offset Compensation Enable
The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will
decrease the input impedance and thus increase the start-up time of the reference.
Value
Description
0
1
Reference buffer offset compensation is disabled.
Reference buffer offset compensation is enabled.
Bits 3:0 – REFSEL[3:0]ꢀReference Selection
These bits select the reference for the ADC.
Table 33-5.ꢀReference Selection
REFSEL[3:0]
Name
Description
0x0
0x1
0x2
0x3
INT1V
1.0V voltage reference
1/1.48 VDDANA
1/2 VDDANA (only for VDDANA > 2.0V)
External reference
INTVCC0
INTVCC1
VREFA
VREFB
0x4
External reference
0x5-0xF
Reserved
Note:ꢀ INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.
DS40001882G-page 795
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.3 Average Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
AVGCTRL
0x02
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
ADJRES[2:0]
SAMPLENUM[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 6:4 – ADJRES[2:0]ꢀAdjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0]ꢀNumber of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result register
(RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
SAMPLENUM[3:0]
Name
Description
0x0
1
1 sample
0x1
2
2 samples
0x2
4
4 samples
0x3
8
8 samples
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB-0xF
16
32
64
128
256
512
1024
16 samples
32 samples
64 samples
128 samples
256 samples
512 samples
1024 samples
Reserved
DS40001882G-page 796
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.4 Sampling Time Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SAMPCTRL
0x03
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
SAMPLEN[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 5:0 – SAMPLEN[5:0]ꢀSampling Time Length
These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus
controlling the ADC input impedance. Sampling time is set according to the equation:
CLK
ADC
Sampling time = SAMPLEN+1 ⋅
2
DS40001882G-page 797
Complete Datasheet
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.5 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x04
0x0000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
7
14
6
13
12
11
10
9
8
PRESCALER[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit
5
4
3
CORREN
R/W
2
FREERUN
R/W
1
LEFTADJ
R/W
0
DIFFMODE
R/W
RESSEL[1:0]
Access
Reset
R/W
0
R/W
0
0
0
0
0
Bits 10:8 – PRESCALER[2:0]ꢀPrescaler Configuration
These bits define the ADC clock relative to the peripheral clock.
PRESCALER[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV4
DIV8
Peripheral clock divided by 4
Peripheral clock divided by 8
Peripheral clock divided by 16
Peripheral clock divided by 32
Peripheral clock divided by 64
Peripheral clock divided by 128
Peripheral clock divided by 256
Peripheral clock divided by 512
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
Bits 5:4 – RESSEL[1:0]ꢀConversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
RESSEL[1:0]
Name
Description
0x0
0x1
0x2
0x3
12BIT
16BIT
10BIT
8BIT
12-bit result
For averaging mode output
10-bit result
8-bit result
Bit 3 – CORRENꢀDigital Correction Logic Enabled
Value
Description
0
Disable the digital result correction.
1
Enable the digital result correction. The ADC conversion result in the RESULT register is then
corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers.
Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit
group in the Offset Correction register.
Bit 2 – FREERUNꢀFree Running Mode
Value
Description
0
The ADC run is single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous conversion
completes.
Bit 1 – LEFTADJꢀLeft-Adjusted Result
Value
Description
0
The ADC conversion result is right-adjusted in the RESULT register.
DS40001882G-page 798
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Value
Description
1
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result
will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust
the value in the RESULT register.
Bit 0 – DIFFMODEꢀDifferential Mode
Value
Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS
and MUXNEG inputs will be converted by the ADC.
DS40001882G-page 799
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.6 Window Monitor Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WINCTRL
0x08
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
WINMODE[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 2:0 – WINMODE[2:0]ꢀWindow Monitor Mode
These bits enable and define the window monitor mode.
WINMODE[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5-0x7
DISABLE
MODE1
MODE2
MODE3
MODE4
No window mode (default)
Mode 1: RESULT > WINLT
Mode 2: RESULT < WINUT
Mode 3: WINLT < RESULT < WINUT
Mode 4: !(WINLT < RESULT < WINUT)
Reserved
DS40001882G-page 800
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.7 Software Trigger
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SWTRIG
0x0C
0x00
Property:ꢀ Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
START
R/W
0
0
FLUSH
R/W
0
Access
Reset
Bit 1 – STARTꢀADC Start Conversion
Writing this bit to zero will have no effect.
Value
Description
0
The ADC will not start a conversion.
1
The ADC will start a conversion. The bit is cleared by hardware when the conversion has started.
Setting this bit when it is already set has no effect.
Bit 0 – FLUSHꢀADC Conversion Flush
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new
conversion.
Writing this bit to zero will have no effect.
Value
Description
0
No flush action.
1
"Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the next
peripheral clock edge, and all conversions in progress will be aborted and lost. This bit will be cleared
after the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start
a new conversion.
DS40001882G-page 801
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.8 Input Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INPUTCTRL
0x10
0x00000000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
GAIN[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
23
22
21
20
19
18
17
16
INPUTOFFSET[3:0]
INPUTSCAN[3:0]
R/W R/W
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
15
14
6
13
5
12
11
10
9
8
MUXNEG[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
4
3
2
1
0
MUXPOS[4:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 27:24 – GAIN[3:0]ꢀGain Factor Selection
These bits set the gain factor of the ADC gain stage.
GAIN[3:0]
Name
Description
0x0
0x1
1X
2X
1x
2x
0x2
4X
4x
0x3
8X
8x
0x4
0x5-0xE
0xF
16X
-
DIV2
16x
Reserved
1/2x
Bits 23:20 – INPUTOFFSET[3:0]ꢀPositive Mux Setting Offset
The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first
conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET. Setting this register
to zero causes the first conversion to use a positive input equal to MUXPOS.
After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be done
with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives the
input that is actually converted.
Bits 19:16 – INPUTSCAN[3:0]ꢀNumber of Input Channels Included in Scan
This register gives the number of input sources included in the pin scan. The number of input sources included is
INPUTSCAN + 1. The input channels included are in the range from MUXPOS + INPUTOFFSET to MUXPOS +
INPUTOFFSET + INPUTSCAN.
The range of the scan mode must not exceed the number of input channels available on the device.
Bits 12:8 – MUXNEG[4:0]ꢀNegative Mux Input Selection
These bits define the Mux selection for the negative ADC input. selections.
DS40001882G-page 802
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08-0x1
7
Name
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
Description
ADC AIN0 pin
ADC AIN1 pin
ADC AIN2 pin
ADC AIN3 pin
ADC AIN4 pin
ADC AIN5 pin
ADC AIN6 pin
ADC AIN7 pin
Reserved
0x18
0x19
0x1A-0x1
F
GND
IOGND
Internal ground
I/O ground
Reserved
Note: 1. Only available in SAM R21G.
Bits 4:0 – MUXPOS[4:0]ꢀPositive Mux Input Selection
These bits define the Mux selection for the positive ADC input. The following table shows the possible input
selections. If the internal bandgap voltage channel is selected, then the Sampling Time Length bit group in the
Sampling Control register must be written.
MUXPOS[4:0]
Group configuration
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
ADC AIN0 pin
ADC AIN1 pin
ADC AIN2 pin
ADC AIN3 pin
ADC AIN4 pin
ADC AIN5 pin
ADC AIN6 pin
ADC AIN7 pin
ADC AIN8 pin
ADC AIN9 pin
ADC AIN10 pin
ADC AIN11 pin
ADC AIN12 pin
ADC AIN13 pin
ADC AIN14 pin
ADC AIN15 pin
ADC AIN16 pin
ADC AIN17 pin
ADC AIN18 pin
ADC AIN19 pin
Reserved
0x08
0x09
PIN8
PIN9
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14-0x17
0x18
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
TEMP
Temperature reference
Bandgap voltage
1/4 scaled core supply
1/4 scaled I/O supply
DAC output (1)
Reserved
0x19
BANDGAP
SCALEDCOREVCC
SCALEDIOVCC
DAC
0x1A
0x1B
0x1C
0x1D-0x1F
Note:ꢀ
1. When using the internal DAC connection to the positive input of the ADC, the DAC CTRLB.EOEN must be
set.
DS40001882G-page 803
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.9 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x14
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
SYNCEI
R/W
0
0
STARTEI
R/W
WINMONEO
RESRDYEO
Access
Reset
R/W
0
R/W
0
0
Bit 5 – WINMONEOꢀWindow Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated
when the window monitor detects something.
Value
Description
0
1
Window Monitor event output is disabled and an event will not be generated.
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEOꢀResult Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated
when the conversion result is available.
Value
Description
0
1
Result Ready event output is disabled and an event will not be generated.
Result Ready event output is enabled and an event will be generated.
Bit 1 – SYNCEIꢀSynchronization Event In
Value
Description
0
1
A flush and new conversion will not be triggered on any incoming event.
A flush and new conversion will be triggered on any incoming event.
Bit 0 – STARTEIꢀStart Conversion Event In
Value
Description
0
1
A new conversion will not be triggered on any incoming event.
A new conversion will be triggered on any incoming event.
DS40001882G-page 804
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.10 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x16
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
SYNCRDY
R/W
2
WINMON
R/W
1
OVERRUN
R/W
0
RESRDY
R/W
Access
Reset
0
0
0
0
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt
request.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
Synchronization Ready interrupt flag is set.
Bit 2 – WINMONꢀWindow Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the Window
Monitor interrupt flag is set.
Bit 1 – OVERRUNꢀOverrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt
flag is set.
Bit 0 – RESRDYꢀResult Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result
Ready interrupt flag is set.
DS40001882G-page 805
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.11 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x17
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
SYNCRDY
R/W
2
WINMON
R/W
1
OVERRUN
R/W
0
RESRDY
R/W
Access
Reset
0
0
0
0
Bit 3 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 2 – WINMONꢀWindow Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
Value
Description
0
1
The Window Monitor interrupt is disabled.
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUNꢀOverrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
Value
Description
0
1
The Overrun interrupt is disabled.
The Overrun interrupt is enabled.
Bit 0 – RESRDYꢀResult Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Value
Description
0
1
The Result Ready interrupt is disabled.
The Result Ready interrupt is enabled.
DS40001882G-page 806
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.12 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x18
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
SYNCRDY
R/W
2
WINMON
R/W
1
OVERRUN
R/W
0
RESRDY
R/W
Access
Reset
0
0
0
0
Bit 3 – SYNCRDYꢀSynchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an interrupt request if
INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 2 – WINMONꢀWindow Monitor
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt
request will be generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUNꢀOverrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDYꢀResult Ready
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/SET.RESRDY
is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
DS40001882G-page 807
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.13 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x19
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
DS40001882G-page 808
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.14 Result
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
RESULT
0x1A
0x0000
Property:ꢀ Read-Synchronized
Bit
15
14
13
12
11
10
9
8
RESULT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
RESULT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 15:0 – RESULT[15:0]ꢀResult Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single conversion mode without averaging, the ADC conversion will produce a 12-bit result, which can be left- or
right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the
remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required;
i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit
locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average
Control register (AVGCTRL).
DS40001882G-page 809
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.15 Window Monitor Lower Threshold
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WINLT
0x1C
0x0000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINLT[15:8]
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINLT[15:0]ꢀWindow Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
DS40001882G-page 810
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.16 Window Monitor Upper Threshold
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WINUT
0x20
0x0000
Property:ꢀ Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINUT[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINUT[15:0]ꢀWindow Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
DS40001882G-page 811
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ADC – Analog-to-Digital Converter
33.8.17 Gain Correction
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
GAINCORR
0x24
0x0000
Property:ꢀ Write-Protected
Bit
15
7
14
6
13
5
12
4
11
10
GAINCORR[11:8]
R/W R/W
9
8
Access
Reset
R/W
0
R/W
0
0
0
Bit
3
2
1
0
GAINCORR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – GAINCORR[11:0]ꢀGain Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for gain error
before being written to the result register. The gain-correction is a fractional value, a 1-bit integer plusan 11-bit
fraction, and therefore 1/2 <= GAINCORR < 2. GAINCORR values range from 0.10000000000 to 1.11111111111.
DS40001882G-page 812
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ADC – Analog-to-Digital Converter
33.8.18 Offset Correction
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
OFFSETCORR
0x26
0x0000
Property:ꢀ Write-Protected
Bit
15
7
14
6
13
5
12
4
11
10
9
8
OFFSETCORR[11:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit
3
2
1
0
OFFSETCORR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – OFFSETCORR[11:0]ꢀOffset Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for offset error
before being written to the Result register. This OFFSETCORR value is in two's complement format.
DS40001882G-page 813
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ADC – Analog-to-Digital Converter
33.8.19 Calibration
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CALIB
0x28
0x0000
Property:ꢀ Write-Protected
Bit
15
7
14
6
13
5
12
4
11
3
10
9
8
BIAS_CAL[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit
2
1
0
LINEARITY_CAL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 10:8 – BIAS_CAL[2:0]ꢀBias Calibration Value
This value from production test must be loaded from the NVM software calibration row into the CALIB register by
software to allow the conversion and achieve the specified accuracy.
The copied value must not be modified.
Bits 7:0 – LINEARITY_CAL[7:0]ꢀLinearity Calibration Value
This value from production test must be loaded from the NVM software calibration row into the CALIB register by
software to allow the conversion and achieve the specified accuracy.
The copied value must not be modified.
DS40001882G-page 814
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ADC – Analog-to-Digital Converter
33.8.20 Debug Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DBGCTRL
0x2A
0x00
Property:ꢀ Write-Protected
Bit
7
6
5
4
3
2
1
0
DBGRUN
R/W
Access
Reset
0
Bit 0 – DBGRUNꢀDebug Run
This bit can be changed only while the ADC is disabled.
This bit should be written only while a conversion is not ongoing.
Value
Description
0
The ADC is halted during debug mode.
1
The ADC continues normal operation during debug mode.
DS40001882G-page 815
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SAM D21/DA1 Family
AC – Analog Comparators
34.
AC – Analog Comparators
34.1
Overview
The Analog Comparator (AC) supports multiple individual comparators. Each comparator (COMP) compares the
voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be
configured to generate interrupt requests and/or peripheral events upon several different combinations of input
change.
Hysteresis can be adjusted to achieve the optimal operation for each application.
The input selection includes four shared analog port pins and several internal signals. Each comparator output state
can also be output on a pin for use by external devices.
The comparators are grouped in pairs on each port. The AC peripheral implements one or two pairs of comparators .
These are called Comparator 0 (COMP0) and Comparator 1 (COMP1) for the first pair and Comparator 2 (COMP2)
and Comparator 3 (COMP3) for the second pair. They have identical behaviors, but separate control registers. Each
pair can be set in window mode to compare a signal to a voltage range instead of a single voltage level.
34.2
Features
•
Up to Four individual comparators
Analog comparator outputs available on pins
– Asynchronous or synchronous
Flexible input selection:
•
•
– Four pins selectable for positive or negative inputs
– Ground (for zero crossing)
– Bandgap reference voltage
– 64-level programmable VDD scaler per comparator
– DAC (if available)
•
•
Interrupt generation on:
– Rising or falling edge
– Toggle
– End of comparison
Window function interrupt generation on:
– Signal above window
– Signal inside window
– Signal below window
– Signal outside window
•
•
Event generation on:
– Comparator output
– Window function inside/outside window
Optional digital filter on comparator output
DS40001882G-page 816
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SAM D21/DA1 Family
AC – Analog Comparators
34.3
Block Diagram
Figure 34-1.ꢀAnalog Comparator Block Diagram (First Pair)
AIN0
+
CMP0
COMP0
AIN1
-
HYSTERESIS
VDD
INTERRUPTS
INTERRUPT
SCALER
ENABLE
INTERRUPT MODE
SENSITIVITY
CONTROL
&
DAC
COMPCTRLn
WINCTRL
EVENTS
WINDOW
FUNCTION
ENABLE
GCLK_AC
BANDGAP
HYSTERESIS
+
AIN2
CMP1
COMP1
AIN3
-
Figure 34-2.ꢀAnalog Comparator Block Diagram (Second Pair)
AIN4
+
CMP2
COMP2
AIN5
-
HYSTERESIS
VDD
INTERRUPTS
SCALER
ENABLE
INTERRUPT
SENSITIVITY
CONTROL
&
INTERRUPT MODE
DAC
COMPCTRLn
WINCTRL
EVENTS
WINDOW
FUNCTION
ENABLE
GCLK_AC
BANDGAP
HYSTERESIS
+
AIN6
CMP3
COMP3
AIN7
-
DS40001882G-page 817
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SAM D21/DA1 Family
AC – Analog Comparators
34.4
Signal Description
Signal
Description
Analog input
Digital output
Type
AIN[7..0]
CMP[3..0]
Comparator inputs
Comparator outputs
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
34.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
34.5.1 I/O Lines
Using the AC’s I/O lines requires the I/O pins to be configured. Refer to PORT - I/O Pin Controller for details.
Related Links
23. PORT - I/O Pin Controller
34.5.2 Power Management
The AC will continue to operate in any sleep mode where the selected source clock is running. The AC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other
operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
34.5.3 Clocks
The AC bus clock (CLK_AC_APB) can be enabled and disabled in the Main Clock module, MCLK (see MCLK - Main
Clock, and the default state of CLK_AC_APB can be found in Peripheral Clock Masking.
Two generic clocks (GCLK_AC_DIG and GCLK_AC_ANA) are used by the AC. The digital clock (GCLK_AC_DIG)
is required to provide the sampling rate for the comparators, while the analog clock (GCLK_AC_ANA) is required for
low voltage operation (VDDANA < 2.5V) to ensure that the resistance of the analog input multiplexors remains low.
These clocks must be configured and enabled in the Generic Clock Controller before using the peripheral.
This generic clock is asynchronous to the bus clock (CLK_AC_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to 34.6.15 Synchronization for further details.
Related Links
16. PM – Power Manager
34.5.4 DMA
Not applicable.
34.5.5 Interrupts
The interrupt request lines are connected to the interrupt controller. Using the AC interrupts requires the interrupt
controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
DS40001882G-page 818
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SAM D21/DA1 Family
AC – Analog Comparators
34.5.6 Events
The events are connected to the Event System. Refer to EVSYS – Event System for details on how to configure the
Event System.
Related Links
24. EVSYS – Event System
34.5.7 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging.
34.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
•
•
Control B register (CTRLB)
Interrupt Flag register (INTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
34.5.9 Analog Connections
Each comparator has up to four I/O pins that can be used as analog inputs. Each pair of comparators shares the
same four pins. These pins must be configured for analog operation before using them as comparator inputs.
Any internal reference source, such as a bandgap voltage reference, or DAC must be configured and enabled prior to
its use as a comparator input.
34.6
Functional Description
34.6.1 Principle of Operation
Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection
of analog input pins. Each negative input may be chosen from a selection of both analog input pins and internal
inputs, such as a bandgap voltage reference.
The digital output from the comparator is '1' when the difference between the positive and the negative input voltage
is positive, and '0' otherwise.
The individual comparators can be used independently (normal mode) or paired to form a window comparison
(window mode).
34.6.2 Basic Operation
34.6.2.1 Initialization
Before enabling the AC, the input and output events must be configured in the Event Control register (EVCTRL).
These settings cannot be changed while the AC is enabled.
34.6.2.2 Enabling, Disabling and Resetting
The AC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The AC is disabled
writing a '0' to CTRLA.ENABLE.
The AC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the AC will be reset to their initial state, and the AC will be disabled. Refer to CTRLA for details.
DS40001882G-page 819
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AC – Analog Comparators
The individual comparators must be also enabled by writing a '1' to the Enable bit in the Comparator x
Control registers (COMPCTRLx.ENABLE). However, when the AC is disabled, this will also disable the individual
comparators, but will not clear their COMPCTRLx.ENABLE bits.
Related Links
34.8.1 CTRLA
34.6.2.3 Comparator Configuration
Each individual comparator must be configured by its respective Comparator Control register (COMPCTRLx) before
that comparator is enabled. These settings cannot be changed while the comparator is enabled.
•
•
•
Select the desired measurement mode with COMPCTRLx.SINGLE. See Starting a Comparison for more details.
Select the hysteresis with the COMPCTRLx.HYST bit. See Input Hysteresis for more details.
Select the comparator speed versus power with COMPCTRLx.SPEED. See Propagation Delay vs. Power
Consumption for more details.
•
•
Select the interrupt source with COMPCTRLx.INTSEL.
Select the positive and negative input sources with the COMPCTRLx.MUXPOS and COMPCTRLx.MUXNEG
bits. See Selecting Comparator Inputs for more details.
•
•
Select the filtering option with COMPCTRLx.FLEN.
Select standby operation with Run in Standby bit (COMPCTRLx.RUNSTDBY).
The individual comparators are enabled by writing a '1' to the Enable bit in the Comparator x Control registers
(COMPCTRLx.ENABLE). The individual comparators are disabled by writing a '0' to COMPCTRLx.ENABLE. Writing
a '0' to CTRLA.ENABLE will also disable all the comparators, but will not clear their COMPCTRLx.ENABLE bits.
34.6.2.4 Starting a Comparison
Each comparator channel can be in one of two different measurement modes, determined by the Single bit in the
Comparator x Control register (COMPCTRLx.SINGLE):
•
•
Continuous measurement
Single-shot
After being enabled, a start-up delay is required before the result of the comparison is ready. This start-up time is
measured automatically to account for environmental changes, such as temperature or voltage supply level, and is
specified in Electrical Characteristics. During the start-up time, the COMP output is not available.
The comparator can be configured to generate interrupts when the output toggles, when the output changes from
'0' to '1' (rising edge), when the output changes from '1' to '0' (falling edge) or at the end of the comparison. An end-
of-comparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of
the state of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator
Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of
whether the interrupt is enabled or not.
Related Links
37. Electrical Characteristics at 85℃
34.6.2.4.1 Continuous Measurement
Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator
is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always
available in the Current State bit in the Status A register (STATUSA.STATEx).
After the start-up time has passed, a comparison is done and STATUSA is updated. The Comparator x Ready bit
in the Status B register (STATUSB.READYx) is set, and the appropriate peripheral events and interrupts are also
generated. New comparisons are performed continuously until the COMPCTRLx.ENABLE bit is written to zero. The
start-up time applies only to the first comparison.
In continuous operation, edge detection of the comparator output for interrupts is done by comparing the current
and previous sample. The sampling rate is the CLK_AC_DIG frequency. An example of continuous measurement is
shown in the next figure.
DS40001882G-page 820
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AC – Analog Comparators
Figure 34-3.ꢀContinuous Measurement Example
GCLK_AC
Write ‘1’
2-3 cycles
COMPCTRLx.ENABLE
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
For low-power operation, comparisons can be performed during sleep modes without a clock. The comparator is
enabled continuously, and changes of the comparator state are detected asynchronously. When a toggle occurs,
the Power Manager will start CLK_AC_DIG to register the appropriate peripheral events and interrupts. The
CLK_AC_DIG clock is then disabled again automatically, unless configured to wake up the system from sleep.
Related Links
37. Electrical Characteristics at 85℃
34.6.2.4.2 Single-Shot
Single-shot operation is selected by writing COMPCTRLx.SINGLE to '1'. During single-shot operation, the
comparator is normally idle. The user starts a single comparison by writing '1' to the respective Start Comparison
bit in the write-only Control B register (CTRLB.STARTx). The comparator is enabled, and after the start-up time has
passed, a single comparison is done and STATUSA is updated. Appropriate peripheral events and interrupts are also
generated. No new comparisons will be performed.
Writing '1' to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx).
STATUSB.READYx is set automatically by hardware when the single comparison has completed.
To remove the need for polling, an additional means of starting the comparison is also available. A read of the Status
C register (STATUSC) will start a comparison on all comparators currently configured for single-shot operation. The
read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a comparison, the
read will stall until the current comparison is compete, and a new comparison will not be started.
A single-shot measurement can also be triggered by the Event System. Setting the Comparator x Event Input bit in
the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator
can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation;
the difference is that a peripheral event from another hardware module causes the hardware to automatically start the
comparison and clear STATUSB.READYx.
To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the
current measurement is compared with the result of the previous measurement (one sampling period earlier). An
example of single-shot operation is shown in the figure below.
Figure 34-4.ꢀSingle-Shot Example
GCLK_AC
Write ‘1’
Write ‘1’
2-3 cycles
2-3 cycles
CTRLB.STARTx
tSTARTUP
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event
occurs, the Power Manager will start CLK_AC_DIG. The comparator is enabled, and after the startup time has
passed, a comparison is done and appropriate peripheral events and interrupts are also generated. The comparator
and CLK_AC_DIG are then disabled again automatically, unless configured to wake up the system from sleep.
Related Links
37. Electrical Characteristics at 85℃
DS40001882G-page 821
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AC – Analog Comparators
34.6.3 Selecting Comparator Inputs
Each comparator has one positive and one negative input. The positive input is one of the external input pins (AINx).
The negative input can be fed either from an external input pin (AINx) or from one of the several internal reference
voltage sources common to all comparators. The user selects the input source as follows:
•
The positive input is selected by the Positive Input MUX Select bit group in the Comparator Control register
(COMPCTRLx.MUXPOS)
•
The negative input is selected by the Negative Input MUX Select bit group in the Comparator Control register
(COMPCTRLx.MUXNEG)
In the case of using an external I/O pin, the selected pin must be configured for analog use in the PORT Controller by
disabling the digital input and output. The switching of the analog input multiplexers is controlled to minimize crosstalk
between the channels. The input selection must be changed only while the individual comparator is disabled.
Note:ꢀ For internal use of the comparison results by the CCL, this bit must be 0x1 or 0x2.
34.6.4 Window Operation
Each comparator pair can be configured to work together in window mode. In this mode, a voltage range is
defined, and the comparators give information about whether an input signal is within this range or not. Window
mode is enabled by the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators
in a pair must have the same measurement mode setting in their respective Comparator Control Registers
(COMPCTRLx.SINGLE).
To physically configure the pair of comparators for window mode, the same I/O pin must be chosen as positive input
for each comparator, providing a shared input signal. The negative inputs define the range for the window. In Figure
34-5, COMP0 defines the upper limit and COMP1 defines the lower limit of the window, as shown but the window
will also work in the opposite configuration with COMP0 lower and COMP1 higher. The current state of the window
function is available in the Window x State bit group of the Status register (STATUS.WSTATEx).
Window mode can be configured to generate interrupts when the input voltage changes to below the window, when
the input voltage changes to above the window, when the input voltage changes into the window or when the input
voltage changes outside the window. The interrupt selections are set by the Window Interrupt Selection bit field in the
Window Control register (WINCTRL.WINTSEL). Events are generated using the inside/outside state of the window,
regardless of whether the interrupt is enabled or not. Note that the individual comparator outputs, interrupts and
events continue to function normally during window mode.
When the comparators are configured for window mode and single-shot mode, measurements are performed
simultaneously on both comparators. Writing '1' to either Start Comparison bit in the Control B register
(CTRLB.STARTx) will start a measurement. Likewise either peripheral event can start a measurement.
DS40001882G-page 822
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AC – Analog Comparators
Figure 34-5.ꢀComparators in Window Mode
+
-
STATE0
COMP0
UPPER LIMIT OF WINDOW
INPUT SIGNAL
WSTATE[1:0]
INTERRUPT
SENSITIVITY
INTERRUPTS
CONTROL
&
WINDOW
FUNCTION
EVENTS
+
-
STATE1
COMP1
LOWER LIMIT OF WINDOW
34.6.5 Voltage Doubler
The AC contains a voltage doubler that can reduce the resistance of the analog multiplexors when the supply
voltage is below 2.5V. The voltage doubler is normally switched on/off automatically based on the supply level. When
enabling the comparators, additional start-up time is required for the voltage doubler to settle. If the supply voltage is
guaranteed to be above 2.5V, the voltage doubler can be disabled by writing the Low-Power Mux bit in the Control A
register (CTRLA.LPMUX) to one. Disabling the voltage doubler saves power and reduces the start-up time.
34.6.6 VDDANA Scaler
The VDDANA scaler generates a reference voltage that is a fraction of the device’s supply voltage, with 64 levels.
One independent voltage channel is dedicated for each comparator. The scaler of a comparator is enabled when the
Negative Input Mux bit field in the respective Comparator Control register (COMPCTRLx.MUXNEG) is set to 0x5 and
the comparator is enabled. The voltage of each channel is selected by the Value bit field in the Scaler x registers
(SCALERx.VALUE).
DS40001882G-page 823
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AC – Analog Comparators
Figure 34-6.ꢀVDDANA Scaler
SCALERx.
VALUE
6
COMPCTRLx.MUXNEG
== 5
to
COMPx
34.6.7 Input Hysteresis
Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help
prevent constant toggling of the output, which can be caused by noise when the input signals are close to each other.
Hysteresis is enabled for each comparator individually by the Hysteresis Enable bit in the Comparator x Control
register (COMPCTRLx.HYSTEN). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0).
34.6.8 Propagation Delay vs. Power Consumption
It is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or
the lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit
group in the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current
provided to the comparator, and as such will also affect the start-up time.
34.6.9 Filtering
The output of the comparators can be filtered digitally to reduce noise. The filtering is determined by the Filter Length
bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each comparator. Filtering is
selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is
considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the GCLK_AC frequency.
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the
comparator output is validated. For continuous mode, the first valid output will occur when the required number of
filter samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the
previous N-1 samples, as shown in Figure 34-7. For single-shot mode, the comparison completes after the Nth filter
sample, as shown in Figure 34-8.
Figure 34-7.ꢀContinuous Mode Filtering
Sampling Clock
Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Majority
Filter Output
DS40001882G-page 824
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AC – Analog Comparators
Figure 34-8.ꢀSingle-Shot Filtering
Sampling Clock
Start
tSTARTUP
3-bit Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Sampled
Comparator Output
5-bit Majority
Filter Output
During sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous
measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly.
34.6.10 Comparator Output
The output of each comparator can be routed to an I/O pin by setting the Output bit group in the Comparator
Control x register (COMPCTRLx.OUT). This allows the comparator to be used by external circuitry. Either the raw,
non-synchronized output of the comparator or the CLK_AC-synchronized version, including filtering, can be used as
the I/O signal source. The output appears on the corresponding CMP[x] pin.
34.6.11 Offset Compensation
The Swap bit in the Comparator Control registers (COMPCTRLx.SWAP) controls switching of the input signals to a
comparator's positive and negative terminals. When the comparator terminals are swapped, the output signal from
the comparator is also inverted, as shown in Figure 34-9. This allows the user to measure or compensate for the
comparator input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the
comparator is disabled.
Figure 34-9.ꢀInput Swapping for Offset Compensation
+
MUXPOS
COMPx
CMPx
HYSTERESIS
-
ENABLE
SWAP
SWAP
MUXNEG
COMPCTRLx
34.6.12 Interrupts
The AC has the following interrupt sources:
•
•
Comparator (COMP0, COMP1, COMP2, COMP3): Indicates a change in comparator status.
Window (WIN0, WIN1): Indicates a change in the window status.
Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the
Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions
selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSELx[1:0]).
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the AC is reset. See INFLAG register for details on how
to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
DS40001882G-page 825
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AC – Analog Comparators
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
Related Links
11.2 Nested Vector Interrupt Controller
34.6.13 Events
The AC can generate the following output events:
•
•
Comparator (COMP0, COMP1, COMP2, COMP3): Generated as a copy of the comparator status
Window (WIN0, WIN1): Generated as a copy of the window inside/outside status
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.COMPEOx) enables the corresponding output event. Writing a zero to this bit disables the corresponding
output event. The events must be correctly routed in the Event System.
The AC can take the following action on an input event:
•
•
Single-shot measurement
Single-shot measurement in window mode
Writing a one to an Event Input bit into the Event Control register (EVCTRL.COMPEIx) enables the corresponding
action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several
events are connected to the AC, the enabled action will be taken on any of the incoming events. Refer to the Event
System chapter for details on configuring the event system.
When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In
normal mode, each comparator responds to its corresponding input event independently. For a pair of comparators in
window mode, either comparator event will trigger a comparison on both comparators simultaneously.
34.6.14 Sleep Mode Operation
The Run in Standby bits in the Comparator x Control registers (COMPCTRLx.RUNSTDBY) control the behavior
of the AC during standby sleep mode. Each RUNSTDBY bit controls one comparator. When the bit is zero, the
comparator is disabled during sleep, but maintains its current configuration. When the bit is one, the comparator
continues to operate during sleep. Note that when RUNSTDBY is zero, the analog blocks are powered off for the
lowest power consumption. This necessitates a start-up time delay when the system returns from sleep.
When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. While the CPU is sleeping,
single-shot comparisons are only triggerable by events. The AC can also be used during sleep modes where the
clock used by the AC is disabled, provided that the AC is still powered (not in shutdown). In this case, the behavior is
slightly different and depends on the measurement mode.
Table 34-1.ꢀSleep Mode Operation
COMPCTRLx.MODE RUNSTDBY=0
RUNSTDBY=1
0 (Continuous)
1 (Single-shot)
COMPx disabled GCLK_AC_DIG stopped, COMPx enabled
COMPx disabled GCLK_AC_DIG stopped, COMPx enabled only when triggered by an
input event
34.6.14.1 Continuous Measurement during Sleep
When a comparator is enabled in Continuous Measurement mode and GCLK_AC_DIG is disabled during sleep, the
comparator will remain continuously enabled and will function asynchronously. The current state of the comparator
is asynchronously monitored for changes. If an edge matching the interrupt condition is found, GCLK_AC_DIG is
started to register the interrupt condition and generate events. If the interrupt is enabled in the Interrupt Enable
registers (INTENCLR/SET), the AC can wake up the device; otherwise GCLK_AC_DIG is disabled until the next edge
detection. Filtering is not possible with this configuration.
DS40001882G-page 826
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Figure 34-10.ꢀContinuous Mode SleepWalking
GCLK_AC
Comparator State
Comparator
Output or Event
34.6.14.2 Single-Shot Measurement during Sleep
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event
occurs, the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the start-up time has
passed, a comparison is done, with filtering if desired, and the appropriate peripheral events and interrupts are also
generated, as the figure below. The comparator and GCLK_AC_DIG are then disabled again automatically, unless
configured to wake the system from sleep. Filtering is allowed with this configuration.
Figure 34-11.ꢀSingle-Shot SleepWalking
GCLK_AC
tSTARTUP
tSTARTUP
Input Event
Comparator
Output or Event
34.6.15 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
•
Software Reset bit in control register (CTRLA.SWRST)
Enable bit in control register (CTRLA.ENABLE)
Enable bit in Comparator Control register (COMPCTRLn.ENABLE)
The following registers are synchronized when written:
Window Control register (WINCTRL)
•
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
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AC – Analog Comparators
34.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
CTRLA
CTRLB
7:0
7:0
7:0
15:8
7:0
7:0
7:0
LPMUX
RUNSTDBY
ENABLE
START1
COMPEO1
COMPEI1
COMP1
SWRST
START0
COMPEO0
COMPEI0
COMP0
WINEO0
0x02
EVCTRL
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
...
INTENCLR
INTENSET
INTFLAG
Reserved
STATUSA
STATUSB
STATUSC
Reserved
WINCTRL
WIN0
WIN0
WIN0
COMP1
COMP0
COMP1
COMP0
7:0
7:0
7:0
WSTATE0[1:0]
STATE1
READY1
STATE1
STATE0
READY0
STATE0
SYNCBUSY
WSTATE0[1:0]
7:0
WINTSEL0[1:0]
WEN0
Reserved
0x0F
7:0
INTSEL[1:0]
INTSEL[1:0]
SPEED[1:0]
HYST
SPEED[1:0]
HYST
SINGLE
ENABLE
ENABLE
15:8
SWAP
SWAP
MUXPOS[1:0]
MUXPOS[1:0]
MUXNEG[2:0]
0x10
0x14
COMPCTRL0
23:16
31:24
7:0
OUT[1:0]
FLEN[2:0]
SINGLE
15:8
MUXNEG[2:0]
COMPCTRL1
Reserved
23:16
31:24
OUT[1:0]
FLEN[2:0]
0x18
...
0x1F
0x20
0x21
SCALER0
SCALER1
7:0
7:0
VALUE[5:0]
VALUE[5:0]
34.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-Synchronized"
or the "Read-Synchronized" property in each individual register description. For details, refer to Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 828
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34.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized
Bit
7
LPMUX
R/W
0
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
0
Bit 7 – LPMUXꢀLow-Power Mux
This bit is not synchronized
Value
Description
0
The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are
driven by the voltage doubler).
1
The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the
voltage doubler is disabled).
Bit 2 – RUNSTDBYꢀRun in Standby
This bit controls the behavior of the comparators during standby sleep mode.
This bit is not synchronized
Value
Description
0
1
The comparator pair is disabled during sleep.
The comparator pair continues to operate during sleep.
Bit 1 – ENABLEꢀEnable
Due to synchronization, there is a delay from the time when the register is updated until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is
set. STATUS.SYNCBUSY is cleared when the peripheral is enabled/disabled
Value
Description
0
The AC is disabled.
1
The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the
Comparator Control register (COMPCTRLn.ENABLE).
Bit 0 – SWRSTꢀSoftware Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the AC to their initial state, and the AC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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34.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x01
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
START1
R/W
0
0
START0
R/W
0
Access
Reset
Bits 0, 1 – STARTxꢀComparator x Start Comparison
Writing a '0' to this field has no effect.
Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the
Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is not
implemented, or if it is not enabled in single-shot mode, Writing a '1' has no effect.
This bit always reads as zero.
DS40001882G-page 830
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34.8.3 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x02
0x0000
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
15
7
14
6
13
12
11
3
10
2
9
COMPEI1
R/W
8
COMPEI0
R/W
Access
Reset
0
0
Bit
5
4
WINEO0
R/W
1
COMPEO1
R/W
0
COMPEO0
R/W
Access
Reset
0
0
0
Bits 8, 9 – COMPEIxꢀComparator x Event Input
Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, the
enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming events
caused the action.
These bits indicate whether a comparison will start or not on any incoming event.
Value
Description
0
1
Comparison will not start on any incoming event.
Comparison will start on any incoming event.
Bit 4 – WINEOxꢀWindow x Event Output Enable
These bits indicate whether the window x function can generate a peripheral event or not.
Value
Description
0
1
Window x Event is disabled.
Window x Event is enabled.
Bits 0, 1 – COMPEOxꢀComparator x Event Output Enable
These bits indicate whether the comparator x output can generate a peripheral event or not.
Value
Description
0
1
COMPx event generation is disabled.
COMPx event generation is enabled.
DS40001882G-page 831
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34.8.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x04
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Access
Reset
Bit 4 – WINxꢀWindow x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Window x interrupt.
Value
Description
0
1
The Window x interrupt is disabled.
The Window x interrupt is enabled.
Bits 0, 1 – COMPxꢀComparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit disables the Comparator x interrupt.
Value
Description
0
1
The Comparator x interrupt is disabled.
The Comparator x interrupt is enabled.
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34.8.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x05
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Access
Reset
Bit 4 – WINxꢀWindow x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit enables the Window x interrupt.
Value
Description
0
1
The Window x interrupt is disabled.
The Window x interrupt is enabled.
Bits 0, 1 – COMPxꢀComparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt.
Value
Description
0
1
The Comparator x interrupt is disabled.
The Comparator x interrupt is enabled.
DS40001882G-page 833
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AC – Analog Comparators
34.8.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x06
0x00
–
Property:ꢀ
Bit
7
6
5
4
WIN0
R/W
0
3
2
1
COMP1
R/W
0
0
COMP0
R/W
0
Access
Reset
Bit 4 – WINxꢀWindow x
This flag is set according to the Window x Interrupt Selection bit group in the WINCTRL register
(WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Window x interrupt flag.
Bits 0, 1 – COMPxꢀComparator x
Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx
always reads as zero.
This flag is set according to the Interrupt Selection bit group in the Comparator x Control register
(COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Comparator x interrupt flag.
DS40001882G-page 834
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AC – Analog Comparators
34.8.7 Status A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUSA
0x08
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
WSTATE0[1:0]
STATE1
STATE0
Access
Reset
R
0
R
0
R
0
R
0
Bits 5:4 – WSTATE0[1:0]ꢀWindow 0 Current State
These bits show the current state of the signal if the window 0 mode is enabled.
Value
0x0
0x1
0x2
0x3
Name
Description
ABOVE
INSIDE
BELOW
Signal is above window
Signal is inside window
Signal is below window
Reserved
Bits 0, 1 – STATExꢀComparator x Current State
This bit shows the current state of the output signal from COMPx. STATEx is valid only when STATUSB.READYx is
one.
DS40001882G-page 835
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34.8.8 Status B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUSB
0x09
0x00
–
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
READY1
READY0
Access
Reset
R
0
R
0
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bits 0, 1 – READYxꢀComparator x Ready
This bit is cleared when the comparator x output is not ready.
This bit is set when the comparator x output is ready.
If comparator x is not implemented, READYx always reads as zero.
DS40001882G-page 836
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34.8.9 Status C
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUSC
0x0A
0x00
–
Property:ꢀ
STATUSC is a copy of STATUSA (see STATUSA register), with the additional feature of automatically starting
single-shot comparisons. A read of STATUSC will start a comparison on all comparators currently configured for
single-shot operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already
busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be
started.
Bit
7
6
5
4
3
2
1
0
WSTATE0[1:0]
STATE1
STATE0
Access
Reset
R
0
R
0
R
0
R
0
Bits 5:4 – WSTATE0[1:0]ꢀWindow 0 Current State
These bits show the current state of the signal if the window 0 mode is enabled.
Value
0x0
0x1
0x2
0x3
Name
Description
ABOVE
INSIDE
BELOW
Signal is above window
Signal is inside window
Signal is below window
Reserved
Bits 0, 1 – STATExꢀComparator x Current State
This bit shows the current state of the output signal from COMPx. STATEx is valid only when STATUSB.READYx is
one.
DS40001882G-page 837
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34.8.10 Window Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
WINCTRL
0x0C
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
WEN0
R/W
0
WINTSEL0[1:0]
Access
Reset
R/W
0
R/W
0
Bits 2:1 – WINTSEL0[1:0]ꢀWindow 0 Interrupt Selection
These bits configure the Interrupt mode for the Comparator Window 0 mode.
Value
0x0
0x1
0x2
0x3
Name
Description
ABOVE
INSIDE
BELOW
OUTSIDE
Interrupt on signal above window
Interrupt on signal inside window
Interrupt on signal below window
Interrupt on signal outside window
Bit 0 – WEN0ꢀWindow 0 Mode Enable
Value
Description
0
1
Window mode is disabled for comparators 0 and 1.
Window mode is enabled for comparators 0 and 1.
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34.8.11 Comparator Control n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
COMPCTRL
0x10 + n*0x04 [n=0..1]
0x00000000
Property:ꢀ PAC Write-Protection, Write-Synchronized
Bit
31
23
30
22
14
6
29
21
13
28
20
12
27
26
25
FLEN[2:0]
R/W
24
Access
Reset
R/W
0
R/W
0
0
Bit
19
HYST
R/W
0
18
17
16
OUT[1:0]
Access
Reset
R/W
0
R/W
0
Bit
15
SWAP
R/W
0
11
10
9
8
MUXPOS[1:0]
MUXNEG[2:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
5
4
3
2
1
SINGLE
R/W
0
0
ENABLE
R/W
INTSEL[1:0]
SPEED[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 26:24 – FLEN[2:0]ꢀFilter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
Name
OFF
Description
No filtering
0x1
0x2
0x3-0x7
MAJ3
MAJ5
N/A
3-bit majority function (2 of 3)
5-bit majority function (3 of 5)
Reserved
Bit 19 – HYSTꢀHysteresis Enable
This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode
(COMPCTRLn. SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.
This bit is not synchronized.
These bits are not synchronized.
Value
Name
0
1
Hysteresis is disabled.
Hysteresis is enabled.
Bits 17:16 – OUT[1:0]ꢀOutput
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
OFF
Description
The output of COMPn is not routed to the COMPn I/O port
ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port
SYNC
N/A
The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port
Reserved
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Bit 15 – SWAPꢀSwap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset
cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
Description
0
The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the
negative input.
1
The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the
negative input.
Bits 13:12 – MUXPOS[1:0]ꢀPositive Input Mux Selection
These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
PIN0
PIN1
PIN2
PIN3
Description
I/O pin 0
I/O pin 1
I/O pin 2
I/O pin 3
Bits 10:8 – MUXNEG[2:0]ꢀNegative Input Mux Selection
These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can
only be written while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
PIN0
PIN1
PIN2
PIN3
Description
I/O pin 0
I/O pin 1
I/O pin 2
I/O pin 3
GND
Ground
VSCALE
BANDGAP
DAC
VDD scaler
Internal bandgap voltage
DAC output
Bits 6:5 – INTSEL[1:0]ꢀInterrupt Selection
These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
Name
Description
TOGGLE
RISING
FALLING
EOC
Interrupt on comparator output toggle
Interrupt on comparator output rising
Interrupt on comparator output falling
Interrupt on end of comparison (single-shot mode only)
Bits 3:2 – SPEED[1:0]ꢀSpeed Selection
This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only
while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Value
0x0
0x1
Name
LOW
HIGH
N/A
Description
Low speed
High speed
Reserved
0x2-0x3
Bit 1 – SINGLEꢀSingle-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while
COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
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Value
Description
0
1
Comparator n operates in continuous measurement mode.
Comparator n operates in single-shot mode.
Bit 0 – ENABLEꢀEnable
Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n. After writing to this bit, the value read back will not change until the
action initiated by the writing is complete.
Due to synchronization, there is a latency of at least two GCLK_AC_DIG clock cycles from updating the register until
the comparator is enabled/disabled. The bit will continue to read the previous state while the change is in progress.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits
remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
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SAM D21/DA1 Family
AC – Analog Comparators
34.8.12 Scaler n
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
SCALER
0x20 + n*0x01 [n=0..1]
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
VALUE[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 5:0 – VALUE[5:0]ꢀScaler Value
These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is:
V
⋅ VALUE+1
DD
V
=
SCALE
64
DS40001882G-page 842
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SAM D21/DA1 Family
DAC – Digital-to-Analog Converter
35.
DAC – Digital-to-Analog Converter
35.1
Overview
The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC has one channel with 10-bit
resolution, and it is capable of converting up to 350,000 samples per second (350ksps).
35.2
35.3
Features
•
•
•
•
•
•
DAC with 10-bit resolution
Up to 350ksps conversion rate
Multiple trigger sources
High-drive capabilities
Output can be used as input to the Analog Comparator (AC)
DMA support
Block Diagram
Figure 35-1.ꢀDAC Block Diagram
DATABUF
Internal input
ADC Input
Output
Buffer
VOUT
DATA
DAC10
VREFA
VDDANA
Ref.voltage (VREF)
DAC Controller
35.4
Signal Description
Signal Name
VOUT
Type
Description
Analog output
Analog input
DAC output
VREFA
External reference
Related Links
7. I/O Multiplexing and Considerations
35.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
35.5.1 I/O Lines
Using the DAC Controller’s I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Related Links
23. PORT - I/O Pin Controller
DS40001882G-page 843
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SAM D21/DA1 Family
DAC – Digital-to-Analog Converter
35.5.2 Power Management
The DAC will continue to operate in any Sleep mode where the selected source clock is running.
The DAC interrupts can be used to wake up the device from sleep modes.
Events connected to the event system can trigger other operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
35.5.3 Clocks
The DAC bus clock (CLK_DAC_APB) can be enabled and disabled by the Power Manager, and the default state of
CLK_DAC_APB can be found in the Peripheral Clock Masking section.
A generic clock (GCLK_DAC) is required to clock the DAC Controller. This clock must be configured and enabled in
the Generic Clock Controller before using the DAC Controller. Refer to GCLK – Generic Clock Controller for details.
This generic clock is asynchronous to the bus clock (CLK_DAC_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to 35.6.7 Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
35.5.4 DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the DAC Controller DMA requests requires
to configure the DMAC first.
Related Links
20. DMAC – Direct Memory Access Controller
35.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DAC Controller interrupt(s) requires the
interrupt controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
35.5.6 Events
The events are connected to the Event System.
Related Links
24. EVSYS – Event System
35.5.7 Debug Operation
When the CPU is halted in debug mode the DAC will halt normal operation. Any on-going conversions will be
completed. The DAC can be forced to continue normal operation during debugging. If the DAC is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
35.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except the
following registers:
•
•
Interrupt Flag Status and Clear (INTFLAG) register
Data Buffer (DATABUF) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger
DS40001882G-page 844
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DAC – Digital-to-Analog Converter
Related Links
11.6 Peripheral Access Controller (PAC)
35.5.9 Analog Connections
The DAC has one output pin (VOUT) and one analog input pin (VREFA) that must be configured first.
When internal input is used, it must be enabled before DAC Controller is enabled.
35.6
Functional Description
35.6.1 Principle of Operation
The DAC converts the digital value located in the Data register (DATA) into an analog voltage on the DAC output
(VOUT).
A conversion is started when new data is written to the Data register. The resulting voltage is available on the DAC
output after the conversion time. A conversion can also be started by input events from the Event System.
35.6.2 Basic Operation
35.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the DAC is disabled
(CTRLA.ENABLE is zero):
•
•
Control B register (CTRLB)
Event Control register (EVCTRL)
Enable-protection is denoted by the Enable-Protected property in the register description.
Before enabling the DAC, it must be configured by selecting the voltage reference using the Reference Selection bits
in the Control B register (CTRLB.REFSEL).
35.6.2.2 Enabling, Disabling and Resetting
The DAC Controller is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The DAC
Controller is disabled by writing a '0' to CTRLA.ENABLE.
The DAC Controller is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the DAC will be reset to their initial state, and the DAC Controller will be disabled. Refer to the CTRLA
register for details.
35.6.2.3 Enabling the Output Buffer
To enable the DAC output on the VOUT pin, the output driver must be enabled by writing a one to the External Output
Enable bit in the Control B register (CTRLB.EOEN).
The DAC output buffer provides a high-drive-strength output, and is capable of driving both resistive and capacitive
loads. To minimize power consumption, the output buffer should be enabled only when external output is needed.
35.6.2.4 Digital to Analog Conversion
The DAC converts a digital value (stored in the DATA register) into an analog voltage. The conversion range is
between GND and the selected DAC voltage reference. The default voltage reference is the internal reference
voltage. Other voltage reference options are the analog supply voltage (VDDANA) and the external voltage reference
(VREFA). The voltage reference is selected by writing to the Reference Selection bits in the Control B register
(CTRLB.REFSEL).
The output voltage from the DAC can be calculated using the following formula:
DATA
0x3FF
V
=
⋅ VREF
OUT
A new conversion starts as soon as a new value is loaded into DATA. DATA can either be loaded via the APB bus
during a CPU write operation, using DMA, or from the DATABUF register when a START event occurs. Refer to
35.6.5 Events for details. As there is no automatic indication that a conversion is done, the sampling period must be
greater than or equal to the specified conversion time.
DS40001882G-page 845
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DAC – Digital-to-Analog Converter
35.6.3 DMA Operation
The DAC generates the following DMA request:
•
Data Buffer Empty (EMPTY): The request is set when data is transferred from DATABUF to the internal data
buffer of DAC. The request is cleared when DATABUF register is written, or by writing a one to the EMPTY bit in
the Interrupt Flag register (INTFLAG.EMPTY).
For each Start Conversion event, DATABUF is transferred into DATA and the conversion starts. When DATABUF
is empty, the DAC generates the DMA request for new data. As DATABUF is initially empty, a DMA request is
generated whenever the DAC is enabled.
If the CPU accesses the registers that are the source of a DMA request set/clear condition, the DMA request can be
lost or the DMA transfer can be corrupted, if enabled.
When DAC registers are write-protected by Peripheral Access Controller, DATABUF cannot be written. To bypass
DATABUF write protection, Bypass DATABUF Write Protection bit (CTRLB.BDWP) must be written to '1'
35.6.4 Interrupts
The DAC Controller has the following interrupt sources:
•
•
Data Buffer Empty (EMPTY): Indicates that the internal data buffer of the DAC is empty.
Underrun (UNDERRUN): Indicates that the internal data buffer of the DAC is empty and a DAC start of
conversion event occurred. Refer to 35.6.5 Events for details.
•
Synchronization Ready (SYNCRDY): this asynchronous interrupt can be used to wake-up the device from any
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the DAC is reset. See
INTFLAG register for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated..
Related Links
11.2 Nested Vector Interrupt Controller
35.6.5 Events
The DAC Controller can generate the following output events:
•
Data Buffer Empty (EMPTY): Generated when the internal data buffer of the DAC is empty. Refer to DMA
Operation for details.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.EMPTYEO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
The DAC can take the following action on an input event:
•
Start Conversion (START): DATABUF value is transferred into DATA as soon as the DAC is ready for the next
conversion, and then conversion is started. START is considered as asynchronous to GCLK_DAC thus it is
resynchronized in DAC Controller. Refer to 35.6.2.4 Digital to Analog Conversion for details.
Writing a '1' to an Event Input bit in the Event Control register (EVCTRL.STARTEI) enables the corresponding action
on an input event. Writing a '0' to this bit disables the corresponding action on input event.
Notes:ꢀ
•
When several events are connected to the DAC Controller, the enabled action will be taken on any of the
incoming events.
•
When a DAC Start Conversion event is enabled, only DATABUF must be written (not DATA)
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DAC – Digital-to-Analog Converter
By default, DAC Controller detects rising edge events. Falling edge detection can be enabled by writing a '1' to
EVCTRL.INVEIx.
Related Links
24. EVSYS – Event System
35.6.6 Sleep Mode Operation
The generic clock for the DAC is running in idle sleep mode. If the Run In Standby bit in the Control A register
(CTRLA.RUNSTDBY) is one, the DAC output buffer will keep its value in standby sleep mode. If CTRLA.RUNSTDBY
is zero, the DAC output buffer will be disabled in standby sleep mode.
35.6.7 Synchronization
Due to the asynchronicity between main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read. A register can require:
•
•
•
•
Synchronization when written
Synchronization when read
Synchronization when written and read
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while its busy bit is one, the operation is discarded and an
error is generated.
The following bits need synchronization when written:
•
•
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
All bits in the Data register (DATA)
All bits in the Data Buffer register (DATABUF)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following bits need synchronization when read:
•
All bits in the Data register (DATA)
35.6.8 Additional Features
35.6.8.1 DAC as an Internal Reference
The DAC output can be internally enabled as input to the analog comparator. This is enabled by writing a one to the
Internal Output Enable bit in the Control B register (CTRLB.IOEN). It is possible to have the internal and external
output enabled simultaneously.
The DAC output can also be enabled as input to the Analog-to-Digital Converter. In this case, the output buffer must
be enabled.
35.6.8.2 Data Buffer
The Data Buffer register (DATABUF) and the Data register (DATA) are linked together to form a two-stage FIFO.
The DAC uses the Start Conversion event to load data from DATABUF into DATA and start a new conversion.
The Start Conversion event is enabled by writing a one to the Start Event Input bit in the Event Control register
(EVCTRL.STARTEI). If a Start Conversion event occurs when DATABUF is empty, an Underrun interrupt request is
generated if the Underrun interrupt is enabled.
The DAC can generate a Data Buffer Empty event when DATABUF becomes empty and new data can be loaded
to the buffer. The Data Buffer Empty event is enabled by writing a one to the Empty Event Output bit in the Event
Control register (EVCTRL.EMPTYEO). A Data Buffer Empty interrupt request is generated if the Data Buffer Empty
interrupt is enabled.
35.6.8.3 Voltage Pump
When the DAC is used at operating voltages lower than 2.5V, the voltage pump must be enabled. This enabling is
done automatically, depending on operating voltage.
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DAC – Digital-to-Analog Converter
The voltage pump can be disabled by writing a one to the Voltage Pump Disable bit in the Control B register
(CTRLB.VPD). This can be used to reduce power consumption when the operating voltage is above 2.5V.
The voltage pump uses the asynchronous GCLK_DAC clock, and requires that the clock frequency be at least four
times higher than the sampling period.
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DAC – Digital-to-Analog Converter
35.7
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CTRLB
7:0
7:0
7:0
RUNSTDBY
LEFTADJ
ENABLE
IOEN
SWRST
EOEN
REFSEL[1:0]
BDWP
VPD
EVCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
STATUS
EMPTYEO
STARTEI
7:0
7:0
7:0
7:0
7:0
15:8
SYNCRDY
SYNCRDY
SYNCRDY
EMPTY
EMPTY
EMPTY
UNDERRUN
UNDERRUN
UNDERRUN
SYNCBUSY
DATA[7:0]
0x08
DATA
DATA[15:8]
0x0A
...
Reserved
DATABUF
0x0B
7:0
DATABUF[7:0]
DATABUF[15:8]
0x0C
15:8
35.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-
protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 35.5.8 Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-
Synchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to
35.6.7 Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-
protection is denoted by the "Enable-Protected" property in each individual register description.
DS40001882G-page 849
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DAC – Digital-to-Analog Converter
35.8.1 Control A
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLA
0x00
0x00
Property:ꢀ PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
2
1
ENABLE
R/W
0
SWRST
R/W
0
RUNSTDBY
Access
Reset
R/W
0
0
Bit 2 – RUNSTDBYꢀRun in Standby
This bit is not synchronized
Value
0
1
Description
The DAC output buffer is disabled in standby sleep mode.
The DAC output buffer can be enabled in standby sleep mode.
Bit 1 – ENABLEꢀEnable DAC Controller
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRLA.ENABLE will read back immediately and the corresponding bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
1
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRSTꢀSoftware Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the DAC to their initial state, and the DAC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
1
There is no reset operation ongoing.
The reset operation is ongoing.
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DAC – Digital-to-Analog Converter
35.8.2 Control B
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
CTRLB
0x01
0x00
Property:ꢀ PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
BDWP
R/W
0
3
2
LEFTADJ
R/W
1
IOEN
R/W
0
0
EOEN
R/W
0
REFSEL[1:0]
VPD
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bits 7:6 – REFSEL[1:0]ꢀReference Selection
This bit field selects the Reference Voltage for the DAC.
Note:ꢀ INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.
Value
0x0
0x1
0x2
0x3
Name
INT1V
VDDANA
VREFA
Description
Internal voltage reference
Analog voltage supply
External reference
Reserved
Bit 4 – BDWPꢀBypass DATABUF Write Protection
This bit can bypass DATABUF write protection.
Value
Description
0
1
DATABUF register is write-protected by Peripheral Access Controller.
DATABUF register is not write-protected.
Bit 3 – VPDꢀVoltage Pump Disabled
This bit controls the behavior of the voltage pump.
Value
Description
0
1
Voltage pump is turned on/off automatically
Voltage pump is disabled.
Bit 2 – LEFTADJꢀLeft-Adjusted Data
This bit controls how the 10-bit conversion data is adjusted in the Data and Data Buffer registers.
Value
Description
0
1
DATA and DATABUF registers are right-adjusted.
DATA and DATABUF registers are left-adjusted.
Bit 1 – IOENꢀInternal Output Enable
Value
Description
0
1
Internal DAC output not enabled.
Internal DAC output enabled to be used by the AC.
Bit 0 – EOENꢀExternal Output Enable
Value
Description
0
The DAC output is turned off.
1
The high-drive output buffer drives the DAC output to the internal ADC Positive Mux Input Selection
and to the VOUT pin.
DS40001882G-page 851
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DAC – Digital-to-Analog Converter
35.8.3 Event Control
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
EVCTRL
0x02
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
1
EMPTYEO
R/W
0
STARTEI
R/W
Access
Reset
0
0
Bit 1 – EMPTYEOꢀData Buffer Empty Event Output
This bit indicates whether or not the Data Buffer Empty event is enabled and will be generated when the Data Buffer
register is empty.
Value
Description
0
1
Data Buffer Empty event is disabled and will not be generated.
Data Buffer Empty event is enabled and will be generated.
Bit 0 – STARTEIꢀStart Conversion Event Input
This bit indicates whether or not the Start Conversion event is enabled .
Value
Description
0
A new conversion will not be triggered on any incoming event.
Only DATA must be written (not DATABUF).
A new conversion will be triggered on any incoming event.
Only DATABUF must be written (not DATA).
1
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DAC – Digital-to-Analog Converter
35.8.4 Interrupt Enable Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENCLR
0x04
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
5
4
3
2
SYNCRDY
R/W
1
EMPTY
R/W
0
0
UNDERRUN
Access
Reset
R/W
0
0
Bit 2 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the Synchronization
Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – EMPTYꢀData Buffer Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Empty Interrupt Enable bit, which disables the Data Buffer Empty
interrupt.
Value
Description
0
1
The Data Buffer Empty interrupt is disabled.
The Data Buffer Empty interrupt is enabled.
Bit 0 – UNDERRUNꢀUnderrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Underrun Interrupt Enable bit, which disables the Data Buffer
Underrun interrupt.
Value
Description
0
1
The Data Buffer Underrun interrupt is disabled.
The Data Buffer Underrun interrupt is enabled.
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DAC – Digital-to-Analog Converter
35.8.5 Interrupt Enable Set
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTENSET
0x05
0x00
Property:ꢀ PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit
7
6
5
4
3
2
SYNCRDY
R/W
1
EMPTY
R/W
0
0
UNDERRUN
Access
Reset
R/W
0
0
Bit 2 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – EMPTYꢀData Buffer Empty Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer Empty
interrupt.
Value
Description
0
1
The Data Buffer Empty interrupt is disabled.
The Data Buffer Empty interrupt is enabled.
Bit 0 – UNDERRUNꢀUnderrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Data Buffer Underrun Interrupt Enable bit, which enables the Data Buffer Underrun
interrupt.
Value
Description
0
1
The Data Buffer Underrun interrupt is disabled.
The Data Buffer Underrun interrupt is enabled.
DS40001882G-page 854
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DAC – Digital-to-Analog Converter
35.8.6 Interrupt Flag Status and Clear
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
INTFLAG
0x06
0x00
Property:ꢀ PAC Write-Protection
Bit
7
6
5
4
3
2
SYNCRDY
R/W
1
EMPTY
R/W
0
0
UNDERRUN
Access
Reset
R/W
0
0
Bit 2 – SYNCRDYꢀSynchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the Synchronization
Ready interrupt.
Value
Description
0
1
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 1 – EMPTYꢀData Buffer Empty
This flag is cleared by writing a '1' to it or by writing new data to DATABUF.
This flag is set when data is transferred from DATABUF to DATA, and the DAC is ready to receive new data in
DATABUF, and will generate an interrupt request if INTENCLR/SET.EMPTY is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Data Buffer Empty interrupt flag.
Bit 0 – UNDERRUNꢀUnderrun
This flag is cleared by writing a '1' to it.
This flag is set when a start conversion event occurs when DATABUF is empty, and will generate an interrupt request
if INTENCLR/SET.UNDERRUN is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Underrun interrupt flag.
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DAC – Digital-to-Analog Converter
35.8.7 Status
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
STATUS
0x07
0x00
-
Property:ꢀ
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
Reset
R
0
Bit 7 – SYNCBUSYꢀSynchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
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35.8.8 Data DAC
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATA
0x08
0x0000
Property:ꢀ PAC Write-Protection, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
DATA[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bits 15:0 – DATA[15:0]ꢀData value to be converted
DATA register contains the 10-bit value that is converted to a voltage by the DAC. The adjustment of these 10 bits
within the 16-bit register is controlled by CTRLB.LEFTADJ.
Table 35-1.ꢀValid Data Bits
CTRLB.LEFTADJ
DATA
Description
0
1
DATA[9:0]
DATA[15:6]
Right adjusted, 10-bits
Left adjusted, 10-bits
DS40001882G-page 857
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
DAC – Digital-to-Analog Converter
35.8.9 Data Buffer
Name:ꢀ
Offset:ꢀ
Reset:ꢀ
DATABUF
0x0C
0x0000
Property:ꢀ Write-Synchronized
Bit
15
14
13
12
11
10
9
8
DATABUF[15:8]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
DATABUF[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bits 15:0 – DATABUF[15:0]ꢀData Buffer
DATABUF contains the value to be transferred into DATA register.
DS40001882G-page 858
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripheral Touch Controller (PTC)
36.
Peripheral Touch Controller (PTC)
36.1
Overview
The Peripheral Touch Controller (PTC) acquires signals in order to detect a touch on the capacitive sensors. The
external capacitive touch sensor is typically formed on a PCB, and the sensor electrodes are connected to the
analog front end of the PTC through the I/O pins in the device. The PTC supports both self- and mutual-capacitance
sensors.
In the mutual-capacitance mode, sensing is done using capacitive touch matrices in various X-Y configurations,
including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line.
In the self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor.
The number of available pins and the assignment of X- and Y-lines is depending on both package type and device
configuration. Refer to the Configuration Summary and I/O Multiplexing table for details.
Related Links
7. I/O Multiplexing and Considerations
2. Configuration Summary
36.2
Features
•
•
•
Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
Supports wake-up on touch from Standby Sleep mode
Supports mutual capacitance and self-capacitance sensing
– 6/10/16 buttons in self-capacitance mode, for 32-/48-/64- pins respectively
– 60/120/256 buttons in mutual-capacitance mode, for 32-/48-/64- pins respectively
– Mix-and-match mutual-and self-capacitance sensors
•
•
One pin per electrode – no external components
Load compensating charge sensing
– Parasitic capacitance compensation and adjustable gain for superior sensitivity
Zero drift over the temperature and VDD range
•
– Auto calibration and recalibration of sensors
•
•
•
•
•
Single-shot charge measurement
Hardware noise filtering and noise signal desynchronization for high conducted immunity
Selectable channel change delay allows choosing the settling time on a new channel, as required
Acquisition-start triggered by command or through auto-triggering feature
Low CPU utilization through interrupt on acquisition-complete
Related Links
7. I/O Multiplexing and Considerations
2. Configuration Summary
DS40001882G-page 859
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripheral Touch Controller (PTC)
36.3
Block Diagram
Figure 36-1.ꢀPTC Block Diagram Mutual-Capacitance
Input
Control
Compensation
Circuit
Y0
Y1
RS
Acquisition Module
- Gain control
- ADC
IRQ
- Filtering
Result
Ym
10
CX0Y0
X0
X1
Xn
X Line Driver
CXnYm
Note:ꢀ For SAM D21 the RS = 0, 20, 50, 100 KΩ.
Figure 36-2.ꢀPTC Block Diagram Self-Capacitance
Input
Control
Compensation
Circuit
Y0
Y1
RS
Acquisition Module
IRQ
- Gain control
- ADC
CY0
- Filtering
Result
Ym
10
CYm
X Line Driver
Note:ꢀ For SAM D21 the RS = 0, 20, 50, 100 KΩ.
DS40001882G-page 860
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripheral Touch Controller (PTC)
36.4
Signal Description
Table 36-1.ꢀSignal Description for PTC
Name
Y[m:0]
X[n:0]
Type
Description
Analog
Digital
Y-line (Input/Output)
X-line (Output)
Note:ꢀ The number of X- and Y-lines are device dependent. Refer to Configuration Summary for details.
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
2. Configuration Summary
36.5
System Dependencies
In order to use this Peripheral, configure the other components of the system as described in the following sections.
36.5.1 I/O Lines
The I/O lines used for analog X-lines and Y-lines must be connected to external capacitive touch sensor electrodes.
External components are not required for normal operation. However, to improve the EMC performance, a series
resistor of 1 kΩ or more can be used on X-lines and Y-lines.
36.5.1.1 Mutual-Capacitance Sensor Arrangement
A mutual-capacitance sensor is formed between two I/O lines - an X electrode for transmitting and Y electrode for
sensing. The mutual capacitance between the X and Y electrode is measured by the Peripheral Touch Controller.
Figure 36-3.ꢀMutual Capacitance Sensor Arrangement
Sensor Capacitance Cx,y
MCU
Cx0,y0 Cx0,y1 Cx0,ym
X0
Cx1,ym
Cx1,y0 Cx1,y1
X1
Xn
Cxn,y0 Cxn,y1 Cxn,ym
PTC
Module
Y0
Y1
Ym
36.5.1.2 Self-Capacitance Sensor Arrangement
A self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for
sensing the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller.
DS40001882G-page 861
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Peripheral Touch Controller (PTC)
Figure 36-4.ꢀSelf-Capacitance Sensor Arrangement
MCU
Sensor Capacitance Cy
Y0
Y1
Cy0
Cy1
PTC
Module
Ym
Cym
For more information about designing the touch sensor, refer to Buttons, Sliders and Wheels Touch Sensor Design
Guide.
36.5.2 Clocks
The PTC is clocked by the GCLK_PTC clock. The PTC operates from an asynchronous clock source and the
operation is independent of the main system clock and its derivative clocks, such as the peripheral bus clock
(CLK_APB). A number of clock sources can be selected as the source for the asynchronous GCLK_PTC. The clock
source is selected by configuring the Generic Clock Selection ID in the Generic Clock Control register. For more
information about selecting the clock sources, refer to GCLK - Generic Clock Controller.
The selected clock must be enabled in the Power Manager, before it can be used by the PTC. By default these clocks
are disabled. The frequency range of GCLK_PTC is 400kHz to 4MHz.
Related Links
15. GCLK - Generic Clock Controller
16. PM – Power Manager
36.6
Functional Description
In order to access the PTC, the user must use the Atmel Start QTouch Configurator to configure and link the
®
QTouch Library firmware with the application software. QTouch Library can be used to implement buttons, sliders,
and wheels in a variety of combinations on a single interface.
Figure 36-5.ꢀQTouch Library Usage
Compiler
Custom Code
Application
Link
QTouch
Library
For more information about QTouch Library, refer to the QTouch Library Peripheral Touch Controller User Guide.
DS40001882G-page 862
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.
Electrical Characteristics at 85℃
37.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
37.2
Thermal Considerations
Related Links
37.2.2 Junction Temperature
37.2.1 Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 37-1.ꢀThermal Resistance Data
Package Type
32-pin TQFP
48-pin TQFP
64-pin TQFP
32-pin QFN
θJA
θJC
64.7°C/W
63.6°C/W
60.9°C/W
40.9°C/W
32.0°C/W
32.5°C/W
41.8°C/W
43.97°C/W
53°C/W
23.1°C/W
12.2°C/W
12.2°C/W
15.2°C/W
10.9°C/W
10.7°C/W
2.26°C/W
2.91°C/W
4.74°C/W
48-pin QFN
64-pin QFN
35-ball WLCSP
45-ball WLCSP
64-pin UFBGA
37.2.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. TJ = TA + (PD x θJA)
2. TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
Related Links
37.2 Thermal Considerations
DS40001882G-page 863
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.3
Absolute Maximum Ratings
Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 37-2.ꢀAbsolute Maximum Ratings
Symbol
VDD
Description
Min.
Max.
3.8
Units
V
Power supply voltage
0
IVDD
Current into a VDD pin
Current out of a GND pin
Pin voltage with respect to GND and VDD
Storage temperature
-
92(1)
mA
mA
V
IGND
-
130(1)
VDD+0.6V
150
VPIN
GND-0.6V
-60
Tstorage
°C
1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of
GPIOs as shown in the table below. Also note that each VDD/GND pair is connected to two clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent
performance degradation or malfunctioning.
CAUTION
Handle the device following best practice ESD protection rules: Be aware that the human body can
accumulate charges large enough to impair functionality or destroy the device.
In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12.
NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that
are mandatory for correct device behavior.
CAUTION
Related Links
7.2.4 GPIO Clusters
7.2.4 GPIO Clusters
37.4
General Operating Ratings
The device must operate within the ratings in order for all other electrical characteristics and typical characteristics of
the device to be valid.
Table 37-3.ꢀGeneral Operating Conditions
Symbol
VDD
Parameter
Condition
Min.
1.62(1)
1.62(1)
-40
Typ.
3.3
3.3
25
Max.
3.63
3.63
85
Units
V
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
VDDANA
TA
V
°C
°C
TJ
-
-
100
1. With BOD33 disabled. If the BOD33 is enabled, check Table 37-21.
DS40001882G-page 864
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.5
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless
otherwise specified and are valid for a junction temperature up to TJ = 100°C. Refer to Power Supply and Start-Up
Considerations.
Table 37-4.ꢀSupply Characteristics
Symbol
Conditions
Voltage
Min.
Max.
Units
VDDIO
VDDIN
Full Voltage Range
1.62
3.63
V
VDDANA
Table 37-5.ꢀSupply Rise Rates
Symbol
Parameter
Rise Rate
Max.
Units
VDDIO
VDDIN
VDDANA
DC supply peripheral
I/Os, internal regulator
and analog supply
voltage
0.1
V/μs
Related Links
8. Power Supply and Start-Up Considerations
37.6
Maximum Clock Frequencies
Table 37-6.ꢀMaximum GCLK Generator Output Frequencies
Symbol
Description
GCLK Generator Output Frequency
Conditions
Undivided
Divided
Max.
Units
MHz
MHz
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
96
48
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 37-7.ꢀMaximum Peripheral Clock Frequencies
Symbol
fCPU
Description
Max. Units
CPU clock frequency
AHB clock frequency
APBA clock frequency
APBB clock frequency
48
48
48
48
MHz
MHz
MHz
MHz
fAHB
fAPBA
fAPBB
DS40001882G-page 865
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Description
Max. Units
fAPBC
APBC clock frequency
48
33
2
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
MHz
fGCLK_DFLL48M_REF
fGCLK_DPLL
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
fGCLK_DPLL_32K
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
96
96
48
48
48
48
64
48
fGCLK_WDT
fGCLK_RTC
RTC input clock frequency
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, fGCLK_TCC1
fGCLK_TCC2, fGCLK_TCC3,fGCLK_TC3
fGCLK_TC4, GCLK_TC5
fGCLK_TC6, GCLK_TC7
fGCLK_ADC
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0,TCC1 input clock frequency
TCC2, TCC3, TC3 input clock frequency
TC4,TC5 input clock frequency
TC6,TC7 input clock frequency
ADC input clock frequency
fGCLK_AC_DIG
AC digital input clock frequency
AC analog input clock frequency
AC1 digital input clock frequency
fGCLK_AC_ANA
fGCLK_AC1_DIG
DS40001882G-page 866
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Description
Max. Units
fGCLK_AC1_ANA
fGCLK_DAC
AC1 analog input clock frequency
DAC input clock frequency
64
48
48
13
13
KHz
MHz
MHz
MHz
MHz
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
fGCLK_I2S_1
I2S serializer 0 input clock frequency
I2S serializer 1 input clock frequency
37.7
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
– VDDIN = 1.8V, CPU is running on Flash with three wait states
•
•
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal
– DFLL48M using XOSC32K as reference and running at 48ꢀMHz
Clocks
•
– DFLL48M used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
•
•
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on flash with 1 wait states
Cache enabled
•
•
•
•
BOD33 disabled
DS40001882G-page 867
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-8.ꢀCurrent Consumption (Device Variant A)
Mode
Conditions
TA
Min.
Typ.
3.37
3.48
3.36
3.48
Max.
3.64
3.76
3.64
3.75
Units
ACTIVE
CPU running a While(1) algorithm
25°C 3.11
85°C 3.24
25°C 3.10
85°C 3.24
mA
CPU running a While(1) algorithm
VDDIN=1.8V,
CPU is running on Flash with 3 wait
states
CPU running a While(1) algorithm,
CPU is
running on Flash with 3 wait states
with
25°C 60*freq + 74 60*freq + 136 62*freq + 196 μA
(with freq in
85°C 62*freq + 154 62*freq + 228 62*freq + 302
MHz)
GCLKIN as reference
CPU running a Fibonacci algorithm
25°C 4.12
85°C 4.27
25°C 4.12
85°C 4.27
4.53
4.63
4.53
4.63
4.92
4.98
4.92
4.98
mA
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
CPU running a Fibonacci algorithm,
CPU is
running on Flash with 3 wait states
with
25°C 86*freq + 76 88*freq + 136 88*freq + 196 μA
(with freq in
85°C 88*freq + 156 88*freq + 230 88*freq + 302
MHz)
GCLKIN as reference
CPU running a CoreMark algorithm
25°C 5.78
85°C 5.93
25°C 5.17
85°C 5.35
6.32
6.47
5.60
5.73
6.80
7.00
5.96
6.10
mA
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
CPU running a CoreMark algorithm, 25°C 106*freq + 78 106*freq +
108*freq +
196
μA
CPU is
136
(with freq in
MHz)
running on Flash with 3 wait states
with
GCLKIN as reference
85°C 106*freq +
154
108*freq +
232
108*freq +
310
IDLE0
IDLE1
IDLE2
Default operating conditions
Default operating conditions
Default operating conditions
25°C 1.89
85°C 1.98
25°C 1.34
85°C 1.41
25°C 1.07
85°C 1.13
2.04
2.14
1.46
1.55
1.17
1.27
2.20
2.33
1.58
1.71
1.28
1.40
mA
DS40001882G-page 868
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Mode
Conditions
TA
Min.
Typ.
4.06
55.2
2.70
53.3
Max.
12.8
100
Units
STANDBY XOSC32K running
RTC running at 1kHz
25°C -
85°C -
25°C -
85°C -
μA
XOSC32K and RTC stopped
12.2
100
Table 37-9.ꢀCurrent Consumption (Device Variant B and L With Silicon Revision E)
Mode
Conditions
TA VCC
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1,8V
Typ.
3.7
3.8
3.7
3.8
Max.
Units
ACTIVE
CPU running a While 1 algorithm
3.9
4
mA
CPU running a While 1 algorithm
3.9
4
CPU running a While 1 algorithm,
with GCLKIN as reference
25°C 3.3V 72*Freq+107 76*Freq+111 µA (with freq in
MHz)
85°C 3.3V 72*Freq+198 76*Freq+210
CPU running a Fibonacci algorithm
CPU running a Fibonacci algorithm
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1.8V
4.2
4.3
4.2
4.3
4.6
4.7
4.6
4.7
mA
CPU running a Fibonacci algorithm,
with GCLKIN as reference
25°C 3.3V 83*Freq+107 87*Freq+111 µA(with freq in
MHz)
85°C 3.3V 84*Freq+199 87*Freq+216
CPU running a CoreMark algorithm
CPU running a CoreMark algorithm
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1.8V
5.2
5.3
4.8
4.9
5.7
5.8
5.1
5.2
CPU running a CoreMark algorithm,
with GCLKIN as reference
25°C 3.3V 104*Freq+109 108*Freq+113 µA (with freq in
MHz)
85°C 3.3V 104*Freq+200 109*Freq+212
IDLE0
IDLE1
IDLE2
Default operating conditions
Default operating conditions
Default operating conditions
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
2.4
2.5
1.8
1.9
1.3
1.4
4
2.5
2.6
1.9
2.0
1.4
1.5
6.2
100
5.0
98.8
mA
STANDBY XOSC32K running, RTC running at
1kHz
µA
54
XOSC32K and RTC stopped
2.8
52
DS40001882G-page 869
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-10.ꢀCurrent Consumption (Device Variant B, C, D, L with Silicon Revision F and Silicon Revision G)
Mode
Conditions
TA VCC
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1,8V
Typ.
3.7
3.8
3.7
3.8
Max.
3.9
4
Units
ACTIVE
CPU running a While 1 algorithm
mA
CPU running a While 1 algorithm
3.9
4
CPU running a While 1 algorithm,
with GCLKIN as reference
25°C 3.3V 72*Freq+107 76*Freq+111 µA (with freq in
MHz)
85°C 3.3V 72*Freq+198 76*Freq+210
CPU running a Fibonacci algorithm
CPU running a Fibonacci algorithm
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1.8V
4.2
4.3
4.2
4.3
4.6
4.7
4.6
4.7
mA
CPU running a Fibonacci algorithm,
with GCLKIN as reference
25°C 3.3V 83*Freq+107 87*Freq+111 µA(with freq in
MHz)
85°C 3.3V 84*Freq+199 87*Freq+216
CPU running a CoreMark algorithm
CPU running a CoreMark algorithm
25°C 3.3V
85°C 3.3V
25°C 1.8V
85°C 1.8V
5.2
5.3
4.8
4.9
5.7
5.8
5.1
5.2
CPU running a CoreMark algorithm,
with GCLKIN as reference
25°C 3.3V 104*Freq+109 108*Freq+113 µA (with freq in
MHz)
85°C 3.3V 104*Freq+200 109*Freq+212
IDLE0
IDLE1
IDLE2
Default operating conditions
Default operating conditions
Default operating conditions
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
25°C 3.3V
85°C 3.3V
2.4
2.5
1.8
1.9
1.3
1.4
4.6
43
2.5
2.6
mA
1.9
2
1.4
1.5
STANDBY XOSC32K running, RTC running at
1kHz
15.0
102.0
14.0
100.0
µA
XOSC32K and RTC stopped
3.4
42
DS40001882G-page 870
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-11.ꢀWake-up Time
Mode
Conditions
TA
Min. Typ. Max. Units
IDLE0
OSC8M used as main clock source, Cache disabled
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
-
-
-
-
-
-
-
-
4.0
-
-
-
-
-
-
-
-
μs
4.0
IDLE1
IOSC8M used as main clock source, Cache disabled
IOSC8M used as main clock source, Cache disabled
IOSC8M used as main clock source, Cache disabled
12.1
13.6
13.0
14.5
19.6
19.7
IDLE2
STANDBY
Figure 37-1.ꢀMeasurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
37.8
Peripheral Power Consumption
Since USB peripheral complies with the Universal Serial Bus (USB) v2.0 standard, USB peripheral power
consumption is described a specific section
37.8.1 All peripheral except USB
Default conditions, except where noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
•
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal
DS40001882G-page 871
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
– OSC8M at 8MHz
Clocks
•
– OSC8M used as main clock source
– CPU, AHB and APBn clocks undivided
•
•
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU in IDLE0 mode
•
•
•
•
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Operating mode for each peripheral in turn:
•
•
•
•
•
•
•
•
•
Configure and enable the peripheral GCLK (When relevant, see conditions)
Unmask the peripheral clock
Enable the peripheral (when relevant)
Set CPU in IDLE0 mode
Measurement Iperiph
Wake-up CPU via EIC (async: level detection, filtering disabled)
Disable the peripheral (when relevant)
Mask the peripheral clock
Disable the peripheral GCLK (when relevant, see conditions)
Each peripheral power consumption provided in table x.y is the value (Iperiph - Idefault), using the same measurement
method as for global power consumption measurement
Table 37-12.ꢀTypical Peripheral Current Consumption
Peripheral
RTC
Conditions
Typ.
7.4
Units
μA
fGCLK_RTC = 32kHz, 32bit counter mode
fGCLK_WDT=32kHz, normal mode with EW
Both fGCLK=8MHz, Enable both COMP
fGCLK=8MHz, Enable + COUNTER
fGCLK=8MHz, Enable + COUNTER
fGCLK=8MHz, Enable + COUNTER
fGCLK=8MHz, Enable
WDT
5.5
μA
ACx
31.3
95.5
μA
TCC2
μA
TCC1
167.5 μA
180.3 μA
TCC0
SERCOMx.I2CM(2)
SERCOMx.I2CS
SERCOMx.SPI
SERCOMx.USART
I2S(3)
69.7
29.2
64.6
65.5
26.4
μA
μA
μA
μA
μA
fGCLK=8MHz, Enable
fGCLK=8MHz, Enable
fGCLK=8MHz, Enable
fGCLK_I2S_0=12.288MHz with source FDPLL with fFDPLL=49,152MHz
RAM to RAM transfer
DMAC(4)
399.5 μA
DS40001882G-page 872
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Notes:ꢀ
1. All TCs from 4 to 7 share the same power consumption values.
2. All SERCOMs from 0 to 5 share the same power consumption values.
3. The value includes the power consumption of the FDPLL.
4. The value includes the power consumption of the R/W access to the RAM.
37.8.2 USB Peripheral Power Consumption
Default conditions, except where noted:
•
•
•
Operating conditions
– VVDDIN = 3.3ꢀV
Oscillators
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal in USB Host mode
Clocks
– USB Device mode: DFLL48M in USB recovery mode (Crystal less)
– USB Host mode: DFLL48M in closed loop with XOSC32K (32ꢀkHz crystal oscillator) running with external
32kHz crystal
– CPU, AHB and APBn clocks undivided
•
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
I/Os are inactive with internal pull-up
CPU in IDLE0 mode
•
•
•
•
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Measurements do not include consumption of clock source (ex: DFLL48M or FDPLL96M) and CPU. However no
CPU activity is required during all states (Suspend, IDLE, Data transfer).
Measurements have been done with an USB cable of 1.5m.
For USB Device mode, measurements include the maximum consumption (200μA) through pull-up resistor on the D+
line for USB attach. This value depends on USB Host characteristic.
Operating modes:
•
Run the USB Device/Host states in regards of the Universal Serial Bus (USB) v2.0 standard.
USB power consumption is provided in the following tables.
Table 37-13.ꢀTypical USB Device Full Speed mode Current Consumption
USB Device state
Conditions
Typ. Units
201 μA
Suspend
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
Suspend
IDLE
GCLK_USB is on.
USB bus in suspend mode.
0.83 mA
1.17 mA
2.17 mA
10.3 mA
Start Of Frame is running.
No packet transferred.
Active OUT
Active IN
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
Start Of Frame is running.
Bulk IN on 100% bandwidth.
DS40001882G-page 873
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-14.ꢀTypical USB Host Full Speed mode Current Consumption
USB Device state
Conditions
Typ. Units
Wait connection
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus not connected.
0.10 μA
Wait connection
Suspend
GCLK_USB is on.
USB bus not connected.
0.19 mA
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
201
μA
Suspend
GCLK_USB is on.
USB bus in suspend mode.
0.83 mA
1.17 mA
2.17 mA
10.3 mA
IDLE
Start Of Frame is running.
No packet transferred.
Active OUT
Active IN
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
Start Of Frame is running.
Bulk IN on 100% bandwidth.
37.9
I/O Pin Characteristics
37.9.1 Normal I/O Pins
Table 37-15.ꢀNormal I/O Pins Characteristics
Symbol Parameter
RPULL Pull-up - Pull-down
Conditions
Min.
Typ.
Max.
Units
All pins except for PA24 and PA25
20
40
60
kΩ
resistance
VIL
Input low-level voltage VDD=1.62V-2.7V
VDD=2.7V-3.63V
-
-
-
-
-
0.25*VDD
V
-
0.3*VDD
VIH
Input high-level
voltage
VDD=1.62V-2.7V
VDD=2.7V-3.63V
VDD>1.6V, IOL maxI
0.7*VDD
0.55*VDD
-
-
-
VOL
Output low-level
voltage
0.1*VDD 0.2*VDD
VOH
Output high-level
voltage
VDD>1.6V, IOH maxII
0.8*VDD 0.9*VDD -
DS40001882G-page 874
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
Output low-level
VDD=1.62V-3V,
-
-
1
mA
current
PORT.PINCFG.DRVSTR=0
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
-
-
-
-
-
-
-
-
-
-
2.5
3
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
10
0.70
2
IOH
Output high-level
current
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=0
-
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
2
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
7
tRISE
tFALL
ILEAK
Rise time(1)
PORT.PINCFG.DRVSTR=0load = 5pF,
VDD = 3.3V
-
15
15
15
15
ns
ns
μA
PORT.PINCFG.DRVSTR=1load = 20pF,
VDD = 3.3V
-
Fall time(1)
PORT.PINCFG.DRVSTR=0load = 5pF,
VDD = 3.3V
-
PORT.PINCFG.DRVSTR=1load = 20pF,
VDD = 3.3V
-
Input leakage current
Pull-up resistors disabled
-1
+/-0.015 1
Note:ꢀ 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
37.9.2 I2C Pins
Refer to I/O Multiplexing and Considerations to get the list of I2C pins.
Table 37-16.ꢀI2C Pins Characteristics in I2C configuration
Symbol Parameter
Condition
Min.
Typ. Max.
Units
VIL
Input low-level voltage
VDD=1.62V-2.7V
VDD=2.7V-3.63V
VDD=1.62V-2.7V
VDD=2.7V-3.63V
-
-
-
-
-
-
-
0.25*VDD
V
-
0.3*VDD
VIH
Input high-level voltage
0.7*VDD
0.55*VDD
0.08*VDD
-
-
-
VHYS
VOL
Hysteresis of Schmitt trigger inputs
Output low-level voltage
-
VDD> 2.0V,
IOL=3mA
0.4
VDD≤2.0V
, IOL=2mA
-
-
0.2*VDD
DS40001882G-page 875
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Condition
Min.
Typ. Max.
Units
IOL
Output low-level current
VOL =0.4V
3
mA
Standard, Fast and HS Modes
VOL =0.4V
20
-
-
Fast Mode +
VOL =0.6V
6
-
-
-
-
fSCL
SCL clock frequency
3.4
MHz
I2C pins timing characteristics can be found in 37.16.3 SERCOM in I2C Mode Timing.
37.9.3 XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to table 37.9.1 Normal I/O Pins.
37.9.4 XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table 37.9.1 Normal I/O Pins.
37.9.5 External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table 37.9.1 Normal I/O Pins.
37.10 Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 37-17.ꢀInjection Current(1)
Symbol
Description
min
-1
max
+1
Unit
mA
mA
mA
(2)
Iinj1
IO pin injection current
IO pin injection current
Sum of IO pins injection current
(3)
Iinj2
-15
-45
+15
+45
Iinjtotal
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Conditions for Vpin: Vpin < GND-0.6V or 3.6V<Vpin≤4.2V.
Conditions for VDD: 3V<VDD≤3.6V.
If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting
resistor R is calculated as R = |(GND-0.6V – Vpin)/Iinj1|.
If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting
resistor R is calculated as R = (Vpin-(VDD+0.6))/Iinj1
.
3. Conditions for Vpin: Vpin < GND-0.6V or Vpin≤3.6V.
Conditions for VDD: VDD≤3V.
If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting
resistor R is calculated as R = |(GND-0.6V – Vpin)/Iinj2|.
If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting
resistor R is calculated as R = (Vpin-(VDD+0.6))/Iinj2
.
DS40001882G-page 876
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.11 Analog Characteristics
37.11.1 Voltage Regulator Characteristics
Table 37-18.ꢀVoltage Regulator Electrical Characteristics
Symbol
Parameter
Conditions
Voltage regulator normal mode
Min. Typ. Max. Units
VDDCORE
DC calibrated output voltage
1.1
1.23 1.30
V
Note:ꢀ Supplying any external components using the VDDCORE pin is not allowed to assure the integrity of the core
supply voltage.
Table 37-19.ꢀDecoupling requirements
Symbol
Parameter
Conditions
Min. Typ. Max. Units
(1)
CIN
Input regulator capacitor, between VDDIN and GND
Ceramic dielectric X7R -
-
10
100
1
-
-
-
µF
nF
µF
(2)
COUT
Output regulator capacitor, between VDDCORE and
GND
-
0.8
ESR Cout External Series Resistance of Cout
-
-
1
Ω
Note:ꢀ 1. It is recommended to use ceramic X7R capacitor with low-series resistance. Refer to Figure 45-1 for a
typical circuit connections of the decoupling capacitor.
Note:ꢀ 2. It is recommended to use ceramic or solid tantalum capacitor with low ESR <= 1 ohms.
37.11.2 Power-On Reset (POR) Characteristics
Table 37-20.ꢀPOR Characteristics
Symbol
VPOT+
VPOT-
Parameter
Conditions
Min. Typ. Max. Units
Voltage threshold on VDD rising
Voltage threshold on VDD falling
VDD falls at 1V/ms or slower
1.27 1.45 1.58
0.72 0.99 1.32
V
V
DS40001882G-page 877
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-2.ꢀPOR Operating Principle
VPOT+
VPOT-
Time
37.11.3 Brown-Out Detectors Characteristics
37.11.3.1 BOD33
Figure 37-3.ꢀBOD33 Hysteresis OFF
VDD
VBOD
RESET pin
Figure 37-4.ꢀBOD33 Hysteresis ON
VBOD+
VDD
VBOD-
RESET pin
DS40001882G-page 878
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-21.ꢀBOD33 LEVEL Value (Silicon Revisions A, B, C, D, E, and F)
Symbol
VBOD+
BOD33.LEVEL
Conditions
Hysteresis ON
Min.
Typ.
1.715
1.750
2.84
3.2
Max.
1.745
1.779
2.92
3.3
Units
6
-
-
7
39
48
6
-
-
V
VBOD-
or
Hysteresis ON
or
1.62
1.64
2.72
3.0
1.64
1.675
2.77
3.07
1.67
1.71
2.81
3.2
7
VBOD
Hysteresis OFF
39
48
Note:ꢀ See chapter Memories table NVM User Row Mapping for the BOD33 default value settings.
Table 37-22.ꢀBOD33 LEVEL Value (Silicon Revision G)
Symbol
BOD33.LEVEL
Conditions
Min.
Typ.
Max.
Units
6
-
-
-
-
1.709 1.748
1.747 1.795
2.872 2.950
3.201 3.340
7
VBOD+
Hysteresis ON
39
48
6
V
1.590 1.638 1.680
1.620 1.670 1.710
2.680 2.764 2.840
2.980 3.071 3.200
7
VBOD- or VBOD
Hysteresis ON or Hysteresis OFF
39
48
Note:ꢀ Refer to NVM User Row Mapping for the BOD33 default value settings.
Table 37-23.ꢀBOD33 Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
34
Max. Units
Step size, between
adjacent values in
BOD33.LEVEL
-
-
35
-
-
170
-
mV
mV
μs
VHYST
tDET
VBOD+ - VBOD-
Detection time
Hysteresis ON
-
Time with VDDANA < VTH
necessary to generate a
reset signal
0.9(1)
IBOD33
Current consumption
Idle2,Continuous mode, VDD=3V
Idle2, Sampling mode, VDD=1.8V
STANDBY,Sample Mode, VDD=3.3V
-
-
-
-
-
25
50
0.034 1.62
μA
μs
0.132
2.2(1)
1
-
tSTARTUP
Startup time
Note:ꢀ 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
DS40001882G-page 879
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Related Links
10.3.1 NVM User Row Mapping
37.11.4 Analog-to-Digital (ADC) characteristics
Table 37-24.ꢀOperating Conditions
Symbol
RES
Parameter
Conditions
Min.
8
Typ.
Max.
12
Units
bits
Resolution
-
-
-
-
-
-
-
fCLK_ADC
ADC Clock frequency
Sample rate(1)
-
30
5
2100
300
350
-
kHz
ksps
ksps
ns
Single shot
Free running
5
Sampling time(1)
-
-
250
3
Sampling time with DAC as
input(2)
-
µs
Sampling time with Temp
sens as input(2)
-
-
10
10
-
-
-
-
µs
µs
Sampling time with
Bandgap as input(2)
Conversion time(1)
1x Gain
-
6
-
-
-
cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
1.0
VDDANA-0.6
INT1V
Internal 1V reference (2,4)
-
-
-
-
1.0
-
-
V
V
INTVCC0
Internal ratiometric
reference 0(2)
VDDANA/1.48
INTVCC0
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 0(2) error
INTVCC1
Internal ratiometric
reference 1(2)
VDDANA>2.0V
-
VDDANA/2
-
V
INTVCC1
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 1(2) error
Conversion range(1)
Differential mode
-VREF
/
-
+VREF/GAIN
V
GAIN
Single-ended mode
0.0
-
3.5
-
+VREF/GAIN
V
CSAMPLE
RSAMPLE
Sampling capacitance(2)
-
-
-
-
-
pF
kΩ
Input channel source
resistance(2)
3.5
IDD
DC supply current(1)
fCLK_ADC = 2.1 MHz(3)
-
1.25
1.79
mA
Notes:ꢀ
1. These values are based on characterization, and are not covered by test limits in production.
2. These values are based on simulation, and are not covered by test limits in production or characterization.
3. In this condition and for a sample rate of 350 ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock.
4. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
DS40001882G-page 880
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-25.ꢀDifferential Mode (Device Variant A)
Symbol Parameter Conditions
Min.
-
Typ.
10.5
4.3
Max.
11.1
15.0
4.5
Units
bits
LSB
LSB
LSB
mV
mV
mV
%
ENOB
TUE
INL
Effective Number Of Bits
With gain compensation
1x gain
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
1.5
1x gain
1.0
1.3
DNL
GE
1x gain
+/-0.3
-10.0
-15.0
-20.0
+/-0.1
+/-0.5 +/-0.95
Ext. Ref 1x
2.5
-1.5
-5.0
+10.0
+10.0
+20.0
VREF = VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
Gain Accuracy(5)
Offset Error
+/-0.2 +/-0.45
+/-0.05 +/-0.1 +/-0.11
%
OE
-5.0
-5.0
-5.0
62.7
54.1
54.5
-77.0
0.6
-1.5
0.5
+5.0
+5.0
+5.0
75.0
68.5
68.6
-63.0
1.6
mV
mV
mV
dB
VREF=VDDANA/1.48
VREF = INT1V
3.0
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1 MHz
70.0
65.0
65.5
-64.0
1.0
dB
FIN = 40 kHz
dB
AIN = 95% FSR
THD
Total Harmonic Distortion
Noise RMS
dB
T = 25°C
mV
Table 37-26.ꢀDifferential Mode (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
-
Typ.
10.5
2.7
Max.
10.8
Units
bits
LSB
LSB
LSB
mV
mV
mV
%
ENOB
TUE
INLI
Effective Number Of Bits
With gain compensation
1x gain
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
1.5
10.0
1x gain
0.9
1.3
4.0
DNL
GE
1x gain
+/-0.3
-10.0
-20.0
-20.0
+/-0.5
1.3
+/-0.95
+10.0
+10.0
+20.0
+/-0.1
+/-0.5
+5.0
Ext. Ref 1x
VREF = VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
-10.0
-2.0
Gain Accuracy(5)
Offset Error
+/-0.02 +/-0.05
+/-0.01 +/-0.03
%
OE
-5.0
-5.0
-5.0
-1.0
-0.60
-1.0
mV
mV
mV
VREF = VDDANA/1.48
VREF = INT1V
+5.0
+5.0
DS40001882G-page 881
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min.
65
Typ.
71.3
65
Max.
77.0
67
Units
dB
SFDR
SINAD
SNR
Spurious Free Dynamic Range
1x gain
FCLK_ADC = 2.1 MHz
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
58
dB
FIN = 40 kHz
60
66
68.6
-67.0
1.6
dB
AIN = 95% FSR
THD
-75.0
0.6
-71.0
1.0
dB
T = 25°C
mV
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the
input voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage):
–
3.1.1I.f |VIN| > VREF/4
– VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 -0.05*VDDANA -0.1V
3.1.2I.f |VIN| < VREF/4
– VCM_IN < 1.2*VDDANA - 0.75V
– VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*Vref/GAIN)
Table 37-27.ꢀSingle-Ended Mode (Device Variant A)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
-
Typ.
9.5
Max.
9.8
Units
Bits
LSB
LSB
LSB
mV
%
ENOB
TUE
INL
Effective Number of Bits
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
Gain Error
-
10.5
1.6
14.0
3.5
1x gain
1.0
DNL
GE
1x gain
+/-0.5
-5.0
+/-0.2
+/-0.01
-5.0
63.1
47.5
48.0
-65.4
-
+/-0.6
0.7
+/-0.95
+5.0
+/-0.4
+/-0.2
+5.0
67.0
61.0
64.0
-62.1
-
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
Gain Accuracy(4)
+/-0.34
+/-0.1
1.5
%
OE
Offset Error
mV
dB
SFDR
SINAD
SNR
THD
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
1x gain
FCLK_ADC = 2.1 MHz
65.0
59.5
60.0
-63.0
1.0
dB
FIN = 40 kHz
dB
AIN = 95% FSR
dB
T = 25°C
mV
DS40001882G-page 882
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-28.ꢀSingle-Ended Mode (Device Variant B,C, D and L)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
-
Typ.
9.7
Max.
10.1
Units
Bits
LSB
LSB
LSB
mV
%
ENOB
TUE
INL
Effective Number of Bits
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
Gain Error
-
7.9
15.0
1x gain
1.4
2.6
4.5
DNL
GE
1x gain
+/-0.6
-5.0
+/-0.2
+/-0.01
-5.0
63.0
55.0
54.0
-70.8
-
+/-0.7
0.6
+/-0.95
+5.0
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
Gain Accuracy(4)
+/-0.37 +/-0.55
+/-0.1
0.6
+/-0.2
+5.0
71.0
63.0
64.0
-65.0
-
%
OE
Offset Error
mV
dB
SFDR
SINAD
SNR
THD
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
1x gain
FCLK_ADC = 2.1 MHz
68.0
60.1
61.0
-68.0
1.0
dB
FIN = 40 kHz
dB
AIN = 95% FSR
dB
T = 25°C
mV
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
37.11.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-
to-be-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 37-29.ꢀAveraging Feature (Device Variant A)
Average
Number
Conditions
SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66.0
67.6
69.7
70.4
65.0
65.8
67.1
67.5
72.8
75.1
75.3
75.5
9.75
8
10.62
10.85
10.91
32
128
DS40001882G-page 883
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-30.ꢀAveraging Feature (Device Variant B,C, D and L)
Average
Number
Conditions
SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66.0
67.6
69.7
70.4
65.0
65.8
67.1
67.5
72.8
75.1
75.3
75.5
10.5
8
10.62
10.85
10.91
32
128
37.11.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
Table 37-31.ꢀOffset and Gain correction feature
Gain Factor Conditions
Offset Error Gain Error Total Unadjusted
(mV)
0.25
0.20
0.15
-0.05
0.10
(mV)
Error (LSB)
0.5x
1x
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
1.0
2.4
1.5
2.7
3.2
6.1
0.10
-0.15
0.05
-0.05
2x
8x
16x
37.11.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally, the ADC input consists of a resistor (R ) and a capacitor
SAMPLE
(C
). In addition, the source resistance (R
) must be taken into account when calculating the required
SAMPLE
SOURCE
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
Figure 37-5.ꢀADC Input
VDDANA/2
Analog Input
C
AINx
SAMPLE
R
R
SAMPLE
SOURCE
V
IN
To achieve n bits of accuracy, the C
− n + 1
capacitor must be charged at least to a voltage of
SAMPLE
V
≥ V × 1 + − 2
IN
CSAMPLE
The minimum sampling time t
for a given R
can be found using this formula:
SAMPLEHOLD
SOURCE
t
≥ R
+ R
× C × n + 1 × ln 2
SAMPLE
SAMPLEHOLD
SAMPLE
SOURCE
DS40001882G-page 884
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
for a 12 bits accuracy: t
≥ R
+ R
× C × 9.02
SAMPLE
SAMPLEHOLD
SAMPLE
SOURCE
37.11.5 Digital to Analog Converter (DAC) Characteristics
Table 37-32.ꢀOperating Conditions(1)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
V
VDDANA
AVREF
Analog supply voltage
-
-
-
-
-
-
-
1.62
-
3.63
External reference voltage
INT1V(3)
1.0
-
VDDANA-0.6
V
-
1
-
V
VDDANA
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
Maximum capacitance load
DC supply current(2)
0.05
-
VDDANA-0.05
V
5
-
-
-
-
kΩ
pF
μA
100
230
IDD
Voltage pump disabled
-
160
Notes:ꢀ
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 37-33.ꢀClock and Timing(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
350
1000
2.85
10
Units
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Normal mode
-
-
-
-
-
-
-
-
ksps
For ΔDATA = +/-1
Startup time
VDDNA > 2.6V
VDDNA < 2.6V
μs
μs
Note:ꢀ
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 37-34.ꢀAccuracy Characteristics(1) (Device Variant A)
Symbol
RES
Parameter
Conditions
Min.
-
Typ.
-
Max.
10
Units
Bits
Input resolution
Integral non-linearity
-
INL
VREF = Ext 1.0V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
0.75
0.6
1.4
0.9
0.75
0.8
1.1
1.2
2.2
1.4
1.3
1.2
2.5
1.5
2.5
1.5
1.5
1.5
LSB
VREF = VDDANA
VREF = INT1V
DS40001882G-page 885
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Parameter
Conditions
VREF = Ext 1.0V
Min.
Typ.
Max.
Units
DNL
Differential non-linearity
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
+/-0.9 +/-1.2 +/-1.5
+/-0.9 +/-1.1 +/-1.2
+/-1.1 +/-1.5 +/-1.7
+/-1.0 +/-1.1 +/-1.2
+/-1.1 +/-1.4 +/-1.5
+/-1.0 +/-1.5 +/-1.6
LSB
VREF = VDDANA
VREF = INT1V
GE
OE
Gain error
Ext. VREF
Ext. VREF
+/-1.5
+/-2
+/-5
+/-3
+/-10
+/-6
mV
mV
Offset error
Table 37-35.ꢀAccuracy Characteristics(1) (Device Variant B,C, D and L)
Symbol
RES
Parameter
Conditions
Min.
Typ.
Max.
Units
Bits
Input resolution
Integral non-linearity
-
-
-
10
INL
VREF = Ext 1.0V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
0.7
0.6
0.6
0.5
0.5
0.7
+/-0.3
0.75
0.65
0.85
0.8
2
LSB
1.5
2
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
1.5
1.5
1.5
+/-1.0
+/-0.75
0.75
0.8
DNL
Differential non-linearity
+/-0.4
LSB
+/-0.25 +/-0.4
+/-0.4
+/-0.2
+/-0.5
+/-0.4
+/-0.5
+/-2
+/-0.55 +/-1.5
+/-0.3
+/-0.7
+/-0.7
+/-5
+/-0.75
+/-1.5
+/-1.5
+/-10
+/-8
GE
OE
Gain error
Ext. VREF
Ext. VREF
mV
mV
Offset error
+/-1.5
Note:ꢀ
1. All values measured using a conversion rate of 35 ksps.
37.11.6 Analog Comparator Characteristics
Table 37-36.ꢀElectrical and Timing (Device Variant A)
Symbol Parameter
Positive input voltage range
Conditions
Min.
Typ.
-
Max. Units
-
0
VDDANA
VDDANA
+15
V
Negative input voltage range
Offset
-
0
-
Hysteresis = 0, Fast mode
-15
-25
0.0
0.0
mV
mV
Hysteresis = 0, Low-power mode
+25
DS40001882G-page 886
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min.
20
15
-
Typ.
50
Max. Units
Hysteresis
Hysteresis = 1, Fast mode
Hysteresis = 1, Low-power mode
80
75
mV
mV
ns
40
Propagation delay
Changes for VACM = VDDANA/2
100 mV overdrive, Fast mode
60
116
Changes for VACM = VDDANA/2
100 mV overdrive, Low-power mode
-
-
-
225
1
370
2
ns
μs
μs
tSTARTUP Startup time
Enable to ready delay
Fast mode
Enable to ready delay
Low power mode
12
19
VSCALE
INL(3)
-
-
-
-
-1.4
-0.9
0.75
0.25
+1.4
+0.9
LSB
LSB
DNL(3)
Offset Error (1)(2)
Gain Error (1)(2)
-0.200 0.260 +0.920 LSB
-0.89 0.215 0.89 LSB
Table 37-37.ꢀElectrical and Timing (Device Variant B,C, D and L)
Symbol Parameter
Positive input voltage range
Conditions
Min.
0
Typ.
-
Max. Units
-
VDDANA
VDDANA
+15
V
Negative input voltage range
Offset
-
0
-
Hysteresis = 0, Fast mode
Hysteresis = 0, Low-power mode
Hysteresis = 1, Fast mode
Hysteresis = 1, Low-power mode
-15
-25
20
15
-
0.0
0.0
50
40
90
mV
mV
mV
mV
ns
+25
Hysteresis
85
75
Propagation delay
Changes for VACM = VDDANA/2
100 mV overdrive, Fast mode
180
Changes for VACM = VDDANA/2
100 mV overdrive, Low-power mode
-
-
-
282
1
520
2.6
22
ns
μs
μs
tSTARTUP Startup time
Enable to ready delay
,Fast mode
Enable to ready delay
, Low-power mode
14
VSCALE
INL(3)
-
-
-
-
-1.4
-0.9
0.75
0.25
+1.4
+0.9
LSB
LSB
DNL(3)
Offset Error (1)(2)
Gain Error (1)(2)
-0.200 0.260 +0.920 LSB
-0.89 0.215 0.89 LSB
Notes:ꢀ
1. According to the standard equation V(X) = VLSB*(X+1); VLSB = VDDANA/64.
2. Data computed with the Best Fit method.
3. Data computed using histogram.
DS40001882G-page 887
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.11.7 Bandgap and Internal 1.0V Reference Characteristics
Table 37-38.ꢀBandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
Conditions
Min. Typ. Max. Units
BANDGAP Internal 1.1V Bandgap
reference
After calibration at T = 25°C,
over [-40℃, +85℃],VDD = 3.3V
1.08 1.1 1.12
V
Over voltage at 25°C
1.09 1.1 1.11
V
V
INT1V
Internal 1.0V reference voltage After calibration at T = 25°C,
0.98
0.99
1
1
1.02
1.01
(1)
over voltage and [-40°C, +85°C],VDD = 3.3V
Over voltage at 25°C
V
Note:ꢀ
1. These values are simulation based and are not covered by production test limits.
37.11.8 Temperature Sensor Characteristics
37.11.8.1 Temperature Sensor Characteristics
Table 37-39.ꢀTemperature Sensor Characteristics(1) (Device Variant A)
Symbol Parameter
Temperature sensor
Conditions
Min. Typ. Max. Units
T= 25°C, VDDANA = 3.3V
-
0.667 -
V
output voltage
Temperature sensor
slope
2.3 2.4
2.5
3.7
10
mV/°C
mV/V
°C
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-1.7
-10
1
-
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
Table 37-40.ꢀTemperature Sensor Characteristics(1) (Device Variant B,C, D and L)
Symbol Parameter
Temperature sensor
Conditions
Min. Typ. Max. Units
0.688 -
T= 25°C, VDDANA = 3.3V
-
V
output voltage
Temperature sensor
slope
2.06 2.16 2.26 mV/°C
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-0.4 1.4
3
mV/V
°C
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-10
-
10
Note:ꢀ 1. These values are based on characterization. These values are not covered by test limits in production.
Temperature sensor values are not guaranteed for Automotive parts.
37.11.8.2 Software-based Refinement of the Actual Temperature
The temperature sensor behavior is linear but depends on several parameters such as the internal voltage reference,
which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with
data measured and written during the production tests. These calibration values should be read by software to infer
the most accurate temperature readings possible.
DS40001882G-page 888
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
This Software Temperature Log row can be read at address 0x00806030
This section specifies the Temperature Log row content and explains how to refine the temperature sensor output
using the values in the Temperature Log row.
37.11.8.2.1 Temperature Log Row
All values in this row were measured in the following conditions:
•
•
•
•
•
VDDIN = VDDIO = VDDANA = 3.3V
ADC Clock speed = 1MHz
ADC mode: Free running mode, ADC averaging mode with 4 averaged samples
ADC voltage reference = 1.0V internal buffered reference (INT1V)
ADC input = Temperature sensor
Table 37-41.ꢀTemperature Log Row Content
Bit position Name
Description
ROOM_TEMP_VAL_INT Integer part of room temperature in °C
ROOM_TEMP_VAL_DEC Decimal part of room temperature
7:0
11:8
19:12
23:20
31:24
HOT_TEMP_VAL_INT
HOT_TEMP_VAL_DEC
ROOM_INT1V_VAL
Integer part of hot temperature in °C
Decimal part of hot temperature
2’s complement of the internal 1V reference drift at room temperature
(versus a 1.0 centered value)
39:32
HOT_INT1V_VAL
2’s complement of the internal 1V reference drift at hot temperature
(versus a 1.0 centered value)
51:40
63:52
ROOM_ADC_VAL
HOT_ADC_VAL
12-bit ADC conversion at room temperature
12-bit ADC conversion at hot temperature
The temperature sensor values are logged during test production flow for Room and Hot insertions:
•
ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room insertion
(e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured temperature at room
insertion is 25.2°C).
•
HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion (e.g.
for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room insertion is
83.3°C).
The temperature log row also contains the corresponding 12-bit ADC conversions of both Room and Hot
temperatures:
•
ROOM_ADC_VAL contains the 12-bit ADC value corresponding to (ROOM_TEMP_VAL_INT,
ROOM_TEMP_VAL_DEC)
•
HOT_ADC_VAL contains the 12-bit ADC value corresponding to (HOT_TEMP_VAL_INT,
HOT_TEMP_VAL_DEC)
The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures:
•
•
•
ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC)
HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC)
ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other words,
the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127] corresponds to
[1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges.
37.11.8.2.2 Using Linear Interpolation
For concise equations, we will use the following notations:
•
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR
DS40001882G-page 889
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
•
•
•
•
•
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH
ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR
HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH
ROOM_INT1V_VAL is denoted INT1VR
HOT_INT1V_VAL is denoted INT1VH
Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation:
+ − V + − V
V
V
ADCH
temp + − temp
H R
ADC
ADCR
ADCR
=
temp+ − temp
R
Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as:
INT1V
1
R
ADC
⋅
+ − ADC
⋅
⋅ temp + − temp
m
R
H
R
12
12
2
+ − 1
2
+ − 1
temp = temp
+
C
R
INT1V
INT1V
H
R
ADC
⋅
+ − ADC ⋅
R
H
12
12
2
+ − 1
2
+ − 1
[Equation 1]
Notes:ꢀ
1. In the previous expression, we have added the conversion of the ADC register value to be expressed in V.
2. This is a coarse value because we assume INT1V=1V for this ADC conversion.
Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation:
INT1V + − INT1V
INT1V + − INT1V
H R
R
=
temp+ − temp
temp + − temp
R
H R
Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as:
INT1V + − INT1V ⋅ temp + − temp
H
R
C
R
INT1V = INT1V +
m
R
temp + − temp
H
R
Back to [Equation 1], if we replace INT1V=1V by INT1V = INT1Vm, we can deduce a finer temperature value as:
INT1V
INT1V
m
R
ADC
⋅
+ − ADC
⋅
⋅ temp ⋅ temp
H R
m
R
12
12
2
+ − 1
2
+ − 1
temp = temp
+
R
f
INT1V
INT1V
H
R
ADC
⋅
+ − ADC ⋅
R
H
12
12
2
+ − 1
2
+ − 1
[Equation 1bis]
37.12 NVM Characteristics
Table 37-42.ꢀMaximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
1
2
3
0
1
14
28
42
48
24
48
MHz
2.7V to 3.63V
DS40001882G-page 890
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 37-43.ꢀFlash Endurance and Data Retention
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
Years
Years
Years
Cycles
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 85°C
10
50
-
-
-
-
20
100
>100
150k
25
25k
1. An endurance cycle is a write and an erase operation.
Table 37-44.ꢀEEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
50
Max. Units
RetEEPROM100k
RetEEPROM10k
CycEEPROM
Retention after up to 100k
Retention after up to 10k
Cycling Endurance(2)
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 85°C
10
20
-
-
-
Years
Years
Cycles
100
100k 600k
1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
Table 37-45.ꢀNVM Characteristics (Device Variant A)
Symbol
tFPP
Parameter
Conditions
Min.
Typ.
Max.
2.5
6
Units
ms
Page programming time
Row erase time
-
-
-
-
-
-
-
-
-
tFRE
ms
tFCE
DSU chip erase time (CHIP_ERASE)
240
ms
Table 37-46.ꢀNVM Characteristics (Device Variant B,C, D and L)
Symbol
tFPP
Parameter
Conditions
Min.
Typ.
Max.
2.5
6
Units
ms
Page programming time
Row erase time
-
-
-
-
-
-
-
tFRE
1.2
-
ms
tFCE
DSU chip erase time (CHIP_ERASE)
240
ms
37.13 Oscillators Characteristics
37.13.1 Crystal Oscillator (XOSC) Characteristics
37.13.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 37-47.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
MHz
fCPXIN
XIN clock frequency
-
-
32
DS40001882G-page 891
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.13.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT . The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T= 113 μm)
Table 37-48.ꢀCrystal Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Crystal oscillator frequency
0.4
-
-
-
32
MHz
Ω
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
f = 0.455ꢀMHz, CL = 100pF
XOSC.GAIN = 0
5.6K
The AGC doesn’t have any noticeable
impact on these measurements.
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
-
-
-
-
-
-
-
-
416
243
138
66
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
f = 8ꢀMHz, CL = 20pF
XOSC.GAIN = 2
f = 16ꢀMHz, CL = 20pF
XOSC.GAIN = 3
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
56
CXIN
Parasitic capacitor load
Parasitic capacitor load
Current Consumption
-
-
5.9
3.2
65
-
pF
pF
μA
CXOUT
-
f = 2MHz, CL = 20pF, AGC off 27
f = 2MHz, CL = 20pF, AGC on 14
f = 4MHz, CL = 20pF, AGC off 61
f = 4MHz, CL = 20pF, AGC on 23
85
52
73
117
74
150
100
296
172
687
552
f = 8MHz, CL = 20pF, AGC off 131 226
f = 8MHz, CL = 20pF, AGC on 56 128
f = 16MHz, CL = 20pF, AGC off 305 502
f = 16MHz, CL = 20pF, AGC on 116 307
f = 32MHz, CL = 18pF, AGC off 1031 1622 2200
f = 32MHz, CL = 18pF, AGC on 278 615 1200
DS40001882G-page 892
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
tSTARTUP Start-up time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
-
-
-
-
14K
48K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
6.8K 19.5K
5.55K 13K
6.75K 14.5K
5.3K 9.6K
f = 8ꢀMHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
f = 16ꢀMHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
Figure 37-6.ꢀOscillator Connection
Xin
CLEXT
Crystal
LM
CSHUNT
RM
CSTRAY
CM
Xout
CLEXT
37.13.2 External 32ꢁkHz Crystal Oscillator (XOSC32K) Characteristics
37.13.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 37-49.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
32.768
50
Max.
Units
fCPXIN32
XIN32 clock frequency
XIN32 clock duty cycle
-
-
-
-
kHz
%
37.13.2.1.1 Crystal Oscillator Characteristics
Figure 37-6 and the equation in also applies to the 32ꢀkHz oscillator connection. The user must choose a crystal
oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
found in the crystal data sheet.
Table 37-50.ꢀ32kHz Crystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Crystal oscillator frequency
-
32768 -
Hz
DS40001882G-page 893
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max. Units
tSTARTUP Startup time
ESRXTAL = 39.9ꢀkΩ, CL =
12.5ꢀpF
-
28K
30K cycles
CL
Crystal load capacitance
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
0.1
3.1
3.3
1.22
-
-
CXIN32
Parasitic capacitor load
-
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
2.19 µA
141 kΩ
ESR
Crystal equivalent series resistance
CL=12.5pF
f=32.768kHz
, Safety Factor = 3
Table 37-51.ꢀ32kHz Crystal Oscillator Characteristics (Device Variant B,C, D, and L)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Crystal oscillator frequency
-
32768 -
Hz
tSTARTUP Startup time
ESRXTAL = 39.9ꢀkΩ, CL =
12.5ꢀpF
-
28K
30K cycles
CL
Crystal load capacitance
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
0.1
3.2
3.7
1.22
-
-
CXIN32
Parasitic capacitor load
-
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
2.19 µA
100 kΩ
ESR
Crystal equivalent series resistance
CL=12.5pF
f=32.768kHz
, Safety Factor = 3
37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 37-52.ꢀDFLL48M Characteristics - Open Loop Mode(1)
Symbol Parameter
Conditions
Min. Typ. Max. Units
48 49 MHz
fOUT
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
403 453 μA
tSTARTUP Start-up time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-
8
9
μs
fOUT within 90ꢀ% of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
DS40001882G-page 894
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-53.ꢀDFLL48M Characteristics - Closed Loop Mode(1) (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Average Output
frequency
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
47.963 47.972 47.981 MHz
fREF
Reference frequency
Cycle to Cycle jitter
0.732 32.768 33
kHz
ns
Jitter
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
-
-
0.42
482
500
IDFLL
Power consumption fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
on VDDIN
-
425
200
μA
μs
1464
tLOCK
Lock time
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
100
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Table 37-54.ꢀDFLL48M Characteristics - Closed Loop Mode(1) (Device Variant B, C, D, and L)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Average Output
fREF = 32 .768kHz
47.963 47.972 47.981 MHz
frequency
fREF
Reference frequency
Cycle to Cycle jitter
0.732 32.768 33
kHz
ns
Jitter
IDFLL
fREF = 32 .768kHz
-
-
-
0.42
453
Power consumption on fREF =32 .768kHz
VDDIN
403
μA
tLOCK
Lock time
fREF = 32 .768kHz
-
200
500
μs
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
1. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in
close loop must be within a 2% error accuracy.
DS40001882G-page 895
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.13.4 32.768kHz Internal oscillator (OSC32K) Characteristics
Table 37-55.ꢀ32kHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency
Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]C, over [1.62, 3.63]V
28.508 32.768 34.734 kHz
32.276 32.768 33.260
31.457 32.768 34.079
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
IOSC32K Current consumption
tSTARTUP Start-up time
-
-
-
0.67
1
1.31
μA
2
-
cycle
%
Duty
Duty Cycle
50
37.13.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 37-56.ꢀUltra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]C, over [1.62, 3.63]V
25.559 32.768 38.011 kHz
31.293 32.768 34.570
31.293 32.768 34.570
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
(1)(2)
iOSCULP32K
tSTARTUP
Duty
-
-
-
-
125
nA
Start-up time
Duty Cycle
10
50
-
-
cycles
%
Notes: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
37.13.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 37-57.ꢀInternal 8MHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
Calibrated against a 8MHz reference at 25°C, 7.8
over [-40, +85]C, over [1.62, 3.63]V
8
8.16 MHz
Calibrated against a 8MHz reference at 25°C, 7.94 8
at VDD=3.3V
8.06
Calibrated against a 8MHz reference at 25°C, 7.92 8
over [1.62, 3.63]V
8.08
TempCo Frequency vs. Temperature
drift
-1.2
1
2
%
%
SupplyCo Frequency vs. Supply drift
-2
DS40001882G-page 896
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
IOSC8M
Current consumption
IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
64
96
μA
tSTARTUP Startup time
-
-
2.4 3.3
50
μs
%
Duty
Duty cycle
-
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 37-58.ꢀFDPLL96M Characteristics(1) (Device Variant A)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
1.5
3.0
1.3
3.0
1.3
700
1200
2.0
10.0
2.0
7.0
2
-
Jp
Period jitter
-
%
-
-
-
tLOCK
Lock Time
Duty cycle
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
50
60
μs
%
Duty
40
Table 37-59.ꢀFDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
1.5
4.0
1.6
4.6
1.2
700
1200
2.1
10.0
2.2
10.2
2
-
Jp
Period jitter
-
%
-
-
-
tLOCK
Lock Time
Duty cycle
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
50
60
μs
%
Duty
40
DS40001882G-page 897
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-60.ꢀFDPLL96M Characteristics(1) (Silicon Revision F and G)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
-
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
2.2
3.7
2.2
4.4
1.0
-
-
Jp
Period jitter
-
3.0
9.0
3.0
9.7
2
%
-
-
-
tLOCK
Lock Time
Duty cycle
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
22
50
50
60
μs
%
Duty
40
Note:ꢀ All values have been characterized with FILTSEL[1/0] as the default value.
37.14 PTC Typical Characteristics
37.14.1 Device Variant A
Figure 37-7.ꢀPower Consumption [μA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
140
120
100
80
Scan rate 10ms
Scan rate 50ms
60
Scan rate 100ms
Scan rate 200ms
40
20
0
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 898
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-8.ꢀPower Consumption [μA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
200
180
160
140
120
100
80
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
60
40
20
0
1
2
4
8
16
32
64
Sample averaging
Figure 37-9.ꢀPower Consumption [μA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
1200
1000
800
600
400
200
0
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
Linear (Scan rate 50ms)
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 899
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-10.ꢀPower Consumption [μA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
900
800
700
600
500
400
300
200
100
0
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
1
2
4
8
16
32
64
Sample averaging
Figure 37-11.ꢀPower Consumption [μA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
0
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 900
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-12.ꢀPower Consumption [μA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
1800
1600
1400
1200
1000
800
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
600
400
200
0
1
2
4
8
16
32
64
Sample averaging
Figure 37-13.ꢀCPU Utilization
80 %
70 %
60 %
50 %
40 %
30 %
20 %
10 %
Channel count 1
Channel count 10
Channel count 100
0 %
10
50
100
200
37.14.2 Device Variant B,C and D
VCC = 3.3C and fCPU = 48 MHz for the following PTC measurements.
DS40001882G-page 901
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-14.ꢀ1 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
Figure 37-15.ꢀ1 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 902
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-16.ꢀ10 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
Figure 37-17.ꢀ10 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 903
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-18.ꢀ100 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
Figure 37-19.ꢀ100 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 904
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-61.ꢀSensor Load Capacitance
Symbol
Mode
PTC channel
Max Sensor Load (1)
Units
Y0
Y1
16
23
19
Y2
Y3
Y4
Y5
Y6
23
Y7
Self-capacitance
Cload
Y8
pF
Y9
Y10
Y11
Y12
Y13
Y14
Y15
All
19
23
30
Mutual-capacitance
Note:ꢀ
1. Capacitance load that the PTC circuitry can compensate for each channel.
Table 37-62.ꢀAnalog Gain Settings
Symbol
Setting
GAIN_1
GAIN_2
GAIN_4
GAIN_8
GAIN_16
GAIN_32
Average
1.0
2.0
3.8
Gain
8.0
12.4
-
Notes:ꢀ
1. Analog Gain is a parameter of the QTouch Library. Refer to the QTouch Library Peripheral Touch Controller
User Guide.
2. GAIN_16 and GAIN_32 settings are not recommended, otherwise the PTC measurements might get unstable.
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating conditions
VDD = 3.3 V
Clocks
DS40001882G-page 905
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC configuration
Mutual-capacitance mode
One touch channel
System configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 37-63.ꢀ
Drift
Calibration
PTC scan
rate (msec)
Symbol
Parameters
Oversamples
Ta
Typ. Max Units
4
16
4
9
107
10
50
17 117
5
6
4
5
4
4
102
104
102
103
102
102
16
4
Disabled
100
200
10
16
4
16
4
Current
Consumption
Max 85°C Typ
25°C
IDD
µA
15 114
23 124
16
4
7
8
5
6
6
6
105
108
103
105
103
104
50
16
4
Enabled
100
200
16
4
16
37.15 USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to
these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
DS40001882G-page 906
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 37-64.ꢀGCLK_USB Clock Setup Recommendations
Clock setup
USB Device
No
USB Host
No
DFLL48M
Open loop
Closed loop, any internal OSC source
Closed loop, any external XOSC source
Closed loop, USB SOF source (USB recovery mode)(1)
Any internal OSC source (32K, 8M, ... )
Any external XOSC source (< 1MHz)
Any external XOSC source (> 1MHz)
No
No
Yes
No
Yes(2)
No
N/A
No
FDPLL96M
Yes
No
Yes(3)
Yes
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can
be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN
in USB specification).
37.16 Timing Characteristics
37.16.1 External Reset
Table 37-65.ꢀExternal Reset Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
10
-
-
ns
Table 37-66.ꢀExternal Reset Characteristics (Silicon Revision G)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
1000
-
-
ns
DS40001882G-page 907
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.16.2 SERCOM in SPI Mode Timing
Figure 37-20.ꢀSPI Timing Requirements in Host Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
tSCK
MISO
(Data Input)
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 37-21.ꢀSPI Timing Requirements in Client Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
tSSCK
MOSI
(Data Input)
MSB
LSB
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
DS40001882G-page 908
Complete Datasheet
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-67.ꢀSPI Timing Characteristics and Requirements(1)
Symbol Parameter
Conditions
Host
Min.
Typ.
Max.
Units
tSCK
SCK period
84
ns
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time(2)
Host
-
0.5*tSCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Host
-
-
SCK fall time(2)
Host
-
-
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Client SCK Period
SCK high/low width
SCK rise time(2)
Host
-
21
tMIH
Host
-
13
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
Host
-
tSCK/2 - 3
Host
-
3
-
-
-
-
-
-
-
Client
Client
Client
Client
Client
Client
Client
1*tCLK_APB
0.5*tSSCK
-
SCK fall time(2)
-
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
tSSCK/2 - 9
tSSCK/2 - 3
tSIH
tSSS
PRELOADEN=1 2*tCLK_APB
+ tSOS
PRELOADEN=0 tSOS+7
-
-
-
-
-
tSSH
tSOS
SS hold after SCK
MISO setup SCK
Client
Client
tSIH - 4
-
tSSCK/2 -
18
tSOH
MISO hold after SCK
Client
Client
-
-
18
18
-
-
tSOSS
MISO setup after SS
low
tSOSH
MISO hold after SS
high
Client
-
10
-
Notes:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production.
2. See 37.9 I/O Pin Characteristics.
37.16.3 SERCOM in I2C Mode Timing
This section describes the requirements for devices connected to the I2C Interface Bus.
DS40001882G-page 909
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-22.ꢀI2C Interface Bus Timing
t
HIGH
t
t
R
OF
t
t
LOW
LOW
SCL
t
t
t
HD;DAT
SU;STA
HD;STA
t
SU;DAT
t
SU;STO
SDA
t
BUF
Table 37-68.ꢀI2C Interface Timing (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ. Max. Units
tR
Rise time for both SDA and SCL
Standard / Fast ICb(2) = 400pF
Mode
-
215 300 ns
Fast
Mode +
ICb(2) = 550pF
60
20
100
40
High Speed
Mode
ICb(2) = 100pF
tOF
Output fall time from VIHmin to
VILmax
Standard / Fast 10pF < Cb(2) < 400pF
Mode
20.0 50.0
15.0 50.0
Fast
10pF < Cb(2) < 550pF
Mode +
High Speed
Mode
10pF < Cb(2)< 100pF
10.0 40.0
tHD;STA Hold time (repeated) START
condition
fSCL > 100 kHz, Host tLOW-9
-
-
tLOW
tBUF
Low period of SCL Clock
fSCL > 100 kHz
fSCL > 100 kHz
113
-
-
-
-
Bus free time between a STOP
and a START condition
tLOW
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host tLOW+7 -
-
tHD;DAT Data hold time
fSCL > 100 kHz, Host
9
-
-
12
-
tSU;DAT Data setup time
fSCL > 100 kHz, Host 104
tSU;STO Setup time for STOP condition
tSU;DAT;rx Data setup time (receive mode)
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Host tLOW+9 -
-
fSCL > 100 kHz, Client 51
fSCL > 100 kHz, Client 71
-
56
138
90
DS40001882G-page 910
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-69.ꢀI2C Interface Timing (Device Variant B,C and D)
Symbol Parameter
Conditions
Min.
Typ. Max. Units
tR
Rise time for both SDA and SCL
Standard / Fast Cb(2) = 400pF
Mode
-
230 350 ns
Fast
Cb(2) = 550pF
60
100
Mode +
High Speed
Mode
Cb(2) = 100pF
30
25
20
60
50
30
tOF
Output fall time from VIHmin to
VILmax
Standard / Fast 10pF < Cb(2) < 400pF
Mode
Fast
10pF < Cb(2) < 550pF
Mode +
High Speed
Mode
10pF < Cb(2) < 100pF
10
-
20
-
tHD;STA Hold time (repeated) START
condition
fSCL > 100 kHz, Host tLOW-9
tLOW
tBUF
Low period of SCL Clock
fSCL > 100 kHz
fSCL > 100 kHz
113
-
-
-
-
Bus free time between a STOP
and a START condition
tLOW
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host tLOW+7 -
-
tHD;DAT Data hold time
fSCL > 100 kHz, Host
9
-
-
12
-
tSU;DAT Data setup time
fSCL > 100 kHz, Host 104
tSU;STO Setup time for STOP condition
tSU;DAT;rx Data setup time (receive mode)
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Host tLOW+9 -
-
fSCL > 100 kHz, Client 51
fSCL > 100 kHz, Client 71
-
56
138
90
Notes:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
DS40001882G-page 911
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.16.4 SWD Timing
Figure 37-23.ꢀSWD Interface Signals
Read Cycle
Fromdebugger to
SWDIOpin
Stop
Park
Tri State
Data
Data
Parity
Start
Thigh
Tos
Tlow
Fromdebugger to
SWDCLK pin
SWDIOpin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
Fromdebugger to
SWDIOpin
Stop
Park
Tri State
Start
Tis
Tih
Fromdebugger to
SWDCLK pin
SWDIOpin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 37-70.ꢀSWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Units
Thigh
Tlow
Tos
SWDCLK High period
SWDCLK Low period
VVDDIO from 3.0ꢀV to 3.6ꢀV, maximum external
capacitor = 40ꢀpF
10
10
-5
500000 ns
500000
5
SWDIO output skew to falling
edge SWDCLK
Tis
Tih
Input Setup time required
between SWDIO
4
1
-
-
Input Hold time required
between SWDIO and rising
edge SWDCLK
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
37.16.5 I2S Timing
Figure 37-24.ꢀI2S Timing Host Mode
MCK output
SCK output
tM_SCKOR
tM_SCKOF
tM_FSOH
tM_SCKO
tM_SDOH
tM_SDIS
tM_SDIH
tM_FSOV
tM_SDOV
FS output
SD output
SD input
LSB right ch.
MSB left ch.
DS40001882G-page 912
Complete Datasheet
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-25.ꢀI2S Timing Client Mode
tS_FSIH
SCK input
tS_SCKI
tS_FSIS
tS_SDOH
tS_SDIS
tS_SDIH
FS input
tS_SDOV
SD output
SD input
LSB rignt ch.
MSB left ch.
Figure 37-26.ꢀI2S Timing PDM2 Mode
tPDM2RH
tPDM2RS
tPDM2LS
tPDM2LH
SCK input
SD input
Left
Right
Right
Left
Left
Right
Table 37-71.ꢀI2S Timing Characteristics and Requirements (Device Variant A)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9.2
4.7
5.3
50
ns
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.5
dM_MCKO
dM_MCKI
tM_SCKOR
I2S MCK duty cycle
I2S MCK duty cycle
I2S SCK rise time(3)
Host mode
45.4
50 45.4
%
%
ns
Host mode, pin is input (1b)
50
50
Host mode / Capacitive load
CL = 15 pF
9
4.6
4.5
50
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
ns
%
dM_SCKO
fM_SCKO,1/
I2S SCK duty cycle
I2S SCK frequency
Host mode
45.6
50 45.6
8
Host mode,Supposing external
device response delay is 30ns
9.5 MHz
tM_SCKO
fS_SCKI,1/
tS_SCKI
I2S SCK frequency
Client mode,Supposing
external device response
delay is 30ns
14.4
14.8 MHz
dS_SCKO
tM_FSOV
tM_FSOH
tS_FSIS
I2S SCK duty cycle
FS valid time
FS hold time
Client mode
Host mode
Host mode
Client mode
Client mode
50
50
%
4.1
-0.9
1.5
0
4
ns
ns
ns
ns
-0.9
2.3
0
FS setup time
FS hold time
tS_FSIH
DS40001882G-page 913
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_SDIS
tM_SDIH
tS_SDIS
Data input setup time Host mode
Data input hold time Host mode
Data input setup time Client mode
Data input hold time Client mode
34.7
-8.2
4.6
24.5
-8.2
3.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS_SDIH
tM_SDOV
tM_SDOH
tS_SDOV
tS_SDOH
tPDM2LS
tPDM2LH
tPDM2RS
tPDM2RH
1.2
1.2
Data output valid time Host transmitter
Data output hold time Host transmitter
Data output valid time Client transmitter
Data output hold time Client transmitter
Data input setup time Host mode PDM2 Left
5.6
4.8
-0.5
-0.5
36.2
25.9
36
25.7
24.5
-8.2
20.9
-6.7
34.7
-8.2
30.5
-6.7
Data input hold time
Data input setup time Host mode PDM2 Right
Data input hold time Host mode PDM2 Right
Host mode PDM2 Left
Table 37-72.ꢀI2S Timing Characteristics and Requirements (Device Variant B, C and D)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9.2
4.7
5.4
50
ns
ns
tM_MCKOF
I2S MCK fall time(3) Host mode / Capacitive load
CL = 15 pF
11.6
dM_MCKO
dM_MCKI
tM_SCKOR
I2S MCK duty cycle
I2S MCK duty cycle
Host mode
47.1
50 47.3
%
%
ns
Host mode, pin is input (1b)
50
50
I2S SCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9
4.6
4.6
50
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
ns
dM_SCKO
fM_SCKO, 1/
I2S SCK duty cycle
I2S SCK frequency
Host mode
47
50 47.2
7.8
%
Host mode, Supposing
external device response
delay is 30ns
9.2 MHz
tM_SCKO
fS_SCKI, 1/tS_SCKI I2S SCK frequency
Client mode, Supposing
external device response
delay is 30ns
12.8
13
MHz
dS_SCKO
tM_FSOV
tM_FSOH
tS_FSIS
I2S SCK duty cycle
FS valid time
Client mode
Host mode
Host mode
Client mode
50
50
%
ns
ns
ns
2.4
-0.1
5.3
1.9
FS hold time
-0.1
6
FS setup time
DS40001882G-page 914
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tS_FSIH
FS hold time
Client mode
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tM_SDIS
tM_SDIH
tS_SDIS
tS_SDIH
tM_SDOV
tM_SDOH
tS_SDOV
tS_SDOH
tPDM2LS
tPDM2LH
tPDM2RS
tPDM2RH
Data input setup time Host mode
Data input hold time Host mode
Data input setup time Client mode
Data input hold time Client mode
36
25.9
-8.2
8.3
-8.2
9.1
3.8
3.7
Data output valid time Host transmitter
Data output hold time Host transmitter
Data output valid time Client transmitter
Data output hold time Client transmitter
Data input setup time Host mode PDM2 Left
2.5
1.9
-0.1
-0.1
29.8
19.7
29.1
35.5
-8.2
30.6
-7
18.9
25.3
-8.2
21.1
-7
Data input hold time
Data input setup time Host mode PDM2 Right
Data input hold time Host mode PDM2 Right
Host mode PDM2 Left
Notes:ꢀ
1. All timing characteristics given for 15pF capacitive load.
2. These values are based on simulations and not covered by test limits in production.
3. See 37.9 I/O Pin Characteristics
DS40001882G-page 915
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.
Electrical Characteristics at 105°C
38.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
38.2
Absolute Maximum Ratings
Stresses beyond those listed in table below may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 38-1.ꢀAbsolute Maximum Ratings
Symbol
VDD
Parameter
Condition
Min.
Max.
3.8
Units
V
Power supply voltage
Current into a VDD pin
Current out of a GND pin
Pin voltage with respect to GND and VDD
Storage temperature
0
IDD
-
92(1)
mA
mA
V
IGND
-
130(1)
VDD+0.3V
150
VPIN
GND-0.3V
-60
Tstorgae
°C
1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of
GPIOs. Also note that each VDD/GND pair is connected to two clusters so current consumption through the
pair will be a sum of the clusters source/sink currents.
Related Links
7.2.4 GPIO Clusters
38.3
General Operating Ratings
The device must operate within the ratings listed in the table below in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 38-2.ꢀGeneral Operating Conditions
Symbol
VDD
Parameter
Condition
Min.
1.62(1)
1.62(1)
-40
Typ.
3.3
3.3
25
Max.
3.63
3.63
105
Units
V
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
VDDANA
TA
V
°C
°C
TJ
-
-
125
1. With BOD33 disabled. If the BOD33 is enabled, refer to the BOD33 characteristics.
Related Links
38.6.2.1 BOD33 Characteristics
DS40001882G-page 916
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.4
Maximum Clock Frequencies
Table 38-3.ꢀMaximum GCLK Generator Output Frequencies
Symbol
Description
Conditions
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
Undivided
96
MHz
fGCLKGEN2
fGCLKGEN3
Divided
48
MHz
fGCLKGEN4
fGCLKGEN5
Table 38-4.ꢀMaximum Peripheral Clock Frequencies
Symbol
Description
Max. Units
fCPU
CPU clock frequency
48
48
48
48
48
33
2
MHz
MHz
MHz
MHz
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fAHB
AHB clock frequency
fAPBA
APBA clock frequency
fAPBB
APBB clock frequency
fAPBC
APBC clock frequency
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
fGCLK_DPLL_32K
fGCLK_WDT
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
fGCLK_RTC
RTC input clock frequency
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
DS40001882G-page 917
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
Description
Max. Units
fGCLK_SERCOMx_SLOW
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, fGCLK_TCC1
fGCLK_TCC2, fGCLK_TCC3, fGCLK_TC3
fGCLK_TC4, fGCLK_TC5
fGCLK_TC6, fGCLK_TC7
fGCLK_ADC
Common SERCOM slow input clock frequency
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2, TCC3, TC3 input clock frequency
TC4, TC5 input clock frequency
TC6, TC7 input clock frequency
ADC input clock frequency
48
48
48
48
48
48
48
96
96
48
48
48
48
64
48
64
48
48
13
13
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
fGCLK_AC_DIG
AC digital input clock frequency
AC analog input clock frequency
AC1 digital input clock frequency
AC1 analog input clock frequency
DAC input clock frequency
fGCLK_AC_ANA
fGCLK_AC1_DIG
fGCLK_AC1_ANA
fGCLK_DAC
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
I2S serial 0 input clock frequency
I2S serial 1 input clock frequency
fGCLK_I2S_1
38.5
Power Consumption
The values in the below table are measured values of power consumption under the following conditions, except
where noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
•
•
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC32K (32ꢀkHz crystal oscillator) stopped
– XOSC (crystal oscillator) running with external 32MHz clock on XIN
– DFLL48M stopped
•
•
Clocks
– XOSC used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
DS40001882G-page 918
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
•
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on flash with 1 wait states
Cache enabled
•
•
•
•
BOD33 disabled
Table 38-5.ꢀCurrent Consumption (Silicon Revisions A, B, C, D, E, and F)
Mode
Conditions
TA
Min. Typ.
Max.
2.75
2.82
Units
ACTIVE
CPU running a While(1) algorithm
105°C -
-
2.55
2.56
mA
CPU running a While(1) algorithm
VDDIN=1.8V,
CPU is running on Flash with 3 wait
states
CPU running a While(1) algorithm, CPU
is
-
42*freq +318 42*freq +432 μA
(with freq in
running on Flash with 3 wait states with
GCLKIN as reference
MHz)
CPU running a Fibonacci algorithm
-
-
4.21
4.23
4.59
4.57
mA
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash with
3
wait states
CPU running a Fibonacci algorithm, CPU
is
-
80*freq +320 82*freq +432 μA
(with freq in
running on Flash with 3 wait states with
GCLKIN as reference
MHz)
CPU running a CoreMark algorithm
-
-
6.02
5.21
6.54
5.57
mA
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash with
3
wait states
CPU running a CoreMark algorithm, CPU
is
-
96*freq +322 98*freq +432 μA
(with freq in
running on Flash with 3 wait states with
GCLKIN as reference
MHz)
IDLE0
-
1.55
1.13
0.96
214
1.62
1.18
1.01
627
mA
IDLE1
-
-
IDLE2
STANDBY
(rev. E silicon)
XOSC32K running
105°C -
μA
μA
/ RTC running at 1kHz(1)
XOSC32K and RTC stopped (1)
105°C -
105°C -
212
175
624
452
STANDBY
XOSC32K running
/ RTC running at 1kHz (1)
(rev. F silicon)
XOSC32K and RTC stopped (1)
105°C -
173
450
DS40001882G-page 919
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Note:ꢀ
1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
Table 38-6.ꢀCurrent Consumption (Silicon Revision G)
Mode
conditions
Ta
Vcc Typ.
Max.
3.6
Units
ACTIVE
CPU running a While 1 algorithm
105°C 3.3V 3.3
105°C 1.8V 3.3
mA
3.6
CPU running a While 1 algorithm, with GCLKIN as
reference
105°C 3.3V 56*Freq+254 55*Freq+596
CPU running a Fibonacci algorithm
105°C 3.3V 4.2
105°C 1.8V 4.3
4.6
4.7
CPU running a Fibonacci algorithm, with GCLKIN as 105°C 3.3V 75*Freq+254 73*Freq+594
reference
CPU running a CoreMark algorithm
105°C 3.3V 4.9
105°C 1.8V 4.7
5.4
5.1
CPU running a CoreMark algorithm, with GCLKIN
as reference
105°C 3.3V 87*Freq+257 86*Freq+597
IDLE0
IDLE1
IDLE2
105°C 3.3V 1.8
105°C 3.3V 1.2
105°C 3.3V 1.0
105°C 3.3V 175.0
2.1
1.5
1.2
STANDBY XOSC32K running, RTC running at 1kHz RTC
running at 1kHz (1)
452.0
µA
XOSC32K and RTC stopped (1)
105°C 3.3V 173.0
450.0
Note:ꢀ Measurements done with VREG.bit.RUNSTDBY = 1.
Table 38-7.ꢀWake-up Time
Mode
Conditions
TA
Min. Typ. Max. Units
4.1 μs
IDLE0
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
105°C 3.8
4
IDLE1
12.8 14.3 15.7
13.7 15.2 16.6
18.7 20.1 21.6
IDLE2
STANDBY
DS40001882G-page 920
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Figure 38-1.ꢀMeasurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
38.6
Analog Characteristics
38.6.1 Power-On Reset (POR) Characteristics
Table 38-8.ꢀPOR Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
VPOT+
VPOT-
Voltage threshold on VDD rising
Voltage threshold on VDD falling
IVDD falls at 1V/ms or slower
1.27 1.45 1.58
0.72 0.99 1.32
V
V
DS40001882G-page 921
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Figure 38-2.ꢀPOR Operating Principle
VPOT+
VPOT-
Time
38.6.2 Brown-Out Detectors Characteristics
38.6.2.1 BOD33 Characteristics
Table 38-9.ꢀBOD33 Characteristics
Symbol Parameter
Conditions
Temp.
Min. Typ. Max. Units
I
Step size, between
adjacent values in
BOD33.LEVEL
-
34
-
mV
VHYST
tDET
VBOD+ - VBOD-
Detection time
Hysteresis ON
35
-
-
170 mV
Time with
0.9(1)
-
μs
VDDANA < VTH
necessary to generate a
reset signal
IIdleBOD33 Current consumption om Active/Idle Continuous mode
mode
25°C
-
25
-
48
51
μA
-40- to 105°C -
25°C
Sampling mode
-
0.034 0.21
- 2.44
-40- to 105°C -
25°C
ISbyBOD33 Current consumption in Standby
mode
Sampling mode
0.132 0.38 μA
1.5
-40- to 105°C
-40- to 105°C -
tSTARTUP Startup time
2.2(1)
-
μs
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
DS40001882G-page 922
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.6.3 Analog-to-Digital Converter (ADC) Characteristics
Table 38-10.ꢀOperating Conditions
Symbol
VDDANA
RES
Parameter
Conditions
Min.
2.7
8
Typ.
Max.
3.6
12
Units
V
Power supply voltage
Resolution
T > 85°C
-
-
-
-
-
-
-
-
bits
kHz
ksps
ksps
ns
fCLK_ADC
ADC Clock frequency
Sample rate(1)
-
30
5
2100
300
350
-
Single shot
Free running
5
Sampling time(1)
-
-
250
3
Sampling time with DAC as
input(2)
-
µs
Sampling time with Temp
sens as input(2)
-
-
10
10
-
-
-
-
µs
µs
Sampling time with
Bandgap as input(2)
Conversion time(1)
1x Gain
-
6
-
-
-
cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
1.0
VDDANA-0.6
INT1V
Internal 1V reference (2,4)
-
-
-
-
1.0
-
-
V
V
INTVCC0
Internal ratiometric
reference 0(2)
VDDANA/1.48
INTVCC0
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 0(2) error
INTVCC1
Internal ratiometric
reference 1(2)
VDDANA>2.0V
-
VDDANA/2
-
V
INTVCC1
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 1(2) error
Conversion range(1)
Differential mode
-VREF
/
-
+VREF/GAIN
V
GAIN
Single-ended mode
0.0
-
3.5
-
+VREF/GAIN
V
CSAMPLE
RSAMPLE
Sampling capacitance(2)
-
-
-
-
-
pF
kΩ
Input channel source
resistance(2)
3.5
IDD
DC supply current(1)
fCLK_ADC = 2.1-MHz(3)
-
1.25
1.83
mA
1. These values are based on characterization. These values are not covered by test limits in production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, a conversion takes 6 clock cycles of the ADC clock
(conditions: 1X gain, 12-bit resolution, differential mode, free-running).
4. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
DS40001882G-page 923
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Table 38-11.ꢀDifferential Mode
Symbol Parameter
Conditions
With gain compensation
1x Gain
Min.
-
Typ.
10.5
2.7
Max.
10.8
13
Units
bits
LSB
LSB
LSB
mV
mV
mV
%
ENOB
TUE
INL
Effective Number Of Bits
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
1.5
1x Gain
0.9
1.3
4
DNL
GE
1x Gain
+/-0.3
-10.0
-20.0
-20.0
+/-0.5
-1.3
-10.0
+2
+/-0.95
+10.0
+10.0
+20.0
+/-0.2
+/-0.5
+8.0
+8.0
+6.0
76.0
67.0
68.6
-67.0
1.6
Ext. Ref 1x
VREF = VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
Gain Accuracy(5)
Offset Error
+/-0.02 +/-0.05
+/-0.01 +/-0.03
%
OE
-8.0
-8.0
-6.0
65.0
58.0
60.0
-75.0
0.6
-1.0
-0.60
-1.0
mV
mV
mV
dB
VREF = VDDANA/1.48
VREF = INT1V
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1 MHz
71.5
65.0
66.0
-71.0
1.0
dB
FIN = 40 kHz
dB
AIN = 95% FSR
THD
Total Harmonic Distortion
Noise RMS
dB
T = 25°C
mV
1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the
input voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where, VCM_IN is the Input channel
common mode voltage):
3.1.
3.2.
If |VIN| > VREF/4
•
•
VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 -0.05*VDDANA -0.1V
If |VIN| < VREF/4
•
•
VCM_IN < 1.2*VDDANA - 0.75V
VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*Vref/GAIN)
Table 38-12.ꢀSingle-Ended Mode
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
Typ.
9.7
Max.
10.1
Units
Bits
ENOB
TUE
INL
Effective Number of Bits
-
-
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
7.9
30.0
LSB
LSB
LSB
1x gain
1.4
+/-0.6
2.6
5.0
DNL
1x gain
+/-0.7
+/-0.95
DS40001882G-page 924
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol Parameter
Conditions
Min.
-5.0
Typ.
0.6
Max.
5.0
Units
mV
%
GE
Gain Error
Ext. Ref. 1x
Gain Accuracy(4)
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
+/-0.1
+/-0.01
-5.0
+/-0.37
+/-0.1
0.6
+/-0.5
+/-0.2
10.0
70.1
62.5
64.0
-65.0
-
%
OE
Offset Error
mV
dB
SFDR
SINAD
SNR
THD
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
1x Gain
FCLK_ADC = 2.1 MHz
63.0
55.0
54.0
-70.0
-
68.0
60.1
61.0
-68.0
1.0
dB
FIN = 40 kHz
dB
AIN = 95% FSR
dB
T = 25°C
mV
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
38.6.3.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-
to-be-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 38-13.ꢀAveraging Feature
Average
Number
Condition
SNR(dB) SINAD(dB) SFDR(dB) ENOB(bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66
65
72.8
75.1
75.3
75.5
10.5
10.62
10.85
10.91
8
67.6
69.7
70.4
65.8
67.1
67.5
32
128
38.6.3.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
DS40001882G-page 925
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Table 38-14.ꢀOffset and Gain Correction Feature
Gain Factor Conditions
Offset Error Gain Error Total Unadjusted
(mV)
0.25
0.2
(mV)
Error (LSB)
0.5x
1x
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
1
2.4
1.5
2.7
3.2
6.1
0.1
2x
0.15
-0.05
0.1
-0.15
0.05
-0.05
8x
16x
38.6.3.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (R ) and a capacitor
SAMPLE
(C
). In addition, the source resistance (R
) must be taken into account when calculating the required
SAMPLE
SOURCE
sample and hold time. The figure below shows the ADC input channel equivalent circuit.
Figure 38-3.ꢀADC Input
VDDANA/2
Analog Input
C
AINx
SAMPLE
R
R
SAMPLE
SOURCE
V
IN
To achieve n bits of accuracy, the C
− n + 1
capacitor must be charged at least to a voltage of
SAMPLE
V
≥ V × 1 − 2
IN
CSAMPLE
The minimum sampling time t
for a given R
can be found using this formula:
SAMPLEHOLD
SOURCE
t
≥ R
+ R
× C
× n + 1 × ln 2
SAMPLEHOLD
SAMPLE
SOURCE
SAMPLE
for a 12 bits accuracy: t
≥ R
+ R
× C × 9.02
SAMPLE
SAMPLEHOLD
SAMPLE
SOURCE
38.6.4 Digital to Analog Converter (DAC) Characteristics
Table 38-15.ꢀOperating Conditions
Symbol Parameter
Conditions
Min.
1.62
1.0
-
Typ.
Max.
Units
V
VDDANA
AVREF
Analog supply voltage
-
-
-
-
-
-
-
3.63
External reference voltage
INT1V(3)
-
VDDANA-0.6
V
1
-
V
VDDANA
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
0.05
5
-
-
VDDANA-0.05
-
V
kΩ
DS40001882G-page 926
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol Parameter
Conditions
Min.
Typ.
-
Max.
100
Units
pF
Maximum capacitance load
DC supply current(2)
-
-
-
IDD
Voltage pump disabled
160
245
μA
Notes:ꢀ
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 38-16.ꢀClock and Timing
Symbol
Parameter
Conditions
Min.
Typ.
Max.
350
1000
2.85
10
Units
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Normal mode
-
-
-
-
-
-
-
-
ksps
For ΔDATA = +/-1
Startup time
VDDNA > 2.6V
VDDNA < 2.6V
μs
μs
Note:ꢀ
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 38-17.ꢀAccuracy Characteristics
Symbol
RES
Parameter
Conditions
Min.
-
Typ.
-
Max.
10
Units
Bits
Input resolution
Integral non-linearity
-
INL
VREF = Ext 1.0V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
0.7
0.75
0.65
0.85
0.8
2.0
LSB
0.6
1.5
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
0.6
2.0
0.5
1.5
0.5
0.75
0.8
1.5
0.7
1.5
DNL
Differential non-linearity
+/-0.3
+/-0.25
+/-0.4
+/-0.2
+/-0.5
+/-0.4
+/-0.5
+/-2
+/-0.4
+/-0.4
+/-0.55
+/-0.3
+/-0.7
+/-0.7
+/-5
+/-1.0
+/-0.75
+/-1.5
+/-0.75
+/-1.5
+/-1.5
+/-12
+/-8
LSB
GE
OE
Gain error
Ext. VREF
Ext. VREF
mV
mV
Offset error
+/-1.5
Note:ꢀ
1. All values measured using a conversion rate of 35 ksps.
DS40001882G-page 927
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.6.5 Analog Comparator Characteristics
Table 38-18.ꢀElectrical and Timing Characteristics
Symbol Parameter
Positive input voltage range
Conditions
Min. Typ.
Max.
VDDANA
VDDANA
+15
Units
0
-
V
Negative input voltage range
Offset
0
-
Hysteresis = 0, Fast mode
-15
-25
20
15
-
0.0
0.0
50
40
90
mV
mV
mV
mV
ns
Hysteresis = 0, Low power mode
Hysteresis = 1, Fast mode
+25
Hysteresis
85
Hysteresis = 1, Low power mode
75
Propagation delay
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
180
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
-
-
282
1
520
2.6
22
ns
μs
μs
tSTARTUP Startup time
Enable to ready delay
Fast mode
Enable to ready delay
Low power mode
14
VSCALE
INL(3)
-1.4
-0.9
0.75
0.25
1.4
LSB
LSB
LSB
LSB
DNL(3)
0.9
Offset Error (1)(2)
Gain Error (1)(2)
-0.20 0.26
+0.92
-0.89 0.215 0.89
1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
38.7
NVM Characteristics
Note that on this flash technology, a max number of four consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 38-19.ꢀFlash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
10
Typ.
50
Max.
Units
Years
Years
Years
Cycles
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 105°C
-
-
-
-
20
100
25
>100
150k
25k
1. An endurance cycle is a write and an erase operation.
Table 38-20.ꢀEEPROM Emulation(1), Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
10
Typ. Max.
50
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
-
Years
DS40001882G-page 928
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ. Max.
Units
Years
Cycles
RetEEPROM10k
CycEEPROM
Retention after up to 10k
Cycling Endurance(2)
Average ambient 55°C
-40°C < Ta < 105°C
20
100
-
-
100k 600k
1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
38.8
Oscillators Characteristics
38.8.1 Crystal Oscillator (XOSC) Characteristics
38.8.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 38-21.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fCPXIN
XIN clock frequency
-
-
32
MHz
38.8.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in Figure 38-4. The user must choose a crystal oscillator where the crystal load capacitance CL is
within the range given in the table. The exact value of CL can be found in the crystal data sheet. The capacitance of
the external capacitors (CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 38-22.ꢀCrystal Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
0.4 32 MHz
fOUT
Crystal oscillator frequency
-
DS40001882G-page 929
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
f = 0.455ꢀMHz, CL = 100pF
XOSC.GAIN = 0
-
-
-
-
-
-
-
-
-
-
-
-
5.6K
416
243
138
66
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
f = 8ꢀMHz, CL = 20pF
XOSC.GAIN = 2
f = 16ꢀMHz, CL = 20pF
XOSC.GAIN = 3
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
56
CXIN
Parasitic capacitor load
Parasitic capacitor load
Current Consumption
-
-
5.9
3.2
65
-
pF
pF
μA
CXOUT
IXOSC
-
f = 2MHz, CL = 20pF, AGC off
f = 2MHz, CL = 20pF, AGC on
f = 4MHz, CL = 20pF, AGC off
f = 4MHz, CL = 20pF, AGC on
f = 8MHz, CL = 20pF, AGC off
f = 8MHz, CL = 20pF, AGC on
f = 16MHz, CL = 20pF, AGC off
f = 16MHz, CL = 20pF, AGC on
f = 32MHz, CL = 18pF, AGC off
f = 32MHz, CL = 18pF, AGC on
87
76
52
117 155
74 104
226 308
128 180
502 714
307 590
1622 2257
615 1280
14K 48K
tSTARTUP Startup time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
-
-
-
-
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
6800 19.5K
5550 13K
f = 8ꢀMHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
f = 16ꢀMHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
6750 14.5K
5.3K 9.6K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
DS40001882G-page 930
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Figure 38-4.ꢀCrystal Oscillator Connection
Xin
CLEXT
Crystal
LM
CSHUNT
RM
CSTRAY
CM
Xout
CLEXT
38.8.2 External 32ꢁkHz Crystal Oscillator (XOSC32K) Characteristics
38.8.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 38-23.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
32.768
50
Max.
Units
kHz
%
fCPXIN32
XIN32 clock frequency
XIN32 clock duty cycle
-
-
-
-
38.8.2.2 Crystal Oscillator Characteristics
Figure 38-4 and the equation in 38.8.1.2 Crystal Oscillator Characteristics also applies to the 32ꢀkHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can be found in the crystal datasheet.
Table 38-24.ꢀ32kHz Crystal Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Crystal oscillator frequency
I
-
32768 - Hz
tSTARTUP Startup time
ESRXTAL = 39.9ꢀkΩ, CL = 12.5ꢀ -
pF
28K
30K cycles
CL
Crystal load capacitance
I
I
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
0.1
3.2
3.7
1.22
-
-
-
-
CXIN32
Parasitic capacitor load
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
2.2
μA
ESR
Crystal equivalent series resistance
CL=12.5pF
100 kΩ
f=32.768kHz
Safety Factor = 3
DS40001882G-page 931
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.8.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 38-25.ꢀDFLL48M Characteristics - Open Loop Mode
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
48
49
MHz
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
403 453 μA
tSTARTUP Startup time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
8
9
μs
fOUT within 90ꢀ% of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table 38-26.ꢀDFLL48M Characteristics - Closed Loop Mode
Symbol Parameter
fOUT Average Output frequency fREF = 32.768kHz
fREF
Conditions
Min. Typ.
Max. Units
47.76 48
48.24 MHz
Reference frequency
Period Jitter
I
0.732 32.768 33
kHz
Jitter
IDFLL
fREF = 32.768kHz
fREF = 32.768kHz
-
-
-
0.42 ns
Power consumption on
VDDIN
403
453
500
μA
μs
tLOCK
Lock time
fREF = 32.768kHz
200
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
38.8.4 32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 38-27.ꢀ32 kHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min.
Typ.
Max. Units
fOUT
Output frequency
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +105]°C, over [1.62, 3.63]V
28.508 32.768 35.132 kHz
32.276 32.768 33.260
31.457 32.768 34.079
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
IOSC32K Current consumption I
tSTARTUP Startup time
-
-
-
0.67
1
1.9
2
μA
cycle
%
I
I
Duty
Duty Cycle
50
-
DS40001882G-page 932
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.8.5 Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 38-28.ꢀUltra Low-Power Internal 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions
Min.
Typ.
Max. Units
fOUT
Output frequency Calibrated against a 32.768 kHz reference at 25°C,
over [-40, +105]°C, over [1.62, 3.63]V
25.559 32.768 40.305 kHz
Calibrated against a 32.768 kHz reference at 25°C, at 31.293 32.768 34.570
VDD = 3.3V
Calibrated against a 32.768 kHz reference at 25°C,
over [1.62, 3.63]V
31.293 32.768 34.570
Duty
Duty cycle
-
50
-
%
1. These values are based on simulation, and not covered by test limits in production or characterization.
2. This oscillator is always on.
38.8.6 8 MHz RC Oscillator (OSC8M) Characteristics
Table 38-29.ꢀInternal 8 MHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
ICalibrated against a 8 MHz reference at 25°C,
over [-40, +105]°C, over [1.62, 3.63]V
7.65
8
8
8
8.17 MHz
Calibrated against a 8 MHz reference at 25°C, at 7.94
VDD = 3.3V
8.06
8.08
1
Calibrated against a 8 MHz reference at 25°C,
over [1.62, 3.63]V
7.92
TempCo Frequency vs. temperature
drift
-1.2
SupplyCo Frequency vs. supply drift
-2
-
2
IOSC8M
Current consumption
IIDLEIDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8 MHz (FRANGE
= 1, PRESC = 0)
64
96
μA
tSTARTUP Startup time
Duty Duty cycle
I
I
-
-
2.4 3.3
50
μs
%
-
38.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 38-30.ꢀFDPLL96M Characteristics (Variant B and L With Silicon Revision E)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
2000 KHz
fOUT
-
96
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
500
900
733
1235
DS40001882G-page 933
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Jp
Period jitter
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
-
2.1
4.0
2.2
4.7
1.2
3.2
6.9
3.6
8.2
2
%
tLOCK
Lock Time
Duty cycle
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
ms
fIN= 2 MHz, fOUT= 96 MHz
25
50
50
60
μs
%
Duty
40
Table 38-31.ꢀFDPLL96M Characteristics(1) (Silicon Revision F and G)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
-
32
48
-
-
2000 KHz
fOUT
-
-
96
-
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
2.1
3.8
2.2
4.4
1.2
-
-
Jp
Period jitter
-
3.0
9.2
3.2
10.0
2
%
-
-
-
tLOCK
Lock Time
Duty cycle
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
-
25
50
50
60
μs
%
Duty
40
Note:ꢀ 1. All values have been characterized with FILTSEL[1/0] as default value.
38.9
PTC Characteristics at 105°C
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating Conditions
VDD = 3.3V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC Configuration
Mutual-capacitance mode
One touch channel
DS40001882G-page 934
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 105°C
System Configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 38-32.ꢀPower Consumption
PTC scan
Drift
Symbol
Parameters
rate
Oversamples
Ta
Typ. Max Units
Calibration
(msec)
4
16
4
9
458
10
50
17 467
5
6
4
5
4
4
452
454
452
453
452
452
16
4
Disabled
100
200
10
16
4
16
4
Current
Consumption
Max 105°C Typ
25°C
IDD
µA
15 466
23 476
16
4
7
8
5
6
6
6
456
459
455
455
453
454
50
16
4
Enabled
100
200
16
4
16
38.10 USB Characteristics
The USB shares the same characteristics as in the -40°C to 85°C.
DS40001882G-page 935
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.
Electrical Characteristics at 125°C
39.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
39.2
Absolute Maximum Ratings
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 39-1.ꢀAbsolute Maximum Ratings
Symbol
VDD
Parameter
Condition
Min.
Max.
3.8
Units
V
Power supply voltage
Current into a VDD pin
Current out of a GND pin
Pin voltage with respect to GND and VDD
Storage temperature
0
IVDD
-
28(1)
mA
mA
V
IGND
-
39(1)
VPIN
GND-0.6V
-60
VDD+0.6V
150
Tstorage
°C
Note:ꢀ
1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group
of GPIOs, see related links. Also note that each VDD/GND pair is connected to 2 clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
Related Links
7.2.4 GPIO Clusters
39.3
General Operating Ratings
The device must operate within the ratings in order for all other electrical characteristics and typical characteristics of
the device to be valid.
Table 39-2.ꢀGeneral Operating Conditions
Symbol
VDD
Parameter
Condition
Min.
1.62(1)
1.62(1)
-40
Typ.
3.3
3.3
25
Max.
3.63
3.63
125
Units
V
Power supply voltage
Analog supply voltage
Temperature range
Junction temperature
VDDANA
TA
V
°C
°C
TJ
-
-
145
Note:ꢀ
Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 37-21.
DS40001882G-page 936
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.4
Maximum Clock Frequencies
Table 39-3.ꢀMaximum GCLK Generator Output Frequencies (Device Variant A)
Symbol
Description
Conditions
Undivided
Divided
Max.
96
Units
MHz
MHz
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
32
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 39-4.ꢀMaximum Peripheral Clock Frequencies (Device Variant A)
Symbol
Description
Max.
32
32
32
32
32
33
2
Units
MHz
MHz
MHz
MHz
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fCPU
CPU clock frequency
fAHB
AHB clock frequency
fAPBA
APBA clock frequency
fAPBB
APBB clock frequency
fAPBC
APBC clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
fGCLK_DPLL_32K
fGCLK_WDT
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
fGCLK_RTC
RTC input clock frequency
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
DS40001882G-page 937
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Description
Max.
48
48
48
48
48
48
48
48
48
96
96
48
48
48
48
64
48
48
13
13
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
MHz
MHz
MHz
MHz
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, fGCLK_TCC1
fGCLK_TCC2, fGCLK_TC3
fGCLK_TC4, fGCLK_TC5
fGCLK_TC6, fGCLK_TC7
fGCLK_ADC
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2, TC3 input clock frequency
TC4, TC5 input clock frequency
TC6, TC7 input clock frequency
ADC input clock frequency
fGCLK_AC_DIG
AC digital input clock frequency
AC analog input clock frequency
DAC input clock frequency
fGCLK_AC_ANA
fGCLK_DAC
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
I2S serializer 0 input clock frequency
I2S serializer 1 input clock frequency
fGCLK_I2S_1
Table 39-5.ꢀMaximum GCLK Generator Output Frequencies (Device Variant B, C, D, and L)
Symbol
Description
Conditions
Undivided
Divided
Max.
96
Units
MHz
MHz
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
48
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 39-6.ꢀMaximum Peripheral Clock Frequencies (Device Variant B, C, D, and L)
Symbol
fCPU
Description
Max. Units
CPU clock frequency
AHB clock frequency
48
48
MHz
MHz
fAHB
DS40001882G-page 938
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Description
Max. Units
fAPBA
APBA clock frequency
48
48
48
33
2
MHz
MHz
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fAPBB
APBB clock frequency
fAPBC
APBC clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
fGCLK_DPLL_32K
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
96
96
48
48
48
48
fGCLK_WDT
fGCLK_RTC
RTC input clock frequency
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, fGCLK_TCC1
fGCLK_TCC2, fGCLK_TCC3, fGCLK_TC3
fGCLK_TC4, fGCLK_TC5
fGCLK_TC6, fGCLK_TC7
fGCLK_ADC
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2, TCC3,TC3 input clock frequency
TC4, TC5 input clock frequency
TC6, TC7 input clock frequency
ADC input clock frequency
fGCLK_AC_DIG
AC digital input clock frequency
DS40001882G-page 939
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Description
Max. Units
fGCLK_AC_ANA
fGCLK_AC1_DIG
fGCLK_AC1_ANA
fGCLK_DAC
AC analog input clock frequency
AC1 digital input clock frequency
AC1 analog input clock frequency
DAC input clock frequency
64
48
64
48
48
13
13
KHz
MHz
KHz
MHz
MHz
MHz
MHz
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
fGCLK_I2S_1
I2S serializer 0 input clock frequency
I2S serializer 1 input clock frequency
39.5
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
•
•
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal
– DFLL48M using XOSC32K as reference and running at 48ꢀMHz
Clocks
•
– DFLL48M used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
•
•
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on flash with 1 wait states
Cache enabled
•
•
•
•
BOD33 disabled
DS40001882G-page 940
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Ta•ble 39-7.ꢀCurrent Consumption (Device Variant A, B, C and L. Silicon Revision F)
Mode
Conditions
TA
Typ.
Max.
4.12
4.13
Units
ACTIVE
CPU running a While(1) algorithm
125°C 3.75
125°C 3.77
mA
CPU running a While(1) algorithm
VDDIN=1.8V,
CPU is running on Flash with 3 wait
states
CPU running a While(1) algorithm, CPU 125°C 62*freq + 228 62*freq + 302 μA
is
(with freq in
running on Flash with 3 wait states with
GCLKIN as reference
MHz)
CPU running a Fibonacci algorithm
125°C 4.85
125°C 4.87
5.29
5.29
mA
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
CPU running a Fibonacci algorithm,
CPU is
125°C 88*freq + 424 88*freq + 486 μA
(with freq in
running on Flash with 3 wait states with
GCLKIN as reference
MHz)
CPU running a CoreMark algorithm
125°C 6.70
125°C 5.98
7.30
6.41
mA
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
CPU running a CoreMark algorithm,
CPU is
running on Flash with 3 wait states with
GCLKIN as reference
125°C 108*freq +
426
108*freq +
492
μA
(with freq in
MHz)
IDLE0
Default operating conditions
Default operating conditions
Default operating conditions
125°C 2.40
125°C 1.79
125°C 1.50
125°C 348.0
2.69
2.05
1.76
850.0
mA
IDLE1
IDLE2
STANDBY
XOSC32K running
, RTC running at 1kHz(1)
μA
μA
(Device Variant B,
Die Revision E)
XOSC32K and RTC stopped(1)
125°C 346.0
125°C 294.0
848.0
782.0
STANDBY
XOSC32K running
, RTC running at 1kHz(1)
(Device Variant B
and C, Die Revision
F)
XOSC32K and RTC stopped(1)
125°C 292.0
780.0
Note:ꢀ
1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
DS40001882G-page 941
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-8.ꢀCurrent Consumption (Silicon Revision G)
Mode
conditions
Ta
Vcc
3,3V
1,8V
Typ.
3.5
Max.
4.0
Units
ACTIVE
CPU running a While 1 algorithm
3.5
4.0
CPU running a While 1 algorithm, with GCLKIN as
reference
3,3V 57*Freq+395 55*Freq+1076
3,3V
1,8V
4.5
4.5
5.0
5.0
CPU running a Fibonacci algorithm
CPU running a Fibonacci algorithm, with GCLKIN
as reference
3,3V 75*Freq+397 72*Freq+1076
mA
3,3V
1,8V
5.1
4.9
5.7
5.5
CPU running a CoreMark algorithm
125°C
CPU running a CoreMark algorithm, with GCLKIN
as reference
3,3V 88*Freq+399 85*Freq+1075
IDLE0
IDLE1
IDLE2
3,3V
3,3V
3,3V
2.0
1.4
1.1
2.5
1.9
1.7
XOSC32K running, RTC running at 1kHz RTC
running at 1kHz (1)
3,3V
3,3V
294.0
292.0
782.0
780.0
STANDBY
µA
XOSC32K and RTC stopped (1)
Note:ꢀ
1. Measurements done with VREG.bit.RUNSTDBY = 1.
Table 39-9.ꢀWake-up Time (SAMD21)
Mode
Conditions
TA
Min. Typ. Max. Units
4.0 4.1 μs
IDLE0
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
125°C 3.9
IDLE1
125°C 13.5 14.9 16.4
125°C 14.4 15.8 17.2
125°C 19.2 20.6 22.1
IDLE2
STANDBY
DS40001882G-page 942
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Figure 39-1.ꢀMeasurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
39.6
Analog Characteristics
39.6.1 Power-On Reset (POR) Characteristics
Table 39-10.ꢀPOR Characteristics
Symbol
VPOT+
VPOT-
Parameter
Conditions
Min. Typ. Max. Units
Voltage threshold on VDD rising
Voltage threshold on VDD falling
VDD falls at 1V/ms or slower
1.27 1.45 1.58
0.72 0.99 1.32
V
V
DS40001882G-page 943
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Figure 39-2.ꢀPOR Operating Principle
39.6.2 Brown-Out Detectors Characteristics
39.6.2.1 BOD33
Table 39-11.ꢀBOD33 Characteristics (Device Variant A)
Symbol Parameter
Step size, between
Conditions
Temp.
Min. Typ. Max. Units
-
34
-
mV
adjacent values in
BOD33.LEVEL
VHYST
tDET
VBOD+ - VBOD-
Detection time
Hysteresis ON
35
-
-
170 mV
Time with VDDANA < VTH
necessary to generate a
reset signal
0.9(1)
-
μs
IBOD33
Current consumption
Continuous mode
Sampling mode
Sampling mode
25°C
-
25
-
48
50
μA
-40 to 125°C -
25°C
-40 to 125°C --
25°C
-
0.034 0.21
2.29
0.132 0.38 μA
-
ISbyBOD33 Current consumption in Standby
mode
-
-40 to 125°C -
-
-
1.62
-
tSTARTUP Start-up time
1.2(1)
μs
DS40001882G-page 944
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-12.ꢀBOD33 Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Step size, between
Conditions
Temp.
Min. Typ. Max. Units
-
34
-
mV
adjacent values in
BOD33.LEVEL
VHYST
tDET
VBOD+ - VBOD-
Detection time
Hysteresis ON
35
-
-
170 mV
Time with VDDANA < VTH
necessary to generate a
reset signal
0.9(1)
-
μs
IBOD33
Current consumption
Continuous mode
Sampling mode
Sampling mode
25°C
-
25
-
48
52
μA
-40 to 125°C -
25°C
-40 to 125°C --
25°C
-
0.03 0.21
2.91
0.13 0.38 μA
-
ISbyBOD33 Current consumption in Standby
mode
-
-40 to 125°C -
-
-
1.7
-
tSTARTUP Start-up time
2.2(1)
μs
Note:ꢀ 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
39.6.3 Analog-to-Digital (ADC) characteristics
Table 39-13.ꢀOperating Conditions (Device Variant A)
Symbol
VDDANA
RES
Parameter
Conditions
Min.
3
Typ.
Max.
3.6
Units
V
Power Supply Voltage
Resolution
T>105°C
-
-
-
-
-
-
8
12
bits
kHz
ksps
fCLK_ADC
ADC Clock frequency
Sample rate(1)
30
5
2100
300
Single shot (with
VDDANA > 3.0V)(4)
Free running
5
250
3
-
-
-
350
ksps
ns
Sampling time(1)
-
-
-
-
Sampling time with DAC as
input(2)
µs
Sampling time with Temp
sens as input(2)
-
-
10
10
-
-
-
-
µs
µs
Sampling time with
Bandgap as input(2)
Conversion time(1)
1x Gain
-
6
-
-
-
cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
1.0
VDDANA-0.6
INT1V
Internal 1V reference (2,5)
-
-
-
-
1.0
-
-
V
V
INTVCC0
Internal ratiometric
reference 0(2)
VDDANA/1.48
DS40001882G-page 945
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
INTVCC0
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 0(2) error
INTVCC1
Internal ratiometric
reference 1(2)
VDDANA>2.0V
-
VDDANA/2
-
V
INTVCC1
Internal ratiometric
2.0V < VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 1(2) error
Conversion range(1)
Differential mode
-VREF
/
-
+VREF/GAIN
V
GAIN
Single-ended mode
0.0
-
3.5
-
+VREF/GAIN
V
CSAMPLE
RSAMPLE
Sampling capacitance(2)
-
-
-
-
-
pF
kΩ
Input channel source
resistance(2)
3.5
IDD
DC supply current(1)
fCLK_ADC = 2.1MHz(3)
-
1.25
1.85
mA
Table 39-14.ꢀOperating Conditions (Device Variant B, C, D and L)
Symbol
VDDANA
RES
Parameter
Conditions
Min.
Typ.
Max.
3.6
12
Units
V
Power Supply Voltage
Resolution
T>105°C
3
-
-
-
-
-
-
-
-
-
8
bits
kHz
ksps
ksps
ksps
ns
fCLK_ADC
ADC Clock frequency
Conversion speed
Sample rate(1)
-
30
10
5
2100
1000
300
350
-
-
Single shot
Free running
5
Sampling time(1)
-
-
250
3
Sampling time with DAC as
input(2)
-
µs
Sampling time with Temp
sens as input(2)
-
-
10
10
-
-
-
-
µs
µs
Sampling time with
Bandgap as input(2)
Conversion time(1)
1x Gain
-
6
-
-
-
cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
1.0
VDDANA-0.6
INTV1
Internal 1V reference (2,4)
-
-
-
-
1.0
-
V
V
INTVCC0
Internal ratiometric
reference 0(2)
VDDANA/1.48 -
INTVCC0
Internal ratiometric
2.0V <
VDDANA<3.63V
-1.0
-
-
+1.0
%
V
Voltage Error reference 0(2) error
INTVCC1
Internal ratiometric
reference 1(2)
VDDANA>2.0V
VDDANA/2
-
DS40001882G-page 946
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
INTVCC1
Internal ratiometric
2.0V <
VDDANA<3.63V
-1.0
-
+1.0
%
Voltage Error reference 1(2) error
Conversion range(1)
Differential mode
-VREF
GAIN
/
-
+VREF/GAIN V
+VREF/GAIN V
Single-ended mode
0.0
-
CSAMPLE
RSAMPLE
Sampling capacitance(2)
-
-
3.5
-
-
pF
Input channel source
resistance(2)
3.5
kΩ
IDD
DC supply current(1)
fCLK_ADC = 2.1MHz(3)
-
1.25
1.85
mA
Notes:ꢀ
1. These values are based on characterization, and are not covered by test limits in production.
2. These values are based on simulation, and are not covered by test limits in production or characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running).
4. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 39-15.ꢀDifferential Mode (Device Variant A)
Symbol
ENOB
TUE
Parameter
Conditions
Min.
-
Typ.
10.5
4.3
Max.
10.9
17.0
6.5
Units
bits
Effective Number Of Bits
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
With gain compensation
1x Gain
1.5
1.0
LSB
LSB
INL
1x Gain
1.3
DNL
1x Gain
+/-0.3 +/-0.5 +/-0.95 LSB
GE
Ext. Ref 1x
-15.0
-20.0
-15.0
2.5
+20.0
+20.0
+15.0
mV
mV
mV
%
VREF=VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
-1.5
-5.0
Gain Accuracy(5)
Offset Error
+/-0.1 +/-0.2 +/-0.45
+/-0.1 +/-0.2 +/-2.0
%
OE
-10.0
-10.0
-10.0
64.2
64.1
64.3
-74.8
0.6
-1.5
0.5
+10.0
+15.0
+15.0
78.9
66
mV
mV
mV
dB
dB
dB
dB
mV
VREF=VDDANA/1.48
VREF = INT1V
3.0
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1 MHz
70.0
65.0
65.5
-64.0
1.0
FIN = 40 kHz
66.0
-65.0
1.6
AIN = 95% FSR
THD
Total Harmonic Distortion
Noise RMS
T = 25°C
DS40001882G-page 947
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-16.ꢀDifferential Mode (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
-
Typ.
10.5
2.7
Max.
10.8
14
Units
bits
ENOB
TUE
INL
Effective Number Of Bits
With gain compensation
1x Gain
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
1.5
LSB
LSB
1x Gain
0.9
1.3
4
DNL
GE
1x Gain
+/-0.3
-10.0
-25.0
-25.0
+/-0.5
-1.3
-10.1
+2
+/-0.95 LSB
Ext. Ref 1x
+10
mV
mV
mV
%
VREF = VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
+10.0
+10.0
Gain Accuracy(5)
Offset Error
+/-0.005 +/-0.05 +/-0.15
+/-0.01
-8.0
+/-0.03 +/-0.5
%
OE
-1.0
-0.6
-1.0
71.5
65.0
66
+8.0
+8.0
+8.0
73.5
67.0
68.6
-67.0
1.6
mV
mV
mV
dB
dB
dB
dB
mV
VREF = VDDANA/1.48
VREF = INT1V
-8.0
-6.0
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1 MHz
65.0
58.0
60.0
-73.0
0.6
FIN = 40 kHz
AIN = 95% FSR
THD
Total Harmonic Distortion
Noise RMS
-71.0
1.0
T = 25°C
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the
input voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage):
–
3.1.1I.f |VIN| > VREF/4
– VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 -0.05*VDDANA -0.1V
3.1.2I.f |VIN| < VREF/4
– VCM_IN < 1.2*VDDANA - 0.75V
– VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*Vref/GAIN)
Table 39-17.ꢀSingle-Ended Mode (Device Variant A)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
Typ.
9.5
Max.
9.8
Units
Bits
ENOB
TUE
INL
Effective Number of Bits
-
Total Unadjusted Error
Integral Non-Linearity
-
10.5
1.6
14.0
7.5
LSB
LSB
1x gain
1.0
DS40001882G-page 948
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
1x gain
Min.
Typ.
+/-0.6
0.7
Max.
Units
DNL
GE
Differential Non-Linearity
+/-0.5
-10.0
+/-0.1
+/-0.95 LSB
Gain Error
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
+10.0
mV
%
Gain Accuracy(4)
+/-0.34 +/-0.4
+/-0.01 +/-0.1
+/-0.15
+10.0
66.5
61.0
64.0
-62.1
-
%
OE
Offset Error
-5.0
63.1
50.7
49.9
-65.4
-
1.5
mV
dB
dB
dB
dB
mV
SFDR
SINAD
SNR
THD
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
1x Gain
FCLK_ADC = 2.1 MHz
65.0
59.5
60.0
-63.0
1.0
FIN = 40 kHz
AIN = 95% FSR
T = 25°C
Table 39-18.ꢀSingle-Ended Mode (Device Variant B, C, D and L)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
-
Typ.
9.7
Max.
10.1
40.0
6.0
Units
Bits
ENOB
TUE
INL
Effective Number of Bits
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
Gain Error
-
7.9
LSB
LSB
1x gain
1.4
2.6
DNL
GE
1x gain
+/-0.6
-5.0
+/-0.1
+/-0.7
0.6
+/-0.95 LSB
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
+5.0
mV
%
Gain Accuracy(4)
+/-0.37 +/-0.55
+/-0.01 +/-0.1
+/-0.2
+10.0
68.7
62.5
64.0
-65.0
-
%
OE
Offset Error
-5.0
63.0
55.0
54.0
-69.0
-
0.6
mV
dB
dB
dB
dB
mV
SFDR
SINAD
SNR
THD
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
1x Gain
FCLK_ADC = 2.1 MHz
68.0
60.1
61.0
-68.0
1.0
FIN = 40 kHz
AIN = 95%FSR
T = 25°C
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
DS40001882G-page 949
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.6.4 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (R ) and a capacitor
SAMPLE
(C
). In addition, the source resistance (R
) must be taken into account when calculating the required
SAMPLE
SOURCE
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
Figure 39-3.ꢀADC Input
VDDANA/2
Analog Input
C
AINx
SAMPLE
R
R
SAMPLE
SOURCE
V
IN
To achieve n bits of accuracy, the C
− n + 1
capacitor must be charged at least to a voltage of
SAMPLE
V
≥ V × 1 + − 2
IN
CSAMPLE
The minimum sampling time t
for a given R
can be found using this formula:
SAMPLEHOLD
SOURCE
t
≥ R
+ R
× C
× n + 1 × ln 2
SAMPLEHOLD
SAMPLE
SOURCE
SAMPLE
for a 12 bits accuracy: t
≥ R
+ R
× C × 9.02
SAMPLE
SAMPLEHOLD
SAMPLE
SOURCE
39.6.5 Digital to Analog Converter (DAC) Characteristics
Table 39-19.ꢀOperating Conditions(1)(Device Variant A)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
V
VDDANA
AVREF
Analog supply voltage
-
-
-
-
-
-
-
1.62
-
3.63
External reference voltage
INT1V(3)
1.0
-
VDDANA-0.6
V
-
1
-
V
VDDANA
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
Maximum capacitance load
DC supply current(2)
0.05
-
VDDANA-0.05
V
5
-
-
-
-
kΩ
pF
μA
100
242
IDD
Voltage pump disabled
-
160
Table 39-20.ꢀOperating Conditions(1)(Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
VDDANA
Analog supply voltage
-
1.62
-
3.63
V
DS40001882G-page 950
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
V
AVREF
External reference voltage
-
1.0
-
VDDANA-0.6
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
Maximum capacitance load
DC supply current(2)
-
0.05
-
VDDANA-0.05
V
-
5
-
-
-
-
kΩ
pF
μA
-
100
283
IDD
Voltage pump disabled
-
160
Notes:ꢀ
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 39-21.ꢀClock and Timing(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
350
1000
2.85
10
Units
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Normal mode
-
-
-
-
-
-
-
-
ksps
For ΔDATA = +/-1
Startup time
VDDNA > 2.6V
VDDNA < 2.6V
μs
μs
Note:ꢀ
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 39-22.ꢀAccuracy Characteristics(1)(Device Variant A)
Symbol
RES
Parameter
Conditions
Min.
-
Typ.
-
Max.
10
Units
Bits
Input resolution
Integral non-linearity
-
INL
VREF = Ext 1.0V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
0.75
0.6
1.4
0.9
0.75
0.8
1.1
1.2
2.2
1.4
1.3
1.2
2.0
2.5
3.5
1.5
2.5
1.5
LSB
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Ext. VREF
DNL
Differential non-linearity
+/-0.9 +/-1.2 +/-2.0
+/-0.9 +/-1.1 +/-1.5
+/-1.1 +/-1.7 +/-3.0
+/-1.0 +/-1.1 +/-1.6
+/-1.1 +/-1.4 +/-2.5
+/-1.0 +/-1.5 +/-1.8
LSB
GE
Gain error
+/-1.0
+/-5
+/-10
mV
DS40001882G-page 951
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Offset error
Conditions
Min.
Typ.
Max.
Units
OE
Ext. VREF
+/-2
+/-3
+/-8
mV
Table 39-23.ꢀAccuracy Characteristics(1)(Device Variant B, C, D and L)
Symbol
RES
Parameter
Conditions
Min.
Typ.
Max.
10
Units
Bits
Input resolution
Integral non-linearity
-
-
-
INL
VREF = Ext 1.0V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
VDD = 1.6V
VDD = 3.6V
0.7
0.75
2.0
LSB
0.6
0.65
1.5
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
0.6
0.85
2.0
0.5
0.8
1.5
0.5
0.75
1.5
0.7
0.8
1.5
DNL
Differential non-linearity
+/-0.3
+/-0.25
+/-0.4
+/-0.2
+/-0.5
+/-0.4
+/-0.5
+/-2
+/-0.4
+/-0.4
+/-0.55
+/-0.3
+/-0.7
+/-0.7
+/-5
+/-1.0
+/-0.75
+/-1.5
+/-0.75
+/-1.5
+/-1.5
+/-12
+/-8
LSB
GE
OE
Gain error
Ext. VREF
Ext. VREF
mV
mV
Offset error
+/-1.5
Note:ꢀ
1. All values measured using a conversion rate of 35 ksps.
39.6.6 Analog Comparator Characteristics
Table 39-24.ꢀElectrical and Timing (Device Variant A)
Symbol Parameter
Positive input voltage range
Conditions
Min.
Typ. Max.
Units
0
-
VDDANA
V
Negative input voltage range
Offset
0
-
VDDANA
+15
+25
83
Hysteresis = 0, Fast mode
-15
-25
20
15
-
0.0
0.0
50
40
60
mV
mV
mV
mV
ns
Hysteresis = 0, Low power mode
Hysteresis = 1, Fast mode
Hysteresis
Hysteresis = 1, Low power mode
75
Propagation delay
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
116
Changes for VACM=VDDANA/2
-
225
370
ns
100mV overdrive, Low power mode
DS40001882G-page 952
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min.
Typ. Max.
Units
tSTARTUP Startup time
Enable to ready delay
Fast mode
-
1
2
μs
Enable to ready delay
Low power mode
-
12
19
μs
VSCALE
INL(3)
-
-
0.75
0.25
+1.58
+0.95
LSB
LSB
DNL(3)
Offset Error (1)(2)
Gain Error (1)(2)
-0.200 0.260 +1.035 LSB
0.55
1.2
2.0
LSB
Table 39-25.ꢀElectrical and Timing (Device Variant B, C, D and L)
Symbol Parameter
Positive input voltage range
Conditions
Min.
0
Typ. Max.
Units
-
VDDANA
V
Negative input voltage range
Offset
0
-
VDDANA
+15
+25
90
Hysteresis = 0, Fast mode
-15
-25
20
15
-
0.0
0.0
50
40
90
mV
mV
mV
mV
ns
Hysteresis = 0, Low power mode
Hysteresis = 1, Fast mode
Hysteresis
Hysteresis = 1, Low power mode
75
Propagation delay
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
180
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
-
-
282
1
520
2.6
22
ns
μs
μs
tSTARTUP Startup time
Enable to ready delay
Fast mode
Enable to ready delay
Low power mode
14
VSCALE
INL(3)
-
-
0.75
0.25
+1.58
+0.95
LSB
LSB
DNL(3)
Offset Error (1)(2)
Gain Error (1)(2)
-0.200 0.260 +1.035 LSB
0.55 1.2 2.0 LSB
Notes:ꢀ
1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
39.6.7 Temperature Sensor Characteristics
Table 39-26.ꢀTemperature Sensor Characteristics(1)(Device Variant A)
Symbol Parameter
Temperature sensor
Conditions
Min. Typ. Max. Units
0.667 -
T= 25°C, VDDANA = 3.3V
-
V
output voltage
DS40001882G-page 953
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
Temperature sensor
2.2
2.4
2.7
mV/°C
slope
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-9
1
14
mV/V
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-13.0 -
13.0 °C
Table 39-27.ꢀTemperature Sensor Characteristics(1)(Device Variant B, C, D and L)
Symbol Parameter
Temperature sensor
Conditions
Min. Typ. Max. Units
0.688 -
T= 25°C, VDDANA = 3.3V
-
V
output voltage
Temperature sensor
slope
2.06 2.16 2.26 mV/°C
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-0.4 1.4
-13.0 -
3
mV/V
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
13.0 °C
Note:ꢀ 1. These values are based on characterization. These values are not covered by test limits in production.
39.7
NVM Characteristics
Table 39-28.ꢀMaximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
1
2
0
1
14
28
40
24
40
MHz
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 39-29.ꢀFlash Endurance and Data Retention
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
Years
Years
Years
Cycles
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 125°C
10
50
-
-
-
-
20
100
>100
150k
25
25k
Note: 1. An endurance cycle is a write and an erase operation.
DS40001882G-page 954
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-30.ꢀEEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
10
Typ.
50
Max. Units
RetEEPROM100k
RetEEPROM10k
CycEEPROM
Retention after up to 100k
Retention after up to 10k
Cycling Endurance(2)
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 125°C
-
-
-
Years
Years
Cycles
20
100
100k 600k
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
39.8
Oscillators Characteristics
39.8.1 Crystal Oscillator (XOSC) Characteristics
39.8.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 39-31.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fCPXIN
XIN clock frequency
-
-
32
MHz
39.8.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT . The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 39-32.ꢀCrystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max. Units
0.4 32 MHz
fOUT
Crystal oscillator frequency
-
DS40001882G-page 955
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
f = 0.455ꢀMHz, CL = 100pF
XOSC.GAIN = 0
-
-
-
-
-
-
-
-
-
-
-
-
5.6K
416
243
138
66
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
f = 8ꢀMHz, CL = 20pF
XOSC.GAIN = 2
f = 16ꢀMHz, CL = 20pF
XOSC.GAIN = 3
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
56
CXIN
Parasitic capacitor load
Parasitic capacitor load
Current Consumption
-
-
5.9
3.2
65
-
pF
pF
μA
CXOUT
-
f = 2MHz, CL = 20pF, AGC off 27
f = 2MHz, CL = 20pF, AGC on 14
f = 4MHz, CL = 20pF, AGC off 61
f = 4MHz, CL = 20pF, AGC on 23
90
79
52
117 161
74 110
f = 8MHz, CL = 20pF, AGC off 131 226 319
f = 8MHz, CL = 20pF, AGC on 56 128 193
f = 16MHz, CL = 20pF, AGC off 305 502 742
f = 16MHz, CL = 20pF, AGC on 116 307 627
f = 32MHz, CL = 18pF, AGC off 1031 1622 2344
f = 32MHz, CL = 18pF, AGC on 278 615 1422
tSTARTUP Start-up time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
-
-
-
-
14K 48K
6800 19.5K
5550 13K
6750 14.5K
5.3K 9.6K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
f = 8ꢀMHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
f = 16ꢀMHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
Table 39-33.ꢀCrystal Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min. Typ. Max. Units
0.4 32 MHz
fOUT
Crystal oscillator frequency
-
DS40001882G-page 956
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max. Units
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
f = 0.455ꢀMHz, CL = 100pF
XOSC.GAIN = 0
-
-
-
-
-
-
-
-
-
-
-
-
5.6K
416
243
138
66
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
f = 8ꢀMHz, CL = 20pF
XOSC.GAIN = 2
f = 16ꢀMHz, CL = 20pF
XOSC.GAIN = 3
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
56
CXIN
Parasitic capacitor load
Parasitic capacitor load
Current Consumption
-
-
5.9
3.2
65
-
pF
pF
μA
CXOUT
-
f = 2MHz, CL = 20pF, AGC off 27
f = 2MHz, CL = 20pF, AGC on 14
f = 4MHz, CL = 20pF, AGC off 61
f = 4MHz, CL = 20pF, AGC on 23
90
79
52
117 160
74 110
f = 8MHz, CL = 20pF, AGC off 131 226 319
f = 8MHz, CL = 20pF, AGC on 56 128 193
f = 16MHz, CL = 20pF, AGC off 305 502 741
f = 16MHz, CL = 20pF, AGC on 116 307 626
f = 32MHz, CL = 18pF, AGC off 1031 1622 2344
f = 32MHz, CL = 18pF, AGC on 278 615 1400
tSTARTUP Start-up time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
-
-
-
-
14K 48K
6800 19.5K
5550 13K
6750 14.5K
5.3K 9.6K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
f = 8ꢀMHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
f = 16ꢀMHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
DS40001882G-page 957
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Figure 39-4.ꢀOscillator Connection
Xin
CLEXT
Crystal
LM
CSHUNT
RM
CSTRAY
CM
Xout
CLEXT
39.8.2 External 32ꢁkHz Crystal Oscillator (XOSC32K) Characteristics
39.8.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 39-34.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
32.768
50
Max.
Units
kHz
%
fCPXIN32
XIN32 clock frequency
XIN32 clock duty cycle
-
-
-
-
39.8.2.2 Crystal Oscillator Characteristics
Figure 37-6 and the equation in also applies to the 32ꢀkHz oscillator connection. The user must choose a crystal
oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
found in the crystal data sheet.
Table 39-35.ꢀ32kHz Crystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Crystal oscillator frequency
-
-
32768 - Hz
tSTARTUP Startup time
ESRXTAL = 39.9ꢀkΩ, CL = 12.5ꢀ
pF
28K
31K cycles
CL
Crystal load capacitance
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
0.1
3.1
3.3
1.22
-
-
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
CL=12.5pF
-
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
2.44 µA
141 kΩ
ESR
Crystal equivalent series resistance
f=32.768kHz
, Safety Factor = 3
DS40001882G-page 958
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-36.ꢀ32kHz Crystal Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Crystal oscillator frequency
-
-
32768 - Hz
tSTARTUP Startup time
ESRXTAL = 39.9ꢀkΩ, CL = 12.5ꢀ
pF
28K
30K cycles
CL
Crystal load capacitance
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
0.1
3.2
3.7
1.22
-
-
-
-
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
CL=12.5pF
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
2.2
µA
ESR
Crystal equivalent series resistance
100 kΩ
f=32.768kHz
, Safety Factor = 3
39.8.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 39-37.ꢀDFLL48M Characteristics - Open Loop Mode(1)(Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max. Units
48 49 MHz
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
403 457 μA
tSTARTUP Start-up time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
7
8
9
μs
fOUT within 90ꢀ% of final value
Table 39-38.ꢀDFLL48M Characteristics - Open Loop Mode(1)(Device Variant B, C, D and L)
Symbol Parameter Conditions
Min. Typ. Max. Units
48 49 MHz
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
403 453 μA
tSTARTUP Start-up time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-
8
9
μs
fOUT within 90ꢀ% of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table 39-39.ꢀDFLL48M Characteristics - Closed Loop Mode(1)(Device Variant A)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
fREF
Jitter
Average Output frequency fREF = 32 .768kHz
Reference frequency
47.76 48
48.24 MHz
0.732 32.768 33
kHz
Cycle to Cycle jitter
fREF = 32 .768kHz
-
-
1.04 ns
DS40001882G-page 959
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max. Units
IDFLL
Power consumption on
fREF = 32 .768kHz
-
425
482
μA
VDDIN
tLOCK
Lock time
fREF = 32 .768kHz
100
200
500
μs
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Table 39-40.ꢀDFLL48M Characteristics - Closed Loop Mode(1)(Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
fREF
Average Output frequency fREF = 32 .768kHz
Reference frequency
47.76 48
48.24 MHz
0.732 32.768 33
kHz
Jitter
IDFLL
Cycle to Cycle jitter
fREF = 32 .768kHz
fREF = 32 .768kHz
-
-
-
0.42 ns
Power consumption on
VDDIN
403
453
500
μA
μs
tLOCK
Lock time
fREF = 32 .768kHz
-
200
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
39.8.4 32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 39-41.ꢀ32 kHz RC Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
28.508 32.768 35.389 kHz
32.276 32.768 33.260
31.457 32.768 34.079
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
IOSC32K Current consumption
tSTARTUP Start-up time
-
-
-
0.79
1
1.80
μA
2
-
cycle
%
Duty
Duty Cycle
50
DS40001882G-page 960
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-42.ꢀ32 kHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
28.508 32.768 35.389 kHz
32.276 32.768 33.260
31.457 32.768 34.079
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
IOSC32K Current consumption
tSTARTUP Start-up time
-
-
-
0.67
1
2.80
μA
2
-
cycle
%
Duty
Duty Cycle
50
39.8.5 Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 39-43.ꢀUltra Low-Power Internal 32 kHz RC Oscillator Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
25.559 32.768 40.305 kHz
31.293 32.768 34.570
31.293 32.768 34.570
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
(1)(2)
iOSCULP32K
tSTARTUP
Duty
-
-
-
-
180
nA
Start-up time
Duty Cycle
10
50
-
-
cycles
%
Table 39-44.ꢀUltra Low-Power Internal 32 kHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency Calibrated against a 32.768 kHz reference at 25°C,
over [-40, +125]°C, over [1.62, 3.63]V
25.559 32.768 40.305 kHz
Calibrated against a 32.768 kHz reference at 25°C, at 31.293 32.768 34.570
VDD = 3.3V
Calibrated against a 32.768 kHz reference at 25°C,
over [1.62, 3.63]V
31.293 32.768 34.570
Duty
Duty Cycle
-
50
-
%
Notes:ꢀ
1. These values are based on simulation, and are not covered by test limits in production or characterization.
2. This oscillator is always on.
DS40001882G-page 961
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.8.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 39-45.ꢀInternal 8MHz RC Oscillator Characteristics (Device Variant A)
Symbol Parameter
fOUT Output frequency
Conditions
Min. Typ. Max. Units
Calibrated against a 8MHz reference at 25°C, over [-40, 7.54 8
+125]°C, over [1.62, 3.63]V
8.19 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.08
IOSC8M Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
64
100 μA
tSTARTUP Startup time
-
-
2.1
50
3
-
μs
%
Duty
Duty cycle
Table 39-46.ꢀInternal 8MHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
fOUT Output frequency
Conditions
Min. Typ. Max. Units
Calibrated against a 8MHz reference at 25°C, over [-40, 7.54 8
+125]°C, over [1.62, 3.63]V
8.19 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.06
IOSC8M Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
64
96
μA
tSTARTUP Startup time
-
-
2.4 3.3
50
μs
%
Duty
Duty cycle
-
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 39-47.ꢀFDPLL96M Characteristics(1) (Device Variant A)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
1.5
3.0
1.3
3.0
1.3
700
1200
2.0
10.0
2.0
7.0
2
-
Jp
Period jitter
-
%
-
-
-
tLOCK
Lock Time
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
μs
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
DS40001882G-page 962
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Duty cycle
Conditions
Min. Typ. Max. Units
Duty
40
50
60
%
Table 39-48.ꢀFDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
1.5
4.0
1.6
4.6
1.2
740
1262
2.5
10.5
2.5
11.0
2
-
Jp
Period jitter
-
%
-
-
-
tLOCK
Lock Time
Duty cycle
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
50
60
μs
%
Duty
40
Table 39-49.ꢀFDPLL96M Characteristics(1) (Device Variant B, C, D and L with Silicon Revision F and G)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
32
48
-
-
2000 KHz
fOUT
-
96
-
MHz
μA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
500
900
2.1
3.8
2.2
5.0
1.2
-
-
Jp
Period jitter
-
3.2
9.2
3.4
10.5
2
%
-
-
-
tLOCK
Lock Time
Duty cycle
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
50
60
μs
%
Duty
40
Note:ꢀ
1. All values have been characterized with FILTSEL[1/0] as default value.
39.8.8 PTC Characteristics at 125°C
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating Conditions
DS40001882G-page 963
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Electrical Characteristics at 125°C
VDD = 3.3V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC is running at 4MHz
PTC Configuration
Mutual-capacitance mode
One touch channel
System Configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 39-50.ꢀPower Consumption (1)
PTC scan
Drift
Symbol
Parameters
rate
Oversamples
Ta
Typ. Max Units
Calibration
(msec)
4
16
4
66 791
75 803
61 787
63 791
61 788
62 790
60 788
10
50
16
4
Disabled
100
200
10
16
4
16
4
61 789
µA
71 802
Current
Consumption
Max 125°C Typ
25°C
IDD (2)
16
4
80 813
63 792
65 795
62 791
63 793
62 790
63 791
50
16
4
Enabled
100
200
16
4
16
Notes:ꢀ
1. These are based on characterization.
2. On this table, the LDO Voltage Regulator is enabled in Standby mode (SYSCTRL.VREG.RUNSTDBY = 1).
39.8.9 USB Characteristics
The USB shares the same characteristics as in the -40°C to 85°C.
DS40001882G-page 964
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
40.
AEC-Q100 125°C Specifications
40.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
40.2
Thermal Considerations
40.2.1 Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 40-1.ꢀThermal Resistance Data
Package Type
θJA
θJC
32-pin QFN (Wettable Flanks)
48-pin QFN (Wettable Flanks)
64-pin QFN (Wettable Flanks)
32-pin TQFP
40.5°C/W
31.9°C/W
32.5°C/W
64.7°C/W
63.6°C/W
60.9°C/W
16.0°C/W
11.7°C/W
11.3°C/W
23.1°C/W
12.2°C/W
12.2°C/W
48-pin TQFP
64-pin TQFP
40.2.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. TJ = TA + (PD x θJA)
2. TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
40.3
Absolute Maximum Ratings
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DS40001882G-page 965
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-2.ꢀAbsolute Maximum Ratings
Symbol
VDD
Description
Conditions
Min.
Max.
3.8
Units
V
Power Supply Voltage
Current into a VDD pin
Current out of a GND pin
Pin voltage with respect to GND and VDD
Storage temperature
0
-
IVDD
28 (1)
39 (1)
mA
mA
V
IGND
-
VPIN
GND-0.3V VDD+0.3V
-60 150
TSTORAGE
°C
Note:ꢀ
1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group
of GPIOs, see related links. Also note that each VDD/GND pair is connected to 2 clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
Related Links
GPIO Clusters
40.4
General Operating Ratings
The device must operate within the ratings listed in the following table in order for all other electrical characteristics
and typical characteristics of the device to be valid.
Table 40-3.ꢀGeneral Operating Conditions
Symbol
VDD
Description
Conditions
Min.
2.7
2.7
-40
-
Typ.
3.3
3.3
25
Max.
3.63
3.63
125
Units
V
Power Supply Voltage
Analog supply voltage
Temperature range
Junction Temperature
VDDANA
TA
V
°C
°C
TJ
-
145
40.5
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 125°C, unless
otherwise specified and are valid for a junction temperature up to TJ = 145°C.
Table 40-4.ꢀSupply Characteristics
Symbol
Conditions
Voltage
Max
Units
Min
VDDIO
VDDIN
Full Voltage Range
2.7
3.63
V
VDDANA
DS40001882G-page 966
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-5.ꢀSupply Rates
Fall Rate Rise Rate
Units
Symbol Conditions
Max
Max
VDDIO
VDDIN
DC supply peripheral I/Os, internal regulator and analog supply voltage
0.05
0.1
V/μs
VDDANA
Note:ꢀ To secure power up and power down sequence, enabling BOD33 is recommended.
Related Links
Power Supply and Start-Up Considerations
40.6
Maximum Clock Frequencies
Table 40-6.ꢀMaximum GCLK Generator Output Frequencies (Device Variant A)
Symbol
Description
Conditions
Undivided
Divided
Max
64
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
MHz
MHz
32
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
Table 40-7.ꢀMaximum Peripheral Clock Frequencies (Device Variant A)
Symbol
Description
Max.
32
32
32
32
32
33
2
Units
MHz
MHz
MHz
MHz
MHz
kHz
fCPU
CPU clock frequency
fAHB
AHB clock frequency
fAPBA
APBA clock frequency
fAPBB
APBB clock frequency
fAPBC
APBC clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
fGCLK_DPLL_32K
fGCLK_WDT
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
RTC input clock frequency
MHz
kHz
32
48
48
48
48
48
48
48
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fGCLK_RTC
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
DS40001882G-page 967
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Description
Max.
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
80
80
48
48
48
48
64
48
48
13
13
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, fGCLK_TCC1
fGCLK_TCC2, fGCLK_TC3
fGCLK_TC4, fGCLK_TC5
fGCLK_TC6, fGCLK_TC7
fGCLK_ADC
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2,TC3 input clock frequency
TC4, TC5 input clock frequency
TC6,TC7 input clock frequency
ADC input clock frequency
fGCLK_AC_DIG
AC digital input clock frequency
AC analog input clock frequency
DAC input clock frequency
fGCLK_AC_ANA
fGCLK_DAC
MHz
MHz
MHz
MHz
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
I2S serial 0 input clock frequency
I2S serial 1 input clock frequency
fGCLK_I2S_1
DS40001882G-page 968
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-8.ꢀMaximum GCLK Generator Output Frequencies (Device Variant B, D)
Symbol
Description
Conditions
Max
Units
fGCLKGEN0
fGCLK_MAIN
/
GCLK Generator
Output Frequency
Undivided
96
MHz
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
Divided
48
MHz
Table 40-9.ꢀMaximum Peripheral Clock Frequencies (Device Variant B, D)
Symbol
Description
Max. Units
fCPU
CPU clock frequency
48
48
48
48
48
33
2
MHz
MHz
MHz
MHz
MHz
KHz
MHz
KHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fAHB
AHB clock frequency
fAPBA
APBA clock frequency
fAPBB
APBB clock frequency
fAPBC
APBC clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
fGCLK_DPLL_32K
fGCLK_WDT
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
fGCLK_RTC
RTC input clock frequency
fGCLK_EIC
EIC input clock frequency
fGCLK_USB
USB input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
DS40001882G-page 969
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Description
Max. Units
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, GCLK_TCC1
fGCLK_TCC2,fGCLK_TCC3
fGCLK_TC4, GCLK_TC5
fGCLK_TC6, GCLK_TC7
fGCLK_ADC
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2, TCC3, TC3 input clock frequency
TC4, TC5 input clock frequency
TC6,TC7 input clock frequency
ADC input clock frequency
48
48
48
48
48
48
96
96
48
48
48
48
64
48
48
13
13
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
,
GCLK_TC3
fGCLK_AC_DIG
AC digital input clock frequency
AC analog input clock frequency
DAC input clock frequency
fGCLK_AC_ANA
fGCLK_DAC
MHz
MHz
MHz
MHz
fGCLK_PTC
PTC input clock frequency
fGCLK_I2S_0
I2S serial 0 input clock frequency
I2S serial 1 input clock frequency
fGCLK_I2S_1
40.7
Power Consumption
The values provided in the following table are measured values of power consumption, which are valid under the
following conditions, except where noted:
•
Operating conditions:
– VDDIN = 3.3V
•
•
Wake up time from Sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in Flash.
Oscillators:
– XOSC (Crystal scillator) stopped
– XOSC32K (32 kHz Crystal Oscillator) running with external 32 kHz crystal
– DFLL48M using XOSC32K as reference and running at 48 MHz
Clocks:
•
– DFLL48M used as main clock source, except otherwise specified.
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
•
•
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
•
•
I/Os are inactive with internal pull-up
CPU is running on Flash with 1 wait states
DS40001882G-page 970
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
•
•
NVMCTRL cache enabled
BOD33 disabled
Table 40-10.ꢀCurrent Consumption (Device Variant A)
Mode
Conditions
TA
VCC Typ.
3.3V 3.4
3.3V 3.8
Max.
3.9
Units
ACTIVE
CPU running a While 1 algorithm 25°C
125°C
mA
6.1
CPU running a While 1 algorithm, 25°C
3.3V 60*Freq+136 81*Freq+126
3.3V 62*Freq+498 70*Freq+1780
µA
with
(with freq. in
MHz)
125°C
GCLKIN as reference
CPU running a Fibonacci
algorithm
25°C
3.3V 4.6
3.3V 5.0
5.0
7.3
mA
125°C
25°C
CPU running a Fibonacci
algorithm, with
3.3V 92*Freq+113 99*Freq+141
3.3V 92*Freq+503 91*Freq+1794
µA
(with freq. in
MHz)
125°C
GCLKIN as reference
CPU running a CoreMark
algorithm
25°C
3.3V 6.3
3.3V 6.7
6.8
8.6
mA
125°C
25°C
CPU running a CoreMark
algorithm, with
3.3V 118*Freq+116 131*Freq+141 µA
(with freq. in
3.3V 121*Freq+506 122*Freq+1792
125°C
GCLKIN as reference
MHz)
IDLE0
IDLE1
IDLE2
Default operating conditions
25°C
3.3V 2.0
3.3V 2.4
3.3V 1.5
3.3V 1.8
3.3V 1.2
3.3V 1.5
3.3V 4.2
2.2
mA
125°C
25°C
4.0
Default operating conditions
Default operating conditions
1.6
125°C
25°C
3.3
1.3
125°C
25°C
3.0
STANDBY (1) XOSC32K running
RTC running at 1kHz
13.3
1128.0
12.2
1126.0
µA
125°C (1) 3.3V 430.6
25°C 3.3V 2.9
125°C(1) 3.3V 428.6
XOSC32K and RTC stopped
Note:ꢀ
1. Measurements done with VREG.bit.RUNSTDBY = 1.
DS40001882G-page 971
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-11.ꢀCurrent Consumption (Device Variant B)
Mode
Conditions
TA
Vcc Typ.
Max.
3.1
Units
ACTIVE
CPU running a While 1 algorithm
25°C 3.3V 2.7
125°C 3.3V 3.0
mA
3.5
CPU running a While 1 algorithm,
with
25°C 3.3V 52*Freq+108 60*Freq+124 µA
(with freq. in
125°C 3.3V 53*Freq+377 48*Freq+1104
GCLKIN as reference
MHz)
CPU running a Fibonacci algorithm
25°C 3.3V 3.3
125°C 3.3V 3.6
3.6
4.1
mA
CPU running a Fibonacci algorithm,
with
25°C 3.3V 66*Freq+108 71*Freq+126 µA
(with freq. in
125°C 3.3V 66*Freq+375 62*Freq+1113
GCLKIN as reference
MHz)
CPU running a CoreMark algorithm
25°C 3.3V 4.5
125°C 3.3V 4.9
5.0
5.4
mA
CPU running a CoreMark algorithm, 25°C 3.3V 90*Freq+109 97*Freq+125 µA
with
(with freq. in
125°C 3.3V 92*Freq+376 89*Freq+1103
GCLKIN as reference
MHz)
IDLE0
IDLE1
IDLE2
Default operating conditions
25°C 3.3V 1.5
125°C 3.3V 1.8
25°C 3.3V 1.0
125°C 3.3V 1.2
25°C 3.3V 0.8
125°C 3.3V 1.0
25°C 3,3V 61.0
125°C 3,3V 294.0
25°C 3,3V 60.0
125°C 3,3V 292.0
1.6
mA
2.4
Default operating conditions
Default operating conditions
1.0
1.8
0.8
1.6
STANDBY (1) XOSC32K running
RTC running at 1kHz
83.0
782.0
82.0
780.0
µA
XOSC32K and RTC stopped
Note:ꢀ
1. Measurements done with VREG.bit.RUNSTDBY = 1.
DS40001882G-page 972
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-12.ꢀCurrent Consumption (Variant D)
Mode
Conditions
Ta
Vcc
Typ.
2.8
Max
3.1
Units
25°C 3.3V
125°C 3.3V
CPU running a While 1 algorithm
mA
3.5
4.1
25°C 3.3V 56*Freq+116 60*Freq+131
125°C 3.3V 57*Freq+395 55*Freq+1232
CPU running a While 1 algorithm, with
GCLKIN as reference
µA (with freq
in MHz)
25°C 3.3V
125°C 3.3V
3.7
4.5
4.1
5.1
CPU running a Fibonacci algorithm
mA
ACTIVE
25°C 3.3V 74*Freq+116 80*Freq+125
125°C 3.3V 75*Freq+397 72*Freq+1231
CPU running a Fibonacci algorithm, with
GCLKIN as reference
µA (with freq
in MHz)
25°C 3.3V
125°C 3.3V
4.2
5.1
4.7
5.9
CPU running a CoreMark algorithm
mA
25°C 3.3V 86*Freq+117 92*Freq+127
125°C 3.3V 88*Freq+399 85*Freq+1230
CPU running a CoreMark algorithm, with
GCLKIN as reference
µA (with freq
in MHz)
25°C 3.3V
125°C 3.3V
25°C 3.3V
125°C 3.3V
25°C 3.3V
125°C 3.3V
25°C 3,3V
125°C 3,3V
25°C 3,3V
125°C 3,3V
1.5
2.0
1.7
2.7
IDLE0
IDLE1
IDLE2
1.0
1.1
mA
1.4
2.1
0.8
0.9
1.1
1.8
61.0
294.0
60.0
292.0
83.0
782.0
82.0
780.0
XOSC32K running RTC running at 1kHz
XOSC32K and RTC stopped
STANDBY (1)
µA
Note:ꢀ
1. Measurements done with VREG.bit.RUNSTDBY = 1.
Table 40-13.ꢀWake-Up Time
Mode
Conditions
TA
Min. Typ. Max. Units
IDLE0
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
OSC8M used as main clock source, Cache disabled
-
-
-
-
4
-
-
-
-
IDLE1
14.9
15.8
20.6
125°C
µs
IDLE2
STANDBY
For Measurement Schematics, refer to Power Supply Schematic.
DS40001882G-page 973
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
40.8
I/O Pin Characteristics
Table 40-14.ꢀNormal I/O Pin Characteristics
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
VIL
Input low-level voltage
VDD=2.7V-3.63V
-
-
-
0.3*VDD
-
V
VIH
VOL
VOH
IOL
Input high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level current
VDD=2.7V-3.63V
0.55*VDD
VDD>2.7V, IOL max.
VDD>2.7V, IOH max.
VDD=2.7V-3V,
-
0.1*VDD 0.2*VDD
0.8*VDD
0.9*VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-1
-
-
mA
PORT.PINCFG.DRVSTR=0
VDD=3V-3.63V,
-
1
-
-
PORT.PINCFG.DRVSTR=0
VDD=2.7V-3V,
-
2.5
-
-
PORT.PINCFG.DRVSTR=1
VDD = 3V-3.63V,
-
3
-
-
PORT.PINCFG.DRVSTR=1
VDD=2.7V-3V,
-
10
-
IOH
Output high-level current
-
PORT.PINCFG.DRVSTR=0
VDD=3V-3.63V,
-
0.7
-
-
PORT.PINCFG.DRVSTR=0
VDD=2.7V-3V,
-
2
-
-
PORT.PINCFG.DRVSTR=1
VDD=3V-3.63V,
-
2
-
-
PORT.PINCFG.DRVSTR=1
Load = 20pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=1
Load = 5pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=0
Load = 20pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=1
Load = 5pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=0
Pull-up resistors disabled
-
7
tRISE
tFALL
ILEAK
Rise time(1)
-
15
-
ns
-
-
15
-
-
Fall time(1)
-
15
-
-
-
15
-
-
Input leakage current
+/-0.015
1
µA
DS40001882G-page 974
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-15.ꢀI2C Pins Characteristics in I2C Configuration
Symbol Parameter
Condition
Min.
Typ. Max.
Units
VIL
Input low-level voltage
VDD = 2.7V-3.63V
VDD = 2.7V-3.63VI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3*VDD V
VIH
Input high-level voltage
0.55*VDD
-
VHYS
VOL
Hysteresis of Schmitt trigger inputs
Output low-level voltage
0.08*VDD
-
VDD> 2.0V
IOL = 3 mA
VDD≤2.0V
-
-
-
0.4
-
-
IOL = 2 mA
-
-
0.2*VDD
CI
Capacitance for each I/O Pin
Output low-level current
-
-
pF
IOL
VOL = 0.4V
Standard, Fast and HS Modes
VOL = 0.4V
Fast Mode +
VOL = 0.6V
-
-
-
mA
3
-
-
-
20
6
-
-
-
fSCL
RP
SCL clock frequency
3.4
MHz
ohms
-
Value of pull-up resistor
fSCL ≤ 100 kHz
fSCL > 100 kHz
-
-
-
-
Table 40-16.ꢀI2C Pin Characteristics in I/O Configuration
Symbol Parameter
RPULL Pull-up - Pull-down resistance
VIL
Conditions
Min.
Typ.
Max.
Units
kΩ
-
20
40
-
60
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
VDD = 2.7V-3.63V
VDD = 2.7V-3.63V
VDD>2.7V, IOL max
VDD>2.7V, IOH max
-
0.3*VDD
-
V
VIH
0.55*VDD
-
-
VOL
VOH
0.1*VDD 0.2*VDD
0.9*VDD
0.8*VDD
-
DS40001882G-page 975
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
Output low-level current
VDD = 2.7V-3V,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-1
-
-
mA
PORT.PINCFG.DRVSTR=0
VDD = 3V-3.63V,
-
1
-
-
PORT.PINCFG.DRVSTR=0
VDD = 2.7V-3V,
-
2.5
-
-
PORT.PINCFG.DRVSTR=1
VDD = 3V-3.63V,
-
3
-
-
PORT.PINCFG.DRVSTR=1
VDD = 2.7V-3V,
-
10
-
IOH
Output high-level current
-
PORT.PINCFG.DRVSTR=0
VDD = 3V-3.63V,
-
0.7
-
-
PORT.PINCFG.DRVSTR=0
VDD = 2.7V-3V,
-
2
-
-
PORT.PINCFG.DRVSTR = 1
VDD = 3V-3.63V,
-
2
-
-
PORT.PINCFG.DRVSTR = 1
load = 20 pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=1
Load = 5 pF, VDD = 3.3V
PORT.PINCFG.DRVSTR=0
load = 20 pF, VDD = 3.3V
PORT.PINCFG.DRVSTR = 1
load = 5 pF, VDD = 3.3V
PORT.PINCFG.DRVSTR = 0
Pull-up resistors disabled
-
7
tRISE
tFALL
ILEAK
Rise time(1)
-
15
-
ns
-
-
15
-
-
Fall time(1)
-
15
-
-
-
15
-
-
Input leakage current
+/-0.015
1
µA
Table 40-17.ꢀPA24/PA25 Pins Characteristics
Symbol Parameter
RPULL Pull-up - Pull-down resistance
VIL
Conditions
Min.
Typ.
Max.
Units
kΩ
-
20
40
-
60
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
VDD = 2.7V-3.63V
VDD = 2.7V-3.63V
VDD>2.7V, IOL max
VDD>2.7V, IOH max
-
0.29*VDD
-
V
VIH
0.55*VDD
-
-
VOL
VOH
0.1*VDD 0.2*VDD
0.9*VDD
0.8*VDD
-
DS40001882G-page 976
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
Output low-level current
VDD = 2.7V-3V,
-
-
-
-
-
-
-
-
-
-
3
mA
VDD=3V-3.63V,
8
IOH
Output high-level current
Rise time(1)
VDD=2.7V-3V,
2
VDD = 3V-3.63V,
7
tRISE
Load = 5pF, VDD = 3.3V
Load = 20pF, VDD = 3.3V
Load = 5pF, VDD = 3.3V
Load = 20pF, VDD = 3.3V
Pull-up resistors disabled
15
ns
tFALL
Fall time(1)
-
-
15
1
ILEAK
Input leakage current
-1
+/-0.015
µA
Notes:ꢀ
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. The I2C pins have faster fall-time in I2C Fast Plus mode (Fm+) and High Speed mode (HS). The fall-time can
be in 7 ns range in Fm+ mode, and in 5 ns range in HS mode.
3. USB pads PA24, PA25 compliant with USB standard in USB mode.
40.9
Analog Characteristics
40.9.1 Power-On Reset (POR) Characteristics
Table 40-18.ꢀPOR Characteristics (Device Variant A)
Symbol Parameters
Conditions
Min. Typ. Max. Unit
VPOT+
VPOT-
Voltage threshold Level on VDDIN rising
Voltage threshold Level on VDDIN falling
1.27 1.44 1.62
0.72 1.07 1.37
V
V
VDD falls at 1V/ms or slower
Table 40-19.ꢀPOR Characteristics (Device Variant B and D)
Symbol Parameters
VPOT+ Voltage threshold Level on VDDIN rising
VPOT- Voltage threshold Level on VDDIN falling
Conditions
VDD falls at 1V/ms or slower
Min. Typ. Max. Unit
1.27 1.45 1.62
0.53 0.99 1.32
V
V
DS40001882G-page 977
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Figure 40-1.ꢀPOR Operating Principle
40.9.2 Brown-Out Detectors (BOD) Characteristics
Table 40-20.ꢀBOD33 Level Value (Device Variant A and B)
Symbol
BOD33.LEVEL
Conditions
Min. Typ. Max.
2.68 2.74
2.51 2.59 2.65
Units
VBOD+
34
34
Hysteresis ON
-
V
VBOD- or VBOD
Hysteresis ON or Hysteresis OFF
Table 40-21.ꢀBOD33 Level Value (Device Variant D)
Symbol
VBOD+
BOD33.LEVEL
Conditions
Hysteresis ON
Min.
-
Typ.
2.69
2.59
Max.
2.76
2.66
Units
34
34
V
VBOD- or VBOD
Hysteresis ON or OFF
2.51
Note:ꢀ Refer to the Memories table NVM User Row Mapping for the BOD33 default value settings.
Table 40-22.ꢀBOD33 Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Step size, between adjacent
values in BOD33.LEVEL
-
34
-
mV
VHYST
VBOD+ - VBOD-
Detection time
Hysteresis ON
35
-
-
170 mV
- µs
(1)
tDET
Time with VDDANA < VTH
necessary to generate a reset
signal
0.9
DS40001882G-page 978
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Current Consumption
Conditions
Min. Typ. Max. Units
IBOD33
IDLE2, Mode CONT
25°C
-40 to 125 -
25°C
-40 to 125 -
25°C
-
33
-
48
µA
53.0
IDLE2, Mode SAMPL
STDBY, Mode SAMPL
-
0.03 0.50
2.3
0.13 0.50
-
-
-40 to 125 -
-
-
1.7
-
(1)
tSTARTUP
Start-up time
1.2
µs
Table 40-23.ꢀBOD33 Characteristics (Device Variant B and D)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
Step size, between adjacent
values in BOD33.LEVEL
-
34
-
mV
VHYST
VBOD+ - VBOD-
Detection time
Hysteresis ON
35
-
-
170 mV
(1)
tDET
Time with VDDANA < VTH
necessary to generate a reset
signal
0.9(1)
-
µs
IBOD33
Current Consumption
IDLE2, Mode CONT
IDLE2, Mode SAMPL
STDBY, Mode SAMPL
25°C
-
33
-
48
µA
-40 to 125 -
25°C
-40 to 125 -
25°C
53.0
-
0.03 0.50
-
3
-
0.13 0.50
-40 to 125 -
-
-
1.7
-
(1)
tSTARTUP
Start-up time
2.2(1)
µs
Note:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
40.9.3 Analog-to-Digital (ADC) Characteristics
Table 40-24.ꢀOperating Conditions (Device Variant A)
Symbol
VDDANA
Res
Parameters
Conditions
Min
2.7
8
Typ
Max
3.6
Unit
V
Power supply voltage
Resolution
-
-
-
-
12
bits
kHz
ksps
fCLK_ADC
ADC Clock frequency
Sampling rate(2)
30
5
2100
300
Single shot (with
VDDANA > 3.0V)(4)
Free running
5
-
-
350
-
Sampling time(2)
250
ns
DS40001882G-page 979
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
Sampling time with DAC as
input(2)
3
-
-
µs
Sampling time with Temp
sens as input(2)
10
10
-
-
-
-
µs
µs
Sampling time with
Bandgap as input(2)
Conversion time(2)
1x Gain
6
1
-
-
-
Cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
VDDANA-0.6
INT1V
Internal 1V reference (2,5)
-
-
1
-
V
V
INTVCC0
Internal ratiometric
reference 0(2)
VDDANA/1.48 -
INTVCC0
Internal ratiometric
2.0V <
VDDANA<3.63V
-1
-
1
%
Voltage Error reference 0(2) error
INTVCC1
Internal ratiometric
reference 1(2)
VDDANA>2.0V
-
VDDANA/2
-
V
INTVCC1
Internal ratiometric
2.0V <
VDDANA<3.63V
-1
-
1
%
Voltage Error reference 1(2) error
Conversion range(2)
Differential mode
-VREF
GAIN
/
-
+VREF/GAIN V
+VREF/GAIN V
Single-ended mode
0
-
-
CSAMPLE
RSAMPLE
Sampling capacitance(2)
3.5
-
-
pF
Input channel source
resistance(2)
-
3.5
kohms
IDD
DC supply current(1)
fCLK_ADC
=
-
1.25
3.9
mA
2.1MHzI(3)
Table 40-25.ꢀOperating Conditions (Device Variant B and D)
Symbol
VDDANA
Res
Parameters
Conditions
Min
2.7
8
Typ
Max
3.6
12
Unit
V
Power supply voltage
Resolution
-
-
-
-
-
-
-
bits
kHz
ksps
fCLK_ADC
ADC Clock frequency
Sampling rate(1)
30
5
2100
300
350
-
Single shot
Free running
5
Sampling time(1)
250
3
ns
µs
Sampling time with DAC as
input(2)
-
Sampling time with Temp
sens as input(2)
10
-
-
µs
DS40001882G-page 980
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
Sampling time with Bandgap
as input(2)
10
-
-
µs
Conversion time(1)
1x Gain
6
1
-
-
-
Cycles
V
VREF
Voltage reference range
(VREFA or VREFB)
VDDANA-0.6
INT1V
Internal 1V reference (2,5)
-
-
1
-
V
V
INTVCC0
Internal ratiometric reference
0(2)
VDDANA/1.48 -
INTVCC0
Internal ratiometric reference 2.0V <
VDDANA<3.63V
-1
-
1
%
Voltage Error 0(2) error
INTVCC1
Internal ratiometric reference VDDANA>2.0V
1(2)
-
VDDANA/2
-
V
INTVCC1
Internal ratiometric reference 2.0V <
-1
-
1
%
Voltage Error 1(2) error
VDDANA<3.63V
Conversion range(1)
Differential mode
-VREF
GAIN
/
-
+VREF/GAIN V
+VREF/GAIN V
Single-ended mode
0
-
-
CSAMPLE
RSAMPLE
Sampling capacitance(2)
3.5
-
-
pF
Input channel source
resistance(2)
-
3.5
kohms
IDD
DC supply current(1)
fCLK_ADC
=
-
1.25
4.7
mA
2.1MHzI(3)
Notes:ꢀ
1. These values are based on characterization. These values are not covered by test limits in production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock.
4. All single-shot measurements are performed with VDDANA > 3.0V (cf. ADC errata).
5. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 40-26.ꢀDifferential Mode : FCLK_ADC = 2.1MHz (Device Variant A)
Symbol
ENOB
TUE
Parameter
Conditions
With gain compensation
1x Gain
Min.
-
Typ.
9.9
Max.
10.1
12.4
6.5
Units
bits
Effective Number Of Bits
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
2.9
1.4
4.6
LSB
LSB
INL
1x Gain
2.2
DNL
1x Gain
+/-0.3 +/-0.5 +/-0.95 LSB
DS40001882G-page 981
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min.
-24
-25
-13
Typ.
-2.5
-1.5
-5
Max.
24
Units
mV
mV
mV
%
GE
Gain Error
Ext. Ref 1x
VREF=VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
25
+13
Gain Accuracy(5)
Offset Error
+/-0.1 +/-0.2 +/-0.45
+/-0.1 +/-0.2 +/-2
%
OE
-10
-2
10
mV
mV
mV
dB
VREF=VDDANA/1.48
VREF = INT1V
1x Gain
-10
0.5
3
15
-10
15
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
64.2
60.4
63.4
-65.0
0.6
70
78.9
62.7
66
FIN = 40kHz
61.1
64.4
-64.0
1
dB
AIN = 95%FSR
dB
THD
Total Harmonic Distortion
Noise RMS
-62.6
2.5
dB
T=25°C
mV
Table 40-27.ꢀDifferential Mode : FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol Parameter
Conditions
Min.
-
Typ.
Max.
10.8
14
Units
bits
ENOB
TUE
INL
Effective Number Of Bits
With gain compensation
1x Gain
10.5
2.9
Total Unadjusted Error
Integral Non Linearity
Differential Non Linearity
Gain Error
1.5
0.9
LSB
LSB
1x Gain
1.3
4
DNL
GE
1x Gain
+/-0.3 +/-0.5
+/-0.95 LSB
Ext. Ref 1x
-15
-56
-36
-
-2.4
-14
15
mV
mV
mV
%
VREF=VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
56
-7
36
Gain Accuracy(5)
Offset Error
+/-0.1
+/-0.7
-
+/-0.04 +/-0.5
%
OE
-8
1.7
8
mV
mV
mV
dB
dB
dB
dB
mV
VREF=VDDANA/1.48
VREF = INT1V
1x Gain
-8
1.6
9
-6
1.8
8
SFDR
SINAD
SNR
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
63.7
56.8
58.8
-71.5
-
69.5
63.7
64.6
-69.5
1
71.5
65.6
66.6
-65.6
2.5
FIN = 40kHz
AIN = 95%FSR
THD
Total Harmonic Distortion
Noise RMS
T=25°C
DS40001882G-page 982
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the
input voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage):
–
3.1.1I.f |VIN| > VREF/4
– VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 -0.05*VDDANA -0.1V
3.1.2I.f |VIN| < VREF/4
– VCM_IN < 1.2*VDDANA - 0.75V
– VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*VREF/GAIN).
Table 40-28.ꢀSingle Ended Mode FCLK_ADC = 2.1MHz (Device Variant A)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
-
Typ.
9.5
Max.
9.8
Units
Bits
ENOB
TUE
INL
Effective Number of Bits
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
Gain Error
-
8.4
14.7
7.5
LSB
LSB
1x gain
1.6
+/-0.5
-10
+/-0.1
2.6
DNL
GE
1x gain
+/-0.6 +/-0.95 LSB
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
1x Gain
0.7
10
mV
%
Gain Accuracy(4)
+/-0.3 +/-0.4
+/-0.01 +/-0.1 +/-0,65
%
OE
Offset Error
-17
63
0.2
65
1
mV
dB
dB
dB
dB
mV
SFDR
SINAD
SNR
THD
-
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
66.5
61
64
-57.9
-
FIN = 40kHz
AIN = 95%FSR
50.7
57.6
-64.4
-
59.5
60
-63
1
T = 25°C
Table 40-29.ꢀSingle Ended Mode FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol Parameter
Conditions
With gain compensation
1x gain
Min.
-
Typ.
9.5
Max.
10.1
40
Units
Bits
ENOB
TUE
INL
Effective Number of Bits
Total Unadjusted Error
Integral Non-Linearity
Differential Non-Linearity
Gain Error
-
7.8
LSB
LSB
1x gain
1.4
2.6
6
DNL
GE
1x gain
+/-0.6
-6.6
+/-0.1
+/-0.7
0.6
+/-0.95 LSB
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
6.6
mV
%
Gain Accuracy(4)
+/-0.37 +/-0.55
+/-0.3
+/-0.01 +/-0.1
%
DS40001882G-page 983
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Ext. Ref. 1x
1x Gain
Min.
-5
Typ.
3.2
Max.
12
Units
mV
dB
OE
Offset Error
SFDR
SINAD
SNR
THD
-
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
61.7
53.9
52.9
-67.6
-
66.6
58.8
59.7
-66.6
1
66.6
60.7
62.7
-63.7
6
FIN = 40kHz
AIN = 95%FSR
dB
dB
dB
T = 25°C
mV
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (VREF/GAIN).
40.9.4 Digital to Analog Converter (DAC) Characteristics
Table 40-30.ꢀOperating Conditions(1)
Symbol
VDDANA
AVREF
Parameters
Conditions
Min. Typ.
Max.
Unit
V
Analog supply voltage
External reference voltage
INT1V(3)
-
2.7
-
3.63
-
1
-
VDDANA-0.6
V
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
Maximum capacitance load
DC supply current(2)
-
0.05
-
VDDANA-0.05
V
-
5
-
-
-
kW
pF
µA
-
-
100
290
IDD
Voltage pump disabled
-
160
Notes:ꢀ
1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 40-31.ꢀClock and Timing (1)
Parameter
Conditions
CLOAD=100pF
RLOAD > 5kΩ
Min.
Typ.
Max.
350
Units
ksps
Conversion rate
Normal mode
-
-
-
-
For ΔDATA=+/-1
1000
DS40001882G-page 984
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Parameter
Conditions
VDDNA > 2.6V
VDDNA < 2.6V
Min.
Typ.
Max.
2.85
10
Units
µs
Startup time
-
-
-
-
µs
Note:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 40-32.ꢀAccuracy Characteristics(1) (Device Variant A)
Symbol
RES
Parameter
Conditions
Min. Typ.
Max.
10
Units
Input resolution
Integral non-linearity
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bits
INL
VREF = Ext 1.0V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
-
1.2
1.5
LSB
1.2
1.5
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
1.4
1.5
1.4
1.5
1.2
2
1.2
2
DNL
Differential non-linearity
+/-1.2
+/-1.1
+-1.3
+/-1.1
+/-1.4
+/-1,5
+/-5
+/-3
+/-1.6
+/-1.5
+/-1.9
+/-1.6
+/-3
+/-3
+/-28
+/-14
LSB
GE
OE
Gain error
Ext. VREF
Ext. VREF
mV
mV
Offset error
-
Table 40-33.ꢀAccuracy Characteristics(1) (Device Variant B and D)
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
RES
Input resolution
-
-
-
-
10
Bits
DS40001882G-page 985
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min. Typ.
Max.
1.5
Units
INL
Integral non-linearity
VREF = Ext 1.0V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.75
0.65
0.85
0.8
LSB
1.5
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
1.5
1.5
0.8
2
0.8
3
DNL
Differential non-linearity
+/-0.4
+/-0.4
+/-0.55
+/-0.3
+/-0.7
+/-0.7
+/-4
+/-1
+/-1
+/-1.0
+/-0.75
+/-3
+/-3
+/-16
+/-13
GE
OE
Gain error
Ext. VREF
Ext. VREF
mV
mV
Offset error
-
+/-1
Note:ꢀ
1. All values measured using a conversion rate of 35ksps.
40.9.5 Analog Comparator Characteristics
Table 40-34.ꢀElectrical and Timing (Device Variant A)
Symbol Parameter
Positive input voltage range
Conditions
Min. Typ. Max.
Units
-
-
0
-
VDDANA
VDDANA
26
V
Negative input voltage range
Offset
0
-
Hysteresis = 0, Fast mode
-26
-43
8
0
mV
mV
mV
mV
ns
Hysteresis = 0, Low power mode
Hysteresis = 1, Fast mode
0
43
Hysteresis
50
40
60
102
Hysteresis = 1, Low power mode
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
14
-
85
Propagation delay
126
Changes for VACM=VDDANA/2
-
225 402
ns
100mV overdrive, Low power mode
tSTARTUP Startup time
Enable to ready delay
Fast mode
-
1
2
µs
Enable to ready delay
Low power mode
-
12
0.8
20
1.6
µs
VSCALE
INL(3)
-
-1.6
LSB
DS40001882G-page 986
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min. Typ. Max.
Units
LSB
LSB
LSB
DNL(3)
-
-
-
-0.95 0.3
-0.2 0.3
-0.89 0.2
0.95
1.04
2
Offset Error (1)(2)
Gain Error (1)(2)
Table 40-35.ꢀElectrical and Timing (Device Variant B and D)
Symbol
Parameter
Conditions
Min. Typ.
Max.
Positive input voltage range
Negative input voltage range
Offset
-
0
-
VDDANA
VDDANA
26
-
0
-
Hysteresis = 0, Fast mode
Hysteresis = 0, Low power mode
Hysteresis = 1, Fast mode
Hysteresis = 1, Low power mode
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-26
-28
8
0
0
28
Hysteresis
50
40
90
102
14
-
75
Propagation delay
180
Changes for VACM=VDDANA/2
-
282
1
534
3
100mV overdrive, Low power mode
tSTARTUP Startup time
Enable to ready delay
Fast mode
-
Enable to ready delay
Low power mode
-
14
23
VSCALE
INL(3)
-
-
-
-
-1.6
0.75
1.6
0.95
1.04
2
DNL(3)
-0.95 0.25
-0.2 0.26
-0.89 0.215
Offset Error (1)(2)
Gain Error (1)(2)
Notes:ꢀ
1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method.
3. Data computed using histogram.
40.9.6 Bandgap and Internal 1.0V Reference Characteristics
Table 40-36.ꢀBandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
Conditions
Min. Typ. Max. Units
BANDGAP Internal 1.1V Bandgap
reference
After calibration at T= 25°C, over [-40°C,
+125°C], Vdd 3.3V
1.06 1.1 1.12
V
Over voltage at 25°C
1.07 1.1 1.12
V
DS40001882G-page 987
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min. Typ. Max. Units
INT1V
Internal 1.0V reference voltage After calibration at T= 25°C, over [-40°C,
0.96 1.00 1.02
V
(1)
+125°C], Vdd 3.3V
Over voltage at 25°C
0.97 1.00 1.02
V
Note:ꢀ
1. These values are simulation based and are not covered by production test limits.
40.10 NVM Characteristics
Table 40-37.ꢀMaximum Operating Frequency (Device Variant A)
VDD range
NVM Wait States
Maximum Operating Frequency
Units
2.7V to 3.63V
0
1
24
40
MHz
Table 40-38.ꢀMaximum Operating Frequency (Device Variant B and D)
VDD range
NVM Wait States
Maximum Operating Frequency
Units
2.7V to 3.63V
0
1
24
48
MHz
Note:ꢀ With on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 40-39.ꢀFlash Endurance and Data Retention (Device Variant A)
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
Years
Years
Years
Cycles
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 125°C
10
50
-
-
-
-
20
100
>100
-
25
10K
Table 40-40.ꢀFlash Endurance and Data Retention (Device Variant B and D)
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
Years
Years
Years
Cycles
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 125°C
10
50
-
-
-
-
20
100
>100
-
25
25k
Note:ꢀ
1. An endurance cycle is a write and an erase operation.
Table 40-41.ꢀEEPROM Emulation(1) Endurance and Data Retention (Device Variant A)
Symbol
Parameter
Conditions
Min. Typ. Max. Units
10 50 Years
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
-
DS40001882G-page 988
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min. Typ. Max. Units
RetEEPROM10k
CycEEPROM
Retention after up to 10k
Cycling Endurance(2)
Average ambient 55°C
-40°C < Ta < 125°C
20
100
-
-
-
Years
40K
Cycles
Table 40-42.ꢀEEPROM Emulation(1) Endurance and Data Retention (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
10
Typ. Max. Units
RetEEPROM100k
RetEEPROM10k
CycEEPROM
Retention after up to 100k
Retention after up to 10k
Cycling Endurance(2)
Average ambient 55°C
Average ambient 55°C
-40°C < Ta < 125°C
50
100
-
-
-
-
Years
Years
Cycles
20
100k
Notes:ꢀ
1. The EEPROM emulation is a software emulation described in the Application Note AT03265: SAM
D10/D11/D20/D21/R/L/C EEPROM Emulator (EEPROM) Service.
2. An endurance cycle is a write and an erase operation.
Table 40-43.ꢀNVM Characteristics
Symbol
tFPP
Parameter
Conditions
Min.
Typ.
Max.
2.5
6
Units
ms
Page programming time
Row erase time
-
-
-
-
-
-
-
-
-
tFRE
ms
tFCE
DSU chip erase time (CHIP_ERASE)
240
ms
40.11 Oscillator Characteristics
40.11.1 Crystal Oscillator (XOSC) Characteristics
Table 40-44.ꢀDigital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max
32
Units
MHz
fCPXIN
XIN clock frequency
digital mode
-
-
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
DS40001882G-page 989
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-45.ꢀCrystal Oscillator Characteristics
Symbol Parameter Conditions
Min. Typ. Max. Units
fOUT
Crystal oscillator frequency
-
0.4
-
32
MHz
Ω
ESR
Crystal Equivalent Series
Resistance - SF = 3
f = 0.455 MHz, CL = 100pF, XOSC.GAIN = 0
f = 2MHz, CL=20 pF XOSC.GAIN=0
f = 4MHz, CL=20 pF XOSC.GAIN=1
f = 8MHz, CL=20 pF XOSC.GAIN=2
f = 16MHz, CL=20 pF XOSC.GAIN=3
f = 32MHz, CL=18 pF XOSC,GAIN=4
-
-
-
-
-
-
-
-
-
-
5.6K
330
240
105
60
-
-
-
-
-
55
CXIN
Parasitic load capacitor
Current consumption
5.9
3.2
65
52
117
74
226
128
502
-
pF
pF
uA
CXOUT
IXOSC
-
-
f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC off -
f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC on -
f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC off -
f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC on -
f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC off -
f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC on -
240
240
309
281
435
356
748
f = 16MHz, CL=20 pF XOSC.GAIN=3, AGC
off
-
-
-
-
-
-
-
-
-
f = 16MHz, CL=20 pF XOSC.GAIN=3, AGC
on
307
627
f = 32MHz, CL=18 pF XOSC.GAIN=4, AGC
off
1622 2344
f = 32MHz, CL=18 pF XOSC.GAIN=4, AGC
on
615
1422
tSTART
Startup time
f = 2MHz, CL=20 pF XOSC,GAIN=0,
ESR=600 Ohms
15.6K 51.0K Cycles
6.3K 20.1K
f = 4MHz, CL=20 pF XOSC,GAIN=1,
ESR=100 Ohms
f = 8MHz, CL=20 pF XOSC,GAIN=2,
ESR=35 Ohms
6.2K 20.3K
f = 16MHz, CL=20 pF XOSC,GAIN=3,
ESR=25 Ohms
7.7K 21.2K
f = 32MHz, CL=18 pF XOSC,GAIN=4,
ESR=40 Ohms
6.0K 14.2K
DS40001882G-page 990
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Figure 40-2.ꢀOscillator Connection
40.11.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 40-46.ꢀDigital Clock Characteristics
Symbol
fCPXIN32
-
Parameter
Conditions
digital mode
digital mode
Min.
Typ.
32.768
50
Max
Units
kHz
%
XIN32 clock frequency
XIN32 clock duty cycle
-
-
-
-
Crystal Oscillator Characteristics
The figure, Oscillator Connection and the equation in Crystal Oscillator Characteristics also applies to the 32 kHz
oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the
range given in the table. The exact value of CL can be found in the crystal data sheet.
Table 40-47.ꢀ32 kHz Crystal Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ.
Max Units
fOUT
Crystal oscillator frequency
-
-
32768 - Hz
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5 pF -
28K
31K cycles
DS40001882G-page 991
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max Units
CL
Crystal load capacitance
-
-
-
-
-
-
-
-
12.5 pF
CSHUNT Crystal shunt capacitance
-
0.1
3.1
3.3
1.2
-
-
-
-
pF
pF
pF
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
2.5 µA
141 kΩ
ESR
Crystal equivalent series resistance
CL=12.5pF
f=32.768kHz
Safety Factor = 3
Table 40-48.ꢀ32 kHz Crystal Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
Conditions
Min. Typ.
Max Units
fOUT
Crystal oscillator frequency
-
-
32768 -
Hz
tSTARTUP Startup time
ESRXTAL = 39.9 kW, CL = 12.5 pF -
28K
-
31K cycles
12.5 pF
CL
Crystal load capacitance
-
-
-
-
-
-
-
CSHUNT Crystal shunt capacitance
-
0.1
3.2
3.7
1.2
-
-
-
-
-
-
-
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
2.2 µA
100 kΩ
ESR
Crystal equivalent series resistance
CL=12.5pF
f=32.768kHz
Safety Factor = 3
40.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 40-49.ꢀDFLL48M Characteristics - Open Loop Mode (Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
fOUT
IDFLL
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 45
DFLLVAL.FINE = 512
48
49
MHz
over [-40°, +125°]C, over [2.7, 3.6]V
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 46.5 48
DFLLVAL.FINE = 512
49
MHz
at 25°C, over [2.7, 3.6]V
Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-
-
403 457 µA
tSTARTUP Startup time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
8
12
µs
fOUT within 90 % of final value
DS40001882G-page 992
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-50.ꢀDFLL48M Characteristics - Open Loop Mode (Device Variant B and D)
Symbol Parameter Conditions
Min. Typ. Max. Units
fOUT
fOUT
fOUT
IDFLL
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 44.75 48
DFLLVAL.FINE = 512
49
49
49
MHz
MHz
MHz
over [-10°, +125°]C, over [2.7, 3.6]V
Output frequency
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 43.5 48
DFLLVAL.FINE = 512
over [-40°, +125°]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL 45.5 48
DFLLVAL.FINE = 512
at 25°C, over [2.7, 3.6]V
Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
403 457 µA
tSTARTUP Startup time
DFLLVAL.COARSE = DFLL48M COARSE CAL -
DFLLVAL.FINE = 512
8
12
µs
fOUT within 90 % of final value
Table 40-51.ꢀDFLL48M Characteristics - Close Loop Mode (Device Variant A)
Symbol Parameter Conditions
Min. Typ.
47.76 48
Max. Units
48.24 MHz
fOUT
Average Output frequency fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
fREF
Reference frequency
Cycle to Cycle jitter
-
0.732 32.768 33
kHz
Jitter
fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
-
-
0.42 ns
IDFLL
Power consumption on
VDDIN
fREF = XTAL, 32 .768kHz, 100ppm
-
-
403
350
457
µA
tLOCK
Lock time
fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
1500 µs
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
DS40001882G-page 993
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-52.ꢀDFLL48M Characteristics - Close Loop Mode (Device Variant B and D)
Symbol Parameter
Conditions
Min. Typ.
Max. Units
fOUT
Average Output frequency fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
47.76 48
48.24 MHz
fREF
Reference frequency
Cycle to Cycle jitter
-
0.732 32.768 33
kHz
Jitter
fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
-
-
0.42 ns
IDFLL
Power consumption on
VDDIN
fREF = XTAL, 32 .768kHz, 100ppm
-
-
403
350
457
µA
tLOCK
Lock time
fREF = XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
1500 µs
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Note:ꢀ All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop
mode with an external OSC reference or the internal OSC8M.
40.11.4 32.768 kHz Internal Oscillator (OSC32K) Characteristics
Table 40-53.ꢀ32 kHz RC Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ.
Max
Units
fOUT
Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
28.508 32.768 35.389 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
31.621 32.768 33.423
31.457 32.768 34.079
Calibrated against a 32.768kHz
reference at 25°C, over [2.7, 3.63]V
IOSC32K Current consumption -
tSTARTUP Startup time
-
-
-
0.79
1
3.7
2
uA
-
-
cycles
%
Duty
Duty Cycle
50
-
DS40001882G-page 994
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-54.ꢀ32 kHz RC Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
Conditions
Min.
Typ.
Max
Units
fOUT
Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
26.214 32.768 39.321 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
32.113 32.768 33.423 kHz
31.457 32.768 34.079 kHz
Calibrated against a 32.768kHz
reference at 25°C, over [2.7, 3.63]V
IOSC32K Current consumption -
tSTARTUP Startup time
-
-
-
0.67
1
5
2
-
uA
-
-
cycles
%
Duty
Duty Cycle
50
40.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 40-55.ꢀUltra Low Power Internal 32 kHz RC Oscillator Electrical Characteristics
Symbol Parameter
Conditions
Min.
Typ.
Max
Units
fOUT
Output frequency Calibrated against a 32.768kHz
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
24.248 32.768 40.96 kHz
-
-
-
-
Calibrated against a 32.768kHz reference at 25°C, at 30.474 32.768 35.061 kHz
VDD=3.3V
Calibrated against a 32.768kHz
30.146 32.768 35.389 kHz
reference at 25°C, over [2.7, 3.63]V
Duty
Duty Cycle
-
-
50
-
%
Notes:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
40.11.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 40-56.ꢀInternal RC Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max Units
fOUT
Output frequency
Calibrated against a 8MHz reference at 25°C, over [-10, 7.84 8
+70]C, over [2.7, 3.6]V
8.16 MHz
Calibrated against a 8MHz reference at 25°C, over [-10, 7.8
+125]C, over [2.7, 3.6]V
8
8.2
Calibrated against a 8MHz reference at 25°C, over [-40, 7.7
+125]C, over [2.7, 3.6]V
8
8.3
Calibrated against a 8MHz reference at 25°C, over [2.7,
3.6]V
7.88 8
8.12
DS40001882G-page 995
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min. Typ. Max Units
IOSC8M Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M
enabled at 8MHz (FRANGE=1, PRESC=0)
-
64
100 uA
tSTARTUP Startup time
Duty Duty Cycle
-
-
-
-
2.4 3.9 us
50
-
%
Table 40-57.ꢀInternal RC Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
fOUT Output frequency
Conditions
Min. Typ. Max Units
Calibrated against a 8MHz reference at 25°C, over [-10, 7.84 8
+70]C, over [2.7, 3.6]V
8.16 MHz
Calibrated against a 8MHz reference at 25°C, over [-10, 7.8
+125]C, over [2.7, 3.6]V
8
8.2
Calibrated against a 8MHz reference at 25°C, over [-40, 7.66 8
+125]C, over [2.7, 3.6]V
8.34
Calibrated against a 8MHz reference at 25°C, over [2.7,
3.6]V
7.88 8
8.12
IOSC8M Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M
enabled at 8MHz (FRANGE=1, PRESC=0)
-
64
96
uA
tSTARTUP Startup time
Duty Duty Cycle
-
-
-
-
2.4 3.9 us
50
-
%
40.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 40-58.ꢀFDPLL96M Characteristics(1) (Device Variant A)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
-
32
48
-
-
2000 kHz
fOUT
-
-
64
700
1200
4
MHz
µA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 64 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 64 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 64 MHz
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 64 MHz
500
900
1.5
2.8
1.3
3.3
1.3
-
JP
Period jitter peak
-
%
-
7
-
5
-
8
tLOCK
Lock Time
-
2
ms
µs
%
After startup, time to get lock signal
fIN= 2MHz, fOUT= 64MHz
-
25
50
50
60
Duty
Duty cycle
-
40
DS40001882G-page 996
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-59.ꢀFDPLL96M Characteristics(1) (Device Variant B and D)
Symbol
fIN
Parameter
Conditions
Min. Typ. Max. Units
Input frequency
Output frequency
Current consumption
-
32
48
-
-
2000 kHz
fOUT
-
-
96
740
1262
4
MHz
µA
IFDPLL96M
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 32 kHz, fOUT= 48 MHz
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 48 MHz
fIN= 2 MHz, fOUT= 96 MHz
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
500
900
2.1
3.8
2.2
5
-
JP
Period jitter peak
-
%
-
11
4
-
-
12
2
tLOCK
Lock Time
Duty cycle
-
1.2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
-
25
50
50
60
µs
%
Duty
40
Note:ꢀ
1. All values have been characterized with FILTSEL[1/0] as default value.
40.12 PTC Characteristics
The values given in the Power Consumption table below are measured values of power consumption, which are valid
under the following conditions:
Operating conditions
VDD = 3.3 V
Clocks
OSC8M used as main clock source, running undivided at 8 MHz.
CPU is running on Flash with '0' wait states, at 8 MHz.
PTC running at 4 MHz.
PTC configuration
Mutual-Capacitance mode.
One-touch channel.
System configuration
Standby Sleep mode enabled.
RTC running on OSCULP32K: Used to define the PTC scan rate through the event system.
Drift Calibration disabled: No interrupts, PTC scans are performed in Standby mode.
Drift Calibration enabled: RTC interrupts (wake-up) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
DS40001882G-page 997
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-60.ꢀPower Consumption (1)(2) (Variant A)
PTC scan
rate (msec)
Symbol Parameters
Drift Calibration
Oversamples Ta
Typ. Max. Units
(2)
IDD
Current Consumption Disabled
10
4
Max. 125°C 72
Typ. 25°C
1151 µA
16
4
84
65
68
64
65
64
64
77
88
67
70
66
67
65
66
1167
1148
1154
1148
1151
1151
1150
1152
1181
1156
1160
1154
1158
1155
1157
50
16
4
100
200
10
16
4
16
4
Enabled
16
4
50
16
4
100
200
16
4
16
DS40001882G-page 998
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-61.ꢀPower Consumption (1)(2) (Variant B and D)
PTC scan
rate (msec)
Symbol Parameters
Drift Calibration
Oversamples Ta
Typ. Max. Units
(2)
IDD
Current Consumption Disabled
10
4
Max. 125°C 66
Typ. 25°C
791 µA
16
4
75
61
63
61
62
60
61
71
80
63
65
62
63
62
63
803
787
791
788
790
788
789
802
813
792
795
791
793
790
791
50
16
4
100
200
10
16
4
16
4
Enabled
16
4
50
16
4
100
200
16
4
16
Notes:ꢀ
1. These are based on characterization.
2. On this table, the LDO voltage regulator is enabled in Standby mode (SYSCTRL.VREG.RUNSTDBY = 1).
DS40001882G-page 999
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.
SAM DA1 Electrical Characteristics
41.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
41.2
Thermal Considerations
41.2.1 Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 41-1.ꢀThermal Resistance Data
Package Type
32-pin QFN
48-pin QFN
64-pin QFN
32-pin TQFP
48-pin TQFP
64-pin TQFP
θJA
θJC
40.9°C/W
32.0°C/W
32.5°C/W
64.7°C/W
63.6°C/W
60.9°C/W
15.2°C/W
10.9°C/W
10.7°C/W
23.1°C/W
12.2°C/W
12.2°C/W
41.2.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. TJ = TA + (PD x θJA)
2. TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
41.3
Absolute Maximum Ratings
Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DS40001882G-page 1000
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-2.ꢀAbsolute Maximum Ratings
Symbol
VDD
Description
Min.
Max.
3.8
Units
V
Power supply voltage
0
IVDD
Current into a VDD pin
Current out of a GND pin
Pin voltage with respect to GND and VDD
Storage temperature
-
92(1)
mA
mA
V
IGND
-
130(1)
VDD+0.6V
150
VPIN
GND-0.6V
-60
Tstorage
°C
1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of
GPIOs as shown in the table below. Also note that each VDD/GND pair is connected to two clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent
performance degradation or malfunctioning.
CAUTION
Handle the device following best practice ESD protection rules: Be aware that the human body can
accumulate charges large enough to impair functionality or destroy the device.
In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12.
NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that
are mandatory for correct device behavior.
CAUTION
Related Links
7.2.4 GPIO Clusters
7.2.4 GPIO Clusters
41.4
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 105°C, unless
otherwise specified and are valid for a junction temperature up to TJ = 125°C. Refer to Power Supply and Start-Up
Considerations.
Table 41-3.ꢀSupply Characteristics
Voltage
Conditions
Symbol
Min.
Max.
Unit
VDDIO
VDDIN
Full Voltage Range
2.7
3.63
V
VDDANA
Table 41-4.ꢀSupply Rates
Conditions
Fall Rate Rise Rate
Symbol
Max.
Max.
Unit
VDDIO
, VDDIN
DC supply peripheral I/Os, internal regulator and analog supply voltage
0.05
0.1
V/μs
, VDDANA
Related Links
8. Power Supply and Start-Up Considerations
DS40001882G-page 1001
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.5
Maximum Clock Frequencies
Table 41-5.ꢀMaximum GCLK Generator Output Frequencies
Description
Conditions
Symbol
Max.
Unit
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
Undivided
96
MHz
fGCLKGEN2
GCLK Generator Output Frequency
fGCLKGEN3
fGCLKGEN4
Divided
48
MHz
fGCLKGEN5
Table 41-6.ꢀMaximum Peripheral Clock Frequencies
Description
CPU clock frequency
Symbol
fCPU
Max.
48
48
48
48
48
33
2
Unit
MHz
MHz
MHz
MHz
MHz
kHz
AHB clock frequency
fAHB
APBA clock frequency
fAPBA
APBB clock frequency
fAPBB
APBC clock frequency
fAPBC
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
WDT input clock frequency
fGCLK_DFLL48M_REF
fGCLK_DPLL
MHz
kHz
fGCLK_DPLL_32K
32
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
fGCLK_WDT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RTC input clock frequency
fGCLK_RTC
EIC input clock frequency
fGCLK_EIC
USB input clock frequency
fGCLK_USB
EVSYS channel 0 input clock frequency
EVSYS channel 1 input clock frequency
EVSYS channel 2 input clock frequency
EVSYS channel 3 input clock frequency
EVSYS channel 4 input clock frequency
EVSYS channel 5 input clock frequency
EVSYS channel 6 input clock frequency
EVSYS channel 7 input clock frequency
EVSYS channel 8 input clock frequency
EVSYS channel 9 input clock frequency
EVSYS channel 10 input clock frequency
EVSYS channel 11 input clock frequency
Common SERCOM slow input clock frequency
fGCLK_EVSYS_CHANNEL_0
fGCLK_EVSYS_CHANNEL_1
fGCLK_EVSYS_CHANNEL_2
fGCLK_EVSYS_CHANNEL_3
fGCLK_EVSYS_CHANNEL_4
fGCLK_EVSYS_CHANNEL_5
fGCLK_EVSYS_CHANNEL_6
fGCLK_EVSYS_CHANNEL_7
fGCLK_EVSYS_CHANNEL_8
fGCLK_EVSYS_CHANNEL_9
fGCLK_EVSYS_CHANNEL_10
fGCLK_EVSYS_CHANNEL_11
fGCLK_SERCOMx_SLOW
DS40001882G-page 1002
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Description
Symbol
fGCLK_SERCOM0_CORE
fGCLK_SERCOM1_CORE
fGCLK_SERCOM2_CORE
fGCLK_SERCOM3_CORE
fGCLK_SERCOM4_CORE
fGCLK_SERCOM5_CORE
fGCLK_TCC0, GCLK_TCC1
fGCLK_TCC2, GCLK_TC3
fGCLK_TC4, GCLK_TC5
fGCLK_TC6, GCLK_TC7
fGCLK_ADC
Max.
48
48
48
48
48
48
96
48
96
48
48
48
64
48
48
13
13
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
SERCOM0 input clock frequency
SERCOM1 input clock frequency
SERCOM2 input clock frequency
SERCOM3 input clock frequency
SERCOM4 input clock frequency
SERCOM5 input clock frequency
TCC0, TCC1 input clock frequency
TCC2,TC3 input clock frequency
TC4, TC5 input clock frequency
TC6,TC7 input clock frequency
ADC input clock frequency
AC digital input clock frequency
AC analog input clock frequency
DAC input clock frequency
fGCLK_AC_DIG
fGCLK_AC_ANA
fGCLK_DAC
MHz
MHz
MHz
MHz
PTC input clock frequency
fGCLK_PTC
I2S serial 0 input clock frequency
I2S serial 1 input clock frequency
fGCLK_I2S_0
fGCLK_I2S_1
41.6
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
– VVDDIN = 2.7V, CPU is running on Flash with 1 wait state
•
•
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal
– DFLL48M using XOSC32K as reference and running at 48ꢀMHz
Clocks
•
– DFLL48M used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
•
•
•
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
DS40001882G-page 1003
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
CPU is running on flash with 1 wait states
Cache enabled
BOD33 disabled
Table 41-7.ꢀCurrent Consumption
Mode
Conditions
TA
VCC
Typ.
3.32
3.57
Max.
3.63
3.98
Unit
25°C 3.3V
105°C 3.3V
CPU running a While(1) algorithm
mA
64 × Freq +
110
70 × Freq +
131
25°C 3.3V
105°C 3.3V
CPU running a While(1) algorithm,
with GCLKIN as reference
μA (with freq
in MHz)
65 × Freq +
342
65 × Freq +
764
25°C 3.3V
105°C 3.3V
4.03
4.29
4.35
4.76
CPU running a Fibonacci algorithm
mA
79 × Freq +
110
85 × Freq +
133
ACTIVE
25°C 3.3V
105°C 3.3V
CPU running a Fibonacci algorithm,
with GCLKIN as reference
μA (with freq
in MHz)
80 × Freq +
346
81 × Freq +
771
25°C 3.3V
105°C 3.3V
5.08
5.41
5.63
5.95
CPU running a CoreMark algorithm
mA
101 × Freq +
113
110 × Freq +
132
25°C 3.3V
105°C 3.3V
CPU running a CoreMark algorithm,
with GCLKIN as reference
μA (with freq
in MHz)
103 × Freq +
347
104 × Freq +
748
25°C 3.3V
105°C 3.3V
25°C 3.3V
105°C 3.3V
25°C 3.3V
105°C 3.3V
25°C 3.3V
70°C 3.3V
105°C 3.3V
25°C 3.3V
70°C 3.3V
105°C 3.3V
2.24
2.49
1.69
1,91
1.23
1.44
4.2
2.41
2.92
1.82
2.33
1.32
1.85
12.8
100.0
627
IDLE0
IDLE1
IDLE2
Default operating conditions
Default operating conditions
Default operating conditions
mA
XOSC32K running
RTC running at 1kHz
26.7
146
3.1
STANDBY
(Device
Variant A / Die rev. E)
μA
12.2
100.0
624
XOSC32K and RTC stopped
25.6
145
DS40001882G-page 1004
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Mode
Conditions
TA
VCC
Typ.
4.6
Max.
15.0
96
Unit
25°C 3.3V
70°C 3.3V
105°C 3.3V
25°C 3.3V
70°C 3.3V
105°C 3.3V
25°C 3.3V
70°C 3.3V
105°C 3.3V
25°C 3.3V
70°C 3.3V
105°C 3.3V
XOSC32K running
23
RTC running at 1kHz
STANDBY(1)
(Device Variant B / Die rev. F)
95.0
3.4
390.0
14.0
95
μA
XOSC32K and RTC stopped
22
94.0
61.0
87
388.0
72.0
176
XOSC32K running
RTC running at 1kHz
STANDBY(2)
(Device Variant B / Die rev. F)
174.0
60.0
86
452.0
71.0
175
μA
XOSC32K and RTC stopped
173.0
450.0
1. Measurements done with SYSCTRL.VREG.RUNSTDBY=0 (low power configuration).
2. Measurements done with SYSCTRL.VREG.RUNSTDBY=1 (normal configuration).
Table 41-8.ꢀWake-up Time(1)
Mode
IDLE0
TA
Typ.
2.3
Unit
IDLE1
21.1
22.0
29.6
2.3
25°C
μs
IDLE2
STANDBY
IDLE0
IDLE1
22.9
23.8
29.8
105°C
μs
IDLE2
STANDBY
1. OSC8M used as main clock source, cache disabled.
DS40001882G-page 1005
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-1.ꢀMeasurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
41.7
Peripheral Power Consumption
41.7.1 All peripheral except USB
Default conditions, except where noted:
•
Operating conditions
– VVDDIN = 3.3ꢀV
•
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal
– OSC8M at 8MHz
•
Clocks
– OSC8M used as main clock source
– CPU, AHB and APBn clocks undivided
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
•
•
The following peripheral clocks running: PM, SYSCTRL
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU in IDLE0 mode
•
•
•
•
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Operating mode for each peripheral in turn:
•
•
Configure and enable the peripheral GCLK (When relevant, see conditions)
Unmask the peripheral clock
DS40001882G-page 1006
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
•
•
•
•
Enable the peripheral (when relevant)
Set CPU in IDLE0 mode
Measurement Iperiph
Wake-up CPU via EIC (async: level detection, filtering disabled)
Disable the peripheral (when relevant)
Mask the peripheral clock
Disable the peripheral GCLK (when relevant, see conditions)
Each peripheral power consumption provided in table x.y is the value (Iperiph - Idefault), using the same measurement
method as for global power consumption measurement
Table 41-9.ꢀTypical Peripheral Current Consumption
Peripheral
RTC
Conditions
Typ.
7.4
Unit
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
fGCLK_RTC = 32kHz, 32bit counter mode
fGCLK_WDT = 32kHz, normal mode with EW
Both fGCLK = 8MHz, Enable both COMP
fGCLK = 8MHz, Enable + COUNTER in 8bit mode
fGCLK = 8MHz, Enable + COUNTER
fGCLK = 8MHz, Enable + COUNTER
fGCLK = 8MHz, Enable + COUNTER
fGCLK = 8MHz, Enable
WDT
5.5
AC
31.3
50
TCx(1)
TCC2
95.5
167.5
180.3
69.7
29.2
64.6
65.5
26.4
399.5
TCC1
TCC0
SERCOMx.I2CM(2)
SERCOMx.I2CS
SERCOMx.SPI
SERCOMx.USART
I2S(3)
fGCLK = 8MHz, Enable
fGCLK = 8MHz, Enable
fGCLK = 8MHz, Enable
fGCLK_I2S_0 = 12.288MHz with source FDPLL with fFDPLL = 49.152MHz
RAM to RAM transfer
DMAC(4)
1. All TCs from 4 to 7 share the same power consumption values.
2. All SERCOMs from 0 to 5 share the same power consumption values.
3. The value includes the power consumption of the FDPLL.
4. The value includes the power consumption of the R/W access to the RAM.
41.7.2 USB Peripheral Power Consumption
Default conditions, except where noted:
•
•
•
Operating conditions
– VVDDIN = 3.3ꢀV
Oscillators
– XOSC32K (32ꢀkHz crystal oscillator) running with external 32kHz crystal in USB Host mode
Clocks
– USB Device mode: DFLL48M in USB recovery mode (Crystal less)
– USB Host mode: DFLL48M in closed loop with XOSC32K (32ꢀkHz crystal oscillator) running with external
32kHz crystal
– CPU, AHB and APBn clocks undivided
•
•
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
I/Os are inactive with internal pull-up
DS40001882G-page 1007
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
CPU in IDLE0 mode
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Measurements do not include consumption of clock source (ex: DFLL48M or FDPLL96M) and CPU. However no
CPU activity is required during all states (Suspend, IDLE, Data transfer).
Measurements have been done with an USB cable of 1.5m.
For USB Device mode, measurements include the maximum consumption (200μA) through pull-up resistor on the D+
line for USB attach. This value depends on USB Host characteristic.
Operating modes:
•
Run the USB Device/Host states in regards of the Universal Serial Bus (USB) v2.0 standard.
USB power consumption is provided in the following tables.
Table 41-10.ꢀTypical USB Device Full Speed mode Current Consumption
USB Device state
Conditions
Typ. Units
201 μA
Suspend
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
Suspend
IDLE
GCLK_USB is on.
USB bus in suspend mode.
0.83 mA
1.17 mA
2.17 mA
10.3 mA
Start Of Frame is running.
No packet transferred.
Active OUT
Active IN
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
Start Of Frame is running.
Bulk IN on 100% bandwidth.
Table 41-11.ꢀTypical USB Host Full Speed mode Current Consumption
USB Device state
Conditions
Typ. Units
Wait connection
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus not connected.
0.10 μA
Wait connection
Suspend
GCLK_USB is on.
USB bus not connected.
0.19 mA
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
201
μA
Suspend
GCLK_USB is on.
USB bus in suspend mode.
0.83 mA
1.17 mA
2.17 mA
10.3 mA
IDLE
Start Of Frame is running.
No packet transferred.
Active OUT
Active IN
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
Start Of Frame is running.
Bulk IN on 100% bandwidth.
DS40001882G-page 1008
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.8
I/O Pin Characteristics
41.8.1 Normal I/O Pins
Table 41-12.ꢀNormal I/O Pins Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Pull-up - Pull-down
resistance
All pins excepted PA24, PA25
RPULL
20
40
60
kΩ
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
VDD = 2.7V-3.63V
VDD = 2.7V-3.63V
VDD > 2.7V, IOL maxI
VDD > 2.7V, IOH maxII
VIL
VIH
-
-
-
0.3 × VDD
-
0.55 × VDD
-
V
VOL
VOH
0.1 × VDD 0.2 × VDD
0.8 × VDD 0.9 × VDD
-
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
2.5
3
Output low-level current
IOL
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
10
0.70
2
mA
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
Output high-level current
IOH
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
2
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
-
7
PORT.PINCFG.DRVSTR = 0load = 5pF, VDD = 3.3V
-
15
15
15
15
1
Rise time(1)
tRISE
ns
PORT.PINCFG.DRVSTR = 1load = 20pF, VDD
3.3V
=
-
-
PORT.PINCFG.DRVSTR = 0load = 5pF, VDD = 3.3V
-
-
Fall time(1)
tFALL
ns
PORT.PINCFG.DRVSTR = 1load = 20pF, VDD
3.3V
=
-
-
Input leakage current
Pull-up resistors disabled
ILEAK
–1
±0.015
μA
Note:ꢀ These values are based on simulation. These values are not covered by test limits in production or
characterization.
41.8.2 I2C Pins
Refer to the SERCOM I2C Pins section to get the list of I2C pins.
DS40001882G-page 1009
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-13.ꢀI2C Pins Characteristics in I2C Configuration
Parameter
Condition
Symbol
VIL
Min.
-
Typ.
Max.
Unit
Input low-level voltage
Input high-level voltage
Hysteresis of Schmitt trigger inputs
VDD = 2.7V-3.63V
VDD = 2.7V-3.63V
-
-
-
0.3 × VDD
V
VIH
0.55 × VDD
0.08 × VDD
-
-
VHYS
VDD > 2.0V,
IOL = 3mA
-
-
-
-
0.4
Output low-level voltage
VOL
VDD ≤ 2.0V
,
0.2 × VDD
IOL = 2mA
VOL = 0.4V
Standard, Fast and HS Modes
3
Output low-level current
SCL clock frequency
VOL = 0.4V
Fast Mode +
IOL
mA
20
-
-
VOL = 0.6V
6
-
-
-
-
fSCL
3.4
MHz
I2C pins timing characteristics can be found in the SERCOM in I2C Mode Timing section.
Table 41-14.ꢀ I2C Pins Characteristics in I/O Configuration
Parameter
Conditions
Symbol
RPULL
VIL
Min.
Typ.
Max.
Unit
Pull-up - Pull-down resistance
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
20
40
60
kΩ
VDD = 2.7V-3.63V
VDD = 2.7V-3.63V
VDD > 2.7V, IOL max
VDD > 2.7V, IOH max
-
0.55 × VDD
-
-
0.3 × VDD
VIH
-
-
V
VOL
0.1 × VDD
0.9 × VDD
0.2 × VDD
-
VOH
0.8*VDD
DS40001882G-page 1010
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
-
-
1
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
3
Output low-level current
IOL
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=1
10
0.70
2
mA
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=0
Output high-level current
IOH
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
2
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=1
7
load = 20pF,
VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=1
Rise time
tRISE
ns
load = 5pF, VDD = 3.3V
15
15
PORT.PINCFG.
DRVSTR=0
load = 20pF,
VDD = 3.3V
PORT.PINCFG.
DRVSTR=1
Fall time
tFALL
ns
load = 5pF, VDD = 3.3V
15
1
PORT.PINCFG.
DRVSTR=0
Input leakage current
Pull-up resistors disabled
ILEAK
-1
0.015
μA
DS40001882G-page 1011
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Related Links
7.2.3 SERCOM I2C Pins
37.16.3 SERCOM in I2C Mode Timing
41.8.3 USB Pins
Table 41-15.ꢀ USB Pins Characteristics in I/O Configuration
Parameter
Conditions
Symbol
RPULL
VIL
Min.
Typ.
Max.
Unit
Pull-up - Pull-down resistance
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
20
40
60
kΩ
VDD = 2.7V-3.63V
-
-
0.29 × VDD
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
V
VDD > 2.7V, IOL max
VDD > 2.7V, IOH max
VDD = 2.7V-3V
VOL
-
0.1 × VDD
0.2 × VDD
VOH
0.8 × VDD
0.9 × VDD
-
-
-
-
-
-
-
-
-
3
9
2
7
Output low-level current
Output high-level current
Rise time
IOL
VDD = 3V-3.63V
mA
VDD = 2.7V-3V
IOH
VDD = 3V-3.63V
load = 5pF, VDD = 3.3V
load = 20pF, VDD = 3.3V
load = 5pF, VDD = 3.3V
load = 20pF, VDD = 3.3V
Pull-up resistors disabled
tRISE
15
ns
Fall time
tFALL
ILEAK
15
1
Input leakage current
–1
±0.015
μA
41.8.4 XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
41.8.5 XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
41.8.6 External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table “Normal I/O Pins Characteristics”.
41.9
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 41-16.ꢀInjection Current(1)
Symbol
Description
min
-1
max
+1
Unit
mA
mA
mA
(2)
Iinj1
IO pin injection current
IO pin injection current
Sum of IO pins injection current
(3)
Iinj2
-15
-45
+15
+45
Iinjtotal
DS40001882G-page 1012
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Conditions for Vpin: Vpin < GND-0.6V or 3.6V<Vpin≤4.2V.
Conditions for VDD: 3V<VDD≤3.6V.
If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting
resistor R is calculated as R = |(GND-0.6V – Vpin)/Iinj1|.
If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting
resistor R is calculated as R = (Vpin-(VDD+0.6))/Iinj1
.
3. Conditions for Vpin: Vpin < GND-0.6V or Vpin≤3.6V.
Conditions for VDD: VDD≤3V.
If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting
resistor R is calculated as R = |(GND-0.6V – Vpin)/Iinj2|.
If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting
resistor R is calculated as R = (Vpin-(VDD+0.6))/Iinj2
.
41.10 Analog Characteristics
41.10.1 Voltage Regulator Characteristics
Table 41-17.ꢀVoltage Regulator Electrical Characteristics
Parameter
Conditions
Symbol
Min. Typ. Max. Unit
1.1 1.23 1.3
DC calibrated output voltage
Voltage regulator normal mode
VDDCORE
V
Note:ꢀ Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core
supply voltage.
Table 41-18.ꢀDecoupling requirements
Symbol
Parameter
Conditions
Min. Typ. Max. Units
(1)
CIN
Input regulator capacitor, between VDDIN and GND
Ceramic dielectric X7R -
-
10
100
1
-
-
-
µF
nF
µF
(2)
COUT
Output regulator capacitor, between VDDCORE and
GND
-
0.8
ESR Cout External Series Resistance of Cout
-
-
1
Ω
Notes:ꢀ
1. It is recommended to use ceramic X7R capacitor with low-series resistance. Refer to Figure 45-1 for a typical
circuit connections of the decoupling capacitor.
2. It is recommended to use ceramic or solid tantalum capacitor with low ESR <= 1 ohms.
41.10.2 Power-On Reset (POR) Characteristics
Table 41-19.ꢀPOR Characteristics
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Voltage threshold level on VDDin rising
Voltage threshold level on VDDin falling
VPOT+
VPOT-
1.27 1.43 1.59
0.69 0.97 1.32
V
V
VDD falls at 1V/ms or slower
DS40001882G-page 1013
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-2.ꢀPOR Operating Principle
VPOT+
VPOT-
Time
41.10.3 Brown-Out Detectors Characteristics
41.10.3.1 BOD33
Table 41-20.ꢀBOD33 LEVEL Value
BOD33.LEVEL
Conditions
Symbol
Min.
Typ.
2.68
2.77
3.08
2.59
2.76
3.07
Max.
2.74
2.92
3.3
Unit
34
39
48
34
39
48
-
-
Hysteresis ON
Hysteresis OFF
VBOD+
-
V
2.51
2.7
3
2.65
2.81
3.2
VBOD-
or
VBOD
DS40001882G-page 1014
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Note:ꢀ Refer to NVM User Row Mapping for the BOD33 default value settings.
Figure 41-3.ꢀBOD33 Hysteresis OFF
VDD
VBOD
RESET pin
Figure 41-4.ꢀBOD33 Hysteresis ON
VBOD+
VDD
VBOD-
RESET pin
Table 41-21.ꢀBOD33 Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
34
Max.
Unit
mV
mV
μs
Step size, between
adjacent values in
BOD33.LEVEL
-
35
-
-
Hysteresis ON
Detection time
Startup time
Hysteresis ON
VHYST
-
170
Time with VDDANA < VTH
necessary to generate a
reset signal
tDET
0.9(1)
2.2(1)
-
-
tSTARTUP
-
μs
Note:ꢀ 1.These values are based on simulation, and are not covered by test limits in production or characterization.
Table 41-22.ꢀBOD33 Power Consumption
Parameter
Conditions
Tj
VCC
3.3V
3.3V
3.3V
3.3V
Typ.
Max.
48
Unit
IDLE2, Mode CONT
25°C
25
–40 to +105°C
25°C
-
0.132
-
51
BOD33
μA
STDBY, Mode SAMPL
0.38
1.5
–40 to +105°C
Related Links
10.3.1 NVM User Row Mapping
41.10.4 Analog-to-Digital Characteristics (ADC)
Table 41-23.ꢀOperating Conditions
Parameter
Conditions
Symbol
RES
Min.
Typ.
Max.
Unit
bits
kHz
ksps
ksps
ns
Resolution
-
-
8
30
5
-
-
-
-
-
-
12
2100
300
350
-
ADC Clock frequency
fCLK_ADC
Single shot
Sample rate (1)
-
Free running
5
Sampling time (1)
-
-
-
-
250
3
Sampling time with DAC as input(2)
-
µs
DS40001882G-page 1015
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min.
10
10
6
Typ.
Max.
Unit
µs
Sampling time with Temp sens as input(2)
Sampling time with Bandgap as input(2)
Conversion time(1)
-
-
-
-
-
-
-
-
-
-
-
µs
1x Gain
-
cycles
Voltage reference range
(VREFA or VREFB)
VREF
1.0
-
VDDANA – 0.6
V
Internal 1V reference(2, 4)
-
-
INT1V
-
-
1
-
-
V
V
Internal ratiometric reference 0(2)
INTVCC0
VDDANA/1.48
INTVCC0
Voltage Error
Internal ratiometric reference 0(2) error
Internal ratiometric reference 1(2)
Internal ratiometric reference 1(2) error
Conversion range(1)
2.0V < VDDANA<3.63V
VDDANA > 2.0V
-1
-
-
1
-
%
V
INTVCC1
VDDANA/2
-
INTVCC1
Voltage Error
2.0V < VDDANA < 3.63V
–1
1
%
Differential mode
–VREF/GAIN
-
-
+VREF/GAIN
V
V
Single-ended mode
0
-
+VREF/GAIN
Sampling capacitance (2)
Input channel source resistance(2)
DC supply current(1)
-
CSAMPLE
RSAMPLE
IDD
3.5
-
-
pF
kΩ
mA
-
-
3.5
4.1
fCLK_ADC = 2.1 MHz(3)
-
2.9
Notes:ꢀ
1. These values are based on characterization, and are not covered by test limits in production.
2. These values are based on simulation, and are not covered by test limits in production or characterization.
3. In this condition and for a sample rate of 350 ksps, 1 conversion at gain 1x takes 6 clock cycles of the ADC
clock.
4. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 41-24.ꢀDifferential Mode
Parameter
Conditions
Symbol
ENOB
TUE
Min.
Typ.
10.4
7.0
Max.
10.8
38.0
5.6
Unit
bits
LSB
LSB
LSB
mV
mV
mV
%
Effective Number Of Bits
Total Unadjusted Error
Integral Non-linearity
Differential Non-linearity
With gain compensation
1x Gain
-
1.2
1x Gain
INL
0.7
1.30
±0.7
±3
1x Gain
DNL
-
-
-
-
-
-
-
-
-
±0.95
±13
Ext. Ref 1x
Gain Error
VREF = VDDANA/1.48
VREF = INT1V
Ext. Ref. 0.5x
Ext. Ref. 2x to 16x
Ext. Ref. 1x
±11
±2
±55
GE
OE
±35
±0.1
±0.6
±2
±0.8
±0.9
±35
Gain Accuracy(5)
Offset Error
%
mV
mV
mV
VREF=VDDANA/1.48
VREF = INT1V
±3
±40
±3
±50
DS40001882G-page 1016
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
SFDR
SINAD
SNR
Min.
65
Typ.
71.5
65
Max.
76
Unit
dB
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1 MHz
58
67
dB
FIN = 40 kHz
60
66
68.6
–67
2.5
dB
AIN = 95% FSR
Total Harmonic Distortion
Noise RMS
THD
–75
0.6
–71
1
dB
T = 25°C
mV
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the
input voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the Input Common mode voltage through the following equations (where, VCM_IN is the Input
Channel Common mode voltage):
If |VIN| > VREF/4
VCM_IN < 0.95 × VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 -0.05 × VDDANA – 0.1V
If |VIN| < VREF/4
VCM_IN < 1.2 × VDDANA – 0.75V
VCM_IN > 0.2 × VDDANA – 0.1V
4. The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (2 × Vref/GAIN)
Table 41-25.ꢀSingle-Ended Mode
Parameter
Conditions
With gain compensation
1x gain
Symbol
ENOB
TUE
Min.
Typ.
9.6
11
Max.
10.1
74
Unit
Bits
LSB
LSB
LSB
mV
%
Effective Number of Bits
Total Unadjusted Error
Integral Non-linearity
Differential Non-linearity
Gain Error
-
3
1x gain
INL
1
4
11
1x gain
DNL
-
±0.5
±0.9
±0.2
±0.15
±3
±0.95
±10
±0.5
±0.3
±40
70.1
62.5
64
Ext. Ref. 1x
Ext. Ref. 0.5x
Ext. Ref. 2x to 16X
Ext. Ref. 1x
-
GE
-
Gain Accuracy(4)
-
%
Offset Error
OE
SFDR
SINAD
SNR
-
mV
dB
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Noise RMS
63
55
54
–70
-
68
1x Gain
FCLK_ADC = 2.1 MHz
60.1
61
dB
FIN = 40 kHz
dB
AIN = 95%FSR
THD
–68
1
–65
5
dB
T = 25°C
mV
DS40001882G-page 1017
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Notes:ꢀ
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations, where VCM_IN is the Input Channel
Common mode voltage for all VIN:
VCM_IN < 0.7 × VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3 × VDDANA – 0.1V
3. The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (Vref/GAIN).
41.10.4.1 Performance with the Averaging Digital Feature
Averaging is a feature that increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-
to-be-Collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 41-26.ꢀAveraging Feature
Average Number Conditions
SNR (dB) SINAD (dB)
SFDR (dB)
72.8
ENOB (bits)
10.5
1
8
66.0
67.6
69.7
70.4
65.0
65.8
67.1
67.5
75.1
10.62
In differential mode, 1x gain,
VDDANA = 3.0V, VREF = 1.0V, 350kSps at 25°C
32
75.3
10.85
128
75.5
10.91
41.10.4.2 Performance with the Hardware Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
Table 41-27.ꢀOffset and Gain Correction Feature
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
Gain Factor Conditions
0.5x
1x
0.25
0.20
0.15
–0.05
0.10
1.0
2.4
1.5
2.7
3.2
6.1
0.10
In differential mode, 1x gain, VDDANA = 3.0V, VREF = 1.0V,
350kSps at 25°C
2x
8x
–0.15
0.05
16x
–0.05
41.10.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally, the ADC input consists of a resistor (R ) and a capacitor
SAMPLE
(C
). In addition, the source resistance (R
) must be taken into account when calculating the required
SAMPLE
SOURCE
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
DS40001882G-page 1018
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-5.ꢀADC Input
VDDANA/2
Analog Input
AINx
C
SAMPLE
R
R
SAMPLE
SOURCE
V
IN
To achieve n bits of accuracy, the C
− n + 1
capacitor must be charged at least to a voltage of
SAMPLE
V
≥ V × 1 + − 2
IN
CSAMPLE
The minimum sampling time t
for a given R
can be found using this formula:
SAMPLEHOLD
SOURCE
t
≥ R
+ R
× C
× n + 1 × ln 2
SAMPLEHOLD
SAMPLE
SOURCE
SAMPLE
for a 12 bits accuracy: t
≥ R
+ R
× C × 9.02
SAMPLE
SAMPLEHOLD
SAMPLE
SOURCE
41.10.5 Digital-to-Analog Converter (DAC) Characteristics
Table 41-28.ꢀOperating Conditions(1)
Symbol
VDDANA
AVREF
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
Analog supply voltage
External reference voltage
INT1V(3)
2.7
-
3.63
1.0
-
VDDANA – 0.6
V
-
1
-
V
VDDANA
-
VDDANA
-
V
Linear output voltage range
Minimum resistive load
Maximum capacitance load
DC supply current(2)
0.05
-
VDDANA – 0.05
V
5
-
-
-
-
kΩ
pF
μA
100
256
IDD
Voltage pump disabled
-
175
Notes:ꢀ
1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 41-29.ꢀClock and Timing(1)
Parameter
Conditions
Min.
Typ.
Max.
350
1000
2.85
10
Unit
Normal mode
For ΔDATA = ±1
-
-
-
-
-
-
-
-
Cload = 100pF
Rload > 5kΩ
Conversion rate
ksps
VDDNA > 2.6V
VDDNA < 2.6V
μs
μs
Startup time
DS40001882G-page 1019
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 41-30.ꢀAccuracy Characteristics(1)
Symbol
Parameter
Conditions
Min.
-
Typ.
-
Max.
10
Unit
RES
Input resolution
Bits
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
VDD = 2.7V
VDD = 3.6V
±0.2
±0.2
±0.2
±0.2
±0.4
±0.4
±0.1
±0.1
±0.1
±0.1
±0.3
±0.3
-
±0.5
±0.4
±0.6
±0.5
±0.7
±0.8
±0.3
±0.3
±0.2
±0.2
±0.6
±0.8
±4
±1
VREF = Ext 1.0V
±1.2
±1.2
±1.3
±2
INL
Integral nonlinearity
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
LSB
±6
±0.8
±0.8
±0.5
±1
DNL
Differential nonlinearity
LSB
±3
±7
VREF = Ext. VREF
±16
±60
±22
±13
±21
±20
mV
mV
mV
mV
mV
mV
GE
OE
Gain error
VREF = VDDANA
VREF = INT1V
VREF = Ext. VREF
VREF = VDDANA
VREF = INT1V
-
±12
±1
-
-
±1
Offset error
-
±2.5
±1.5
-
Note:ꢀ
1. All values measured using a conversion rate of 35ksps.
41.10.6 Analog Comparator Characteristics
Table 41-31.ꢀElectrical and Timing
Parameter
Conditions
Symbol
Min.
0
Typ.
-
Max.
VDDANA
VDDANA
26
Unit
Positive input voltage range
Negative input voltage range
V
0
-
Hysteresis = 0, Fast mode
–26
–28
8
0
mV
mV
mV
mV
Offset
Hysteresis = 0, Low-power mode
Hysteresis = 1, Fast mode
0
28
50
50
102
Hysteresis
Hysteresis = 1, Low-power mode
14
75
DS40001882G-page 1020
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Changes for VACM = VDDANA/2
100mV overdrive, Fast mode
90
180
ns
Propagation delay
Start-up time
Changes for VACM = VDDANA/2
100mV overdrive, Low-power mode
302
1
534
2
ns
μs
μs
Enable to ready delay
Fast mode
tSTARTUP
Enable to ready delay
Low-power mode
-
14
23
INL(3)
–1.4
–0.9
0.201
0.022
0.056
0.079
1.4
0.9
LSB
LSB
LSB
LSB
DNL(3)
VSCALE
Offset Error (1)(2)
Gain Error (1)(2)
–0.2
0.92
0.89
–0.89
1. According to the standard equation V(X) = VLSB × (X + 1); VLSB = VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
41.10.7 Bandgap and Internal 1.0V Reference Characteristics
Table 41-32.ꢀBandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
After calibration
at T= 25°C,
over [–40°C,
+105°C],
1.07
1.1
1.12
V
Internal 1.1V
Bandgap
BANDGAP
reference
VDD = 3.3V
Over voltage at
25°C
1.08
0.97
0.98
1.1
1.11
1.02
1.01
V
V
V
After calibration
at T= 25°C, over
[-40°C,+105°C],
Vdd 3.3V
1.00
1.00
Internal 1.0V
INT1V
reference voltage
(1)
Over voltage at
25°C
Note:ꢀ
1. These values are simulation based and are not covered by production test limits.
DS40001882G-page 1021
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.11 NVM Characteristics
Table 41-33.ꢀMaximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Unit
0
1
24
48
MHz
MHz
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 41-34.ꢀFlash Endurance and Data Retention
Parameter
Conditions
Symbol
RetNVM25k
RetNVM2.5k
RetNVM100
CycNVM
Min.
10
Typ.
50
Max.
Unit
Years
Years
Years
Cycles
Retention after up to 25k
Retention after up to 2.5k
Retention after up to 100
Cycling Endurance(1)
Average ambient 55°C
Average ambient 55°C
Average ambient 55°C
–40°C < Ta < 105°C
-
-
-
-
20
100
25
>100
150k
25k
An endurance cycle is a write and an erase operation.
Table 41-35.ꢀEEPROM Emulation(1) Endurance and Data Retention
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Years
Years
Retention after up to 100k
Retention after up to 10k
Average ambient 55°C
Average ambient 55°C
RetEEPROM100k
RetEEPROM10k
10
20
50
-
-
100
–40°C < Ta
< 105°C
Cycling Endurance(2)
CycEEPROM
100k
600k
-
Cycles
The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write
and an erase operation.
Table 41-36.ꢀNVM Characteristics
Parameter
Conditions
Symbol
tFPP
Min.
Typ.
Max.
2.5
6
Unit
ms
Page programming time
Row erase time
-
-
-
-
-
-
-
-
-
tFRE
ms
DSU chip erase time (CHIP_ERASE)
tFCE
240
ms
41.12 Oscillators Characteristics
All temperature values are TC unless otherwise stated.
41.12.1 Crystal Oscillator (XOSC) Characteristics
41.12.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
DS40001882G-page 1022
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-37.ꢀDigital Clock Characteristics
Parameter
Conditions
Digital mode
Digital mode
Symbol
Fxin
Min.
Typ.
Max.
32
-
Unit
MHz
%
XIN clock frequency
XIN clock duty cycle
-
-
-
-
DCxin
41.12.1.2 XOSC Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 41-38.ꢀCrystal Oscillator Characteristics
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Crystal oscillator frequency
fOUT
0.4
-
32 MHz
f = 0.455ꢀMHz,
CL = 100pF
-
-
5.6K
XOSC.GAIN = 0
f = 2 MHz,
CL = 20pF
-
-
-
-
-
-
-
-
-
-
330
XOSC.GAIN = 0
f = 4 MHz,
Crystal Equivalent Series Resistance
Safety Factor = 3
CL = 20pF
240
XOSC.GAIN = 1
ESR
Ω
f = 8ꢀMHz,
The AGC does not have any noticeable impact on these
measurements.
CL = 20pF
105
XOSC.GAIN = 2
f = 16ꢀMHz,
CL = 20pF
60
55
XOSC.GAIN = 3
f = 32 MHz,
CL = 18pF
XOSC.GAIN = 4
DS40001882G-page 1023
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Parasitic capacitor load
Parasitic capacitor load
CXIN
-
-
5.9
3.2
-
-
pF
pF
CXOUT
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
f = 2 MHz,
CL = 20pF,
-
15.6K
51.0K
20.1K
XOSC.GAIN = 0,
ESR = 600Ω
f = 4 MHz,
CL = 20pF,
-
-
6.3K
6.2K
7.7K
6.0K
XOSC.GAIN = 1,
ESR = 100Ω
f = 8ꢀMHz,
CL = 20pF,
20.3K
21.2K
14.2K
Startup time
tSTARTUP
cycles
XOSC.GAIN = 2,
ESR = 35Ω
f = 16ꢀMHz,
CL = 20pF,
-
-
XOSC.GAIN = 3,
ESR = 25Ω
f = 32 MHz,
CL = 18pF,
XOSC.GAIN = 4,
ESR = 40Ω
DS40001882G-page 1024
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Parameter
Conditions
f = 2 MHz,
Symbol
Min.
Typ.
Max.
Unit
CL = 20pF,
XOSC.GAIN = 0,
AGC off
-
89
190
f = 2 MHz,
CL = 20pF,
XOSC.GAIN = 0,
AGC on
-
-
-
-
82
187
256
219
380
f = 4 MHz,
CL = 20pF,
XOSC.GAIN = 1,
AGC off
Current Consumption
140
102
243
μA
f = 4 MHz,
CL = 20pF,
XOSC.GAIN = 1,
AGC on
f = 8 MHz,
CL = 20pF,
XOSC.GAIN = 2,
AGC off
DS40001882G-page 1025
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
f = 8 MHz,
Symbol
Min.
Typ.
Max.
Unit
CL = 20pF,
XOSC.GAIN = 2,
AGC on
-
166
299
f = 16 MHz,
CL = 20pF,
-
-
-
-
493
293
685
480
XOSC.GAIN = 3,
AGC off
f = 16 MHz,
CL = 20pF,
Current Consumption
μA
XOSC.GAIN = 3,
AGC on
f = 32 MHz,
CL = 18pF,
1343
555
1975
776
XOSC.GAIN = 4,
AGC off
f = 32 MHz,
CL = 18pF,
XOSC.GAIN = 4,
AGC on
Figure 41-6.ꢀOscillator Connection
Xin
CLEXT
Crystal
LM
CSHUNT
RM
CSTRAY
CM
Xout
CLEXT
DS40001882G-page 1026
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.12.2 External 32ꢁkHz Crystal Oscillator (XOSC32K) Characteristics
41.12.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 41-39.ꢀDigital Clock Characteristics
Parameter
Conditions
Symbol
fCPXIN32
DCxin
Min.
Typ.
32.768
50
Max.
Unit
kHz
%
XIN32 clock frequency
XIN32 clock duty cycle
-
-
-
-
41.12.2.2 XOSC32K Characteristics
Figure 41-6 and the equation in 41.12.1.2 XOSC Characteristics also apply to the 32ꢀkHz oscillator connection. The
user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The
exact value of CL can be found in the crystal data sheet.
Table 41-40.ꢀ32 kHz Crystal Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Crystal oscillator frequency
fOUT
-
32768
-
Hz
ESRXTAL = 39.9ꢀkΩ,
CL = 12.5ꢀpF
Start-up time
tSTARTUP
-
28K
30K
cycles
Crystal load capacitance
Crystal shunt capacitance
Parasitic capacitor load
Parasitic capacitor load
Current consumption
CL
-
-
-
-
-
-
12.5
pF
pF
pF
pF
μA
CSHUNT
CXIN32
CXOUT32
IXOSC32K
0.1
3.2
3.7
1.22
-
-
-
2.2
Crystal equivalent series resistance
f = 32.768 kHz
CL=12.5pF
ESR
-
-
100
kΩ
Safety Factor = 3
41.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 41-41.ꢀDFLL48M Characteristics - Open Loop Mode
Parameter
Conditions
Symbol
Min. Typ. Max. Unit
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
Output frequency
fOUT
44.75
43.75
45.5
48
48
48
49
49
49
MHz
MHz
MHz
over [–10, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
Output frequency
Output frequency
fOUT
over [–40, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
fOUT
at 25°C, over [2.7, 3.6]V
DS40001882G-page 1027
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min. Typ. Max. Unit
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
Power consumption on VDDIN
IDFLL
-
403
453
μA
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
Startup time
tSTARTUP
-
8.6
11.5
μs
fOUT within 90ꢀ% of final value
Table 41-42.ꢀDFLL48M Characteristics - Closed Loop Mode(1)
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Average Output frequency
fCloseOUT
47.963
47.972
47.981
MHz
Reference frequency
fREF
Jitter
IDFLL
0.732
32.768
33
kHz
ns
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Cycle to Cycle jitter
-
-
-
0.42
453
fREF = XTAL, 32.768kHz, 100ppm
Power consumption on VDDIN
403
μA
fREF = XTAL, 32.768kHz, 100ppm
DFFLMUL = 1464
DFLLVAL.COARSE = DFLL48M
COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Lock time
tLOCK
-
350
1500
μs
Notes:ꢀ
1. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop
mode with an external OSC reference or the internal OSC8M.
2. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in
close loop must be within a 2% error accuracy.
DS40001882G-page 1028
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.12.4 32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 41-43.ꢀ32 kHz RC Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
All temperatures TC
Calibrated against a 32.768 kHz
reference at 25°C,
over [–40, +105]°C,
over [2.7, 3.63]V
26.214
32.768
39.321
Calibrated against a 32.768 kHz
reference at 25°C,
Output frequency
fOUT
kHz
32.113
31.457
32.768
32.768
33.423
34.079
at VDD = 3.3V
Calibrated against a 32.768 kHz
reference at 25°C,
over [2.7, 3.63]V
Current consumption
Startup time
IOSC32K
tSTARTUP
Duty
0.67
1
4.06
2
μA
cycle
%
Duty Cycle
50
41.12.5 Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 41-44.ꢀUltra Low-Power Internal 32 kHz RC Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
kHz
%
All temperatures TC
Calibrated against a 32.768 kHz
reference
at 25°C,
24.576
32.768
40.960
over
[–40, +105]°C,
over [2.7, 3.63]V
Calibrated against a 32.768 kHz
reference
Output frequency
fOUT
31.457
32.768
34.078
at 25°C,
at VDD = 3.3V
Calibrated against a 32.768 kHz
reference
31.293
-
32.768
50
34.570
-
at 25°C,
over [2.7, 3.63]V
Duty Cycle
Duty
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
DS40001882G-page 1029
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
2. This oscillator is always on.
41.12.6 8 MHz RC Oscillator (OSC8M) Characteristics
Table 41-45.ꢀInternal 8 MHz RC Oscillator Characteristics
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Calibrated against a 8 MHz reference
at 25°C,
7.84
7.80
7.66
8
8
8
8.16
8.20
8.34
over [–10, +70]°C,
over [2.7, 3.6]V
Calibrated against a 8 MHz reference
at 25°C,
over [–10, +105]°C,
over [2.7, 3.6]V
Output frequency
fOUT
MHz
Calibrated against a 8 MHz reference
at 25°C,
over [–40, +105]°C,
over [2.7, 3.6]V
Calibrated against a 8 MHz reference
at 25°C,
7.88
-
8
8.12
96
over [2.7, 3.6]V
IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8 MHz
(FRANGE = 1, PRESC = 0)
Current consumption
IOSC8M
64
μA
Startup time
Duty cycle
tSTARTUP
Duty
-
-
2.3 3.9
50
μs
%
-
41.12.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 41-46.ꢀFDPLL96M Characteristics(1) (Device Variant A / Die revision E)
Parameter
Conditions
Symbol
fIN
Min. Typ. Max. Unit
Input frequency
Output frequency
32
48
-
-
2000
96
733
1235
4
kHz
fOUT
-
MHz
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
fIN = 2MHz, fOUT = 96MHz
500
900
1.3
3.1
1.3
3.6
Current consumption
IFDPLL96M
μA
%
-
-
-
7
Period jitter
Jp
-
4
-
9
DS40001882G-page 1030
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
tLOCK
Min. Typ. Max. Unit
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
-
1
2
ms
Lock Time
Duty cycle
fIN = 2MHz, fOUT = 96MHz
-
25
50
50
60
μs
%
Duty
40
Table 41-47.ꢀFDPLL96M Characteristics(1) (Device Variant B / Die revision F)
Parameter
Conditions
Symbol
fIN
Min. Typ. Max. Unit
Input frequency
Output frequency
32
48
-
-
2000
96
kHz
fOUT
-
MHz
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
fIN = 2MHz, fOUT = 96MHz
500
900
2.1
4.0
2.2
4.7
-
Current consumption
IFDPLL96M
μA
-
-
-
4.0
11.0
4.0
12.0
-
Period jitter
Jp
%
-
-
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
-
1.2
2
ms
Lock Time
Duty cycle
tLOCK
Duty
fIN = 2MHz, fOUT = 96MHz
-
25
50
35
60
μs
%
40
1. All values have been characterized with FILTSEL[1/0] as default value.
DS40001882G-page 1031
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.13 PTC Typical Characteristics
41.13.1 Device Variant A
Figure 41-7.ꢀPower Consumption [μA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
140
120
100
80
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
60
40
20
0
1
2
4
8
16
32
64
Sample averaging
Figure 41-8.ꢀPower Consumption [μA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
200
180
160
140
120
100
80
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
60
40
20
0
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 1032
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-9.ꢀPower Consumption [μA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
1200
1000
800
600
400
200
0
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
Linear (Scan rate 50ms)
1
2
4
8
16
32
64
Sample averaging
Figure 41-10.ꢀPower Consumption [μA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
900
800
700
600
500
400
300
200
100
0
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 1033
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-11.ꢀPower Consumption [μA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
0
1
2
4
8
16
32
64
Sample averaging
Figure 41-12.ꢀPower Consumption [μA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
1800
1600
1400
1200
1000
800
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
600
400
200
0
1
2
4
8
16
32
64
Sample averaging
DS40001882G-page 1034
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-13.ꢀCPU Utilization
80 %
70 %
60 %
50 %
40 %
30 %
20 %
10 %
Channel count 1
Channel count 10
Channel count 100
0 %
10
50
100
200
41.13.2 Device Variant B,C and D
VCC = 3.3C and fCPU = 48 MHz for the following PTC measurements.
Figure 41-14.ꢀ1 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 1035
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-15.ꢀ1 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
Figure 41-16.ꢀ10 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 1036
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-17.ꢀ10 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
Figure 41-18.ꢀ100 Sensor / PTC_GCLK = 4 MHz / FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
DS40001882G-page 1037
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-19.ꢀ100 Sensor / PTC_GCLK = 2 MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
Table 41-48.ꢀSensor Load Capacitance
Symbol
Mode
PTC channel
Max Sensor Load (1)
Units
Y0
Y1
16
23
19
Y2
Y3
Y4
Y5
Y6
23
Y7
Self-capacitance
Cload
Y8
pF
Y9
Y10
Y11
Y12
Y13
Y14
Y15
All
19
23
30
Mutual-capacitance
Note:ꢀ
1. Capacitance load that the PTC circuitry can compensate for each channel.
DS40001882G-page 1038
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-49.ꢀAnalog Gain Settings
Symbol
Setting
GAIN_1
GAIN_2
GAIN_4
GAIN_8
GAIN_16
GAIN_32
Average
1.0
2.0
3.8
Gain
8.0
12.4
-
Notes:ꢀ
1. Analog Gain is a parameter of the QTouch Library. Refer to the QTouch Library Peripheral Touch Controller
User Guide.
2. GAIN_16 and GAIN_32 settings are not recommended, otherwise the PTC measurements might get unstable.
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating conditions
VDD = 3.3 V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC configuration
Mutual-capacitance mode
One touch channel
System configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
DS40001882G-page 1039
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-50.ꢀ
Symbol
Drift
Calibration
PTC scan
rate (msec)
Parameters
Oversamples
Ta
Typ. Max Units
4
16
4
9
107
10
50
17 117
5
6
4
5
4
4
102
104
102
103
102
102
16
4
Disabled
100
200
10
16
4
16
4
Current
Consumption
Max 85°C Typ
25°C
IDD
µA
15 114
23 124
16
4
7
8
5
6
6
6
105
108
103
105
103
104
50
16
4
Enabled
100
200
16
4
16
41.14 USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to
these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 41-51.ꢀGCLK_USB Clock Setup Recommendations
Clock setup
USB Device
USB Host
No
DFLL48M
Open loop
No
Closed loop, any internal OSC source
Closed loop, any external XOSC source
Closed loop, USB SOF source (USB recovery mode)(1)
No
No
Yes
Yes(2)
No
N/A
DS40001882G-page 1040
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Clock setup
USB Device
No
USB Host
No
FDPLL96M
Any internal OSC source (32K, 8M, ... )
Any external XOSC source (< 1MHz)
Any external XOSC source (> 1MHz)
Yes
No
Yes(3)
Yes
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can
be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN
in USB specification).
41.15 Timing Characteristics
41.15.1 External Reset
Table 41-52.ꢀExternal Reset Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
10
-
-
ns
Table 41-53.ꢀExternal Reset Characteristics (Silicon Revision G)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tEXT
Minimum reset pulse width
1000
-
-
ns
41.15.2 SERCOM in SPI Mode Timing
Figure 41-20.ꢀSPI Timing Requirements in Host Mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
tSCK
MISO
(Data Input)
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
DS40001882G-page 1041
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-21.ꢀSPI Timing Requirements in Client Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
tSSCK
MOSI
(Data Input)
MSB
LSB
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
Table 41-54.ꢀSPI Timing Characteristics and Requirements(1)
Symbol Parameter
Conditions
Host
Min.
Typ.
Max. Units
tSCK
SCK period
84
ns
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK rise time(2)
Host
-
-
-
-
-
-
-
0.5*tSCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Host
-
SCK fall time(2)
Host
-
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Client SCK Period
SCK high/low width
SCK rise time(2)
Host
21
tMIH
Host
13
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
Host
tSCK/2 - 3
Host
3
Client
Client
Client
Client
Client
Client
1*tCLK_APB
0.5*tSSCK
-
-
-
-
SCK fall time(2)
-
-
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
tSSCK/2 - 9
tSSCK/2 - 3
-
tSIH
-
tSSS
Client PRELOADEN=1 2*tCLK_APB + tSOS
PRELOADEN=0 tSOS+7
-
-
tSSH
SS hold after SCK
Client
Client
Client
Client
Client
tSIH - 4
-
tSOS
MISO setup SCK
-
-
-
-
tSSCK/2 - 18
tSOH
tSOSS
tSOSH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
18
18
10
DS40001882G-page 1042
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Notes:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production.
2. See 41.8 I/O Pin Characteristics.
41.15.3 SERCOM in I2C Mode Timing
This section describes the requirements for devices connected to the I2C Interface Bus.
Figure 41-22.ꢀI2C Interface Bus Timing
t
HIGH
t
t
R
OF
t
t
LOW
LOW
SCL
SDA
t
t
t
HD;DAT
SU;STA
HD;STA
t
SU;DAT
t
SU;STO
t
BUF
Table 41-55.ꢀI2C Interface Timing (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ. Max. Units
tR
Rise time for both SDA and SCL
Standard / Fast ICb(2) = 400pF
Mode
-
215 300 ns
Fast
Mode +
ICb(2) = 550pF
60
20
100
40
High Speed
Mode
ICb(2) = 100pF
tOF
Output fall time from VIHmin to
VILmax
Standard / Fast 10pF < Cb(2) < 400pF
Mode
20.0 50.0
15.0 50.0
Fast
10pF < Cb(2) < 550pF
Mode +
High Speed
Mode
10pF < Cb(2)< 100pF
10.0 40.0
tHD;STA Hold time (repeated) START
condition
fSCL > 100 kHz, Host tLOW-9
-
-
tLOW
tBUF
Low period of SCL Clock
fSCL > 100 kHz
fSCL > 100 kHz
113
-
-
-
-
Bus free time between a STOP
and a START condition
tLOW
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host tLOW+7 -
-
tHD;DAT Data hold time
fSCL > 100 kHz, Host
9
-
-
12
-
tSU;DAT Data setup time
fSCL > 100 kHz, Host 104
tSU;STO Setup time for STOP condition
tSU;DAT;rx Data setup time (receive mode)
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Host tLOW+9 -
-
fSCL > 100 kHz, Client 51
fSCL > 100 kHz, Client 71
-
56
138
90
DS40001882G-page 1043
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-56.ꢀI2C Interface Timing (Device Variant B,C and D)
Symbol Parameter
Conditions
Min.
Typ. Max. Units
tR
Rise time for both SDA and SCL
Standard / Fast Cb(2) = 400pF
Mode
-
230 350 ns
Fast
Cb(2) = 550pF
60
100
Mode +
High Speed
Mode
Cb(2) = 100pF
30
25
20
60
50
30
tOF
Output fall time from VIHmin to
VILmax
Standard / Fast 10pF < Cb(2) < 400pF
Mode
Fast
10pF < Cb(2) < 550pF
Mode +
High Speed
Mode
10pF < Cb(2) < 100pF
10
-
20
-
tHD;STA Hold time (repeated) START
condition
fSCL > 100 kHz, Host tLOW-9
tLOW
tBUF
Low period of SCL Clock
fSCL > 100 kHz
fSCL > 100 kHz
113
-
-
-
-
Bus free time between a STOP
and a START condition
tLOW
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host tLOW+7 -
-
tHD;DAT Data hold time
fSCL > 100 kHz, Host
9
-
-
12
-
tSU;DAT Data setup time
fSCL > 100 kHz, Host 104
tSU;STO Setup time for STOP condition
tSU;DAT;rx Data setup time (receive mode)
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Host tLOW+9 -
-
fSCL > 100 kHz, Client 51
fSCL > 100 kHz, Client 71
-
56
138
90
Notes:ꢀ
1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
DS40001882G-page 1044
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.15.4 SWD Timing
Figure 41-23.ꢀSWD Interface Signals
Read Cycle
Fromdebugger to
SWDIOpin
Stop
Park
Tri State
Data
Data
Parity
Start
Thigh
Tos
Tlow
Fromdebugger to
SWDCLK pin
SWDIOpin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
Fromdebugger to
SWDIOpin
Stop
Park
Tri State
Start
Tis
Tih
Fromdebugger to
SWDCLK pin
SWDIOpin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 41-57.ꢀSWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Units
Thigh
Tlow
Tos
SWDCLK High period
SWDCLK Low period
VVDDIO from 3.0ꢀV to 3.6ꢀV, maximum external
capacitor = 40ꢀpF
10
10
-5
500000 ns
500000
5
SWDIO output skew to falling
edge SWDCLK
Tis
Tih
Input Setup time required
between SWDIO
4
1
-
-
Input Hold time required
between SWDIO and rising
edge SWDCLK
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
41.15.5 I2S Timing
Figure 41-24.ꢀI2S Timing Host Mode
MCK output
SCK output
tM_SCKOR
tM_SCKOF
tM_FSOH
tM_SCKO
tM_SDOH
tM_SDIS
tM_SDIH
tM_FSOV
tM_SDOV
FS output
SD output
SD input
LSB right ch.
MSB left ch.
DS40001882G-page 1045
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-25.ꢀI2S Timing Client Mode
tS_FSIH
SCK input
tS_SCKI
tS_FSIS
tS_SDOH
tS_SDIS
tS_SDIH
FS input
tS_SDOV
SD output
LSB rignt ch.
MSB left ch.
SD input
Figure 41-26.ꢀI2S Timing PDM2 Mode
tPDM2RH
tPDM2RS
tPDM2LS
tPDM2LH
SCK input
SD input
Right
Left
Right
Left
Left
Right
Table 41-58.ꢀI2S Timing Characteristics and Requirements (Device Variant A)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9.2
4.7
5.3
50
ns
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.5
dM_MCKO
dM_MCKI
tM_SCKOR
I2S MCK duty cycle
I2S MCK duty cycle
I2S SCK rise time(3)
Host mode
45.4
50 45.4
%
%
ns
Host mode, pin is input (1b)
50
50
Host mode / Capacitive load
CL = 15 pF
9
4.6
4.5
50
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
ns
%
dM_SCKO
fM_SCKO,1/
I2S SCK duty cycle
I2S SCK frequency
Host mode
45.6
50 45.6
8
Host mode,Supposing external
device response delay is 30ns
9.5 MHz
tM_SCKO
fS_SCKI,1/
tS_SCKI
I2S SCK frequency
Client mode,Supposing
external device response
delay is 30ns
14.4
14.8 MHz
dS_SCKO
tM_FSOV
tM_FSOH
tS_FSIS
I2S SCK duty cycle
FS valid time
FS hold time
Client mode
Host mode
Host mode
Client mode
Client mode
50
50
%
4.1
-0.9
1.5
0
4
ns
ns
ns
ns
-0.9
2.3
0
FS setup time
FS hold time
tS_FSIH
DS40001882G-page 1046
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_SDIS
tM_SDIH
tS_SDIS
Data input setup time Host mode
Data input hold time Host mode
Data input setup time Client mode
Data input hold time Client mode
34.7
-8.2
4.6
24.5
-8.2
3.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS_SDIH
tM_SDOV
tM_SDOH
tS_SDOV
tS_SDOH
tPDM2LS
tPDM2LH
tPDM2RS
tPDM2RH
1.2
1.2
Data output valid time Host transmitter
Data output hold time Host transmitter
Data output valid time Client transmitter
Data output hold time Client transmitter
Data input setup time Host mode PDM2 Left
5.6
4.8
-0.5
-0.5
36.2
25.9
36
25.7
24.5
-8.2
20.9
-6.7
34.7
-8.2
30.5
-6.7
Data input hold time
Data input setup time Host mode PDM2 Right
Data input hold time Host mode PDM2 Right
Host mode PDM2 Left
Table 41-59.ꢀI2S Timing Characteristics and Requirements (Device Variant B and C)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9.2
4.7
5.4
50
ns
ns
tM_MCKOF
I2S MCK fall time(3) Host mode / Capacitive load
CL = 15 pF
11.6
dM_MCKO
dM_MCKI
tM_SCKOR
I2S MCK duty cycle
I2S MCK duty cycle
Host mode
47.1
50 47.3
%
%
ns
Host mode, pin is input (1b)
50
50
I2S SCK rise time(3) Host mode / Capacitive load
CL = 15 pF
9
4.6
4.6
50
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
ns
dM_SCKO
fM_SCKO, 1/
I2S SCK duty cycle
I2S SCK frequency
Host mode
47
50 47.2
7.8
%
Host mode, Supposing
external device response
delay is 30ns
9.2 MHz
tM_SCKO
fS_SCKI, 1/tS_SCKI I2S SCK frequency
Client mode, Supposing
external device response
delay is 30ns
12.8
13
MHz
dS_SCKO
tM_FSOV
tM_FSOH
tS_FSIS
I2S SCK duty cycle
FS valid time
Client mode
Host mode
Host mode
Client mode
50
50
%
ns
ns
ns
2.4
-0.1
5.3
1.9
FS hold time
-0.1
6
FS setup time
DS40001882G-page 1047
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tS_FSIH
FS hold time
Client mode
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tM_SDIS
tM_SDIH
tS_SDIS
tS_SDIH
tM_SDOV
tM_SDOH
tS_SDOV
tS_SDOH
tPDM2LS
tPDM2LH
tPDM2RS
tPDM2RH
Data input setup time Host mode
Data input hold time Host mode
Data input setup time Client mode
Data input hold time Client mode
36
25.9
-8.2
8.3
-8.2
9.1
3.8
3.7
Data output valid time Host transmitter
Data output hold time Host transmitter
Data output valid time Client transmitter
Data output hold time Client transmitter
Data input setup time Host mode PDM2 Left
2.5
1.9
-0.1
-0.1
29.8
19.7
29.1
35.5
-8.2
30.6
-7
18.9
25.3
-8.2
21.1
-7
Data input hold time
Data input setup time Host mode PDM2 Right
Data input hold time Host mode PDM2 Right
Host mode PDM2 Left
Notes:ꢀ
1. All timing characteristics given for 15pF capacitive load.
2. These values are based on simulations and not covered by test limits in production.
3. See I/O Pin Characteristics.
DS40001882G-page 1048
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Appendix A
42.
Appendix A
42.1
SIL 2 Enabled Functional Safety Devices
Microchip offers IEC 61508 SIL 2-enabled devices which can utilize the self-test library available on request from
Microchip Sales Office. The download includes the library binary, library user’s manual, and user’s checklist for
integration of the library. Refer to the “Embex SIL 2 Library User’s Manual” for additional information on using the IEC
61508 SIL 2-enabled Microchip devices.
Contact Microchip Sales Office for additional information on the IEC 61508 SIL 2-enabled devices, or to request a
part number which is not shown in the following Ordering Information.
42.1.1 Ordering Information
The following tables list the IEC 61508 SIL-enabled devices which can utilize the SIL 2 certified self-test library (STL).
Table 42-1.ꢀSAM D21J
Ordering Code
FLASH (bytes) SRAM (bytes) Temperature Grade Package Carrier Type
ATSAMD21J18A-AU-SLL
ATSAMD21J18A-MU-SLL
256K
256K
32K
32K
-40°C to 85°C
-40°C to 85°C
TQFP64 Tray
QFN64 Tray
Table 42-2.ꢀSAM D21G
Ordering Code
FLASH (bytes) SRAM (bytes) Temperature Grade Package Carrier Type
ATSAMD21G18A-AU-SLL
ATSAMD21G18A-MU-SLL
256K
256K
32K
32K
-40°C to 85°C
-40°C to 85°C
TQFP48 Tray
QFN48 Tray
Table 42-3.ꢀSAM D21E
Ordering Code
FLASH(bytes) SRAM (bytes) Temperature Grade Package Carrier Type
ATSAMD21E18A-AU-SLL
ATSAMD21E18A-MU-SLL
ATSAMD21E17D-MUT-SLL
ATSAMD21E16B-MU-SLL
ATSAMD21E16B-MUT-SLL
256K
256K
128K
64K
32K
32K
16K
8K
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
TQFP32 Tray
QFN32
QFN32
QFN32
QFN32
Tray
Tape & Reel
Tray
64K
8K
Tape & Reel
DS40001882G-page 1049
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Appendix B
43.
Appendix B
43.1
ISELED FULL License Enabled Functional Devices
Microchip offers ISELED full license enabled devices which can utilize the ISELED software stack and library
available for download from the Microchip Website. Included in the download will be the ISELED stack source code
file, header, the library binary, and the library user’s manual. Refer to the Inova data sheet of the INLC10AQ (ISELED
control commands; document AN-INLC_04; ) For more information on Microchip’s ISELED solutions, please visit the
Microchip Website (www.microchip.com/iseled).
Contact the Microchip Sales Office for more details on the ISELED full license enabled devices, or to request a part
number which is not available in the following Ordering Information.
43.2
Ordering Information
The following table lists the ISELED full license enabled devices, which can utilize the ISELED full license software
stack and library.
Table 43-1.ꢀSAM D21J
FLASH
(bytes)
SRAM
Ordering Code
Temperature Grade
Package
Carrier Type
(bytes)
ATSAMD21J18A-AZT510
ATSAMD21J18A-AZ510
256K
256K
32K
32K
-40°C to 125°C
TQFP64
TQFP64
Tape & Reel
-40°C to 125°C
Tray
DS40001882G-page 1050
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.
Packaging Information
44.1
Package Drawings
Note:ꢀ For current package drawings, refer to the Microchip Packaging Specification, which is available at http://
www.microchip.com/packaging.
DS40001882G-page 1051
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.1 64-Pin TQFP
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
E1/2
A
B
E1
E
A
A
SEE DETAIL 1
N
4X N/4 TIPS
1
3
0.20 C A-B D
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
A1
C A-B D
64 X b
0.08
0.08 C
e
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
DS40001882G-page 1052
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
L
(L1)
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
0.50 BSC
-
1.00
-
MAX
Number of Leads
Lead Pitch
Overall Height
N
e
A
-
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
Foot Length
0.60
Footprint
Foot Angle
L1
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
-
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
b
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
DS40001882G-page 1053
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
E
C2
G
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
0.50 BSC
11.40
MIN
0.20
MAX
Contact Pitch
E
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X28)
Contact Pad Length (X28)
Distance Between Pads
C1
C2
X1
Y1
G
11.40
0.30
1.50
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
Table 44-1.ꢀDevice and Package Maximum Weight
300
mg
DS40001882G-page 1054
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-2.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-085
E3
DS40001882G-page 1055
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.2 64-Pin VQFN
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.08 C
0.10 C
D
A
B
N
1
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
A1
TOP VIEW
0.15 C
(A3)
0.10
C A B
D2
A
SEATING
PLANE
C
SIDE VIEW
0.10
C A B
E2
e
2
NOTE 1
2
1
K
N
L
64X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 1 of 2
DS40001882G-page 1056
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
64
0.50 BSC
0.90
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
0.02
0.203 REF
9.00 BSC
4.70
9.00 BSC
4.70
4.60
4.80
4.60
0.15
0.30
0.20
4.80
0.25
0.55
-
0.20
0.40
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 2 of 2
DS40001882G-page 1057
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
64
1
2
ØV
G2
C2 Y2
EV
Y1
G1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
4.80
4.80
8.90
8.90
Contact Pad Spacing
Contact Pad Width (X64)
Contact Pad Length (X64)
Contact Pad to Center Pad (X64)
Contact Pad to Contact Pad (X60)
Thermal Via Diameter
0.30
0.90
1.60
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 1 of 2
Note:ꢀ The exposed die attach pad is not connected electrically inside the device.
DS40001882G-page 1058
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-3.ꢀDevice and Package Maximum Weight
200
mg
Table 44-4.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-21441
E3
DS40001882G-page 1059
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.3 64 Lead QFN with Sawn Wettable Flanks
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.08 C
0.10 C
D
A
NOTE 1
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.05
0.20
0.90
TOP VIEW
0.10 C
0.10
C A B
D2
SEATING
PLANE
C
SIDE VIEW
DETAIL A
0.10
C A B
E2
A4
A
A
e
2
STEPPED
WETTABLE
FLANK
(K)
2
1
D3
SECTION A-A
N
L
64X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-21497 Rev A Sheet 1 of 2
DS40001882G-page 1060
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
64
0.50 BSC
0.85
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
0.90
0.05
0.035
0.203 REF
9.00 BSC
4.70
9.00 BSC
4.70
4.60
4.80
4.60
0.15
0.35
4.80
0.25
0.45
0.20
0.40
Terminal-to-Exposed-Pad
Wettable Flank Step Length
Wettable Flank Step Height
K
D3
A4
1.75 REF
-
-
0.085
0.19
0.10
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21497 Rev A Sheet 1 of 2
DS40001882G-page 1061
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
64
1
2
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
4.80
4.80
8.90
8.90
Contact Pad Spacing
Contact Pad Width (X64)
Contact Pad Length (X64)
Contact Pad to Center Pad (X64)
Contact Pad to Contact Pad (X60)
Thermal Via Diameter
0.30
0.85
1.63
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23497 Rev A
Table 44-5.ꢀDevice and Package Maximum Weight
200
mg
DS40001882G-page 1062
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-6.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21497
E3
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
DS40001882G-page 1063
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.4 64-ball UFBGA
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.10 C
D
A
0.10 C
1
2
3
4
5
6
7
8
B
A
B
C
D
E
F
E
G
H
2X
0.10 C
2X
A1
(S)
TOP VIEW
0.10 C
(M)
1
2
3
4
5
6
7
8
SEATING
PLANE
A
C
H
G
F
END VIEW
e
2
E
D
C
B
A
E2
NOTE 1
e
64X Øb
0.15
0.05
C A B
C
D2
BOTTOM VIEW
Microchip Technology Drawing C04-21153 Rev A Sheet 1 of 2
DS40001882G-page 1064
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Ball Height
Mold Thickness
Substrate Thickness
Overall Length
Ball Array Length
Overall Width
Ball Array Width
Ball Width
N
e
64
0.50 BSC
–
A
A1
M
S
D
D2
E
–
0.14
0.65
0.24
0.19
0.25 REF
1.36 REF
5.00 BSC
3.50 BSC
5.00 BSC
3.50 BSC
0.25
E2
b
0.20
0.3
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21153 Rev A Sheet 2 of 2
DS40001882G-page 1065
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
C2
G
H
SILK SCREEN
ØX
E
C1
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
0.20
Contact Pitch
E
C1
C2
X
0.50 BSC
3.50 BSC
3.50 BSC
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (Xnn)
Contact Pad to Contact Pad (Xnn)
G
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23153 Rev A
DS40001882G-page 1066
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-7.ꢀDevice and Package Maximum Weight
27.4
mg
Table 44-8.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-21153
E8
DS40001882G-page 1067
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.5 48-Pin TQFP
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1
2
D
2
D
E1
2
A
B
E
E1
A
A
NOTE 1
E
2
N
N/4 TIPS
0.20 C A-B D
1
2
3
e
2
0.20 C A-B D 4X
e
TOP VIEW
C
A2
A1
A
SEATING
PLANE
48X
0.08 C
48X b
0.08
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 1 of 2
DS40001882G-page 1068
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ϴ2
ϴ1
R2
H
R1
c
ϴ2
ϴ
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Terminals
Pitch
N
e
48
0.50 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
Molded Package Length
Overall Width
A
A1
A2
D
D1
E
-
-
-
1.20
0.15
1.05
0.05
0.95
1.00
9.00 BSC
7.00 BSC
9.00 BSC
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
E1
b
c
7.00 BSC
0.22
0.17
0.09
0.45
0.27
0.16
0.75
-
L
0.60
1.00 REF
L1
R1
R2
ϴ
ϴ1
ϴ2
0.08
0.08
0°
0°
11°
-
-
-
0.20
7°
3.5°
-
12°
Lead Angle
Mold Draft Angle
-
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 2 of 2
DS40001882G-page 1069
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
0.50 BSC
8.40
8.40
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X48)
C1
C2
X1
0.30
1.50
Contact Pad Length (X48)
Distance Between Pads
Y1
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-Y8 Rev D
Table 44-9.ꢀDevice and Package Maximum Weight
140
mg
DS40001882G-page 1070
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-10.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-00300
E3
DS40001882G-page 1071
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.6 48-Pin VQFN
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A1
48X
0.08 C
0.08 C
D
A
B
E
NOTE 1
N
1
2
(DATUM B)
(DATUM A)
2X
0.15 C
2X
TOP VIEW
0.15 C
(A3)
0.10
C A B
A
D2
SEATING
PLANE
C
SIDE VIEW
E2
e
2
2
1
0.10
C A B
NOTE 1
N
L
48X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21425 Rev A Sheet 1 of 2
DS40001882G-page 1072
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
48
0.50 BSC
0.85
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
0.90
0.05
0.02
0.20 REF
7.00 BSC
5.15
7.00 BSC
5.15
0.25
0.40
-
5.05
5.25
5.05
0.18
0.30
0.20
5.25
0.30
0.50
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21425 Rev A Sheet 2 of 2
DS40001882G-page 1073
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
48
1
2
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
5.15
5.15
6.90
6.90
Contact Pad Spacing
Contact Pad Width (X20)
Contact Pad Length (X20)
Contact Pad to Center Pad (X48)
Contact Pad to Contact Pad (X44)
Thermal Via Diameter
0.30
0.90
0.20
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23425 Rev A
Note:ꢀ The exposed die attach pad is not connected electrically inside the device.
DS40001882G-page 1074
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-11.ꢀDevice and Package Maximum Weight
140
mg
Table 44-12.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-21425
E3
DS40001882G-page 1075
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.7 48 lead VQFN with Sawn Wettable Flanks
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48X
0.08 C
D
A
0.10 C
D
4
B
N
E
4
1
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
0.10 C A B
(A3)
D2
A
SEATING
PLANE
C
0.10 C A B
DETAIL A
SIDE VIEW
A
A
E2
A4
e
2
2
1
D3
SECTION A-A
N
(K)
L
48X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21493 Rev A Sheet 1 of 2
DS40001882G-page 1076
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
48
0.50 BSC
0.85
A
A1
A3
D
D2
E
E2
b
L
0,80
0.00
0.90
0.05
0.02
0.203 REF
7.00 BSC
5.15
7.00 BSC
5.15
5.05
5.25
5.05
0.20
0.35
5.25
0.30
0.45
0.25
0.40
Terminal-to-Exposed-Pad
Wettable Flank Step Length
Wettable Flank Step Height
K
D3
A4
0.53 REF
-
-
0.085
0.19
0.10
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21493 Rev A Sheet 2 of 2
DS40001882G-page 1077
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
48
1
ØV
2
G2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
5.25
5.25
6.90
6.90
Contact Pad Spacing
Contact Pad Width (X48)
Contact Pad Length (X48)
Contact Pad to Center Pad (X48)
Contact Pad to Center Pad (X44)
Thermal Via Diameter
0.30
0.85
0.20
0.40
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23493 Rev A
Table 44-13.ꢀDevice and Package Maximum Weight
140
mg
DS40001882G-page 1078
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-14.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21493
E3
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
DS40001882G-page 1079
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.8 45-ball WLCSP
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
NOTE 1
(DATUM
A)
(DATUM
B)
2X
0.03 C
2X
TOP VIEW
0.03 C
SEE DETAIL A
C
A
SEATING
PLANE
SIDE VIEW
D1
45X Øb
0.15
C A B
C
0.05
E1
NOTE 1
e
2
e
BOTTOM VIEW
Microchip Technology Drawing C04-21247 Rev A Sheet 1 of 2
DS40001882G-page 1080
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
45X
0.075 C
DETAIL A
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Bump Height
Die Thickness
Backside Coating
Overall Length
Overall Bump Pitch
Overall Width
N
e
45
0.40 BSC
-
0.20
0.203
0.04 REF
2.944 BSC
2.40
2.699 BSC
2.079 BSC
0.26
A
A1
A2
A3
D
D1
E
E1
b
-
0.483
0.23
0.228
0.17
0.178
Overall Bump Pitch
Terminal Width
0.23
0.29
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21247 Rev A Sheet 2 of 2
DS40001882G-page 1081
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ØX
E
C1
E
SILK SCREEN
C2
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.40 BSC
2.079 BSC
2.40 BSC
0.26
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Spacing
E
C1
C2
Contact Pad Diameter (X45)
X
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23247 Rev A
Table 44-15.ꢀDevice and Package Maximum Weight
7.3
mg
DS40001882G-page 1082
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-16.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-21247
E1
DS40001882G-page 1083
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.9 32-Pin TQFP
32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D
32X TIPS
0.20 C A-B D
A
B
E1
E
A
A
N
NOTE 1
1
2
4X
0.20 H A-B D
32X b
0.20
C A-B D
e
TOP VIEW
0.10 C
32X
C
A2
A1
A
SEATING
PLANE
0.10 C
SIDE VIEW
Microchip Technology Drawing C04-074 Rev C Sheet 1 of 2
DS40001882G-page 1084
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Leads
Lead Pitch
N
e
32
0.80 BSC
Overall Height
Standoff
Molded Package Thickness
Foot Length
A
A1
A2
L
-
-
-
1.20
0.15
1.05
0.75
0.05
0.95
0.45
1.00
0.60
Footprint
Foot Angle
L1
1.00 REF
-
0°
7°
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Width
E
D
E1
D1
b
9.00 BSC
9.00 BSC
7.00 BSC
7.00 BSC
0.37
0.30
11°
0.45
13°
Mold Draft Angle Top
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-074 Rev C Sheet 2 of 2
DS40001882G-page 1085
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Thin Plastic Quad Flatpack (PT) - 7x7 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
Y
X
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.80 BSC
8.40
MAX
Contact Pitch
E
C1
C2
X
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (Xnn)
8.40
0.55
1.55
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2074 Rev C
Table 44-17.ꢀDevice and Package Maximum Weight
100
mg
DS40001882G-page 1086
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-18.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-00074
E3
DS40001882G-page 1087
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.10 32-Pin VQFN
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
32X
0.08 C
0.10 C
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
A1
TOP VIEW
0.15 C
(A3)
0.10
C A B
A
D2
SEATING
PLANE
C
SIDE VIEW
0.10
C A B
E2
e
2
K
2
1
NOTE 1
N
L
32X b
0.10
0.05
C A B
e
C
BOTTOM VIEW
Microchip Technology Drawing C04-21402 Rev A Sheet 1 of 2
DS40001882G-page 1088
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
32
0.50 BSC
0.90
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
0.02
0.20 REF
5.00 BSC
3.60
5.00 BSC
3.60
0.25
0.40
-
3.50
3.70
3.50
0.18
0.30
0.20
3.70
0.30
0.50
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21402 Rev A Sheet 1 of 2
DS40001882G-page 1089
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
1
2
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
3.70
3.70
5.00
5.00
Contact Pad Spacing
Contact Pad Width (X32)
Contact Pad Length (X32)
Contact Pad to Center Pad (X32)
Contact Pad to Contact Pad (X28)
Thermal Via Diameter
0.30
0.85
0.23
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23402 Rev A
Note:ꢀ The exposed die attach pad is connected inside the device to GND and GNDANA.
DS40001882G-page 1090
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-19.ꢀDevice and Package Maximum Weight
90
mg
Table 44-20.ꢀPackage Reference
Package Outline Drawing MCHP reference
JESD97 Classification
C04-21402
E3
DS40001882G-page 1091
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.11 32 lead VQFN with Sawn Wettable Flanks
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
A1
0.10 C
0.08 C
C
A
SEATING
PLANE
32X
(A3)
0.10
SIDE VIEW
C A B
D2
A4
DETAIL A
PARTIALLY
PLATED
D3
SECTION A–A
A
A
E2
e
2
K
2
1
0.10
C A B
NOTE 1
N
e
L
32X b
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21391 Rev E Sheet 1 of 2
DS40001882G-page 1092
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
MILLIMETERS
Dimension Limits
MIN
NOM
32
0.50 BSC
0.90
0.035
0.203 REF
5.00 BSC
3.60
5.00 BSC
3.60
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
1.00
0.05
3.50
3.70
3.50
0.20
0.35
0.20
-
3.70
0.30
0.45
-
0.085
0.19
0.25
0.40
-
-
Terminal-to-Exposed-Pad
K
Wettable Flank Step Cut Width
Wettable Flank Step Cut Depth
D3
A4
0.10
-
Dimensions D3 and A4 above apply to all new products released after
November 1, and all products shipped after January 1, 2019, and supersede
dimensions D3 and A4 below.
No physical changes are being made to any package; this update is to align
cosmetic and tolerance variations from existing suppliers.
Wettable Flank Step Length
Wettable Flank Step Height
D3
A4
0.035
0.10
0.06
-
0.085
0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21391 Rev E Sheet 2 of 2
DS40001882G-page 1093
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
G1
1
2
ØV
CH
C2
Y2
G2
X1
EV
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
X2
Y2
3.70
3.70
Exposed Pad 45° Corner Chamfer CH
0.25
5.00
5.00
Contact Pad Spacing
Contact Pad Spacing
C1
C2
X1
Y1
G1
G2
V
Contact Pad Width (X32)
Contact Pad Length (X32)
Contact Pad to Center Pad (X32)
Contact Pad to Contact Pad (X28)
Thermal Via Diameter
0.30
0.80
0.25
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23391 Rev. E
Table 44-21.ꢀDevice and Package Maximum Weight
90
mg
DS40001882G-page 1094
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-22.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21391
E3
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
DS40001882G-page 1095
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.12 35 ball WLCSP (Device Variant B)
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
NOTE 1
1
2
3
4
5
6
A
B
C
D
E
F
(DATUM B)
(DATUM A)
2X
0.03 C
2X
TOP VIEW
0.03 C
SEE DETAIL A
C
A
SEATING
PLANE
SIDE VIEW
D1
1
2
3
4
5
6
F
E
D
C
B
A
e
2
E1
NOTE 1
35X Øb
0.15
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21245 Rev A Sheet 1 of 2
DS40001882G-page 1096
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
35X
0.075 C
DETAIL A
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Bump Height
Die Thickness
Backside Coating
Overall Length
Overall Bump Pitch
Overall Width
N
e
35
0.40 BSC
-
0.20
0.203
0.04 REF
2.529 BSC
2.00 BSC
2.821 BSC
2.00 BSC
0.26
A
A1
A2
A3
D
D1
E
E1
b
-
0.483
0.23
0.228
0.17
0.178
Overall Bump Pitch
Terminal Width
0.23
0.29
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21245 Rev A Sheet 2 of 2
DS40001882G-page 1097
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
A
B
C
D
E
ØX
C1
E
F
E
SILK SCREEN
C2
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.40 BSC
2.00 BSC
2.00 BSC
0.26
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Spacing
E
C1
C2
Contact Pad Diameter (X35)
X
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23245 Rev. A
Table 44-23.ꢀDevice and Package Maximum Weight
6.2
mg
DS40001882G-page 1098
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-24.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21245
E1
DS40001882G-page 1099
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.13 35 ball WLCSP (Device Variant C)
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SEE DETAIL A
D
A
B
1
2
3
4
5
6
NOTE1
A
B
C
D
E
F
E
(DATUM B)
(DATUM A)
2X
0.03 C
2X
A
TOP VIEW
0.03 C
SEATING
PLANE
C
SIDE VIEW
D1
1
2
3
4
5
6
F
E
D
C
B
A
E1
35X Øb
0.05
0.015
e
2
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21492 Rev A Sheet 1 of 2
DS40001882G-page 1100
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
35X
0.075 C
DETAIL A
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Bump Height
Die Thickness
Backside Coating
Overall Length
Overall Bump Pitch
Overall Width
N
e
35
0.40 BSC
0.443
A
A1
A2
A3
D
D1
E
E1
b
0.403
0.17
0.178
0.483
0.23
0.228
–
0.203
0.04 REF
2.578 BSC
2.00 BSC
2.78 BSC
2.00 BSC
0.26
Overall Bump Pitch
Bump Diameter
0.23
0.29
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21492 Rev A Sheet 2 of 2
DS40001882G-page 1101
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
A
B
C
D
E
F
G
C2
ØX
SILK SCREEN
E
C1
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Contact Pitch
E
C1
C2
X
0.40 BSC
2.00 BSC
2.00 BSC
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width
0.20
Contact Pad to Contact Pad (X35)
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23492 Rev A
Table 44-25.ꢀDevice and Package Maximum Weight
6.22
mg
DS40001882G-page 1102
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-26.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21492
e1
DS40001882G-page 1103
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
44.1.14 35 Ball WLCSP (Device Variant D)
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
35X
0.05 C
0.06 C
D
A
B
E
NOTE 1
5
6
1
2
3
4
A
B
C
D
E
F
(DATUM B)
(DATUM A)
2X
0.03 C
2X
TOP VIEW
A1
0.03 C
A3
A2
eD
e
2
A
SEATING
PLANE
C
SIDE VIEW
F
E
D
C
B
A
e
2
eE
1
2
3
4
5
6
35X Øb
0.015
C A B
e
BOTTOM VIEW
Microchip Technology Drawing C04-21491 Rev A Sheet 1 of 2
DS40001882G-page 1104
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Ball Height
Die Thickness
Film Thickness
Overall Length
Overall Pitch
Overall Width
Overall Pitch
Ball Diameter
N
e
35
0.40 BSC
0.443
0.20
0.203
A
A1
A2
A3
D
eD
E
eE
b
0.403
0.17
0.178
0.036
0.483
0.23
0.228
0.044
0.040
2.831 BSC
2.00 BSC
2.916 BSC
2.00 BSC
0.27
0.24
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21491 Rev A Sheet 2 of 2
DS40001882G-page 1105
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
1
2
3
4
5
6
A
B
C
D
C2
E
F
ØX
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.40 BSC
2.00
MAX
0.20
Contact Pitch
Contact Pad Spacing
Contact Pad Spacing
E
C1
C2
2.00
Contact Pad Diameter (X35)
X
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23491 Rev A
Table 44-27.ꢀDevice and Package Maximum Weight
5.98
mg
DS40001882G-page 1106
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Packaging Information
Table 44-28.ꢀPackage Reference
JEDEC Drawing Reference
JESD97 Classification
C04-21491
e1
44.2
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 44-29.ꢀRecommended Soldering Profile
Profile Feature
Green Package
3°C/s max.
150-200°C
60-150s
Average Ramp-up Rate (217°C to peak)
Preheat Temperature 175°C ±25°C
Time Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
30s
260°C
Ramp-down Rate
6°C/s max.
8 minutes max.
Time 25°C to Peak Temperature
A maximum of three reflow passes is allowed per component.
44.3
Package Markings
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
Where:
•
•
•
•
“YY”: Manufacturing year
“WW”: Manufacturing week
“R”: Internal Code
“XXXXXX”: Lot number
DS40001882G-page 1107
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
45.
Schematic Checklist
45.1
Introduction
This chapter describes a common checklist which should be used when starting and reviewing the schematics for a
SAM D21 design. This chapter illustrates a recommended power supply connection, how to connect external analog
references, programmer, debugger, oscillator and crystal.
45.1.1 Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise, it must be protected from this noise to
ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed
in the schematic checklist sections must be followed. In particular, placing decoupling capacitors very close to the
power pins, an RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations.
It is also relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals.
45.2
Power Supply
The SAM D21 supports a single power supply from 1.62V - 3.63V.
45.2.1 Power Supply Connections
Figure 45-1.ꢀPower Supply Schematic(1)
Close to device
(for every pin)
1.62V-3.63V
VDDANA
10µF
100nF
GNDANA
VDDIO
VDDIN
100nF
100nF
VDDCORE
10µF
1µF
GND
Note:ꢀ 1. It is recommended to use a ceramic or solid tantalum capacitor with low ESR. Refer to table 37-18 in
37.11.1 Voltage Regulator Characteristics for additional details on ESR.
Table 45-1.ꢀPower Supply Connections, VDDCORE From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Digital supply voltage
Decoupling/filtering inductor 10μH(1)(3)
DS40001882G-page 1108
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
...........continued
Signal Name Recommended Pin Connection
Description
VDDANA
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Analog supply voltage
Ferrite bead(4) prevents the VDD noise interfering the VDDANA
VDDCORE
1.6V to 1.8V
Decoupling/filtering capacitor 1μF(1)(2)
Core supply voltage / external
decoupling pin
GND
Ground
GNDANA
Ground for the analog power domain
Notes:ꢀ
1. These values are only given as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group, low
ESR caps should be used for better decoupling.
3. An inductor should be added between the external power and the VDD for power filtering.
4. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can be added
between VDD and VDDANA for preventing digital noise from entering the analog power domain. The bead
should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz) for separating the digital power
from the analog power domain. Make sure to select a ferrite bead designed for filtering applications with a low
DC resistance to avoid a large voltage drop across the ferrite bead.
45.3
External Analog Reference Connections
The following schematic checklist is only necessary if the application is using one or more of the external analog
references. If the internal references are used instead, the following circuits are not necessary.
Figure 45-2.ꢀExternal Analog Reference Schematic With Two References
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE 1
4.7µF
100nF
GND
AREFB
EXTERNAL
REFERENCE 2
4.7µF
100nF
GND
DS40001882G-page 1109
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-3.ꢀExternal Analog Reference Schematic With One Reference
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE
4.7µF
100nF
GND
AREFB
100nF
GND
Table 45-2.ꢀExternal Analog Reference Connections
Signal Name
Recommended Pin Connection
1.0V to VDDANA - 0.6V for ADC
1.0V to VDDANA- 0.6V for DAC
Description
AREFx
External reference from AREFx pin on
the analog port
Decoupling/filtering capacitors
100nF(1)(2) and 4.7μF(1)
GND
Ground
1. These values are given as a typical example.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
45.4
External Reset Circuit
The external Reset circuit is connected to the RESET pin when the external Reset function is used. The circuit is not
necessary when the RESET pin is not driven low externally by the application circuitry.
The reset switch can also be removed, if a manual reset is not desired. The RESET pin itself has an internal pull-up
resistor, hence it is optional to add any external pull-up resistor.
A pull-up resistor makes sure that the reset does not go low and unintentionally cause a device reset. An additional
resistor has been added in series with the switch to safely discharge the filtering capacitor, that is, preventing a
current surge when shorting the filtering capacitor, which again can cause a noise spike that can have a negative
effect on the system.
DS40001882G-page 1110
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-4.ꢀExternal Reset Circuit Schematic
VDD
10kΩ
330Ω
RESET
GND
100nF
Figure 45-5.ꢀExternal Reset Circuit Schematic (EFT Immunity Enhancement)
VDD
2.2kΩ
330Ω
100pF
RESET
GND
Note:ꢀ This reset circuit is intended to improve EFT immunity, but does not filter low-frequency glitches, which makes
it not suitable as an example for applications requiring debouncing on a reset button.
Table 45-3.ꢀReset Circuit Connections
Signal Name Recommended Pin Connection
Description
RESET
Reset low-level threshold voltage
Reset pin
VDDIO = 1.6V - 2.0V: Below 0.33 * VDDIO
VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO
Decoupling/filter capacitor 100 pF(1)Pull-up resistor 2.2 kΩ(1)(2)Resistor in series with
the switch 330Ω(1)
1. These values are given as a typical example.
DS40001882G-page 1111
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
2. The SAM D21 features an internal pull-up resistor on the RESET pin, hence an external pull-up is optional.
45.5
Clocks and Crystal Oscillators
The SAM D21 can be run from internal or external clock sources, or a mix of internal and external sources. An
example of usage will be to use the internal 8MHz oscillator as source for the system clock, and an external
32.768kHz watch crystal as clock source for the Real-Time counter (RTC).
45.5.1 External Clock Source
Figure 45-6.ꢀExternal Clock Source Example Schematic
External
Clock
XIN
XOUT/GPIO
NC/GPIO
Table 45-4.ꢀExternal Clock Source Connections
Signal Name
XIN
Recommended Pin Connection
Description
XIN is used as input for an external clock signal
Can be left unconnected or used as normal GPIO
Input for inverting oscillator pin
XOUT/GPIO
45.5.2 Crystal Oscillator
Figure 45-7.ꢀCrystal Oscillator Example Schematic
XIN
CLEXT
XOUT
CLEXT
The crystal should be located as close to the device as possible. Long signal lines may cause a load too high to
operate the crystal, and cause crosstalk to other parts of the system.
Table 45-5.ꢀCrystal Oscillator Checklist
Signal Name
XIN
Recommended Pin Connection
Description
(1)(2)
Load capacitor CLEXT
External crystal between 0.4 to 30 MHz
(1)(2)
XOUT
Load capacitor CLEXT
1. Use the equation in Crystal Oscillator Characteristics to calculate CLEXT
.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
45.5.3 External Real Time Oscillator
The low-frequency crystal oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals,
load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are
specified by the crystal vendor.
DS40001882G-page 1112
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
The SAM D21 oscillator is optimized for very-low-power consumption, so pay close attention when selecting crystals.
See the table below for maximum ESR recommendations on 9pF and 12.5pF crystals.
The low-frequency crystal oscillator provides an internal load capacitance of typical values available in Table , 32 kHz
Crystal Oscillator Characteristics. This internal load capacitance and PCB capacitance can use a crystal inferior to
12.5pF load capacitance without external capacitors as shown in the following figure.
Table 45-6.ꢀMaximum ESR Recommendation for 32.768 kHz Crystal
Crystal CL (pF)
Max ESR [kΩ]
12.5
313
Note: Maximum ESR is typical value based on characterization. These values are not covered by test limits in
production.
Figure 45-8.ꢀExternal Real Time Oscillator without Load Capacitor
XIN32
32.768kHz
XOUT32
However, to improve crystal accuracy and safety factor, the data sheet recommends adding external capacitors as
shown in the next figure.
To find suitable load capacitance for a 32.768 kHz crystal, consult the crystal data sheet.
Figure 45-9.ꢀExternal Real Time Oscillator with Load Capacitor
XIN32
CLEXT
32.768kHz
CLEXT
XOUT32
Table 45-7.ꢀExternal Real Time Oscillator Checklist
Signal Name
XIN32
Recommended Pin Connection
Description
(1)(2)
Load capacitor CLEXT
Load capacitor CLEXT
Timer oscillator input
Timer oscillator output
(1)(2)
XOUT32
1. Use the equation in Crystal Oscillator Characteristics to calculate CLEXT
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
Note:ꢀ
.
In order to minimize the cycle-to-cycle jitter of the external oscillator, keep the neighboring pins as steady as possible.
For neighboring pin details, refer to the Oscillator Pinout section.
Related Links
7.2.1 Oscillator Pinout
37.13 Oscillators Characteristics
45.5.4 Calculating the Correct Crystal Decoupling Capacitor
In order to calculate correct load capacitor for a given crystal, refer to Oscillator Characteristics for parasitic load
capacitance values and equation to calculate CLEXT
.
DS40001882G-page 1113
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
45.6
45.7
Unused or Unconnected Pins
For unused pins, the default state of the pins for the will provide the lowest current leakage. There is no need to do
any configuration of the unused pins in order to lower the power consumption.
Programming and Debug Ports
For programming and/or debugging the SAM D21 the device should be connected using the Serial Wire Debug,
SWD, interface. Currently the SWD interface is supported by several Microchip and third party programmers
and debuggers, like the JTAGICE3, SAM-ICE, ATMEL_ICE or SAM D21 Xplained Pro ( SAM D21 evaluation kit)
Embedded Debugger.
Refer to the JTAGICE3, SAM-ICE, ATMEL_ICE or SAM D21 Xplained Pro user guides for details on debugging and
programming connections and options. For connecting to any other programming or debugging tool, refer to that
specific programmer or debugger’s user guide.
The SAM D21 Xplained Pro evaluation board for the SAM D21 supports programming and debugging through the
onboard embedded debugger so no external programmer or debugger is needed.
Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to related link for more
information.
Figure 45-10.ꢀSWCLK Circuit Connections
VDD
1kΩ
SWCLK
Table 45-8.ꢀSWCLK Circuit Connections
Pin Name
Description
Recommended Pin Connection
SWCLK
Serial wire clock pin
Pull-up resistor 1kΩ
Related Links
45.1.1 Operation in Noisy Environment
45.7.1 Cortex Debug Connector (10-pin)
For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be
connected as shown in the figure below with details described in the next table.
DS40001882G-page 1114
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-11.ꢀCortex Debug Connector (10-pin)
VDD
Cortex Debug Connector
(10-pin)
VTref
GND
GND
NC
SWDIO
SWDCLK
NC
1
RESET
SWCLK
SWDIO
GND
NC
NC
nRESET
Table 45-9.ꢀCortex Debug Connector (10-pin)
Header Signal Name Description
Recommended Pin
Connection
SWDCLK
SWDIO
RESET
Serial wire clock pin
Pull-up resistor 1kΩ
Serial wire bidirectional data pin
Target device reset pin, active low
Refer to 45.4 External Reset Circuit.
VTref
GND
Target voltage sense, should be connected to the device
VDD
Ground
45.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a
special pinout is needed to directly connect the SAM D21 to the JTAGICE3, alternatively one can use the JTAGICE3
squid cable and manually match the signals between the JTAGICE3 and SAM D21. The following figure describes
how to connect a 10-pin header that support connecting the JTAGICE3 directly to the SAM D21 without the need for
a squid cable.
To connect the JTAGICE3 programmer and debugger to the SAM D21, one can either use the JTAGICE3 squid
cable, or use a 10-pin connector as shown in the figure below with details given in the next table to connect to the
target using the JTAGICE3 50 mil cable directly.
DS40001882G-page 1115
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-12.ꢀ10-pin JTAGICE3 Compatible Serial Wire Debug Interface
10-pin JTAGICE3 Compatible
VDD
Serial Wire Debug Header
SWDCLK
NC
GND
VTG
RESET
NC
1
RESET
SWCLK
SWDIO
GND
SWDIO
NC
NC
NC
Table 45-10.ꢀ10-pin JTAGICE3 Compatible Serial Wire Debug Interface
Header Signal Name
SWDCLK
SWDIO
Description
Serial wire clock pin
Serial wire bidirectional data pin
Target device reset pin, active low
RESET
VTG
Target voltage sense, should be connected to the device VDD
Ground
GND
45.7.3 20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals
should be connected as shown in the next figure with details described in the table.
DS40001882G-page 1116
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-13.ꢀ20-pin IDC JTAG Connector
VDD
20-pin IDC JTAG Connector
VCC
NC
NC
1
RESET
SWCLK
SWDIO
GND
GND
GND
GND
GND
GND
GND*
GND*
GND*
GND*
NC
SWDIO
SWDCLK
NC
NC
nRESET
NC
NC
Table 45-11.ꢀ20-pin IDC JTAG Connector
Header Signal Name Description
SWDCLK
SWDIO
RESET
VCC
Serial wire clock pin
Serial wire bidirectional data pin
Target device reset pin, active low
Target voltage sense, should be connected to the device VDD
Ground
GND
GND*
These pins are reserved for firmware extension purposes. They can be left open or
connected to GND in normal debug environment. They are not essential for SWD in
general.
45.8
USB Interface
The USB interface consists of a differential data pair (D+/D-) and a power supply (VBUS, GND). Refer to the
Electrical Characteristics for operating voltages which will allow USB operation.
Table 45-12.ꢀUSB Interface Checklist
Signal
Name
Recommended Pin Connection
Description
D+
•
•
•
The impedance of the pair should be matched on the PCB to minimize
reflections.
USB full speed / low
speed positive data
upstream pin
USB differential tracks should be routed with the same characteristics
(length, width, number of vias, etc.)
D-
USB full speed / low
speed negative data
upstream pin
Signals should be routed as parallel as possible, with a minimum
number of angles and vias
DS40001882G-page 1117
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Schematic Checklist
Figure 45-14.ꢀLow Cost USB Interface Example Schematic
VBUS
USB
Connector
USB
Differential
Data Line Pair
USB_D+
USB_D-
VBUS
D+
D-
GND
Shield
GND (Board)
It is recommended to increase ESD protection on the USB D+, D-, and VBUS lines using dedicated transient
suppressors. These protections should be located as close as possible to the USB connector to reduce the potential
discharge path and reduce discharge propagation within the entire system.
The USB FS cable includes a dedicated shield wire that should be connected to the board with caution. Special
attention should be paid to the connection between the board ground plane and the shield from the USB connector
and the cable.
Tying the shield directly to ground would create a direct path from the ground plane to the shield, turning the USB
cable into an antenna. To limit the USB cable antenna effect, it is recommended to connect the shield and ground
through an RC filter.
Figure 45-15.ꢀProtected USB Interface Example Schematic
USB Transient
VBUS
protection
USB
Connector
USB
Differential
Data Line Pair
USB_D+
USB_D-
VBUS
D+
D-
GND
Shield
RC Filter
(GND/Shield
Connection)
GND (Board)
DS40001882G-page 1118
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Conventions
46.
Conventions
46.1
Numerical Notation
Table 46-1.ꢀNumerical Notation
Symbol
165
Description
Decimal number
0b0101
'0101'
0x3B24
X
Binary number (example 0b0101 = 5 decimal)
Binary numbers are given without prefix if unambiguous
Hexadecimal number
Represents an unknown or don't care value
Z
Represents a high-impedance (floating) state for either a
signal or a bus
46.2
Memory Size and Type
Table 46-2.ꢀMemory Size and Bit Rate
Symbol
KB (kbyte)
MB (Mbyte)
GB (Gbyte)
b
Description
kilobyte (210 = 1024)
megabyte (220 = 1024*1024)
gigabyte (230 = 1024*1024*1024)
bit (binary '0' or '1')
byte (8 bits)
B
1kbit/s
1,000 bit/s rate (not 1,024 bit/s)
1,000,000 bit/s rate
1,000,000,000 bit/s rate
32 bit
1Mbit/s
1Gbit/s
word
half-word
16 bit
46.3
Frequency and Time
Table 46-3.ꢀFrequency and Time
Symbol
kHz
Description
1 kHz = 103 Hz = 1,000 Hz
1 KHz = 1,024 Hz, 32 KHz = 32,768 Hz
1 MHz = 106 Hz = 1,000,000 Hz
1 GHz = 109 Hz = 1,000,000,000 Hz
second
KHz
MHz
GHz
s
DS40001882G-page 1119
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Conventions
...........continued
Symbol
Description
millisecond
microsecond
nanosecond
ms
µs
ns
46.4
Registers and Bits
Table 46-4.ꢀRegister and Bit Mnemonics
Symbol
R/W
R
Description
Read/Write accessible register bit. The user can read from and write to this bit.
Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W
Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BIT
Bit names are shown in uppercase. (Example ENABLE)
FIELD[n:m]
Reserved
A set of bits from bit n down to m. (Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}
Reserved bits are unused and reserved for future use. For compatibility with future devices,
always write reserved bits to zero when the register is written. Reserved bits will always return
zero when read.
Reserved bit field values must not be written to a bit field. A reserved value will not be read from
a read-only bit field.
PERIPHERALi
Reset
If several instances of a peripheral exist, the peripheral name is followed by a number to indicate
the number of the instance in the range 0-n. PERIPHERAL0 denotes one specific instance.
Value of a register after a power Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR
Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing
a read-modify-write operation. These registers always come in pairs. Writing a ‘1’ to a bit in the
CLR register will clear the corresponding bit in both registers, while writing a ‘1’ to a bit in the
SET register will set the corresponding bit in both registers. Both registers will return the same
value when read. If both registers are written simultaneously, the write to the CLR register will
take precedence.
DS40001882G-page 1120
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Acronyms and Abbreviations
47.
Acronyms and Abbreviations
The below table contains acronyms and abbreviations used in this document.
Table 47-1.ꢀAcronyms and Abbreviations
Abbreviation
AC
Description
Analog Comparator
ADC
Analog-to-Digital Converter
Address
ADDR
AES
Advanced Encryption Standard
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
AMBA Advanced Peripheral Bus
Analog reference voltage
Boot Lock Bit
AHB
®
AMBA
APB
AREF
BLB
BOD
CAL
Brown-out Detector
Calibration
CC
Compare/Capture
CCL
Configurable Custom Logic
Clock
CLK
CRC
CTRL
DAC
DAP
Cyclic Redundancy Check
Control
Digital-to-Analog Converter
Debug Access Port
DFLL
DPLL
DMAC
DSU
EEPROM
EIC
Digital Frequency Locked Loop
Digital Phase Locked Loop
DMA (Direct Memory Access) Controller
Device Service Unit
Electrically Erasable Programmable Read-Only Memory
External Interrupt Controller
Event System
EVSYS
FDPLL
GCLK
GND
GPIO
I2C
Fractional Digital Phase Locked Loop, also DPLL
Generic Clock Controller
Ground
General Purpose Input/Output
Inter-Integrated Circuit
IF
Interrupt flag
INT
Interrupt
DS40001882G-page 1121
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Acronyms and Abbreviations
...........continued
Abbreviation
Description
MBIST
MEM-AP
MTB
Memory built-in self-test
Memory Access Port
Micro Trace Buffer
NMI
Non-maskable interrupt
Nested Vector Interrupt Controller
Non-Volatile Memory
Non-Volatile Memory Controller
Oscillator
NVIC
NVM
NVMCTRL
OSC
PAC
Peripheral Access Controller
Program Counter
PC
PER
Period
PM
Power Manager
POR
PORT
PTC
Power-on reset
I/O Pin Controller
Peripheral Touch Controller
Pulse Width Modulation
Random-Access Memory
Reference
PWM
RAM
REF
RTC
Real-Time Counter
RX
Receiver/Receive
SEEP
SERCOM
SMBus™
SP
SmartEEPROM Page
Serial Communication Interface
System Management Bus
Stack Pointer
SPI
Serial Peripheral Interface
Static Random-Access Memory
Supply Controller
SRAM
SUPC
SWD
TC
Serial Wire Debug
Timer/Counter
TCC
Timer/Counter for Control Applications
True Random Number Generator
Transmitter/Transmit
Ultra low-power
TRNG
TX
ULP
USART
USB
Universal Synchronous and Asynchronous Serial Receiver and Transmitter
Universal Serial Bus
DS40001882G-page 1122
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Acronyms and Abbreviations
...........continued
Abbreviation
Description
VDD
Common voltage to be applied to VDDIO, VDDIN and VDDANA
Digital supply voltage
VDDIN
VDDIO
VDDANA
VREF
WDT
Digital supply voltage
Analog supply voltage
Voltage reference
Watchdog Timer
XOSC
Crystal Oscillator
DS40001882G-page 1123
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
48.
Data Sheet Revision History
Page numbers listed in this section refer to this document. The revision listed in this section refers to the document
revision.
48.1
Revision G - April 2021
This revision includes the updates as listed in the following table, and numerous typographical corrections throughout
the document.
Section
Description
General
The SPI, I2S, and I2C standards use the terminology "Master" and "Slave". The equivalent
Microchip terminology used in this document is "Host" and "Client" respectively.
These terms have been updated throughout this document for this revision.
Features
Updated RWW to RWWEE for Memories
Ordering
Updated RWW to RWWEE in the Device Variant description
Information
Pinout
Updated the following Pinouts to accurately display the RESET pin
•
•
•
•
•
QFN48
QFN32 / TQFP32
UFBGA64
WLCSP45
WLCSP35
I/O Multiplexing
•
•
•
Added a new notes to table 7-1 for SERCOM and TCC3 availability
Added a new note to table 7-2 for TCC3 availability
Removed erroneous text from the header of Table 7-5 in SERCOM I2C Pins
Product Mapping
Memories
Updated RWW to RWWEE in the figure
•
•
•
Updated EEPROM and RWWEE text in Embedded Memories
Updated RWW to RWWEE in all the tables in Physical Memory Map
Updated Table 10-7 in NVM User Row Mapping to display text for Emulation
Processor and
Architecture
•
•
Updated the Addresses of the bits in SRAM Quality of Service
Updated the following registers, changing clear to set:
– PCA0 Register WPSET
– PCA1 Register WPSET
– PCA2 Register WPSET
DSU
•
•
Added verbiage for RWWEE Emulation to Chip Erase
Updated table 13-3 in 32-bit Cyclic Redundancy Check CRC32 with proper capitalization
on Emulation
•
•
Updated table 13-6 in System Services Availability when Accessed Externally and Device
is Protected with the correct RWWEE verbiage
Updated the DEVSEL bit of the DID Register with information for Device identification
Clock System
GCLK
Updated Read Request with new verbiage for the READREQ.RCONT and READREQ.RREQ
bits
Updated the GENDIV Register with a new Register property, and added a new column for the
Maximum Division Factor to the table for the DIV bit.
DS40001882G-page 1124
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
Updated the following registers:
– XOSC with new verbiage for the AMPGC and GAIN bits
– DFLLCTRL - removed erroneous RUNSTDBY bit
SYSCTRL
•
RTC
Updated the Overview with new verbiage for clock sources selectable through the GCLK.
DMAC
•
Updated the following registers:
– BASEADDR with new text for the bitfield BASEADDR
– WRBADDR with new text for the bitfield WRBADDR
– SRCADDR with new text for the bitfield SRCADDR
– DSTADDR with new text for the bitfield DSTADDR
– DESCADDR bitfield was updated for 64 bit alignment in the DESCADDR register
EIC
Updated the EXTINTx bit of the INTENCLR register to read “disables the external interrupt.”
NVMCTRL
•
•
•
•
Updated the Overview with new text for the EEPROM Emulation array
Updated Memory Organization with new EEPROM Emulation verbiage
Updated NVM User Configuration with new EEPROM Emulation verbiage
Updated the following registers:
– PARAM
– The ADDR bit of the ADDR Register was updated with new verbiage
– The LOCK bit of the LOCK Register was updated with the correct reset value
EVSYS
•
•
Updated Features with new event user verbiage
Updated the CHSTATUS Register with a new Reset value for the USRRDY bitfield
SERCOM I2C
•
•
Updated the Signal Description with a cross reference to the proper I/O Multiplexing table
In DMA, Interrupts and Events, erroneous information referring to the TX FIFO and RX
FIFO was removed from table 28-1 and table 28-2
•
•
•
In Interrupts erroneous information regarding the RX FIFO and TX FIFO was removed
Updated the SYNCBUSY Register to remove the SYSOP bitfield
Updated the DATA Register with a new register Property and added a note to the DATA
Bitfield
I2S
TC
Added new slotsize information to PDM Reception.
Updated the RCONT bit of the READREQ Register with new verbiage for clearing and reading
the RREQ and RCONT bits.
USB
ADC
Updated the SPEED Bitfield of the STATUS Register with the proper allocation of low-speed
and full-speed mode.
•
•
Updated the Block Diagram to properly display INTVCC0/1, and updated the note
Updated the Note for the REFSEL bit of the REFCTRL Register
DAC
Updated the CTRLB Register with a new note for the REFSEL bitfield.
DS40001882G-page 1125
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
Electrical
Characteristics at
85°C
•
•
•
In Maximum Clock Frequencies, table 37-7 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 37-24
– 37-25
– 37-26
•
•
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 37-32
– 37-34
– 37-35
Updated table 37-38 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
Electrical
Characteristics at
105°C
•
•
•
In Maximum Clock Frequencies, table 38-4 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 38-10
– 38-11
– 38-12
•
•
Updated table 38-14 in Performance with the Hardware Offset and Gain Correction by
applying the Conditions value to the whole column
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 38-15
– 38-16
– 38-17
DS40001882G-page 1126
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
Electrical
Specifications at
125°C
•
•
•
In Maximum Clock Frequencies, table 39-4 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 39-13
– 39-14
– 39-15
– 39-16
– 39-17
– 39-18
•
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 39-19
– 39-20
– 39-22
– 39-23
AEC-Q100 125°C
Specifications
•
•
•
In Maximum Clock Frequencies, table 40-7 and 40-9 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 40-24
– 40-25
– 40-26
– 40-27
•
•
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 40-30
– 40-32
– 40-33
Updated table 40-36 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
DS40001882G-page 1127
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
SAM DA1
Electrical
Characteristics
•
•
•
In Maximum Clock Frequencies, table 41-6 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 41-23
– 41-24
– 41-25
•
•
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 41-28
– 41-30
Updated table 41-32 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
Appendix B
Packaging
Added a new Appendix for ISELED Specifications.
The following packages were updated with new drawings:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64TQFP
64 pin QFN
64 Lead QFN with Sawn Wettable Flanks
64-ball UFBGA
48 pin TQFP
48 pin QFN
48 lead QFN with Sawn Wettable Flanks
45-ball WLCSP
32 pin TQFP
32 pin QFN
32 lead QFN with Sawn Wettable Flanks
35-ball WLCSP (Device Variant B)
35-ball WLCSP (Device Variant C)
35-ball WLCSP (Device Variant D)
48.2
Revision F - March 2020
This revision includesthe updates as listed in the following table, and several typographical corrections throughout the
document.
Section
Description
Appendix A
Packaging Information
DAC
Added a new appendix SIL 2 Enabled Functional Safety Devices
Added ‘35-ball WLCSP (Device variant D)’
•
•
Updated the INTENSET register, changed disable to enable for interrupts.
Updated the SYNCRDY bit of the INTENSET Register.
Added information about internal 1.0V buffered reference voltage.
ADC
Added information about internal 1.0V buffered reference voltage.
Updated CALIB register description.
DS40001882G-page 1128
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
SAM DA1 Electrical
Characteristics
Updated I2C Pins Characteristics in I2C Configuration in I2C Pins.
Updated label for internal 1.1V Bandgap Reference
Added information about internal 1.0V buffered reference voltage for ADC and DAC.
SERCOM I2C
Updated the SYSOP bit of the SYNCBUSY Register with the removal of erroneous
text
SERCOM SPI
EIC
Updated DOPO description.
Note added for CONFIGn registers.
DMAC
Updatetd Sleep mode operation description.
Removed reference to BOD12 registers. Added ENABLE bit in the VREG register.
Related linked added in the DID register description.
SYSCTRL
DSU
48.3
Revision E - January 2020
This revision encompasses changes made to combine the SAM D21 Data Sheet with the SAM DA1 Data Sheet to
improve readability and information access.
Section
Description
Block Diagram
Pinout
Added arrow between PORT and AHB-APB BRIDGE B.
Updated section titles
Product Mapping
PORT I/O Pin Controller
Updated the diagram to show the Internal Flash.
Corrected the WRCONFIG register to show the
DRVSTR bit.
SERCOM
Under Clock Generation - Baud-Rate Generator, the
table was updated with a new information and equations.
SERCOM USART
•
•
•
Information regarding FIFO was removed as it is
not supported on this device
The FIFOCLR bit was removed from the CTRLB
register
The FIFOSPACE and FIFOPTR registers were
removed
SERCOM SPI
•
•
•
Information on FIFO was removed as it is not
supported on this device
The FIFOCLR bit was removed from the CTRLB
register
The FIFOSPACE and FIFOPTR registers were
removed
DS40001882G-page 1129
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
SERCOM I2C
•
•
•
Information on FIFO was removed as it is not
supported on this device
The FIFOCLR bit was removed from the CTRLB
Slave Register
Bit fields RXFF and TXFE were removed from
the INTENCLR, INTENSET, and INTFLAG Slave
Registers
•
•
•
•
The LENERR bit was removed from the STATUS
Slave Register
Registers FIFOSPACE and FIFOPTR were
removed from the Slave Registers
The FIFOCLR bit was removed from the CTRLB
Master Register
Bit fields, RXFF and TXFE, were removed from
the INTENCLR, INTENSET, and INTFLAG Master
Registers
•
Registers FIFOSPACE and FIFOPTR were
removed from the Master Registers
Timer Counter (TC)
•
•
In Counter Mode, Count32 was updated with new
TC numbering
The register summaries for 8-bit Mode, 16-bit
Mode, and 32-bit Mode were updated to correctly
display
TCC
•
•
FCTRLA and FCTRLB had their naming corrected
In the WEXCTRL register the DTIEN bit had the
numbering updated
•
•
In the DRVCTRL register the numbering was
updated for the INVENx, NRVx, and NREx bits
In the EVCTRL register the numbering was updated
for the MCEOx, MCEIx, TCEIx, and TCINVx
Registers
•
In the INTENCLR, INTENSET, and INTFLAG
registers the numbering was updated for the MCx
bit
•
•
•
In the STATUS register the numbering was updated
for the CMPx and FAULTx bits
The PATT register was updated to properly display
the PGVx and PGEx bits
The PATTB register was updated to properly display
the PGVBx and PGEBx bits
USB
ADC
Updated cross references.
Updated the MUXPOS Bit table in the INPUTCTRL
register.
DS40001882G-page 1130
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
AC
•
•
Updated the STARTx bit numbering in the CTRLB
register
Updated the bit numbering for the COMPEIx,
COMPEOx, and WINEOx bits in the EVCTRL
register
•
Updated the bit numbering for the WINx, and
COMPx bits in the INTENCLR, INTENSET, and
INTFLAG registers
•
•
•
•
Updated the bit numbering for the WSTATEx and
STATEx bits in the STATUSA register
Updated the bit numbering for the READYx bit in
the STATUSB register
Updated the bit numbering for the WSTATEx and
STATEx bits in the STATUSC register
Updated the bit numbering for the WINTSELx and
WENx bits in the WINCTRL register
SAM DA1 Electrical Characteristics
Schematic Checklist
This section was migrated into this data sheet from the
original SAM DA1 data sheet.
Updated External Reset Circuit with changes to the
diagram External Reset Circuit Schematic.
Packaging Information
Updated Package Markings with a new marking
diagram.
48.4
Rev D - 9/2018
Configuration Summary
Product Mapping
RTC
Updated to Add new packages for device variant D.
Updated diagram.
Updated READREQ register tables.
Updated Channel Control B Register tables.
DMAC
24. EVSYS – Event System
•
•
Updated the Channel Register tables
Updated the User Register tables.
DAC
Updated the 35.3 Block Diagram to display ADC Input.
Updated Decoupling Requirements table.
Electrical Characteristics at 85°C
•
.
38. Electrical Characteristics at 105°C
39. Electrical Characteristics at 125°C
AEC-Q100 Electrical Characteristics at 125°C
Packaging Information
Updated the WLSCP 45-Ball Package diagram.
48.5
Rev. C – 06/2018
Features
•
Added Qualification AEC-Q100 Grade 1 (-40C to 125C).
DS40001882G-page 1131
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Ordering Information
Electrical Characteristics
Packaging Information
•
•
•
Added: under Package Grade Z = -40 – 125C Matte Sn Plating AEC-Q100
Updated with new chapter for AEC-Q100 Specifications.
Added QFN package drawings with wettable flanks.
48.6
Rev. B – 04/2018
General
•
•
This revision was updated to include the SAM D21EL and SAM D21GL Variant
information, which was released separately in DS40001883A. The SAM D21EL/SAM
D21GL Data Sheet (DS40001883A) is superseded by this revision (DS40001882B).
IOBUS start addressed is added which was missing in previous revision
(DS40001882A).
Electrical
Characteristics
•
•
Clarified ESR information for VDDCORE capacitor
Typo addressed for VDDIN capacitor value
DMA
AC
•
•
•
RUNSTDBY not supported, typo addressed
Continuous Mode SleepWalking figure is updated
ADC
Bandgap reference as input was omitted in previous version of the data sheet. It is
added in this version.
Packaging
Information
•
•
WLCSP package drawings updated
Thermal characteristic for 45-ball WLCSP & 64-pin UFBGA is added
48.7
Rev. A – 01/2017
General
•
Template: Updated from Atmel to Microchip template.
Document number: Changed from the Atmel 42181 to Microchip xxxxx.
Document revision letter reset to A.
•
•
•
ISBN number added.
Electrical
Characteristics
•
•
Die Revision F final characterization added.
37.7 Power Consumption: Added Standby typical numbers for Device Variant C / Die
Revision F.
•
•
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
Errata
New errata added:
– B
– Device Variant A: Errata reverence 15625, 15683, 15753 added.
– Device Variant B: Errata reverence 15625, 15683, 15753 added.
– Device Variant C: Errata reverence 15625, 15683, 15753 added.
39. Electrical
Characteristics at
125°C
•
•
Die Revision F final characterization is preliminary.
39.5 Power Consumption: Added Standby typical numbers for Device Variant C / Die
Revision F.
•
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
DS40001882G-page 1132
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
48.8
Rev. O – 12/2016
General
•
Introduced Device Variant C.
37. Electrical
Characteristics at 85℃
•
•
Die Revision F characterization is preliminary.
37.7 Power Consumption: Added Standby typical numbers for Device Variant C /
Die Revision F.
•
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
39. Electrical
Characteristics at 125°C
•
•
Die Revision F characterization is preliminary.
39.5 Power Consumption: Added Standby typical numbers for Device Variant C /
Die Revision F.
•
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
48.9
Rev. N – 10/2016
7. I/O Multiplexing and
Considerations
•
•
7.1 Multiplexed Signals: Updated table note 6 with information on PA24
and PA25.
10. Memories
10.3.1 NVM User Row Mapping: Added BOOTPROT default value for
WLCSP.
30. TC – Timer/Counter
•
•
30.5.3 Clocks: Corrected TC instance numbers.
30.6.2.4 Counter Mode: Corrected TC instance numbers.
37. Electrical Characteristics at 85℃
•
37.9.1 Normal I/O Pins: Added condition to Pull-up - Pull-down
resistance.
48.10 Rev. M – 09/2016
2. Configuration
Summary
•
•
Added information on number of pins for the SAM D21G WLCSP pakcage option.
SAM D21G is offered in 48 pin packages, while the WLCSP has 45 pins.
3. SAM D21 Ordering
Information(1)
Added information to the pin count explanation. For the The G letter indicates 48 pin
packages, while the WLCSP option is 45 pins.
•
•
ATSAMD21E18A-MFUT corrected to ATSAMD21E18A-MFT.
Device Identification:
– Removed C variants.
– Added device identification values for the devices in WLCSP packages. These
have separate device id's compared to the other package options.
18. WDT – Watchdog
Timer
•
18.5.7 Debug Operation: Removed the sentence "This peripheral can be forced
to continue operation during debugging." The WDT can not be forced to continue
operation in debug mode.
DS40001882G-page 1133
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
48.11 Rev. L – 09/2016
2. Configuration Summary
•
Added information on number of pins for the WLCSP pakcage. SAM D21E is
offered in 32 pin packages, while the WLCSP has 35 pins.
13. DSU - Device Service Unit
14. Clock System
•
•
•
13.11.5 Testing of On-Board Memories MBIST: Updated description.
14.5 Disabling a Peripheral: New section added.
17. SYSCTRL – System
Controller
17.8.5 XOSC.AMPGC bit description updated.
21. EIC – External Interrupt
Controller
•
21.6.6 Interrupts: Added note explaining how it works when the same
external interrupt (EXTINT) is common on sevral pins.
24. EVSYS – Event System
•
•
24.8.1 CTRL.SWRST: Added recommendation when doing a software reset.
28. SERCOM I2C – Inter-
Integrated Circuit
Corrected cross references in the Master 28.10.1 CTRLA.SCLSM and Slave
28.8.1 CTRLASCLSM bits.
31. TCC – Timer/Counter for
Control Applications
•
Value 0 in CAPTMIN mode is captured only in down-counting mode.
33. ADC – Analog-to-Digital
Converter
•
•
33.6.5 Differential and Single-Ended Conversions: Corrected register
reference from INPUTCTRL.DIFFMODE to CTRLB.DIFFMODE.
33.8.14 RESULT: Corrected description. Reference to "single-ended mode"
corrected to "single conversion mode".
37. Electrical Characteristics at
85℃
•
•
37.3 Absolute Maximum Ratings: Add ESD warnings.
37.16.5 I2S Timing: fM_SCKO and fM_SCKI values for VDD=1.8V moved from
the minimum to maximum column.
•
XOSC32K 37.13.2.1.1 Crystal Oscillator Characteristics: Removed
conditions from the parasitic capacitor loads CXIN32 and CXOUT32. The
difference between package types is so small that it can be ingored.
45. Schematic Checklist
•
•
45.5.3 External Real Time Oscillator: Added note on how to minimize jitter.
39. Electrical Characteristics at
125°C
39.4 Maximum Clock Frequencies: Corrected heading of Table 39-6 say
"Device Variant B".
48.12 Rev. K – 09/2016
3. SAM D21 Ordering
Information(1)
•
•
SAM D21E: Added Device Variant C ordering codes.
Device Identification: Added Device Variant C.
7. I/O Multiplexing and
Considerations
•
The section is reorgnaized:
– 7.2.3 SERCOM I2C Pins: Replaces the "Type" column in 7.1 Multiplexed
Signals.
– 7.2.4 GPIO Clusters: Moved from 37.3 Absolute Maximum Ratings.
– 7.2.5 TCC Configurations: Moved from the TCC 31.1 Overview.
16. PM – Power Manager
•
•
16.8.10 APBCMASK updated.
13. DSU - Device Service
Unit
13.11.6 System Services Availability when Accessed Externally and Device is
Protected: MBIST not available when device is operated from external address
range and device is protected.
DS40001882G-page 1134
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
19. RTC – Real-Time
Counter
•
19.6.3.3 Clock/Calendar (Mode 2): Example added on how the clock counter
works in calendar mode.
30. TC – Timer/Counter
•
•
30.8.1 CTRLA.WAVEGEN[1:0]: Name column updated.
31. TCC – Timer/Counter
for Control Applications
31.6.3.6 Non-Recoverable Faults: Removed references to Update Fault State
(UFS).
•
Removed the UFS bit from the INTENCLR, INTENSET, INTFLAG and STATUS
registers.
•
•
Removed RAMP2C from the 31.8.16 WAVE.WAVE[2:0]=0x3
37. Electrical
Characteristics at 85℃
37.3 Absolute Maximum Ratings: Updated VPIN minimum and maximum values.
(Related to the new Injection Current definition section)
•
•
37.5 Supply Characteristics: Corrected supply rise rates units from V/s to V/μs.
37.7 Power Consumption: Added power consumption numbers for Device
Variant C.
•
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics:
Added characterization data for Device Variant C.
•
•
•
•
Added 37.10 Injection Current section.
44. Packaging Information
Errata
Added 44.1.13 35 ball WLCSP (Device Variant C) package outline drawing.
Added errata for Device Variant C.
39. Electrical
Characteristics at 125°C
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics:
Added characterization data for Device Variant C.
•
39.2 Absolute Maximum Ratings: Updated VPIN minimum and maximum values.
(Related to the new Injection Current definition section)
48.13 Rev. J – 07/2016
3. SAM D21 Ordering
Information(1)
•
•
SAM D21E: Added ATSAMD21E15B-UUT.
30. TC – Timer/Counter
30.8.7 EVCTRL:EVACT[2:0] bit description updated: Time stamp capture
and pulse width capture removed
.
31. TCC – Timer/Counter for
Control Applications
•
•
31.6.3 Additional Features: Removed "Time-Stamp Capture" section.
31.8.9 EVCTRL:EVACT0[2:0] bit description updated: "Capture Overflow
times (Max value)" option removed (Related to Time-Stamp Capture).
Errata
•
Cleaned up errata section: Split between device variant A and B.
48.14 Rev. I – 03/2016
2. Configuration Summary
Updated value for Waveform output channels per TCC to 8/4/2.
7. I/O Multiplexing and Considerations
Added Note.6 for Table 7-1
10. Memories
DS40001882G-page 1135
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Table 10-1: Updated start address in Internal RWW section to from 0x00010000 to 0x00400000.
22. Nonvolatile Memory Controller (NVMCTRL)
Updated value from "NVM Base Address + 0x00010000" to "NVM Base Address + 0x00400000"in
Figure 22-3
26. SERCOM USART
Updated equation and added error calculation explained w/example in section
26.6.2.6.4 Asynchronous Operational Range
31. TCC – Timer/Counter for Control Applications:
Register Summary: Remove INTENCLR.SYNCRDY. Add MC0 (located in bit 0) for INTENSET and
INTFLAG, and left shift MC1, MC2 and MC3 for one bit. Therefore, MC0/1/2/3 are located in bit
0/1/2/3.
37. Electrical Characteristics at 85℃
Updated unit from 's' to 'us' in the following tables:
•
•
•
•
•
•
•
•
•
•
•
•
Table 39-11
Table 39-12
Table 39-24
Table 39-25
Table 39-37
Table 39-38
Table 39-39
Table 39-40
Table 39-45
Table 39-46
Table 39-47
Table 39-48
Update value and condition for Table 39-39 and Table 39-40
44. Packaging Information
Updated section 44.1.10 32-Pin VQFN .
48.15 Rev. H – 01/2016
20. DMAC – Direct Memory Access Controller
Updated bit description of the PRICTRL0.LVLPRIn [n=3..0].
22. Nonvolatile Memory Controller (NVMCTRL)
Updated description in 22.6.4.3 NVM Write: Removed reference to default NWM CTRLB.MANW
default value.
Updated reset value for CTRLB.MANW from 0 to 1. Note that this change is only applicable for
Device Variant B. Device Variant A will continue to have MANW bit reset value 0.
Updated reset value of the CTRLB register from 0x00000000 to 0x00000080.
Note that this change is change is only applicable for Device Variant B. Device Variant A will
continue to have CTRLB register reset value 0x00000000.
13. DSU - Device Service Unit
DS40001882G-page 1136
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Bit CTRL.CRC is write-only.
32. USB – Universal Serial Bus:
Register HSOFC.FLENCE description updated.
USB Device Registers - Common: Bit description of CTRLB .SPDCONF[1:0] updated.
44. Packaging Information
Updated values in 37.2.1 Thermal Resistance Data.
Corrected junction temperature equations: TC updated to TJ.
Updated package drawing for 44.1.12 35 ball WLCSP (Device Variant B): GPC corrected from GJP
to GJR. No other changes.
45. Schematic Checklist
Added 45.1.1 Operation in Noisy Environment.
Updated section 45.7 Programming and Debug Ports.
Updated recommended pin connection in 45.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug
Interface: Pull-up resistor value on SWCLK pin changed from 10kΩ to 1kΩ.
VDDCORE decoupling capacitor value updated from 100nF to 1μF in 45.2.1 Power Supply
Connections
48.16 Rev. G – 09/2015
17. SYSCTRL – System Controller:
Updated description in 17.6.7.1.5 Drift Compensation.
37. Electrical Characteristics at 85℃:
Removed note from Table 37-53 and Table 37-54.
44. Packaging Information:
Package drawing updated 44.1.8 45-ball WLCSP.
39. Electrical Characteristics at 125°C:
Removed note from:Table 39-39 and Table 39-40.
Updated power consumption units in Table 39-7.
48.17 Rev. F – 07/2015
Ordering Information
Added ATSAMD21E15B-UUT and ATSAMD21E16B-UUT ordering codes (WLCSP35 package
option).
4. Block Diagram
Updated system block diagram.
5. Pinout
Added pinout figure for 5.6.1 WLCSP35.
9. Product Mapping
DS40001882G-page 1137
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Updated Internal RWW section to start address from 0x00010000 to 0x00400000.
ADC - Analog-to-Digital Converter
References to AREFA and AREFB replaced with VREFA and VREFB respectively.
37. Electrical Characteristics at 85℃
Added GPIO cluster note to '37.3 Absolute Maximum Ratings.
Added 37.16.5 I2S Timing.
Updated BOD33 characteristics.
Added characterization data for Device Variant B.
Packaging Information
Updated ΘJC value from 3.1 to 15.0 °C/W for 32-pin QFN package in 37.2.1 Thermal Resistance
Data.
Added package drawing for 44.1.12 35 ball WLCSP (Device Variant B).
Schematic Checklist
45.2.1 Power Supply Connections:
VDDCORE decoupling capacitor value updated from 100nF to 1μF.
References to AREFA and AREFB replaced with VREFA and VREFB respectively.
Electrical Characteristics at 125C
Added I2S Timing.
Updated BOD33 characteristics.
Added characterization data for Device Variant B.
48.18 Rev. E – 02/2015
1. Description:
CoreMark score updated from 2.14 to 2.46 CoreMark/MHz.
3. SAM D21 Ordering Information(1):
Added Ordering codes for Device Variant B.
Added 125°C ordering codes for QFN and TQFP package options: SAMD21E, SAM D21E, SAM
D21G, and SAM D21J, and .
Added WLCSP package option for SAM D21G .
Added UFBGA package option for SAM D21J .
5. Pinout:
Added pinout figures for 5.1.2 UFBGA64 and 5.3.1 WLCSP45.
9. Product Mapping:
Updated Product Mapping figure with Internal RWW section block for Device Variant B.
10. Memories:
10.2 Physical Memory Map: Added start address for Internal Read While Write (RWW) section for
Device Variant B.
DS40001882G-page 1138
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
11. Processor And Architecture:
11.1.1 Cortex M0+ Configuration: Removed green connection dots between DMAC Data and AHB-
APB Bridge A and Bridge B.
22. Nonvolatile Memory Controller (NVMCTRL):
Introducing Read While Write (RWW) feature for Device Variant B.
Updated and New sections:
22.1 Overview
22.2 Features
22.3 Block Diagram
22.6.4.1 NVM Read
22.6.4.2 RWWEE Read
22.6.4.3 NVM Write
22.6.4.5 Erase Row
22.6.2 Memory Organization: Figure 22-2 updated.
Register Summary and 22.8 Register Description: 22.8.3 PARAM: Added RWWEEP[12:0] bits for
Device Variant B.
23. PORT - I/O Pin Controller:
23.6.3 I/O Pin Configuration: Removed reference to “open-drain”.
Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from W to R/W.
17. SYSCTRL – System Controller:
Removed references to XOSC32K and OSC32 1kHz clock output option:
- XOSC32K: 17.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
- OSC32K: 17.6.4 32 kHz Internal Oscillator (OSC32K) Operation
1kHz Output Enable (EN1K) bit set as reserved bit:
- Bit 4 in 17.8.6 XOSC32K
- Bit 3 in 17.8.7 OSC32K
37. Electrical Characteristics at 85℃:
37.11.3 Brown-Out Detectors Characteristics: Added Figure 37-3 and Figure 37-4 and updated
conditions in Table 37-21 and Table 37-23.
44. Packaging Information:
Added 44.1.4 64-ball UFBGA and 44.1.8 45-ball WLCSP package drawings.
45. Schematic Checklist
Updated description in 45.6 Unused or Unconnected Pins.
Errata:
DS40001882G-page 1139
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Device Variant A:
- Updated errata for revision A: Added Errata Reference 12291, 13507, 13574.
- Updated errata for revision B: Added Errata Reference 12291, 13507, 13574.
- Updated errata for revision C: Added Errata Reference 12291, 13507, 13574, 13951.
- Added errata for revision D.
Device Variant B:
- Added errata for revision E (Only available for SAMD21x15/16).
39. Electrical Characteristics at 125°C:
Electrical characteristics for 125°C added.
48.19 Rev. D – 09/2014
Block Diagram
NVM Controller bus connection changed from Master to Slave.
Clock System
Register Synchronization updated by splitting the section into Common synchronizer Register
Synchronization and Distributed Synchronizer Register Synchronization.
Electrical Characterstics
ADC
: Added note defining gain accuracy parameter in:
Characteristi - ADC Differential Mode, Differential Mode (Device Variant)
cs
ADC Single-Ended Mode, Single-Ended Mode (Device Variant A)
Errata
Updated errata for revision A, B and C: Added Errata Reference 13140, 12860.
48.20 Rev. C – 07/2014
37. Electrical Characteristics at 85℃
Updated condition for Rise time for both SDA and SCL (tR) in High Speed Mode: Cb changed from
1000pF to 100pF in Table 37-16.
Errata for revision C and E added.
Errata
48.21 Rev. B – 07/2014
General:
Introduced the new product family name: Atmel | SMART
Removed references to Clock Failure Detection.
Sub sections within chapters might been moved to other location within the chapter.
Typo corrections.
2. Configuration Summary
DS40001882G-page 1140
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Added 32KB Flash and 4KB SRAM options to SAM D21J and SAM D21G.
3. SAM D21 Ordering Information(1)
Added Tray to Carrier Type option for SAM D21E, SAMD 21G and SAMD21J ordering codes.
7. I/O Multiplexing and Considerations:
Updated REF function on PA03 and PA04 in Table 7-1:
PA03: DAC/VREFP changed to DAC/VREFA.
PA04: ADC VREFP changed to ADC/VREFB.
Updated COM function on PA30 and PA31:
PA30: CORTEX_M0P/SWCLK changed to SWCKL.
PA31: Added SWDIO.
10. Memories
Added a second note to Table 10-3.
Added Figure 10-1 Calibration and Auxiliary Space.
Added default values for fuses in Table 10-7 NVM User Row Mapping.
11. Processor And Architecture
MTB renamed from “Memory Trace Buffer” to “Micro Trace Buffer”.
13. DSU - Device Service Unit
Updated description of 13.11.3.1 Starting CRC32 Calculation.
Updated title of Table 13-6.
Added Device Selection table to Device Selection bit description the Device Identification register (DID.DEVSEL).
15. GCLK - Generic Clock Controller
Signal names updated in Device Clocking Diagram, 15.3 Block Diagram.
16. PM – Power Manager
Added figure Figure 16-2.
Register Summary:
Removed CFD bit from INTENCLR, INTENSET and INTFLAG.
Added PTC bit to APBCMASK register.
Register Description:
AHB Mask register (AHBMASK): Full bit names updated.
APBC Mask register (APBCMASK.PTC): Added PTC to bit 19.
CFD bit removed from INTENCLR, INTENSET and INTFLAG.
17. SYSCTRL – System Controller
Updated description of 17.6.6 8MHz Internal Oscillator (OSC8M) Operation.
FDPLL96M section reorganized and more integrated in the SYSCTRL chapter: Features, Signal Description and
Product Dependencies sub sections removed and integrated with the corresponding sections in SYSCTRL.
Register Summary: Added VREG register on address 0x3C - 0x3D.
Register Description:
Updated reset values in OSC8M.
Updated CALIB[11:0] bit description in OSC8M.
Updated LBYPASS bit description in DPLLCTRLB.
18. WDT – Watchdog Timer
DS40001882G-page 1141
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Updated description in 18.6.1 Principle of Operation: Introducing the bits used in Table 18-1.
Updated description in 18.6.2.1 Initialization.
Updated description in 18.6.2.4 Normal Mode.
Updated description in 18.6.2.5 Window Mode.
Updated description in 18.6.4 Interrupts.
WEN bit description in the Control register (CTRL.WEN) updated with information on enable-protection.
19. RTC – Real-Time Counter
19.6.9.1 Periodic Events: Bit names updated fro, PERx to PEREOx in example, Figure 19-4.
CLOCK.HOUR[4:0]: Updated Table 19-4
Mode 0 and Mode 2: CMPx bit renamed to CMP0 since only one CMP0 is available.
Bit description of CLOCK.HOUR[4:0]: Updated Table 19-4
ALARMn register renamed to ALARM0.
20. DMAC – Direct Memory Access Controller
Updated block diagram, 20.3 Block Diagram.
General updated description.
21. EIC – External Interrupt Controller
Register Summary and Register Description:
EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively.
INTENCLR, INTENSET, INTENFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16
respectively.
WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively.
CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31.
22. Nonvolatile Memory Controller (NVMCTRL)
CTRLB register: Removed table from NVM Read Wait States description (RWS[3:0])
23. PORT - I/O Pin Controller
Instances of the term “pad” replaced with “pin”.
Instances of the term “bundle” replaced with “group” and “interface”.
23.6.2 Basic Operation description updated.
Peripheral Multiplexing n (PMUX0) register: Offset formula updated.
24. EVSYS – Event System
Updated information in 24.2 Features.
24.5.2 Power Management updated: Description of on how event generators can generate an event when the
system clock is stopped moved to 24.6.4 Sleep Mode Operation.
24.5.3 Clocks updated: Renamed EVSYS channel dedicated generic clock from GCLK_EVSYS_x to
GCLK_EVSYS_CHANNELx.
Updated description in 24.6.1 Principle of Operation.
Updated description in sub sections of 24.6.2 Basic Operation.
Updated description in 24.6.3.1 The Overrun Channel n Interrupt.
Channel x Overrun bit description in 24.8.7 INTFLAG updated.
26. SERCOM USART
DS40001882G-page 1142
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
Updated description in 26.6.3.4 Break Character Detection and Auto-Baud.
Updated description in 26.6.3.7 Start-of-Frame Detection.
29. I2S - Inter-IC Sound Controller
Introducing Frame Synch Clock.
29.4 Signal Description: Added separate tables for Master-, Slave- and Controller mode.
Updated description in 29.5.7 Debug Operation and 29.5.8 Register Access Protection.
Updated description in 29.6.1 Principle of Operation.
Updated description in sub sections of 29.6.2 Basic Operation.
Updated formula in 29.6.2.1.3 MCKn Clock Frequency.
Updated formulas in 29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs.
Updated description in 29.6.6 PDM Reception.
Section on MONO removed and information included in 29.6.2 Basic Operation.
Updated property of Control A (CTRLA) register: Added Write-Synchronized
31. TCC – Timer/Counter for Control Applications
Updated description in 31.6.1 Principle of Operation.
Updated description in sub sections of 31.6.2 Basic Operation.
Updated description in sub sections of 31.6.3 Additional Features.
Updated description in 31.6.6 Synchronization.
Lock Update (LUPD) bit description updated in Control B Clear (CTRLBCLR) register.
Compare Channel Buffer x Busy (CCBx) bit description updated in Synchronization Busy (SYNCBUSY) register.
Event Control (EVCTRL) register property updated: Removed Enable-Protected.
Interrupt Enable Clear (INTENCLR), Interrupt Enable Set (INTENSET) and Interrupt Flag Status and Clear
(INTFLAG) registers: Updated bit description of FAULT0, FAULT1, FAULTA and FAULTB.
STATUS register bit descriptions updated.
Wave Control (WAVE) register property updated: Removed Read-Synchronized.
Pattern Buffer (PATTB) register: Updated property and bit description.
Waveform Control Buffer (WAVEB) register: Updated property and bit descriptions.
32. USB – Universal Serial Bus
Removed figures: Setup Transaction Overview, OUT Single Bank Transaction Overview, IN Single Bank
Transaction Overview and USB Host Communication Flow.
Updated description and graphics in sub sections of 32.6.2 USB Device Operations.
Updated description in sub sections of 32.6.3 Host Operations.
Pad Calibration (PADCAL) register: Access updated.
Upgraded bit descriptions.
Pipe Descriptor Structure: Updated register reset values.
33. ADC – Analog-to-Digital Converter
Register Description:
REFCTRL bit selection names updated from AREFA / AREFB to VREFA / VREFB in Table 33-5
35. DAC – Digital-to-Analog Converter
Updated block diagram and signal description: VREFP replaced with VREFB.
DS40001882G-page 1143
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
Data Sheet Revision History
37. Electrical Characteristics at 85℃
Updated VDD max from 3.63V to 3.63V in 37.3 Absolute Maximum Ratings.
Updated VDDIN pin from 57 to 56 in 7.2.4 GPIO Clusters.
37.7 Power Consumption: Updated Max values for STANDBY from 190.6μA and 197.3μA to 100μA in Table 37-8.
Added 37.8 Peripheral Power Consumption.
37.9 I/O Pin Characteristics: tRISE and tFALL updated with different load conditions depending on the DVRSTR
value in .
37.9 I/O Pin Characteristics: Correct typo IOL and IOH Max values inverted between PORT.PINCFG.DRVSTR=0
and 1, tRISE and tFALL updated with different load conditions depending on the DVRSTR value in Table 37-15.
37.11 Analog Characteristics: Removed note from Table 37-19.
37.11.4 Analog-to-Digital (ADC) characteristics: Added Max DC supply current (IDD), RSAMPLE maximum value
changed from 2.8kW to 3.5kW, Conversion time Typ value change to Min Value in Table 37-24.
37.11.5 Digital to Analog Converter (DAC) Characteristics: Added Max DC supply current (IDD) in Table 37-32.
37.11.6 Analog Comparator Characteristics: Added Min and Max values for VSCALE INL, DNL, Offset Error and
Gain Error in Table 37-36.
37.11.7 Bandgap and Internal 1.0V Reference Characteristics: Added Min and Max values, removed accuracy row
in Table 37-38.
37.16.3 SERCOM in I2C Mode Timing: Add Typical values for tR in Table 37-68.
Removed Asynchronous Watchdog Clock Characterization.
37.13.4 32.768kHz Internal oscillator (OSC32K) Characteristics: Added Max current consumption (IOSC32K) in Table
37-55.
Updated Crystal Oscillator Characteristics (XOSC32K) ESR maximum values, 37.13.2.1.1 Crystal Oscillator
Characteristics.
Updated Crystal Oscillator Characteristics (XOSC) ESR maximum value, 37.13.1.2 Crystal Oscillator
Characteristics from 348kΩ to 141kΩ.
37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics: Updated presentation, now separating
between Open- and Closed Loop Modes. Added fREF Min and Max values to Table 37-52.
Updated typical Startup time ( tSTARTUP) from 6.1µs to 8µs in Table 37-53.
Updated typical Fine lock time (tLFINE) from 700µs to 600µs in Table 37-53.
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added Current consumption
(IFDPLL96M), Period Jitter (Jp), Lock time (tLOCK), Duty cycles parameters in Table 37-58.
Added 37.15 USB Characteristics.
37.16 Timing Characteristics: Added SCK period (tSCK) Typ value in Table 37-65.
Errata
Errata for revision B added.
48.22 Rev. A - 02/2014
Initial released version of this data sheet.
DS40001882G-page 1144
Complete Datasheet
© 2021 Microchip Technology Inc.
SAM D21/DA1 Family
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DS40001882G-page 1145
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SAM D21/DA1 Family
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
ATSAMD 21 E 15 A
- M U T
Product Family
SAMD = General Purpose Microcontroller
Package Carrier
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
Pin Count
U = -40 - 85°C Matte Sn Plating
N = -40 - 105°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Z = -40 - 125°C Matte Sn Plating
E = 32 Pins (35 Pins for WLCSP)
G = 48 Pins (45 Pins for WLCSP)
J = 64 Pins
P(aAcECk-aQ1g0e0 QTuaylipfieed)
Flash Memory Density
18 = 256 KB
17 = 128 KB
16 = 64 KB
15 = 32 KB
A = TQFP(4)
M = QFN(4)
(2,3)
U = WLCSP
C = UFBGA
Device Variant
A = Default Variant
B = Added RWWEE support for 32 KB and 64 KB memory options
C = Silicon revision F for WLCSP45 package option
L = Pinout optimized for Analog and PWM
D = Silicon Revision G with RWWEE Support in 128KB memory options
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Note the following details of the code protection feature on Microchip devices:
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Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
DS40001882G-page 1146
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SAM D21/DA1 Family
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Tel: 86-532-8502-7355
China - Shanghai
Itasca, IL
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-9-744-7705
Italy - Milan
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
China - Suzhou
Tel: 86-186-6233-1526
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Novi, MI
Tel: 248-848-4000
Houston, TX
Vietnam - Ho Chi Minh
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Tel: 86-29-8833-7252
China - Xiamen
Tel: 84-28-5448-2100
Tel: 281-894-5983
Indianapolis
Tel: 86-592-2388138
China - Zhuhai
Noblesville, IN
Tel: 86-756-3210040
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
Tel: 44-118-921-5800
Fax: 44-118-921-5820
DS40001882G-page 1148
Complete Datasheet
© 2021 Microchip Technology Inc.
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