ATSAME54N19A_技术文档

SAM D5x/E5x Family

SAM D5x/E5x Family Silicon Errata and Data Sheet

Clarification

SAM D5x/E5x Family Errata

The SAM D5x/E5x family of devices that you have received conform functionally to the current Device

Data Sheet (DS60001507A), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision

IDs listed in SAM D5x/E5x Family Silicon Device Identification. The silicon issues are summarized in

the Table of Contents following this section.

The errata described in this document will be addressed in future revisions of the SAM D5x/E5x family

silicon.

Note:ꢀ This document summarizes all silicon errata issues from all revisions of silicon, previous as well

as current.

Table 1.ꢀSAM D5x/E5x Family Silicon Device Identification

Revision (DID.REVISION[3:0])

Part Number

Device Identification (DID[31:0])

A

ATSAME54P19A

ATSAME54P20A

ATSAME54N19A

ATSAME54N20A

ATSAME53N20A

ATSAME53N19A

ATSAME53J18A

ATSAME53J19A

ATSAME53J20A

ATSAME51N19A

ATSAME51N20A

ATSAME51J18A

ATSAME51J19A

ATSAME51J20A

ATSAMD51P20A

0x6184xx01

0x6184xx00

0x6184xx03

0x6184xx02

0x6183xx02

0x6183xx03

0x6183xx06

0x6183xx05

0x6183xx04

0x6181xx01

0x6181xx00

0x6181xx03

0x6181xx02

0x6181xx04

0x6006xx00

0x0

DS80000748B-page 1

SAM D5x/E5x Family

Revision (DID.REVISION[3:0])

A

Part Number

Device Identification (DID[31:0])

ATSAMD51P19A

ATSAMD51N19A

ATSAMD51N20A

ATSAMD51J18A

ATSAMD51J19A

ATSAMD51J20A

ATSAMD51G18A

ATSAMD51G19A

0x6006xx01

0x6006xx03

0x6006xx02

0x6006xx06

0x6006xx05

0x6006xx04

0x6006xx08

0x6006xx07

Data Sheet clarifications and corrections (if applicable) are located in Data Sheet Clarifications, following the

discussion of silicon issues.

Note:ꢀ Refer to the “Device Service Unit” chapter in the current Device Data Sheet (DS60001507A) for a

detailed information on Device Identification and Revision IDs for your specific device.

DS80000748B-page 2

Table of Contents

SAM D5x/E5x Family Errata............................................................................................1

1. Silicon Errata Issues..................................................................................................4

1.1. Analog-to-Digital Converter (ADC)...............................................................................................4

1.2. Analog Comparator (AC)..............................................................................................................4

1.3. Controller Area Network (CAN)....................................................................................................5

1.4. Clock Failure Detector (CFD).......................................................................................................6

1.5. Device.......................................................................................................................................... 7

1.6. Device Service Unit (DSU)...........................................................................................................8

1.7. 48 MHz Digital Frequency-Locked Loop (DFLL48M)...................................................................8

1.8. Digital-to-Analog Converter (DAC)...............................................................................................9

1.9. Direct Memory Access Controller (DMAC).................................................................................10

1.10. Ethernet MAC (GMAC)...............................................................................................................11

1.11. External Interrupt Controller (EIC)..............................................................................................11

1.12. Fractional Digital Phase-Locked Loop (FDPLL).........................................................................12

1.13. Non-Volatile Memory Controller (NVMCTRL).............................................................................12

1.14. I/O Pin Controller (PORT).......................................................................................................... 13

1.15. Serial Communication Interface (SERCOM)..............................................................................13

1.16. Timer/Counter (TC).................................................................................................................... 15

1.17. Timer/Counter for Control Applications (TCC)............................................................................15

2. Data Sheet Clarifications.........................................................................................16

2.1. Analog-to-Digital (ADC) Characteristics ....................................................................................16

2.2. Ethernet MAC (GMAC) ..............................................................................................................16

2.3. SERCOM ...................................................................................................................................16

2.4. Packaging Information................................................................................................................16

2.5. Digital-to-Analog (DAC)..............................................................................................................17

3. Appendix A: Revision History.................................................................................. 18

The Microchip Web Site................................................................................................ 19

Customer Change Notification Service..........................................................................19

Customer Support......................................................................................................... 19

Microchip Devices Code Protection Feature................................................................. 19

Legal Notice...................................................................................................................20

Trademarks................................................................................................................... 20

Quality Management System Certified by DNV.............................................................21

Worldwide Sales and Service........................................................................................22

DS80000748B-page 3

SAM D5x/E5x Family

1.

Silicon Errata Issues

The following issues apply to the SAM D5x/E5x Family of devices.

1.1

Analog-to-Digital Converter (ADC)

1.1.1

ADC

The ADC SYNCBUSY.SWTRIG gets stuck to '1' after wake-up from Standby Sleep mode.

Workaround

Ignore the ADC SYNCBUSY.SWTRIG status when waking up from Sleep mode.

Affected Silicon Revisions

A

X

1.1.2

ADC

ADC TUE/INL/DNL performance is not guaranteed in the following scenarios:

•

Sampling frequency is above 500 ksps

ADC VREF is different from VDDANA

Workaround

None.

Affected Silicon Revisions

A

X

1.2

Analog Comparator (AC)

1.2.1

AC

Enabling Hysteresis (COMPCTRLn.HYSTEN = 0x1) changes the threshold voltage (VTH-), which may

result in unexpected behavior of the Analog Comparator.

Workaround

None.

Affected Silicon Revisions

A

X

DS80000748B-page 4

SAM D5x/E5x Family

1.3

Controller Area Network (CAN)

1.3.1

CAN

When edge filtering is activated (CCCR.EFBI = 1) and when the end of the integration phase coincides

with a falling edge at the Rx input pin, it may occur that the CAN synchronizes itself incorrectly and does

not correctly receive the first bit of the frame. In this case, the CRC will detect that the first bit was

received incorrectly, it will rate the received FD frame as faulty, and an error frame will be send.

The issue only occurs when there is a falling edge at the Rx input pin (CAN_RX) within the last time

quantum (tq) before the end of the integration phase. The last time quantum of the integration phase is at

the sample point of the 11th recessive bit of the integration phase. When edge filtering is enabled, the bit

timing logic of the CAN sees the Rx input signal delayed by the edge filtering. When the integration phase

ends, edge filtering is automatically disabled. This affects the reset of the FD CRC registers at the

beginning of the frame. The Classical CRC register is not affected, hence this issue does not affect the

reception of Classical frames.

In CAN communication, the CAN module may enter an integrating state (either by resetting the

CCCR.INIT or by protocol exception event) while a frame is active on the bus. In this case, the 11

recessive bits are counted between the acknowledge bit and the following start of frame. All nodes have

synchronized at the beginning of the dominant acknowledge bit. This means that the edge of the following

start of frame bit cannot fall on the sample point, hence the issue does not occur. The issue occurs only

when the CAN is by local errors, mis-synchronized with regard to the other nodes.

Glitch filtering as specified in ISO 11898-1:2015 is fully functional.

Edge filtering was introduced for applications where the data bit time is at least 2-tq (of nominal bit time)

long. In that case, edge filtering requires at least two consecutive dominant time quanta before the

counter counting the 11 recessive bits for idle detection is restarted. This means edge filtering covers the

theoretical case of occasional 1-tq long dominant spikes on the CAN bus that would delay idle detection.

Repeated dominant spikes on the CAN bus would disturb all CAN communication, so the filtering to

speed up idle detection would not help network performance.

When this rare event occurs, the CAN sends an error frame and the sender of the affected frame

retransmits the frame. When the retransmitted frame is received, the CAN has left the integration phase

and the frame will be received correctly. Edge filtering is only applied during the integration phase; it is

never used during normal operation. Since the integration phase is very short with respect to "active

communication time", the impact on total error frame rate is negligible. The issue has no impact on data

integrity.

The CAN enters the integration phase under the following conditions:

•

When CCCR.INIT is set to '0' after start-up

After a protocol exception event (only when CCCR.PXHD = 0)

Scope:

The erratum is limited to FD frame reception when edge filtering is active (CCCR.EFBI = '1') and when

the end of the integration phase coincides with a falling edge at the Rx input pin.

Effects:

The calculated CRC value does not match the CRC value of the received FD frame and the CAN module

sends an error frame. After retransmission the frame is received correctly.

DS80000748B-page 5

SAM D5x/E5x Family

Workaround

Disable edge filtering or wait on retransmission in the event that this rare event occurs.

Affected Silicon Revisions

A

X

1.3.2

CAN

When NBTP.NTSEG2 is configured to zero (Phase_Seg2(N) = 1), and when there is a pending

transmission request, a dominant third bit of Intermission may cause the CAN to wrongly transmit the first

identifier bit dominant instead of recessive, even if this bit was configured as '1' in the Tx Buffer Element

of the CAN module.

Workaround

A phase buffer segment 2 of length '1' (Phase_Seg2(N) = 1) is not sufficient to switch to the first identifier

bit after the sample point in Intermission where the dominant bit was detected.

The CAN protocol according to ISO 11898-1 defines that a dominant third bit of Intermission causes a

pending transmission to be started immediately. The received dominant bit is handled as if the CAN has

transmitted a Start-of-Frame (SoF) bit.

The ISO 11898-1 specifies the minimum configuration range for Phase_Seg2(N) to be 2..8 tq. Therefore,

excluding a Phase_Seg2(N) of '1' will not affect CAN conformance.

Effects:

In case NBTP.NTSEG2 = 0, it may occur that the CAN transmits the first identifier bit dominant instead of

recessive.

Update configuration range of NBTP.NTSEG2 from 0..127 tq to 1..127 tq in the CAN documentation.

Affected Silicon Revisions

A

X

1.4

Clock Failure Detector (CFD)

1.4.1

CFD

When the CFD is enabled for the XOSC/XOSC32K oscillator and the oscillator input signal is stuck at 1,

the clock failure detection works correctly but the switch to the safe clock will fail.

Workaround

Two possible workarounds are:

1. If the main clock source itself comes from the XOSC/XOSC32K oscillator, the only workaround is

indirect (i.e., using the WDT in firmware and switch to safe clock source in firmware at WDT reset).

2. Because the clock failure detection is functional, once the STATUS.CLKFAIL is set, and if the

STATUS.CLKSW is not set, manually switch to safe clock from firmware by changing configurations

of the generic clock generators that use the XOSC/XOSC32K oscillator as a clock source to use

another source clock instead.

DS80000748B-page 6

SAM D5x/E5x Family

Affected Silicon Revisions

A

X

1.5

Device

1.5.1

Device

The internal pull-up of the RESET pin is not functional.

Workaround

An external 100K pull-up must be added on the RESET pin.

Affected Silicon Revisions

A

X

1.5.2

Device

The detection of a debugger probe may fail if the "BOD33 Disable" fuse is cleared (i.e., BOD33 is

enabled).

Workaround

To secure the detection of debugger probes, enable BOD33 using the SUPC.BOD33 register instead of

the "BOD33 Disable" fuse. The "BOD33 Disable" fuse must be kept set.

Affected Silicon Revisions

A

X

1.5.3

Device

VBAT mode is not functional.

Workaround

None.

Affected Silicon Revisions

A

X

1.5.4

Device

When the internal reference is used with the DAC and ADC, their outputs become non-linear when the

operating temperature is less than 0°C.

DS80000748B-page 7

SAM D5x/E5x Family

Workaround

The internal reference must be used only for positive temperatures (i.e., above 0°C).

Affected Silicon Revisions

A

X

1.6

Device Service Unit (DSU)

1.6.1

DSU

DSU CRC32 may never complete when targeting NVM memory space while the NVM cache is disabled.

Workaround

Be sure to always enable the NVM cache when performing a DSU CRC32 request targeting the NVM

memory space.

Affected Silicon Revisions

A

X

1.7

48 MHz Digital Frequency-Locked Loop (DFLL48M)

1.7.1

DFFL48M

If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the

locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if

the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be

false out of bounds interrupts.

Workaround

Check that lockbits, DFLLLCKC and DFLLLCKF, in the OSCCTRL Interrupt Flag Status and Clear

register (INTFLAG) are both set before enabling the DFLLOOB interrupt.

Affected Silicon Revisions

A

X

1.7.2

DFFL48M

In Close Loop mode, the STATUS.DFLLRDY bit does not rise before lock fine occurs. Therefore, the

information about DFLL ready to start Close Loop mode is not available.

Workaround

None.

DS80000748B-page 8

SAM D5x/E5x Family

Affected Silicon Revisions

A

X

1.7.3

DFFL48M

If the DFLL is disabled and then re-enabled, the DFLLVAL.FINE value is ignored by the DFLL module,

which will then start its lock fine process at another frequency.

Workaround

Before writing the final configuration in the DFLLCTRLB register, the DFLL module must be re-enabled in

Open Loop mode to read and rewrite the DFLLVAL register.

1. OSCCTRL->DFLLMUL.reg = X; // Write new DFLLMULL configuration

2. OSCCTRL.DFLLCTRLB.reg = 0; // Select Open loop configuration

3. OSCCTRL.DFLLCTRLA.bit.ENABLE = 1; // Enable DFLL

4. OSCCTRL.DFLLVAL.reg = OSCCTRL->DFLLVAL.reg; // Reload DFLLVAL register

5. OSCCTRL.DFLLCTRLB.reg = X; // Write final DFLL configuration

Affected Silicon Revisions

A

X

1.8

Digital-to-Analog Converter (DAC)

1.8.1

DAC

In Differential mode the smoothing of the output signal is not fully functional. Smoothing works normally in

Differential mode as long as the value of two consecutive data are both positive or negative. The behavior

is incorrect when the data changes from positive to negative or vice versa.

Workaround

None.

Affected Silicon Revisions

A

X

1.8.2

DAC

The selection of VDDANA as the DAC reference in DAC.CTRLB.REFSEL is non-functional.

Workaround

The VDDANA must be connected externally to a VREF pin and DAC.CTRLB.VREFAU must be selected.

DS80000748B-page 9

SAM D5x/E5x Family

Affected Silicon Revisions

A

X

1.8.3

DAC

No analog compare will be done on Comparator 0 (AC0) when using the DAC on negative input AIN1 and

on Comparator 1 (AC1) when using the DAC on negative input AIN3.

Workaround

Use the internal VDD scaler.

Affected Silicon Revisions

A

X

1.8.4

DAC

If the Interpolation mode is enabled (with filter integrated to the DAC), the last data from the filter is

missing, and therefore, the DAC final output value does not correspond to the DAC input value.

Although interrupt events are generated at the end of conversion (EOC), the EOC occurs before the final

value from the filter and is of no use in the application.

Workaround

None.

Affected Silicon Revisions

A

X

1.9

Direct Memory Access Controller (DMAC)

1.9.1

DMAC

When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may

occur upon enabling a channel with no linked descriptor or the second descriptor (index 1) of the channel

being enabled may be fetched by one of the already active channels using linked descriptors. These

errors may occur when a channel is being enabled during the link request of another channel and if the

channel number of the channel being enabled is lower than the channel already active.

Workaround

When enabling a channel while other channels using linked descriptors are already active, the channel

number of the new channel to enable must be greater than the other channel numbers.

DS80000748B-page 10

SAM D5x/E5x Family

Affected Silicon Revisions

A

X

1.10

Ethernet MAC (GMAC)

1.10.1 Ethernet Functionality in 64-pin Packages

Ethernet functionality in 64-pin packages is not available.

Workaround

None.

Affected Silicon Revisions

A

X

1.11

External Interrupt Controller (EIC)

1.11.1

EIC

When enabling EIC, SYNCBUSY.ENABLE is released before EIC is fully enabled. Edge detection can be

done only after three cycles of the selected GCLK (GCLK_EIC or CLK_ULP32K).

Workaround

None.

Affected Silicon Revisions

A

X

1.11.2

EIC

When the asynchronous edge detection is enabled, and the system is in Standby mode, only the first

edge will be detected. The following edges are ignored until the system wakes up.

Workaround

Use the asynchronous edge detection with debouncer enabled. It is recommended to set the

DPRESCALER.PRESCALER and DPRESCALER.TICKON to have the lowest frequency possible. To

reduce the power consumption, set the EIC GCLK frequency as low as possible or select the ULP32K

clock (EIC CTRLA.CKSEL set).

Affected Silicon Revisions

A

X

DS80000748B-page 11

SAM D5x/E5x Family

1.12

Fractional Digital Phase-Locked Loop (FDPLL)

1.12.1 FDPLL

When using a low frequency input clock on FDPLLn, several FDPLL unlocks may occur while the output

frequency is stable.

Workaround

When using a low frequency input clock on FDPLLn, enable the lock bypass feature to avoid FDPLL

unlocks.

Affected Silicon Revisions

A

X

1.12.2 FDPLL

When changing the FDPLL ratio in DPLLnRATIO register on-the-fly, STATUS.DPLLnLDRTO will not be

set when the ratio update will be completed.

Workaround

Wait for the interruption flag INTFLAG.DPLLnLDRTO instead.

Affected Silicon Revisions

A

X

1.13

Non-Volatile Memory Controller (NVMCTRL)

1.13.1 NVMCTRL

NVM reads may be corrupted when mixing NVM reads with Page Buffer writes.

Workaround

Disable cache lines before writing to the Page Buffer when executing from NVM or reading data from

NVM while writing to the Page Buffer. Cache lines are disabled by writing a one to CTRLA.CACHEDIS0

and CTRLA.CACHEDIS1.

Affected Silicon Revisions

A

X

1.13.2 NVMCTRL

The device does not start correctly under temperatures below -20°C.

Workaround

Reset the device (RESET pin) during power-up until VDDIO has reached 2V.

DS80000748B-page 12

SAM D5x/E5x Family

A

X

1.13.3 NVMCTRL

Flash Write/Erase operations are not functional under temperatures below -20°C.

Workaround

VDDIO must be supplied at 2V minimum to guarantee Flash Write/Erase operations down to -40°C .

A

X

1.14

I/O Pin Controller (PORT)

1.14.1 PORT

PORT read/write attempts on non-implemented registers, including addresses beyond the last

implemented register group (PA, PB,...), do not generate a PAC protection error.

Workaround

None.

Affected Silicon Revisions

A

X

1.14.2 PORT Pull-Up/Pull-Down Resistor

The pull-down on PA24/PA25 are activated during power-up and when Sleep mode is OFF. On all other

pins, except those in the VSWOUT cluster, the pull-up is activated during power-up and when Sleep

mode is OFF.

Workaround

None.

Affected Silicon Revisions

A

X

1.15

Serial Communication Interface (SERCOM)

1.15.1 SERCOM

In USART Auto-baud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing

(FERR) errors.

DS80000748B-page 13

SAM D5x/E5x Family

Workaround

None.

Affected Silicon Revisions

A

X

1.15.2 SERCOM-I2C

SDAHOLD timing of the SERCOM-I2C does not match the value shown in the current device data sheet.

The following table shows the specified and real values of SDA Hold timing.

Table -1.ꢀSDA Hold Timing

SDA Hold Time Value

Specified SDA Hold Time

Disabled

Real SDA Hold Time

Disabled

0x0

0x1

0x2

0x3

50 ns to 100 ns

300 ns to 600 ns

400 ns to 800 ns

20 ns to 40 ns

100 ns to 250 ns

150 ns to 350 ns

Workaround

None.

Affected Silicon Revisions

A

X

1.15.3 SERCOM

When 32-bit Extension mode is enabled and data to be sent is not in multiples of 4 bytes (which means

the length counter must be enabled), additional bytes will be sent over the line.

Workarounds

Use any one of the following workarounds:

1. Write the Inter-Character Spacing bits (CTRLC.ICSPACE) to a non-zero-value.

2. Do not use length counter in firmware by keeping data to be sent is in multiples of 4 bytes.

Affected Silicon Revisions

A

X

1.15.4 SERCOM-UART

The TXINV and RXINV bits in the CTRLA register have inverted functionality.

DS80000748B-page 14

SAM D5x/E5x Family

Workarounds

In software, interpret the TXINV bit as a functionality of RXINV, and conversely, interpret the RXINV bit as

a functionality of TXINV.

Affected Silicon Revisions

A

X

1.16

Timer/Counter (TC)

1.16.1 TC

When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, the SYNCBUSY flag is released before

the PERBUF/CCBUFx register is restored to its appropriate value.

Workaround

Clear successively twice the STATUS.PERBUFV/STATUS.CCBUFx flag to ensure that the PERBUF/

CCBUFx register value is restored before updating it.

Affected Silicon Revisions

A

X

1.17

Timer/Counter for Control Applications (TCC)

1.17.1 TCC

Using TCC in Dithering mode with external retrigger events can lead to an unexpected stretch of right-

aligned pulses, or shrink of left-aligned pulses.

Workaround

Do not use retrigger events or actions when the TCC module is configured in Dithering mode.

Affected Silicon Revisions

A

X

DS80000748B-page 15

SAM D5x/E5x Family

2.

Data Sheet Clarifications

The following typographic corrections and clarifications are to be noted for the latest version of the device

data sheet (DS60001507A):

2.1

Analog-to-Digital (ADC) Characteristics

Operating Conditions

In Table 54-23. Operating Conditions, the following note pertaining to the V_CMINparameter was omitted.

Note:ꢀ Respect the input common mode voltage using the following equations (where VCM_IN is the

input channel common mode voltage):

When CTRLC.R2R = 0:

•

VCM_IN < 0.75*VREF

VCM_IN > Maximum of (0, VREF-VDDANA-0.7, 1.25*VREF-VDDANA)

2.2

2.3

Ethernet MAC (GMAC)

IEEE 802.3AZ Energy Efficient Support

The Ethernet MAC supports IEEE 802.3AZ energy efficient standard. AF/PoE is an Ethernet PHY and

application hardware dependent feature. The data sheet will be updated to cover this clarification.

SERCOM

Baud Rate Equations

In Table 33-2. Baud Rate Equations, the Asynchronous Fractional mode equation was omitted.

The following table shows the missing equation.

Table 1-1.ꢀBaud Rate Equations

Operating Mode Condition

Baud Rate (Bits Per Second)

BAUD Register Value Calculation

Asynchronous

Fractional

ꢀ

ꢅꢆꢀ

ꢇꢈ

8

ꢅꢆꢀ

ꢉꢊꢇ

ꢀ

ꢁꢂꢃꢄ

≤

ꢀ

ꢁꢂꢃꢄ

=

ꢁꢂꢃꢄ =

−

S

S ꢁꢂꢃꢄ + ꢇꢈ/ 8

ꢋ × ꢀ

ꢁꢂꢃꢄ

SERCOM in SPI Mode Timing

In Table 54-51. SPI Timing Characteristics and Requirements, the maximum SPI clock frequency should

be selected as the minimum of Reception and Transmission mode.

2.4

Packaging Information

TQFP 64-pin Package

The TQFP 64-pin package drawing was omitted from the data sheet.

A PDF of the TQFP 64-pin package, Microchip Drawing C04-085C, is available for download from the

following URL:

DS80000748B-page 16

SAM D5x/E5x Family

http://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en596496

2.5

Digital-to-Analog (DAC)

INL & DNL in Table 54-28

Table 54-28 has a note but it is omitted for INL and DNL symbols, this omitted note is shown below.

Note 1 : Specified in a restricted temperature range [0-85°C ] when 1V internal reference is used.

INL & DNL in Table 54-29

Table 54-29 has a note but it is omitted for INL and DNL symbol, this omitted note is shown below

Note 1 : Specified only at Temp > 0°C when 1V internal reference is used.

DS80000748B-page 17

SAM D5x/E5x Family

3.

Appendix A: Revision History

Rev. A (7/2017)

Initial release of this document.

Rev. B (10/2017)

This revision includes the following additions:

Silicon Issues

•

Ethernet Functionality in 64-pin Packages

Data Sheet Clarifications

•

ADC Operating Conditions

GMAC IEEE 802.3AZ Energy Efficient Support

SERCOM Baud Rate Equations

SERCOM in SPI Mode Timing

TQFP 64-pin Package

DAC Operating Conditions

DS80000748B-page 18

SAM D5x/E5x Family

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a means to make files and information easily available to customers. Accessible by using your favorite

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To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on

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Customer Support

Users of Microchip products can receive assistance through several channels:

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Distributor or Representative

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Technical support is available through the web site at: http://www.microchip.com/support

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the

operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is

engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

DS80000748B-page 19

SAM D5x/E5x Family

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their

code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the

code protection features of our products. Attempts to break Microchip’s code protection feature may be a

violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software

or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for

your convenience and may be superseded by updates. It is your responsibility to ensure that your

application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS

CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life

support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting

from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,

BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,

SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight

Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,

chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient

Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL

ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

DS80000748B-page 20

SAM D5x/E5x Family

ISBN: 978-1-5224-2215-0

Quality Management System Certified by DNV

ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer

fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures are for its PIC^®MCUs and dsPIC^®

DSCs, KEELOQ^®code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design and manufacture of development

systems is ISO 9001:2000 certified.

DS80000748B-page 21

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

China - Xiamen

Austria - Wels

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Tel: 86-756-3210040

Fax: 86-756-3210049

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 852-2943-5100

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Fax: 45-4485-2829

Finland - Espoo

Tel: 358-9-4520-820

France - Paris

Web Address:

www.microchip.com

Atlanta

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

France - Saint Cloud

Tel: 33-1-30-60-70-00

Germany - Garching

Tel: 49-8931-9700

Duluth, GA

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

China - Nanjing

Tel: 512-257-3370

Boston

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Japan - Tokyo

Germany - Haan

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-67-3636

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Korea - Daegu

Itasca, IL

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 972-9-744-7705

Italy - Milan

Novi, MI

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Tel: 248-848-4000

Houston, TX

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 281-894-5983

Indianapolis

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-7289-7561

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Tel: 86-21-3326-8000

Fax: 86-21-3326-8021

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

China - Wuhan

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Poland - Warsaw

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS80000748B-page 22


型号：	ATSAME54N19A
厂家：	MICROCHIP
描述：	SAM D5x/E5x Family Silicon Errata and Data Sheet Clarification
文件：	总22页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATSAME54N19A [MICROCHIP]

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