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ATTINY2313V-10PU

更新时间：2025-07-01 18:41:29

品牌：MICROCHIP

描述：IC MCU 8BIT 2KB FLASH 20DIP

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ATTINY2313V-10PU 概述

IC MCU 8BIT 2KB FLASH 20DIP 微控制器微控制器

ATTINY2313V-10PU 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	0.300 INCH, GREEN, PLASTIC, MS-001AD, DIP-20
Reach Compliance Code：	compliant	Factory Lead Time：	13 weeks
风险等级：	1.69	具有ADC：	NO
其他特性：	OPERATES AT 1.8 V MINIMUM SUPPLY AT 4 MHZ	地址总线宽度：
位大小：	8	CPU系列：	AVR RISC
最大时钟频率：	10 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e3
长度：	25.7385 mm	湿度敏感等级：	1
I/O 线路数量：	18	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
PWM 通道：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	245	电源：	2/5 V
认证状态：	Not Qualified	RAM（字节）：	128
ROM（单词）：	2048	ROM可编程性：	FLASH
座面最大高度：	5.334 mm	速度：	10 MHz
子类别：	Microcontrollers	最大压摆率：	6 mA
最大供电电压：	5.5 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC	Base Number Matches：	1

ATTINY2313V-10PU 数据手册

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Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

• Data and Non-volatile Program and Data Memories

– 2K Bytes of In-System Self Programmable Flash

Endurance 10,000 Write/Erase Cycles

– 128 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 128 Bytes Internal SRAM

8-bit

Microcontroller

with 2K Bytes

In-System

Programmable

Flash

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes

– Four PWM Channels

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– USI – Universal Serial Interface

– Full Duplex USART

• Special Microcontroller Features

– debugWIRE On-chip Debugging

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low-power Idle, Power-down, and Standby Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

ATtiny2313/V

Summary

• I/O and Packages

– 18 Programmable I/O Lines

– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF

• Operating Voltages

– 1.8 – 5.5V (ATtiny2313V)

– 2.7 – 5.5V (ATtiny2313)

• Speed Grades

– ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V

– ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V

• Typical Power Consumption

– Active Mode

1 MHz, 1.8V: 230 µA

32 kHz, 1.8V: 20 µA (including oscillator)

– Power-down Mode

< 0.1 µA at 1.8V

Rev. 2543MS–AVR–10/16

Figure 1. Pinout ATtiny2313

Configurations

PDIP/SOIC

VCC

(RESET/dW) PA2

(RXD) PD0

PB7 (UCSK/SCL/PCINT7)

PB6 (MISO/DO/PCINT6)

PB5 (MOSI/DI/SDA/PCINT5)

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

PB0 (AIN0/PCINT0)

PD6 (ICP)

(TXD) PD1

(XTAL2) PA1

(XTAL1) PA0

(CKOUT/XCK/INT0) PD2

(INT1) PD3

(T0) PD4

(OC0B/T1) PD5

GND

MLF

(TXD) PD1

XTAL2) PA1

PB5 (MOSI/DI/SDA/PCINT5)

PB4 (OC1B/PCINT4)

PB3 (OC1A/PCINT3)

PB2 (OC0A/PCINT2)

PB1 (AIN1/PCINT1)

(XTAL1) PA0

(CKOUT/XCK/INT0) PD2

(INT1) PD3

NOTE: Bottom pad should be soldered to ground.

Overview

The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Block Diagram

Figure 2. Block Diagram

XTAL1

XTAL2

PA0 - PA2

PORTA DRIVERS

DATA DIR.

REG. PORTA

DATA REGISTER

PORTA

INTERNAL

CALIBRATED

OSCILLATOR

VCC

GND

8-BIT DATA BUS

INTERNAL

OSCILLATOR

STACK

POINTER

TIMING AND

CONTROL

PROGRAM

COUNTER

WATCHDOG

TIMER

RESET

MCU CONTROL

PROGRAM

FLASH

SRAM

ON-CHIP

DEBUGGER

MCU STATUS

INSTRUCTION

GENERAL

PURPOSE

TIMER/

COUNTERS

INSTRUCTION

DECODER

INTERRUPT

UNIT

EEPROM

USI

CONTROL

LINES

ALU

STATUS

PROGRAMMING

LOGIC

SPI

USART

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD6

2543MS–AVR–10/16

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash,

128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose work-

ing registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with

compare modes, internal and external interrupts, a serial programmable USART, Universal

Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal

Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip

functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscil-

lator is running while the rest of the device is sleeping. This allows very fast start-up combined

with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit

RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313

is a powerful microcontroller that provides a highly flexible and cost effective solution to many

embedded control applications.

The ATtiny2313 AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,

and Evaluation kits.

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Pin Descriptions

VCC

Digital supply voltage.

Ground.

GND

Port A (PA2..PA0)

Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny2313 as listed on page

53.

Port B (PB7..PB0)

Port D (PD6..PD0)

RESET

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny2313 as listed on page

53.

Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATtiny2313 as listed on page

56.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page

34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate func-

tion for PA2 and dW.

XTAL1

XTAL2

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1

is an alternate function for PA0.

Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.

2543MS–AVR–10/16

General

Information

Resources

A comprehensive set of development tools, application notes and datasheets are available for

download at http://www.atmel.com/avr.

Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (ox42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

SREG

Reserved

SPL

–

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

OCR0B

GIMSK

EIFR

Timer/Counter0 – Compare Register B

INT1

INTF1

TOIE1

TOV1

–

INT0

INTF0

OCIE1A

OCF1A

–

PCIE

PCIF

–

TIMSK

OCIE1B

OCF1B

–

ICIE1

ICF1

RFLB

OCIE0B

OCF0B

PGWRT

TOIE0

TOV0

PGERS

OCIE0A

OCF0A

SELFPRGEN

78, 109

TIFR

–

SPMCSR

OCR0A

MCUCR

MCUSR

TCCR0B

TCNT0

OSCCAL

TCCR0A

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

Reserved

CLKPR

ICR1H

CTPB

155

Timer/Counter0 – Compare Register A

PUD

–

SM1

–

SM0

ISC11

WDRF

ISC10

BORF

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

–

FOC0A

FOC0B

–

WGM02

Timer/Counter0 (8-bit)

–

CAL6

COM0A0

COM1A0

ICES1

CAL5

COM0B1

COM1B1

–

CAL4

CAL3

CAL2

–

CAL1

WGM01

WGM11

CS11

CAL0

WGM00

WGM10

CS10

COM0A1

COM1A1

ICNC1

COM0B0

COM1BO

WGM13

–

104

107

108

109

WGM12

CS12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Compare Register A High Byte

Timer/Counter1 – Compare Register A Low Byte

Timer/Counter1 – Compare Register B High Byte

Timer/Counter1 – Compare Register B Low Byte

–

CLKPCE

CLKPS3

CLKPS2

CLKPS1

CLKPS0

109

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

ICR1L

GTCCR

TCCR1C

WDTCSR

PCMSK

Reserved

EEAR

–

FOC1A

WDIF

PCINT7

–

PSR10

–

FOC1B

WDIE

PCINT6

–

108

WDP3

PCINT5

–

WDCE

PCINT4

–

WDE

PCINT3

–

WDP2

PCINT2

–

WDP1

PCINT1

–

WDP0

PCINT0

–

EEPROM Address Register

EEPROM Data Register

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

PORTA2

DDA2

EEPE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA

DDRA

–

PINA

–

PINA2

PINA1

PINA0

PORTB

DDRB

PORTB7

DDB7

PINB7

PORTB6

DDB6

PINB6

PORTB5

DDB5

PINB5

PORTB4

DDB4

PINB4

PORTB3

DDB3

PINB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

PINB

PINB2

PINB1

PINB0

GPIOR2

GPIOR1

GPIOR0

PORTD

DDRD

General Purpose I/O Register 2

General Purpose I/O Register 1

General Purpose I/O Register 0

–

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

PIND

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

USIDR

USI Data Register

144

145

129

131

133

149

USISR

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USICR

USIWM1

USIWM0

UDR

UART Data Register (8-bit)

UCSRA

UCSRB

UBRRL

ACSR

RXC

TXC

UDRE

UDRIE

DOR

UPE

U2X

MPCM

TXB8

RXCIE

TXCIE

RXEN

TXEN

UCSZ2

RXB8

UBRRH[7:0]

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

Reserved

UCSRC

UBRRH

DIDR

–

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

132

133

150

UBRRH[11:8]

–

AIN1D

–

AIN0D

–

Reserved

2543MS–AVR–10/16

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Add two Registers

Rd  Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd  Rd + Rr + C

Rdh:Rdl  Rdh:Rdl + K

Rd  Rd - Rr

Rd  Rd - K

Rd  Rd - Rr - C

Rd  Rd - K - C

Rdh:Rdl  Rdh:Rdl - K

Rd Rd  Rr

Rd  Rd K

Z,N,V

Rd  Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd  Rd  Rr

Rd  0xFF  Rd

Rd  0x00  Rd

Rd  Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Two’s Complement

Rd,K

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd  Rd  (0xFF - K)

Rd  Rd + 1

Z,N,V

DEC

TST

Decrement

Rd  Rd  1

Z,N,V

Test for Zero or Minus

Clear Register

Rd  Rd  Rd

Rd  Rd  Rd

Rd  0xFF

Z,N,V

CLR

SER

Z,N,V

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

Relative Jump

PC PC + k + 1

None

Indirect Jump to (Z)

PC  Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC  PC + k + 1

PC  Z

Subroutine Return

PC  STACK

RETI

Interrupt Return

PC  STACK

CPSE

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC PC + 2 or 3

Rd  Rr

None

Z, N,V,C,H

None

1/2/3

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd  Rr  C

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd  K

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC  PC + 2 or 3

if (Rr(b)=1) PC  PC + 2 or 3

if (P(b)=0) PC  PC + 2 or 3

if (P(b)=1) PC  PC + 2 or 3

if (SREG(s) = 1) then PCPC+k + 1

if (SREG(s) = 0) then PCPC+k + 1

if (Z = 1) then PC  PC + k + 1

if (Z = 0) then PC  PC + k + 1

if (C = 1) then PC  PC + k + 1

if (C = 0) then PC  PC + k + 1

if (C = 1) then PC  PC + k + 1

if (N = 1) then PC  PC + k + 1

if (N = 0) then PC  PC + k + 1

if (N  V= 0) then PC  PC + k + 1

if (N  V= 1) then PC  PC + k + 1

if (H = 1) then PC  PC + k + 1

if (H = 0) then PC  PC + k + 1

if (T = 1) then PC  PC + k + 1

if (T = 0) then PC  PC + k + 1

if (V = 1) then PC  PC + k + 1

if (V = 0) then PC  PC + k + 1

if ( I = 1) then PC  PC + k + 1

if ( I = 0) then PC  PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b)  1

None

CBI

LSL

LSR

ROL

I/O(P,b)  0

None

Rd(n+1)  Rd(n), Rd(0)  0

Rd(n)  Rd(n+1), Rd(7)  0

Rd(0)C,Rd(n+1) Rd(n),CRd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

2543MS–AVR–10/16

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

Rotate Right Through Carry

Rd(7)C,Rd(n) Rd(n+1),CRd(0)

Z,C,N,V

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Arithmetic Shift Right

Swap Nibbles

Rd(n)  Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)

None

Flag Set

SREG(s)  1

SREG(s)  0

T  Rr(b)

Rd(b)  T

C  1

SREG(s)

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

None

Clear Carry

C  0

Set Negative Flag

N  1

Clear Negative Flag

Set Zero Flag

N  0

Z  1

Clear Zero Flag

Z  0

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I  1

CLI

I 0

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S  1

S  0

V  1

V  0

T  1

Clear T in SREG

T  0

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H  1

H  0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd  Rr

None

Rd+1:Rd  Rr+1:Rr

Load Immediate

Rd  K

Rd, X

Load Indirect

Rd  (X)

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd  (X), X  X + 1

X  X - 1, Rd  (X)

Rd  (Y)

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd  (Y), Y  Y + 1

Y  Y - 1, Rd  (Y)

Rd  (Y + q)

Rd  (Z)

LDD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd  (Z), Z  Z+1

Z  Z - 1, Rd  (Z)

Rd  (Z + q)

Rd  (k)

LDD

LDS

X, Rr

(X) Rr

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) Rr, X  X + 1

X  X - 1, (X)  Rr

(Y)  Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y)  Rr, Y  Y + 1

Y  Y - 1, (Y)  Rr

(Y + q)  Rr

STD

(Z)  Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z)  Rr, Z  Z + 1

Z  Z - 1, (Z)  Rr

(Z + q)  Rr

STD

STS

LPM

SPM

(k)  Rr

R0  (Z)

Rd, Z

Rd  (Z)

Rd, Z+

Rd  (Z), Z  Z+1

(Z)  R1:R0

Rd, P

P, Rr

Rd  P

OUT

PUSH

POP

Out Port

P  Rr

Push Register on Stack

Pop Register from Stack

STACK  Rr

Rd  STACK

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

BREAK

N/A

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Ordering Information

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽⁴⁾

Package⁽²⁾

Operation Range

ATtiny2313V-10PU

ATtiny2313V-10SU

ATtiny2313V-10SUR

ATtiny2313V-10MU

ATtiny2313V-10MUR

20P3

20S

20M1

Industrial

1.8 - 5.5

2.7 - 5.5

(-40C to +85C)⁽¹⁾

ATtiny2313-20PU

ATtiny2313-20SU

ATtiny2313-20SUR

ATtiny2313-20MU

ATtiny2313-20MUR

20P3

20S

20M1

Industrial

(-40C to +85C)⁽¹⁾

Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 82 on page 180 and Figure 83 on page 180.

4. Code Indicators:

– U: matte tin

– R: tape & reel

Package Type

20P3

20S

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)

20M1

2543MS–AVR–10/16

Packaging Information

20P3

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

–

0.381

25.493

7.620

6.096

0.356

1.270

2.921

0.203

–

25.984 Note 2

8.255

7.112 Note 2

0.559

1.551

3.810

0.356

Notes:

10.922

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

0.000

1.524

2.540 TYP

2010-10-19

DRAWING NO. REV.

20P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

20S

2543MS–AVR–10/16

20M1

Pin 1 ID

SIDE VIEW

TOP VIEW

0.08

Pin #1

Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.70

–

MAX

0.80

0.05

NOM

0.75

NOTE

SYMBOL

0.01

0.20 REF

0.23

0.18

2.45

0.35

0.30

2.75

0.55

4.00 BSC

2.60

BOTTOM VIEW

4.00 BSC

2.60

0.50 BSC

0.40

Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

Note:

12/02/2014

TITLE

DRAWING NO. REV.

20M1

2325 Orchard Parkway

San Jose, CA 95131

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

Errata

The revision in this section refers to the revision of the ATtiny2313 device.

No known errata

ATtiny2313 Rev C

ATtiny2313 Rev B

• Wrong values read after Erase Only operation

• Parallel Programming does not work

• Watchdog Timer Interrupt disabled

• EEPROM can not be written below 1.9 volts

1. Wrong values read after Erase Only operation

At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only oper-

ation may read as programmed (0x00).

Problem Fix/Workaround

If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write opera-

tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can

be used as intended. Thus no special considerations are needed as long as the erased loca-

tion is not read before it is programmed.

2. Parallel Programming does not work

Parallel Programming is not functioning correctly. Because of this, reprogramming of the

device is impossible if one of the following modes are selected:

–

In-System Programming disabled (SPIEN unprogrammed)

Reset Disabled (RSTDISBL programmed)

Problem Fix/Workaround

Serial Programming is still working correctly. By avoiding the two modes above, the device

can be reprogrammed serially.

3. Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog

will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in

interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-

out following an interrupt, the device works correctly.

Problem fix / Workaround

Make sure there is enough time to always service the first timeout event before a new

watchdog timeout occurs. This is done by selecting a long enough time-out period.

4. EEPROM can not be written below 1.9 volts

Writing the EEPROM at V_CCbelow 1.9 volts might fail.

Problem fix / Workaround

Do not write the EEPROM when V_CCis below 1.9 volts.

ATtiny2313 Rev A

Revision A has not been sampled.

2543MS–AVR–10/16

Datasheet

Revision

History

Refer to the complete datasheet for revision history change log.

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

2543MS–AVR–10/16

ATtiny2313

2543MS–AVR–10/16

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

Hong Kong

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BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

2543MS–AVR–10/16

ATTINY2313V-10PU CAD模型

原理图符号

PCB 封装图

3D模型

ATTINY2313V-10PU 替代型号

型号	制造商	描述	替代类型	文档
ATTINY2313V-10PI	ATMEL	8-bit Microcontroller with 2K Bytes In-System Programmable Flash	类似代替
ATTINY2313-20PU	MICROCHIP	IC MCU 8BIT 2KB FLASH 20DIP	类似代替
ATTINY2313-20PU	ATMEL	8-bit Microcontroller with 2K Bytes In-System Programmable Flash	功能相似

ATTINY2313V-10PU 相关器件

型号	制造商	描述	价格	文档
ATTINY2313V-10SI	ATMEL	8-bit Microcontroller with 2K Bytes In-System Programmable Flash	获取价格
ATTINY2313V-10SI	MICROCHIP		获取价格
ATTINY2313V-10SJ	ATMEL	8-bit Microcontroller with 2K Bytes In-System Programmable Flash	获取价格
ATTINY2313V-10SJ	MICROCHIP		获取价格
ATTINY2313V-10SU	ATMEL	8-bit Microcontroller with 2K Bytes In-System Programmable Flash	获取价格
ATTINY2313V-10SU-SL383	ATMEL	Microcontroller	获取价格
ATTINY2313V-10SUR	ATMEL	RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PDSO20, 0.300 INCH, GREEN, PLASTIC, MS-013AC, SOIC-20	获取价格
ATTINY2313V-10SUR	MICROCHIP	IC MCU 8BIT 2KB FLASH 20SOIC	获取价格
ATTINY2313V-12PI	MICROCHIP	RISC Microcontroller, 8-Bit, FLASH, 12MHz, CMOS, PDIP20	获取价格
ATTINY2313V-12PJ	MICROCHIP	RISC Microcontroller, 8-Bit, FLASH, 12MHz, CMOS, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, MS-001AD, DIP-20	获取价格