ATTINY48-MU_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 123 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

• High Endurance Non-volatile Memory Segments

– 4K/8K Bytes of In-System Self-Programmable Flash Program Memory

– 64/64 Bytes EEPROM

8-bit

– 256/512 Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data Retention: 20 years at 85°C / 100 years at 25°C

– Programming Lock for Software Security

• Peripheral Features

Microcontroller

with 4/8K Bytes

In-System

Programmable

Flash

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes

– 6- or 8-channel 10-bit ADC

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I²C Compatible)

– Programmable Watchdog Timer with Separate On-Chip Oscillator

– On-Chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– debugWIRE On-Chip Debug System

– In-System Programmable via SPI Port

– Power-On Reset and Programmable Brown-Out Detection

– Internal Calibrated Oscillator

ATtiny48/88

Summary

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down

– On-Chip Temperature Sensor

• I/O and Packages

– 24 Programmable I/O Lines:

• 28-pin PDIP

• 28-pad QFN

– 28 Programmable I/O Lines:

• 32-lead TQFP

• 32-pad QFN

• 32-ball UFBGA

• Operating Voltage:

– 1.8 – 5.5V

• Temperature Range:

– -40°C to +85°C

• Speed Grade:

– 0 – 4 MHz @ 1.8 – 5.5V

– 0 – 8 MHz @ 2.7 – 5.5V

– 0 – 12 MHz @ 4.5 – 5.5V

• Low Power Consumption

– Active Mode: 1 MHz, 1.8V: 240 µA

– Power-Down Mode: 0.1 µA at 1.8V

Rev. 8008HS–AVR–04/11

1. Pin Configurations

Figure 1-1. Pinout of ATtiny48/88

TQFP Top View

PDIP

(PCINT14/RESET) PC6

(PCINT16) PD0

(PCINT17) PD1

(PCINT18/INT0) PD2

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

VCC

1

2

3

4

5

6

7

8

9

28 PC5 (ADC5/SCL/PCINT13)

27 PC4 (ADC4/SDA/PCINT12)

26 PC3 (ADC3/PCINT11)

25 PC2 (ADC2/PCINT10)

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 GND

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT26) PA2

VCC

1

2

3

4

5

6

7

8

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 PA1 (ADC7/PCINT25)

21 GND

GND

21 PC7 (PCINT15)

(PCINT6/CLKI) PB6

20 AVCC

(PCINT7) PB7 10

(PCINT21/T1) PD5 11

19 PB5 (SCK/PCINT5)

18 PB4 (MISO/PCINT4)

17 PB3 (MOSI/PCINT3)

16 PB2 (SS/OC1B/PCINT2)

15 PB1 (OC1A/PCINT1)

GND

20 PC7 (PCINT15)

19 PA0 (ADC6/PCINT24)

18 AVCC

(PCINT27) PA3

(PCINT6/CLKI) PB6

(PCINT7) PB7

(PCINT22/AIN0) PD6 12

(PCINT23/AIN1) PD7 13

(PCINT0/CLKO/ICP1) PB0 14

17 PB5 (SCK/PCINT5)

32 QFN Top View

28 QFN Top View

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

(PCINT26) PA2

VCC

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

PA1 (ADC7/PCINT25)

GND

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

(PCINT19/INT1) PD3

(PCINT20/T0) PD4

VCC

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

1

2

3

4

5

6

7

21

20

19

18

17

16

15

GND

PC7 (PCINT15)

PA0 (ADC6/PCINT24)

AVCC

GND

(PCINT27) PA3

(PCINT6/CLKI) PB6

(PCINT7) PB7

(PCINT6/CLKI) PB6

(PCINT7) PB7

(PCINT21/T1) PD5

PC7 (PCI NT15)

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

Table 1-1.

32 UFBGA Top View. See page 288.

1

2

3

4

5

6

A

B

C

D

E

F

PD2

PD3

GND

VCC

PB6

PB7

PD1

PD4

PA2

PA3

PD6

PD5

PC6

PD0

PC4

PC5

PC2

PC3

PA1

PC1

PC0

GND

PA0

PB5

PB4

PC7

AVCC

PB3

PB0

PD7

PB2

PB1

2

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

AVCC

AV_CCis the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should

be externally connected to V_CCeven if the ADC is not used. If the ADC is used, it is recom-

mended this pin is connected to V_CCthrough a low-pass filter, as described in “Analog Noise

Canceling Techniques” on page 172.

The following pins receive their supply voltage from AV_CC: PC7, PC[5:0] and (in 32-lead pack-

ages) PA[1:0]. All other I/O pins take their supply voltage from V_CC

.

1.1.3

1.1.4

GND

Ground.

Port A (PA3:0)

Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PA[3:0] output buffers have symmetrical drive characteristics with both sink and source capabil-

ity. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors

are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

This port is available in 32-lead TQFP, 32-pad QFN and 32-ball UFBGA packages, only.

1.1.5

Port B (PB7:0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both sink and source capability.

As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are

activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock

operating circuit.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

69.

1.1.6

1.1.7

Port C (PC7, PC5:0)

Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC7 and PC[5:0] output buffers have symmetrical drive characteristics with both sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for

longer than the minimum pulse width will generate a reset, even if the clock is not running. The

3

8008HS–AVR–04/11

minimum pulse length is given in Table 22-3 on page 209. Shorter pulses are not guaranteed to

generate a reset.

The various special features of Port C are elaborated in “Alternate Functions of Port C” on page

72.

1.1.8

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabil-

ities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port D pins are

tri-stated when a reset condition becomes active, even if the clock is not running.

The various special features of Port D are elaborated in “Alternate Functions of Port D” on page

75.

4

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

2. Overview

The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

Program

Logic

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

8bit T/C 0

16bit T/C 1

A/D Conv.

6

2

Internal

Bandgap

Analog

Comp.

SPI

PORT B (8)

PB[0:7]

TWI

PORT D (8)

PORT C (8)

PORT A (4)

RESET

CLKI

PD[0:7]

PC[0:7]

PA[0:3] (in TQFP and MLF)

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

5

8008HS–AVR–04/11

The ATtiny48/88 provides the following features:

• 4/8K bytes of In-System Programmable Flash

• 64/64 bytes EEPROM

• 256/512 bytes SRAM

• 24 general purpose I/O lines

– 28 in 32-lead TQFP, 32-pad QFN, and 32-ball UFBGA packages

• 32 general purpose working registers

• Two flexible Timer/Counters with compare modes

• Internal and external interrupts

• A byte-oriented, 2-wire serial interface

• An SPI serial port

• A 6-channel, 10-bit ADC

– 8 in 32-lead TQFP, 32-pad QFN, and 32-ball UFBGA packages

• A programmable Watchdog Timer with internal oscillator

• Three software selectable power saving modes.

The device includes the following modes for saving power:

• Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI,

TWI, and interrupt system to continue functioning

• ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping

the CPU and all I/O modules except the ADC

• Power-down mode: registers keep their contents and all chip functions are disabled until the

next interrupt or hardware reset

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro-

gram running on the AVR core. The boot program can use any interface to download the

application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self-

Programmable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller

that provides a highly flexible and cost effective solution to many embedded control applications.

The ATtiny48/88 AVR is supported by a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators and evaluation kits.

2.2

Comparison Between ATtiny48 and ATtiny88

The ATtiny48 and ATtiny88 differ only in memory sizes, as summarised in Table 2-1, below.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

64 Bytes

RAM

ATtiny48

ATtiny88

4K Bytes

256 Bytes

512 Bytes

8K Bytes

6

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

3. General Information

3.1

Resources

A comprehensive set of development tools, application notes and datasheets are available for

download at http://www.atmel.com/avr.

3.2

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

3.3

Capacitive Touch Sensing

Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel

AVR microcontrollers. The QTouch Library includes support for QTouch^®and QMatrix^®acquisi-

tion methods.

Touch sensing is easily added to any application by linking the QTouch Library and using the

Application Programming Interface (API) of the library to define the touch channels and sensors.

The application then calls the API to retrieve channel information and determine the state of the

touch sensor.

The QTouch Library is free and can be downloaded from the Atmel website. For more informa-

tion and details of implementation, refer to the QTouch Library User Guide – also available from

the Atmel website.

3.4

3.5

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology.

7

8008HS–AVR–04/11

4. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

Reserved

–

8

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

TWHSR

TWAMR

TWCR

–

TWAM0

–

TWHS

–

160

156

159

158

156

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

–

^{Timer/Counter1}– Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

^{Timer/Counter1}– Output Compare Register A High Byte

^{Timer/Counter1}– Output Compare Register A Low Byte

Timer/Counter1 – Input Capture Register High Byte

^{Timer/Counter1}– Input Capture Register Low Byte

^{Timer/Counter1}– Counter Register High Byte

114

113

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 – Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

WGM13

COM1B0

–

CS12

–

113

112

110

163

180

–

WGM12

CS11

WGM11

AIN1D

ADC1D

–

CS10

WGM10

AIN0D

ADC0D

–

COM1B1

–

ADC5D

–

ADC3D

–

DIDR0

ADC7D

–

ADC6D

–

ADC4D

–

ADC2D

–

Reserved

9

8008HS–AVR–04/11

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7C)

(0x7B)

ADMUX

ADCSRB

ADCSRA

ADCH

–

REFS0

ACME

ADSC

ADLAR

–

MUX3

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

176

162, 179

178

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

179

(0x78)

ADCL

179

(0x77)

Reserved

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

PCMSK3

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

(0x6F)

–

ICIE1

–

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

PCINT26

ISC10

PCIE2

–

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

PCINT25

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

PCINT24

114

87

59

55

57

(0x6E)

–

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT11

PCINT3

PCINT27

(0x6C)

PCINT15

PCINT14

PCINT13

PCINT12

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

(0x6A)

–

-

(0x69)

–

ISC11

PCIE3

–

ISC01

PCIE1

–

ISC00

PCIE0

–

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

(0x66)

Oscillator Calibration Register

34

40

(0x65)

–

(0x64)

PRTWI

–

PRTIM0

–

PRTIM1

PRSPI

–

PRADC

(0x63)

Reserved

CLKPR

WDTCSR

SREG

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

34

49

9

(0x60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

I

–

T

H

–

S

V

N

Z

C

SPH

–

SP9

SP8

11

SPL

SP7

–

SP6

SP5

–

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

RWWSB

–

CTPB

RFLB

PGWRT

PGERS

SELFPRGEN

186

–

BODS

BODSE

PUD

–

40, 77

49

–

WDRF

BORF

SM1

–

EXTRF

SM0

–

PORF

SE

–

39

Reserved

DWDR

–

debugWire Data Register

182

162

ACSR

ACD

–

ACBG

–

ACO

–

ACI

–

ACIE

–

ACIC

–

ACIS1

–

ACIS0

–

Reserved

SPDR

SPI Data Register

128

127

126

27

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

27

–

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8-bit)

87

86

85

TCCR0A

Reserved

GTCCR

Reserved

EEARL

–

CTC0

CS02

CS01

CS00

–

PSRSYNC

–

TSM

–

118

EEPROM Address Register Low Byte

EEPROM Data Register

25

27

56

58

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

EIMSK

General Purpose I/O Register 0

–

INT1

INTF1

PCIF1

INT0

INTF0

PCIF0

EIFR

PCIFR

PCIF3

PCIF2

10

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved

TIFR1

–

ICF1

–

OCF1B

OCF0B

–

OCF1A

OCF0A

–

TOV1

TOV0

–

115

87

TIFR0

–

Reserved

PORTCR

Reserved

PORTA

DDRA

–

BBMD

BBMC

BBMB

BBMA

PUDD

–

PUDC

–

PUDB

–

PUDA

–

77

–

PORTA3

DDA3

PINA3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PORTA2

DDA2

PINA2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTA1

DDA1

PINA1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTA0

DDA0

PINA0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

78

–

PINA

–

PORTD

DDRD

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

–

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

79

78

79

78

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a com-

plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN

and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

11

8008HS–AVR–04/11

5. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

LSR

ROL

ROR

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

12

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ASR

Rd

Arithmetic Shift Right

Swap Nibbles

Flag Set

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

1

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

s

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

13

8008HS–AVR–04/11

6. Ordering Information

6.1

ATtiny48

Speed (MHz)

Power Supply

Ordering Code⁽¹⁾

Package⁽²⁾

Operational Range

ATtiny48-MMU

ATtiny48-MMUR

ATtiny48-MMH

ATtiny48-MMHR

ATtiny48-PU

28M1

28P3

32A

32CC1

32M1-A

Industrial

(-40°C to +85°C)⁽³⁾

12

1.8 – 5.5V

ATtiny48-AU

ATtiny48-AUR

ATtiny48-CCU

ATtiny48-CCUR

ATtiny48-MU

ATtiny48-MUR

Notes: 1. Code indicators:

– H: NiPdAu lead finish

– U: matte tin

– R: tape & reel

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

Package Type

28M1

28P3

32A

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm, Quad Flat No-Lead (QFN)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball (6 x 6 Array), 0.50 mm Pitch, 4 x 4 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm, Quad Flat No-Lead (QFN)

14

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

6.2

ATtiny88

Speed (MHz)

Power Supply

Ordering Code⁽¹⁾

Package⁽²⁾

Operational Range

ATtiny88-MMU

ATtiny88-MMUR

ATtiny88-MMH

ATtiny88-MMHR

ATtiny88-PU

28M1

28P3

32A

32CC1

32M1-A

Industrial

(-40°C to +85°C)⁽³⁾

12

1.8 – 5.5V

ATtiny88-AU

ATtiny88-AUR

ATtiny88-CCU

ATtiny88-CCUR

ATtiny88-MU

ATtiny88-MUR

Notes: 1. Code indicators:

– H: NiPdAu lead finish

– U: matte tin

– R: tape & reel

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

Package Type

28M1

28P3

32A

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm, Quad Flat No-Lead (QFN)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32CC1

32-ball (6 x 6 Array), 0.50 mm Pitch, 4 x 4 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm, Quad Flat No-Lead (QFN)

15

8008HS–AVR–04/11

7. Packaging Information

7.1

28M1

D

C

1

2

3

Pin 1 ID

E

SIDE VIEW

A1

TOP VIEW

A

y

K

D2

0.45

E2

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

3

R 0.20

MIN

MAX

NOM

NOTE

SYMBOL

A

0.80

0.90

1.00

A1

b

0.00

0.17

0.02

0.22

0.20 REF

4.00

2.40

4.00

2.40

0.45

0.40

–

0.05

0.27

b

C

D

D2

E

3.95

2.35

3.95

2.35

4.05

2.45

4.05

2.45

L

e

E2

e

0.4 Ref

(4x)

BOTTOM VIEW

L

0.35

0.00

0.20

0.45

0.08

–

y

K

–

The terminal #1 ID is a Laser-marked Feature.

Note:

10/24/08

GPC

DRAWING NO.

TITLE

REV.

28M1, 28-pad,4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 x 2.4 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

ZBV

28M1

B

16

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

7.2

28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

17

8008HS–AVR–04/11

7.3

32A

PIN 1 IDENTIFIER

PIN 1

e

B

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

E1

B

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

3. Lead coplanarity is 0.10 mm maximum.

L

–

e

0.80 TYP

2010-10-20

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

C

R

18

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

7.4

32CC1

1 2

3

4

5

6

0.08

A

B

Pin#1 ID

C

D

SIDE VIEW

b1

D

E

F

A1

A

E

A2

TOP VIEW

E1

e

32-Øb

1 2

3

4

5

6

F

COMMON DIMENSIONS

(Unit of Measure = mm)

E

D

C

MIN

–

MAX

0.60

–

NOM

–

NOTE

SYMBOL

D1

A

A1

A2

b

0.12

–

B

A

e

0.38 REF

0.30

0.25

3.90

0.35

–

1

2

b1

D

–

4.00

4.10

A1 BALL CORNER

BOTTOM VIEW

D1

E

2.50 BSC

4.00

3.90

4.10

E1

e

2.50 BSC

0.50 BSC

Note1: Dimension“b”is measured at the maximum ball dia. in a plane parallel

to the seating plane.

Note2: Dimension “b1” is the solderable surface defined by the opening of the

solder resist layer.

07/06/10

GPC

DRAWING NO.

TITLE

REV.

32CC1, 32-ball (6 x 6 Array), 4 x 4 x 0.6 mm

package, ball pitch 0.50 mm, Ultra Thin,

Fine-Pitch Ball Grid Array (UFBGA)

Package Drawing Contact:

packagedrawings@atmel.com

B

CAG

32CC1

19

8008HS–AVR–04/11

7.5

32M1-A

D

D1

1

0

2

3

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

0.08

C

(Unit of Measure = mm)

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

20

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

8. Errata

8.1

ATtiny48

8.1.1

Rev. C

Rev. B

Rev. A

No known errata.

Not sampled.

8.1.2

8.1.3

21

8008HS–AVR–04/11

8.2

ATtiny88

8.2.1

Rev. C

No known errata.

Not sampled.

8.2.2

8.2.3

Rev. B

Rev. A

22

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

9. Datasheet Revision History

9.1

Rev. 8008H - 04/11

1. Updated:

– “Ordering Information” on page 283, added tape & reel code -MMUR

9.2

Rev. 8008G - 04/11

1. Updated:

– “Block Diagram” on page 5

– “Memories” on page 17

– “Clock System” on page 28

– “Lock Bits, Fuse Bits and Device Signature” on page 188

– “External Programming” on page 191

– “Speed” on page 208

– “Two-Wire Serial Interface Characteristics” on page 212

2. Added:

– “Capacitive Touch Sensing” on page 7

– “Register Description” on page 15

– “Overview” on page 129

– “Compatibility with SMBus” on page 156

3. Changed document status from “Preliminary” to “Final”.

9.3

Rev. 8008F - 06/10

1. Updated notes 1 and 10 in table in Section 22.2 “DC Characteristics” on page 206.

2. Updated package drawing in Section 27.4 “32CC1” on page 288.

3. Updated bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].

9.4

9.5

Rev. 8008E - 05/10

1. Section 24. “Register Summary” on page 277, added SPH at address 0x3E.

2. Section 27.1 “28M1” on page 285 updated with correct package drawing.

Rev. 8008D - 03/10

1. Separated Typical Characteristic plots, added Section 23.2 “ATtiny88” on page 248.

2. Updated:

– Section 1.1 “Pin Descriptions” on page 3, Port D, adjusted texts ‘sink and source’

and ‘high sink’.

– Table 6-3 on page 28 adjusted, to fix TBD.

– Section 6.2.3 “Internal 128 kHz Oscillator” on page 31 adjusted, to fix TBD.

– Section 8.4 “Watchdog Timer” on page 46, updated.

– Section 22.2 “DC Characteristics” on page 206, updated TBD in notes 5 and 8.

3. Added:

23

8008HS–AVR–04/11

– UFBGA package (32CC1) in, “Features” on page 1, “Pin Configurations” on page 2,

Section 26. “Ordering Information” on page 283, and Section 27. “Packaging

Information” on page 285

– Addresses in all Register Desc. tables, with cross-references to Register Summary

– Tape and reel in Section 26. “Ordering Information” on page 283

9.6

Rev. 8008C - 03/09

1. Updated sections:

– “Features” on page 1

– “Reset and Interrupt Handling” on page 12

– “EECR – EEPROM Control Register” on page 25

– “Features” on page 129

– “Bit Rate Generator Unit” on page 135

– “TWBR – TWI Bit Rate Register” on page 156

– “TWHSR – TWI High Speed Register” on page 160

– “Analog Comparator” on page 161

– “Overview” on page 164

– “Operation” on page 165

– “Starting a Conversion” on page 166

– “Programming the Lock Bits” on page 199

– “Absolute Maximum Ratings*” on page 206

– “DC Characteristics” on page 206

– “Speed” on page 208

– “Register Summary” on page 277

2. Added sections

– “High-Speed Two-Wire Interface Clock – clk_TWIHS” on page 29

– “Analog Comparator Characteristics” on page 210

3. Updated Figure 6-1 on page 28.

4. Updated order codes on page 283 and page 284 to reflect changes in leadframe

composition.

9.7

9.8

Rev. 8008B - 06/08

1. Updated introduction of “I/O-Ports” on page 60.

2. Updated “DC Characteristics” on page 206.

3. Added “Typical Characteristics” on page 219.

Rev. 8008A - 06/08

1. Initial revision.

24

ATtiny48/88

8008HS–AVR–04/11

ATtiny48/88

25

8008HS–AVR–04/11

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: (+1)(408) 441-0311

Fax: (+1)(408) 487-2600

Atmel Asia Limited

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

HONG KONG

Atmel Munich GmbH

Business Campus

Parkring 4

D-85748 Garching b. Munich

GERMANY

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

JAPAN

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Tel: (+49) 89-31970-0

Fax: (+49) 89-3194621

Tel: (+852) 2245-6100

Fax: (+852) 2722-1369

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8008HS–AVR–04/11


型号：	ATTINY48-MU
厂家：	MICROCHIP
描述：	IC MCU 8BIT 4KB FLASH 32VQFN 时钟微控制器外围集成电路装置
文件：	总26页 (文件大小：551K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY48-MU [MICROCHIP]

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