DSA557-0344FI0TVAO [MICROCHIP]
Clock Generator;
| 型号： | DSA557-0344FI0TVAO |
| 厂家： | 
MICROCHIP |
| 描述： | Clock Generator |
| 文件： | 总20页 (文件大小：1139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSA557-03/04/05
Multiple Output MEMS PCIe Gen1/2/3/4 Clocks for Automotive
Features
General Description
• Automotive AEC-Q100 Qualified
The DSA557 series of high performance PCI Express
clock generators use
a proven silicon MEMS
• Complies with PCIe Gen1/2/3/4 Common Clock
Spec
technology to provide 100 MHz differential output
clocks with excellent jitter and stability over a wide
range of supply voltages and temperatures. By
eliminating the need for quartz or SAW technology,
MEMS oscillators significantly enhance reliability and
accelerate product development, while meeting
stringent clock performance criteria for a variety of
communications, storage, and networking applications.
• Integrated MEMS Resonator Eliminates the Need
for External 25 MHz Crystal
• Wide Temperature Range:
- Automotive Grade 2: –40°C to +105°C
- Automotive Grade 3: –40°C to +85°C
• 100 MHz HCSL/LVDS/LVCMOS Options
Available
The DSA557-03/04/05 have two, three, and four
100 MHz outputs, respectively. All have output
enable/disable features.
• Dedicated Output Pins for Clock Outputs
• Small Footprints:
- 14-Lead QFN (DSA557-03, Two Outputs)
The DSA557-03 is available in a space-saving 14-lead
QFN package. The DSA557-04 and DSA557-05 are
available in a 20-lead VQFN.
- 20-Lead VQFN (DSA557-04, Three Outputs;
DSA557-05, Four Outputs)
• Excellent Shock and Vibration Immunity
- Qualified to MIL-STD-883
Additional LVDS and LVCMOS output formats are
available in addition to the default HCSL output format.
• High Reliability
- 20x Better MTF than Quartz Oscillators
• Low Current Consumption: 30% Lower than
Competing Devices
• Supply Range of 2.25V to 3.63V
• Lead-Free and RoHS Compliant
Applications
• Automotive Infotainment
• Automotive ADAS
• Autonomous Driving
• In-Vehicle Network
2019-2020 Microchip Technology Inc.
DS20006175B-page 1
DSA557-03/04/05
Package Types
DSA557-05
20-Lead VQFN
(Top View)
DSA557-04
20-Lead VQFN
(Top View)
DSA557-03
14-Lead QFN
(Top View)
20 19 18 17 16 15
20 19 18 17 16 15
14 13 12
OE1
OE1
NC
1
2
3
4
14
13
12
11
VSS
VSS
NC
1
2
3
4
14
13
12
11
VSS
VSS
NC
OE
NC
1
2
3
4
11
10
9
CLK0+
CLK0-
CLK1-
CLK1+
NC
VSS
VSS
VSS
VSS
OE2
OE2
NC
5
6
7
8
9
10
5
6
7
8
9
10
VSS
8
5
6
7
Block Diagrams
DSA557-04
DSA557-03
CLK0+
CLK0-
Control Circuitry
Control Circuitry
Output
CLK0+
CLK0-
CLK1+
CLK1-
Control
and
Output
Control
and
MEMS
PLLs
MEMS
PLL
Divider
Divider
OE1
OE2
CLK2-
CLK2+
CLK1-
CLK1+
OE
DSA557-05
Note:
CLK0+/–, CLK1+/–, CLK2+/–, and CLK3+/–
are 100 MHz, per PCIe standards.
DS20006175B-page 2
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage .................................................................................................................................... –0.3V to VDD + 0.3V
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
ESD Protection on All Pins (HBM) .............................................................................................................................4 kV
ESD Protection on All Pins (CDM) ..........................................................................................................................1.5 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise specified, T = +25°C, VDD = 3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Conditions
Supply Voltage
VDD
2.25
—
3.63
V
Note 1
HCSL output, EN pin low, output
disabled
—
—
—
—
—
21
60
23
—
46
—
46
Supply Current, DSA557-03
Supply Current, DSA557-04
Supply Current, DSA557-05
IDD
mA
HCSL output, EN pin high, output
enabled
HCSL output, EN pin low, output
disabled
42
IDD
mA
HCSL output, EN pin high, output
enabled
100
42
HCSL output, EN pin low, output
disabled
IDD
mA
HCSL output, EN pin high, output
enabled
—
—
120
—
—
Frequency Stability (including
frequency variations due to
initial tolerance, temp., and
power supply voltage)
±100
Δf
ppm
All temperature ranges
—
—
±50
Aging - 1st Year
Δf
—
—
—
—
±5
5
ppm
ms
±1 ppm each subsequent year
T = +25°C
Startup Time (Note 2)
Input Logic Levels
tSU
0.75 x
VDD
Input Logic High
Input Logic Low
VIH
VIL
—
—
—
V
V
—
—
0.25 x
VDD
—
Output Disable Time (Note 3)
Output Enable Time
tDS
tEN
—
—
—
—
5
ns
ns
—
—
20
Enable Pull-Up Resistor
(Note 4)
—
—
40
—
kΩ
Internally pulled up
HCSL Outputs (Note 5)
Output Logic High
VOH
VOL
—
0.725
—
—
—
—
0.1
—
V
V
RL = 50Ω
RL = 50Ω
Single-Ended
—
Output Logic Low
Peak-to-Peak Output Swing
Output Frequency
—
750
100
mV
MHz
fOUT
—
—
2019-2020 Microchip Technology Inc.
DS20006175B-page 3
DSA557-03/04/05
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, T = +25°C, VDD = 3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Conditions
Output Transition Time
(Note 6)
tr/tf
200
—
400
ps
%
20% to 80%, RL = 50Ω, CL = 2 pF
Differential
Output Duty Cycle
SYM
JPER
48
—
—
52
—
Period Jitter (Note 7)
2.5
psRMS f01 = f02 = 100 MHz
PCIe Gen 1.1, (Note 8)
psPP
TJ
—
—
—
23
86
3.1
3.0
TJ = DJ + 14.069 x RJ (BER 10-12
)
PCIe Gen 2.1, 1.5 MHz to Nyquist,
(Note 8)
J
2.20
0.08
psRMS
psRMS
RMS-CCHF
Jitter, Phase (Common Clock
Architecture)
PCIe Gen 2.1, 10 kHz to 1.5 MHz,
(Note 8)
J
RMS-CCLF
JRMS-CC
JRMS-CC
—
—
0.37
200
1.0
psRMS PCIe Gen 3.0, (Note 8)
fsRMS PCIe Gen 4.0, 16 GHz
500
PCIe Gen 2.1, 1.5 MHz to Nyquist,
(Note 8)
J
—
2.15
4.0
psRMS
psRMS
RMS-DCHF
Integrated Phase Noise (Data
Clock Architecture)
PCIe Gen 2.1, 10 kHz to 1.5 MHz,
(Note 8)
J
—
—
0.06
0.32
7.5
1.0
RMS-DCLF
JRMS-DC
psRMS PCIe Gen 3.0, (Note 8)
LVDS Output
Offset Voltage
VOS
ΔVOS
VOH
VOL
1.125
—
1.25
—
1.40
50
V
mV
V
VDD = 2.5V/3.3V
VOS Magnitude Change
Output High Voltage
Output Low Voltage
Output Frequency
—
0.9xV
—
—
??? mA test current
DD
0.1xV
—
—
—
V
??? mA test current
DD
fOUT
VOD
ΔVOD
tr/tf
100
350
—
—
475
40
—
MHz
mVPP
mV
ps
—
Differential Output Voltage
VOD Magnitude Change
LVDS Output Rise/Fall Time
Output Duty Cycle
275
—
—
—
—
200
50
20% – 80%
ODC
JPTP
48
—
52
—
%
20% – 80%, RL = 50ꢀ, CL = 2 pF
fOUT = 100 MHz, Standard Drive
Period Jitter, Peak to Peak
2.5
ps
200 kHz to 20 MHz @ 100 MHz,
TA = +105°C
—
0.28
—
Integrated Phase Noise
JPH
psRMS
—
—
0.4
1.7
—
100 kHz to 80 MHz @ 100 MHz
12 kHz to 10 MHz @ 100 MHz
2.0
DS20006175B-page 4
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, T = +25°C, VDD = 3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Conditions
LVCMOS Output
Output High Voltage
Output Low Voltage
Output Frequency
Output Rise/Fall Time
Output Duty Cycle
Period Jitter
0.8xV
VOH
VOL
fOUT
tr/tf
—
—
—
V
V
±10 mA drive current
DD
0.2xV
—
—
—
48
—
—
—
—
±10 mA drive current
—
DD
100
1.2
50
—
—
52
—
—
—
2.0
MHz
ns
20% – 80%, CL = 15 pF
fOUT = 100 MHz, Standard Drive
ODC
JPTP
%
3
psRMS fOUT = 100 MHz, Standard Drive
200 kHz to 20 MHz @ 100 MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS 100 kHz to 20 MHz @ 100 MHz
12 kHz to 20 MHz @ 100 MHz
Note 1: Each pin VDD should be filtered with a 0.1 μF capacitor.
2: SU is time to 100 ppm of output frequency after VDD is applied and outputs are enabled.
t
3: Output Waveform and Test Circuit figures define the parameters.
4: Output is enabled if pad is floated or not connected.
5: Contact Microchip for alternate output options (LVDS, LVCMOS).
6: Output Waveform and Connection Diagram define the parameters.
7: Period Jitter includes crosstalk from adjacent output.
8: Jitter limits established by Gen 1.1, Gen 2.1, Gen 3.0, and Gen 4.0 PCIe standards.
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
–40
–40
—
—
—
+85
+105
+150
+150
—
°C
°C
°C
°C
°C
Ordering Option I
Operating Temperature Range
TA
Ordering Option L
Junction Operating Temperature
Storage Temperature Range
Lead Temperature
TJ
TS
—
—
—
–55
—
—
—
+260
Soldering, 40s
2019-2020 Microchip Technology Inc.
DS20006175B-page 5
DSA557-03/04/05
2.0
PIN DESCRIPTIONS AND CONNECTION DIAGRAMS
The descriptions of the pins are listed in Table 2-1, Table 2-2, and Table 2-3.
TABLE 2-1:
Pin Number
DSA557-03 QFN-14 PIN FUNCTION TABLE
Pin Name Pin Type
Description
1
2
OE
NC
I
Output enable, active-high.
N/A
N/A
P
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
Ground.
3
NC
4
VSS
NC
5
N/A
N/A
N/A
O
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
Ground recommended or leave as a NC.
True output of differential pair.
6
NC
7
NC
8
CLK1+
CLK1–
CLK0–
CLK0+
VDD1
VDD0
NC
9
O
Complement output of differential pair.
Complement output of differential pair.
True output of differential pair.
10
11
12
13
14
O
O
P
Power supply for core and output 1 (CLK1+/CLK1–)
Power supply for output 0 (CLK0+/CLK0–)
Ground recommended or leave as a NC.
P
N/A
+
VDD
-
0.1μF
14 13 12
1
2
3
4
11
10
9
CLK0+
CLK0-
+
Enable
-
5ꢀȍ
5ꢀȍ
8
5
6
7
CLK1-
CLK1+
Ropt
Ropt 22Ω – 33Ω optional
5ꢀȍ
5ꢀȍ
FIGURE 2-1:
14-Lead QFN Connection Diagram with Two HCSL Outputs.
14
13
13
14
12
11
12
1
1
11
CLK0+
CLK0-
CLK0
CLK1
RS
Z0 = 50ё
Z0 = 50Ω
Z0 = 50Ω
2
10
2
10
DSA557-03
DSA557-03
3
4
9
8
3
9
8
CLK1-
Z0 = 50ё
CLK1+
4
5
6
7
5
6
RS
7
FIGURE 2-2:
LVDS Outputs.
FIGURE 2-3:
LVCMOS Outputs.
DS20006175B-page 6
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
TABLE 2-2:
Pin Number
DSA557-04 QFN-20 PIN FUNCTION TABLE
Pin Name Pin Type
Description
1
2
OE1
NC
I
N/A
P
Output enable, active-high. Controls CLK0.
Leave unconnected or grounded.
Ground.
3
VSS
VSS
CLK0–
CLK0+
CLK1–
CLK1+
VDD
NC
4
P
Ground.
5
O
Complement output of differential pair.
True output of differential pair.
Complement output of differential pair.
True output of differential pair.
Power supply.
6
O
7
O
8
O
9
P
10
11
12
13
14
15
16
17
18
19
20
N/A
I
Leave unconnected or grounded.
Output enable, active-high. Controls CLK1 and CLK2.
Leave unconnected or grounded.
Ground.
OE2
NC
N/A
P
VSS
VSS
CLK2–
CLK2+
NC
P
Ground.
O
Complement output of differential pair.
True output of differential pair.
Leave unconnected or grounded.
Leave unconnected or grounded.
Power supply.
O
N/A
N/A
P
NC
VDD
NC
N/A
Leave unconnected or grounded.
+
VDD
-
0.1μF
0.1μF
CLK2+
CLK2-
5ꢀȍ
5ꢀȍ
5ꢀȍ
5ꢀȍ
20 19 18 17 16 15
1
2
3
4
14
13
12
11
CLK1+
CLK1-
5
6
7
8
9
10
CLK0+
CLK0-
Ropt
+
Enable
-
5ꢀȍ
5ꢀȍ
5RSWꢁꢂꢂȍꢁ±ꢁꢃꢃȍꢁRSWLRQDO
FIGURE 2-4:
20-Lead QFN Connection Diagram with Three HCSL Outputs.
CLK2+
19
17
15
14
CLK2
CLK1
CLK0
20
18
16
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
1
19
17
15
14
20
18
16
CLK2-
RS
RS
1
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
2
3
4
13
12
11
CLK1+
CLK1-
2
3
4
13
12
11
DSA557-04
DSA557-04
CLK0-
5
6
7
8
10
9
RS
CLK0+
5
6
7
8
10
9
FIGURE 2-6:
LVCMOS Outputs.
FIGURE 2-5:
LVDS Outputs.
2019-2020 Microchip Technology Inc.
DS20006175B-page 7
DSA557-03/04/05
TABLE 2-3:
Pin Number
DSA557-05 QFN-20 PIN FUNCTION TABLE
Pin Name Pin Type
Description
1
2
OE1
NC
I
N/A
P
Output enable, active-high. Controls CLK0 and CLK3.
Leave unconnected or grounded.
Ground.
3
VSS
4
VSS
P
Ground.
5
CLK0–
CLK0+
CLK1–
CLK1+
VDD
O
Complement output of differential pair.
True output of differential pair.
Complement output of differential pair.
True output of differential pair.
Power supply.
6
O
7
O
8
O
9
P
10
11
12
13
14
15
16
17
18
19
20
NC
N/A
I
Leave unconnected or grounded.
Output enable, active-high. Controls CLK1 and CLK2.
Leave unconnected or grounded.
Ground.
OE2
NC
N/A
P
VSS
VSS
P
Ground.
CLK2–
CLK2+
CLK3–
CLK3+
VDD
O
Complement output of differential pair.
True output of differential pair.
Complement output of differential pair.
True output of differential pair.
Power supply.
O
O
O
P
NC
N/A
Leave unconnected or grounded.
0.1μF
5RSWꢁꢂꢂȍꢁ±ꢁꢃꢃȍ
0.1μF
optional
FIGURE 2-7:
20-Lead QFN Connection Diagram with Four HCSL Outputs.
CLK3
CLK2
CLK1
CLK0
CLK3+
RS
RS
RS
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
19
17
15
20
18
16
CLK3-
1
14
13
12
11
19
17
15
14
20
18
16
1
CLK2+
CLK2-
2
3
4
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
2
3
4
13
12
11
DSA557-05
DSA557-05
CLK1+
CLK1-
5
6
7
8
10
9
5
6
7
8
10
9
RS
CLK0-
CLK0+
FIGURE 2-9:
LVCMOS Outputs.
FIGURE 2-8:
LVDS Outputs.
DS20006175B-page 8
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
3.0
OUTPUT WAVEFORM
tR
tF
Output
80%
50%
20%
Output voltage swing.
Refer to table below.
Output
tEN
1/f0
tDA
VIH
Enable
VIL
FIGURE 3-1:
DSA557-03/04/05 Output Waveform.
TABLE 3-1:
OUTPUT VOLTAGE SWING
Specification
VCM
VSWING_SE (typ.)
LVDS
HCSL
1.2V
350 mV
675 mV
350 mV
2019-2020 Microchip Technology Inc.
DS20006175B-page 9
DSA557-03/04/05
4.0
SOLDER REFLOW PROFILE
FIGURE 4-1:
Solder Reflow Profile.
TABLE 4-1:
SOLDER REFLOW
QFN-14 MSL 1 @ 260°C Refer to JSTD-020C
TSSOP-16 MSL 3 @ 260°C Refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp.)
Preheat Time 150°C to 200°C
Time Maintained above 217°C
Peak Temperature
3°C/sec. max.
60 to 180 sec.
60 to 150 sec.
255°C to 260°C
20 to 40 sec.
Time within 5°C of Actual Peak
Ramp-Down Rate
6°C/sec. max.
8 minutes max.
Time 25°C to Peak Temperature
DS20006175B-page 10
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
14-Lead QFN*
Example
XXXXXX-XX
DCPYYWW
0SSS
DSA557-03
DCP1936
0943
20-Lead QFN*
Example
XXXXXX-XX
DCPYYWW
0SSS
DSA557-05
DCP1918
0235
Legend: XX...X Product code
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
SSS
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
e
3
)
e
3
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar (‾) symbol may not be to scale.
2019-2020 Microchip Technology Inc.
DS20006175B-page 11
DSA557-03/04/05
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20006175B-page 12
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2019-2020 Microchip Technology Inc.
DS20006175B-page 13
DSA557-03/04/05
NOTES:
DS20006175B-page 14
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
APPENDIX A: REVISION HISTORY
Revision A (April 2019)
• Initial release of DSA557-03/04/05 as Microchip
data sheet DS20006175A.
Revision B (May 2020)
• Updated Product Identification System section to
add the Automotive Suffix to the full part number.
• Removed LVPECL option throughout data sheet.
• Added LVDS and LVCMOS information to Electri-
cal Characteristics section.
• Added Figure 2-2, Figure 2-3, Figure 2-5,
Figure 2-6, Figure 2-8, and Figure 2-9.
2019-2020 Microchip Technology Inc.
DS20006175B-page 15
DSA557-03/04/05
NOTES:
DS20006175B-page 16
2019-2020 Microchip Technology Inc.
DSA557-03/04/05
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
PART No.
XXXX
X
X
X
X
XXX
a) DSA557-0344FL0VAO:
Device
Output
Format
Package
Temp.
Range
Stability
Packing
Option
Automotive
Suffix
Two HCSL Outputs PCIe Clock
Generator for Automotive,
14-Lead QFN, –40°C to +105°C
Temperature Range, ±100 ppm
Stability, 96/Tube, Standard
Automotive
Device:
DSA557-03: Two Output PCIe Clock Generator for
Automotive
DSA557-04: Three Output PCIe Clock Generator for
Automotive
DSA557-05: Four Output PCIe Clock Generator for
Automotive
b) DSA557-04111KI1TVAO:
Three LVCMOS Outputs PCIe
Clock Generator for Automotive,
20-Lead QFN, –40°C to +85°C
Temperature Range, ±50 ppm
Stability, 1000/Reel, Standard
Automotive
Output Format:
(Note 1)
1
3
4
=
=
=
LVCMOS
LVDS
HCSL
c) DSA557-053344KL0VAO:
Four Output PCIe Clock
Package:
F
K
=
=
14-Lead QFN (DSA557-03 Only)
20-Lead QFN (DSA557-04/05 Only)
Generator for Automotive,
(CLK3/CLK2: LVDS, CLK1/
CLK0: HCSL), 20-Lead QFN,
–40°C to +105°C Temperature
Range, ±100 ppm Stability,
96/Tube, Standard Automotive
Temperature
Range:
L
I
=
=
–40C to +105C (Automotive Grade 2)
–40C to +85C (Automotive Grade 3)
Stability:
0
1
=
=
±100 ppm
±50 ppm
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the Tape
and Reel option.
Packing Option:
<blank>= 72/Tube (DSA557-04/05)
<blank>= 96/Tube (DSA557-03)
T
=
1000/Reel (All Package Options)
Automotive Suffix: Vxx
=
Automotive suffix in which “xx” is assigned by
Microchip. Default value is “AO” for standard
automotive part.
Note 1: The Output Format’s arrangement is CLK3 to CLK0 (left-to-right)
and may only have as many digits as that particular part allows. For
example, DSA557-03 has two outputs; the part number example
can only have two digits in that location. DSA557-04 can only have
three and DSA557-05 can only have four.
2019-2020 Microchip Technology Inc.
DS20006175B-page 17
DSA557-03/04/05
NOTES:
DS20006175B-page 18
2019-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
ISBN: 978-1-5224-6056-5
2019-2020 Microchip Technology Inc.
DS20006175B-page 19
Worldwide Sales and Service
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DS20006175B-page 20
2019-2020 Microchip Technology Inc.
02/28/20
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