DSPIC30F3010AT-30E/SO [MICROCHIP]
High-Performance, 16-Bit Digital Signal Controllers; 高性能16位数字信号控制器型号: | DSPIC30F3010AT-30E/SO |
厂家: | MICROCHIP |
描述: | High-Performance, 16-Bit Digital Signal Controllers |
文件: | 总220页 (文件大小:3161K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
dsPIC30F3010/3011
Data Sheet
High-Performance, 16-Bit
Digital Signal Controllers
© 2007 Microchip Technology Inc.
DS70141D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS70141D-page ii
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
dsPIC30F3010/3011 Enhanced Flash
16-bit Digital Signal Controller
Peripheral Features:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
• High-current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
- Five 16-bit timers/counters; optionally pair
16-bit timers into 32-bit timer modules
• 16-bit capture input functions
• 16-bit compare/PWM output functions
• 3-wire SPI modules (supports 4 Frame modes)
High-Performance Modified RISC CPU:
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Modified Harvard architecture
• C compiler optimized instruction set architecture
with flexible addressing modes
• 2 UART modules with FIFO Buffers
• 83 base instructions
Motor Control PWM Module Features:
• 24-bit wide instructions, 16-bit wide data path
• 24 Kbytes on-chip Flash program space
(8K Instruction words)
• 6 PWM output channels
- Complementary or Independent Output
modes
• 1 Kbyte of on-chip data RAM
• 1 Kbyte of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPs operation:
- Edge and Center-Aligned modes
• 3 duty cycle generators
• Dedicated time base
- DC to 40 MHz external clock input
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• 29 interrupt sources
• Trigger for A/D conversions
- 3 external interrupt sources
- 8 user-selectable priority levels for each
interrupt source
Quadrature Encoder Interface Module
Features:
- 4 processor trap sources
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
DSP Engine Features:
• Count direction status
• Dual data fetch
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow
• Accumulator write back for DSP operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions single cycle
• ± 16-bit single-cycle shift
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 1
dsPIC30F3010/3011
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Analog Features:
• 10-bit Analog-to-Digital Converter (ADC) with
4 S/H Inputs:
• Flexible Watchdog Timer (WDT) with on-chip low-
power RC oscillator for reliable operation
- 1 Msps conversion rate
• Fail-Safe clock monitor operation detects clock
failure and switches to on-chip low-power RC
oscillator
- 9 input channels
- Conversion available during Sleep and Idle
• Programmable Brown-out Reset
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
CMOS Technology:
• Data EEPROM memory:
• Low-power, high-speed Flash technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
(1)
dsPIC30F Motor Control and Power Conversion Family
Program
Pins Mem. Bytes/
Instructions
Output
Comp/Std Control
PWM
Motor
SRAM EEPROM Timer Input
A/D 10-bit Quad
Device
Bytes
Bytes
16-bit Cap
1 Msps
Enc
PWM
dsPIC30F2010
dsPIC30F3010
dsPIC30F4012
28
28
28
12K/4K
24K/8K
512
1024
1024
1024
1024
1024
1024
4096
3
5
5
5
5
5
5
4
4
4
4
4
4
8
2
2
2
4
4
4
8
6 ch
6 ch
6 ch
6 ch
6 ch
8 ch
8 ch
6 ch
6 ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
1
1
2
2
1
2
1
1
1
1
1
2
2
1
1
1
1
1
1
1
-
-
1024
2048
1024
2048
2048
8192
48K/16K
24K/8K
6 ch
1
-
dsPIC30F3011 40/44
dsPIC30F4011 40/44
9 ch
48K/16K
66K/22K
144K/48K
9 ch
1
1
2
dsPIC30F5015
dsPIC30F6010
64
80
16 ch
16 ch
Note 1: This table provides a summary of the dsPIC30F3010/3011 peripheral features. Other available devices in
the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison.
DS70141D-page 2
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Pin Diagrams
40-Pin PDIP
MCLR
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
2
3
4
5
PWM2L/RE2
6
PWM2H/RE3
7
PWM3L/RE4
8
PWM3H/RE5
9
VDD
10
11
12
13
14
15
16
17
18
19
20
AN8/RB8
VSS
VDD
VSS
RF0
RF1
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
FLTA/INT0/RE8
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUD2/OC2/IC2/INT2/RD1
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
OC4/RD3
VSS
44-Pin TQFP
NC
PGC/EMUC/U1RX/SDI1/SDA/RF2
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VDD
AN8/RB8
RF0
VSS
VDD
dsPIC30F3011
AN7/RB7
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
AN6/OCFA/RB6
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
9
10
11
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 3
dsPIC30F3010/3011
Pin Diagrams (Continued)
44-Pin QFN
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
PGC/EMUC/U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
VSS
VDD
VDD
AN8/RB8
AN7/RB7
AN6/OCFA/RB6
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
RF0
VSS
VDD
VDD
dsPIC30F3011
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
10
11
DS70141D-page 4
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Pin Diagrams (Continued)
28-Pin SPDIP
28-Pin SOIC
MCLR
1
2
3
4
5
28
27
26
25
24
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
PWM2L/RE2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
VSS
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
6
7
8
23
22
21
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
VDD
VDD
VSS
9
20
19
18
17
16
15
10
11
12
13
14
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
FLTA/INT0/SCK1/OCFA/RE8
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
44-Pin QFN
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
PGC/EMUC/U1RX/SDI1/SDA/RF2
NC
NC
NC
NC
VSS
VSS
VDD
VDD
NC
NC
dsPIC30F3010
VDD
VDD
NC
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
10
11
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 5
dsPIC30F3010/3011
Table of Contents
Device Overview ................................................................................................................................................................................... 7
CPU Architecture Overview ................................................................................................................................................................ 15
Memory Organization .......................................................................................................................................................................... 23
Address Generator Units ..................................................................................................................................................................... 35
Interrupts ............................................................................................................................................................................................. 41
Flash Program Memory ....................................................................................................................................................................... 47
Data EEPROM Memory ...................................................................................................................................................................... 53
I/O Ports .............................................................................................................................................................................................. 57
Timer1 Module .................................................................................................................................................................................... 63
Timer2/3 Module ................................................................................................................................................................................. 67
Timer4/5 Module ................................................................................................................................................................................ 73
Input Capture Module .......................................................................................................................................................................... 77
Output Compare Module ..................................................................................................................................................................... 81
Quadrature Encoder Interface (QEI) Module ...................................................................................................................................... 85
Motor Control PWM Module ................................................................................................................................................................ 91
SPI Module ........................................................................................................................................................................................ 103
I2C™ Module .................................................................................................................................................................................... 107
Universal Asynchronous Receiver Transmitter (UART) Module ....................................................................................................... 115
10-bit High-Speed Analog-to-Digital Converter (ADC) Module ......................................................................................................... 123
System Integration ............................................................................................................................................................................ 135
Instruction Set Summary ................................................................................................................................................................... 149
Development Support ....................................................................................................................................................................... 157
Electrical Characteristics ................................................................................................................................................................... 161
Packaging Information ...................................................................................................................................................................... 199
The Microchip Web Site .................................................................................................................................................................... 215
Customer Change Notification Service ............................................................................................................................................. 215
Customer Support ............................................................................................................................................................................. 215
Reader Response ............................................................................................................................................................................. 216
Product Identification System ............................................................................................................................................................ 217
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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•
Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70141D-page 6
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
This document contains device specific information for
the dsPIC30F3010/3011 device. The dsPIC30F
devices contain extensive Digital Signal Processor
(DSP) functionality within a high-performance 16-bit
microcontroller (MCU) architecture. Figure 1-1 and
Figure 1-2 show device block diagrams for the
dsPIC30F3011 and dsPIC30F3010 devices.
1.0
DEVICE OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 7
dsPIC30F3010/3011
FIGURE 1-1:
dsPIC30F3011 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
16
16
16
Data Latch
Data Latch
Interrupt
Controller
PSV & Table
Data Access
Control Block
Y Data
RAM
(4 Kbytes)
Address
Latch
X Data
RAM
(4 Kbytes)
Address
Latch
8
16
24
24
24
16 16
X RAGU
X WAGU
16
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
Y AGU
PCH PCL
PCU
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
(24 Kbytes)
AN7/RB7
AN8/RB8
Data EEPROM
(1 Kbyte)
Effective Address
16
16
Data Latch
PORTB
ROM Latch
24
IR
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
16
16
16 x 16
PORTC
W Reg Array
Decode
Instruction
Decode and
Control
16 16
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Power-up
Timer
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
OC3/RD2
Timing
OSC1/CLKI
Generation
Oscillator
Start-up Timer
OC4/RD3
ALU<16>
16
PORTD
POR/BOR
Reset
16
MCLR
Watchdog
Timer
VDD, VSS
AVDD, AVSS
Input
Capture
Module
Output
Compare
Module
2
I C™
10-bit ADC
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
FLTA/INT0/RE8
UART1,
UART2
Motor Control
PWM
SPI
Timers
QEI
PORTE
RF0
RF1
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
SCK1/RF6
PORTF
DS70141D-page 8
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 1-2:
dsPIC30F3010 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
16
16
16
Data Latch
Data Latch
Interrupt
Controller
PSV & Table
Data Access
Control Block
Y Data
RAM
(4 Kbytes)
Address
Latch
X Data
RAM
(4 Kbytes)
Address
Latch
8
16
24
24
24
16 16
X RAGU
X WAGU
16
Y AGU
PCH PCL
PCU
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
Program Counter
Loop
Control
Logic
Stack
Control
Logic
Address Latch
Program Memory
(24 Kbytes)
Data EEPROM
(1 Kbyte)
PORTB
Effective Address
16
16
Data Latch
ROM Latch
24
IR
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
16
16
16 x 16
W Reg Array
PORTC
Decode
Instruction
Decode and
Control
16 16
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Power-up
Timer
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
Timing
Generation
OSC1/CLKI
Oscillator
Start-up Timer
PORTD
ALU<16>
16
POR/BOR
Reset
16
MCLR
Watchdog
Timer
VDD, VSS
AVDD, AVSS
Input
Capture
Module
Output
Compare
Module
2
I C™
10-bit ADC
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
Motor Control
PWM
FLTA/INT0/SCK1/OCFA/RE8
SPI
Timers
QEI
UART
PORTE
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
PORTF
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 9
dsPIC30F3010/3011
Table 1-1 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1:
Pin Name
AN0-AN8
dsPIC30F3011 I/O PIN DESCRIPTIONS
Pin
Type
Buffer
Type
Description
I
Analog Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs,
respectively.
AVDD
AVSS
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN7
I
ST
Input change notification inputs.
CN17-CN18
Can be software programmed for internal weak pull-ups on all inputs.
EMUD
EMUC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
IC1, IC2, IC7,
IC8
I
ST
Capture inputs 1, 2, 7 and 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
QEB
I
ST
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
FLTA
I
ST
—
—
—
—
—
—
PWM Fault A input.
PWM 1 Low output.
PWM 1 High output.
PWM 2 Low output.
PWM 2 High output.
PWM 3 Low output.
PWM 3 High output.
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
O
O
O
O
O
O
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an active
low Reset to the device.
OCFA
OC1-OC4
I
O
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
ST
I
=
=
Schmitt Trigger input with CMOS levels
Input
O
P
=
=
Output
Power
DS70141D-page 10
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 1-1:
Pin Name
dsPIC30F3011 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Description
Type
OSC1
OSC2
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
I/O
—
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RB0-RB8
I/O
I/O
I/O
I/O
ST
ST
ST
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
RC13-RC15
RD0-RD3
RE0-RE5,
RE8
RF0-RF6
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
I
O
I
ST
SPI #1 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
ST
—
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
O
UART2 Transmit.
VDD
P
P
I
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
VREF+
VREF-
Analog Analog Voltage Reference (High) input.
Analog Analog Voltage Reference (Low) input.
I
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
ST
I
=
=
Schmitt Trigger input with CMOS levels
Input
O
P
=
=
Output
Power
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 11
dsPIC30F3010/3011
Table 1-2 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-2:
Pin Name
AN0-AN5
dsPIC30F3010 I/O PIN DESCRIPTIONS
Pin
Type
Buffer
Type
Description
I
Analog Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs,
respectively.
AVDD
AVSS
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN7
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
EMUD
EMUC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
IC1, IC2, IC7,
IC8
I
ST
Capture inputs 1, 2, 7 and 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
QEB
I
ST
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
FLTA
I
ST
—
—
—
—
—
—
PWM Fault A input.
PWM 1 Low output.
PWM 1 High output.
PWM 2 Low output.
PWM 2 High output.
PWM 3 Low output.
PWM 3 High output.
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
O
O
O
O
O
O
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an active
low Reset to the device.
OCFA
OC1, OC2
I
O
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 and 2.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
ST
I
=
=
Schmitt Trigger input with CMOS levels
Input
O
P
=
=
Output
Power
DS70141D-page 12
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 1-2:
Pin Name
dsPIC30F3010 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Description
Type
OSC1
OSC2
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
I/O
—
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RB0-RB5
I/O
8I/O
I/O
ST
8ST
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
RC13-RC15
RD0-RD1
RE0-RE5,
RE8
I/O
ST
RF2-RF3
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
O
VDD
P
P
I
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
VREF+
VREF-
Analog Analog Voltage Reference (High) input.
Analog Analog Voltage Reference (Low) input.
I
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
ST
I
=
=
Schmitt Trigger input with CMOS levels
Input
O
P
=
=
Output
Power
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 13
dsPIC30F3010/3011
NOTES:
DS70141D-page 14
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
2.0
CPU ARCHITECTURE
OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 "Address Generator Units" for
details on Modulo and Bit-Reversed addressing.
2.1
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1), and the Most
Significant bit (MSb) is ignored during normal program
execution, except for certain specialized instructions.
Thus, the PC can address up to 4M instruction words
of user program space. An instruction prefetch mecha-
nism is used to help maintain throughput. Program loop
constructs, free from loop count management over-
head, are supported using the DOand REPEATinstruc-
tions, both of which are interruptible at any point.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3 operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
The working register array consists of 16x16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer (SP) for interrupts and calls.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula-
tor or any working register can be shifted up to 16 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by
dedicating certain working registers to each address
space for the MAC class of instructions.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 "Data Address Space"). The X and Y
data space boundary is device specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
There are two methods of accessing data stored in
program memory:
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
• The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of pro-
gram space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an addi-
tional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 15
dsPIC30F3010/3011
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS Register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as Data,
Address or Offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated software Stack Pointer, and will
be automatically modified by exception processing and
subroutine calls and returns. However, W15 can be ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned
stack accesses, W15<0> is always clear.
Some of these registers have a Shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
Shadow register is used as a temporary holding regis-
ter and can transfer its contents to or from its host reg-
ister upon the occurrence of an event. None of the
Shadow registers are accessible directly. The following
rules apply for transfer of registers into and out of
shadows.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
• PUSH.Sand POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS Register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
• DOinstruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level status bits, IPL<2:0>, and the REPEAT active
status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a com-
plete word value which is then stacked.
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte wide data memory space accesses.
The upper byte of the SR register contains the DSP
adder/subtracter status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) status bit.
2.2.3
PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
DS70141D-page 16
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 2-1:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD0
AD15
AD39
AD31
DSP
Accumulators
ACCA
ACCB
PC22
PC0
0
Program Counter
0
7
P
A
G
TBLPAG
Data Table Page Address
0
7
PS
V
PA
G
PSVPAG
Program Space Visibility Page Address
15
15
0
0
RCOUNT
DCOUNT
REPEATLoop Counter
DOLoop Counter
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
IPL0 RA
OA OB
SA SB OAB SAB DA DC
SRH
N
OV
Z
C
IPL2 IPL1
STATUS Register
SRL
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 17
dsPIC30F3010/3011
The divide instructions must be executed within a
REPEATloop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the REPEATinstruction, as shown
in Table 2-1 (REPEATwill execute the target instruction
{operand value + 1} times). The REPEAT loop count
must be set up for 18 iterations of the DIV/DIVFinstruc-
tion. Thus, a complete divide operation requires 19
cycles.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The fol-
lowing instructions and data sizes are supported:
1. DIVF– 16/16 signed fractional divide
2. DIV.sd– 32/16 signed divide
3. DIV.ud– 32/16 unsigned divide
4. DIV.sw– 16/16 signed divide
5. DIV.uw– 16/16 unsigned divide
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
TABLE 2-1:
DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
DIV.sd
DIV.sw
DIV.ud
DIV.uw
Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
A block diagram of the DSP engine is shown in
Figure 2-2.
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
TABLE 2-2:
DSP INSTRUCTION
SUMMARY
Instruction
Algebraic Operation
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
CLR
ED
A = 0
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
No change in A
A = x * y
EDAC
MAC
MOVSAC
MPY
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUBand NEG.
MPY.N
MSC
A = – x * y
A = A – x * y
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for ACCA (SATA).
5. Automatic saturation on/off for ACCB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
DS70141D-page 18
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
S
a
40
16
40-bit Accumulator A
40-bit Accumulator B
40
t
Round
Logic
u
r
a
t
Carry/Borrow Out
Saturate
e
Adder
Carry/Borrow In
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 19
dsPIC30F3010/3011
2.4.1
MULTIPLIER
2.4.2.1
Adder/Subtracter, Overflow and
Saturation
The 17x17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17x17-bit
multiplier/scaler is a 33-bit value, which is sign-
extended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaking, the range of an N-bit two’s complement
integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
range is -32768 (0x8000) to 32767 (0x7FFF), including
0. For a 32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit
(QX format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1-21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF), including 0 and
has a precision of 3.01518x10-5. In fractional mode, a
16x16 multiply operation generates a 1.31 product,
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to sup-
port saturation and overflow; they are:
1. OA:
which has a precision of 4.65661x10-10
.
ACCA overflowed into guard bits
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiplies.
2. OB:
ACCB overflowed into guard bits
3. SA:
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4. SB:
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
The data accumulator consists of a 40-bit adder/sub-
tracter with automatic sign extension logic. It can select
one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADDand LACinstructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 5.0) is set. This
allows the user to take immediate action, for example,
to correct system gain.
DS70141D-page 20
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The SA and SB bits are modified each time data passes
through the adder/subtracter, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit
saturation, or bit 39 for 40-bit saturation) and will be
saturated (if saturation is enabled). When saturation is
not enabled, SA and SB default to bit 39 overflow and
thus indicate that a catastrophic overflow has occurred.
If the COVTE bit in the INTCON1 register is set, SA and
SB bits will generate an arithmetic warning trap when
saturation is disabled.
2.4.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
The overflow and saturation status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
2. [W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as
incremented by 2 (for a word write).
a
1.15 fraction. W13 is then
2.4.2.3
Round Logic
The round logic is a combinational block, which per-
forms a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least signif-
icant word (lsw) is simply discarded.
The device supports three Saturation and Overflow
modes.
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target
accumulator. The SA or SB bit is set and
remains set until cleared by the user. This is
referred to as ‘super saturation’ and provides
protection against erroneous data or unexpected
algorithm problems (e.g., gain calculations).
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this
algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally
positive 1.31 value (0x007FFFFFFF) or
maximally negative 1.31 value (0x0080000000)
into the target accumulator. The SA or SB bit is
set and remains set until cleared by the user.
When this Saturation mode is in effect, the guard
bits are not used (so the OA, OB or OAB bits are
never set).
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb (bit
16 of the accumulator) of ACCxH is examined. If it is ‘1’,
ACCxH is incremented. If it is ‘0’, ACCxH is not modi-
fied. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
3. Bit 39 Catastrophic Overflow
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4). Note
that for the MACclass of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 21
dsPIC30F3010/3011
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the
maximum positive 1.15 value, 0x7FFF. For input data
less than 0xFF8000, data written to memory is forced
to the maximum negative 1.15 value, 0x8000. The MSb
of the source (bit 39) is used to determine the sign of
the operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
to 31 for right shifts, and bit positions 0 to 15 for left
shifts.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70141D-page 22
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dsPIC30F3010/3011
FIGURE 3-1:
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F3010/3011
3.0
MEMORY ORGANIZATION
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Reset - GOTOInstruction
000000
000002
000004
Reset - Target Address
Vector Tables
Interrupt Vector Table
3.1
Program Address Space
The program address space is 4M instruction words. It
is addressable by the 23-bit PC, table instruction
Effective Address (EA), or data space EA, when
program space is mapped into data space, as defined
by Table 3-1. Note that the program space address is
incremented by two between successive program
words, in order to provide compatibility with data space
addressing.
00007E
000080
000084
0000FE
000100
Reserved
Alternate Vector Table
User Flash
Program Memory
(8K instructions)
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the configuration bits. Otherwise, bit 23 is always
clear.
003FFE
004000
Reserved
(Read 0’s)
7FFBFE
7FFC00
Data EEPROM
(1 Kbyte)
7FFFFE
800000
Reserved
8005BE
8005C0
UNITID (32 instr.)
Reserved
8005FE
800600
F7FFFE
Device Configuration
Registers
F80000
F8000E
F80010
Reserved
DEVID (2)
FEFFFE
FF0000
FFFFFE
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 23
dsPIC30F3010/3011
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
User
User
(TBLPAG<7> = 0)
0
PC<22:1>
0
TBLRD/TBLWT
TBLPAG<7:0>
TBLPAG<7:0>
PSVPAG<7:0>
Data EA <15:0>
Data EA <15:0>
TBLRD/TBLWT
Configuration
(TBLPAG<7> = 1)
Program Space Visibility User
0
Data EA <14:0>
FIGURE 3-2:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
0
0
Select
1
EA
Using
Program
Space
PSVPAG Reg
Visibility
8 bits
15 bits
EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/
Configuration
Space
Byte
24-bit EA
Select
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
DS70141D-page 24
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
A set of Table Instructions are provided to move byte or
word-sized data to and from program space.
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
1. TBLRDL:Table Read Low
Word: Read the lsw of the program
address;
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 "Data
Access From Program Memory Using Program
Space Visibility"). The TBLRDLand TBLWTLinstruc-
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data space. The TBLRDHand TBLWTHinstruc-
tions are the only method whereby the upper 8 bits of a
program space word can be accessed as data.
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
2. TBLWTL:Table Write Low (refer to Section 6.0
"Flash Program Memory" for details on Flash
Programming).
3. TBLRDH:Table Read High
Word: Read the msw of the program
address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the lsw, and TBLRDH
and TBLWTH access the space which contains the
MSB.
4. TBLWTH:Table Write High (refer to Section 6.0
"Flash Program Memory" for details on Flash
Programming).
Figure 3-2 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (lsw)
PC Address
23
8
16
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
(Read as ‘0’).
TBLRDL.B (Wn<0> = 1)
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 25
dsPIC30F3010/3011
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MSB)
TBLRDH.W
PC Address
23
8
0
16
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
TBLRDH.B (Wn<0> = 1)
Note that by incrementing the PC by 2 for each
program memory word, the 15 LSb of data space
addresses directly map to the 15 LSb in the
corresponding program space addresses. The
remaining bits are provided by the Program Space
Visibility Page register, PSVPAG<7:0>, as shown in
Figure 3-5.
3.1.2
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/Hinstructions).
Note:
PSV access is temporarily disabled during
Table Reads/Writes.
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 "DSP
Engine".
For instructions that use PSV which are executed
outside a REPEATloop:
• The following instructions will require one instruc-
tion cycle in addition to the specified execution
time:
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
- MACclass of instructions with data operand
prefetch
- MOVinstructions
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically
contain state (variable) data for DSP operations,
- MOV.Dinstructions
• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEATloop:
whereas
X data space should typically contain
coefficient (constant) data.
• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer
to the “dsPIC30F/33F Programmer’s Reference Man-
ual” (DS70157) for details on instruction encoding.
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEATloop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
DS70141D-page 26
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Program Space
Data Space
0x0000
0x8000
0x000100
PSVPAG(1)
0x00
8
15
15
EA<15> =
0
Data
Space
EA
16
23
15
0
Address
Concatenation
EA<15> = 1
0x001200
0x003FFE
15
23
Upper half of Data
Space is mapped
into Program Space
0xFFFF
Data Read
BSET CORCON,#2
; PSV bit set
MOV
MOV
MOV
#0x00, W0
W0, PSVPAG
0x9200, W0
; Set PSVPAG register
; Access program memory location
; using a data space access
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
When executing any instruction other than one of the
MACclass of instructions, the X block consists of the 64
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64 Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MACclass instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
A data space memory map is shown in Figure 3-6.
Figure 3-7 shows a graphical summary of how X and Y
data spaces are accessed for MCU and DSP
instructions.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 27
dsPIC30F3010/3011
FIGURE 3-6:
dsPIC30F3010/3011 DATA SPACE MEMORY MAP
LSB
Address
MSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
Y Data RAM (Y)
3072 bytes
Near
Data
1 Kbyte
0x09FF
0x0A01
0x09FE
0x0A00
Space
SRAM Space
0x0BFF
0x0C01
0xBFE
0x0C00
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
DS70141D-page 28
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dsPIC30F3010/3011
DATA SPACE FOR MCU AND DSP (MACCLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
FIGURE 3-7:
SFR SPACE
UNUSED
Y SPACE
UNUSED
(Y SPACE)
UNUSED
Non-MACClass Ops (Read/Write)
MACClass Ops (Write)
MACClass Ops Read Only
Indirect EA using any W
Indirect EA using W10, W11 Indirect EA using W8, W9
© 2007 Microchip Technology Inc.
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DS70141D-page 29
dsPIC30F3010/3011
3.2.2
DATA SPACES
3.2.3
DATA SPACE WIDTH
The X data space is used by all instructions and sup-
ports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data mem-
ory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
The X data space also supports Modulo Addressing for
all instructions, subject to addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions
dedicates two W register pointers, W10 and W11, to
always address Y data space, independent of X data
space, whereas W8 and W9 always address X data
space. Note that during accumulator write back, the
data address space is considered a combination of X
and Y data spaces, so the write occurs across the X
bus. Consequently, the write can be to any address in
the entire data space.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word-sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X data path, as part of the composite linear space.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
FIGURE 3-8:
DATA ALIGNMENT
LSB
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
MSB
15
8 7
0
Attempted Operation
Data Returned
0000
0002
0004
0001
Byte 1
Byte 3
Byte 5
Byte 0
Byte 2
Byte 4
EA = an unimplemented address
0x0000
0x0000
0003
0005
W8 or W9 used to access Y data
space in a MACinstruction
W10 or W11 used to access X
0x0000
data space in a MACinstruction
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70141D-page 30
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All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
There is a Stack Pointer Limit register (SPLIM) associ-
ated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM<0>
is forced to ‘0’, because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap will not occur.
The stack error trap will occur on a subsequent push
operation. Thus, for example, if it is desirable to cause
a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
Similarly, a stack pointer underflow (stack error) trap is
generated when the Stack Pointer Address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
CALLSTACK FRAME
3.2.6
SOFTWARE STACK
0x0000
15
0
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
PC<15:0>
W15 (before CALL)
W15 (after CALL)
000000000PC<22:16>
<Free Word>
POP: [--W15]
PUSH: [W15++]
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 31
TABLE 3-3:
CORE REGISTER MAP
Address
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
(Home)
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032
0034
0036
0038
003A
003C
003E
0040
0042
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
0000 0000 0000 0000
W0
W0 / WREG
W1
W1
W2
W2
W3
W3
W4
W4
W5
W5
W6
W6
W7
W7
W8
W8
W9
W9
W10
W10
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
Sign-Extension (ACCA<39>)
Sign-Extension (ACCB<39>)
ACCAU
ACCBL
ACCBH
ACCBU
PCL
—
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCH
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
DOSTARTH
DOENDL
DOENDH
SR
—
TBLPAG
PSVPAG
—
RCOUNT
DCOUNT
DOSTARTL
0
0
—
—
—
—
—
—
—
—
—
DOSTARTH
DOENDL
—
—
—
—
—
—
—
—
—
DOENDH
N
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
OV
Z
C
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
TABLE 3-3:
CORE REGISTER MAP (CONTINUED)
Address
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
(Home)
0044
0046
0048
004A
004C
004E
0050
0052
0000 0000 0010 0000
0000 0000 0000 0000
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
CORCON
MODCON
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
—
—
—
—
US
—
EDT
DL2
DL1
DL0
SATA
SATB SATDW ACCSAT
YWM<3:0>
IPL3
PSV
RND
IF
XMODEN YMODEN
BWM<3:0>
XWM<3:0>
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
0
1
0
1
BREN
XB<14:0>
DISICNT
—
—
DISICNT<13:0>
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 34
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
4.1.1
FILE REGISTER INSTRUCTIONS
4.0
ADDRESS GENERATOR UNITS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word-sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs sup-
port three types of data addressing:
4.1.2
MCU INSTRUCTIONS
• Linear Addressing
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
where Operand 1 is always a working register (i.e., the
addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• 5-bit or 10-bit Literal
Note:
Not all instructions support all the address-
ing modes given above. Individual
instructions may support different subsets
of these addressing modes.
TABLE 4-1:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description
The address of the file register is specified explicitly.
Addressing Mode
File Register Direct
Register Direct
The contents of a register are accessed directly.
The contents of Wn forms the EA.
Register Indirect
Register Indirect Post-modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 35
dsPIC30F3010/3011
In summary, the following addressing modes are
supported by the MACclass of instructions:
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
• Register Indirect
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
• Register Indirect Post-modified by 2
• Register Indirect Post-modified by 4
• Register Indirect Post-modified by 6
• Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADDAcc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
In summary, the following addressing modes are
supported by Move and Accumulator instructions:
• Register Direct
4.2
Modulo Addressing
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
Modulo Addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
• 16-bit Literal
Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
Addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for
Modulo Addressing, since these two registers are used
as the Stack Frame Pointer and Stack Pointer,
respectively.
Note:
Not all instructions support all the address-
ing modes given above. Individual
instructions may support different subsets
of these addressing modes.
4.1.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR,ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MACinstructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for
incrementing buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
The only exception to the usage restrictions is for
buffers which have a power-of-2 length. As these
buffers satisfy the start and end address criteria, they
may operate in a Bidirectional mode, (i.e., address
boundary checks will be performed on both the lower
and upper address boundaries).
Note:
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70141D-page 36
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
4.2.1
START AND END ADDRESS
4.2.2
W ADDRESS REGISTER
SELECTION
The Modulo Addressing scheme requires that a
starting and an end address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
The Modulo and Bit-Reversed Addressing Control
register MODCON<15:0> contains enable flags, as
well as a W register field to specify the W address
registers. The XWM and YWM fields select which
registers will operate with Modulo Addressing. If XWM
= 15, X RAGU and X WAGU Modulo Addressing are
disabled. Similarly, if YWM = 15, Y AGU Modulo
Addressing is disabled.
Note:
Y-space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON<14>.
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DO
#0x1100,W0
W0, XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
#0x0000,W0
#0x1110,W1
AGAIN,#0x31
W0, [W1++]
;set modulo start address
;set modulo end address
0x1100
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
MOV
AGAIN: INC
W0,W0
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032words
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 37
dsPIC30F3010/3011
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries check for addresses less than or greater than the
upper (for incrementing buffers) and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word-sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be gener-
ated instead. When Bit-Reversed Addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word-sized data is a requirement, the
LSb of the EA is ignored (and always clear).
4.3
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing will assume priority when active for the
X WAGU, and X WAGU Modulo Address-
ing will be disabled. However, Modulo
Addressing will continue to function in the
X RAGU.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
1. BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed
Addressing) and
2. the BREN bit is set in the XBREV register and
3. the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b2 b3 b4
0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1
Bit-Reversed Address
Pivot Point
XB = 0x0008for a 16-word Bit-Reversed Buffer
DS70141D-page 38
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal
Address
Bit-Reversed
Address
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Decimal
A3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Decimal
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
TABLE 4-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB<14:0> Bit-Reversed Address Modifier Value
512
256
128
64
32
16
8
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
4
2
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 39
dsPIC30F3010/3011
NOTES:
DS70141D-page 40
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
• INTCON1<15:0>, INTCON2<15:0>
5.0
INTERRUPTS
Global interrupt control functions are derived from
these two registers. INTCON1 contains the
control and status flags for the processor
exceptions. The INTCON2 register controls the
external interrupt request signal behavior and the
use of the alternate vector table.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
Interrupt Flag bits get set when an
interrupt condition occurs, regardless of
the state of its corresponding Enable bit.
User software should ensure the
appropriate Interrupt Flag bits are clear
prior to enabling an interrupt.
The dsPIC30F3010/3011 has 29 interrupt sources and
processor exceptions (traps), which must be
arbitrated based on a priority scheme.
4
The CPU is responsible for reading the Interrupt
Vector Table (IVT) and transferring the address con-
tained in the interrupt vector to the program counter.
The interrupt vector is transferred from the program
data bus into the program counter, via a 24-bit wide
multiplexer on the input of the program counter.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Table 5-1. Levels 7 and 1 repre-
sent the highest and lowest maskable priorities,
respectively.
The Interrupt Vector Table (IVT) and Alternate
Interrupt Vector Table (AIVT) are placed near the
beginning of program memory (0x000004). The IVT
and AIVT are shown in Figure 5-1.
Note:
Assigning a priority level of 0 to an
interrupt source is equivalent to disabling
that interrupt.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers (SFR):
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Note:
The IPL bits become read-only whenever
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for fea-
tures like edge or level triggered interrupts, interrupt-
on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All Interrupt Enable Control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
• IPC0<15:0>... IPC11<7:0>
The user assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program
Memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to Figure 5-2).
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Figure 5-2). These locations contain 24-bit addresses,
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space, or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTOinstruction to this vector space will also generate
an address error trap.
• IPL<3:0> The current CPU priority level is
explicitly stored in the IPL bits. IPL<3> is present
in the CORCON register, whereas IPL<2:0> are
present in the STATUS Register (SR) in the
processor core.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 41
dsPIC30F3010/3011
TABLE 5-1:
INTERRUPT VECTOR TABLE
5.1
Interrupt Priority
INT
Vector
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the 3
LSbs of each nibble, within the IPCx register(s). Bit 3
of each nibble is not used and is read as a ‘0’. These
bits define the priority level assigned to a particular
interrupt by the user.
Interrupt Source
Number Number
Highest Natural Order Priority
0
1
8
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer 1
9
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
3
Note:
The user-selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
4
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer 2
5
6
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
7
T3 – Timer 3
8
SPI #1
9
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45-53
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
2
SI2C – I C™ Slave Interrupt
2
MI2C – I C Master Interrupt
Input Change Interrupt
INT1 – External Interrupt 1
IC7 – Input Capture 7
IC8 – Input Capture 8
OC3 – Output Compare 3*
OC4 – Output Compare 4*
T4 – Timer 4
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
Note1: The natural order priority scheme has 0 as
the highest priority and 53 as the lowest
priority.
2: The natural order priority number is the
T5 – Timer 5
same as the INT number.
INT2 – External Interrupt 2
U2RX – UART2 Receiver*
U2TX – UART2 Transmitter*
Reserved
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PWM Fault
A Interrupt can be given a priority of 7. The INT0
(external interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM – PWM Period Match
QEI – QEI Interrupt
Reserved
Reserved
FLTA – PWM Fault A
Reserved
53-61 Reserved
Lowest Natural Order Priority
* Available on dsPIC30F3011 only
DS70141D-page 42
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
5.2
Reset Sequence
5.3
Traps
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The
processor initializes its registers in response to a
Reset, which forces the PC to zero. The processor then
begins program execution at location 0x000000. A
GOTOinstruction is stored in the first program memory
location, immediately followed by the address target for
the GOTOinstruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
5.2.1
RESET SOURCES
There are 6 sources of error which will cause a device
reset.
• Watchdog Time-out:
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
• Brown-out Reset (BOR):
5.3.1
TRAP SOURCES
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
Math Error Trap:
The math error trap executes under the following three
circumstances:
1. Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2. If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
3. If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4. If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 43
dsPIC30F3010/3011
Address Error Trap:
5.3.2
HARD AND SOFT TRAPS
This trap is initiated when any of the following
circumstances occurs:
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
1. A misaligned data word access is attempted.
2. A data fetch from our unimplemented data
memory location is attempted.
3. A data access of an unimplemented program
memory location is attempted.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
4. An instruction fetch from vector space is
attempted.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Note:
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
5. Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
6. Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
Stack Error Trap:
FIGURE 5-1:
TRAP VECTORS
This trap is initiated under the following conditions:
Reset - GOTOInstruction
Reset - GOTOAddress
0x000000
0x000002
0x000004
1. The Stack Pointer is loaded with a value which
is greater than the (user programmable) limit
value written into the SPLIM register (stack
overflow).
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
2. The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
IVT
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
0x000014
Oscillator Fail Trap:
—
—
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
0x00007E
0x000080
0x000082
Reserved
Reserved
0x000084
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
AIVT
0x000094
0x0000FE
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
DS70141D-page 44
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
5.4
Interrupt Sequence
5.5
Alternate Vector Table
In Program Memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and
exception processes use the alternate vectors instead
of the default vectors. The alternate vectors are
organized the same as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a
support environment without requiring the interrupt
vectors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 5-2. The low byte of the
STATUS register contains the processor priority level at
the time, prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this inter-
rupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine (ISR).
If the AIVT is not required, the program memory
allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using Shadow
registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The
Shadow registers are accessible using the PUSH.S
and POP.S instructions only. When the processor
vectors to an interrupt, the PUSH.Sinstruction can be
used to store the current value of the aforementioned
registers into their respective Shadow registers.
FIGURE 5-2:
INTERRUPT STACK
FRAME
0x0000 15
0
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same
instructions. Users must save the key registers in
software during a lower priority interrupt, if the higher
priority ISR uses fast context saving.
PC<15:0>
SRL IPL3 PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
5.7
External Interrupt Requests
Note1: The user can always lower the priority level
by writing a new value into SR. The Interrupt
Service Routine must clear the interrupt flag
bits in the IFSx register before lowering the
processor interrupt priority, in order to avoid
recursive interrupts.
The dsPIC30F3010/3011 interrupt controller supports
three external interrupt request signals, INT0-INT2.
These inputs are edge sensitive; they require a low-to-
high or a high-to-low transition to generate an interrupt
request. The INTCON2 register has five bits, INT0EP-
INT4EP, that select the polarity of the edge detection
circuitry.
2: The IPL3 bit (CORCON<3>) is always clear
when interrupts are being processed. It is
set only during execution of traps.
5.8
Wake-up from Sleep and Idle
The RETFIE (Return from Interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
The interrupt controller may be used to wake up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine needed to process the interrupt request.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 45
TABLE 5-2:
INTERRUPT CONTROLLER REGISTER MAP(1)
SFR
Name
ADR Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0000 0100 0100
0000 0000 0000 0000
0000 0000 0000 0000
0100 0000 0100 0100
0100 0000 0000 0100
0000 0000 0000 0000
INTCON1 0080 NSTDIS
INTCON2 0082 ALTIVT
—
—
—
—
—
—
—
OVATE OVBTE COVTE
—
—
—
—
—
—
MATHERR ADDRERR STKERR OSCFAIL
—
DISI
—
—
—
—
IC2IF
OC4IF
—
—
T1IF
OC3IF
—
INT2EP INT1EP INT0EP
IFS0
IFS1
IFS2
IEC0
IEC1
IEC2
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
0084 CNIF MI2CIF SI2CIF NVMIF
ADIF U1TXIF U1RXIF SPI1IF
T3IF
T2IF OC2IF
OC1IF
IC8IF
—
IC1IF
IC7IF
INT0IF
INT1IF
—
0086
0088
—
—
—
—
—
—
—
—
—
—
—
U2TXIF U2RXIF INT2IF
QEIIF PWMIF
T3IE
U2TXIE U2RXIE INT2IE T5IE
T5IF
T4IF
—
FLTAIF
—
—
—
008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE
T2IE OC2IE
IC2IE
OC4IE
—
T1IE
OC3IE
—
OC1IE
IC8IE
—
IC1IE
INT0IE
INT1IE
—
008E
0090
0094
0096
0098
009A
009C
009E
00A0
00A2
00A4
00A6
00A8
00AA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FLTAIE
—
—
—
T4IE
—
IC7IE
—
QEIIE PWMIE
—
—
T1IP<2:0>
T31P<2:0>
ADIP<2:0>
CNIP<2:0>
OC3IP<2:0>
INT2IP<2:0>
—
OC1IP<2:0>
—
—
—
—
—
—
IC1IP<2:0>
OC2IP<2:0>
U1RXIP<2:0>
SI2CIP<2:0>
IC7IP<2:0>
T4IP<2:0>
U2TXIP<2:0>
—
—
INT0IP<2:0>
IC2IP<2:0>
SPI1IP<2:0>
NVMIP<2:0>
INT1IP<2:0>
OC4IP<2:0>
U2RXIP<2:0>
—
—
T2IP<2:0>
—
—
U1TXIP<2:0>
—
—
MI2CIP<2:0>
—
—
IC8IP<2:0>
—
—
T5IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWMIP<2:0>
FLTAIP<2:0>
—
—
INT41IP<2:0>
—
—
INT3IP<2:0>
QEIIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: u= uninitialized bit; — = unimplemented
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
6.2
Run-Time Self-Programming
(RTSP)
6.0
FLASH PROGRAM MEMORY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT(table write) instructions.
With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 32 instructions (96 bytes) at a time.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
6.3
Table Instruction Operation Summary
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits <15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
Word or Byte mode.
1. In-Circuit Serial Programming™ (ICSP™)
capabilities
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan access program memory in Word or
Byte mode.
2. Run Time Self-Programming (RTSP)
6.1
In-Circuit Serial Programming
(ICSP)
A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manu-
facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 6-1:
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
16 bits
Byte
Select
User/Configuration
Space Select
24-bit EA
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 47
dsPIC30F3010/3011
6.4
RTSP Operation
6.5
RTSP Control Registers
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program 32
instructions at one time.
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The addresses loaded must always be from an
even group of 32 boundary.
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
6.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWTinstructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions.
6.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register
captures the EA<23:16> of the last table instruction
that has been executed.
All of the table-write operations are single-word writes
(2 instruction cycles), because only the table latches
are written.
After the latches are written, a programming operation
needs to be initiated to program the data.
6.5.4
NVMKEY REGISTER
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
"Programming Operations" for further details.
Note:
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
DS70141D-page 48
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
6.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
5. Program 32 instruction words into program
Flash.
a) Setup NVMCON register for multi-word,
program Flash, program and set WREN bit.
b) Write ‘55’ to NVMKEY.
c) Write ‘AA’ to NVMKEY.
6.6.1
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
d) Set the WR bit. This will begin program
cycle.
The user can erase or program one row of program
Flash memory at a time. The general process is:
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
1. Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
6. Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
2. Update the data image with the desired new
data.
6.6.2
ERASING A ROW OF PROGRAM
MEMORY
3. Erase program Flash row.
a) Setup NVMCON register for multi-word,
program Flash, erase and set WREN bit.
Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write ‘55’ to NVMKEY.
d) Write ‘AA’ to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 6-1:
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV
MOV
#0x4041,W0
W0 NVMCON
;
; Init NVMCON SFR
,
; Init pointer to row to be ERASED
MOV
MOV
MOV
MOV
DISI
#tblpage(PROG_ADDR),W0
;
W0 NVMADRU
; Initialize PM Page Boundary SFR
; Intialize in-page EA[15:0] pointer
; Intialize NVMADR SFR
; Block all interrupts with priority <7
; for next 5 instructions
,
#tbloffset(PROG_ADDR),W0
W0, NVMADR
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 49
dsPIC30F3010/3011
6.6.3
LOADING WRITE LATCHES
Example 6-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches. 32
TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the table pointer.
EXAMPLE 6-2:
LOADING WRITE LATCHES
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000,W0
;
W0 TBLPAG
; Initialize PM Page Boundary SFR
; An example program memory address
,
#0x6000,W0
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0,W2
#HIGH_BYTE_0,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
; 1st_program_word
MOV
MOV
#LOW_WORD_1,W2
#HIGH_BYTE_1,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
;
2nd_program_word
MOV
MOV
#LOW_WORD_2,W2
#HIGH_BYTE_2,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
•
•
•
; 31st_program_word
MOV
MOV
#LOW_WORD_31,W2
#HIGH_BYTE_31,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
Note: In Example 6-2, the contents of the upper byte of W3 have no effect.
6.6.4
INITIATING THE PROGRAMMING
SEQUENCE
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.
EXAMPLE 6-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
DS70141D-page 50
Confidential
© 2007 Microchip Technology Inc.
TABLE 6-1:
NVM REGISTER MAP(1)
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All RESETS
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
PROGOP<6:0>
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
NVMADR
NVMADRU
NVMKEY
0762
0764
0766
NVMADR<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMADR<22:16>
NVMKEY<7:0>
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 52
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Control bit WR initiates write operations, similar to pro-
gram Flash writes. This bit cannot be cleared, only set,
in software. This bit is cleared in hardware at the com-
pletion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
7.0
DATA EEPROM MEMORY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
The Data EEPROM Memory is readable and writable
during normal operation over the entire VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 4.0
"Address Generator Units", these registers are:
Note:
Interrupt flag bit NVMIF in the IFS0
register is set when write is complete. It
must be cleared in software.
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
7.1
Reading the Data EEPROM
A TBLRD instruction reads a word at the current
program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in Example 7-1.
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, is used to address the EEPROM
location being accessed. TBLRDLand TBLWTLinstruc-
tions are used to read and write data EEPROM. The
dsPIC30F3010/3011 device has 1 Kbyte (512 words) of
data EEPROM, with an address range from 0x7FFC00
to 0x7FFFFE.
EXAMPLE 7-1:
DATA EEPROM READ
MOV
MOV
MOV
#LOW_ADDR_WORD,W0 ; Init Pointer
#HIGH_ADDR_WORD,W1
W1 TBLPAG
,
TBLRDL [ W0 ], W4
; read data EEPROM
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 53
dsPIC30F3010/3011
7.2
Erasing Data EEPROM
7.2.1
ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially
point to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM, and
set the ERASE and WREN bits in NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-2.
EXAMPLE 7-2:
DATA EEPROM BLOCK ERASE
; Select data EEPROM block, ERASE, WREN bits
MOV
MOV
#0x4045,W0
W0 NVMCON
; Initialize NVMCON SFR
,
; Start erase cycle by setting WR after writing key sequence
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
;
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
7.2.2
ERASING A WORD OF DATA
EEPROM
The TBLPAG and NVMADR registers must point to
the block. Select erase a block of data Flash, and set
the ERASE and WREN bits in NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-3.
EXAMPLE 7-3:
DATA EEPROM WORD ERASE
; Select data EEPROM word, ERASE, WREN bits
MOV
MOV
#0x4044,W0
W0 NVMCON
,
; Start erase cycle by setting WR after writing key sequence
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
;
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
DS70141D-page 54
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
7.3
Writing to the Data EEPROM
To write an EEPROM data location, the following
sequence must be followed:
1. Erase data EEPROM word.
a) Select word, data EEPROM, erase and set
WREN bit in NVMCON register.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM, due to unexpected code
execution. The WREN bit should be kept clear at all
times, except when updating the EEPROM. The
WREN bit is not cleared by hardware.
b) Write address of word to be erased into
NVMADRU/NVMADR.
c) Enable NVM interrupt (optional).
d) Write ‘55’ to NVMKEY.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
e) Write ‘AA’ to NVMKEY.
f) Set the WR bit. This will begin erase cycle.
g) Either poll NVMIF bit or wait for NVMIF
interrupt.
h) The WR bit is cleared when the erase cycle
ends.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt, or poll this bit. NVMIF
must be cleared by software.
2. Write data word into data EEPROM write
latches.
3. Program 1 data word into data EEPROM.
a) Select word, data EEPROM, program, and
set WREN bit in NVMCON register.
7.3.1
WRITING A WORD OF DATA
EEPROM
b) Enable NVM write done interrupt (optional).
c) Write ‘55’ to NVMKEY.
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 7-4.
d) Write ‘AA’ to NVMKEY.
e) Set The WR bit. This will begin program
cycle.
f) Either poll NVMIF bit or wait for NVM
interrupt.
g) The WR bit is cleared when the write cycle
ends.
EXAMPLE 7-4:
DATA EEPROM WORD WRITE
; Point to data memory
MOV
MOV
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
; Init pointer
MOV
W1 TBLPAG
,
MOV
#LOW(WORD),W2
; Get data
TBLWTL
W2 [ W0]
; Write data
,
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
MOV
#0x4004,W0
W0 NVMCON
,
; Operate key to allow write operation
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
,
#0xAA,W1
W1 NVMKEY
; Write the 0xAA key
; Initiate program sequence
,
NVMCON,#WR
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 55
dsPIC30F3010/3011
7.3.2
WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
EXAMPLE 7-5:
DATA EEPROM BLOCK WRITE
MOV
MOV
#LOW_ADDR_WORD,W0 ; Init pointer
#HIGH_ADDR_WORD,W1
MOV
W1 TBLPAG
,
MOV
#data1,W2
; Get 1st data
TBLWTL
MOV
W2 [ W0]++
#data2,W2
; write data
; Get 2nd data
,
TBLWTL
MOV
W2 [ W0]++
#data3,W2
; write data
; Get 3rd data
,
TBLWTL
MOV
W2 [ W0]++
#data4,W2
; write data
; Get 4th data
,
TBLWTL
MOV
W2 [ W0]++
#data5,W2
; write data
; Get 5th data
,
TBLWTL
MOV
W2 [ W0]++
#data6,W2
; write data
; Get 6th data
,
TBLWTL
MOV
W2 [ W0]++
#data7,W2
; write data
; Get 7th data
,
TBLWTL
MOV
W2 [ W0]++
#data8,W2
; write data
; Get 8th data
,
TBLWTL
MOV
W2 [ W0]++
#data9,W2
; write data
; Get 9th data
,
TBLWTL
MOV
W2 [ W0]++
#data10,W2
; write data
; Get 10th data
,
TBLWTL
MOV
W2 [ W0]++
#data11,W2
; write data
; Get 11th data
,
TBLWTL
MOV
W2 [ W0]++
#data12,W2
; write data
; Get 12th data
,
TBLWTL
MOV
W2 [ W0]++
#data13,W2
; write data
; Get 13th data
,
TBLWTL
MOV
W2 [ W0]++
#data14,W2
; write data
; Get 14th data
,
TBLWTL
MOV
W2 [ W0]++
#data15,W2
; write data
; Get 15th data
,
TBLWTL
MOV
W2 [ W0]++
#data16,W2
; write data
; Get 16th data
,
TBLWTL
MOV
MOV
W2 [ W0]++
#0x400A,W0
; write data. The NVMADR captures last table access address.
; Select data EEPROM for multi word op
; Operate Key to allow program operation
; Block all interrupts with priority <7
; for next 5 instructions
,
W0 NVMCON
,
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
,
#0xAA,W1
W1 NVMKEY
; Write the 0xAA key
; Start write cycle
,
NVMCON,#WR
7.4
Write Verify
7.5
Protection Against Spurious Write
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together,
help prevent an accidental write during brown-out,
power glitch or software malfunction.
DS70141D-page 56
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
8.0
I/O PORTS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
The format of the registers for PORTX is shown in
Table 8-1.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
The TRISX register controls the direction of the pins.
The LATX register supplies data to the outputs, and is
readable/writable. Reading the PORTX register yields
the state of the input pins, while writing the PORTX
register modifies the contents of the LATX register.
8.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the Parallel Port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
A parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-2 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 8-1 shows the
formats of the registers for the shared ports, PORTB
through PORTF.
All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISX) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
FIGURE 8-1:
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Dedicated Port Module
Read TRIS
I/O Cell
TRIS Latch
D
Q
Data Bus
WR TRIS
CK
Data Latch
I/O Pad
D
Q
WR LAT +
WR Port
CK
Read LAT
Read Port
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 57
dsPIC30F3010/3011
FIGURE 8-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
Peripheral Output Data
1
0
Output Enable
1
0
PIO Module
Output Data
Read TRIS
I/O Pad
Data Bus
WR TRIS
D
Q
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
8.2.1
I/O PORT WRITE/READ TIMING
8.2
Configuring Analog Port Pins
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
EXAMPLE 8-1:
PORT WRITE/READ
EXAMPLE
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
MOV
0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
MOV
NOP
W0, TRISBB ; and PORTB<7:0> as outputs
; Delay 1 cycle
btss PORTB, #13 ; Next Instruction
DS70141D-page 58
Confidential
© 2007 Microchip Technology Inc.
TABLE 8-1:
dsPIC30F3010 PORT REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0001 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
TRISB
02C6
02C8
02CA
TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PORTB
LATB
TRISC
PORTC
LATC
02CC TRISC15 TRISC14 TRISC13
02CE RC15 RC14 RC13
02D0 LATC15 LATC14 LATC13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1110 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 1111
0000 0000 0000 0000
0000 0000 0000 0000
—
TRISD
PORTD
LATD
02D2
02D4
02D6
02D8
02DA
02DC
02DE
02E0
02E2
TRISD3 TRISD2 TRISD1 TRISD0
RD3 RD2 RD1 RD0
LATD3 LATD2 LATD1 LATD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE
PORTE
LATE
TRISE8
RE8
LATE8
—
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
RE5 RE4 RE3 RE2 RE1 RE0
LATE5 LATE4 LATE3 LATE2 LATE1 LATE0
0000 0001 0011 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0111 1111
0000 0000 0000 0000
0000 0000 0000 0000
TRISF
PORTF
LATF
TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
RF6 RF5 RF4 RF3 RF2 RF1 RF0
LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0
—
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
TABLE 8-2:
dsPIC30F3011 PORT REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0011 1111
0000 0000 0000 0000
0000 0000 0000 0000
TRISB
02C6
02C8
02CB
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
RB5 RB4 RB3 RB2 RB1 RB0
LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PORTB
LATB
—
TRISC
PORTC
LATC
02CC TRISC15 TRISC14 TRISC13
02CE RC15 RC14 RC13
02D0 LATC15 LATC14 LATC13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1110 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0011
0000 0000 0000 0000
0000 0000 0000 0000
—
—
TRISD
PORTD
LATD
02D2
02D4
02D6
02D8
02DA
02DC
02EE
02E0
02E2
TRISD1 TRISD0
RD1 RD0
LATD1 LATD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE
PORTE
LATE
TRISE8
RE8
LATE8
—
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
RE5 RE4 RE3 RE2 RE1 RE0
LATE5 LATE4 LATE3 LATE2 LATE1 LATE0
0000 0001 0011 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 1100
0000 0000 0000 0000
0000 0000 0000 0000
TRISF
PORTF
LATF
TRISF3 TRISF2
RF3 RF2
LATF3 LATF2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
8.3
Input Change Notification Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This module is capable of
detecting input change-of-states even in Sleep mode,
when the clocks are disabled. There are 10 external
signals (CN0 through CN7, CN17 and CN18) that may
be selected (enabled) for generating an interrupt
request on a change-of-state.
Please refer to the Pin Diagrams for CN pin locations.
TABLE 8-3:
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)
SFR Name Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
CNEN1
CNPU1
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000 0000 0000 0000
0000 0000 0000 0000
00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE
CN2PUE
CN1PUE
CN0PUE
Legend: u= uninitialized bit; — = unimplemented bit
Note 1:
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit
positions, are available on this device.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 61
dsPIC30F3010/3011
NOTES:
DS70141D-page 62
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
9.0
TIMER1 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the Period register PR1, then
resets to ‘0’ and continues to count.
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1 depicts the simplified block diagram of the
16-bit Timer1 Module.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
Note:
Timer1 is a ‘Type A’ timer. Please refer to
the specifications for a Type A timer in
Section 23.0 "Electrical Characteris-
tics" of this document.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0and continues.
The following sections provide a detailed description,
including setup and control registers along with associ-
ated block diagrams for the operational modes of the
timers.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free-running interval timer/counter. The 16-bit timer has
the following modes:
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
When the timer is configured for the Asynchronous mode
of operation and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit period register match or falling
edge of external gate signal
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 63
dsPIC30F3010/3011
FIGURE 9-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
PR1
Comparator x 16
TMR1
Equal
Reset
TSYNC
1
Sync
0
0
1
T1IF
Event Flag
Q
D
TGATE
Q
CK
TGATE
TCKPS<1:0>
2
TON
SOSCO/
T1CK
1X
Gate
Sync
Prescaler
1, 8, 64, 256
LPOSCEN
0 1
00
SOSCI
TCY
9.1
Timer Gate Operation
9.3
Timer Operation During Sleep
Mode
The 16-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal TCY
to increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 1) and
• The TSYNC bit (T1CON<2>) is asserted to a logic
0, which defines the external clock source as
asynchronous
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
When all three conditions are true, the timer will
continue to count up to the Period register and be reset
to 0x0000.
9.2
Timer Prescaler
When a match between the timer and the Period
register occurs, an interrupt can be generated, if the
respective Timer Interrupt Enable bit is asserted.
The input clock (FOSC/4 or external clock) to the 16-bit
Timer, has a prescale option of 1:1, 1:8, 1:64 and 1:256
selected by control bits TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the fol-
lowing occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
DS70141D-page 64
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
9.5.1
RTC OSCILLATOR OPERATION
9.4
Timer Interrupt
When the TON = 1, TCS = 1and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register, and is then reset to ‘0’.
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
Period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
When the CPU enters Sleep mode, the RTC will
continue to operate, provided the 32 kHz external
crystal oscillator is active and the control bits have not
been changed. The TSIDL bit should be cleared to ‘0’
in order for RTC to continue operation in Idle mode.
Enabling an interrupt is accomplished via the
respective Timer Interrupt Enable bit, T1IE. The Timer
Interrupt Enable bit is located in the IEC0 control
register in the Interrupt Controller.
9.5.2
RTC INTERRUPTS
9.5
Real-Time Clock
When an interrupt event occurs, the respective
interrupt flag, T1IF, is asserted and an interrupt will be
generated, if enabled. The T1IF bit must be cleared in
software. The respective Timer interrupt flag, T1IF, is
located in the IFS0 status register in the Interrupt
Controller.
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time-of-day and event time stamping
capabilities. Key operational features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
Enabling an interrupt is accomplished via the
respective Timer Interrupt Enable bit, T1IE. The Timer
Interrupt Enable bit is located in the IEC0 control
register in the Interrupt Controller.
• Real-Time Clock Interrupts
These Operating modes are determined by setting the
appropriate bit(s) in the T1CON control register
FIGURE 9-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
C1
SOSCI
32.768 kHz
XTAL
dsPIC30FXXXX
SOSCO
C2
R
C1 = C2 = 18 pF; R = 100K
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 65
TABLE 9-1:
TIMER1 REGISTER MAP(1)
SFR Name Addr.
Bit 15
Bit 14 Bit 13
Bit 12
Bit 11
Bit 10 Bit 9
Bit 8
Timer 1 Register
Period Register 1
TGATE TCKPS1 TCKPS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
TMR1
PR1
0100
0102
0104
T1CON
TON
—
TSIDL
—
—
—
—
—
—
—
TSYNC
TCS
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
For 32-bit timer/counter operation, Timer2 is the lsw
and Timer3 is the msw of the 32-bit timer.
10.0 TIMER2/3 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Note:
For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer 2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer3 interrupt flag
(T3IF) and the interrupt is enabled with the
Timer3 Interrupt Enable bit (T3IE).
This section describes the 32-bit general purpose
Timer module (Timer2/3) and associated operational
modes. Figure 10-1 depicts the simplified block dia-
gram of the 32-bit Timer2/3 module. Figure 10-2 and
Figure 10-3 show Timer2/3 configured as two
independent 16-bit timers; Timer2 and Timer3,
respectively.
16-bit Mode: In the 16-bit mode, Timer2 and Timer3
can be configured as two independent 16-bit timers.
Each timer can be set up in either 16-bit Timer mode or
16-bit Synchronous Counter mode. See Section 9.0
"Timer1 Module", Timer1 Module, for details on these
two operating modes.
Note:
Timer2 is a ‘Type B’ timer and Timer3 is a
‘Type C’ timer. Please refer to the
appropriate timer type in Section 23.0
"Electrical Characteristics" of this
document.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high-frequency
external clock inputs.
The Timer2/3 module is a 32-bit timer, which can be
configured as two 16-bit timers, with selectable operat-
ing modes. These timers are utilized by other
peripheral modules such as:
32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloads into the combined 32-bit period register
PR3/PR2, then resets to ‘0’ and continues to count.
• Input Capture
• Output Compare/Simple PWM
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the lsw (TMR2 register) will cause the
msw to be read and latched into a 16-bit holding regis-
ter, termed TMR3HLD.
The following sections provide a detailed description,
including setup and control registers, along with
associated block diagrams for the operational modes of
the timers.
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to ‘0’ and continues.
• Single 32-bit Timer operation
• Single 32-bit Synchronous Counter
Further, the following operational characteristics are
supported:
• ADC Event Trigger
• Timer Gate Operation
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing, unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-bit Period Register Match
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 67
dsPIC30F3010/3011
FIGURE 10-1:
32-BIT TIMER2/3 BLOCK DIAGRAM
Data Bus<15:0>
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3
TMR2
LSB
Sync
MSB
ADC Event Trigger
Comparator x 32
Equal
PR3
PR2
0
1
T3IF
Event Flag
Q
Q
D
TGATE(T2CON<6>)
CK
TGATE
(T2CON<6>)
TCKPS<1:0>
2
TON
T2CK
1X
Prescaler
1, 8, 64, 256
Gate
Sync
01
00
TCY
Note:
Timer Configuration bit T32, T2CON(<3>) must be set to 1for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
DS70141D-page 68
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 10-2:
16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER)
PR2
Comparator x 16
TMR2
Equal
Reset
Sync
0
1
T2IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
T2CK
1X
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TCY
FIGURE 10-3:
16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER)
PR3
ADC Event Trigger
Equal
Reset
Comparator x 16
TMR3
0
1
T3IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
Sync
TCY
1X
01
00
Prescaler
1, 8, 64, 256
Note:
The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER3. In these devices the following
modes should not be used:
1. TCS = 1
2. TCS = 0and TGATE = 1(Gated Time Accumulation)
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 69
dsPIC30F3010/3011
10.1 Timer Gate Operation
10.4 Timer Operation During Sleep
Mode
The 32-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal TCY
to increment the respective timer when the gate input
signal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
10.5 Timer Interrupt
The 32-bit timer module can generate an interrupt-on-
period match, or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener-
ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.
The falling edge of the external signal terminates the
count operation, but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2 ADC Event Trigger
When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
Enabling an interrupt is accomplished via the
respective Timer Interrupt Enable bit, T3IE (IEC0<7>).
10.3 Timer Prescaler
The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler
operation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• clearing either of the TON (T2CON<15> or
T3CON<15>) bits to ‘0’
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70141D-page 70
Confidential
© 2007 Microchip Technology Inc.
TABLE 10-1: TIMER2/3 REGISTER MAP(1)
SFR Name Addr.
TMR2 0106
TMR3HLD 0108
Bit 15
Bit 14 Bit 13
Bit 12
Bit 11
Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
Timer2 Register
Timer3 Holding Register (For 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
Period Register 2
PR3
Period Register 3
T2CON
T3CON
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T32
—
—
—
TCS
TCS
—
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 72
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
The Timer4/5 module is similar in operation to the
Timer 2/3 module. However, there are some
differences, which are as follows:
11.0 TIMER4/5 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• The Timer4/5 module does not support the ADC
Event Trigger feature
• Timer4/5 can not be utilized by other peripheral
modules such as Input Capture and Output Compare
This section describes the second 32-bit general
purpose Timer module (Timer4/5) and associated oper-
ational modes. Figure 11-1 depicts the simplified block
diagram of the 32-bit Timer4/5 Module. Figure 11-2 and
Figure 11-3 show Timer4/5 configured as two indepen-
dent 16-bit timers, Timer4 and Timer5, respectively.
The operating modes of the Timer4/5 module are
determined by setting the appropriate bit(s) in the 16-bit
T4CON and T5CON SFRs.
For 32-bit timer/counter operation, Timer4 is the lsw
and Timer5 is the msw of the 32-bit timer.
Note:
For 32-bit timer operation, T5CON control
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer5 interrupt flag
(T5IF) and the interrupt is enabled with the
Timer5 Interrupt Enable bit (T5IE).
Note:
Timer4 is a ‘Type B’ timer and Timer5 is a
‘Type C’ timer. Please refer to the
appropriate timer type in Section 23.0
"Electrical Characteristics" of this
document.
FIGURE 11-1:
32-BIT TIMER4/5 BLOCK DIAGRAM
Data Bus<15:0>
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
TMR5
MSB
TMR4
LSB
Sync
Comparator x 32
Equal
PR5
PR4
0
1
T5IF
Event Flag
Q
Q
D
TGATE(T4CON<6>)
CK
TGATE
(T4CON<6>)
TCKPS<1:0>
TON
2
1X
Prescaler
1, 8, 64, 256
Gate
01
00
Sync
TCY
Note:
Timer Configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All
control bits are respective to the T4CON register.
The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices, the following modes should not be used:
1. TCS = 1
2. TCS = 0and TGATE = 1(Gated Time Accumulation)
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 73
dsPIC30F3010/3011
FIGURE 11-2:
16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER)
PR4
Comparator x 16
TMR4
Equal
Reset
Sync
0
1
T4IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
1X
Prescaler
1, 8, 64, 256
Gate
Sync
01
00
TCY
Note:
The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices, the following modes should not be used:
1. TCS = 1
2. TCS = 0and TGATE = 1(Gated Time Accumulation)
DS70141D-page 74
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 11-3:
16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER)
PR5
Comparator x 16
TMR5
Equal
Reset
ADC Event Trigger
0
1
T5IF
Event Flag
Q
D
TGATE
Q
CK
TGATE
TCKPS<1:0>
2
TON
Sync
TCY
1X
Prescaler
1, 8, 64, 256
01
00
Note:
The dsPIC30F3010/3011 devices do not have external pin inputs to TIMER4 or TIMER5. In these
devices, the following modes should not be used:
1. TCS = 1
2. TCS = 0and TGATE = 1(Gated Time Accumulation)
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 75
TABLE 11-1: TIMER4/5 REGISTER MAP(1)
SFR Name
Addr.
0114
0116
0118
011A
011C
011E
0120
Bit 15 Bit 14 Bit 13 Bit 12
Bit 11
Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
TMR4
Timer 4 Register
TMR5HLD
TMR5
Timer 5 Holding Register (For 32-bit operations only)
Timer 5 Register
PR4
Period Register 4
PR5
Period Register 5
T4CON
T5CON
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T45
—
—
—
TCS
TCS
—
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
The key operational features of the Input Capture
module are:
12.0 INPUT CAPTURE MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting
the appropriate bits in the ICxCON register
(where x = 1,2,...,N).
This section describes the Input Capture module and
associated operational modes. The features provided
by this module are useful in applications requiring
Frequency (Period) and Pulse measurement.
Figure 12-1 depicts a block diagram of the Input
Capture module. Input capture is useful for such modes
as:
Note:
The dsPIC30F3010/3011 devices have
four capture channels. The channels are
designated IC1, IC2, IC7 and IC8 to
maintain software compatibility with other
dsPIC30F devices.
• Frequency/Period/Pulse Measurements
• Additional sources of External Interrupts
FIGURE 12-1:
INPUT CAPTURE MODE BLOCK DIAGRAM
T3_CNT
16
T2_CNT
From General Purpose Timer Module
16
ICx
Pin
ICTMR
1
0
Edge
Detection
Logic
FIFO
R/W
Logic
Prescaler
1, 4, 16
Clock
Synchronizer
3
ICM<2:0>
Mode Select
ICxBUF
ICBNE, ICOV
ICI<1:0>
Interrupt
Logic
ICxCON
Data Bus
Set Flag
ICxIF
Note:
Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 77
dsPIC30F3010/3011
12.1.3
TIMER2 AND TIMER3 SELECTION
MODE
12.1 Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
Each capture channel can select between one of two
timers for the time base, Timer2 or Timer3.
• Capture every falling edge
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
• Capture every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
12.1.4
HALL SENSOR MODE
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the
following operations are performed by the input
capture logic:
12.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
• The input capture interrupt flag is set on every
edge, rising and falling.
• The interrupt on Capture Mode Setting bits,
ICI<1:0>, is ignored, since every capture
generates an interrupt.
12.1.2
CAPTURE BUFFER OPERATION
• A capture overflow condition is not generated in
this mode.
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
12.2 Input Capture Operation During
Sleep and Idle Modes
• ICBNE — Input Capture Buffer Not Empty
• ICOV — Input Capture Overflow
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
The ICBNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU Sleep or Idle
mode when a capture event occurs, if ICM<2:0> = 111
and the Interrupt Enable bit is asserted. The same
wake-up can generate an interrupt, if the conditions for
processing the interrupt have been satisfied. The wake-
up feature is useful as a method of adding extra external
pin interrupts.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured till all four events have been
read from the buffer.
12.2.1
INPUT CAPTURE IN CPU SLEEP
MODE
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
CPU Sleep mode allows input capture module opera-
tion with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111) in order for
the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
are not applicable in this mode.
DS70141D-page 78
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
12.2.2
INPUT CAPTURE IN CPU IDLE
MODE
12.3 Input Capture Interrupts
The input capture channels have the ability to generate
an interrupt, based upon the selected number of
capture events. The selection number is set by control
bits ICI<1:0> (ICxCON<6:5>).
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the interrupt
mode selected by the ICI<1:0> bits are applicable, as
well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
Capture Interrupt Enable bit is located in the
corresponding IEC control register.
If the input capture module is defined as ICM<2:0> = 111
in CPU Idle mode, the input capture pin will serve only as
an external interrupt pin.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 79
TABLE 12-1: INPUT CAPTURE REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Input 1 Capture Register
ICTMR
Input 2 Capture Register
ICTMR
Input 7 Capture Register
ICTMR
Input 8 Capture Register
ICTMR
Bit 8
Bit 7
Bit 6 Bit 5
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
ICM<2:0>
Reset State
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
IC1BUF
IC1CON
IC2BUF
IC2CON
IC7BUF
IC7CON
IC8BUF
IC8CON
0140
0142
0144
0146
0158
015A
015C
015E
—
—
—
—
—
—
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICOV ICBNE
ICOV ICBNE
ICOV ICBNE
ICOV ICBNE
—
—
ICM<2:0>
—
—
ICM<2:0>
—
—
ICM<2:0>
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
The key operational features of the Output Compare
module include:
13.0 OUTPUT COMPARE MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
This section describes the Output Compare module
and associated operational modes. The features
provided by this module are useful in applications
requiring operational modes such as:
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where x =
1,2,3,...,N). The dsPIC30F3010/3011 devices have 4/2
compare channels, respectively.
• Generation of Variable Width Output Pulses
• Power Factor Correction
OCxRS and OCxR in the figure represent the dual
compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
Figure 13-1 depicts a block diagram of the Output
Compare module.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
S
R
Q
OCx
Output Enable
3
OCM<2:0>
Mode Select
OCFA
Comparator
(for x = 1, 2, 3 or 4)
OCTSEL
1
1
0
0
From GP Timer Module
T3P3_MATCH
TMR3<15:0> T2P2_MATCH
TMR2<15:0
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 81
dsPIC30F3010/3011
13.3.2
CONTINUOUS PULSE MODE
13.1 Timer2 and Timer3 Selection Mode
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
Each output compare channel can select between one
of two 16-bit timers; Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the Output Compare module.
• Determine instruction cycle time TCY.
• Calculate desired pulse value based on TCY.
• Calculate timer to start pulse width from timer start
value of 0x0000.
13.2 Simple Output Compare Match
Mode
• Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
compare registers, respectively.
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple output compare
match modes:
• Set Timer Period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 101.
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
• Enable timer, TON (TxCON<15>) = 1.
13.4 Simple PWM Mode
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these compare match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config-
ured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the main latch
(read only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
13.3 Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config-
ured for one of two dual output compare modes, which
are:
1. Set the PWM period by writing to the appropriate
period register.
2. Set the PWM duty cycle by writing to the OCxRS
register.
• Single Output Pulse mode
• Continuous Output Pulse mode
3. Configure the output compare module for PWM
operation.
13.3.1
SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
Timer, TON (TxCON<15>) = 1.
13.4.1
INPUT PIN FAULT PROTECTION
FOR PWM
• Determine instruction cycle time TCY.
• Calculate desired pulse width value based on TCY.
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config-
ured for the PWM mode of operation, with the addi-
tional feature of input fault protection. While in this
mode, if a logic ‘0’ is detected on the OCFA/B pin, the
respective PWM output pin is placed in the high-imped-
ance input state. The OCFLT bit (OCxCON<4>) indi-
cates whether a Fault condition has occurred. This
state will be maintained until both of the following
events have occurred:
• Calculate time to start pulse from timer start value
of 0x0000.
• Write pulse width start and stop times into OCxR
and OCxRS compare registers (x denotes
channel 1, 2, ...,N).
• Set Timer Period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 100.
• Enable timer, TON (TxCON<15>) = 1.
• The external Faultcondition has been removed.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
• The PWM mode has been re-enabled by writing
to the appropriate control bits.
DS70141D-page 82
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
13.4.2
PWM PERIOD
The PWM period is specified by writing to the PRx
register. The PWM period can be calculated using
Equation 13-1.
• TMRx is cleared.
• The OCx pin is set.
EQUATION 13-1: PWM PERIOD
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
PWM period = [(PRx) + 1] • 4 • TOSC •
(TMRx prescale value)
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
• The PWM duty cycle is latched from OCxRS into
OCxR.
PWM frequency is defined as 1 / [PWM period].
• The corresponding timer interrupt flag is set.
See Figure 13-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
FIGURE 13-1:
PWM OUTPUT TIMING
Period
Duty Cycle
TMR3 = PR3
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
OCxR = OCxRS
TMR3 = Duty Cycle (OCxR)
TMR3 = Duty Cycle (OCxR)
13.5 Output Compare Operation During
CPU Sleep Mode
13.7 Output Compare Interrupts
The output compare channels have the ability to
generate an interrupt on a compare match, for
whichever match mode has been selected.
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
status register, and must be cleared in software. The
interrupt is enabled via the respective compare
interrupt enable (OCxIE) bit, located in the
corresponding IEC control register.
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 status register, and must be cleared
in software. The interrupt is enabled via the respective
Timer Interrupt Enable bit (T2IE or T3IE), located in the
IEC0 control register. The output compare interrupt flag
is never set during the PWM mode of operation.
13.6 Output Compare Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic 0and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic 0.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 83
TABLE 13-1: OUTPUT COMPARE REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
Output Compare 1 Secondary Register
Output Compare 1 Main Register
OC1CON
OC2RS
OC2R
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Output Compare 2 Secondary Register
Output Compare 2 Main Register
OC2CON
OC3RS*
OC3R*
—
—
—
—
Output Compare 3 Secondary Register
Output Compare 3 Main Register
OC3CON*
OC4RS*
OC4R*
—
—
—
—
Output Compare 4 Secondary Register
Output Compare 4 Main Register
OC4CON*
—
—
—
—
Legend: u= uninitialized bit; — = unimplemented bit, * = not available on dsPIC30F3010
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
The operational features of the QEI include:
14.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
• Three input channels for two phase signals and
index pulse
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
This section describes the Quadrature Encoder
Interface (QEI) module and associated operational
modes. The QEI module provides the interface to
incremental encoders for obtaining mechanical position
data.
These operating modes are determined by setting the
appropriate bits QEIM<2:0> (QEICON<10:8>).
Figure 14-1 depicts the Quadrature Encoder Interface
block diagram.
FIGURE 14-1:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
2
Sleep Input
TQCS
TCY
0
1
Synchronize
Det
Prescaler
1, 8, 64, 256
1
0
QEIM<2:0>
QEIIF
Event
Flag
D
Q
Q
TQGATE
CK
16-bit Up/Down Counter
(POSCNT)
2
Programmable
Digital Filter
QEA
Reset
Quadrature
Encoder
Interface Logic
UPDN_SRC
Comparator/
Zero Detect
Equal
QEICON<11>
3
0
QEIM<2:0>
Mode Select
1
Max Count Register
(MAXCNT)
Programmable
Digital Filter
QEB
Up/Down(1)
Programmable
Digital Filter
INDX
3
Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 85
dsPIC30F3010/3011
14.2.2
POSITION COUNTER RESET
14.1 Quadrature Encoder Interface
Logic
The Position Counter Reset Enable bit, POSRES
(QEI<2>) controls whether the position counter is reset
when the index pulse is detected. This bit is only
applicable when QEIM<2:0> = ‘100’ or ‘110’.
A typical incremental (a.k.a. optical) encoder has three
outputs: Phase A, Phase B and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
If the POSRES bit is set to ‘1’, then the position counter
is reset when the index pulse is detected. If the
POSRES bit is set to ‘0’, then the position counter is not
reset when the index pulse is detected. The position
counter will continue counting up or down, and will be
reset on the rollover or underflow condition.
The two channels, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction (of
the motor) is deemed negative or reverse.
When selecting the INDX signal to reset the position
counter (POSCNT), the user has to specify the states
on QEA and QEB input pins. These states have to be
matched in order for a reset to occur. These states are
selected by the IMV<1:0> bit in the DFLTCON <10:9>
register.
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
14.2 16-bit Up/Down Position Counter
Mode
The IMV<1:0> (Index Match Value) bit allows the user
to specify the state of the QEA and QEB input pins
during an index pulse when the POSCNT register is to
be reset.
The 16-bit Up/Down Counter counts up or down on
every count pulse, which is generated by the difference
of the Phase A and Phase B input signals. The counter
acts as an integrator, whose count value is proportional
to position. The direction of the count is determined by
the UPDN signal, which is generated by the
Quadrature Encoder Interface Logic.
In 4X Quadrature Count Mode:
IMV1 = Required State of Phase B input signal for
match on index pulse
IMV0 = Required State of Phase A input signal for
match on index pulse
In 2X Quadrature Count Mode:
IMV1 = Selects Phase input signal for index state
match (0= Phase A, 1= Phase B)
14.2.1
POSITION COUNTER ERROR
CHECKING
Position count error checking in the QEI is provided for
and indicated by the CNTERR bit (QEICON<15>). The
error checking only applies when the position counter
is configured for Reset on the Index Pulse modes
(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the
contents of the POSCNT register is compared with the
values (0xFFFF or MAXCNT + 1, depending on direc-
tion). If these values are detected, an error condition is
generated by setting the CNTERR bit and a QEI count
error interrupt is generated. The QEI count error
interrupt can be disabled by setting the CEID bit
(DFLTCON<8>). The position counter continues to
count encoder edges after an error has been detected.
The POSCNT register continues to count up/down until
a natural rollover/underflow. No interrupt is generated
for the natural rollover/underflow event. The CNTERR
bit is a Read/Write bit and reset in software by the user.
IMV0 = Required State of the selected phase input
signal for match on index pulse
The interrupt is still generated on the detection of the
index pulse and not on the position counter overflow/
underflow.
14.2.3
COUNT DIRECTION STATUS
As mentioned in the previous section, the QEI logic
generates an UPDN signal, based upon the relation-
ship between Phase A and Phase B. In addition to the
output pin, the state of this internal UPDN signal is
supplied to a SFR bit UPDN (QEICON<11>) as a read-
only bit.
Note:
QEI pins are multiplexed with analog inputs.
User must insure that all QEI associated
pins are set as digital inputs in the ADPCFG
register.
DS70141D-page 86
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
14.3 Position Measurement Mode
14.5 Alternate 16-bit Timer/Counter
There are two measurement modes which are sup-
ported and are termed x2 and x4. These modes are
selected by the QEIM<2:0> mode select bits located in
SFR QEICON<10:8>.
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the
QEICON SFR register. This timer functions identically
to Timer1. The QEA pin is used as the timer clock input.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be incre-
mented or decremented. The Phase B signal is still
utilized for the determination of the counter direction,
just as in the x4 Measurement mode.
When configured as a timer, the POSCNT register
serves as the timer count register and the MAXCNT
register serves as the period register. When a timer/
period register match occur, the QEI interrupt flag will
be asserted.
The only exception between the general purpose
timers and this timer is the added feature of external
Up/Down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
1. Position counter reset by detection of index
pulse, QEIM<2:0> = 100.
2. Position counter reset by match with MAXCNT,
Note:
Changing the operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the timer/position count register contents.
QEIM<2:0> = 101.
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input
signals. Every edge of both signals causes the position
counter to increment or decrement.
The UPDN Control/Status bit (QEICON<11>) can be
used to select the count direction state of the timer
register. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
Within the x4 Measurement mode, there are two
variations of how the position counter is reset:
In addition, control bit UPDN_SRC (QEICON<0>)
determines whether the timer count direction state is
based on the logic state, written into the UPDN Control/
Status bit (QEICON<11>), or the QEB pin state. When
UPDN_SRC = 1, the timer count direction is controlled
from the QEB pin. Likewise, when UPDN_SRC = 0, the
timer count direction is controlled by the UPDN bit.
1. Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
2. Position counter reset by match with MAXCNT,
QEIM<2:0> = 111.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
Note:
This Timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.
14.4 Programmable Digital Noise
Filters
14.6 QEI Module Operation During CPU
Sleep Mode
The digital noise filter section is responsible for reject-
ing noise on the incoming capture or quadrature
signals. Schmitt Trigger inputs and a three-clock cycle
delay filter combine to reject low level noise and large,
short duration noise spikes that typically occur in noise
prone applications, such as a motor system.
14.6.1
QEI OPERATION DURING CPU
SLEEP MODE
The QEI module will be halted during the CPU Sleep
mode.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
14.6.2
TIMER OPERATION DURING CPU
SLEEP MODE
For the QEA, QEB and INDX pins, the clock divide
frequency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle TCY.
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 87
dsPIC30F3010/3011
14.7 QEI Module Operation During CPU
Idle Mode
14.8 Quadrature Encoder Interface
Interrupts
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
rollover/underflow
14.7.1
QEI OPERATION DURING CPU IDLE
MODE
• Detection of qualified index pulse, or if CNTERR
bit is set
When the CPU is placed in the Idle mode, the QEI
module will operate if the QEISIDL bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’
upon executing POR and BOR. For halting the QEI
module during the CPU Idle mode, QEISIDL should
be set to ‘1’.
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 status register.
14.7.2
TIMER OPERATION DURING CPU
IDLE MODE
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 control register.
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if the QEISIDL bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
DS70141D-page 88
Confidential
© 2007 Microchip Technology Inc.
TABLE 14-1: QEI REGISTER MAP(1)
SFR
Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
QEICON
0122 CNTERR
—
—
QEISIDL INDX
UPDN
—
QEIM2 QEIM1 QEIM0 SWPAB
—
TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC
DFLTCON 0124
POSCNT 0126
MAXCNT 0128
ADPCFG 02A8
—
—
—
IMV1
—
IMV0
CEID QEOUT QECK2 QECK1
Position Counter<15:0>
QECK0
—
—
—
—
Maximun Count<15:0>
—
—
—
—
—
—
PCFG8 PCFG7 PCFG6 PCFG5
PCFG4
PCFG3
PCFG2 PCFG1
PCFG0
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 90
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
• ‘On-the-Fly’ PWM frequency changes
• Edge and Center-Aligned Output modes
• Single Pulse Generation mode
15.0 MOTOR CONTROL PWM
MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Interrupt support for asymmetrical updates in
Center-Aligned mode
• Output override control for Electrically
Commutative Motor (ECM) operation
• ‘Special Event’ comparator for scheduling other
peripheral events
This module simplifies the task of generating multiple,
synchronized Pulse Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
• Fault pins to optionally drive each of the PWM
output pins to a defined state
This module contains
3 duty cycle generators,
• Three-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
numbered 1 through 3. The module has 6 PWM output
pins, numbered PWM1H/PWM1L through PWM3H/
PWM3L. The six I/O pins are grouped into high/low
numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
• Uninterruptible Power Supply (UPS)
The PWM module has the following features:
• 6 PWM I/O pins with 3 duty cycle generators
• Up to 16-bit resolution
The PWM module allows several modes of operation
which are beneficial for specific power control
applications.
© 2007 Microchip Technology Inc.
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dsPIC30F3010/3011
FIGURE 15-1:
PWM MODULE BLOCK DIAGRAM
PWMCON1
PWMCON2
DTCON1
PWM Enable and Mode SFRs
Dead-Time Control SFRs
FLTACON
OVDCON
Fault Pin Control SFRs
PWM Manual
Control SFR
PWM Generator #3
PDC3 Buffer
PDC3
PWM3H
PWM3L
Comparator
Channel 3 Dead-Time
Generator and
Override Logic
PWM Generator
#2
PWM2H
PWM2L
PTMR
Comparator
PTPER
Channel 2 Dead-Time
Generator and
Output
Driver
Block
Override Logic
PWM Generator
#1
PWM1H
PWM1L
Channel 1 Dead-Time
Generator and
Override Logic
FLTA
PTPER Buffer
PTCON
Special Event
Postscaler
Comparator
SEVTCMP
Special Event Trigger
SEVTDIR
PTDIR
PWM time base
Note:
Details of PWM Generator #1 and #2 not shown for clarity.
DS70141D-page 92
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
15.1.1
FREE-RUNNING MODE
15.1 PWM Time Base
In the Free-Running mode, the PWM time base counts
upwards until the value in the Time Base Period
register (PTPER) is matched. The PTMR register is
reset on the following input clock edge and the time
base will continue to count upwards as long as the
PTEN bit remains set.
The PWM time base is provided by a 15-bit timer with
a prescaler and postscaler. The time base is accessible
via the PTMR SFR. PTDIR (PTMR<15>) is a read-only
Status bit that indicates the present count direction of
the PWM time base. If PTDIR is cleared, PTMR is
counting upwards. If PTDIR is set, PTMR is counting
downwards. The PWM time base is configured via the
PTCON SFR. The time base is enabled/disabled by
setting/clearing the PTEN bit in the PTCON SFR.
PTMR is not cleared when the PTEN bit is cleared in
software.
When the PWM time base is in the Free-Running mode
(PTMOD<1:0> = 00), an interrupt event is generated
each time a match with the PTPER register occurs and
the PTMR register is reset to zero. The postscaler
selection bits may be used in this mode of the timer to
reduce the frequency of the interrupt events.
The PTPER SFR sets the counting period for PTMR.
The user must write a 15-bit value to PTPER<14:0>.
When the value in PTMR<14:0> matches the value in
PTPER<14:0>, the time base will either reset to 0, or
reverse the count direction on the next occurring clock
cycle. The action taken depends on the operating
mode of the time base.
15.1.2
SINGLE-SHOT MODE
In the Single-Shot Counting mode, the PWM time base
begins counting upwards when the PTEN bit is set.
When the value in the PTMR register matches the
PTPER register, the PTMR register will be reset on the
following input clock edge and the PTEN bit will be
cleared by the hardware to halt the time base.
Note:
If the period register is set to 0x0000, the
timer will stop counting, and the interrupt
and the special event trigger will not be
generated, even if the special event value
is also 0x0000. The module will not update
the period register, if it is already at
0x0000; therefore, the user must disable
the module in order to update the period
register.
When the PWM time base is in the Single-Shot mode
(PTMOD<1:0> = 01), an interrupt event is generated
when a match with the PTPER register occurs, the
PTMR register is reset to zero on the following input
clock edge, and the PTEN bit is cleared. The postscaler
selection bits have no effect in this mode of the timer.
15.1.3
CONTINUOUS UP/DOWN
COUNTING MODES
The PWM time base can be configured for four different
modes of operation:
In the Continuous Up/Down Counting modes, the PWM
time base counts upwards until the value in the PTPER
register is matched. The timer will begin counting
downwards on the following input clock edge. The
PTDIR bit in the PTCON SFR is read-only and indi-
cates the counting direction. The PTDIR bit is set when
the timer counts downwards.
• Free-Running mode
• Single-Shot mode
• Continuous Up/Down Count mode
• Continuous Up/Down Count mode with interrupts
for double updates
These four modes are selected by the PTMOD<1:0>
bits in the PTCON SFR. The Up/Down Counting modes
support center-aligned PWM generation. The Single-
Shot mode allows the PWM module to support pulse
control of certain Electronically Commutative Motors
(ECMs).
In the Up/Down Counting mode (PTMOD<1:0> = 10),
an interrupt event is generated each time the value of
the PTMR register becomes zero and the PWM time
base begins to count upwards. The postscaler selec-
tion bits may be used in this mode of the timer to reduce
the frequency of the interrupt events.
The interrupt signals generated by the PWM time base
depend on the mode selection bits (PTMOD<1:0>) and
the postscaler bits (PTOPS<3:0>) in the PTCON SFR.
© 2007 Microchip Technology Inc.
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dsPIC30F3010/3011
15.1.4
DOUBLE-UPDATE MODE
15.2 PWM Period
In the Double-Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR regis-
ter is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
PTPER is a 15-bit register and is used to set the count-
ing period for the PWM time base. PTPER is a double-
buffered register. The PTPER buffer contents are
loaded into the PTPER register at the following
instances:
The Double-Update mode provides two additional
functions to the user. First, the control loop bandwidth
is doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical
center-aligned PWM waveforms can be generated,
which are useful for minimizing output waveform
distortion in certain motor control applications.
• Free-Running and Single-Shot modes: When the
PTMR register is reset to zero after a match with
the PTPER register.
• Up/Down Counting modes: When the PTMR
register is zero.
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
Note:
Programming a value of 0x0001 in the
period register could generate a continu-
ous interrupt pulse, and hence, must be
avoided.
The PWM period can be determined using
Equation 15-1:
EQUATION 15-1: PWM PERIOD (FREE-
RUNNING MODE)
15.1.5
PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4), has prescaler
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
TCY • (PTPER + 1)
TPWM =
(PTMR Prescale Value)
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period is given by
Equation 15-2.
The PTMR register is not cleared when PTCON is
written.
EQUATION 15-2: PWM PERIOD (UP/DOWN
COUNTING MODE)
15.1.6
PWM TIME BASE POSTSCALER
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
2 • TCY • (PTPER + 0.75)
TPWM =
(PTMR Prescale Value)
The postscaler counter is cleared when any of the
following occurs:
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-3:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
EQUATION 15-3: PWM RESOLUTION
The PTMR register is not cleared when PTCON is written.
log (2 • TPWM / TCY)
Resolution =
log (2)
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FIGURE 15-3:
CENTER-ALIGNED PWM
15.3 Edge-Aligned PWM
Period/2
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate duty cycle
register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the duty cycle register
matches PTMR.
PTPER
PTMR
Value
Duty
Cycle
0
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is greater
than the value held in the PTPER register.
Period
15.5 PWM Duty Cycle Comparison
Units
FIGURE 15-2:
EDGE-ALIGNED PWM
New Duty Cycle Latched
There are three 16-bit special function registers (PDC1,
PDC2 and PDC3) used to specify duty cycle values for
the PWM module.
PTPER
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The duty cycle registers are 16 bits wide. The LS
bit of a duty cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
PTMR
Value
0
Duty Cycle
15.5.1
DUTY CYCLE REGISTER BUFFERS
The three PWM duty cycle registers are double buff-
ered to allow glitchless updates of the PWM outputs.
For each duty cycle, there is a duty cycle register that
is accessible by the user and a second duty cycle
register that holds the actual compare value used in the
present PWM period.
Period
15.4 Center-Aligned PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in an
Up/Down Counting mode (see Figure 15-3).
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER
register occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is equal to
the value held in the PTPER register.
© 2007 Microchip Technology Inc.
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dsPIC30F3010/3011
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
15.7.1
DEAD-TIME GENERATORS
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-4, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
15.7.2
DEAD-TIME RANGES
The amount of dead time provided by the dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value.
15.6 Complementary PWM Operation
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7).
Four input clock prescaler selections have been pro-
vided to allow a suitable range of dead time, based on
the device operating frequency. The dead-time clock
prescaler values are selected using the DTAPS<1:0>
control bits in the DTCON1 SFR. One of four clock
prescaler options (TCY, 2TCY, 4TCY or 8TCY) may be
selected.
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC1 register controls PWM1H/PWM1L outputs
• PDC2 register controls PWM2H/PWM2L outputs
• PDC3 register controls PWM3H/PWM3L outputs
After the prescaler value is selected, the dead time is
adjusted by loading 6-bit unsigned values into the
DTCON1 SFR.
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device Reset.
The dead-time unit prescaler is cleared on the following
events:
• On a load of the down timer due to a duty cycle
comparison edge event.
• On a write to the DTCON1 register.
• On any device Reset.
15.7 Dead-Time Generators
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the Comple-
mentary Output mode. The PWM outputs use Push-
Pull drive circuits. Due to the inability of the power out-
put devices to switch instantaneously, some amount of
time must be provided between the turn-off event of
one PWM output in a complementary pair and the turn-
on event of the other transistor.
Note:
The user should not modify the DTCON1
value while the PWM module is operating
(PTEN = 1). Unexpected results may
occur.
The PWM module allows two different dead times to be
programmed. These two dead times may be used in
one of two methods described below to increase user
flexibility:
• The PWM output signals can be optimized for
different turn-off times in the high side and low
side transistors in a complementary pair of
transistors. The first dead time is inserted
between the turn-off event of the lower transistor
of the complementary pair and the turn-on event
of the upper transistor. The second dead time is
inserted between the turn-off event of the upper
transistor and the turn-on event of the lower
transistor.
• The two dead times can be assigned to individual
PWM I/O pin pairs. This Operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
DS70141D-page 96
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 15-4:
DEAD-TIME TIMING DIAGRAM
Duty Cycle Generator
PWMxH
PWMxL
Dead Time
Dead Time
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15.8 Independent PWM Output
15.10 PWM Output Override
An independent PWM Output mode is required for
driving certain types of loads. A particular PWM output
pair is in the Independent Output mode when the
corresponding PMOD bit in the PWMCON1 register is
set. No dead-time control is implemented between
adjacent PWM I/O pins when the module is operating
in the Independent mode and both I/O pins are allowed
to be active simultaneously.
The PWM output override bits allow the user to
manually drive the PWM I/O pins to specified logic
states, independent of the duty cycle comparison units.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains six
bits, POVDxH<3:1> and POVDxL<3:1>, that determine
which PWM I/O pins will be overridden. The lower half
of the OVDCON register contains six bits,
POUTxH<3:1> and POUTxL<3:1>, that determine the
state of the PWM I/O pins when a particular output is
overridden via the POVD bits.
In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output
pair. By using the associated duty cycle register and
the appropriate bits in the OVDCON register, the user
may select the following signal output options for each
PWM I/O pin operating in the Independent mode:
15.10.1 COMPLEMENTARY OUTPUT MODE
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the comple-
ment of the corresponding PWMxH pin in the pair.
Dead-time insertion is still performed when PWM
channels are overridden manually.
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
15.9 Single Pulse PWM Operation
15.10.2 OVERRIDE SYNCHRONIZATION
The PWM module produces single pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only edge-
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR
register is cleared, all active PWM I/O pins are driven
to the inactive state, the PTEN bit is cleared and an
interrupt is generated.
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge-Aligned mode, when PTMR is zero.
• Center-Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
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15.12.2 Fault STATES
15.11 PWM Output and Polarity Control
The FLTACON special function register has 6 bits that
determine the state of each PWM I/O pin when it is
overridden by a Fault input. When these bits are
cleared, the PWM I/O pin is driven to the inactive state.
If the bit is set, the PWM I/O pin will be driven to the
active state. The active and inactive states are refer-
enced to the polarity defined for each PWM I/O pin
(HPOL and LPOL polarity control bits).
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control:
• HPOL Configuration bit
• LPOL Configuration bit
• PWMPIN Configuration bit
These three bits in the FPORBOR configuration regis-
ter (see Section 21) work in conjunction with the PWM
Enable bits (PENxH and PENxL) located in the
PWMCON1 SFR. The configuration bits and PWM
Enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs. The PWMPIN con-
figuration fuse allows the PWM module outputs to be
optionally enabled on a device Reset. If PWMPIN = 0,
the PWM outputs will be driven to their inactive states
at Reset. If PWMPIN = 1 (default), the PWM outputs
will be tri-stated. The HPOL bit specifies the polarity for
the PWMxH outputs, whereas the LPOL bit specifies
the polarity for the PWMxL outputs.
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a Fault condition. The
PWMxH pin always has priority in the Complementary
mode, so that both I/O pins cannot be driven active
simultaneously.
15.12.3 Fault INPUT MODES
The Fault input pin has two modes of operation:
• Latched Mode: When the Fault pin is driven low,
the PWM outputs will go to the states defined in
the FLTACON register. The PWM outputs will
remain in this state until the Fault pin is driven
high and the corresponding interrupt flag has
been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the Fault condition
ends, the PWM module will wait until the Fault pin
is no longer asserted to restore the outputs.
15.11.1 OUTPUT PIN CONTROL
The PEN<3:1>H and PEN<3:1>L control bits in the
PWMCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a
particular PWM output pin is not enabled, it is treated
as a general purpose I/O pin.
15.12 PWM Fault Pin
• Cycle-by-Cycle Mode: When the Fault input pin
is driven low, the PWM outputs remain in the
defined Fault states for as long as the Fault pin is
held low. After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
There is one Fault pin (FLTA) associated with the PWM
module. When asserted, these pins can optionally drive
each of the PWM I/O pins to a defined state.
15.12.1 Fault PIN ENABLE BITS
The FLTACON SFR has 3 control bits that determine
whether a particular pair of PWM I/O pins is to be
controlled by the Fault input pin. To enable a
specific PWM I/O pin pair for Fault overrides, the
corresponding bit should be set in the FLTACON
register.
The Operating mode for the Fault input pin is selected
using the FLTAM control bit in the FLTACON special
function register.
The Fault pin can be controlled manually in software.
If all enable bits are cleared in the FLTACON register,
then the corresponding Fault input pin has no effect on
the PWM module and the pin may be used as a general
purpose interrupt or I/O pin.
Note:
The Fault pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON register are cleared, then
the Fault pin could be used as a general
purpose interrupt pin. The Fault pin has an
interrupt vector, Interrupt Flag bit and
Interrupt Priority bits associated with it.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 99
dsPIC30F3010/3011
15.14.1 SPECIAL EVENT TRIGGER
POSTSCALER
15.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to three duty cycle registers and the Time Base
Period register, PTPER, at a given time. In some appli-
cations, it is important that all buffer registers be written
before the new duty cycle and period values are loaded
for use by the module.
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events:
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
Time Base Period buffer, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
• Any write to the SEVTCMP register
• Any device Reset
15.15 PWM Operation During CPU Sleep
Mode
15.14 PWM Special Event Trigger
The Fault A input pin has the ability to wake the CPU
from Sleep mode. The PWM module generates an
interrupt if the Fault pin is driven low while in Sleep.
The PWM module has a special event trigger that
allows A/D conversions to be synchronized to the PWM
time base. The A/D sampling and conversion time may
be programmed to occur at any point within the PWM
period. The special event trigger allows the user to min-
imize the delay between the time when A/D conversion
results are acquired and the time when the duty cycle
value is updated.
15.16 PWM Operation During CPU Idle
Mode
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
The PWM special event trigger has a SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Counting
mode, an additional control bit is required to specify the
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the
special event trigger will occur on the upward counting
cycle of the PWM time base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time base. The SEVTDIR
control bit has no effect unless the PWM time base is
configured for an Up/Down Counting mode.
DS70141D-page 100
Confidential
© 2007 Microchip Technology Inc.
TABLE 15-1: PWM REGISTER MAP(1)
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
SFR Name
PTCON
PTMR
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0000 0000 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
01C0
01C2
01C4
PTEN
PTDIR
—
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
PWM Timer Count Value
PTPER
PWM Time Base Period Register
SEVTCMP 01C6 SEVTDIR
PWM Special Event Compare Register
PWMCON1 01C8
PWMCON2 01CA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTMOD3 PTMOD2 PTMOD1
SEVOPS<3:0>
—
—
PEN3H PEN2H
PEN1H
—
—
—
PEN3L
—
PEN2L
PEN1L
UDIS
—
—
OSYNC
DTCON1
FLTACON
OVDCON
PDC1
01CC
01D0
01D4
01D6
01D8
01DA
—
—
—
DTAPS<1:0>
Dead-Time A Value
FAEN3
FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM
POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
—
—
—
—
—
FAEN2
FAEN1
—
POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
PWM Duty Cycle #1 Register
PWM Duty Cycle #2 Register
PWM Duty Cycle #3 Register
PDC2
PDC3
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 102
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPI1BUF. The interrupt is generated
at the middle of the transfer of the last bit.
16.0 SPI MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the
interrupt is generated when the last bit is latched. If
SSx control is enabled, then transmission and
reception are enabled only when SSx = low. The
SDOx output will be disabled in SSx mode with SSx
high.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface. It is useful for
communicating with other peripheral devices such as
EEPROMs, shift registers, display drivers and A/D
converters or other microcontrollers. It is compatible
with SPI and SIOP interfaces available on some other
microcontrollers.
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
16.1 Operating Function Description
The SPI module consists of a 16-bit Shift register,
SPI1SR, used for shifting data in and out, and a Buffer
register, SPI1BUF. A Control register, SPI1CON,
configures the module. Additionally, a Status register,
SPI1STAT, indicates various status conditions.
16.1.1
WORD AND BYTE
COMMUNICATION
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation, except
that the number of bits transmitted is 16 instead of 8.
The serial interface consists of 4 pins: SDI1 (serial
data input), SDO1 (serial data output), SCK1 (shift
clock input or output) and SS1 (active low slave
select).
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
In Master mode operation, SCK is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPI1SR to the SDO1 pin and
simultaneously shifts in data from the SDI1 pin. An
interrupt is generated when the transfer is complete
and the corresponding Interrupt Flag bit (SPI1IF) is
set. This interrupt can be disabled through an Interrupt
Enable bit (SPI1IE).
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit 15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.
16.1.2
SDO1 DISABLE
The receive operation is double-buffered. When a
complete byte is received, it is transferred from
SPI1SR to SPI1BUF.
A control bit, DISSDO, is provided to the SPI1CON
register to allow the SDO1 output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDO can also be used for general
purpose I/O.
If the receive buffer is full when new data is being
transferred from SPI1SR to SPI1BUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPI1SR to SPI1BUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is 1, effectively disabling the module until
SPI1BUF is read by user software.
16.2 Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SS1 pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SS1
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active high pulse for a
single SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
Transmit writes are also double buffered. The user
writes to SPI1BUF. When the master or slave transfer
is completed, the contents of the Shift register
(SPI1SR) are moved to the receive buffer. If any trans-
mit data has been written to the Buffer register, the
contents of the transmit buffer are moved to SPI1SR.
The received data is thus placed in SPI1BUF and the
transmit data in SPI1SR is ready for the next transfer.
Note:
Both the transmit buffer (SPI1TXB) and
the receive buffer (SPI1RXB) are mapped
to the same register address, SPI1BUF.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 103
dsPIC30F3010/3011
FIGURE 16-1:
SPI BLOCK DIAGRAM
Internal
Data Bus
Read
Write
SPI1BUF
Transmit
SPI1BUF
Receive
SPI1SR
bit 0
SDI1
SDO1
Shift
clock
SS & FSYNC
Control
Clock
Control
Edge
Select
SS1
Secondary
Prescaler
1:1 – 1:8
Primary
Prescaler
1, 4, 16, 64
FCY
SCK1
Enable Master Clock
Note: In dsPIC30F3010/3011, the SS1 pin is not available.
FIGURE 16-2:
SPI MASTER/SLAVE CONNECTION
SPI Master
SPI Slave
SDOx
SDIy
Serial Input Buffer
(SPIxBUF)
Serial Input Buffer
(SPIyBUF)
SDIx
SDOy
SCKy
Shift Register
(SPIxSR)
Shift Register
(SPIySR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
PROCESSOR 1
PROCESSOR 2
Note: x = 1 or 2, y = 1 or 2.
DS70141D-page 104
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
16.3 Slave Select Synchronization
16.4 SPI Operation During CPU Sleep
Mode
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDO1 pin is driven. When the SS1 pin goes high, the
SDO1 pin is no longer driven. Also, the SPI module is
re-synchronized and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb,
even if SS1 has been de-asserted in the middle of a
transmit/receive.
During Sleep mode, the SPI module is shutdown. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5 SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 105
TABLE 16-1: SPI1 REGISTER MAP(1)
SFR
Name
Addr. Bit 15 Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SPI1STAT 0220 SPIEN
—
SPISIDL
—
—
—
—
—
—
—
SPIROV
CKP
—
—
—
—
SPITBF SPIRBF
SPI1CON
SPI1BUF
0222
0224
—
FRMEN SPIFSD
DISSDO MODE16 SMP
CKE
SSEN
MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0
Transmit and Receive Buffer
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
2
17.1.1
VARIOUS I2C MODES
17.0 I C™ MODULE
The following types of I2C operation are supported:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• I2C Slave operation with 7-bit address
• I2C Slave operation with 10-bit address
• I2C Master operation with 7 or 10-bit address
See the I2C programmer’s model in Figure 17-1.
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
17.1.2
PIN CONFIGURATION IN I2C MODE
I2C has a 2-pin interface; pin SCL is clock and pin SDA
is data.
This module offers the following key features:
• I2C interface supporting both master and slave
operation.
• I2C Slave mode supports 7 and 10-bit address.
• I2C Master mode supports 7 and 10-bit address.
• I2C port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
17.1.3
I2C REGISTERS
I2CCON and I2CSTAT are Control and Status
registers, respectively. The I2CCON register is read-
able and writable. The lower 6 bits of I2CSTAT are read
only. The remaining bits of the I2CSTAT are read/write.
I2CRSR is the Shift register used for shifting data,
whereas I2CRCV is the Buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 17-1.
I2CTRN is the Transmit register to which bytes are
written during a transmit operation, as shown in
Figure 17-2.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator (BRG)
reload value.
17.1 Operating Function Description
The hardware fully implements all the master and
slave functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
In receive operations, I2CRSR and I2CRCV together
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
form
a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double buffered.
Note:
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
FIGURE 17-1:
PROGRAMMER’S MODEL
I2CRCV (8 bits)
bit 0
bit 7
I2CTRN (8 bits)
bit 0
bit 7
bit 8
I2CBRG (9 bits)
bit 0
I2CCON (16 bits)
bit 0
bit 15
bit 15
I2CSTAT (16 bits)
bit 0
I2CADD (10 bits)
bit 0
bit 9
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 107
dsPIC30F3010/3011
FIGURE 17-2:
I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CRCV
Read
Shift
Clock
SCL
SDA
I2CRSR
LSB
Addr_Match
Match Detect
I2CADD
Write
Read
Start and
Stop bit Detect
Write
Read
Start, Restart,
Stop bit Generate
Collision
Detect
Write
Read
Acknowledge
Generation
Clock
Stretching
Write
Read
I2CTRN
LSB
Shift
Clock
Reload
Control
Write
Read
I2CBRG
BRG Down
Counter
FCY
DS70141D-page 108
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
2
17.3.2
SLAVE RECEPTION
17.2 I C Module Addresses
If the R_W bit received is a ‘0’ during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 LSbs of the
I2CADD register.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value ‘11110 A9 A8’ (where
A9and A8are two Most Significant bits of I2CADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CADD, as specified
in the 10-bit addressing protocol.
Note:
The I2CRCV will be loaded if the I2COV
bit = 1and the RBF flag = 0. In this case,
a read of the I2CRCV was performed, but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The acknowledgement is not
sent (ACK = 1) and the I2CRCV is
updated.
The 7-bit I2C Slave Addresses supported by the
dsPIC30F are shown in Table 17-1.
TABLE 17-1: 7-BIT I2C™ SLAVE
ADDRESSES
0x00
General call address or start byte
Reserved
2
17.4 I C 10-bit Slave Mode Operation
0x01-0x03
0x04-0x07
0x08-0x77
0x78-0x7b
0x7c-0x7f
Hs-mode Master codes
Valid 7-bit addresses
Valid 10-bit addresses (lower 7 bits)
Reserved
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation, with two address bytes
following a Start bit.
2
17.3 I C 7-bit Slave Mode Operation
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a
7-bit address. The address detection protocol for the
first byte of a message address is identical for 7-bit
and 10-bit messages, but the bits being compared are
different.
Once enabled (I2CEN = 1), the slave module will wait
for a start bit to occur (i.e., the I2C module is ‘Idle’).
Following the detection of a Start bit, 8 bits are shifted
into I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the
rising edge of SCL.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
If an address match occurs, an acknowledgement will
be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK) bit. The
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.
17.3.1
SLAVE TRANSMISSION
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
If the R_W bit received is a ‘1’, then the serial port will
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to ‘0’ until the CPU responds by
writing to I2CTRN. SCL is released by setting the
SCLREL bit, and 8 bits of data are shifted out. Data bits
are shifted out on the falling edge of SCL, such that
SDA is valid during SCL high (see timing diagram). The
interrupt pulse is sent on the falling edge of the ninth
clock pulse, regardless of the status of the ACK
received from the master.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 109
dsPIC30F3010/3011
Clock stretching takes place following the ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing the
SCL output to be held low. The user’s ISR must set the
SCLREL bit before reception is allowed to continue. By
holding the SCL line low, the user has time to service
the ISR and read the contents of the I2CRCV before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring.
17.4.1
10-BIT MODE SLAVE
TRANSMISSION
Once a slave is addressed in this fashion, with the full
10-bit address (we will refer to this state as
"PRIOR_ADDR_MATCH"), the master can begin
sending data bytes for a slave reception operation.
17.4.2
10-BIT MODE SLAVE RECEPTION
Once addressed, the master can generate a Repeated
Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation.
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
stretching will not occur.
17.5 Automatic Clock Stretch
In the Slave modes, the module can synchronize buffer
reads and writes to the master device by clock
stretching.
2: The SCLREL bit can be set in software,
regardless of the state of the RBF bit. The
user should be careful to clear the RBF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.5.1
TRANSMIT CLOCK STRETCHING
Both 10-bit and 7-bit transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock if the TBF bit is cleared, indicat-
ing the buffer is empty.
17.5.4
CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)
In slave transmit modes, clock stretching is always
performed, irrespective of the STREN bit.
Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock, and if the
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to ‘0’ will
assert the SCL line low. The user’s ISR must set the
SCLREL bit before transmission is allowed to
continue. By holding the SCL line low, the user has
time to service the ISR and load the contents of the
I2CTRN before the master device can initiate another
transmit sequence.
After the address phase is complete, clock stretching
will occur on each data receive or transmit sequence
as was described earlier.
17.6 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit will not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low. If the SCLREL bit is cleared by
the user while the SCL line has been sampled low, the
SCL output will be asserted (held low). The SCL out-
put will remain low until the SCLREL bit is set, and all
other devices on the I2C bus have de-asserted SCL.
This ensures that a write to the SCLREL bit will not
violate the minimum high time requirement for SCL.
Note 1: If the user loads the contents of I2CTRN,
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not
be cleared and clock stretching will not
occur.
2: The SCLREL bit can be set in software,
regardless of the state of the TBF bit.
17.5.2
RECEIVE CLOCK STRETCHING
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at
the end of each data receive sequence.
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
17.5.3
CLOCK STRETCHING DURING
7-BIT ADDRESSING (STREN = 1)
When the STREN bit is set in Slave Receive mode,
the SCL line is held low when the buffer register is full.
The method for stretching the SCL output is the same
for both 7- and 10-bit addressing modes.
DS70141D-page 110
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
2
17.7 Interrupts
17.11 I C Master Support
The I2C module generates two interrupt flags, MI2CIF
(I2C Master Interrupt Flag) and SI2CIF (I2C Slave
Interrupt Flag). The MI2CIF interrupt flag is activated
on completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message
directed to the slave.
As a Master device, six operations are supported:
• Assert a Start condition on SDA and SCL
• Assert a Restart condition on SDA and SCL
• Write to the I2CTRN register initiating
transmission of data/address
• Generate a Stop condition on SDA and SCL
• Configure the I2C port to receive data
17.8 Slope Control
• Generate an ACK condition at the end of a
received byte of data
The I2C standard requires slope control on the SDA
and SCL signals for Fast Mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate
control, if desired. It is necessary to disable the slew
rate control for 1 MHz mode.
2
17.12 I C Master Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
17.9 IPMI Support
The control bit IPMIEN enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic ‘0’. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
17.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R_W = 0.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic ‘1’. Thus, the first byte
transmitted is a 7-bit slave address, followed by a ‘1’ to
indicate receive bit. Serial data is received via SDA,
while SCL outputs the serial clock. Serial data is
received 8 bits at a time. After each byte is received,
an ACK bit is transmitted. Start and Stop conditions
indicate the beginning and end of transmission.
The general call address is recognized when the Gen-
eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).
Following a start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.
If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set, and on the falling edge of the ninth bit
(ACK bit), the master event interrupt flag (MI2CIF) is
set.
17.12.1 I2C MASTER TRANSMISSION
Transmission of a data byte, a 7-bit address or the
second half of a 10-bit address is accomplished by
simply writing a value to I2CTRN register. The user
should only write to I2CTRN when the module is in a
WAITstate. This action will set the buffer full flag (TBF)
and allow the Baud Rate Generator to begin counting
and start the next transmission. Each bit of address/
data will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific, or a general call address.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 111
dsPIC30F3010/3011
17.12.2 I2C MASTER RECEPTION
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted, and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service
Routine, if the I2C bus is free (i.e., the P bit is set) the
user can resume communication by asserting a Start
condition.
Master mode reception is enabled by programming the
receive enable (RCEN) bit (I2CCON<3>). The I2C
module must be Idle before the RCEN bit is set, other-
wise the RCEN bit will be disregarded. The Baud Rate
Generator begins counting, and on each rollover, the
state of the SCL pin toggles, and data is shifted into the
I2CRSR on the rising edge of each clock.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are deasserted,
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus
collision Interrupt Service Routine, and if the I2C bus is
free, the user can resume communication by asserting
a Start condition.
17.12.3 BAUD RATE GENERATOR (BRG)
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
The Master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
As per the I2C standard, FSCL may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
A write to the I2CTRN will start the transmission of data
at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
EQUATION 17-1: I2CBRG VALUE
In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FCY
FSCL
FCY
1,111,111
I2CBRG =
– 1
–
(
)
17.12.4 CLOCK ARBITRATION
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit or Restart/Stop condition. When the SCL pin is
allowed to float high, the Baud Rate Generator is
suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the
Baud Rate Generator is reloaded with the contents of
I2CBRG and begins counting. This ensures that the
SCL high time will always be at least one BRG rollover
count in the event that the clock is held low by an
external device.
2
17.13 I C Module Operation During CPU
Sleep and Idle Modes
17.13.1 I2C OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
17.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master operation support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
17.13.2 I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
DS70141D-page 112
Confidential
© 2007 Microchip Technology Inc.
TABLE 17-2: I2C™ REGISTER MAP(1)
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
Bit 10
—
Bit 9
—
Bit 8
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
—
—
—
—
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0001 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
I2CRCV
I2CTRN
I2CBRG
I2CCON
I2CSTAT
I2CADD
0200
0202
0204
0206
Receive Register
Transmit Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Baud Rate Generator
GCEN STREN ACKDT ACKEN RCEN
GCSTAT ADD10 IWCOL I2COV D_A
Address Register
—
I2CEN
I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
PEN
R_W
RSEN
RBF
SEN
TBF
—
—
—
—
—
—
0208 ACKSTAT TRSTAT
BCL
P
S
—
—
—
020A
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 114
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
18.1 UART Module Overview
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
The key features of the UART module are:
• Full-duplex, 8 or 9-bit data communication
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates range from 38 bps to 1.875 Mbps at a
30 MHz instruction rate
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.
• 4-word deep transmit data buffer
• 4-word deep receive data buffer
• Parity, Framing and Buffer Overrun error detection
• Support for Interrupt only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for diagnostic support
FIGURE 18-1:
UART TRANSMITTER BLOCK DIAGRAM
Internal Data Bus
Control and Status bits
Write
Write
UTX8
UxTXREG Low Byte
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
Transmit Shift Register (UxTSR)
‘0’ (Start)
‘1’ (Stop)
UxTX
16X Baud Clock
from Baud Rate
Generator
Parity
Generator
16 Divider
Parity
Control
Signals
Note:
x = 1 or 2
dsPIC30F3010 only has UART1.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 115
dsPIC30F3010/3011
FIGURE 18-2:
UART RECEIVER BLOCK DIAGRAM
Internal Data Bus
16
Write
Read
Read Read
Write
UxMODE
UxSTA
UxRXREG Low Byte
URX8
Receive Buffer Control
– Generate Flags
– Generate Interrupt
– Shift Data Characters
8-9
LPBACK
From UxTX
UxRX
Load RSR
to Buffer
Receive Shift Register
(UxRSR)
1
0
Control
Signals
· Start bit Detect
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
16 Divider
16X Baud Clock from
Baud Rate Generator
UxRXIF
DS70141D-page 116
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
18.2 Enabling and Setting Up UART
18.2.1 ENABLING THE UART
18.3 Transmitting Data
18.3.1
TRANSMITTING IN 8-BIT DATA
MODE
The UART module is enabled by setting the UARTEN
bit in the UxMODE register (where x = 1 or 2). Once
enabled, the UxTX and UxRX pins are configured as an
output and an input respectively, overriding the TRIS
and LATCH register bit settings for the corresponding
I/O port pins. The UxTX pin is at logic ‘1’ when no
transmission is taking place.
The following steps must be performed in order to
transmit 8-bit data:
1. Set up the UART:
First, the data length, parity and number of stop
bits must be selected. Then, the Transmit and
Receive Interrupt enable and priority bits are
setup in the UxMODE and UxSTA registers.
Also, the appropriate baud rate value must be
written to the UxBRG register.
18.2.2
DISABLING THE UART
The UART module is disabled by clearing the
UARTEN bit in the UxMODE register. This is the
default state after any Reset. If the UART is disabled,
all I/O pins operate as port pins under the control of
the latch and TRIS bits of the corresponding port pins.
2. Enable the UART by setting the UARTEN bit
(UxMODE<15>).
3. Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
Disabling the UART module resets the buffers to
empty states. Any data characters in the buffers are
lost, and the baud rate counter is reset.
4. Write the byte to be transmitted to the lower byte
of UxTXREG. The value will be transferred to the
Transmit Shift register (UxTSR) immediately
and the serial bit stream will start shifting out
during the next rising edge of the baud clock.
Alternatively, the data byte may be written while
UTXEN = 0, following which, the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
All error and status flags associated with the UART
module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
5. A Transmit interrupt will be generated depend-
ing on the value of the interrupt control bit
UTXISEL (UxSTA<15>).
Clearing the UARTEN bit while the UART is active will
abort all pending transmissions and receptions and
reset the module as defined above. Re-enabling the
UART will restart the UART in the same configuration.
18.3.2
TRANSMITTING IN 9-BIT DATA
MODE
18.2.3
ALTERNATE I/O
The sequence of steps involved in the transmission of
9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
The alternate I/O function is enabled by setting the
ALTIO bit (U1MODE<10>). If ALTIO = 1, the UxATX and
UxARX pins (alternate transmit and alternate receive
pins, respectively) are used by the UART module
instead of the UxTX and UxRX pins. If ALTIO = 0, the
UxTX and UxRX pins are used by the UART module.
18.3.3
TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9 bits wide and 4 characters
deep. Including the Transmit Shift register (UxTSR),
the user effectively has a 5-deep FIFO (First In First
Out) buffer. The UTXBF Status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
18.2.4
SETTING UP DATA, PARITY AND
STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxMODE register are
used to select the data length and parity used in the
transmission. The data length may either be 8 bits with
even, odd or no parity, or 9 bits with no parity.
If a user attempts to write to a full buffer, the new data
will not be accepted into the FIFO, and no data shift
will occur within the buffer. This enables recovery from
a buffer overrun condition.
The STSEL bit determines whether one or two Stop bits
will be used during data transmission.
The FIFO is reset during any device Reset, but is not
affected when the device enters or wakes up from a
Power-Saving mode.
The default (power-on) setting of the UART is 8 bits, no
parity, 1 Stop bit (typically represented as 8, N, 1).
© 2007 Microchip Technology Inc.
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dsPIC30F3010/3011
18.3.4
TRANSMIT INTERRUPT
18.4.2
RECEIVE BUFFER (UXRXB)
The transmit interrupt flag (U1TXIF or U2TXIF) is
located in the corresponding Interrupt Flag register.
The receive buffer is 4 words deep. Including the
Receive Shift register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
The transmitter generates an edge to set the UxTXIF
bit. The condition for generating the interrupt depends
on UTXISEL control bit:
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0implies that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read and no
data shift will occur within the FIFO.
a) If UTXISEL = 0, an interrupt is generated when
a word is transferred from the Transmit buffer to
the Transmit Shift register (UxTSR). This implies
that the transmit buffer has at least one empty
word.
The FIFO is reset during any device Reset. It is not
affected when the device enters or wakes up from a
Power Saving mode.
b) If UTXISEL = 1, an interrupt is generated when
a word is transferred from the Transmit buffer to
the Transmit Shift register (UxTSR) and the
Transmit buffer is empty.
18.4.3
RECEIVE INTERRUPT
The receive interrupt flag (U1RXIF or U2RXIF) can be
read from the corresponding Interrupt Flag register.
The interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
Switching between the two interrupt modes during
operation is possible and sometimes offers more
flexibility.
18.3.5
TRANSMIT BREAK
a) If URXISEL<1:0> = 00 or 01, an interrupt is
generated every time a data word is transferred
from the Receive Shift register (UxRSR) to the
receive buffer. There may be one or more
characters in the receive buffer.
Setting the UTXBRK bit (UxSTA<11>) will cause the
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
b) If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive
Shift register (UxRSR) to the receive buffer,
which, as a result of the transfer, contains 3
characters.
To send a break character, the UTXBRK bit must be
set by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate stop bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid stop bit(s) before reloading
the UxTXB or starting other transmitter activity. Trans-
mission of a break character does not generate a
transmit interrupt.
c) If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
register (UxRSR) to the receive buffer, which, as
a result of the transfer, contains 4 characters
(i.e., becomes full).
Switching between the Interrupt modes during opera-
tion is possible, though generally not advisable during
normal operation.
18.4 Receiving Data
18.4.1
RECEIVING IN 8-BIT OR 9-BIT DATA
MODE
18.5 Reception Error Handling
The following steps must be performed while receiving
8-bit or 9-bit data:
18.5.1
RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
1. Set up the UART (see Section 18.3.1 and
Section 18.3.2).
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
2. Enable the UART (see Section 18.3.1 and
Section 18.3.2).
a) The receive buffer is full.
3. A receive interrupt will be generated when one
or more data words have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
b) The Receive Shift register is full, but unable to
transfer the character to the receive buffer.
c) The Stop bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.
5. Read the received data from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FERR values will be updated.
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
18.5.2
FRAMING ERROR (FERR)
18.6 Address Detect Mode
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a Stop bit. If two stop bits are selected, both
stop bits must be ‘1’, otherwise FERR will be set. The
read-only FERR bit is buffered along with the received
data. It is cleared on any Reset.
Setting the ADDEN bit (UxSTA<5>) enables the
Address Detect mode, in which a 9th bit (URX8) value
of ‘1’ identifies the received word as an address rather
than data. This mode is only applicable for 9-bit data
communication. The URXISEL control bit does not
have any impact on interrupt generation in this mode,
since an interrupt (if enabled) will be generated every
time the received word has the 9th bit set.
18.5.3
PARITY ERROR (PERR)
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read-only PERR bit is buffered along with the received
data bytes. It is cleared on any Reset.
18.7 Loopback Mode
Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
pin. When configured for the loopback mode, the UxRX
pin is disconnected from the internal UART receive
logic. However, the UxTX pin still functions as in a
normal operation.
18.5.4
IDLE STATUS
When the receiver is active (i.e., between the initial
detection of the start bit and the completion of the stop
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the
completion of the stop bit and detection of the next
start bit, the RIDLE bit is ‘1’, indicating that the UART
is Idle.
To select this mode:
a) Configure UART for desired mode of operation.
b) Set LPBACK = 1to enable Loopback mode.
c) Enable transmission as defined in Section 18.3
"Transmitting Data".
18.5.5
RECEIVE BREAK
The receiver will count and expect a certain number of
bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
bits.
18.8 Baud Rate Generator
The UART has a 16-bit Baud Rate Generator to allow
maximum flexibility in baud rate generation. The Baud
Rate Generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specified by PDSEL and STSEL. The URXDA bit is
set, FERR is set, zeros are loaded into the receive
FIFO, interrupts are generated, if appropriate and the
RIDLE bit is set.
BRG = 16-bit value held in UxBRG register
(0 through 65535)
FCY = Instruction Clock Rate (1/TCY)
The baud rate is given by Equation 18-1.
When the module receives a long break signal and the
receiver has detected the start bit, the data bits and
the invalid stop bit (which sets the FERR), the receiver
must wait for a valid stop bit before looking for the next
start bit. It cannot assume that the break condition on
the line is the next start bit.
EQUATION 18-1: BAUD RATE
Baud Rate = FCY / (16*(BRG+1))
Break is regarded as a character containing all 0’s,
with the FERR bit set. The break character is loaded
into the buffer. No further reception can occur until a
stop bit is received. Note that RIDLE goes high when
the stop bit has not been received yet.
Therefore, maximum baud rate possible is
FCY /16 (if BRG = 0),
and the minimum baud rate possible is
FCY / (16* 65536).
With a full 16-bit Baud Rate Generator, at 30 MIPs
operation, the minimum baud rate achievable is
28.5 bps.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 119
dsPIC30F3010/3011
18.10.2 UART OPERATION DURING CPU
IDLE MODE
18.9 Auto Baud Support
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a selected capture input. To enable this mode, the
user must program the input capture module to detect
the falling and rising edges of the start bit.
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode, or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
18.10 UART Operation During CPU
Sleep and Idle Modes
18.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is
in progress, then the transmission is aborted. The
UxTX pin is driven to logic ‘1’. Similarly, if entry into
Sleep mode occurs while a reception is in progress,
then the reception is aborted. The UxSTA, UxMODE,
Transmit and Receive registers and buffers, and the
UxBRG register are not affected by Sleep mode.
If the Wake bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select Mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from Sleep. The UARTEN
bit must be set in order to generate a wake-up
interrupt.
DS70141D-page 120
Confidential
© 2007 Microchip Technology Inc.
TABLE 18-1: UART1 REGISTER MAP(1)
SFR Name Addr.
Bit 15
Bit 14 Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PDSEL1 PDSEL0 STSEL
FERR OERR URXDA
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0001 0001 0000
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
U1MODE
U1STA
020C UARTEN
020E UTXISEL
—
—
—
—
USIDL
—
—
—
—
—
—
ALTIO
—
—
WAKE
LPBACK ABAUD
—
—
UTXBRK UTXEN UTXBF
TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
U1TXREG 0210
U1RXREG 0212
—
—
—
—
—
—
—
—
—
UTX8
Transmit Register
Receive Register
—
URX8
U1BRG
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
0214
Baud Rate Generator Prescaler
TABLE 18-2: UART2 REGISTER MAP(1) (NOT AVAILABLE ON dsPIC30F3010)
SFR
Addr.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Name
U2MODE
U2STA
0000 0000 0000 0000
0000 0001 0001 0000
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0216 UARTEN
0218 UTXISEL
—
—
—
—
USIDL
—
—
—
—
—
—
—
—
—
WAKE
LPBACK ABAUD
—
—
PDSEL1 PDSEL0 STSEL
FERR OERR URXDA
UTXBRK UTXEN UTXBF
TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
U2TXREG 021A
U2RXREG 021C
—
—
—
—
—
—
—
—
—
UTX8
Transmit Register
Receive Register
—
URX8
U2BRG
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
021E
Baud Rate Generator Prescaler
dsPIC30F3010/3011
NOTES:
DS70141D-page 122
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
The ADC module has six 16-bit registers:
19.0 10-BIT HIGH-SPEED ANALOG-
TO-DIGITAL CONVERTER
(ADC) MODULE
• A/D Control register 1 (ADCON1)
• A/D Control register 2 (ADCON2)
• A/D Control register 3 (ADCON3)
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• A/D Input Select register (ADCHS)
• A/D Port Configuration register (ADPCFG)
• A/D Input Scan Selection register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers
control the operation of the ADC module. The ADCHS
register selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
The10-bit high-speed Analog-to-Digital Converter (ADC)
allows conversion of an analog input signal to a 10-bit
digital number. This module is based on a Successive
Approximation Register (SAR) architecture, and provides
a maximum sampling rate of 1 Msps. The ADC module
has 16 analog inputs which are multiplexed into four
sample and hold amplifiers. The output of the sample and
hold is the input into the converter, which generates the
result. The analog reference voltages are software
selectable to either the device supply voltage (AVDD/
AVSS) or the voltage level on the (VREF+/VREF-) pin. The
ADC has a unique feature of being able to operate while
the device is in Sleep mode.
Note:
The SSRC<2:0>, ASAM, SIMSAM,
SMPI<3:0>, BUFM and ALTS bits, as well
as the ADCON3 and ADCSSL registers,
must not be written to while ADON = 1.
This would lead to indeterminate results.
The block diagram of the ADC module is shown in
Figure 19-1.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 123
dsPIC30F3010/3011
FIGURE 19-1:
10-BIT HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM
AVSS
AVDD
VREF+
VREF-
AN0
AN3
AN0
AN1
AN2
+
CH1
ADC
S/H
AN6
-
10-bit Result
Conversion Logic
AN1
AN4
+
CH2
S/H
AN7
-
16-word, 10-bit
Dual Port
Buffer
AN2
AN5
+
CH3
S/H
AN8
CH1,CH2,
CH3,CH0
-
Sample/Sequence
Control
sample
AN0
AN1
AN2
AN3
Input
Switches
Input Mux
Control
AN3
AN4
AN4
AN5
AN6
AN7
AN8
AN5
*AN6
*AN7
*AN8
+
CH0
S/H
-
AN1
* = Not available on dsPIC30F3010.
DS70141D-page 124
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
The CHPS bits selects how many channels are sam-
pled. This can vary from 1, 2 or 4 channels. If CHPS
selects 1 channel, the CH0 channel will be sampled at
the sample clock and converted. The result is stored in
the buffer. If CHPS selects 2 channels, the CH0 and
CH1 channels will be sampled and converted. If CHPS
selects 4 channels, the CH0, CH1, CH2 and CH3
channels will be sampled and converted.
19.1 ADC Result Buffer
The module contains a 16-word dual-port read-only
buffer, called ADCBUF0...ADCBUFF, to buffer the ADC
results. The RAM is 10 bits wide, but is read into different
format 16-bit words. The contents of the sixteen ADC
conversion result buffer registers, ADCBUF0 through
ADCBUFF, cannot be written by user software.
The SMPI bits select the number of acquisition/conver-
sion sequences that would be performed before an
interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
19.2 Conversion Operation
After the ADC module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs and
external events, will terminate acquisition and start a con-
version. When the A/D conversion is complete, the result
is loaded into ADCBUF0...ADCBUFF, and the A/D
interrupt flag ADIF and the DONE bit are set after the
number of samples specified by the SMPI bit.
The user cannot program a combination of CHPS and
SMPI bits that specifies more than 16 conversions per
interrupt, or 8 conversions per interrupt, depending on
the BUFM bit. The BUFM bit, when set, will split the
16-word results buffer (ADCBUF0...ADCBUFF) into
two 8-word groups. Writing to the 8-word buffers will be
alternated on each interrupt event. Use of the BUFM bit
will depend on how much time is available for moving
data out of the buffers after the interrupt, as determined
by the application.
The following steps should be followed for doing an
A/D conversion:
• Configure the ADC module:
- Configure analog pins, voltage reference and
digital I/O
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be ‘0’ and up to 16 conversions may
be done per interrupt. The processor will have one
sample and conversion time to move the sixteen
conversions.
- Select A/D input channels
- Select A/D conversion clock
- Select A/D conversion trigger
- Turn on A/D module
• Configure A/D interrupt (if required):
- Clear ADIF bit
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should
be ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) =
0111, then eight conversions will be loaded into 1/2 of
the buffer, following which an interrupt occurs. The next
eight conversions will be loaded into the other 1/2 of the
buffer. The processor will have the entire time between
interrupts to move the eight conversions.
- Select A/D interrupt priority
• Start sampling
• Wait the required acquisition time
• Trigger acquisition end; start conversion
• Wait for A/D conversion to complete, by either:
- Waiting for the A/D interrupt
- Waiting for the DONE bit to be set
• Read A/D result buffer; clear ADIF if required
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000, on the first sample/convert
sequence, the MUX A inputs are selected, and on the
next acquire/convert sequence, the MUX B inputs are
selected.
19.3 Selecting the Conversion
Sequence
Several groups of control bits select the sequence in
which the A/D connects inputs to the sample/hold
channels, converts channels, writes the buffer memory,
and generates interrupts. The sequence is controlled
by the sampling clocks.
The CSCNA bit (ADCON2<10>) will allow the CH0
channel inputs to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is ‘1’, the corre-
sponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
The SIMSAM bit controls the acquire/convert
sequence for multiple channels. If the SIMSAM bit is
‘0’, the two or four selected channels are acquired and
converted sequentially, with two or four sample clocks.
If the SIMSAM bit is ‘1’, two or four selected channels
are acquired simultaneously, with one sample clock.
The channels are then converted sequentially. Obvi-
ously, if there is only 1 channel selected, the SIMSAM
bit is not applicable.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 125
dsPIC30F3010/3011
19.4 Programming the Start of
Conversion Trigger
19.6 Selecting the A/D Conversion
Clock
The conversion trigger will terminate acquisition and
start the requested conversions.
The A/D conversion requires 12 TAD. The source of the
A/D conversion clock is software selected using a six
bit counter. There are 64 possible options for TAD.
The SSRC<2:0> bits select the source of the
conversion trigger.
EQUATION 19-1: A/D CONVERSION CLOCK
The SSRC bits provide for up to 5 alternate sources of
conversion trigger.
TAD = TCY * (0.5 * (ADCS<5:0> + 1))
TAD
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
ADCS<5:0> = 2
– 1
TCY
The internal RC oscillator is selected by setting the
ADRC bit.
When SSRC<2:0> = 111 (Auto Start mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least 1 clock cycle.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 83.33 nsec (for VDD = 5V). Refer to the Section 23.0
"Electrical Characteristics" for minimum TAD under
other operating conditions.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
Note:
To operate the A/D at the maximum
specified conversion speed, the Auto
Convert Trigger option should be selected
(SSRC = 111) and the Auto Sample Time
bits should be set to 1 TAD (SAMC =
00001). This configuration will give a total
conversion period (sample + convert) of
13 TAD.
EXAMPLE 19-1:
A/D CONVERSION CLOCK
CALCULATION
TAD = 154 nsec
TCY = 33 nsec (30 MIPS)
The use of any other conversion trigger
will result in additional TAD cycles to
synchronize the external event to the A/D.
TAD
TCY
154 nsec
33 nsec
ADCS<5:0> = 2
– 1
= 2 •
– 1
19.5 Aborting a Conversion
= 8.33
Therefore,
Set ADCS<5:0> = 9
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
TCY
2
Actual TAD =
=
(ADCS<5:0> + 1)
33 nsec
2
(9 + 1)
If the clearing of the ADON bit coincides with an auto
start, the clearing has a higher priority.
= 165 nsec
After the A/D conversion is aborted, a 2 TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multi-channel group conversion sequence.
DS70141D-page 126
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
19.7 ADC Conversion Speeds
The dsPIC30F 10-bit ADC specifications permit a
maximum
1
Msps sampling rate. Table 19-1
summarizes the conversion speeds for the dsPIC30F
10-bit A/D converter and the required operating
conditions.
TABLE 19-1: 10-BIT ADC CONVERSION RATE PARAMETERS
dsPIC30F 10-bit ADC Conversion Rates
TAD
Sampling
ADC Speed
RS Max
VDD
Temperature
A/D Channels Configuration
Minimum Time Min
Up to
83.33 ns
12 TAD
500Ω
4.5V to 5.5V -40°C to +85°C
V
CH1, CH2 or CH3
CH0
REF- VREF+
1 Msps(1)
ANx
S/H
S/H
ADC
Up to
95.24 ns
2 TAD
500Ω
500Ω
4.5V to 5.5V -40°C to +85°C
3.0V to 5.5V -40°C to +125°C
V
REF
-
VREF+
750 ksps(1)
CHX
ANx
S/H
ADC
Up to
138.89 ns
12 TAD
VREF
-
VREF+
600 ksps(1)
CH1, CH2 or CH3
CH0
ANx
S/H
S/H
ADC
Up to
500 ksps
153.85 ns
256.41 ns
1 TAD
1 TAD
5.0 kΩ
5.0 kΩ
4.5V to 5.5V -40°C to +125°C
3.0V to 5.5V -40°C to +125°C
V
REF
or
-
V
REF
or
+
AVSS AVDD
CHX
ANx
S/H
ADC
ANx or VREF
-
Up to
300 ksps
VREF
-
VREF
+
or
or
AVSS AVDD
CHX
ANx
S/H
ADC
ANx or VREF
-
Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 19-2 for recommended
circuit.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 127
dsPIC30F3010/3011
The configuration guidelines give the required setup
values for the conversion speeds above 500 ksps,
since they require external VREF pins usage and there
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.
The following figure depicts the recommended circuit
for the conversion rates above 500 ksps.
FIGURE 19-2:
ADC VOLTAGE REFERENCE SCHEMATIC
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
V
DD
DD
V
DD
DD
V
DD
DD
C8
C7
0.1
C6
0.01
μ
F
μ
F
1 μF
V
SS
V
SS
VDD
VDD
dsPIC30F3011
VDD
VDD
V
V
V
C5
1 μF
C4
0.1
C3
0.01
μ
F
μ
F
10
11
V
DD
R1
10
R2
10
VDD
C2
0.1 μF
C1
0.01
μF
19.7.1
1 Msps CONFIGURATION
GUIDELINE
19.7.1.3
1 Msps Configuration Items
The following configuration items are required to
achieve a 1 Msps conversion rate.
The configuration for 1 Msps operation is dependent on
whether a single input pin is to be sampled or whether
multiple pins will be sampled.
• Comply with conditions provided in Table 20-2
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 19-2
19.7.1.1
Single Analog Input
• Set SSRC<2:0> = 111in the ADCON1 register to
For conversions at 1 Msps for a single analog input, at
least two sample and hold channels must be enabled.
The analog input multiplexer must be configured so
that the same input pin is connected to both sample
and hold channels. The ADC converts the value held
on one S/H channel, while the second S/H channel
acquires a new input sample.
enable the auto-convert option
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable sequential sampling by clearing the
SIMSAM bit in the ADCON1 register
• Enable at least two sample and hold channels by
writing the CHPS<1:0> control bits in the
ADCON2 register
19.7.1.2
Multiple Analog Inputs
• Write the SMPI<3:0> control bits in the ADCON2
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI<3:0> = 0001since at least two sample and
hold channels should be enabled
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 1 Msps conversion rate is divided among
the different input signals. For example, four inputs can
be sampled at a rate of 250 ksps for each signal or two
inputs could be sampled at a rate of 500 ksps for each
signal. Sequential sampling must be used in this con-
figuration to allow adequate sampling time on each
input.
DS70141D-page 128
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
• Configure the A/D clock period to be:
1
19.7.3.2
Multiple Analog Input
The A/D converter can also be used to sample multiple
analog inputs using multiple sample and hold channels.
In this case, the total 600 ksps conversion rate is
divided among the different input signals. For example,
four inputs can be sampled at a rate of 150 ksps for
each signal or two inputs can be sampled at a rate of
300 ksps for each signal. Sequential sampling must be
used in this configuration to allow adequate sampling
time on each input.
= 83.33 ns
12 x 1,000,000
by writing to the ADCS<5:0> control bits in the
ADCON3 register
• Configure the sampling time to be 2 TAD by
writing: SAMC<4:0> = 00010
• Select at least two channels per analog input pin
by writing to the ADCHS register
19.7.3.3
600 ksps Configuration Items
19.7.2
750 ksps CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 600 ksps conversion rate.
The following configuration items are required to
achieve a 750 ksps conversion rate. This configuration
assumes that a single analog input is to be sampled.
• Comply with conditions provided in Table 20-2
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 19-2
• Comply with conditions provided in Table 20-2
• Set SSRC<2:0> = 111in the ADCON1 register to
enable the auto-convert option
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 19-2
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Set SSRC<2:0> = 111in the ADCON1 register to
enable the auto-convert option
• Enable sequential sampling by clearing the
SIMSAM bit in the ADCON1 register
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable at least two sample and hold channels by
writing the CHPS<1:0> control bits in the
ADCON2 register
• Enable one sample and hold channel by setting
CHPS<1:0> = 00in the ADCON2 register
• Write the SMPI<3:0> control bits in the ADCON2
register for the desired number of conversions
between interrupts
• Write the SMPI<3:0> control bits in the ADCON2
register for the desired number of conversions
between interrupts. At a minimum, set
• Configure the A/D clock period to be:
SMPI<3:0> = 0001since at least two sample and
hold channels should be enabled
1
= 95.24 ns
• Configure the A/D clock period to be:
(12 + 2) X 750,000
1
= 138.89 ns
by writing to the ADCS<5:0> control bits in the
ADCON3 register
12 x 600,000
• Configure the sampling time to be 2 TAD by
writing: SAMC<4:0> = 00010
by writing to the ADCS<5:0> control bits in the
ADCON3 register
• Configure the sampling time to be 2 TAD by
writing: SAMC<4:0> = 00010
19.7.3
600 ksps CONFIGURATION
GUIDELINE
Select at least two channels per analog input pin by
writing to the ADCHS register
The configuration for 600 ksps operation is dependent
on whether a single input pin is to be sampled or
whether multiple pins will be sampled.
19.7.3.1
Single Analog Input
When performing conversions at 600 ksps for a single
analog input, at least two sample and hold channels
must be enabled. The analog input multiplexer must be
configured so that the same input pin is connected to
both sample and hold channels. The A/D converts the
value held on one S/H channel, while the second S/H
channel acquires a new input sample.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 129
dsPIC30F3010/3011
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
19.8 A/D Acquisition Requirements
The analog input model of the 10-bit ADC is shown in
Figure 19-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
VDD and the holding capacitor charge time.
The user must allow at least 1 TAD period of sampling
time, TSAMP, between conversions to allow each
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
ADC. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Section 23.0 "Electrical Characteristics" for TAD and
sample time requirements.
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
source impedance (RS), the interconnect impedance
(RIC) and the internal sampling switch (RSS) imped-
ance combine to directly affect the time required to
charge the capacitor CHOLD. The combined imped-
ance of the analog sources must therefore be small
enough to fully charge the holding capacitor within the
chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the A/D converter,
the maximum recommended source impedance, RS, is
5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
FIGURE 19-3:
ADC ANALOG INPUT MODEL
VDD
RIC ≤ 250Ω
RSS ≤ 3 kΩ
Sampling
Switch
VT = 0.6V
ANx
RSS
Rs
CHOLD
CPIN
= DAC capacitance
VA
I leakage
500 nA
VT = 0.6V
= 4.4 pF
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
RSS
= sampling switch resistance
= sample/hold capacitance (from DAC)
CHOLD
Note:
CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
DS70141D-page 130
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
If the ADC interrupt is enabled, the device will wake-up
from Sleep. If the ADC interrupt is not enabled, the
ADC module will then be turned off, although the
ADON bit will remain set.
19.9 Module Power-down Modes
The module has 3 internal power modes. When the
ADON bit is ‘1’, the module is in Active mode; it is fully
powered and functional. When ADON is ‘0’, the module
is in Off mode. The digital and analog portions of the
circuit are disabled for maximum current savings. In
order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
19.10.2 A/D OPERATION DURING CPU IDLE
MODE
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will
continue operation on assertion of Idle mode. If
ADSIDL = 1, the module will stop on Idle.
19.10 ADC Operation During CPU Sleep
and Idle Modes
19.11 Effects of a Reset
19.10.1 ADC OPERATION DURING CPU
SLEEP MODE
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and acquisition sequence is aborted. The
values that are in the ADCBUF registers are not
modified. The A/DC Result register will contain
unknown data after a Power-on Reset.
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exit from
Sleep mode.
19.12 Output Formats
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC result is 10 bits wide. The data buffer RAM is
also 10 bits wide. The 10-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits
one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed,
which eliminates all digital switching noise from the
conversion. When the conversion is complete, the
DONE bit will be set and the result loaded into the
ADCBUF register.
Write data will always be in right justified (integer)
format.
FIGURE 19-4:
ADC OUTPUT DATA FORMATS
RAM Contents:
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15)
Fractional (1.15)
Signed Integer
Integer
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
0
0
0
0
0
0
d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 131
dsPIC30F3010/3011
19.13 Configuring Analog Port Pins
19.14 Connection Considerations
The use of the ADPCFG and TRIS registers control the
operation of the ADC port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The analog inputs have diodes to VDD and VSS as ESD
protection. This requires that the analog input be
between VDD and VSS. If the input voltage exceeds this
range by greater than 0.3V (either direction), one of the
diodes becomes forward biased and it may damage the
device if the input current specification is exceeded.
The A/D operation is independent of the state of the
CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.
An external RC filter is sometimes added for anti-
aliasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
When reading the PORT register, all pins configured as
analog input channels will read as cleared.
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) may cause the
input buffer to consume current that exceeds the
device specifications.
DS70141D-page 132
Confidential
© 2007 Microchip Technology Inc.
TABLE 19-2: ADC REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14
Bit 13
—
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 00uu uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADCBUF4
ADCBUF5
ADCBUF6
ADCBUF7
ADCBUF8
ADCBUF9
ADCBUFA
ADCBUFB
ADCBUFC
ADCBUFD
ADCBUFE
ADCBUFF
ADCON1
ADCON2
ADCON3
ADCHS
0280
0282
0284
0286
0288
028A
028C
028E
0290
0292
0294
0296
0298
029A
029C
029E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 8
ADC Data Buffer 9
ADC Data Buffer 10
ADC Data Buffer 11
ADC Data Buffer 12
ADC Data Buffer 13
ADC Data Buffer 14
ADC Data Buffer 15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
02A0 ADON
02A2
ADSIDL
—
FORM<1:0>
CHPS<1:0>
SSRC<2:0>
SIMSAM ASAM
SMPI<3:0>
ADCS<5:0>
CH0SA<3:0>
SAMP DONE
VCFG<2:0>
—
CSCNA
SAMC<4:0>
BUFS
ADRC
—
—
BUFM ALTS
02A4
—
—
02A6 CH123NB<1:0> CH123SB CH0NB
CH0SB<3:0>
CH123NA<1:0>
PCFG8* PCFG7* PCFG6*
CSSL8* CSSL7* CSSL6*
CH123SA CH0NA
ADPCFG
ADCSSL
02A8
02AA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCFG5
CSSL5
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
Legend: u= uninitialized bit; — = unimplemented bit, * = not available on dsPIC30F3010
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
NOTES:
DS70141D-page 134
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
20.1 Oscillator System Overview
20.0 SYSTEM INTEGRATION
The dsPIC30F oscillator system has the following
modules and features:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual “ (DS70157).
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to boost internal operating
frequency
• A clock switching mechanism between various
clock sources
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection:
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• Oscillator Selection
• Reset
• Clock Control register OSCCON
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• Power-Saving modes (Sleep and Idle)
• Code Protection
• Configuration bits for main oscillator selection
Configuration bits determine the clock source upon
Power-on Reset and Brown-out Reset. Thereafter, the
clock source can be changed between permissible
clock sources. The OSCCON register controls the
clock switching and reflects system clock related sta-
tus bits.
Table 20-1 provides a summary of the dsPIC30F
Oscillator Operating modes. A simplified diagram of the
oscillator system is shown in Figure 20-1.
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
dsPIC30F devices have a Watchdog Timer, which is
permanently enabled via the Configuration bits, or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator Start-
up Timer (OST), intended to keep the chip in Reset until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a delay on power-up
only, designed to keep the part in Reset while the
power supply stabilizes. With these two timers on-chip,
most applications need no external Reset circuitry.
Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active, but the CPU is shut-off. The RC oscillator
option saves system cost, while the LP crystal option
saves power.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 135
dsPIC30F3010/3011
TABLE 20-1: OSCILLATOR OPERATING MODES
Oscillator Mode
Description
XTL
200 kHz-4 MHz crystal on OSC1:OSC2.
4 MHz-10 MHz crystal on OSC1:OSC2.
XT
XT w/ PLL 4x
XT w/ PLL 8x
XT w/ PLL 16x
LP
4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled.
4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled.
4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1)
.
32 kHz crystal on SOSCO:SOSCI(2)
.
HS
10 MHz-25 MHz crystal.
HS/2 w/PLL 4x
HS/2 w/PLL 8x
HS/2 w/PLL 16x
HS/3 w/PLL 4x
HS/3 w/PLL 8x
HS/3 w/PLL 16x
EC
10 MHz-25 MHz crystal, divide by 2, 4x PLL enabled.
10 MHz-25MHz crystal, divide by 2, 8x PLL enabled.
10 MHz-25MHz crystal, divide by 2, 16x PLL enabled(1)
10 MHz-25 MHz crystal, divide by 3, 4x PLL enabled.
10 MHz-25MHz crystal, divide by 3, 8x PLL enabled.
10 MHz-25MHz crystal, divide by 3, 16x PLL enabled(1)
External clock input (0-40 MHz).
.
.
ECIO
External clock input (0-40 MHz), OSC2 pin is I/O.
EC w/PLL 4x
EC w/PLL 8x
EC w/PLL 16x
ERC
External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled(1)
External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled(1)
.
.
External clock input (4-10 MHz), OSC2 pin is I/O, 16x PLL enabled(1)
External RC oscillator, OSC2 pin is FOSC/4 output(3)
.
.
ERCIO
External RC oscillator, OSC2 pin is I/O(3)
.
FRC
8 MHz internal RC oscillator.
FRC w/PLL 4x
FRC w/PLL 8x
FRC w/PLL 16x
LPRC
7.37 MHz Internal RC oscillator, 4x PLL enabled.
7.37 MHz Internal RC oscillator, 8x PLL enabled.
7.37 MHz Internal RC oscillator, 16x PLL enabled.
512 kHz internal RC oscillator.
Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.
2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.
3: Requires external R and C. Frequency operation up to 4 MHz.
DS70141D-page 136
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 20-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
Oscillator Configuration bits
PWRSAVInstruction
Wake-up Request
FPLL
OSC1
OSC2
Primary
PLL
Oscillator
x4, x8, x16
PLL
Lock
COSC<2:0>
NOSC<2:0>
OSWEN
Primary Osc
TUN<3:0>
4
Primary
Oscillator
Stability Detector
Internal Fast RC
Oscillator (FRC)
Oscillator
Start-up
Timer
POR Done
Clock
Programmable
Switching
and Control
Block
Secondary Osc
Clock Divider
System
Clock
SOSCO
SOSCI
Secondary
Oscillator
Stability Detector
32 kHz LP
Oscillator
2
POST<1:0>
LPRC
Internal Low
Power RC
Oscillator (LPRC)
CF
Fail-Safe Clock
Monitor (FSCM)
FCKSM<1:0>
2
Oscillator Trap
To Timer1
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 137
dsPIC30F3010/3011
20.2.2
OSCILLATOR START-UP TIMER
(OST)
20.2 Oscillator Configurations
20.2.1
INITIAL CLOCK SOURCE
SELECTION
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an oscillator
start-up timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscillator clock to the rest of the system. The time-out
period is designated as TOST. The TOST time is involved
every time the oscillator has to restart (i.e., on POR,
BOR and wake-up from Sleep). The oscillator start-up
timer is applied to the LP Oscillator, XT, XTL and HS
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator.
While coming out of Power-on Reset or Brown-out
Reset, the device selects its clock source based on:
a) FOS<2:0> Configuration bits that select one of
four oscillator groups,
b) and FPR<4:0> Configuration bits that select one
of 15 oscillator choices within the primary group.
The selection is as shown in Table 20-2.
TABLE 20-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator
Source
Oscillator Mode
FOS<2:0>
FPR<4:0>
OSC2 Function
ECIO w/PLL 4x
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
X
X
X
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
X
X
X
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
X
X
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
X
X
X
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
0
1
1
0
0
X
X
X
I/O
I/O
ECIO w/PLL 8x
ECIO w/PLL 16x
FRC w/PLL 4X
FRC w/PLL 8x
FRC w/PLL 16x
XT w/PLL 4x
XT w/PLL 8x
XT w/PLL 16x
HS2 w/PLL 4x
HS2 w/PLL 8x
HS2 w/PLL 16x
HS3 w/PLL 4x
HS3 w/PLL 8x
HS3 w/PLL 16x
ECIO
I/O
I/O
I/O
I/O
OSC2
OSC2
OSC2
OSC2
OSC2
OSC2
OSC2
OSC2
OSC2
I/O
External
XT
External
OSC2
OSC2
CLKO
CLKO
I/O
HS
External
EC
External
ERC
External
ERCIO
External
XTL
External
OSC2
(Note 1, 2)
(Note 1, 2)
(Note 1, 2)
LP
Secondary
Internal FRC
Internal LPRC
FRC
LPRC
Note 1: OSC2 pin function is determined by (FPR<4:0>).
2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all
times.
DS70141D-page 138
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
.
20.2.3
LP OSCILLATOR CONTROL
Note:
When a 16x PLL is used, the FRC fre-
quency must not be tuned to a frequency
greater than 7.5 MHz.
Enabling the LP oscillator is controlled with two
elements:
1. The current oscillator group bits COSC<2:0>
2. The LPOSCEN bit (OSCON register)
TABLE 20-4: FRC TUNING
TUN<3:0>
FRC Frequency
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
Bits
0111
0110
0101
0100
0011
0010
0001
0000
+ 10.5%
+ 9.0%
+ 7.5%
+ 6.0%
+ 4.5%
+ 3.0%
+ 1.5%
•
COSC<1:0> = 00(LP selected as main oscillator)
and
•
LPOSCEN = 1
Keeping the LP oscillator on at all times allows for a
fast switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator will
still require a start-up time.
Center Frequency (oscillator is
running at calibrated frequency)
20.2.4
PHASE LOCKED LOOP (PLL)
1111
1110
1101
1100
1011
1010
1001
1000
- 1.5%
- 3.0%
- 4.5%
- 6.0%
- 7.5%
- 9.0%
- 10.5%
- 12.0%
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8, and x16. Input and output frequency
ranges are summarized in Table 20-3.
TABLE 20-3: PLL FREQUENCY RANGE
PLL
Fin
Fout
Multiplier
4 MHz-10 MHz
4 MHz-10 MHz
4 MHz-7.5 MHz
x4
x8
16 MHz-40 MHz
32 MHz-80 MHz
64 MHz-120 MHz
20.2.6
LOW-POWER RC OSCILLATOR
(LPRC)
x16
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a low
frequency clock source option for applications where
power consumption is critical, and timing accuracy is
not required.
The PLL features a lock output, which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the
read only LOCK bit in the OSCCON register.
20.2.5
FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (7.37 MHz +/- 2% nominal)
internal RC oscillator. This oscillator is intended to pro-
vide reasonable device operating speeds without the
use of an external crystal, ceramic resonator or RC net-
work. The FRC oscillator can be used with the PLL to
obtain higher clock frequencies.
The LPRC oscillator is always enabled at a Power-on
Reset, because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator will
remain ONif one of the following is true:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled
The dsPIC30F operates from the FRC oscillator
whenever the Current Oscillator Selection control bits
in the OSCCON register (OSCCON<13:12>) are set to
‘01’.
• The LPRC oscillator is selected as the system
clock via the COSC<1:0> control bits in the
OSCCON register
The four bit field specified by TUN<3:0>
(OSCTUN<3:0>) allows the user to tune the internal
fast RC oscillator (nominal 7.37 MHz). The user can
tune the FRC oscillator within a range of +10.5% (840
kHz) and -12% (960 kHz) in steps of 1.50% around the
factory-calibrated setting, see Table 20-4.
If one of the above conditions is not true, the LPRC will
shut-off after the PWRT expires.
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR<3:0>).
2: OSC1 pin cannot be used as an I/O pin,
even if the secondary oscillator or an
internal clock source is selected at all
times.
If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are
set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multi-
plier of 4, 8 or 16 (respectively) is applied
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 139
dsPIC30F3010/3011
The OSCCON register holds the control and status bits
related to clock switching.
20.2.7
FAIL-SAFE CLOCK MONITOR
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM configuration bits (Clock
Switch and Monitor Selection bits) in the FOSC Device
Configuration register. If the FSCM function is
enabled, the LPRC Internal oscillator will run at all
times (except during Sleep mode) and will not be
subject to control by the SWDTEN bit.
• COSC<1:0>: Read-only status bits always reflect
the current oscillator group in effect.
• NOSC<1:0>: Control bits which are written to
indicate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
NOSC<1:0> are both loaded with the
Configuration bit values FOS<1:0>.
• LOCK: The LOCK status bit indicates a PLL lock.
In the event of an oscillator failure, the FSCM will
generate a clock failure trap event and will switch the
system clock over to the FRC oscillator. The user will
then have the option to either attempt to restart the
oscillator or execute a controlled shut down. The user
may decide to treat the trap as a warm Reset by simply
loading the Reset address into the oscillator fail trap
vector. In this event, the CF (Clock Fail) status bit
(OSCCON<3>) is also set whenever a clock failure is
recognized.
• CF: Read-only Status bit indicating if a clock fail
detect has occurred.
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up
situations).
If Configuration bits FCKSM<1:0> = 1x, then the clock
switching and fail-safe clock monitor functions are
disabled. This is the default Configuration bit setting.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection
and the COSC<1:0> bits do not control the clock
selection. However, these bits will reflect the clock
source selection.
If the oscillator has a very slow start-up time coming
out of POR, BOR or Sleep, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM will be activated and
the FSCM will initiate a clock failure trap, and the
COSC<1:0> bits are loaded with FRC oscillator selec-
tion. This will effectively shut-off the original oscillator
that was trying to start.
Note:
The application should not attempt to
switch to a clock of frequency lower than
100 kHz when the fail-safe clock monitor is
enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the fast RC
oscillator.
The user may detect this situation and restart the
oscillator in the clock fail trap ISR.
Upon a clock failure detection, the FSCM module will
initiate a clock switch to the FRC Oscillator as follows:
20.2.8
PROTECTION AGAINST
1. The COSC bits (OSCCON<13:12>) are loaded
with the FRC Oscillator selection value.
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
2. CF bit is set (OSCCON<3>).
3. OSWEN control bit (OSCCON<0>) is cleared.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
1. Primary
2. Secondary
3. Internal FRC
4. Internal LPRC
Byte Write “0x46” to OSCCON low
Byte Write “0x57” to OSCCON low
Byte Write is allowed for one instruction cycle. Write the
The user can switch between these functional groups,
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<3:0>
Configuration bits.
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
:
Byte Write “0x78” to OSCCON high
Byte Write “0x9A” to OSCCON high
Byte Write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
DS70141D-page 140
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 20-5. These bits
are used in software to determine the nature of the
Reset.
20.3 Reset
The dsPIC30F3010/3011 differentiates between various
kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during normal
operation)
A block diagram of the on-chip Reset circuit is shown in
Figure 20-2.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
g) Reset cause by trap lockup (TRAPR)
Internally generated Resets do not drive MCLR pin low.
h) Reset caused by illegal opcode, or by using an
uninitialized W register as an address pointer
(IOPUWR)
FIGURE 20-2:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
POR
VDD Rise
Detect
S
VDD
Brown-out
Reset
BOR
BOREN
R
Q
SYSRST
TRAP Conflict
Illegal Opcode/
Uninitialized W Register
The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected power-
up time-out (TPWRT) is applied. The TPWRT parameter
is based on device Configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
20.3.1
POR: POWER-ON RESET
A power-on event will generate an internal POR pulse
when a VDD rise is detected. The Reset pulse will occur
at the POR circuit threshold voltage (VPOR), which is
nominally 1.85V. The device supply voltage
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 141
dsPIC30F3010/3011
FIGURE 20-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
DS70141D-page 142
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FOS<1:0> and
FPR<3:0>). Furthermore, if an Oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
20.3.1.1
POR with Long Crystal Start-up Time
(with FSCM Enabled)
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially low fre-
quency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the POR timer and the PWRT have
expired:
Concurrently, the POR time-out (TPOR) and the PWRT
time-out (TPWRT) will be applied before the internal
Reset is released. If TPWRT = 0and a crystal oscillator
is being used, then a nominal delay of TFSCM = 100 μs
is applied. The total delay in this case is (TPOR +
TFSCM).
• The oscillator circuit has not begun to oscillate.
• The oscillator start-up timer has NOT expired (if a
crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is
used).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
The BOR status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit, if enabled,
will continue to operate while in Sleep or Idle modes
and will reset the device should VDD fall below the BOR
threshold voltage.
20.3.1.2
Operating without FSCM and PWRT
FIGURE 20-6:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device will exit
rapidly from Reset on power-up. If the clock source is
FRC, LPRC, EXTRC or EC, it will be active
immediately.
VDD
D
R
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
R1
MCLR
dsPIC30F
C
Note 1: External Power-on Reset circuit is
required only if the VDD power-up slope
is too slow. The diode D helps discharge
the capacitor quickly when VDD powers
down.
20.3.2
BOR: PROGRAMMABLE
BROWN-OUT RESET
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when
a brown-out condition occurs. Brown-out conditions
are generally caused by glitches on the AC mains
(i.e., missing portions of the AC cycle waveform due
to bad power transmission lines or voltage sags due
to excessive current draw when a large inductive load
is turned on).
2: R should be suitably chosen so as to
make sure that the voltage drop across
R does not violate the device’s electrical
specification.
3: R1 should be suitably chosen so as to
limit any current flowing into MCLR from
external capacitor C, in the event of
MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
The BOR module allows selection of one of the
following voltage trip points:
• 2.6V-2.71V
• 4.1V-4.4V
Note:
Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
• 4.58V-4.73V
Note:
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 143
dsPIC30F3010/3011
Table 20-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 20-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Program
Condition
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset
0x000000
0x000000
0x000000
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
0x000000
0
0
0
1
0
0
0
0
0
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
0x000000
0x000000
0x000000
PC + 2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Interrupt Wake-up from
Sleep
PC + 2(1)
Clock Failure Trap
Trap Reset
0x000004
0x000000
0x000000
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Illegal Operation Trap
Legend: u= unchanged, x= unknown
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 20-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 20-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Program
Condition
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset
0x000000
0x000000
0x000000
0
u
u
0
u
u
0
u
1
0
u
0
0
u
0
0
u
0
0
u
0
1
0
u
1
1
u
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
0x000000
u
u
0
1
0
0
0
u
u
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
0x000000
0x000000
0x000000
PC + 2
u
u
u
u
u
u
u
u
u
u
1
1
0
u
u
u
u
0
u
u
0
0
1
1
u
0
1
0
u
u
1
0
0
1
1
u
u
u
u
u
u
u
u
u
u
Interrupt Wake-up from
Sleep
PC + 2(1)
Clock Failure Trap
Trap Reset
0x000004
0x000000
0x000000
u
1
u
u
u
1
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Illegal Operation Reset
Legend: u= unchanged, x= unknown
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70141D-page 144
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
20.5.1
SLEEP MODE
20.4
Watchdog Timer (WDT)
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
20.4.1
WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer, which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
The fail-safe clock monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The Brown-out protection circuit and the Low-Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
20.4.2
ENABLING AND DISABLING THE
WDT
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register FWDT.
• any interrupt that is individually enabled and
meets the required priority level
• any Reset (POR, BOR and MCLR)
• WDT time-out
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit = 1. Any
device programmer capable of programming
dsPIC30F devices allows programming of this and
other Configuration bits.
On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry
into Sleep mode. When clock switching is enabled,
bits COSC<1:0> will determine the oscillator source
that will be used on wake-up. If clock switch is
disabled, then there is only one system clock.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
Note:
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<1:0>
and FPR<3:0> Configuration bits.
If a WDT times out during Sleep, the device will wake-
up. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.
If the clock source is an oscillator, the clock to the
device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, TPOR, TLOCK and TPWRT delays
are applied.
Setting FWDTEN = 0allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
If EC, FRC, LPRC or EXTRC oscillators are used, then
a delay of TPOR (~ 10 μs) is applied. This is the smallest
delay possible on wake-up from Sleep.
20.5 Power-Saving Modes
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to TPOR. PWRT delay and OST
timer delay are not applied. In order to have the small-
est possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
These are: Sleep and Idle.
The format of the PWRSAVinstruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 145
dsPIC30F3010/3011
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR.
The Sleep status bit in RCON register is set upon
wake-up.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle status bit in
RCON register is set upon wake-up.
Any Reset, other than POR, will set the Idle status bit.
On a POR, the Idle bit is cleared.
Note:
In spite of various delays applied (TPOR,
TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low frequency crys-
tals. In such cases), if FSCM is enabled,
then the device will detect this as a clock
failure and process the clock failure trap,
the FRC oscillator will be enabled, and the
user will have to re-enable the crystal
oscillator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable, and will
remain in Sleep until the oscillator clock
has started.
If the Watchdog Timer is enabled, then the processor
will wake-up from Idle mode upon WDT time-out. The
IDLE and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
20.6 Device Configuration Registers
The Configuration bits in each device configuration
register specify some of the device modes and are pro-
grammed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are four device
configuration registers available to the user:
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the SLEEP
status bit. In a POR, the Sleep bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
SLEEP and WDTO status bits are both set.
1. FOSC (0xF80000): Oscillator Configuration
register
2. FWDT (0xF80002): Watchdog Timer
Configuration register
20.5.2
IDLE MODE
3. FBORPOR (0xF80004): BOR and POR
Configuration register
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
4. FGS (0xF8000A): General Code Segment
Configuration register
Several peripherals have a control bit in each module,
that allows them to operate during Idle.
The placement of the Configuration bits is
automatically handled when you select the device in
your device programmer. The desired state of the
Configuration bits may be specified in the source code
(dependent on the language tool used), or through the
programming interface. After the device has been
programmed, the application software may read the
Configuration bit values through the table read
instructions. For additional information, please refer to
the programming specifications of the device.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• on any interrupt that is individually enabled (IE bit
is ‘1’) and meets the required priority level
• on any Reset (POR, BOR, MCLR)
• on WDT time-out
Note:
If the code protection configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages VDD ≥ 4.5V.
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAVinstruction.
DS70141D-page 146
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
In each case, the selected EMUD pin is the Emulation/
Debug Data line, and the EMUC pin is the Emulation/
Debug Clock line. These pins will interface to the
MPLAB ICD 2 module available from Microchip. The
selected pair of debug I/O pins is used by MPLAB
ICD 2 to send commands and receive responses, as
well as to send and receive data. To use the In-Circuit
Debugger function of the device, the design must
implement ICSP connections to MCLR, VDD, VSS,
PGC, PGD and the selected EMUDx/EMUCx pin pair.
20.7 In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. When the device has this feature enabled,
some of the resources are not available for general
use. These resources include the first 80 bytes of data
RAM and two I/O pins.
One of four pairs of debug I/O pins may be selected by
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.
This gives rise to two possibilities:
1. If EMUD/EMUC is selected as the debug I/O pin
pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are multi-
plexed with the PGD and PGC pin functions in
all dsPIC30F devices.
2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
EMUC3 is selected as the debug I/O pin pair,
then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 147
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP(1)
SFR
Name
Addr
.
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
RCON
0740 TRAPR IOPUWR BGST
—
EXTR
SWR SWDTEN WDTO SLEEP
LOCK CF
IDLE
—
BOR
POR
Depends on type of Reset.
OSCCON 0742 TUN3
TUN2
COSC<1:0>
TUN1 TUN0
NOSC<1:0>
POST<1:0>
—
LPOSCEN OSWEN Depends on configuration bits.
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual “(DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
TABLE 20-8: DEVICE CONFIGURATION REGISTER MAP(1)
File Name
Addr.
F80000
F80002
F80004
F8000A
Bits 23-16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
—
Bit 6
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FOSC
—
—
—
—
FCKSM<1:0>
—
—
—
—
—
FOS<1:0>
—
—
FPR<3:0>
FWDT
FWDTEN
—
—
—
—
—
—
—
HPOL
—
—
LPOL
—
—
—
FWPSA<1:0>
BORV<1:0>
FWPSB<3:0>
FBORPOR
FGS
MCLREN
—
—
—
—
PWMPIN
—
BOREN
—
—
—
—
—
—
FPWRT<1:0>
GCP GWRP
—
—
—
—
—
—
Legend: u= uninitialized bit; — = unimplemented bit
Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Not all peripherals, and therefore their bit positions, are available on this device.
dsPIC30F3010/3011
Most bit oriented instructions (including simple rotate/
shift instructions) have two operands:
21.0 INSTRUCTION SET SUMMARY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
• The W register (with or without an address modi-
fier) or File register (specified by the value of ‘Ws’
or ‘f’)
• The bit in the W register or File register
(specified by a literal value, or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
The dsPIC30F instruction set adds many
enhancements to the previous PIC® microcontroller
(MCU) instruction sets, while maintaining an easy
migration from PIC MCU instruction sets.
• A literal value to be loaded into a W register or
File register (specified by the value of ‘k’)
• The W register or File register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction.
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions may use some of the
following operands:
• DSP operations
• The accumulator (A or B) to be used (required
operand)
• Control operations
Table 21-1 shows the general symbols used in
describing the instructions.
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
The dsPIC30F instruction set summary in Table 21-2
lists all the instructions along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication, and may include:
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The accumulator to be used (required)
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The amount of shift, specified by a W register
‘Wn’ or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands:
• A program memory address
• The File register specified by the value ‘f’
• The mode of the table read and table write
instructions
• The destination, which could either be the File
register ‘f’ or the W0 register, which is denoted as
‘WREG’
All instructions are a single word, except for certain
double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 149
dsPIC30F3010/3011
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions, but take two or
three cycles. Certain instructions that involve skipping
over the subsequent instruction, require either two or
three cycles if the skip is performed, depending on
whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
Note:
For more details on the instruction set,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text
Means literal defined by “text“
Means “content of text“
Means “the location addressed by text”
Optional field or operation
Register bit field
(text)
[text]
{
}
<n:m>
.b
Byte mode selection
.d
Double-word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator Write Back Destination Address register ∈ {W13, [W13] + = 2}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU status bits: Carry, Digit Carry, Negative, Overflow, Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
lit14
lit16
lit23
None
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’
Field does not require an entry, may be blank
DSP status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
DS70141D-page 150
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wb
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wm*Wm
Dividend, Divisor working register pair (direct addressing)
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in File register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space Prefetch Address register for DSP instructions
∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd
Wy
X data space Prefetch Destination register for DSP instructions ∈ {W4..W7}
Y data space Prefetch Address register for DSP instructions
∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Wyd
Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7}
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 151
dsPIC30F3010/3011
TABLE 21-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
# of
cycle
s
Assembly
Mnemonic
# of
words
Status Flags
Affected
Assembly Syntax
Description
Add Accumulators
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
Acc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
Wd = Wb + Ws
Wd = Wb + lit5
16-bit Signed Add to Accumulator
f = f + WREG + (C)
2
3
4
ADDC
AND
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
f = f .AND. WREG
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
N,Z
N,Z
Wd = Wb .AND. lit5
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
N,Z
5
6
BCLR
BRA
None
Bit Clear Ws
None
Branch if Carry
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
Branch if unsigned less than
Branch if Negative
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if accumulator A overflow
Branch if accumulator B overflow
Branch if Overflow
Branch if accumulator A saturated
Branch if accumulator B saturated
Branch Unconditionally
Branch if Zero
2
None
Z,Expr
1 (2) None
Wn
Computed Branch
2
1
1
1
1
1
1
None
None
None
None
None
None
None
7
8
9
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
Bit Set Ws
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
Ws,Wb
BTG
f,#bit4
Ws,#bit4
Bit Toggle Ws
DS70141D-page 152
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
cycle
s
Assembly
Mnemonic
# of
words
Status Flags
Affected
Assembly Syntax
Description
Bit Test f, Skip if Clear
10
11
12
13
BTSC
BTSS
BTST
BTSTS
BTSC
BTSC
BTSS
BTSS
f,#bit4
1
1
1
1
1
(2 or
3)
None
None
None
None
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
(2 or
3)
1
(2 or
3)
Bit Test Ws, Skip if Set
1
(2 or
3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
C
Ws,Wb
Z
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb - Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb - Ws - C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ≠
1
1
1
1
1
(2 or
3)
None
None
None
None
1
(2 or
3)
1
(2 or
3)
1
(2 or
3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
f = f -1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f -1
DEC
Wd = Ws - 1
27
28
DEC2
DISI
DEC2
DEC2
DEC2
DISI
f = f -2
f,WREG
Ws,Wd
#lit14
WREG = f -2
Wd = Ws - 2
Disable Interrupts for k instruction cycles
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 153
dsPIC30F3010/3011
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
cycle
s
Assembly
Mnemonic
# of
words
Status Flags
Affected
Assembly Syntax
Description
29
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
Wm,Wn
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC+Expr, lit14+1 times
Do code to PC+Expr, (Wn)+1 times
Euclidean Distance ( no accumulate)
1
1
1
1
1
2
2
1
18
18
18
18
18
2
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
None
Wm,Wn
Wm,Wn
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
DO
2
None
32
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link frame pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
f
f = Logical Right Shift f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
None
None
None
None
N,Z
MOV.b
MOV
MOV
Wso,Wdo
Move Ws to Wd
MOV
WREG,f
Move WREG to f
MOV.D
MOV.D
MOVSAC
MPY
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
Move Double from Ws to W(nd+1):W(nd)
Pre-fetch and store accumulator
Multiply Wm by Wn to Accumulator
None
None
None
Ws,Wnd
47
48
MOVSAC
MPY
Acc,Wx,Wxd,Wy,Wyd,AWB
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
49
50
MPY.N
MSC
MPY.N
MSC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator
1
1
1
1
None
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator
AWB
OA,OB,OAB,
SA,SB,SAB
DS70141D-page 154
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
cycle
s
Assembly
Mnemonic
# of
words
Status Flags
Affected
Assembly Syntax
Description
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * signed(Ws)
{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
52
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from top-of-stack (TOS)
Pop from top-of-stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from top-of-stack (TOS) to
W(nd):W(nd+1)
None
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
2
1
1
1
All
55
PUSH
f
Push f to top-of-stack (TOS)
Push Wso to top-of-stack (TOS)
Push W(ns):W(ns+1) to top-of-stack (TOS)
Push Shadow Registers
None
None
None
None
WDTO,Sleep
None
None
None
None
None
Wso
Wns
56
57
PWRSAV
RCALL
#lit1
Expr
Go into Sleep or Idle mode
Relative Call
Wn
Computed Call
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14+1 times
Repeat Next Instruction (Wn)+1 times
Software device Reset
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
Return from interrupt
3 (2) None
3 (2) None
3 (2) None
#lit10,Wn
Return with literal in Wn
Return from Subroutine
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,N,Z
C,N,Z
C,N,Z
N,Z
RLC
f,WREG
RLC
Ws,Wd
64
65
66
67
RLNC
RRC
RLNC
RLNC
RLNC
RRC
f
f,WREG
N,Z
Ws,Wd
N,Z
f
C,N,Z
C,N,Z
C,N,Z
N,Z
RRC
f,WREG
RRC
Ws,Wd
RRNC
SAC
RRNC
RRNC
RRNC
SAC
f
f,WREG
N,Z
Ws,Wd
N,Z
Acc,#Slit4,Wdo
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = sign extended Ws
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
f = 0xFFFF
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 155
dsPIC30F3010/3011
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
cycle
s
Assembly
Mnemonic
# of
words
Status Flags
Affected
Assembly Syntax
Description
71
SL
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
WREG = Left Shift f
Ws,Wd
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
72
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f - WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f - WREG
Wn = Wn - lit10
SUB
SUB
Wd = Wb - Ws
SUB
Wd = Wb - lit5
73
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
f = f - WREG - (C)
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f - WREG - (C)
Wn = Wn - lit10 - (C)
Wd = Wb - Ws - (C)
Wd = Wb - lit5 - (C)
f = WREG - f
74
75
76
SUBR
SUBBR
SWAP
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG - f
Wd = Ws - Wb
Wd = lit5 - Wb
f = WREG - f - (C)
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
WREG = WREG -f - (C)
Wd = Ws - Wb - (C)
Wd = lit5 - Wb - (C)
Wn = nibble swap Wn
Wn = byte swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink frame pointer
f = f .XOR. WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
Wnd = Zero-Extend Ws
Wn
None
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
None
XOR
f
N,Z
XOR
f,WREG
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
N,Z
83
ZE
ZE
C,Z,N
DS70141D-page 156
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
22.1 MPLAB Integrated Development
Environment Software
22.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
DS70141D-page 157
dsPIC30F3010/3011
22.2 MPASM Assembler
22.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
22.6 MPLAB SIM Software Simulator
22.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 family of microcontrollers and the
dsPIC30, dsPIC33 and PIC24 family of digital signal
controllers. These compilers provide powerful integra-
tion capabilities, superior code optimization and ease
of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
22.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS70141D-page 158
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
22.7 MPLAB ICE 2000
High-Performance
22.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers. Software control of the MPLAB ICE 2000
In-Circuit Emulator is advanced by the MPLAB Inte-
grated Development Environment, which allows edit-
ing, building, downloading and source debugging from
a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
22.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
22.8 MPLAB ICE 4000
High-Performance
In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to
provide the product development engineer with a
complete microcontroller design tool set for high-end
PIC MCUs and dsPIC DSCs. Software control of the
MPLAB ICE 4000 In-Circuit Emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2007 Microchip Technology Inc.
DS70141D-page 159
dsPIC30F3010/3011
22.11 PICSTART Plus Development
Programmer
22.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
22.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer with an easy-to-use interface for pro-
gramming many of Microchip’s baseline, mid-range
and PIC18F families of Flash memory microcontrollers.
The PICkit 2 Starter Kit includes a prototyping develop-
ment board, twelve sequential lessons, software and
HI-TECH’s PICC™ Lite C compiler, and is designed to
help get up to speed quickly using PIC® micro-
controllers. The kit provides everything needed to
program, evaluate and develop applications using
Microchip’s powerful, mid-range Flash memory family
of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS70141D-page 160
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
23.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to dsPIC30F Family Reference Manual
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1)..................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS ....................................................................................................... 0V to +13.25V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 2)................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Voltage spikes below Vss at the MCLR/Vpp pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/Vpp pin, rather
than pulling this pin directly to Vss.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 23-2.
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
23.1 DC Characteristics
TABLE 23-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
Temp Range
dsPIC30F301x-30I
dsPIC30F301x-20E
4.5-5.5V
4.5-5.5V
3.0-3.6V
3.0-3.6V
2.5-3.0V
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
30
—
20
—
10
—
20
—
15
—
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 161
dsPIC30F3010/3011
TABLE 23-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
dsPIC30F301x-30I
Operating Junction Temperature Range
Operating Ambient Temperature Range
dsPIC30F301x-20E
TJ
TA
-40
-40
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
+150
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD × (IDD
–
)
∑ IOH
PD
PINT + PI/O
W
I/O Pin power dissipation:
PI/O
=
({
} ×
) +
IOH
(
∑
)
VOL × IOL
VDD – VOH
∑
Maximum Allowed Power Dissipation
PDMAX
(TJ - TA) / θJA
W
TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 28-pin SPDIP (SP)
Package Thermal Resistance, 28-pin SOIC (SO)
Package Thermal Resistance, 40-pin DIP
θJA
θJA
θJA
θJA
θJA
42
49
37
45
28
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
Package Thermal Resistance, 44-pin TQFP (10x10x1mm)
Package Thermal Resistance, 44-pin QFN
Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.
TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1) Max Units
Conditions
Operating Voltage(2)
DC10
DC11
DC12
DC16
VDD
VDD
VDR
VPOR
Supply Voltage
2.5
3.0
—
—
—
5.5
5.5
—
V
V
V
V
Industrial temperature
Extended temperature
Supply Voltage
RAM Data Retention Voltage(3)
1.5
VSS
VDD Start Voltage
to ensure internal
—
—
Power-on Reset signal
DC17
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms 0-5V in 0.1 sec
0-3V in 60 ms
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: This is the limit to which VDD can be lowered without losing RAM data.
DS70141D-page 162
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Operating Current (IDD)(2)
DC31a
DC31b
DC31c
DC31e
DC31f
DC31g
DC30a
DC30b
DC30c
DC30e
DC30f
DC30g
DC23a
DC23b
DC23c
DC23e
DC23f
DC23g
DC24a
DC24b
DC24c
DC24e
DC24f
DC24g
DC27a
DC27b
DC27d
DC27e
DC27f
DC29a
DC29b
1.4
1.4
2.5
2.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
1.4
2.5
0.128 MIPS
LPRC ( 512 kHz)
3.0
4.5
2.8
4.5
2.8
4.5
3.2
5.0
3.3
5.0
3.3V
5V
3.3
5.0
(1.8 MIPS)
FRC (7.37MHz)
6.0
9.0
5.9
9.0
5.9
9.0
10.0
10.0
11.0
17.0
17.0
18.0
24.0
25.0
25.0
41.0
41.0
41.0
46.0
46.0
76.0
76.0
76.0
109.0
108.0
17.0
17.0
17.0
27.0
27.0
27.0
38.0
38.0
38.0
62.0
62.0
62.0
70.0
70.0
115.0
115.0
115.0
155.0
155.0
3.3V
5V
4 MIPS
3.3V
10 MIPS
5V
3.3V
5V
20 MIPS
30 MIPS
5V
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 163
dsPIC30F3010/3011
TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1,2)
No.
Max
Units
Conditions
Operating Current (IDD)
DC51a
DC51b
DC51c
DC51e
DC51f
DC51g
DC50a
DC50b
DC50c
DC50e
DC50f
DC50g
DC43a
DC43b
DC43c
DC43e
DC43f
DC43g
DC44a
DC44b
DC44c
DC44e
DC44f
DC44g
DC47a
DC47b
DC47d
DC47e
DC47f
DC49a
DC49b
1.1
1.1
1.8
1.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
1.1
1.8
0.128 MIPS
LPRC (512 kHz)
2.6
4.0
2.4
4.0
2.3
4.0
3.2
5.0
3.3
5.0
3.3V
5V
3.3
5.0
(1.8 MIPS)
FRC (7.37MHz)
6.0
9.0
5.9
9.0
5.9
9.0
6.0
9.3
6.1
9.3
3.3V
5V
6.2
9.3
4 MIPS
11.0
11.0
11.0
13.0
14.0
14.0
23.0
23.0
23.0
25.0
26.0
43.0
43.0
43.0
62.0
63.0
17.0
17.0
17.0
21.0
21.0
21.0
35.0
35.0
35.0
40.0
40.0
60.0
60.0
60.0
80.0
80.0
3.3V
10 MIPS
5V
3.3V
5V
20 MIPS
30 MIPS
5V
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.
DS70141D-page 164
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Power Down Current (IPD)(2)
DC60a
DC60b
DC60c
DC60e
DC60f
DC60g
DC61a
DC61b
DC61c
DC61e
DC61f
DC61g
DC62a
DC62b
DC62c
DC62e
DC62f
DC62g
DC63a
DC63b
DC63c
DC63e
DC63f
DC63g
0.3
1.0
14.0
27.0
55.0
20.0
40.0
90.0
12.0
12.0
12.0
21.0
21.0
21.0
10.0
10.0
10.0
15.0
15.0
15.0
57.0
57.0
57.0
65.0
65.0
65.0
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
3.3V
5V
12.0
0.5
Base Power Down Current
2.0
17.0
8.0
8.0
3.3V
5V
8.0
(3)
Watchdog Timer Current: ΔIWDT
14.0
14.0
14.0
4.0
5.0
3.3V
5V
4.0
Timer 1 w/32 kHz Crystal: ΔITI32(3)
4.0
6.0
5.0
33.0
37.0
38.0
38.0
41.0
43.0
3.3V
5V
(3)
BOR On: ΔIBOR
Note 1: Parameters are for design guidance only and are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: These values represent the difference between the Base Power-Down Current and the Power-Down
current with the specified peripheral enabled during Sleep.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 165
dsPIC30F3010/3011
TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
VIL
DI10
I/O pins:
with Schmitt Trigger buffer
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
V
DI15
DI16
DI17
DI18
DI19
MCLR
OSC1 (in XT, HS and LP modes)
OSC1 (in RC mode)(3)
SDA, SCL
SMbus disabled
SDA, SCL
SMbus enabled
VIH
Input High Voltage(2)
DI20
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
DI25
DI26
DI27
DI28
DI29
MCLR
OSC1 (in XT, HS and LP modes) 0.7 VDD
OSC1 (in RC mode)(3)
0.9 VDD
0.7 VDD
0.8 VDD
SDA, SCL
SMbus disabled
SMbus enabled
SDA, SCL
ICNPU
IIL
CNXX Pull-up Current(2)
DI30
50
250
400
μA VDD = 5V, VPIN = VSS
Input Leakage Current(2)(4)(5)
DI50
DI51
I/O ports
—
—
0.01
0.50
±1
—
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
Analog input pins
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55
DI56
MCLR
OSC1
—
—
0.05
0.05
±5
±5
μA
VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD, XT, HS
and LP Osc mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
5: Negative current is defined as current sourced by the pin.
DS70141D-page 166
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1) Max Units
Conditions
VOL
Output Low Voltage(2)
DO10
DO16
I/O ports
—
—
—
—
—
—
—
—
0.6
TBD
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 5V
IOL = 2.0 mA, VDD = 3V
IOL = 1.6 mA, VDD = 5V
IOL = 2.0 mA, VDD = 3V
OSC2/CLKO
(RC or EC Osc mode)
Output High Voltage(2)
I/O ports
TBD
VOH
DO20
DO26
VDD – 0.7
TBD
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 5V
IOH = -2.0 mA, VDD = 3V
IOH = -1.3 mA, VDD = 5V
IOH = -2.0 mA, VDD = 3V
OSC2/CLKO
VDD – 0.7
TBD
(RC or EC Osc mode)
Capacitive Loading Specs
on Output Pins(2)
DO50 COSC2
OSC2/SOSC2 pin
—
—
15
pF In XTL, XT, HS and LP modes
when external clock is used to
drive OSC1.
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCL, SDA
—
—
—
—
50
pF RC or EC Osc mode
pF In I2C™ mode
400
Legend: TBD = To Be Determined
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
FIGURE 23-1:
BROWN-OUT RESET CHARACTERISTICS
VDD
(Device not in Brown-out Reset)
BO15
BO10
(Device in Brown-out Reset)
Reset (due to BOR)
Power-Up Time-out
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 167
dsPIC30F3010/3011
TABLE 23-10: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min Typ(1) Max Units
Conditions
BO10
BO15
VBOR
BOR Voltage(2) on
VDD transition high to
low
BORV = 11(3)
—
—
—
V
Not in operating
range
BORV = 10
BORV = 01
BORV = 00
2.6
4.1
4.58
—
—
—
—
5
2.71
4.4
V
V
4.73
—
V
VBHYS
mV
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: ‘11’ values not in usable operating range.
TABLE 23-11: DC CHARACTERISTICS: PROGRAM AND EEPROM
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min Typ(1) Max Units
Conditions
Data EEPROM Memory(2)
Byte Endurance
D120
D121
ED
100K
VMIN
1M
—
—
E/W -40°C ≤ TA ≤ +85°C
VDRW
VDD for Read/Write
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122
D123
TDEW
Erase/Write Cycle Time
Characteristic Retention
—
2
—
—
ms
TRETD
40
100
Year Provided no other specifications
are violated
D124
IDEW
IDD During Programming
Program Flash Memory(2)
Cell Endurance
—
10
30
mA Row Erase
D130
D131
EP
10K
100K
—
—
E/W -40°C ≤ TA ≤ +85°C
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
D133
D134
D135
VEB
VDD for Bulk Erase
4.5
3.0
—
—
—
5.5
5.5
—
V
V
VPEW
TPEW
TRETD
VDD for Erase/Write
Erase/Write Cycle Time
Characteristic Retention
2
ms
40
100
—
Year Provided no other specifications
are violated
D136
D137
D138
TEB
IPEW
IEB
ICSP Block Erase Time
IDD During Programming
IDD During Programming
—
—
—
4
—
30
30
ms
10
10
mA Row Erase
mA Bulk Erase
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
2: These parameters are characterized but not tested in manufacturing.
DS70141D-page 168
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
23.2 AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 23-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in DC Spec Section 23.1 "DC
Characteristics".
FIGURE 23-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 - for all pins except OSC2
VDD/2
Load Condition 2 - for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS
5 pF for OSC2 output
FIGURE 23-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
OS20
OS30 OS30
OS25
OS31 OS31
OS40
OS41
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 169
dsPIC30F3010/3011
TABLE 23-13: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10
FOSC
External CLKI Frequency(2)
(External clocks allowed only
in EC mode)
DC
4
4
—
—
—
—
40
10
10
7.5
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
4
Oscillator Frequency(2)
DC
0.4
4
4
4
—
—
—
—
—
—
—
—
7.37
512
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
10
10
10
7.5
25
33
—
—
4
10
31
—
—
LP
MHz
kHz
FRC internal
LPRC internal
OS20
TOSC
TOSC = 1/FOSC
—
—
—
—
See parameter OS10
for FOSC value
OS25 TCY
Instruction Cycle Time(2)(3)
External Clock(2) in (OSC1)
High or Low Time
33
—
—
DC
—
ns
ns
See Table 23-16
EC
OS30 TosL,
TosH
.45 x
TOSC
OS31 TosR,
TosF
External Clock(2) in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40 TckR
OS41 TckF
CLKO Rise Time(2)(4)
CLKO Fall Time(2)(4)
—
—
—
—
—
—
ns
ns
See parameter D031
See parameter D032
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
4: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is
low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS70141D-page 170
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OS50
FPLLI
PLL Input Frequency Range(2)
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
10
10
MHz EC with 4x PLL
MHz EC with 8x PLL
MHz EC with 16x PLL
MHz XT with 4x PLL
MHz XT with 8x PLL
MHz XT with 16x PLL
MHz HS/2 with 4x PLL
MHz HS/2 with 8x PLL
MHz HS/2 with 16x PLL
7.5(4)
10
10
4
7.5(4)
10
5(3)
5(3)
5(3)
4
10
7.5(4)
8.33(3) MHz HS/3 with 4x PLL
4
4
8.33(3) MHz HS/3 with 8x PLL
7.5(4)
120
MHz HS/3 with 16x PLL
OS51
OS52
FSYS
TLOC
On-Chip PLL Output(2)
16
—
MHz EC, XT, HS/2, HS/3
modes with PLL
PLL Start-up Time (Lock Time)
—
20
50
μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Limited by oscillator frequency range.
4: Limited by device operating frequency range.
TABLE 23-15: PLL JITTER
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
AC CHARACTERISTICS
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
-40°C ≤ TA ≤ +85°C
OS61
x4 PLL
—
—
—
—
—
—
—
—
—
—
—
0.251 0.413
0.251 0.413
%
%
%
%
%
%
%
%
%
%
%
VDD = 3.0 to 3.6V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 4.5 to 5.5V
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
0.256
0.256
0.47
0.47
x8 PLL
0.355 0.584
0.355 0.584
0.362 0.664
0.362 0.664
x16 PLL
0.67
0.92
0.632 0.956
0.632 0.956
Note 1: These parameters are characterized but not tested in manufacturing.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 171
dsPIC30F3010/3011
TABLE 23-16: INTERNAL CLOCK TIMING EXAMPLES
Clock
FOSC
MIPS(3)
MIPS(3)
w PLL x4
MIPS(3)
w PLL x8
MIPS(3)
w PLL x16
Oscillator
Mode
TCY (μsec)(2)
(MHz)(1)
w/o PLL
EC
XT
0.200
4
20.0
1.0
0.05
1.0
—
4.0
10.0
—
—
8.0
20.0
—
—
16.0
—
10
25
4
0.4
2.5
0.16
1.0
6.25
1.0
—
4.0
10.0
8.0
20.0
16.0
—
10
0.4
2.5
Note 1: Assumption: Oscillator Postscaler is divide by 1.
2: Instruction Execution Cycle Time: TCY = 1/MIPS.
3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 since there are 4 Q clocks per instruction cycle.
DS70141D-page 172
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dsPIC30F3010/3011
TABLE 23-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS(2)
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Characteristic
No.
Min
Typ
Max
Units
Conditions
Internal FRC Jitter @ FRC Freq. = 7.37 MHz(1)
OS62
FRC
—
—
—
—
—
—
—
+0.04 +0.16
+0.07 +0.23
+0.31 +0.62
+0.34 +0.77
+0.44 +0.87
+0.48 +1.08
+0.71 +1.23
%
%
%
%
%
%
%
-40°C ≤ TA ≤ +85°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +125°C
FRC with 4x PLL
FRC with 8x PLL
FRC with 16x PLL
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
FRC +0.5
Internal FRC Drift @ FRC Freq. = 7.37 MHz(1)
OS63
OS64
—
—
%
-40°C ≤ TA ≤ +125°C
VDD = 3.0-5.5V
-0.7
-0.7
-0.7
-0.7
—
—
—
—
0.5
0.7
0.5
0.7
%
%
%
%
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.
2: Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift
percentages.
TABLE 23-18: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ Freq. = 512 kHz(1)
OS65
-35
—
+35
%
—
Note 1: Change of LPRC frequency as VDD changes.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 173
dsPIC30F3010/3011
FIGURE 23-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)(2)(3)
Min
Typ(4)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port output rise time
—
—
7
7
20
20
—
—
ns
ns
ns
ns
—
—
—
—
Port output fall time
INTx pin high or low time (output)
CNx high or low time (input)
20
—
—
DI40
2 TCY
Note 1: These parameters are asynchronous events not related to any internal clock edges.
2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.
3: These parameters are characterized but not tested in manufacturing.
4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
DS70141D-page 174
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dsPIC30F3010/3011
FIGURE 23-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TmcL
MCLR Pulse Width (low)
Power-up Timer Period
-40°C to +85°C
2
—
—
μs
ms
TPWRT
3
4
6
-40°C to +85°C
12
50
16
64
22
90
User programmable
SY12
SY13
TPOR
TIOZ
Power On Reset Delay
3
10
30
μs
μs
-40°C to +85°C
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
0.8
1.0
SY20
TWDT1
Watchdog Timer Time-out Period
(No Prescaler)
1.4
2.1
2.8
ms
VDD = 5V, -40°C to +85°C
TWDT2
TBOR
TOST
1.4
100
—
2.1
—
2.8
—
ms
μs
—
VDD = 3V, -40°C to +85°C
VDD ≤ VBOR (D034)
TOSC = OSC1 period
-40°C to +85°C
SY25
SY30
SY35
Brown-out Reset Pulse Width(3)
Oscillation Start-up Timer Period
Fail-Safe Clock Monitor Delay
1024 TOSC
500
—
TFSCM
—
900
μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
3: Refer to Figure 23-1 and Table 23-10 for BOR.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 175
dsPIC30F3010/3011
FIGURE 23-6:
BAND GAP START-UP TIME CHARACTERISTICS
VBGAP
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
Note: Band gap is enabled when FBORPOR<7> is set.
TABLE 23-21: BAND GAP START-UP TIME REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Band Gap Start-up Time
Min Typ(2) Max Units
Conditions
SY40
TBGAP
—
40 65
μs Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON<13> Status bit
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
DS70141D-page 176
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dsPIC30F3010/3011
FIGURE 23-7:
TIMER 1, 2, 3, 4 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRX
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 10
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale value
(1, 8, 64, 256)
(TCY + 40)/N
Asynchronous
20
—
—
—
ns
OS60
TA20
Ft1
SOSC1/T1CK oscillator input
DC
50
kHz
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5
TCY
—
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 177
dsPIC30F3010/3011
TABLE 23-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max
Units
Conditions
TB10
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
TB11
TB15
TtxL
TtxP
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
Must also meet
parameter TB15
Synchronous,
with prescaler
10
TxCK Input Period Synchronous,
no prescaler
TCY + 10
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5 TCY
—
TABLE 23-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max Units
Conditions
TC10
TC11
TC15
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns
ns
ns
Must also meet
parameter TC15
TtxL
TtxP
0.5 TCY + 20
TCY + 10
—
—
Must also meet
parameter TC15
TxCK Input Period Synchronous,
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5
TCY
—
DS70141D-page 178
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 23-8:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 23-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10 TtQH
TQ11 TtQL
TQ15 TtQP
TQCK High Time Synchronous,
with prescaler
TCY + 20
—
ns
Must also meet
parameter TQ15
TQCK Low Time
Synchronous,
with prescaler
TCY + 20
—
—
ns
ns
—
Must also meet
parameter TQ15
TQCP Input
Period
Synchronous, 2 * TCY + 40
with prescaler
—
TQ20
TCKEXTMRL Delay from External TQCK Clock
Edge to Timer Increment
0.5 TCY
1.5
TCY
—
Note 1: These parameters are characterized but not tested in manufacturing.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 179
dsPIC30F3010/3011
FIGURE 23-9:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICX
IC10
IC11
IC15
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
ICx Input Period
(2 TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 23-10:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
DS70141D-page 180
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 23-11:
OCFA/OCFB
OCx
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OC15
TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15 TFD
Fault Input to PWM I/O
Change
—
—
50
ns
—
—
OC20 TFLT
Fault Input Pulse Width
50
—
—
ns
Note 1: These parameters are characterized but not tested in manufacturing.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 181
dsPIC30F3010/3011
FIGURE 23-12:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA/B
PWMx
MP20
FIGURE 23-13:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
See parameter D032
See parameter D031
MP10
MP11
TFPWM
TRPWM
PWM Output Fall Time
—
—
—
—
—
—
ns
ns
PWM Output Rise
Time
TFD
TFH
Fault Input ↓ to PWM
—
—
—
50
—
ns
ns
—
—
MP20
MP30
I/O Change
Minimum Pulse Width
50
Note 1: These parameters are characterized but not tested in manufacturing.
DS70141D-page 182
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© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 23-14:
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ31
TQ40
TQ30
TQ35
QEB
Internal
TABLE 23-30: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Typ(2)
Max
Units
Conditions
TQ30
TQ31
TQ35
TQ36
TQ40
TQUL
Quadrature Input Low Time
Quadrature Input High Time
Quadrature Input Period
Quadrature Phase Period
6 TCY
6 TCY
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
TQUH
TQUIN
TQUP
TQUFL
12 TCY
3 TCY
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ41
TQUFH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
Note 1: These parameters are characterized but not tested in manufacturing.
2: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. “Quadrature Encoder
Interface (QEI)” in the “dsPIC30F Family Reference Manual” (DS70046).
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 183
dsPIC30F3010/3011
FIGURE 23-15:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position
TABLE 23-31: QEI INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
TQ50
TQ51
TQ55
TqIL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TqiH
Tqidxr
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
3 TCY
—
—
ns
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
Index Pulse Recognized to Position
Counter Reset (Ungated Index)
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Alignment of Index Pulses to QEA and QEB is shown for position counter reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB), but
Index Pulse recognition occurs on falling edge.
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dsPIC30F3010/3011
FIGURE 23-16:
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
BIT14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb IN
SP40
LSb IN
BIT14 - - - -1
SP41
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
SP10
SP11
SP20
TscL
TscH
TscF
SCKX Output Low Time(2)
SCKX Output High Time(2)
SCKX Output Fall Time(3)
TCY / 2
TCY / 2
—
—
—
—
—
—
—
ns
ns
ns
—
—
See parameter
D032
SP21
SP30
SP31
SP35
SP40
SP41
TscR
TdoF
TdoR
SCKX Output Rise Time(3)
—
—
—
—
20
20
—
—
—
—
—
—
—
—
—
30
—
—
ns
ns
ns
ns
ns
ns
See parameter
D031
SDOX Data Output Fall Time(3)
SDOX Data Output Rise Time(3)
See parameter
D032
See parameter
D031
TscH2doV, SDOX Data Output Valid after
TscL2doV SCKX Edge
—
—
—
TdiV2scH, Setup Time of SDIX Data Input
TdiV2scL
TscH2diL, Hold Time of SDIX Data Input
TscL2diL to SCKX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
to SCKX Edge
2: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPI pins.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 185
dsPIC30F3010/3011
FIGURE 23-17:
SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKX
(CKP = 1)
SP35
LSb
MSb
SP40
BIT14 - - - - - -1
SDOX
SDIX
SP30,SP31
BIT14 - - - -1
MSb IN
SP41
LSb IN
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ
Max
Units
Conditions
SP10
SP11
SP20
SCKX output low time(2)
SCKX output high time(2)
SCKX output fall time(3)
TCY / 2
TCY / 2
—
—
—
—
—
—
—
ns
ns
ns
—
—
TscH
TscF
See parameter
D032
SP21
SP30
SP31
SP35
SP36
SP40
SP41
TscR
TdoF
TdoR
SCKX output rise time(3)
—
—
—
—
30
20
20
—
—
—
—
—
—
—
—
—
—
30
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter
D031
SDOX data output fall time(3)
SDOX data output rise time(3)
See parameter
D032
See parameter
D031
TscH2doV, SDOX data output valid after
TscL2doV SCKX edge
—
—
—
—
TdoV2sc,
TdoV2scL first SCKX edge
SDOX data output setup to
TdiV2scH, Setup time of SDIX data input
TdiV2scL
TscH2diL, Hold time of SDIX data input
TscL2diL to SCKX edge
Note 1: These parameters are characterized but not tested in manufacturing.
to SCKX edge
2: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not
violate this specification.
3: Assumes 50 pF load on all SPI pins.
DS70141D-page 186
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 23-18:
SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCK
(CKP =
X
0
)
)
SP71
SP70
SP72
SP73
SCK
(CKP =
X
1
SP73
LSb
SP72
SP35
MSb
BIT14 - - - - - -1
SDOX
SP51
SP30,SP31
BIT14 - - - -1
SDIX
MSb IN
SP41
LSb IN
SP40
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for
Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKX Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKX Input High Time
—
—
SCKX Input Fall Time(3)
SCKX Input Rise Time(3)
SDOX Data Output Fall Time(3)
SDOX Data Output Rise Time(3)
—
See D032
See D031
—
TscH2doV,
TscL2doV
SDOX Data Output Valid after
SCKX Edge
SP40
SP41
SP50
SP51
SP52
TdiV2scH,
TdiV2scL
Setup Time of SDIX Data Input
to SCKX Edge
20
20
—
—
—
—
—
—
—
—
50
—
ns
ns
ns
ns
ns
—
—
—
—
—
TscH2diL,
TscL2diL
Hold Time of SDIX Data Input
to SCKX Edge
TssL2scH,
TssL2scL
SSX↓ to SCKX↑ or SCKX↓ Input
120
TssH2doZ
SSX↑ to SDOX Output
10
High-Impedance(3)
TscH2ssH SSX after SCK Edge
TscL2ssH
1.5 TCY +40
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Assumes 50 pF load on all SPI pins.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 187
dsPIC30F3010/3011
FIGURE 23-19:
SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKX
(CKP = 1)
SP35
SP72
LSb
SP52
BIT14 - - - - - -1
MSb
SDOX
SDIX
SP30,SP31
BIT14 - - - -1
SP51
MSb IN
SP41
LSb IN
SP40
Note: Refer to Figure 23-2 for load conditions.
DS70141D-page 188
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TscL
TscH
TscF
TscR
TdoF
SP70
SP71
SP72
SP73
SP30
SCKX Input Low Time
30
30
—
—
—
—
—
10
10
—
—
—
25
25
—
ns
ns
ns
ns
ns
—
—
—
—
SCKX Input High Time
SCKX Input Fall Time(3)
SCKX Input Rise Time(3)
SDOX Data Output Fall Time(3)
See parameter
D032
SP31
SP35
SP40
SP41
SP50
SP51
SP52
SP60
TdoR
SDOX Data Output Rise Time(3)
—
—
—
—
—
—
—
—
—
—
30
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
ns
ns
See parameter
D031
TscH2doV, SDOX Data Output Valid after
TscL2doV SCKX Edge
—
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIX Data Input
TdiV2scL to SCKX Edge
20
TscH2diL, Hold Time of SDIX Data Input
TscL2diL
20
to SCKX Edge
TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input
TssL2scL
120
TssH2doZ SS↑ to SDOX Output
10
1.5 TCY + 40
—
High-Impedance(4)
TscH2ssH SSX↑ after SCKX Edge
TscL2ssH
TssL2doV SDOX Data Output Valid after
SSX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 189
dsPIC30F3010/3011
FIGURE 23-20:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
SDA
IM31
IM34
IM30
IM33
Stop
Condition
Start
Condition
Note: Refer to Figure 23-2 for load conditions.
FIGURE 23-21:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM33
IM25
SDA
In
IM45
IM40
IM40
SDA
Out
Note: Refer to Figure 23-2 for load conditions.
DS70141D-page 190
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
)
TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
—
SDA and SCL
Rise Time
—
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
—
250
100
TBD
0
TSU:DAT Data Input
Setup Time
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
TBD
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Hold Time
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
TBD
—
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
CB
Bus Capacitive Loading
400
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit (I2C)”
in the “dsPIC30F Family Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 191
dsPIC30F3010/3011
FIGURE 23-22:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
SDA
IS34
IS31
IS30
IS33
Stop
Condition
Start
Condition
FIGURE 23-23:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS33
IS25
SDA
In
IS45
IS40
IS40
SDA
Out
TABLE 23-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
—
μs
μs
Device must operate at a
minimum of 1.5 MHz
1.3
Device must operate at a
minimum of 10 MHz.
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
IS11
THI:SCL
Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
300
300
100
1000
300
300
μs
ns
ns
ns
ns
ns
ns
—
IS20
IS21
TF:SCL
TR:SCL
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
SDA and SCL
Rise Time
—
20 + 0.1 CB
—
CB is specified to be from
10 to 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
DS70141D-page 192
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max Units
Conditions
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TSU:DAT Data Input
100 kHz mode
250
100
100
0
—
—
—
—
0.9
0.3
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
Setup Time
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
THD:DAT Data Input
Hold Time
—
0
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for repeated
Start condition
THD:STA Start Condition
Hold Time
After this period the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
—
—
—
THD:STO Stop Condition
Hold Time
TAA:SCL
Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive
Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 193
dsPIC30F3010/3011
TABLE 23-38: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
Greater of
VDD - 0.3
or 2.7
—
Lesser of
VDD + 0.3
or 5.5
V
V
—
—
Vss - 0.3
—
VSS + 0.3
Reference Inputs
AD05
AD06
AD07
AD08
VREFH
VREFL
VREF
IREF
Reference Voltage High
Reference Voltage Low
AVss+2.7
AVss
—
—
—
AVDD
V
V
V
—
—
—
AVDD - 2.7
AVDD + 0.3
Absolute Reference Voltage AVss - 0.3
Current Drain
—
200
.001
300
3
μA A/D operating
μA A/D off
Analog Input
AD10
AD12
VINH-VINL Full-Scale Input Span
VREFL
VREFH
±0.244
V
—
—
Leakage Current
—
—
—
±0.001
μA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
Source Impedance = 5 kΩ
AD13
AD17
—
Leakage Current
±0.001
—
±0.244
5K
μA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Source Impedance = 5 kΩ
RIN
Recommended Impedance
Of Analog Voltage Source
Ω
—
DC Accuracy(2)
10 data bits
AD20 Nr
AD21 INL
Resolution
bits
—
Integral Nonlinearity
—
—
—
—
+1
+1
±1
±1
±1
±1
±5
±5
±1
±1
±1
±1
±6
±6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD21A INL
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Gain Error
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22 DNL
AD22A DNL
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23
GERR
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD23A GERR
Gain Error
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Note 1: These parameters are characterized but not tested in manufacturing.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS70141D-page 194
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
TABLE 23-38: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Offset Error(2)
Min.
Typ
Max.
Units
Conditions
AD24
EOFF
±1
±2
±3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD24A EOFF
Offset Error(2)
Monotonicity(3)
±1
—
±2
—
±3
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25
—
—
Guaranteed
Dynamic Performance
AD30 THD
Total Harmonic Distortion
—
—
-64
57
-67
58
dB
dB
—
—
AD31 SINAD
Signal to Noise and
Distortion
AD32 SFDR
Spurious Free Dynamic
Range
—
67
71
dB
—
AD33
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
500
—
kHz
bits
—
—
AD34 ENOB
9.29
9.41
Note 1: These parameters are characterized but not tested in manufacturing.
2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 195
dsPIC30F3010/3011
FIGURE 23-24:
10-BIT HIGH-SPEED ADC TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)
AD50
ADCLK
Instruction
Execution
SET SAMP
CLEAR SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
TSAMP
AD55
AD55
DONE
ADIF
ADRES(0)
ADRES(1)
1
2
3
4
5
6
7
8
5
6
7
8
— Software sets ADCON. SAMP to start sampling.
— Sampling starts after discharge period.
1
2
TSAMP is described in the “dsPIC30F Family Reference Manual”, (DS70046), Section 17, “10-bit A/D Converter”.
— Software clears ADCON. SAMP to start conversion.
— Sampling ends, conversion sequence starts.
— Convert bit 9.
3
4
5
6
8
9
— Convert bit 8.
— Convert bit 0.
— One TAD for end of conversion.
DS70141D-page 196
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
FIGURE 23-25:
10-BIT HIGH-SPEED ADC TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)
AD50
ADCLK
Instruction
Execution
SET ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
TSAMP
AD55
AD55
TCONV
DONE
ADIF
ADRES(0)
ADRES(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
— Software sets ADCON. ADON to start AD operation.
— Convert bit 0.
5
1
2
— Sampling starts after discharge period.
— One TAD for end of conversion.
— Begin conversion of next channel
6
7
8
TSAMP is described in the “dsPIC30F
Family Reference Manual”, (DS70046),
Section 17, “10-bit A/D Converter”.
— Convert bit 9.
— Sample for time specified by SAMC.
3
4
TSAMP is described in the “dsPIC30F
Family Reference Manual”, (DS70046),
Section 17, “10-bit A/D Converter”.
— Convert bit 8.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 197
dsPIC30F3010/3011
TABLE 23-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50 TAD
AD51 tRC
A/D Clock Period
A/D Internal RC Oscillator Period
—
84
900
—
ns
ns
See Table 20-2(1)
700
1100
—
Conversion Rate
AD55 tCONV
AD56 FCNV
Conversion Time
Throughput Rate
—
—
—
12 TAD
—
—
—
—
—
1.0
Msps See Table 20-2(1)
AD57 TSAMP Sample Time
1 TAD
—
See Table 20-2(1)
Timing Parameters
AD60 tPCS
AD61 tPSS
AD62 tCSS
AD63 tDPU
Conversion Start from Sample
Trigger
—
0.5 TAD
—
1.0 TAD
—
1.5 TAD
—
—
—
—
μs
—
—
—
—
Sample Start from Setting
Sample (SAMP) Bit
—
0.5 TAD
20
Conversion Completion to
Sample Start (ASAM = 1)
Time to Stabilize Analog Stage
from A/D Off to A/D On
—
—
Note 1: Because the sample caps will eventually lose charge, clock periods above 100 μsec can affect linearity
performance, especially at elevated temperatures.
DS70141D-page 198
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
dsPIC30F3010
30I/SP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
YYWWNNN
0710017
28-Lead SOIC
Example
dsPIC30F3010
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
30I/SO
e
3
YYWWNNN
0710017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC
30F3011
30I/ML
0710017
e
3
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
dsPIC30F3011
30I/P
e
3
0710017
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 199
dsPIC30F3010/3011
Package Marking Information (Continued)
44-Lead TQFP
Example
dsPIC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
30F3011
30I/PT
0710017
e
3
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC
30F3011
30I/ML
0710017
e
3
DS70141D-page 200
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
24.2 Package Details
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 201
dsPIC30F3010/3011
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
–
–
–
–
–
8°
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
DS70141D-page 202
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
40
.100 BSC
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
–
–
–
–
–
–
–
–
–
–
–
–
.250
.195
–
A2
A1
E
.125
.015
.590
.485
1.980
.115
.008
.030
.014
–
.625
.580
2.095
.200
.015
.070
.023
.700
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 203
dsPIC30F3010/3011
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Leads
Lead Pitch
N
e
0.80 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.30
11°
0.20
0.45
13°
b
0.37
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
DS70141D-page 204
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Pins
N
e
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
8.00 BSC
6.45
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
6.30
6.80
8.00 BSC
6.45
D2
b
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
0.30
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
]
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 205
dsPIC30F3010/3011
NOTES:
DS70141D-page 206
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
APPENDIX A: REVISION HISTORY
Revision B (May 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were
distributed with incomplete characterization data.
This revision reflects these updates:
• Supported I2C Slave Addresses
(see Table 17-1)
• ADC Conversion Clock selection to allow 1 Msps
operation (see Section 19.0 “10-bit High-Speed
Analog-to-Digital Converter (ADC) Module”)
• Operating Current (IDD) Specifications
(see Table 23-5)
• Power-Down Current (IPD)
(see Table 23-7)
• I/O pin Input Specifications
(see Table 23-8)
• BOR voltage limits
(see Table 23-10)
• Watchdog Timer time-out limits
(see Table 23-20)
Revision C (September 2006)
Updates made to
Section 23.0 “Electrical Characteristics”.
Revision D (January 2007)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
DS70141D-page 207
dsPIC30F3010/3011
NOTES:
DS70141D-page 208
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
INDEX
Block Diagrams
Numerics
10-bit High Speed ADC Functional........................... 124
16-bit Timer1 Module.................................................. 64
16-bit Timer4 .............................................................. 74
16-bit Timer5 .............................................................. 75
32-bit Timer4/5 ........................................................... 73
Dedicated Port Structure ............................................ 57
DSP Engine................................................................ 19
dsPIC30F3010.............................................................. 9
dsPIC30F3011.............................................................. 8
External Power-on Reset Circuit .............................. 143
10-bit High Speed A/D
A/D Acquisition Requirements .................................. 130
Aborting a Conversion .............................................. 126
ADCHS ..................................................................... 123
ADCON1................................................................... 123
ADCON2................................................................... 123
ADCON3................................................................... 123
ADCSSL.................................................................... 123
ADPCFG................................................................... 123
Configuring Analog Port Pins.................................... 132
Connection Considerations....................................... 132
Conversion Operation............................................... 125
Effects of a Reset...................................................... 131
Operation During CPU Idle Mode ............................. 131
Operation During CPU Sleep Mode.......................... 131
Output Formats......................................................... 131
Power-Down Modes.................................................. 131
Programming the Start of Conversion Trigger .......... 126
Register Map............................................................. 133
Result Buffer ............................................................. 125
Sampling Requirements............................................ 130
Selecting the Conversion Sequence......................... 125
10-Bit High-Speed Analog-to-Digital Converter (ADC)
Module ...................................................................... 123
16-bit Up/Down Position Counter Mode.............................. 86
Count Direction Status................................................ 86
Error Checking............................................................ 86
2
I C ............................................................................ 108
Input Capture Mode.................................................... 77
Oscillator System...................................................... 137
Output Compare Mode............................................... 81
PWM Module.............................................................. 92
Quadrature Encoder Interface.................................... 85
Reset System ........................................................... 141
Shared Port Structure................................................. 58
SPI............................................................................ 104
SPI Master/Slave Connection................................... 104
UART Receiver......................................................... 116
UART Transmitter..................................................... 115
BOR Characteristics ......................................................... 168
BOR. See Brown-out Reset
Brown-out Reset
Timing Requirements ............................................... 175
Brown-out Reset (BOR).................................................... 135
C
A
C Compilers
A/D
MPLAB C18.............................................................. 158
MPLAB C30.............................................................. 158
Center-Aligned PWM.......................................................... 95
CLKOUT and I/O Timing
Characteristics.......................................................... 174
Requirements ........................................................... 174
Code Examples
1 Msps Configuration Guideline................................ 128
600 ksps Configuration Guideline............................. 129
Conversion Rate Parameters.................................... 127
Selecting the Conversion Clock................................ 126
Voltage Reference Schematic .................................. 128
AC Characteristics ............................................................ 169
Load Conditions........................................................ 169
AC Temperature and Voltage Specifications.................... 169
ADC
750 ksps Configuration Guideline............................. 129
Conversion Speeds................................................... 127
Address Generator Units .................................................... 35
Alternate 16-bit Timer/Counter............................................ 87
Alternate Vector Table ........................................................ 45
Assembler
Data EEPROM Block Erase ....................................... 54
Data EEPROM Block Write ........................................ 56
Data EEPROM Read.................................................. 53
Data EEPROM Word Erase ....................................... 54
Data EEPROM Word Write ........................................ 55
Erasing a Row of Program Memory ........................... 49
Initiating a Programming Sequence ........................... 50
Loading Write Latches................................................ 50
Code Protection................................................................ 135
Complementary PWM Operation........................................ 96
Configuring Analog Port Pins.............................................. 58
Control Registers................................................................ 48
NVMADR.................................................................... 48
NVMADRU ................................................................. 48
NVMCON.................................................................... 48
NVMKEY .................................................................... 48
Core Overview.................................................................... 15
Core Register Map.............................................................. 31
Customer Change Notification Service............................. 215
Customer Notification Service .......................................... 215
Customer Support............................................................. 215
MPASM Assembler................................................... 158
Automatic Clock Stretch.................................................... 110
During 10-bit Addressing (STREN = 1)..................... 110
During 7-bit Addressing (STREN = 1)....................... 110
Receive Mode........................................................... 110
Transmit Mode.......................................................... 110
B
Bandgap Start-up Time
Requirements............................................................ 176
Timing Characteristics .............................................. 176
Barrel Shifter ....................................................................... 22
Bit-Reversed Addressing .................................................... 38
Example...................................................................... 38
Implementation ........................................................... 38
Modifier Values (table)................................................ 39
Sequence Table (16-Entry)......................................... 39
D
Data Access from Program Memory Using Program
Space Visibility ........................................................... 26
Data Accumulators and Adder/Subtracter .......................... 20
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 209
dsPIC30F3010/3011
Overflow and Saturation .............................................20
Data Accumulators and Adder/Subtractor
Exception Processing
Interrupt Priority.......................................................... 42
Exception Sequence
Data Space Write Saturation ......................................22
Round Logic................................................................21
Write Back...................................................................21
Data Address Space ...........................................................27
Alignment....................................................................30
Alignment (Figure) ......................................................30
Effect of Invalid Memory Accesses.............................30
MCU and DSP (MAC Class) Instructions Example.....29
Memory Map ......................................................... 27, 28
Near Data Space ........................................................31
Software Stack............................................................31
Spaces........................................................................30
Width...........................................................................30
Data EEPROM Memory......................................................53
Erasing........................................................................54
Erasing, Block.............................................................54
Erasing, Word .............................................................54
Protection Against Spurious Write ..............................56
Reading.......................................................................53
Write Verify .................................................................56
Writing.........................................................................55
Writing, Block..............................................................56
Writing, Word ..............................................................55
DC Characteristics ............................................................161
BOR ..........................................................................168
Brown-out Reset .......................................................167
I/O Pin Output Specifications ....................................167
Idle Current (IIDLE) ....................................................164
Operating Current (IDD).............................................163
Power-Down Current (IPD) ........................................165
Program and EEPROM.............................................168
Temperature and Voltage Specifications..................161
Dead-Time Generators .......................................................96
Ranges........................................................................96
Development Support .......................................................157
Device Configuration
Register Map.............................................................148
Device Configuration Registers.........................................146
FBORPOR ................................................................146
FGS...........................................................................146
FOSC ........................................................................146
FWDT........................................................................146
Device Overview ...................................................................7
Divide Support.....................................................................18
DSP Engine.........................................................................18
Multiplier......................................................................20
dsPIC30F3010 Port Register Map ......................................59
dsPIC30F3011 Port Register Map ......................................60
Dual Output Compare Match Mode ....................................82
Continuous Pulse Mode..............................................82
Single Pulse Mode ......................................................82
Trap Sources .............................................................. 43
External Clock Timing Characteristics
Type 1, 2, 3, 4 and 5 Timer....................................... 177
External Clock Timing Requirements ............................... 170
Timer1 ...................................................................... 177
Timer2 and Timer 4 .................................................. 178
Timer3 and Timer5 ................................................... 178
External Interrupt Requests................................................ 45
F
Fast Context Saving ........................................................... 45
Flash Program Memory ...................................................... 47
In-Circuit Serial Programming (ICSP)......................... 47
Run-Time Self-Programming (RTSP)......................... 47
Table Instruction Operation Summary........................ 47
I
I/O Pin Specifications
Output....................................................................... 167
I/O Ports.............................................................................. 57
Parallel I/O (PIO) ........................................................ 57
2
I C 10-bit Slave Mode Operation...................................... 109
Reception ................................................................. 110
Transmission ............................................................ 110
I C 7-bit Slave Mode Operation........................................ 109
2
Reception ................................................................. 109
Transmission ............................................................ 109
I C Master Mode
2
Baud Rate Generator ............................................... 112
Clock Arbitration ....................................................... 112
Multi-Master Communication, Bus Collision and
Bus Arbitration.................................................. 112
Reception ................................................................. 112
Transmission ............................................................ 111
2
I C Module
Addresses................................................................. 109
Bus Data Timing Characteristics
Master Mode..................................................... 190
Slave Mode....................................................... 192
Bus Data Timing Requirements
Master Mode..................................................... 191
Slave Mode....................................................... 192
Bus Start/Stop Bits Timing Characteristics
Master Mode..................................................... 190
Slave Mode....................................................... 192
General Call Address Support.................................. 111
Interrupts .................................................................. 111
IPMI Support............................................................. 111
Master Operation...................................................... 111
Master Support ......................................................... 111
Operating Function Description ................................ 107
Operation During CPU Sleep and Idle Modes.......... 112
Pin Configuration ...................................................... 107
Programmer’s Model ................................................ 107
Register Map ............................................................ 113
Registers .................................................................. 107
Slope Control............................................................ 111
Software Controlled Clock Stretching (STREN = 1) . 110
Various Modes.......................................................... 107
Idle Current (IIDLE) ............................................................ 164
In-Circuit Serial Programming (ICSP)............................... 135
Independent PWM Output .................................................. 98
Initialization Condition for RCON Register Case 1 ........... 144
E
Edge-Aligned PWM.............................................................95
Electrical Characteristics...................................................161
AC .............................................................................169
DC.............................................................................161
Equations
A/D Conversion Clock...............................................126
Baud Rate.................................................................119
PWM Period................................................................94
PWM Resolution .........................................................94
Serial Clock Rate ......................................................112
Errata ....................................................................................6
DS70141D-page 210
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
Initialization Condition for RCON Register Case 2 ........... 144
Input Capture (CAPX) Timing Characteristics .................. 180
Input Capture Interrupts...................................................... 79
Register Map............................................................... 80
Input Capture Module ......................................................... 77
In CPU Sleep Mode .................................................... 78
Simple Capture Event Mode....................................... 78
Input Capture Timing Requirements................................. 180
Input Change Notification Module....................................... 61
Register Map (bits 7-0) ............................................... 61
Input Characteristics
QEA/QEB.................................................................. 183
Instruction Addressing Modes............................................. 35
File Register Instructions ............................................ 35
Fundamental Modes Supported.................................. 35
MAC Instructions......................................................... 36
MCU Instructions ........................................................ 35
Move and Accumulator Instructions............................ 36
Other Instructions........................................................ 36
Instruction Set Overview ................................................... 152
Instruction Set Summary................................................... 149
Internal Clock Timing Examples ....................................... 172
Internet Address................................................................ 215
Interrupt Controller
LP Oscillator Control................................................. 139
Phase Locked Loop (PLL)........................................ 139
Start-up Timer (OST)................................................ 138
Oscillator Selection........................................................... 135
Oscillator Start-up Timer
Timing Characteristics.............................................. 175
Timing Requirements ............................................... 175
Output Compare Interrupts................................................. 83
Output Compare Mode
Register Map .............................................................. 84
Output Compare Module .................................................... 81
Timing Characteristics.............................................. 180
Timing Requirements ............................................... 180
Output Compare Operation During CPU Idle Mode ........... 83
Output Compare Sleep Mode Operation ............................ 83
P
Packaging......................................................................... 199
Marking..................................................................... 199
PICSTART Plus Development Programmer..................... 160
Pinout Descriptions....................................................... 10, 12
PLL Clock Timing Specifications ...................................... 171
POR. See Power-on Reset
Port Write/Read Example ................................................... 58
Position Measurement Mode.............................................. 87
Power Saving Modes (Sleep and Idle) ............................. 135
Power-Down Current (IPD)................................................ 165
Power-on Reset (POR)..................................................... 135
Oscillator Start-up Timer (OST)................................ 135
Power-up Timer (PWRT).......................................... 135
Power-Saving Modes........................................................ 145
Idle............................................................................ 146
Sleep ........................................................................ 145
Power-up Timer
Register Map............................................................... 46
Interrupt Priority
Traps........................................................................... 43
Interrupt Sequence ............................................................. 45
Interrupt Stack Frame ................................................. 45
Interrupts............................................................................. 41
L
Load Conditions................................................................ 169
M
Timing Characteristics.............................................. 175
Timing Requirements ............................................... 175
Program Address Space..................................................... 23
Construction ............................................................... 24
Data Access From Program Memory Using
Memory Organization.......................................................... 23
Microchip Internet Web Site.............................................. 215
Modulo Addressing ............................................................. 36
Applicability................................................................. 38
Operation Example ..................................................... 37
Start and End Address................................................ 37
W Address Register Selection .................................... 37
Motor Control PWM Module................................................ 91
Fault Timing Characteristics ..................................... 182
Timing Characteristics .............................................. 182
Timing Requirements................................................ 182
MPLAB ASM30 Assembler, Linker, Librarian ................... 158
MPLAB ICD 2 In-Circuit Debugger ................................... 159
MPLAB ICE 2000 High-Performance Universal
Table Instructions ............................................... 25
Data Access from, Address Generation ..................... 24
Memory Map............................................................... 23
Table Instructions
TBLRDH ............................................................. 25
TBLRDL.............................................................. 25
TBLWTH............................................................. 25
TBLWTL ............................................................. 25
Program and EEPROM Characteristics............................ 168
Program Counter................................................................ 16
Program Data Table Access............................................... 26
Program Space Visibility
In-Circuit Emulator .................................................... 159
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator .................................................... 159
MPLAB Integrated Development Environment Software .. 157
MPLAB PM3 Device Programmer .................................... 159
MPLINK Object Linker/MPLIB Object Librarian ................ 158
Window into Program Space Operation ..................... 27
Programmable .................................................................. 135
Programmable Digital Noise Filters .................................... 87
Programmer’s Model .......................................................... 16
Diagram...................................................................... 17
Programming Operations.................................................... 49
Algorithm for Program Flash....................................... 49
Erasing a Row of Program Memory ........................... 49
Initiating the Programming Sequence ........................ 50
Loading Write Latches................................................ 50
PWM
O
OC/PWM Module Timing Characteristics.......................... 181
Operating Current (IDD)..................................................... 163
Oscillator
Operating Modes (Table).......................................... 136
Oscillator Configurations................................................... 138
Fail-Safe Clock Monitor............................................. 140
Fast RC (FRC).......................................................... 139
Initial Clock Source Selection ................................... 138
Low-Power RC (LPRC)............................................. 139
Register Map ............................................................ 101
PWM Duty Cycle Comparison Units................................... 95
Duty Cycle Register Buffers ....................................... 95
PWM Fault Pins.................................................................. 99
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 211
dsPIC30F3010/3011
Enable Bits..................................................................99
Fault States.................................................................99
Modes .........................................................................99
Cycle-by-Cycle....................................................99
Software Simulator (MPLAB SIM) .................................... 158
Software Stack Pointer, Frame Pointer .............................. 16
CALL Stack Frame ..................................................... 31
SPI Mode
Latched ...............................................................99
Slave Select Synchronization ................................... 105
SPI1 Register Map.................................................... 106
SPI Module ....................................................................... 103
Framed SPI Support................................................. 103
Operating Function Description ................................ 103
SDOx Disable ........................................................... 103
Timing Characteristics
PWM Operation During CPU Idle Mode............................100
PWM Operation During CPU Sleep Mode ........................100
PWM Output and Polarity Control.......................................99
Output Pin Control ......................................................99
PWM Output Override.........................................................98
Complementary Output Mode.....................................98
Synchronization ..........................................................98
PWM Period........................................................................94
PWM Special Event Trigger..............................................100
Postscaler .................................................................100
PWM Time Base .................................................................93
Continuous Up/Down Counting Modes.......................93
Double Update Mode ..................................................94
Free Running Mode ....................................................93
Postscaler ...................................................................94
Prescaler.....................................................................94
Single Shot Mode........................................................93
PWM Update Lockout .......................................................100
Master Mode (CKE = 0).................................... 185
Master Mode (CKE = 1).................................... 186
Slave Mode (CKE = 1).............................. 187, 188
Timing Requirements
Master Mode (CKE = 0).................................... 185
Master Mode (CKE = 1).................................... 186
Slave Mode (CKE = 0)...................................... 187
Slave Mode (CKE = 1)...................................... 189
Word and Byte Communication................................ 103
SPI Operation During CPU Idle Mode .............................. 105
SPI Operation During CPU Sleep Mode........................... 105
Status Register ................................................................... 16
Symbols Used in Opcode Descriptions ............................ 150
System Integration............................................................ 135
Overview................................................................... 135
Register Map ............................................................ 148
Q
QEA/QEB Input Characteristics ........................................183
QEI Module
External Clock Timing Requirements........................179
Index Pulse Timing Characteristics...........................184
Index Pulse Timing Requirements ............................184
Operation During CPU Idle Mode ...............................88
Operation During CPU Sleep Mode............................87
Register Map...............................................................89
Timer Operation During CPU Idle Mode .....................88
Timer Operation During CPU Sleep Mode..................87
Quadrature Decoder Timing Requirements ......................183
Quadrature Encoder Interface (QEI) Module ......................85
Quadrature Encoder Interface Interrupts ............................88
Quadrature Encoder Interface Logic...................................86
T
Temperature and Voltage Specifications
AC............................................................................. 169
DC ............................................................................ 161
Timer1 Module.................................................................... 63
16-bit Asynchronous Counter Mode ........................... 63
16-bit Synchronous Counter Mode............................. 63
16-bit Timer Mode....................................................... 63
Gate Operation ........................................................... 64
Interrupt ...................................................................... 65
Operation During Sleep Mode .................................... 64
Prescaler .................................................................... 64
Real-Time Clock ......................................................... 65
RTC Interrupts.................................................... 65
RTC Oscillator Operation ................................... 65
Register Map .............................................................. 66
Timer2 and Timer3 Selection Mode.................................... 82
Timer2/3 Module................................................................. 67
32-bit Synchronous Counter Mode............................. 67
32-bit Timer Mode....................................................... 67
ADC Event Trigger...................................................... 70
Gate Operation ........................................................... 70
Interrupt ...................................................................... 70
Operation During Sleep Mode .................................... 70
Register Map .............................................................. 71
Timer Prescaler .......................................................... 70
Timer4/5 Module................................................................. 73
Register Map .............................................................. 76
TimerQ (QEI Module) External Clock Timing
R
Reader Response .............................................................216
Reset......................................................................... 135, 141
Reset Sequence..................................................................43
Reset Sources ............................................................43
Reset Timing Characteristics ............................................175
Reset Timing Requirements..............................................175
Resets
BOR, Programmable.................................................143
POR ..........................................................................141
POR with Long Crystal Start-up Time.......................143
POR, Operating without FSCM and PWRT ..............143
S
Simple Capture Event Mode
Capture Buffer Operation............................................78
Capture Prescaler.......................................................78
Hall Sensor Mode .......................................................78
Input Capture in CPU Idle Mode .................................79
Timer2 and Timer3 Selection Mode............................78
Simple OC/PWM Mode Timing Requirements..................181
Simple Output Compare Match Mode.................................82
Simple PWM Mode .............................................................82
Input Pin Fault Protection............................................82
Period..........................................................................83
Single Pulse PWM Operation..............................................98
Characteristics.......................................................... 179
Timing Characteristics
A/D Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001)........ 197
ADC Conversion
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000).................................. 196
Bandgap Start-up Time............................................. 176
DS70141D-page 212
Confidential
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
CLKOUT and I/O....................................................... 174
External Clock........................................................... 169
I C Bus Data
Timer3 and Timer5 External Clock........................... 178
Watchdog Timer ....................................................... 175
Timing Specifications
2
Master Mode..................................................... 190
Slave Mode....................................................... 192
I C Bus Start/Stop Bits
PLL Clock ................................................................. 171
Trap Vectors....................................................................... 44
2
U
UART
Master Mode..................................................... 190
Slave Mode....................................................... 192
Input Capture (CAPX)............................................... 180
Motor Control PWM Module...................................... 182
Motor Control PWM Module Falult............................ 182
OC/PWM Module...................................................... 181
Oscillator Start-up Timer........................................... 175
Output Compare Module........................................... 180
Power-up Timer ........................................................ 175
QEI Module Index Pulse ........................................... 184
Reset......................................................................... 175
SPI Module
Master Mode (CKE = 0).................................... 185
Master Mode (CKE = 1).................................... 186
Slave Mode (CKE = 0)...................................... 187
Slave Mode (CKE = 1)...................................... 188
TimerQ (QEI Module) External Clock ....................... 179
Type 1, 2, 3, 4 and 5 Timer External Clock............... 177
Watchdog Timer........................................................ 175
Address Detect Mode............................................... 119
Auto Baud Support ................................................... 120
Baud Rate Generator ............................................... 119
Enabling and Setting Up UART................................ 117
Alternate I/O ..................................................... 117
Disabling........................................................... 117
Enabling ........................................................... 117
Setting Up Data, Parity and Stop Bit Selections117
Loopback Mode........................................................ 119
Module Overview...................................................... 115
Operation During CPU Sleep and Idle Modes.......... 120
Receiving Data ......................................................... 118
In 8-bit or 9-bit Data Mode................................ 118
Interrupt ............................................................ 118
Receive Buffer (UxRCB)................................... 118
Reception Error Handling ......................................... 118
Framing Error (FERR) ...................................... 119
Idle Status ........................................................ 119
Parity Error (PERR).......................................... 119
Receive Break .................................................. 119
Receive Buffer Overrun Error (OERR Bit)........ 118
Transmitting Data ..................................................... 117
In 8-bit Data Mode............................................ 117
In 9-bit Data Mode............................................ 117
Interrupt ............................................................ 118
Transmit Buffer (UxTXB) .................................. 117
UART1 Register Map ............................................... 121
UART2 Register Map ............................................... 121
Unit ID Locations .............................................................. 135
Universal Asynchronous Receiver Transmitter
Timing Diagrams
Center Aligned PWM .................................................. 95
Dead-Time .................................................................. 97
Edge-Aligned PWM..................................................... 95
PWM Output ............................................................... 83
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 1 .................................. 142
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 2 .................................. 142
Time-out Sequence on Power-up
(MCLR Tied to VDD).......................................... 142
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 172
Timing Diagrams.See Timing Characteristics
Timing Requirements
Module (UART)......................................................... 115
W
A/D Conversion
Wake-up from Sleep......................................................... 135
Wake-up from Sleep and Idle ............................................. 45
Watchdog Timer
Timing Characteristics.............................................. 175
Timing Requirements ............................................... 175
Watchdog Timer (WDT)............................................ 135, 145
Enabling and Disabling............................................. 145
Operation.................................................................. 145
WWW Address ................................................................. 215
WWW, On-Line Support ....................................................... 6
10-Bit High-speed ............................................. 198
Bandgap Start-up Time............................................. 176
Brown-out Reset ....................................................... 175
CLKOUT and I/O....................................................... 174
External Clock........................................................... 170
2
I C Bus Data (Master Mode)..................................... 191
2
I C Bus Data (Slave Mode)....................................... 192
Input Capture ............................................................ 180
Motor Control PWM Module...................................... 182
Oscillator Start-up Timer........................................... 175
Output Compare Module........................................... 180
Power-up Timer ........................................................ 175
QEI Module
External Clock................................................... 179
Index Pulse ....................................................... 184
Quadrature Decoder ................................................. 183
Reset......................................................................... 175
Simple OC/PWM Mode............................................. 181
SPI Module
Master Mode (CKE = 0).................................... 185
Master Mode (CKE = 1).................................... 186
Slave Mode (CKE = 0)...................................... 187
Slave Mode (CKE = 1)...................................... 189
Timer1 External Clock............................................... 177
© 2007 Microchip Technology Inc.
Confidential
DS70141D-page 213
dsPIC30F3010/3011
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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DS70141D-page 214
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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DS70141D
Literature Number:
Device:
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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© 2007 Microchip Technology Inc.
DS70141D-page 215
dsPIC30F3010/3011
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC30F3010AT-30I/PF-000
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
Package
PT = TQFP 10x10
PT = TQFP 12x12
P
= DIP
Flash
SO = SOIC
SP = SPDIP
ML = QFN 6x6 or 8x8
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
S
W
= Die (Waffle Pack)
= Die (Wafers)
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Temperature
I = Industrial -40°C to +85°C
E = Extended High Temp -40°C to +125°C
Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID
T = Tape and Reel
A,B,C… = Revision Level
Example:
dsPIC30F3010AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
DS70141D-page 216
© 2007 Microchip Technology Inc.
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12/08/06
DS70141D-page 217
© 2007 Microchip Technology Inc.
dsPIC30F3010/3011
DS70141D-page 218
© 2007 Microchip Technology Inc.
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