DSPIC30F3011AP-I/PT_技术文档

dsPIC30F Data Sheet

Motor Control and

Power Conversion Family

High Performance

Digital Signal Controllers

 2003 Microchip Technology Inc.

Advance Information

DS70082C

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, K^EELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,

SEEVAL and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor, SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

DS70082C-page ii

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

dsPIC30F Enhanced Flash 16-bit Digital Signal Controllers

Motor Control and Power Conversion Family

High Performance Modified RISC CPU:

Peripheral Features (Continued):

• Modified Harvard architecture

• 16-bit Compare/PWM output functions

- Dual Compare mode available

• C compiler optimized instruction set architecture

• 84 base instructions

• 3-wire SPI^TMmodules (supports 4 Frame modes)

2

• I C^TMmodule supports Multi-Master/Slave mode

• 24-bit wide instructions, 16-bit wide data path

and 7-bit/10-bit addressing

• Addressable UART modules supporting:

- Interrupt on address bit

• Linear program memory addressing up to 4M

Instruction Words

• Linear data memory addressing up to 64 Kbytes

• Up to 144 Kbytes on-chip Flash program space

• Up to 48K Instruction Words

- Wake-up on Start bit

- 4 characters deep TX and RX FIFO buffers

• CAN bus modules

• Up to 8 Kbytes of on-chip data RAM

• Up to 4 Kbytes of non-volatile data EEPROM

• 16 x 16-bit working register array

Motor Control PWM Module Features:

• Three Address Generation Units that enable:

- Dual data fetch

• Up to 8 PWM output channels

- Complementary or Independent Output

modes

- Accumulator write back for DSP operations

• Flexible Addressing modes supporting:

- Indirect, Modulo and Bit-Reversed modes

- Edge and Center Aligned modes

• 4 duty cycle generators

• Two, 40-bit wide accumulators with optional

saturation logic

• Dedicated time base with 4 modes

• Programmable output polarity

• Dead-time control for Complementary mode

• Manual output control

• 17-bit x 17-bit single cycle hardware fractional/

integer multiplier

• Single cycle Multiply-Accumulate (MAC) operation

• 40-stage Barrel Shifter

• Trigger for A/D conversions

• Up to 30 MIPs operation:

Quadrature Encoder Interface Module

Features:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• Phase A, Phase B and Index Pulse input

• 16-bit up/down position counter

• Up to 42 interrupt sources

• Count direction status

- 8 user selectable priority levels

• Vector table with up to 62 vectors

- 54 interrupt vectors

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Interrupt on position counter rollover/underflow

- 8 processor exceptions and software traps

Peripheral Features:

• High current sink/source I/O pins: 25 mA/25 mA

• Up to 5 external interrupt sources

• Timer module with programmable prescaler:

- Up to five 16-bit timers/counters; optionally

pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 1

dsPIC30F

Input Capture Module Features:

Special Microcontroller Features:

• Captures 16-bit timer value

• Enhanced Flash program memory:

- Capture every 1st, 4th or 16th rising edge

- Capture every falling edge

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- Capture every rising and falling edge

• Resolution of 33 ns at 30 MIPs

• Timer2 or Timer3 time base selection

• Input Capture during Idle

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Interrupt on input capture event

• Flexible Watchdog Timer (WDT) with on-chip low

power RC oscillator for reliable operation

Analog Features:

• 10-bit Analog-to-Digital Converter (A/D) with:

- 500 Ksps (for 10-bit A/D) conversion rate

- Up to 16 input channels

• Fail-Safe clock monitor operation

• Detects clock failure and switches to on-chip low

power RC oscillator

- Conversion available during Sleep and Idle

• Programmable Low Voltage Detection (PLVD)

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™) via 3

pins and power/ground

• Programmable Brown-out Detection and Reset

generation

• Selectable Power Management modes

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low power, high speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F Motor Control and Power Conversion Family

Program

Pins Mem. Bytes/

Instructions

Output

Motor

SRAM EEPROM Timer Input

A/D 10-bit Quad

500 Ksps Enc

Device

Comp/Std Control

Bytes

16-bit Cap

PWM

dsPIC30F2010

dsPIC30F3010

dsPIC30F4012

28

12K/4K

24K/8K

512

1024

4096

3

5

4

8

2

4

8

6 ch

8 ch

6 ch

Yes

1

2

1

2

1

2

1

-

1024

2048

1024

2048

8192

48K/16K

24K/8K

6 ch

1

-

dsPIC30F3011 40/44

dsPIC30F4011 40/44

9 ch

48K/16K

66K/22K

144K/48K

9 ch

1

2

dsPIC30F5015

dsPIC30F6010

64

80

16 ch

DS70082C-page 2

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Pin Diagrams

28-Pin SDIP and SOIC

MCLR

1

2

3

4

5

28

27

26

25

24

AVDD

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V^REF-/CN3/RB1

AN2/SS1/CN4/RB2

AVSS

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

V^DD

AN3/INDX/CN5/RB3

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

V^SS

6

23

22

21

20

19

18

17

16

15

7

8

OSC1/CLKI

9

OSC2/CLKO/RC15

V^SS

10

11

12

13

14

EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

FLTA/INT0/SCK1/OCFA/RE8

EMUC2/OC1/IC1/INT1/RD0

EMUD2/OC2/IC2/INT2/RD1

Note: Pinout subject to change.

28-Pin SDIP and SOIC

MCLR

1

28

AV^DD

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V^REF-/CN3/RB1

AN2/SS1/CN4/RB2

2

3

4

5

27

26

25

24

AVSS

PWM1L/RE0

PWM1H/RE1

AN3/INDX/CN5/RB3

PWM2L/RE2

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

V^SS

PWM2H/RE3

6

23

22

21

20

19

18

17

16

15

PWM3L/RE4

7

PWM3H/RE5

8

OSC1/CLKI

V^DD

9

OSC2/CLKO/RC15

V^SS

10

11

12

13

14

EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2

PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3

FLTA/INT0/SCK1/OCFA/RE8

EMUC2/OC1/IC1/INT1/RD0

EMUD2/OC2/IC2/INT2/RD1

Note: Pinout subject to change.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 3

dsPIC30F

Pin Diagrams (Continued)

40-Pin PDIP

MCLR

AV^DD

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V^REF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

AN6/OCFA/RB6

AVSS

2

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

VDD

3

4

5

6

7

8

9

AN7/RB7

V^SS

10

11

12

13

AN8/RB8

VDD

RF0

VSS

RF1

OSC1/CLKI

U2RX/RF4

U2TX/RF5

OSC2/CLKO/RC15 14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

FLTA/INT0/RE8 17

EMUD2/OC2/IC2/INT2/RD1 18

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCK/RF3

SCK1/RF6

15

16

EMUC2/OC1/IC1/INT1/RD0

OC4/RD3

V^SS

19

20

OC3/RD2

VDD

Note: Pinout subject to change.

40-Pin PDIP

MCLR

AV^DD

1

2

3

4

5

6

7

8

9

40

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/V^REF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

AN4/QEA/IC7/CN6/RB4

AN5/QEB/IC8/CN7/RB5

AN6/OCFA/RB6

AVSS

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

VDD

AN7/RB7

V^SS

10

AN8/RB8

VDD

C1RX/RF0

C1TX/RF1

11

12

13

VSS

OSC1/CLKI

U2RX/RF4

U2TX/RF5

OSC2/CLKO/RC15 14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

FLTA/INT0/RE8 17

EMUD2/OC2/IC2/INT2/RD1 18

OC4/RD3

V^SS

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCK/RF3

SCK1/RF6

15

16

EMUC2/OC1/IC1/INT1/RD0

19

20

OC3/RD2

VDD

Note: Pinout subject to change.

DS70082C-page 4

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Pin Diagrams (Continued)

44-Pin TQFP

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

V^DD

33

32

31

30

29

28

27

26

AN4/QEA/IC7/CN6/RB4

1

AN5/QEB/IC8/CN7/RB5

2

AN6/OCFA/RB6

3

AN7/RB7

4

VSS

AN8/RB8

5

dsPIC30F3011

NC

6

RF0

V^DD

7

RF1

VSS

OSC1/CLKI

8

U2RXRF4

U2TX/RF5

9

25

24

23

OSC2/CLKO/RC15

10

11

PGC/EMUC/U1RX/SDI1/SDA/RF2

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

Note: Pinout subject to change.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 5

dsPIC30F

Pin Diagrams (Continued)

44-Pin TQFP

PWM2H/RE3

33

32

31

30

29

28

27

26

AN4/QEA/IC7/CN6/RB4

1

PWM3L/RE4

AN5/QEB/IC8/CN7/RB5

2

PWM3H/RE5

AN6/OCFA/RB6

3

V^DD

AN7/RB7

4

VSS

AN8/RB8

5

dsPIC30F4011

NC

6

C1RX/RF0

V^DD

VSS

7

C1TX/RF1

8

U2RXRF4

OSC1/CLKI

9

25

24

23

U2TX/RF5

OSC2/CLKO/RC15

10

11

PGC/EMUC/U1RX/SDI1/SDA/RF2

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

Note: Pinout subject to change.

DS70082C-page 6

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Pin Diagrams (Continued)

64-pin TQFP

PWM3H/RE5

PWM4L/RE6

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0

INT4/RD11

2

PWM4H/RE7

3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

4

5

INT3/RD10

6

IC2/FLTB/INT2/RD9

IC1/FLTA/INT1/RD8

V^SS

7

SS2/CN11/RG9

VSS

8

dsPIC30F5015

9

OSC2/CLKO/RC15

OSC1/CLKIN

VDD

10

11

12

13

14

15

16

AN5/QEB/IC8/CN7/RB5

AN4/QEA/IC7/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/V^REF-/CN3/RB1

AN0/V^REF+/CN2/RB0

V^DD

SCL/RG2

SDA/RG3

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

Note: Pinout subject to change.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 7

dsPIC30F

Pin Diagrams (Continued)

80-Pin TQFP

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

EMUC2/OC1/RD0

IC4/RD11

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

1

PWM3H/RE5

PWM4L/RE6

2

3

PWM4H/RE7

T2CK/RC1

4

IC3/RD10

T4CK/RC3

5

IC2/RD9

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

6

IC1/RD8

7

INT4/RA15

8

INT3/RA14

V^SS

9

SS2/CN11/RG9

V^SS

10

11

12

13

14

15

16

17

18

19

20

dsPIC30F6010

OSC2/CLKO/RC15

OSC1/CLKI

VDD

V^DD

FLTA/INT1/RE8

FLTB/INT2/RE9

AN5/QEB/CN7/RB5

SCL/RG2

SDA/RG3

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

EMUC3/SCK1/INT0/RF6

SDI1/RF7

AN2/SS1/LVDIN/CN4/RB2

AN1/CN3/RB1

EMUD3/SDO1/RF8

U1RX/RF2

AN0/CN2/RB0

U1TX/RF3

Note: Pinout subject to change.

DS70082C-page 8

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Table of Contents

1.0

Device Overview .................................................................................................................................................................... 11

CPU Architecture Overview ................................................................................................................................................... 17

Memory Organization............................................................................................................................................................. 29

Address Generator Units........................................................................................................................................................ 41

Interrupts................................................................................................................................................................................ 49

Flash Program Memory.......................................................................................................................................................... 55

Data EEPROM Memory......................................................................................................................................................... 61

I/O Ports................................................................................................................................................................................. 65

Timer1 Module ....................................................................................................................................................................... 71

Timer2/3 Module .................................................................................................................................................................... 75

Timer4/5 Module .................................................................................................................................................................... 81

Input Capture Module............................................................................................................................................................. 85

Output Compare Module........................................................................................................................................................ 89

Quadrature Encoder Interface (QEI) Module ......................................................................................................................... 93

Motor Control PWM Module................................................................................................................................................... 99

SPI™ Module....................................................................................................................................................................... 109

I2C Module........................................................................................................................................................................... 113

Universal Asynchronous Receiver Transmitter (UART) Module.......................................................................................... 121

CAN Module......................................................................................................................................................................... 129

10-bit High Speed Analog-to-Digital Converter (A/D) Module.............................................................................................. 141

System Integration ............................................................................................................................................................... 149

Instruction Set Summary...................................................................................................................................................... 161

Development Support .......................................................................................................................................................... 169

Electrical Characteristics...................................................................................................................................................... 175

DC and AC Characteristics Graphs and Tables................................................................................................................... 225

Packaging Information ......................................................................................................................................................... 227

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

21.0

22.0

23.0

24.0

25.0

26.0

On-Line Support................................................................................................................................................................................. 243

Systems Information and Upgrade Hot Line...................................................................................................................................... 243

Reader Response.............................................................................................................................................................................. 244

Product Identification System ............................................................................................................................................................ 245

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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We welcome your feedback.

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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 9

dsPIC30F

NOTES:

DS70082C-page 10

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Figure 1-1 shows a sample device block diagram.

1.0

DEVICE OVERVIEW

Note:

The device(s) depicted in this block dia-

gram are representative of the correspond-

ing device family. Other devices of the

same family may vary in terms of number

of pins and multiplexing of pin functions.

Typically, smaller devices in the family con-

tain a subset of the peripherals present in

the device(s) shown in this diagram.

This document contains device family specific informa-

tion for the dsPIC30F family of Digital Signal Controller

(DSC) devices. The dsPIC30F devices contain exten-

sive Digital Signal Processor (DSP) functionality within a

high performance 16-bit microcontroller (MCU)

architecture.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 11

dsPIC30F

FIGURE 1-1:

dsPIC30F6010 BLOCK DIAGRAM

Y Data Bus

X Data Bus

16

16 16

16

VREF-/RA9

VREF+/RA10

INT3/RA14

INT4/RA15

16

Data Latch

Interrupt

PSV & Table

Data Access

Control Block

Controller

Y Data

RAM

X Data

RAM

8

NS

24

(4 Kbytes)

PORTA

Address

Latch

Address

Latch

24

AN0/CN2/RB0

AN1/CN3/RB1

NS

AN2/SS1/LVDIN/CN4/RB2

AN3/INDX/CN5/RB3

X RAGU

X WAGU

24

Y AGU

PCH PCL

PCU

AN4/QEA/CN6/RB4

AN5/QEB/CN7/RB5

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AN8/RB8

Program Counter

Loop

Control

Logic

Stack

Control

Logic

Address Latch

Program Memory

(144 Kbytes)

AN9/RB9

Data EEPROM

(4 Kbytes)

AN10/RB10

Effective Address

AN11/RB11

16

Data Latch

AN12/RB12

AN13/RB13

AN14/RB14

ROM Latch

16

AN15/OCFB/CN12/RB15

24

PORTB

T2CK/RC1

IR

T4CK/RC3

16

EMUD1/SOSCI/CN1/RC13

EMUC1/SOSCO/T1CK/CN0/RC14

OSC2/CLKO/RC15

16

16 x 16

W Reg Array

Decode

PORTC

Instruction

Decode &

Control

16 16

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

Control Signals

to Various Blocks

DSP

OC4/RD3

Divide

Unit

Power-up

Timer

Engine

OC5/CN13/RD4

OC6/CN14/RD5

OC7/CN15/RD6

OC8/CN16/UPDN/RD7

IC1/RD8

Timing

Generation

Oscillator

OSC1/CLKI

Start-up Timer

ALU<16>

POR/BOR

Reset

IC2/RD9

IC3/RD10

IC4/RD11

16

Watchdog

Timer

MCLR

IC5/RD12

IC6/CN19/RD13

IC7/CN20/RD14

IC8/CN21/RD15

Low Voltage

Detect

VDD, VSS

AVDD, AVSS

PORTD

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

FLTA/INT1/RE8

FLTB/INT2/RE9

Input

Output

Compare

Module

`^kNI

2

I C

Capture

Module

10-bit ADC

CAN2

UART1,

UART2

SPI1,

SPI2

Motor Control

PWM

QEI

Timers

PORTE

C1RX/RF0

C2RX/RG0

C1TX/RF1

C2TX/RG1

SCL/RG2

SDA/RG3

U1RX/RF2

U1TX/RF3

U2RX/CN17/RF4

U2TX/CN18/RF5

EMUC3/SCK1/INT0/RF6

SDI1/RF7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9

EMUD3/SDO1/RF8

PORTG

PORTF

DS70082C-page 12

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1:

Pin Name

PINOUT I/O DESCRIPTIONS

Buffer

Type

Description

Type

AN0-AN15

I

Analog Analog input channels.

AN0 and AN1 are also used for device programming data and clock inputs,

respectively.

AVDD

AVSS

P

Positive supply for analog module.

Ground reference for analog module.

CLKI

I

ST/CMOS External clock source input. Always associated with OSC1 pin function.

CLKO

O

—

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

CN0-CN23

I

ST

Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

COFS

CSCK

CSDI

I/O

I

ST

—

Data Converter Interface frame synchronization pin.

Data Converter Interface serial clock input/output pin.

Data Converter Interface serial data input pin.

Data Converter Interface serial data output pin.

CSDO

O

C1RX

C1TX

C2RX

C2TX

I

ST

—

CAN1 bus receive pin.

CAN1 bus transmit pin.

CAN2 bus receive pin.

CAN2 bus transmit pin.

O

I

ST

—

O

EMUD

I/O

ST

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

IC1-IC8

I

ST

Capture inputs 1 through 8.

INDX

QEA

I

ST

Quadrature Encoder Index Pulse input.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

QEB

I

ST

UPDN

O

CMOS Position Up/Down Counter Direction State.

INT0

INT1

INT2

INT3

INT4

I

ST

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

LVDIN

I

Analog Low Voltage Detect Reference Voltage input pin.

Legend: CMOS = CMOS compatible input or output

ST Schmitt Trigger input with CMOS levels

Input

Analog = Analog input

Output

Power

=

O

=

I

=

P

=

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 13

dsPIC30F

TABLE 1-1:

PINOUT I/O DESCRIPTIONS (CONTINUED)

Buffer

Type

Pin Name

Description

Type

FLTA

I

ST

—

PWM Fault A input.

PWM Fault B input.

PWM 1 Low output.

PWM 1 High output.

PWM 2 Low output.

PWM 2 High output.

PWM 3 Low output.

PWM 3 High output.

PWM 4 Low output.

PWM 4 High output.

FLTB

I

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

O

MCLR

I/P

ST

Master Clear (Reset) input or programming voltage input. This pin is an active

low Reset to the device.

OCFA

I

ST

—

Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8).

Compare outputs 1 through 8.

OCFB

OC1-OC8

O

OSC1

OSC2

I

ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS other-

I/O

—

wise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

PGD

PGC

I/O

I

ST

In-Circuit Serial Programming data input/output pin.

In-Circuit Serial Programming clock input pin.

RA9-RA10

I/O

ST

PORTA is a bi-directional I/O port.

RA14-RA15

RB0-RB15

I/O

ST

PORTB is a bi-directional I/O port.

PORTC is a bi-directional I/O port.

RC1

I/O

ST

RC3

RC13-RC15

RD0-RD15

RE0-RE9

RF0-RF8

I/O

ST

PORTD is a bi-directional I/O port.

PORTE is a bi-directional I/O port.

PORTF is a bi-directional I/O port.

PORTG is a bi-directional I/O port.

RG0-RG3

RG6-RG9

I/O

ST

SCK1

SDI1

SDO1

SS1

I/O

ST

—

Synchronous serial clock input/output for SPI1.

SPI1 Data In.

I

O

I

SPI1 Data Out.

ST

—

SPI1 Slave Synchronization.

Synchronous serial clock input/output for SPI2.

SPI2 Data In.

SCK2

SDI2

SDO2

SS2

I/O

I

O

I

SPI2 Data Out.

ST

SPI2 Slave Synchronization.

2

Synchronous serial clock input/output for I C.

SCL

SDA

I/O

ST

2

Synchronous serial data input/output for I C.

SOSCO

SOSCI

O

I

—

32 kHz low power oscillator crystal output.

ST/CMOS 32 kHz low power oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

Legend: CMOS = CMOS compatible input or output

Analog = Analog input

Output

Power

ST

I

=

Schmitt Trigger input with CMOS levels

Input

O

=

P

=

DS70082C-page 14

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 1-1:

PINOUT I/O DESCRIPTIONS (CONTINUED)

Buffer

Type

Pin Name

Description

Type

T1CK

T2CK

T3CK

T4CK

T5CK

I

ST

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

U1RX

U1TX

I

O

I

ST

—

UART1 Receive.

UART1 Transmit.

U1ARX

U1ATX

U2RX

U2TX

ST

—

UART1 Alternate Receive.

UART1 Alternate Transmit.

UART2 Receive.

O

I

ST

—

O

UART2 Transmit.

VDD

P

I

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

VSS

V^REF+

V^REF-

Analog Analog Voltage Reference (High) input.

Analog Analog Voltage Reference (Low) input.

I

Legend: CMOS = CMOS compatible input or output

ST Schmitt Trigger input with CMOS levels

Input

Analog = Analog input

Output

Power

=

O

=

I

=

P

=

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 15

dsPIC30F

NOTES:

DS70082C-page 16

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

The X AGU also supports bit-reversed addressing on

destination effective addresses, to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 for details on modulo and

bit-reversed addressing.

2.0

CPU ARCHITECTURE

OVERVIEW

2.1

Core Overview

The core has a 24-bit instruction word. The Program

Counter (PC) is 23 bits wide with the Least Significant

(LS) bit always clear (see Section 3.1), and the Most

Significant (MS) bit is ignored during normal program

execution, except for certain specialized instructions.

Thus, the PC can address up to 4M instruction words

of user program space. An instruction pre-fetch mech-

anism is used to help maintain throughput. Program

loop constructs, free from loop count management

overhead, are supported using the DO and REPEAT

instructions, both of which are interruptible at any point.

The core supports Inherent (no operand), Relative, Lit-

eral, Memory Direct, Register Direct, Register Indirect,

Register Offset and Literal Offset Addressing modes.

Instructions are associated with predefined Addressing

modes, depending upon their functional requirements.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A+B operations to be executed in a single cycle.

The working register array consists of 16x16-bit regis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

software stack pointer for interrupts and calls.

A DSP engine has been included to significantly

enhance the core arithmetic capability and throughput.

It features a high speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bi-directional barrel shifter. Data in the accumu-

lator or any working register can be shifted up to 15 bits

right or 16 bits left in a single cycle. The DSP instruc-

tions operate seamlessly with all other instructions and

have been designed for optimal real-time performance.

The MAC class of instructions can concurrently fetch

two data operands from memory, while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear for all others. This has been

achieved in a transparent and flexible manner, by ded-

icating certain working registers to each address space

for the MAC class of instructions.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2). The X and Y data space boundary is

device specific and cannot be altered by the user. Each

data word consists of 2 bytes, and most instructions

can address data either as words or bytes.

There are two methods of accessing data stored in

program memory:

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction pre-fetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle, with certain

exceptions as outlined in Section 2.3.

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of pro-

gram space at any 16K program word boundary,

defined by the 8-bit Program Space Visibility Page

(PSVPAG) register. This lets any instruction

access program space as if it were data space,

with a limitation that the access requires an addi-

tional cycle. Moreover, only the lower 16 bits of

each instruction word can be accessed using this

method.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are reserved) and 54 interrupts. Each interrupt

is prioritized based on a user assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest) in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities, ranging from 8 to 15.

• Linear indirect access of 32K word pages within

program space is also possible using any working

register, via table read and write instructions.

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (modulo addressing) are

supported in both X and Y address spaces. This is pri-

marily intended to remove the loop overhead for DSP

algorithms.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 17

dsPIC30F

2.2.2

STATUS REGISTER

2.2

Programmer’s Model

The dsPIC core has a 16-bit status register (SR), the

LS Byte of which is referred to as the SR Low Byte

(SRL) and the MS Byte as the SR High Byte (SRH).

See Figure 2-1 for SR layout.

The programmer’s model is shown in Figure 2-1 and

consists of 16x16-bit working registers (W0 through

W15), 2x40-bit accumulators (AccA and AccB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT), and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

SRL contains all the MCU ALU operation status flags

(including the Z bit), as well as the CPU Interrupt Prior-

ity Level status bits, IPL<2:0>, and the REPEAT active

status bit, RA. During exception processing, SRL is

concatenated with the MS Byte of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP Adder/Subtractor status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) status bit.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary holding register

and can transfer its contents to or from its host register

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

Most SR bits are read/write. Exceptions are:

1. The DA bit: DA is read and clear only, because

accidentally setting it could cause erroneous

operation.

2. The RA bit: RA is a read only bit, because acci-

dentally setting it could cause erroneous opera-

tion. RA is only set on entry into a repeat loop,

and cannot be directly cleared by software.

• PUSH.Sand POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

• DOinstruction

DOSTART, DOEND, DCOUNT shadows are

3. The OV, OA, OB and OAB bits: These bits are

read only and can only be set by the DSP engine

overflow logic.

pushed on loop start, and popped on loop end.

When a byte operation is performed on a working reg-

ister, only the Least Significant Byte of the target regis-

ter is affected. However, a benefit of memory mapped

working registers is that both the Least and Most Sig-

nificant Bytes can be manipulated through byte wide

data memory space accesses.

4. The SA, SB and SAB bits: These are read and

clear only and can only be set by the DSP

engine saturation logic. Once set, these flags

remain set until cleared by the user, irrespective

of the results from any subsequent DSP

operations.

Note 1: Clearing the SAB bit will also clear both

2.2.1

SOFTWARE STACK POINTER/

FRAME POINTER

the SA and SB bits.

The dsPIC^®devices contain a software stack. W15 is

the dedicated software stack pointer (SP), and will be

automatically modified by exception processing and

subroutine calls and returns. However, W15 can be ref-

erenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the stack pointer (e.g., creating

stack frames).

2: When the memory mapped status regis-

ter (SR) is the destination address for an

operation which affects any of the SR bits,

data writes are disabled to all bits.

2.2.2.1

Z Status Bit

Instructions that use a carry/borrow input (ADDC,

CPB, SUBBand SUBBR) will only be able to clear Z

(for a non-zero result) and can never set it. A multi-

precision sequence of instructions, starting with an

instruction with no carry/borrow input, will thus auto-

matically logically AND the successive results of the

zero test. All results must be zero for the Z flag to

remain set by the end of the sequence.

Note:

In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a stack frame pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

All other instructions can set as well as clear the Z bit.

2.2.3

PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

DS70082C-page 18

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 2-1:

PROGRAMMER’S MODEL

D15

D0

W0/WREG

W1

PUSH.S Shadow

DO Shadow

W2

W3

Legend

W4

DSP Operand

Registers

W5

W6

W7

Working Registers

W8

W9

DSP Address

Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

SPLIM

Stack Pointer Limit Register

AD15

AD39

AD31

AD0

DSP

AccA

AccB

Accumulators

PC22

PC0

0

Program Counter

=0

7

TABPAG

TBLPAG

Data Table Page Address

T

M

PSVPAG

mpsm^d

Program Space Visibility Page Address

15

0

RCOUNT

REPEAT Loop Counter

15

DCOUNT

al=iççé=`çìåíÉê

22

=0

DOSTART

DO Loop Start Address

22

DO Loop End Address

DOEND

15

0

=Core Configuration Register

CORCON

OA OB

SA SB OAB SAB DA DC

RA

N

Z

C

IPL2 IPL1 IPL0

OV

Status Register

SRH

SRL

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 19

dsPIC30F

2.3

Instruction Flow

There are 8 types of instruction flows:

1. Normal one-word, one-cycle instructions: these

instructions take one effective cycle to execute,

as shown in Figure 2-2.

FIGURE 2-2:

INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE

TCY0

TCY1

Execute 1

Fetch 2

TCY2

TCY3

TCY4

TCY5

1. MOV.b #0x55,W0

2. MOV.b #0x35,W1

3. ADD.b W0,W1,W2

Fetch 1

Execute 2

Fetch 3

Execute 3

2. One-word, two-cycle (or three-cycle) instruc-

tions that are flow control instructions: these

instructions include the relative branches, rela-

tive call, skips and returns. When an instruction

changes the PC (other than to increment it), the

pipeline fetch is discarded. This causes the

instruction to take two effective cycles to exe-

cute as shown in Figure 2-3. Some instructions

that change program flow require 3 cycles, such

as the RETURN, RETFIE and RETLWinstruc-

tions, and instructions that skip over 2-word

instructions.

FIGURE 2-3:

INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE

TCY0

TCY1

Execute 1

Fetch 2

TCY2

TCY3

TCY4

TCY5

1. MOV #0x55,W0

2. BTSC W1,#3

Fetch 1

Execute 2

Skip Taken

3. ADD W0,W1,W2

4. BRA SUB_1

Fetch 3

Flush

Fetch 4

Execute 4

Fetch 5

5. SUB W0,W1,W3

Flush

Fetch SUB_1

6. Instruction @ address SUB_1

DS70082C-page 20

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

3. One-word, two-cycle instructions that are not

flow control instructions: the only instructions of

this type are the MOV.D (load and store double

word) instructions, as shown in Figure 2-4.

FIGURE 2-4:

INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE MOV.DOPERATIONS

TCY0

TCY1

Execute 1

Fetch 2

TCY2

TCY3

TCY4

TCY5

1. MOV W0,0x1234

Fetch 1

2. MOV.D [W0++],W1

Execute 2

R/W Cycle 1

3. MOV W1,0x00AA

Fetch 3

Execute 2

R/W Cycle2

3a.Stall

Stall

Execute 3

Fetch 4

4. MOV 0x0CC, W0

Execute 4

4. Table read/write instructions. These instructions

will suspend the fetching to insert a read or write

cycle to the program memory. The instruction

fetched, while executing the table operation, is

saved for 1 cycle and executed in the cycle

immediately after the table operation, as shown

in Figure 2-5.

FIGURE 2-5:

INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE TABLE OPERATIONS

TCY0

TCY1

Execute 1

Fetch 2

TCY2

TCY3

TCY4

TCY5

1. MOV #0x1234,W0

2. TBLRDL [W0++],W1

3. MOV #0x00AA,W1

Fetch 1

Execute 2

Fetch 3

Execute 2

Read Cycle

3a.Table Operation

4. MOV #0x0CC,W0

Bus Read Execute 3

Fetch 4

Execute 4

5. Two-word instructions for CALL and GOTO. In

these instructions, the fetch after the instruction

provides the remainder of the jump or call desti-

nation address. These instructions require 2

cycles to execute, 1 cycle to fetch the 2 instruc-

tion words (enabled by a high speed path on the

second fetch), and 1 cycle to flush the pipeline,

as shown in Figure 2-6.

FIGURE 2-6:

INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE GOTO, CALL

TCY0

TCY1

Execute 1

Fetch 2L

TCY2

TCY3

TCY4

TCY5

1. MOV #0x1234,W0

2. GOTO LABEL

Fetch 1

Update PC

2a.Second Word

Fetch 2H NOP

Fetch

LABEL

3. Instruction @ address LABEL

Execute

LABEL

4. BSET W1, #BIT3

Fetch 4

Execute 4

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 21

dsPIC30F

6. Two-word instructions for DO. In these instruc-

tions, the fetch after the instruction contains an

address offset. This address offset is added to

the first instruction address to generate the last

loop instruction address. Therefore, these

instructions require 2 cycles, as shown in

Figure 2-7.

FIGURE 2-7:

INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW

TCY0

TCY1

Execute 1

Fetch 2L

TCY2

TCY3

TCY4

1. PUSH DOEND

Fetch 1

2. DO LABEL,#COUNT

2a.Second Word

NOP

Fetch 2H Execute 2

3. 1st Instruction of Loop

Fetch 3

Execute 3

7. Instructions that are subjected to a stall due to a

data dependency between the X RAGU and X

WAGU. An additional cycle is inserted to resolve

the resource conflict, as shown in Figure 2-8.

Instruction stalls caused by data dependencies

are further discussed in Section 4.0.

FIGURE 2-8:

INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOV.b W0,[W1]

2. MOV.b [W1],PORTB

2a.Stall (NOP)

Fetch 1

Execute 1

Fetch 2

NOP

Stall

Execute 2

Fetch 3

3. MOV.b W0,PORTB

Execute 3

8. Interrupt recognition execution. Refer to

Section 5.0 for details on interrupts.

DS70082C-page 22

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

The non-restoring divide algorithm requires one cycle

for an initial dividend shift (for integer divides only), one

cycle per divisor bit, and a remainder/quotient correc-

tion cycle. The correction cycle is the last cycle of the

iteration loop, but must be performed (even if the

remainder is not required) because it may also adjust

the quotient. A consequence of this is that DIVF will

also produce a valid remainder (though it is of little use

in fractional arithmetic).

2.4

Divide Support

The dsPIC devices feature a 16/16-bit signed fractional

divide operation, as well as 32/16-bit and 16/16-bit

signed and unsigned integer divide operations, in the

form of single instruction iterative divides. The following

instructions and data sizes are supported:

1. DIVF– 16/16 signed fractional divide

2. DIV.sd– 32/16 signed divide

3. DIV.ud– 32/16 unsigned divide

4. DIV.sw– 16/16 signed divide

5. DIV.uw– 16/16 unsigned divide

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g. a

series of discrete divide instructions) will not function

correctly because the instruction flow depends on

RCOUNT. The divide instruction does not automatically

set up the RCOUNT value, and it must, therefore, be

explicitly and correctly specified in the REPEATinstruc-

tion, as shown in Table 2-1 (REPEAT will execute the

target instruction {operand value+1} times). The

REPEAT loop count must be set up for 18 iterations of

the DIV/DIVF instruction. Thus, a complete divide

operation requires 19 cycles.

The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or

sign-extended during the first iteration.

The quotient for all divide instructions is stored in W0,

and the remainder in W1. DIVand DIVFcan specify any

W register for both the 16-bit dividend and divisor. All

other divides can specify any W register for the 16-bit

divisor, but the 32-bit dividend must be in an aligned W

register pair, such as W1:W0, W3:W2, etc.

Note:

The Divide flow is interruptible. However,

the user needs to save the context as

appropriate.

TABLE 2-1:

DIVIDE INSTRUCTIONS

Instruction

Function

DIVF

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

DIV.sd

DIV.sw (or DIV.s)

DIV.ud

Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

DIV.uw (or DIV.u)

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 23

dsPIC30F

The DSP engine also has the capability to perform inher-

ent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUBand NEG.

2.5

DSP Engine

Concurrent operation of the DSP engine with MCU

instruction flow is not possible, though both the MCU

ALU and DSP engine resources may be used concur-

rently by the same instruction (e.g., ED and EDAC

instructions).

The DSP engine has various options selected through

various bits in the CPU Core Configuration Register

(CORCON), as listed below:

The DSP engine consists of a high speed 17-bit x

17-bit multiplier, a barrel shifter, and a 40-bit adder/

Subtractor (with two target accumulators, round and

saturation logic).

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for AccA (SATA).

5. Automatic saturation on/off for AccB (SATB).

Data input to the DSP engine is derived from one of the

following:

6. Automatic saturation on/off for writes to data

memory (SATDW).

1. Directly from the W array (registers W4, W5, W6

or W7) via the X and Y data buses for the MAC

class of instructions (MAC,MSC,MPY,MPY.N,

ED,EDAC,CLRand MOVSAC).

7. Accumulator Saturation mode selection

(ACCSAT).

2. From the X bus for all other DSP instructions.

Note:

For CORCON layout, see Table 4-3.

3. From the X bus for all MCU instructions which

use the barrel shifter.

A block diagram of the DSP engine is shown in

Figure 2-9.

Data output from the DSP engine is written to one of the

following:

1. The target accumulator, as defined by the DSP

instruction being executed.

2. The X bus for MAC, MSC, CLR and MOVSAC

accumulator writes, where the EA is derived

from W13 only. (MPY,MPY.N,EDand EDACdo

not offer an accumulator write option.)

3. The X bus for all MCU instructions which use the

barrel shifter.

DS70082C-page 24

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 2-9:

DSP ENGINE BLOCK DIAGRAM

S

a

40

16

40-bit Accumulator A

40-bit Accumulator B

40

Round

t

u

r

Logic

a

t

Carry/Borrow Out

Saturate

Adder

e

Carry/Borrow In

Negate

40

Barrel

Shifter

16

40

Sign-Extend

32

16

Zero Backfill

32

33

17-bit

Multiplier/Scaler

16

To/From W Array

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 25

dsPIC30F

32768 (0x8000) to 32767 (0x7FFF), including 0 (see

Figure 2-10). For a 32-bit integer, the data range is -

2,147,483,648 (0x8000 0000) to 2,147,483,645

(0x7FFF FFFF).

2.5.1

MULTIPLIER

The 17x17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. The respective number representation

formats are shown in Figure 2-10. Unsigned operands

are zero-extended into the 17th bit of the multiplier

input value. Signed operands are sign-extended into

the 17th bit of the multiplier input value. The output of

the 17x17-bit multiplier/scaler is a 33-bit value, which is

sign-extended to 40 bits. Integer data is inherently rep-

resented as a signed two’s complement value, where

the MSB is defined as a sign bit. Generally speaking,

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction, where the MSB is defined as a sign bit and the

radix point is implied to lie just after the sign bit (QX for-

mat). The range of an N-bit two’s complement fraction

1-N

with this implied radix point is -1.0 to (1-2 ). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF), including 0 and has a preci-

-5

sion of 3.01518x10 . In fractional mode, a 16x16 mul-

N-1

tiply operation generates a 1.31 product, which has a

the range of an N-bit two’s complement integer is -2

-10

N-1

precision of 4.65661x10

.

to 2

– 1. For a 16-bit integer, the data range is -

FIGURE 2-10:

16-BIT INTEGER AND FRACTIONAL MODES

Different Representations of 0x4001

Integer:

1

0

1

0

14

13

12

11

2 ....

2

14

0

0x4001= 2 + 2 = 16385

1.15 Fractional:

0

1

0

1

-15

0

-1

-2

-3

2 ...

2

-2

2

-1

-15

0x4001= 2 + 2 = 0.500030518

Certain multiply operations always operate on signed

data. These include the MAC/MSC, MPY[.N] and

ED[AC]instructions. The 40-bit adder/subtractor may

also optionally negate one of its operand inputs to

change the result sign (without changing the oper-

ands). This is used to create a multiply and subtract

(MSC) or multiply and negate (MPY.N) operation.

because of the implied radix point used by dsPIC30F

fractions. In Integer mode, multiplying two 16-bit inte-

gers produces a 32-bit integer result. However, multi-

plying two 1.15 values generates a 2.30 result. Since

the dsPIC30F uses 1.31 format for the accumulators,

a DSP multiply in Fractional mode also includes a left

shift by one bit to keep the radix point properly

aligned. This feature reduces the resolution of the

In the special case when both input operands are 1.15

-30

DSP multiplier to 2 , but has no other effect on the

fractions and equal to 0x8000(-1 ), the result of the

10

computation.

multiplication is corrected to 0x7FFFFFFF(as the clos-

est approximation to +1) by hardware, before it is used.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies. Additional data

paths are provided to allow these instructions to write

the result back into the W array and X data bus (via the

W array). These paths are placed prior to the data

scaler. The IF bit in the CORCON register, therefore,

only affects the result of the MACclass of DSP instruc-

tions. All other multiply operations are assumed to be

integer operations. If the user executes a MACinstruc-

tion on fractional data without clearing the IF bit, the

result must be explicitly shifted left by the user program

after multiplication in order to obtain the correct result.

It should be noted that with the exception of DSP mul-

tiplies, the dsPIC30F ALU operates identically on inte-

ger and fractional data. Namely, an addition of two

integers will yield the same result (binary number) as

the addition of two fractional numbers. The only differ-

ence is how the result is interpreted by the user. How-

ever, multiplies performed by DSP operations are

different. In these instructions, data format selection is

made with the IF bit (CORCON<0>) and US bits

(CORCON<12>), and it must be set accordingly (‘0’

for Fractional mode, ‘1’ for Integer mode in the case

of the IF bit, and ‘0’ for signed mode, ‘1’ for unsigned

mode in the case of the US bit). This is required

DS70082C-page 26

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

The MUL instruction may be directed to use byte or

word sized operands. Byte operands will direct a 16-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/Subtractor. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATEN, OVBTEN) in

the INTCON1 register (refer to Section 5.0) is set. This

allows the user to take immediate action, for example,

to correct system gain.

2.5.2

DATA ACCUMULATORS AND

ADDER/SUBTRACTOR

The data accumulator consists of a 40-bit adder/

subtractor with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADDand LACinstructions, the data to be

accumulated or loaded can be optionally scaled via the

barrel shifter, prior to accumulation.

The SA and SB bits are modified each time data passes

through the adder/subtractor, but can only be cleared by

the user. When set, they indicate that the accumulator

has overflowed its maximum range (bit 31 for 32-bit sat-

uration, or bit 39 for 40-bit saturation) and will be satu-

rated (if saturation is enabled). When saturation is not

enabled, SA and SB default to bit 39 overflow and thus

indicate that a catastrophic overflow has occurred. If the

COVTE bit in the INTCON1 register is set, SA and SB

bits will generate an arithmetic warning trap when satu-

ration is disabled.

2.5.2.1

Adder/Subtractor, Overflow and

Saturation

The adder/subtractor is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtraction, the carry/borrow input is active low and the

other input is complemented. The adder/subtractor

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the status register.

The overflow and saturation status bits can optionally

be viewed in the Status Register (SR) as the logical OR

of OA and OB (in bit OAB) and the logical OR of SA and

SB (in bit SAB). This allows programmers to check one

bit in the Status Register to determine if either accumu-

lator has overflowed, or one bit to determine if either

accumulator has saturated. This would be useful for

complex number arithmetic which typically uses both

the accumulators.

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

The device supports three Saturation and Overflow

modes.

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic loads the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

Six status register bits have been provided to support

saturation and overflow; they are:

1. OA:

AccA overflowed into guard bits

2. OB:

AccB overflowed into guard bits

3. SA:

AccA saturated (bit 31 overflow and saturation)

or

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally nega-

tive 1.31 value (0x0080000000) into the target

accumulator. The SA or SB bit is set and remains

set until cleared by the user. When this Saturation

mode is in effect, the guard bits are not used (so

the OA, OB or OAB bits are never set).

AccA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

4. SB:

AccB saturated (bit 31 overflow and saturation)

or

AccB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 27

dsPIC30F

3. Bit 39 Catastrophic Overflow

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the contents

of the target accumulator to data memory, via the X bus

(subject to data saturation, see Section 2.5.2.4). Note

that for the MACclass of instructions, the accumulator

write back operation will function in the same manner,

addressing combined MCU (X and Y) data space

though the X bus. For this class of instructions, the data

is always subject to rounding.

The bit 39 overflow status bit from the adder is

used to set the SA or SB bit, which remain set

until cleared by the user. No saturation operation

is performed and the accumulator is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

overflow can initiate a trap exception.

2.5.2.2

Accumulator ‘Write Back’

2.5.2.4

Data Space Write Saturation

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator that is not targeted by the instruction

into data space memory. The write is performed across

the X bus into combined X and Y address space. The

following addressing modes are supported:

In addition to adder/subtractor saturation, writes to data

space may also be saturated, but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combined and used to select the appropriate 1.15 frac-

tional value as output to write to data space memory.

1. W13, Register Direct:

The rounded contents of the non-target accumula-

tor are written into W13 as a 1.15 fraction.

If the SATDW bit in the CORCON register is set, data

(after rounding or truncation) is tested for overflow and

adjusted accordingly. For input data greater than

0x007FFF, data written to memory is forced to the

maximum positive 1.15 value, 0x7FFF. For input data

less than 0xFF8000, data written to memory is forced

to the maximum negative 1.15 value, 0x8000. The MS

bit of the source (bit 39) is used to determine the sign

of the operand being tested.

2. [W13]+=2, Register Indirect with Post-Increment:

The rounded contents of the non-target accumu-

lator are written into the address pointed to by

W13 as

a

1.15 fraction. W13 is then

incremented by 2 (for a word write).

2.5.2.3

Round Logic

The round logic is a combinational block, which per-

forms a conventional (biased) or convergent (unbiased)

round function during an accumulator write (store). The

Round mode is determined by the state of the RND bit

in the CORCON register. It generates a 16-bit, 1.15 data

value which is passed to the data space write saturation

logic. If rounding is not indicated by the instruction, a

truncated 1.15 data value is stored and the LS Word is

simply discarded.

If the SATDW bit in the CORCON register is not set, the

input data is always passed through unmodified under

all conditions.

2.5.3

BARREL SHIFTER

The barrel shifter is capable of performing up to 15-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators or the X bus (to support multi-bit

shifts of register or memory data).

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and adds it to the ACCxH word (bits 16

through 31 of the accumulator). If the ACCxL word (bits

0 through 15 of the accumulator) is between 0x8000

and 0xFFFF (0x8000 included), ACCxH is incre-

mented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this algo-

rithm is that over a succession of random rounding

operations, the value will tend to be biased slightly

positive.

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of 0will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right shifts, and bit positions 0 to 15 for left shifts.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000. If this is the case, the LS bit (bit

16 of the accumulator) of ACCxH is examined. If it is ‘1’,

ACCxH is incremented. If it is ‘0’, ACCxH is not modi-

fied. Assuming that bit 16 is effectively random in

nature, this scheme will remove any rounding bias that

may accumulate.

DS70082C-page 28

Advance Information

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dsPIC30F

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE), for all accesses other than TBLRD/TBLWT,

which use TBLPAG<7> to determine user or configura-

tion space access. In Table 3-1, Read/Write instruc-

tions, bit 23 allows access to the Device ID, the User ID

and the configuration bits. Otherwise, bit 23 is always

clear.

3.0

MEMORY ORGANIZATION

3.1

Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction EA, or data space EA, when pro-

gram space is mapped into data space, as defined by

Table 3-1. Note that the program space address is

incremented by two between successive program

words, in order to provide compatibility with data space

addressing.

Note:

The address map shown in Figure 3-5 is

conceptual, and the actual memory con-

figuration may vary across individual

devices depending on available memory.

TABLE 3-1:

PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

<22:16> <15> <14:1>

PC<22:1>

Access

Space

Access Type

<23>

<0>

Instruction Access

User

0

TBLRD/TBLWT

User

TBLPAG<7:0>

Data EA <15:0>

(TBLPAG<7> = 0)

TBLRD/TBLWT

Configuration

TBLPAG<7:0>

Data EA <15:0>

(TBLPAG<7> = 1)

Program Space Visibility User

0

PSVPAG<7:0>

Data EA <14:0>

FIGURE 3-1:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using

Program

Counter

Program Counter

0

Select

1

EA

Using

0

PSVPAG Reg

Program

Space

Visibility

8 bits

15 bits

EA

Using

1/0

TBLPAG Reg

8 bits

Table

Instruction

16 bits

User/

Byte

24-bit EA

Configuration

Space

Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 29

dsPIC30F

A set of Table Instructions are provided to move byte or

word sized data to and from program space.

3.1.1

PROGRAM SPACE ALIGNMENT

AND DATA ACCESS USING TABLE

INSTRUCTIONS

1. TBLRDL:Table Read Low

Word: Read the LS Word of the program

address;

This architecture fetches 24-bit wide program memory.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be present in program space.

P<15:0> maps to D<15:0>.

Byte: Read one of the LS Bytes of the program

address;

There are two methods by which program space can

be accessed; via special table instructions, or through

the remapping of a 16K word program space page into

the upper half of data space (see Section 3.1.2). The

TBLRDLand TBLWTLinstructions offer a direct method

of reading or writing the LS Word of any address within

program space, without going through data space. The

TBLRDHand TBLWTHinstructions are the only method

whereby the upper 8 bits of a program space word can

be accessed as data.

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> maps to the destination byte when byte

select = 1.

2. TBLWTL:Table Write Low (refer to Section 6.0

for details on Flash Programming).

3. TBLRDH:Table Read High

Word: Read the MS Word of the program

address;

P<23:16> maps to D<7:0>; D<15:8> always

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the LS Data Word,

and TBLRDH and TBLWTH access the space which

contains the MS Data Byte.

be = 0.

Byte: Read one of the MS Bytes of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH:Table Write High (refer to Section 6.0

for details on Flash Programming).

Figure 3-1 shows how the EA is created for table oper-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

FIGURE 3-2:

PROGRAM DATA TABLE ACCESS (LS WORD)

PC Address

23

8

0

16

0x000000

0x000002

0x000004

0x000006

00000000

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

Program Memory

‘Phantom’ Byte

(Read as ‘0’).

TBLRDL.B (Wn<0> = 1)

DS70082C-page 30

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 3-3:

PROGRAM DATA TABLE ACCESS (MS BYTE)

TBLRDH.W

PC Address

23

8

16

0

0x000000

0x000002

0x000004

0x000006

00000000

TBLRDH.B (Wn<0> = 0)

Program Memory

‘Phantom’ Byte

(Read as ‘0’)

TBLRDH.B (Wn<0> = 1)

Note that by incrementing the PC by 2 for each pro-

gram memory word, the LS 15 bits of data space

addresses directly map to the LS 15 bits in the corre-

sponding program space addresses. The remaining

bits are provided by the Program Space Visibility Page

register, PSVPAG<7:0>, as shown in Figure 3-4.

3.1.2

PROGRAM SPACE VISIBILITY

FROM DATA SPACE

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space, without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/Hinstructions).

Note:

PSV access is temporarily disabled during

Table Reads/Writes.

Program space access through the data space occurs

if the MS bit of the data space EA is set and program

space visibility is enabled, by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.5, DSP Engine.

For instructions that use PSV which are executed

outside a REPEAT loop:

• The following instructions will require one instruc-

tion cycle in addition to the specified execution

time:

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetches are required.

- MACclass of instructions with data operand

pre-fetch

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP operation uses program space mapping to access

this memory region, Y data space should typically con-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) data.

- MOVinstructions

- MOV.Dinstructions

• All other instructions will require two instruction

cycles in addition to the specified execution time

of the instruction.

For instructions that use PSV which are executed

inside a REPEAT loop:

Although each data space address, 0x8000 and

higher, maps directly into a corresponding program

memory address (see Figure 3-4), only the lower

16-bits of the 24-bit program word are used to contain

the data. The upper 8 bits should be programmed to

force an illegal instruction to maintain machine robust-

ness. Refer to the Programmer’s Reference Manual

(DS70030) for details on instruction encoding.

• The following instances will require two instruction

cycles in addition to the specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEAT loop will allow

the instruction, accessing data using PSV, to

execute in a single cycle.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 31

dsPIC30F

FIGURE 3-4:

DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Program Space

Data Space

0x0000

(1)

PSVPAG

0x21

8

15

EA<15> =

0

Data

16

Space

EA

0x108000

0x108200

0x8000

15

EA<15> = 1

23

15

0

Address

Concatenation

15

23

Upper half of Data

Space is mapped

into Program Space

0x10FFFF

0xFFFF

BSET CORCON,#2

; PSV bit set

MOV

#0x21, W0

W0, PSVPAG

0x8200, W0

; Set PSVPAG register

; Access program memory location

; using a data space access

Data Read

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

DS70082C-page 32

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dsPIC30F

FIGURE 3-5:

SAMPLE PROGRAM

SPACE MEMORY MAP

3.2

Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), or as one unified linear address range (for MCU

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

Reset - GOTOInstruction

Reset - Target Address

000000

000002

000004

Vector Tables

Interrupt Vector Table

3.2.1

DATA SPACES

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

00007E

000080

000084

0000FE

000100

Reserved

Alternate Vector Table

User Flash

Program Memory

(48K instructions)

017FFE

018000

The X data space also supports Modulo Addressing for

all instructions, subject to Addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

Reserved

(Read 0’s)

7FEFFE

7FF000

Data EEPROM

(4 Kbytes)

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC,MAC,MOVSAC,MPY, MPY.Nand MSC) to pro-

vide two concurrent data read paths. No writes occur

across the Y bus. This class of instructions dedicates

two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address space is considered a combination of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

7FFFFE

800000

Reserved

The Y data space can only be used for the data pre-

fetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automated circular buffers. Of course, all other instruc-

tions can access the Y data address space through the

X data path, as part of the composite linear space.

8005BE

8005C0

UNITID (32 instr.)

8005FE

800600

Reserved

The boundary between the X and Y data spaces is

defined as shown in Figure 3-8 and is not user pro-

grammable. Should an EA point to data outside its own

assigned address space, or to a location outside phys-

ical memory, an all-zero word/byte will be returned. For

example, although Y address space is visible by all

non-MAC instructions using any Addressing mode, an

attempt by a MAC instruction to fetch data from that

space, using W8 or W9 (X space pointers), will return

0x0000.

F7FFFE

Device Configuration

Registers

F80000

F8000E

F80010

Reserved

FEFFFE

FF0000

FFFFFE

DEVID (2)

Note: These address boundaries may vary from one device

to another.

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dsPIC30F

TABLE 3-2:

EFFECT OF INVALID

MEMORY ACCESSES

FIGURE 3-6:

DATA ALIGNMENT

MS Byte

LS Byte

15

8 7

0

Attempted Operation

Data Returned

0000

0002

0004

0001

Byte 1

Byte 3

Byte 5

Byte 0

Byte 2

Byte 4

EA = an unimplemented address

0x0000

0003

0005

W8 or W9 used to access Y data

space in a MACinstruction

W10 or W11 used to access X

0x0000

data space in a MACinstruction

All byte loads into any W register are loaded into the LS

Byte. The MSB is not modified.

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

A sign-extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

zero-extend (ZE) instruction on the appropriate

address.

3.2.2

DATA SPACE WIDTH

The core data width is 16-bits. All internal registers are

organized as 16-bit wide words. Data space memory is

organized in byte addressable, 16-bit wide blocks.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words.

3.2.3

DATA ALIGNMENT

To help maintain backward compatibility with

PICmicro^®devices and improve data space memory

usage efficiency, the dsPIC30F instruction set supports

both word and byte operations. Data is aligned in data

memory and registers as words, but all data space EAs

resolve to bytes. Data byte reads will read the complete

word, which contains the byte, using the LS bit of any

EA to determine which byte to select. The selected byte

is placed onto the LS Byte of the X data path (no byte

accesses are possible from the Y data path as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode,

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

3.2.4

DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MACclass of instructions, the X block consists of the 64

Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions,

the X block consists of the 64 Kbyte data address

space excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one composite address space.

The MACclass instructions extract the Y address space

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

addressed using W8 and W9. Both address spaces are

concurrently accessed only with the MAC class

instructions.

As a consequence of this byte accessibility, all effective

address calculations (including those generated by the

DSP operations, which are restricted to word sized

data) are internally scaled to step through word aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode,

[Ws++], will result in a value of Ws+1 for byte opera-

tions and Ws+2 for word operations.

An example data space memory map is shown in

Figure 3-8.

All word accesses must be aligned to an even address.

Mis-aligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Should a mis-

aligned read or write be attempted, an Address Error

trap will be generated. If the error occurred on a read,

the instruction underway is completed, whereas if it

occurred on a write, the instruction will be executed but

the write will not occur. In either case, a trap will then

be executed, allowing the system and/or user to exam-

ine the machine state prior to execution of the address

fault.

DS70082C-page 34

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dsPIC30F

3.2.5

NEAR DATA SPACE

3.2.6

SOFTWARE STACK

An 8 Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000and 0x1FFF, which is

directly addressable via a 13-bit absolute address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

addressable indirectly. Additionally, the whole of X data

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

The dsPIC device contains a software stack. W15 is

used as the Stack Pointer.

There is a Stack Pointer Limit register (SPLIM) associ-

ated with the stack pointer. SPLIM is uninitialized at

Reset. As is the case for the stack pointer, SPLIM<0>

is forced to ‘0’, because all stack operations must be

word aligned. Whenever an effective address (EA) is

generated using W15 as a source or destination

pointer, the address thus generated is compared with

the value in SPLIM. If the contents of the Stack Pointer

(W15) and the SPLIM register are equal and a push

operation is performed, a Stack Error Trap will not

occur. The Stack Error Trap will occur on a subsequent

push operation. Thus, for example, if it is desirable to

cause a Stack Error Trap when the stack grows beyond

address 0x2000in RAM, initialize the SPLIM with the

value, 0x1FFE.

The stack pointer always points to the first available

free word and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops and

post-increments for stack pushes, as shown in

Figure 3-7. Note that for a PC push during any CALL

instruction, the MSB of the PC is zero-extended before

the push, ensuring that the MSB is always clear.

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

Similarly, a Stack Pointer Underflow (Stack Error) trap

is generated when the stack pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 3-7:

CALLSTACK FRAME

0x0000

15

0

PC<15:0>

W15 (before CALL)

W15 (after CALL)

000000000PC<22:16>

POP: [--W15]

PUSH: [W15++]

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dsPIC30F

FIGURE 3-8:

SAMPLE DATA SPACE MEMORY MAP

LS Byte

Address

MS Byte

Address

16 bits

MSB

LSB

0x0000

0x0001

2 Kbyte

SFR Space

0x07FE

0x0800

0x07FF

0x0801

8 Kbyte

Near

Data

X Data RAM (X)

Space

8 Kbyte

0x17FF

0x1801

0x17FE

0x1800

SRAM Space

0x1FFF

0x1FFE

Y Data RAM (Y)

0x27FF

0x2801

0x27FE

0x2800

0x8001

0x8000

X Data

Unimplemented (X)

Optionally

Mapped

into Program

Memory

0xFFFE

0xFFFF

Note: The address map shown is conceptual, and may vary across individual devices depending on

available memory.

DS70082C-page 36

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dsPIC30F

FIGURE 3-9:

DATA SPACE FOR MCU AND DSP (MACCLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

UNUSED

Y SPACE

UNUSED

(Y SPACE)

UNUSED

Non-MACClass Ops (Read)

MACClass Ops (Read)

Indirect EA from any W

Indirect EA from W8, W9

Indirect EA from W10, W11

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dsPIC30F

NOTES:

DS70082C-page 40

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dsPIC30F

low overhead circular buffers. The X WAGU also sup-

ports Bit-Reversed Addressing to facilitate FFT data

reorganization.

4.0

ADDRESS GENERATOR UNITS

The dsPIC core contains two independent address

generator units: the X AGU and Y AGU. Further, the X

AGU has two parts: X RAGU (Read AGU) and X

WAGU (Write AGU). The X RAGU and X WAGU sup-

port byte and respectively, for both MCU and DSP

instructions. The Y AGU supports word sized data

reads for the DSP MACclass of instructions only. They

are each capable of supporting two types of data

addressing:

When executing instructions which require two source

operands to be concurrently fetched (i.e., the MACclass

of DSPinstructions), both the X RAGU and Y AGU are

used simultaneously and the data space is split into 2

independent address spaces, X and Y. The Y AGU sup-

ports Register Indirect Post-Modified and Modulo

Addressing only. Note that the data write phase of the

MACclass of instruction does not split X and Y address

space. The write EA is calculated using the X WAGU

and the data space is configured for full 64 Kbyte

access.

• Linear Addressing

• Modulo (Circular) Addressing

In addition, the X WAGU can support:

• Bit-Reversed Addressing

In the Split Data Space mode, some W register address

pointers are dedicated to X RAGU, and others to Y

AGU. The EAs of each operand must, therefore, be

restricted within different address spaces. If they are

not, one of the EAs will be outside the address space

of the corresponding data space (and will fetch the bus

default value, 0x0000).

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

addressing is only applicable to data space addresses.

4.1

Data Space Organization

Although the data space memory is organized as 16-bit

words, all effective addresses (EAs) are byte

addresses. Instructions can thus access individual

bytes, as well as properly aligned words. Word

addresses must be aligned at even boundaries. Mis-

aligned word accesses are not supported, and if

attempted, will initiate an address error trap.

4.2

Instruction Addressing Modes

The Addressing modes in Table 4-1 form the basis of

the Addressing modes optimized to support the specific

features of individual instructions. The Addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

When executing instructions which require just one

source operand to be fetched from data space, the X

RAGU and X WAGU are used to calculate the effective

address. The X RAGU and X WAGU can generate any

address in the 64 Kbyte data space. They support all

MCU Addressing modes and Modulo Addressing for

Some Addressing mode combinations may lead to a

one-cycle stall during instruction execution, or are not

allowed, as discussed in Section 4.3.

TABLE 4-1:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode

Description

File Register Direct

Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the EA.

Register Indirect

Register Indirect Post-modified

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

Register Indirect with Literal Offset

The sum of Wn and a literal forms the EA.

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dsPIC30F

In summary, the following Addressing modes are

supported by Move and Accumulator instructions:

4.2.1

FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory. These memory locations are

known as File Registers. Most file register instructions

employ a working register W0, which is denoted as

WREG in these instructions. The destination is typically

either the same file register, or WREG (with the excep-

tion of the MULinstruction), which writes the result to a

register or register pair. The MOVinstruction can use a

16-bit address field.

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note:

Not all instructions support all the

Addressing modes given above. Individual

instructions may support different subsets

of these Addressing modes.

4.2.2

MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the

Addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be W register,

fetched from data memory, or 5-bit literal. In two-

operand instructions, the result location is the same as

that of one of the operands. Certain MCU instructions

are one-operand operations. The following Addressing

modes are supported by MCU instructions:

4.2.4

MACINSTRUCTIONS

The dual source operand DSP instructions (CLR,ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to as MACinstructions, utilize a simplified set of

Addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand pre-fetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will always be directed to the

Y AGU. The effective addresses generated (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9 and Y data space

for W10 and W11.

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

Note:

Not all instructions support all the

Addressing modes given above. Individual

instructions may support different subsets

of these Addressing modes.

Note:

Register Indirect with Register Offset

Addressing is only available for W9 (in X

space) and W11 (in Y space).

4.2.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

In summary, the following Addressing modes are

supported by the MACclass of instructions:

Move instructions and the DSP Accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, Move and Accumulator instructions also support

Register Indirect with Register Offset Addressing

mode, also referred to as Register Indexed mode.

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.2.5

OTHER INSTRUCTIONS

Note:

For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared between both source and

destination (but typically only used by

one).

Besides the various Addressing modes outlined above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADDAcc, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as NOP, do not have any

operands.

DS70082B-page 42

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dsPIC30F

4.3.2

RAW DEPENDENCY DETECTION

4.3

Instruction Stalls

During the instruction pre-decode, the core determines

if any address register dependency is imminent across

an instruction boundary. The stall detection logic com-

pares the W register (if any) used for the destination EA

of the instruction currently being executed, with the W

register to be used by the source EA (if any) of the pre-

fetched instruction. As the W registers are also memory

mapped, the stall detection logic also derives an SFR

address from the W register being used by the destina-

tion EA, and determines whether this address is being

issued during the write phase of the instruction cur-

rently being executed.

4.3.1

INTRODUCTION

In order to maximize data space, EA calculation and

operand fetch time, the X data space read and write

accesses are partially pipelined. The latter half of the

read phase overlaps the first half of the write phase of

an instruction, as shown in Section 2.

Address register data dependencies, also known as

‘Read After Write’ (RAW) dependencies, may therefore

arise between successive read and write operations

using common registers. They occur across instruction

boundaries and are detected by the hardware.

When it observes a match between the destination and

source registers, a set of rules are applied to decide

whether or not to stall the instruction by one cycle.

Table 4-2 lists out the various RAW conditions which

cause an instruction execution stall.

An example of a RAW dependency is a write operation

(in the current instruction) that modifies W5, followed

by a read operation (in the next instruction) that uses

W5 as a source address pointer. W5 will not be valid for

the read operation until the earlier write completes.

This problem is resolved by stalling the instruction exe-

cution for one instruction cycle, thereby allowing the

write to complete before the next read is started.

TABLE 4-2:

Destination

RAW DEPENDENCY RULES (DETECTION BY HARDWARE)

Source Addressing

Mode Using Wn

Examples

(Wn = W2)

Addressing Mode

Using Wn

Status

Direct

No Stall ADD.w W0, W1, W2

MOV.w W2, W3

Direct

Indirect

Stall

ADD.w W0, W1, W2

MOV.w [W2], W3

Direct

Indirect with Pre- or

Post-Modification

ADD.w W0, W1, W2

MOV.w [W2++], W3

Indirect

Direct

No Stall ADD.w W0, W1, [W2]

MOV.w W2, W3

Indirect

No Stall ADD.w W0, W1, [W2]

MOV.w [W2], W3

Stall

ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w [W2], W3 ; (i.e., if W2 = addr. of W2)

Indirect with Pre- or

Post-Modification

No Stall ADD.w W0, W1, [W2]

MOV.w [W2++], W3

Indirect with Pre- or

Post-Modification

Stall

ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)

MOV.w [W2++], W3 ; (i.e., if W2 = addr. of W2)

Indirect with Pre- or Direct

Post-Modification

No Stall ADD.w W0, W1, [W2++]

MOV.w W2, W3

Indirect with Pre- or Indirect

Post-Modification

Stall

ADD.w W0, W1, [W2++]

MOV.w [W2], W3

Indirect with Pre- or Indirect with Pre- or

ADD.w W0, W1, [W2++]

MOV.w [W2++], W3

Post-Modification

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dsPIC30F

For example, if the start address was chosen to be

0x2000, then the X/YMODEND would be set to

(0x2000+ 0x0064– 1) = 0x2063.

4.4

Modulo Addressing

Modulo addressing is a method of providing an auto-

mated means to support circular data buffers using

hardware. The objective is to remove the need for soft-

ware to perform data address boundary checks when

executing tightly looped code, as is typical in many

DSP algorithms.

Note:

‘Start address’ refers to the smallest

address boundary of the circular buffer.

The first access of the buffer may be at

any address within the modulus range

(see Section 4.4.4).

Modulo addressing can operate in either data or pro-

gram space (since the data pointer mechanism is essen-

tially the same for both). One circular buffer can be

supported in each of the X (which also provides the

pointers into Program space) and Y data spaces. Mod-

ulo addressing can operate on any W register pointer.

However, it is not advisable to use W14 or W15 for Mod-

ulo addressing, since these two registers are used as

the Stack Frame Pointer and Stack Pointer, respectively.

In the case of a decrementing buffer, the last ‘N’ bits of

the data buffer end address must be ones. There are

no such restrictions on the start address of a decre-

menting buffer. For example, if the buffer size (modulus

value) is chosen to be 100 bytes (0x64), then the buffer

end address for a decrementing buffer must contain 7

Least Significant ones. Valid end addresses may,

therefore, be 0xXXFF and 0xXX7F, where ‘X’ is any

hexadecimal value. Subtracting the buffer length from

this value and adding 1 will give the start address to be

written into X/YMODSRT. For example, if the end

address was chosen to be 0x207F, then the start

address would be (0x207F – 0x0064+1) = 0x201C,

which is the first physical address of the buffer.

In general, any particular circular buffer can only be

configured to operate in one direction, as there are cer-

tain restrictions on the buffer start address (for incre-

menting buffers) or end address (for decrementing

buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for buff-

ers which have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bi-Directional mode, (i.e., address bound-

ary checks will be performed on both the lower and

upper address boundaries).

Note:

Y-space modulo addressing EA calcula-

tions assume word-sized data (LS bit of

every EA is always clear).

The length of a circular buffer is not directly specified. It

is determined by the difference between the corre-

sponding start and end addresses. The maximum pos-

sible length of the circular buffer is 32K words

(64 Kbytes).

4.4.1

START AND END ADDRESS

The Modulo addressing scheme requires that a starting

and an end address be specified and loaded into the

16-bit modulo buffer address registers: XMODSRT,

XMODEND, YMODSRT, YMODEND (see Table 3-3).

A write operation to the MODCON register should not

be immediately followed by an indirect read operation

using any W register.

Note:

The start and end addresses are the first

and last byte addresses of the buffer (irre-

spective of whether it is a word or byte

buffer, or an increasing or decreasing

buffer). Moreover, the start address must

be even and the end address must be odd

(for both word and byte buffers).

Note 1: Using a POP instruction to pop the con-

tents of the top-of-stack (TOS) location

into MODCON, also constitutes a write to

MODCON. Therefore, the instruction

immediately following such a POPcannot

be any instruction performing an indirect

read operation.

If the length of an incrementing buffer is greater than

2: It should be noted that some instructions

perform an indirect read operation implic-

itly. These are: POP, RETURN, RETFIE,

RETLWand ULNK.

N-1

N

M = 2 , but not greater than M = 2 bytes, then the

last ’N’ bits of the data buffer start address must be

zeros. There are no such restrictions on the end

address of an incrementing buffer. For example, if the

buffer size (modulus value) is chosen to be 100 bytes

(0x64), then the buffer start address for an increment-

ing buffer must contain 7 Least Significant zeros. Valid

start addresses may, therefore, be 0xXX00 and

0xXX80, where ‘X’ is any hexadecimal value. Adding

the buffer length to this value and subtracting 1 will

give the end address to be written into X/YMODEND.

DS70082B-page 44

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dsPIC30F

The X Address Space Pointer W register (XWM) to

which modulo addressing is to be applied, is stored in

MODCON<3:0> (see Table 3-3). Modulo addressing is

enabled for X data space when XWM is set to any value

other than 15 and the XMODEN bit is set at

MODCON<15>.

4.4.2

W ADDRESS REGISTER

SELECTION

The Modulo and Bit-Reversed Addressing Control reg-

ister MODCON<15:0> contains enable flags as well as

a W register field to specify the W address registers.

The XWM and YWM fields select which registers will

operate with modulo addressing. If XWM = 15, X RAGU

and X WAGU modulo addressing are disabled. Simi-

larly, if YWM = 15, Y AGU modulo addressing is dis-

abled.

The Y Address Space Pointer W register (YWM) to

which modulo addressing is to be applied, is stored in

MODCON<7:4>. Modulo addressing is enabled for Y

data space when YWM is set to any value other than 15

and the YMODEN bit is set at MODCON<14>.

Note:

The XMODSRT and XMODEND registers,

and the XWM register selection, are

shared between X RAGU and X WAGU.

FIGURE 4-1:

INCREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE

Byte

MOV

DO

#0x1100,W0

W0, XMODSRT

#0x1163,W0

W0,MODEND

#0x8001,W0

W0,MODCON

#0x0000,W0

#0x1110,W1

AGAIN,#0x31

W0, [W1++]

Address

;set modulo start address

;set modulo end address

0x1100

;enable W1, X AGU for modulo

;W0 holds buffer fill value

;point W1 to buffer

;fill the 50 buffer locations

;fill the next location

;increment the fill value

MOV

AGAIN: INC

W0,W0

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032words

 2003 Microchip Technology Inc.

Advance Information

DS70082B-page 45

dsPIC30F

FIGURE 4-2:

DECREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE

Byte

Address

MOV

DO

#0x11D0,W0

#0, XMODSRT

0x11FF,W0

W0,XMODEND

#0x8001,W0

W0,MODCON

#0x000F,W0

#0x11E0,W1

AGAIN,#0x17

W0, [W1--]

;set modulo start address

;set modulo end address

;enable W1, X AGU for modulo

;W0 holds buffer fill value

;point W1 to buffer

0x11D0

;fill the 24 buffer locations

;fill the next location

;decrement the fill value

MOV

AGAIN: DEC

W0,W0

0x11FF

Start Addr = 0x11D0

End Addr = 0x11FF

Length = 0x0018words

4.4.3

MODULO ADDRESSING

APPLICABILITY

4.4.4

MODULO ADDRESSING

RESTRICTIONS

Modulo addressing can be applied to the effective

address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries check for addresses less than or greater than the

upper (for incrementing buffers) and lower (for decre-

menting buffers) boundary addresses (not just equal

to). Address changes may, therefore, jump over bound-

aries and still be adjusted correctly (see Section 4.4.4

for restrictions).

For an incrementing buffer the circular buffer start

address (lower boundary) is arbitrary, but must be at a

‘zero’ power-of-two boundary (see Section 4.4.1). For

a decrementing buffer, the circular buffer end address

is arbitrary, but must be at a ‘ones’ boundary.

There are no restrictions regarding how much an EA

calculation can exceed the address boundary being

checked and still be successfully corrected.

Note:

The modulo corrected effective address is

written back to the register only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the Effective Address.

When an address offset (e.g., [W7+W2]) is

used, modulo address correction is per-

formed, but the contents of the register

remains unchanged.

DS70082B-page 46

Advance Information

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dsPIC30F

Once configured, the direction of successive

addresses into a buffer should not be changed.

Although all EAs will continue to be generated correctly

irrespective of offset sign, only one address boundary

is checked for each type of buffer. Thus, if a buffer is set

up to be an incrementing buffer by choosing an appro-

priate starting address, then correction of the effective

address will be performed by the AGU at the upper

address boundary, but no address correction will occur

if the EA crosses the lower address boundary. Similarly,

for a decrementing boundary, address correction will

be performed by the AGU at the lower address bound-

ary, but no address correction will take place if the EA

crosses the upper address boundary. The circular

buffer pointer may be freely modified in both directions

without a possibility of out-of-range address access

only when the start address satisfies the condition for

an incrementing buffer (last ‘N’ bits are zeroes) and the

end address satisfies the condition for a decrementing

buffer (last ‘N’ bits are ones). Thus, the modulo

addressing capability is truly bi-directional only for

modulo-2 length buffers.

2. the BREN bit is set in the XBREV register and

3. the Addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

N

If the length of a bit-reversed buffer is M = 2 bytes,

then the last ’N’ bits of the data buffer start address

must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

data buffer size.

Note:

All Bit-Reversed EA calculations assume

word sized data (LS bit of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

When enabled, bit-reversed addressing will only be

executed for register indirect with pre-increment or

post-increment addressing and word sized data writes.

It will not function for any other addressing mode or for

byte-sized data, and normal addresses will be gener-

ated instead. When bit-reversed addressing is active,

the W address pointer will always be added to the

address modifier (XB) and the offset associated with

the register Indirect Addressing mode will be ignored.

In addition, as word sized data is a requirement, the LS

bit of the EA is ignored (and always clear).

4.5

Bit-Reversed Addressing

Bit-Reversed addressing is intended to simplify data re-

ordering for radix-2 FFT algorithms. It is supported by

the X WAGU only (i.e., for data writes only).

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed.

The address source and destination are kept in normal

order. Thus, the only operand requiring reversal is the

modifier.

Note:

Modulo addressing and bit-reversed

addressing should not be enabled

together. In the event that the user

attempts to do this, bit reversed address-

ing will assume priority when active for the

X WAGU, and X WAGU modulo address-

ing will be disabled. However, modulo

addressing will continue to function in the

X RAGU.

4.5.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed addressing is enabled when:

If bit-reversed addressing has already been enabled by

setting the BREN (XBREV<15>) bit, then a write to the

XBREV register should not be immediately followed by

an indirect read operation using the W register that has

been designated as the bit-reversed pointer.

1. BWM (W register selection) in the MODCON

register is any value other than 15 (the stack can

not be accessed using bit-reversed addressing)

and

FIGURE 4-3:

BIT-REVERSED ADDRESS EXAMPLE

Sequential Address

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1

0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

b2 b3 b4

0

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1

Bit-Reversed Address

Pivot Point

XB = 0x0008for a 16-word Bit-Reversed Buffer

 2003 Microchip Technology Inc.

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DS70082B-page 47

dsPIC30F

TABLE 4-3:

BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal

Bit-Reversed

Address

A3

0

1

A2

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Decimal

A3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A2

0

1

0

1

0

1

0

1

A1

A0

0

1

Decimal

0

1

0

1

0

1

0

1

0

1

0

8

2

4

3

12

2

4

5

10

6

7

14

1

8

9

10

11

12

13

14

15

5

13

3

11

7

15

TABLE 4-4:

BIT-REVERSED ADDRESS MODIFIER VALUES

Buffer Size (Words)

XB<14:0> Bit-Reversed Address Modifier Value

32768

16384

8192

4096

2048

1024

512

256

128

64

0x4000

0x2000

0x1000

0x0800

0x0400

0x0200

0x0100

0x0080

0x0040

0x0020

0x0010

0x0008

0x0004

0x0002

0x0001

32

16

8

4

2

DS70082B-page 48

Advance Information

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dsPIC30F

All interrupt sources can be user assigned to one of 7

priority levels, 1 through 7, via the IPCx registers.

Each interrupt source is associated with an interrupt

vector, as shown in Figure 5-2. Levels 7 and 1 repre-

sent the highest and lowest maskable priorities,

respectively.

5.0

INTERRUPTS

The dsPIC30F Motor Control and Power Conversion

Family has up to 44 interrupt sources and 4 processor

exceptions (traps), which must be arbitrated based on

a priority scheme.

The CPU is responsible for reading the Interrupt Vec-

tor Table (IVT) and transferring the address contained

in the interrupt vector to the program counter. The

interrupt vector is transferred from the program data

bus into the program counter, via a 24-bit wide

multiplexer on the input of the program counter.

Note:

Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that

interrupt.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prevented. Thus, if an interrupt is currently

being serviced, processing of a new interrupt is pre-

vented, even if the new interrupt is of higher priority

than the one currently being serviced.

The Interrupt Vector Table (IVT) and Alternate Inter-

rupt Vector Table (AIVT) are placed near the beginning

of program memory (0x000004). The IVT and AIVT

are shown in Figure 5-2.

Note:

The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized and controlled using centralized special function

registers:

Certain interrupts have specialized control bits for fea-

tures like edge or level triggered interrupts, interrupt-

on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the pro-

cessing of interrupts of priorities 6 and lower for a cer-

tain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals, and they are

cleared via software.

When an interrupt is serviced, the PC is loaded with the

address stored in the vector location in Program Mem-

ory that corresponds to the interrupt. There are 63 dif-

ferent vectors within the IVT (refer to Figure 5-2). These

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Figure 5-2).

These locations contain 24-bit addresses, and in order

to preserve robustness, an address error trap will take

place should the PC attempt to fetch any of these

words during normal execution. This prevents execu-

tion of random data as a result of accidentally decre-

menting a PC into vector space, accidentally mapping

a data space address into vector space, or the PC roll-

ing over to 0x000000after reaching the end of imple-

mented program memory space. Execution of a GOTO

instruction to this vector space will also generate an

address error trap.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC11<7:0>

The user assignable priority level associated with

each of these 44 interrupts is held centrally in

these twelve registers.

• IPL<3:0> The current CPU priority level is explic-

itly stored in the IPL bits. IPL<3> is present in the

CORCON register, whereas IPL<2:0> are present

in the status register (SR) in the processor core.

• INTCON1<15:0>, INTCON2<15:0>

Global interrupt control functions are derived from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit. User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

 2003 Microchip Technology Inc.

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dsPIC30F

TABLE 5-1:

NATURAL ORDER PRIORITY

5.1

Interrupt Priority

Vector

Numbe

The user assignable Interrupt Priority (IP<2:0>) bits for

each individual interrupt source are located in the LS 3-

bits of each nibble, within the IPCx register(s). Bit 3 of

each nibble is not used and is read as a ‘0’. These bits

define the priority level assigned to a particular interrupt

by the user.

INT

Number

Interrupt Source

r

Highest Natural Order Priority

0

1

8

INT0 - External Interrupt 0

IC1 - Input Capture 1

OC1 - Output Compare 1

T1 - Timer 1

9

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Note:

The user selectable priority levels start at

0, as the lowest priority, and level 7, as the

highest priority.

3

4

IC2 - Input Capture 2

OC2 - Output Compare 2

T2 - Timer 2

5

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means is provided to assign priority within a given level.

This method is called “Natural Order Priority”.

6

7

T3 - Timer 3

8

SPI1

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC devices and their associated

vector numbers.

9

U1RX - UART1 Receiver

U1TX - UART1 Transmitter

ADC - ADC Convert Done

NVM - NVM Write Complete

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45-53

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2

SI2C - I C Slave Interrupt

2

MI2C - I C Master Interrupt

2: The natural order priority number is the

Input Change Interrupt

INT1 - External Interrupt 1

IC7 - Input Capture 7

IC8 - Input Capture 8

OC3 - Output Compare 3

OC4 - Output Compare 4

T4 - Timer 4

same as the INT number.

The ability for the user to assign every interrupt to one

of seven priority levels implies that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low

Voltage Detect) can be given a priority of 7. The INT0

(external interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

T5 - Timer 5

INT2 - External Interrupt 2

U2RX - UART2 Receiver

U2TX - UART2 Transmitter

SPI2

C1 - Combined IRQ for CAN1

IC3 - Input Capture 3

IC4 - Input Capture 4

IC5 - Input Capture 5

IC6 - Input Capture 6

OC5 - Output Compare 5

OC6 - Output Compare 6

OC7 - Output Compare 7

OC8 - Output Compare 8

INT3 - External Interrupt 3

INT4 - External Interrupt 4

C2 - Combined IRQ for CAN2

PWM - PWM Period Match

QEI - QEI Interrupt

Reserved

LVD - Low Voltage Detect

FLTA - PWM Fault A

FLTB - PWM Fault B

53-61 Reserved

Lowest Natural Order Priority

DS70082C-page 50

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dsPIC30F

Note that many of these trap conditions can only be

detected when they occur. Consequently, the question-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

5.2

Reset Sequence

A Reset is not a true exception, because the interrupt

controller is not involved in the Reset process. The pro-

cessor initializes its registers in response to a Reset,

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion, immediately followed by the address target for the

GOTOinstruction. The processor executes the GOTOto

the specified address and then begins operation at the

specified target (start) address.

There are 8 fixed priority levels for traps: Level 8

through Level 15, which implies that the IPL3 is always

set during processing of a trap.

If the user is not currently executing a trap, and he sets

the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all

interrupts are disabled, but traps can still be processed.

5.2.1

RESET SOURCES

5.3.1

TRAP SOURCES

In addition to External Reset and Power-on Reset

(POR), there are 6 sources of error conditions which

‘trap’ to the Reset vector.

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

• Watchdog Time-out:

The watchdog has timed out, indicating that the

processor is no longer executing the correct flow

of code.

Math Error Trap:

The Math Error trap executes under the following three

circumstances:

• Uninitialized W Register Trap:

1. Should an attempt be made to divide by zero,

the divide operation will be aborted on a cycle

boundary and the trap taken.

An attempt to use an uninitialized W register as

an address pointer will cause a Reset.

• Illegal Instruction Trap:

2. If enabled, a Math Error trap will be taken when

an arithmetic operation on either accumulator A

or B causes an overflow from bit 31 and the

accumulator guard bits are not utilized.

Attempted execution of any unused opcodes will

result in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

3. If enabled, a Math Error trap will be taken when

an arithmetic operation on either accumulator A

or B causes a catastrophic overflow from bit 39

and all saturation is disabled.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected, which may result in

malfunction.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap will occur.

• Trap Lockout:

Occurrence of multiple Trap conditions simulta-

neously will cause a Reset.

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

5.3

Traps

1. A misaligned data word access is attempted.

Traps can be considered as non-maskable, non-stable

interrupts, which adhere to a predefined priority as

shown in Figure 5-2. They are intended to provide the

user a means to correct erroneous operation during

debug and when operating within the application.

2. A data fetch from our unimplemented data mem-

ory location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

Note:

If the user does not intend to take correc-

tive action in the event of a trap error con-

dition, these vectors must be loaded with

the address of a default handler that sim-

ply contains the RESET instruction. If, on

the other hand, one of the vectors contain-

ing an invalid address is called, an

address error trap is generated.

Note:

In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

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dsPIC30F

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruction, where literal

is an unimplemented program memory address.

Each hard trap that occurs must be acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict will occur. The conflict occurs

because the lower priority trap cannot be acknowl-

edged until processing for the higher priority trap

completes.

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

• Stack Error Trap:

The device is automatically Reset in a hard trap conflict

condition. The TRAPR status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

This trap is initiated under the following

conditions:

1. The stack pointer is loaded with a value which is

greater than the (user programmable) limit value

written into the SPLIM register (stack overflow).

In the case of a Math Error Trap or Oscillator Failure

Trap, the condition that causes the trap to occur must

be removed before the respective trap flag bit in the

INTCON1 register may be cleared.

2. The stack pointer is loaded with a value which is

less than 0x0800(simple stack underflow).

• Oscillator Fail Trap:

This trap is initiated if the external oscillator fails

and operation becomes reliant on an internal RC

backup.

5.4

Interrupt Sequence

All interrupt event flags are sampled in the beginning of

each instruction cycle by the IFSx registers. A pending

interrupt request (IRQ) is indicated by the flag bit being

equal to a ‘1’ in an IFSx register. The IRQ will cause an

interrupt to occur if the corresponding bit in the interrupt

enable (IECx) register is set. For the remainder of the

instruction cycle, the priorities of all pending interrupt

requests are evaluated.

5.3.2

HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-2 is implemented,

which may require the user to check if other traps are

pending, in order to completely correct the fault.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

‘Soft’ traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps. Soft traps can be treated

like non-maskable sources of interrupt that adhere to

the priority assigned by their position in the IVT. Soft

traps are processed like interrupts and require 2 cycles

to be sampled and acknowledged prior to exception

processing. Therefore, additional instructions may be

executed before a soft trap is acknowledged.

The processor then stacks the current program counter

and the low byte of the processor status register (SRL),

as shown in Figure 5-1. The low byte of the status reg-

ister contains the processor priority level at the time,

prior to the beginning of the interrupt cycle. The proces-

sor then loads the priority level for this interrupt into the

status register. This action will disable all lower priority

interrupts until the completion of the Interrupt Service

Routine.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Like soft traps, hard traps can also be viewed as non-

maskable sources of interrupt. The difference between

hard traps and soft traps is that hard traps force the

CPU to stop code execution after the instruction caus-

ing the trap has completed. Normal program execution

flow will not resume until after the trap has been

acknowledged and processed.

If a higher priority trap occurs while any lower priority

trap is in progress, processing of the lower priority trap

will be suspended and the higher priority trap will be

acknowledged and processed. The lower priority trap

will remain pending until processing of the higher

priority trap completes.

DS70082C-page 52

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dsPIC30F

FIGURE 5-1:

INTERRUPT STACK

5.5

Alternate Vector Table

FRAME

In Program Memory, the Interrupt Vector Table (IVT) is

followed by the Alternate Interrupt Vector Table (AIVT),

as shown in Figure 5-2. Access to the Alternate Vector

Table is provided by the ALTIVT bit in the INTCON2

register. If the ALTIVT bit is set, all interrupt and excep-

tion processes will use the alternate vectors instead of

the default vectors. The alternate vectors are organized

in the same manner as the default vectors. The AIVT

supports emulation and debugging efforts by providing

a means to switch between an application and a sup-

port environment, without requiring the interrupt vec-

tors to be reprogrammed. This feature also enables

switching between applications for evaluation of

different software algorithms at run time.

0x000015

0

PC<15:0>

SRL IPL3 PC<22:16>

W15 (before CALL)

W15 (after CALL)

POP : [--W15]

PUSH : [W15++]

Note 1: The user can always lower the priority level

by writing a new value into SR. The Interrupt

Service Routine must clear the interrupt flag

bits in the IFSx register before lowering the

processor interrupt priority, in order to avoid

recursive interrupts.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6

Fast Context Saving

2: The IPL3 bit (CORCON<3>) is always clear

when interrupts are being processed. It is

set only during execution of traps.

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.Sand POP.S

instructions only.

The RETFIE (Return from Interrupt) instruction will

unstack the program counter and status registers to

return the processor to its state prior to the interrupt

sequence.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

FIGURE 5-2:

EXCEPTION VECTORS

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority ISR should not include the same instruc-

tions. Users must save the key registers in software

during a lower priority interrupt, if the higher priority ISR

uses fast context saving.

Reset - GOTOInstruction

Reset - GOTOAddress

Reserved

0x000000

0x000002

0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Vector

IVT

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

0x000014

5.7

External Interrupt Requests

The interrupt controller supports up to five external

interrupt request signals, INT0-INT4. These inputs are

edge sensitive; they require a low-to-high or a high-to-

low transition to generate an interrupt request. The

INTCON2 register has five bits, INT0EP-INT4EP, that

select the polarity of the edge detection circuitry.

—

Interrupt 52 Vector

Interrupt 53 Vector

Reserved

0x00007E

0x000080

0x000082

Reserved

0x000084

Reserved

Oscillator Fail Trap Vector

Stack Error Trap Vector

Address Error Trap Vector

Math Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

5.8

Wake-up from Sleep and Idle

AIVT

The interrupt controller may be used to wake up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

0x000094

0x0000FE

—

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from Sleep or

Idle and begin execution of the Interrupt Service

Routine (ISR) needed to process the interrupt request.

—

Interrupt 52 Vector

Interrupt 53 Vector

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dsPIC30F

6.2

Run Time Self-Programming

(RTSP)

6.0

FLASH PROGRAM MEMORY

The dsPIC30F family of devices contains internal

program Flash memory for executing user code. There

are two methods by which the user can program this

memory:

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions, and the following

control registers:

TM

1. In-Circuit Serial Programming (ICSP

TM

)

• NVMCON: Non-Volatile Memory Control Register

• NVMKEY: Non-Volatile Memory Key Register

2. Run Time Self-Programming (RTSP)

• NVMADR: Non-Volatile Memory Address

6.1

In-Circuit Serial Programming

(ICSP)

Register

With RTSP, the user may erase program memory, 32

instructions (96 bytes) at a time and can write program

memory data, 4 instructions (12 bytes) at a time.

dsPIC30F devices can be serially programmed while in

the end application circuit. This is simply done with two

lines for Programming Clock and Programming Data

(which are named PGC and PGD respectively), and

three other lines for Power (V^DD), Ground (VSS) and

Master Clear (MCLR). this allows customers to manu-

facture boards with unprogrammed devices, and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

6.3

Table Instruction Operation Summary

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits <15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

Word or Byte mode.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan access program memory in Word or

Byte mode.

A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the effective

address (EA) from a W register specified in the table

instruction, as shown in Figure 6-1.

FIGURE 6-1:

ADDRESSING FOR TABLE AND NVM REGISTERS

24 bits

Using

Program

Counter

Program Counter

0

NVMADR Reg EA

Using

NVMADR

1/0

NVMADRU Reg

Addressing

8 bits

16 bits

Working Reg EA

Using

1/0

TBLPAG Reg

8 bits

Table

Instruction

16 bits

Byte

Select

User/Configuration

Space Select

24-bit EA

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6.5.3

NVMADRU REGISTER

6.4

RTSP Operation

The NVMADRU register is used to hold the upper byte

of the effective address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been executed.

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions, or 96 bytes. Each panel consists of 128 rows, or

4K x 24 instructions. RTSP allows the user to erase one

row (32 instructions) at a time and to program four

instructions at one time. RTSP may be used to program

multiple program memory panels, but the table pointer

must be changed at each panel boundary.

6.5.4

NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55and

0xAAto the NVMKEY register. Refer to Section 6.6 for

further details.

Each panel of program memory contains write latches

that hold four instructions of programming data. Prior to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction 0, instruction 1,

etc. The instruction words loaded must always be from

a group of four boundary (e.g., loading of instructions 3,

4, 5 and 6 is not allowed).

6.6

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 2 msec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

The basic sequence for RTSP programming is to set up

a table pointer, then do a series of TBLWTinstructions

to load the write latches. Programming is performed by

setting the special bits in the NVMCON register. Four

TBLWTL and four TBLWTH instructions are required to

load the four instructions. To fully program a row of

program memory, eight cycles of four TBLWTL and four

TBLWTH are required. If multiple panel programming

is required, the table pointer needs to be changed and

the next set of multiple write latches written.

6.6.1

PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

The user can erase one row of program Flash memory

at a time. The user can program one block (4 instruc-

tion words) of Flash memory at a time. The general pro-

cess is:

All of the table write operations are single word writes

(2 instruction cycles), because only the table latches

are written. A total of 8 programming passes, each writ-

ing 4 instruction words, are required per row. A 128 row

panel requires 1024 programming cycles.

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

2. Update the data image with the desired new

data.

The Flash Program Memory is readable, writable and

erasable during normal operation over the entire V^DD

range.

3. Erase program Flash row.

a) Setup NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

6.5

Control Registers

The three SFRs used to read and write the program

Flash memory are:

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

• NVMCON

• NVMADR

• NVMADRU

• NVMKEY

e) Set the WR bit. This will begin erase cycle.

f) CPU will stall for the duration of the erase

cycle.

g) The WR bit is cleared when erase cycle

ends.

6.5.1

NVMCON REGISTER

4. Write four instruction words of data from data

RAM into the program Flash write latches.

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and

start of the programming cycle.

6.5.2

NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the effective address. The NVMADR register

captures the EA<15:0> of the last table instruction that

has been executed and selects the row to write.

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5. Program 4 instruction words into program Flash.

6. Repeat steps (4-5) seven more times to finish

programming Flash row.

a) Setup NVMCON register for multi-word,

program Flash, program, and set WREN

bit.

7. Repeat steps 1 through 6 as needed to program

desired amount of program Flash memory.

b) Write ‘55’ to NVMKEY.

c) Write ‘AA’ to NVMKEY.

6.6.2

ERASING A ROW OF PROGRAM

MEMORY

d) Set the WR bit. This will begin program

cycle.

Example 6-1 shows a code sequence that can be used

to erase a row (32 instructions) of program memory.

e) CPU will stall for duration of the program

cycle.

f) The WR bit is cleared by the hardware

when program cycle ends.

EXAMPLE 6-1:

ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV

#0x4041,W0

W0_,NVMCON

;

; Init NVMCON SFR

; Init pointer to row to be ERASED

MOV

DISI

#tblpage(PROG_ADDR),W0

W0_,NVMADRU

#tbloffset(PROG_ADDR),W0

W0, NVMADR

;

; Initialize PM Page Boundary SFR

; Intialize in-page EA[15:0] pointer

; Intialize NVMADR SFR

; Block all interrupts with priority <7

; for next 5 instructions

#5

MOV

BSET

NOP

#0x55,W0

W0_,NVMKEY

#0xAA,W1

W1_,NVMKEY

NVMCON,#WR

; Write the 0x55 key

;

; Write the 0xAA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

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6.6.3

LOADING WRITE LATCHES

Example 6-2 shows a sequence of instructions that

can be used to load the 96 bits of write latches. Four

TBLWTL and four TBLWTH instructions are needed to

load the write latches selected by the table pointer.

EXAMPLE 6-2:

LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000,W0

W0_,TBLPAG

#0x6000,W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0,W2

#HIGH_BYTE_0,W3

;

TBLWTL W2_,[W0]

TBLWTH W3_,[W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1,W2

#HIGH_BYTE_1,W3

;

TBLWTL W2_,[W0]

TBLWTH W3_,[W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

;

2nd_program_word

MOV

#LOW_WORD_2,W2

#HIGH_BYTE_2,W3

;

TBLWTL W2_,[W0]

TBLWTH W3_,[W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 3rd_program_word

MOV

#LOW_WORD_3,W2

#HIGH_BYTE_3,W3

;

TBLWTL W2_,[W0]

TBLWTH W3_,[W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

Note: In Example 6-2, the contents of the upper byte of W3 has no effect.

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6.6.4

INITIATING THE PROGRAMMING

SEQUENCE

For protection, the write initiate sequence for NVMKEY

must be used to allow any erase or program operation

to proceed. After the programming command has been

executed, the user must wait for the programming time

until programming is complete. The two instructions

following the start of the programming sequence

should be NOPs.

EXAMPLE 6-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55,W0

W0_,NVMKEY

#0xAA,W1

W1_,NVMKEY

NVMCON,#WR

; Write the 0x55 key

;

; Write the 0xAA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

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Control bit WR initiates write operations, similar to pro-

gram Flash writes. This bit cannot be cleared, only set,

in software. This bit is cleared in hardware at the com-

pletion of the write operation. The inability to clear the

WR bit in software prevents the accidental or

premature termination of a write operation.

7.0

DATA EEPROM MEMORY

The Data EEPROM Memory is readable and writable

during normal operation over the entire V^DDrange. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

Flash memory are used to access data EEPROM

memory, as well. As described in Section 4.0, these

registers are:

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation. In these situations, following Reset, the user can

check the WRERR bit and rewrite the location. The

address register NVMADR remains unchanged.

• NVMCON

• NVMADR

• NVMADRU

• NVMKEY

Note:

Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be

cleared in software.

The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to

data memory, NVMADR, in conjunction with the

NVMADRU register, is used to address the EEPROM

location being accessed. TBLRDLand TBLWTLinstruc-

tions are used to read and write data EEPROM. The

dsPIC30F devices have up to 8 Kbytes (4K words) of

data EEPROM, with an address range from 0x7FF000

to 0x7FFFFE.

7.1

Reading the Data EEPROM

A TBLRD instruction reads a word at the current pro-

gram word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

register W4, as shown in Example 7-1.

A word write operation should be preceded by an erase

of the corresponding memory location(s). The write typ-

ically requires 2 ms to complete, but the write time will

vary with voltage and temperature.

EXAMPLE 7-1:

DATA EEPROM READ

MOV

#LOW_ADDR_WORD,W0 ; Init Pointer

#HIGH_ADDR_WORD,W1

W1 TBLPAG

,

TBLRDL [ W0], W4

; read data EEPROM

A program or erase operation on the data EEPROM

does not stop the instruction flow. The user is respon-

sible for waiting for the appropriate duration of time

before initiating another data EEPROM write/erase

operation. Attempting to read the data EEPROM while

a programming or erase operation is in progress results

in unspecified data.

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7.2

Erasing Data EEPROM

7.2.1

ERASING A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPROM, the

NVMADRU and NVMADR registers must initially

point to the block of memory to be erased. Configure

NVMCON for erasing a block of data EEPROM, and

set the ERASE and WREN bits in NVMCON register.

Setting the WR bit initiates the erase, as shown in

Example 7-2.

EXAMPLE 7-2:

DATA EEPROM BLOCK ERASE

; Select data EEPROM block, ERASE, WREN bits

MOV #4045,W0

MOV W0 NVMCON

; Initialize NVMCON SFR

,

; Start erase cycle by setting WR after writing key sequence

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55,W0

W0_,NVMKEY

#0xAA,W1

W1_,NVMKEY

NVMCON,#WR

;

; Write the 0x55 key

;

; Write the 0xAA key

; Initiate erase sequence

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

7.2.2

ERASING A WORD OF DATA

EEPROM

The TBLPAG and NVMADR registers must point to

the block. Select erase a block of data Flash, and set

the ERASE and WREN bits in NVMCON register. Set-

ting the WR bit initiates the erase, as shown in

Example 7-3.

EXAMPLE 7-3:

DATA EEPROM WORD ERASE

; Select data EEPROM word, ERASE, WREN bits

MOV #4044,W0

MOV W0 NVMCON

,

; Start erase cycle by setting WR after writing key sequence

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55,W0

W0_,NVMKEY

#0xAA,W1

W1_,NVMKEY

NVMCON,#WR

;

; Write the 0x55 key

;

; Write the 0xAA key

; Initiate erase sequence

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

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The write will not initiate if the above sequence is not

exactly followed (write 0x55to NVMKEY, write 0xAAto

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

7.3

Writing to the Data EEPROM

To write an EEPROM data location, the following

sequence must be followed:

1. Erase data EEPROM word.

a) Select word, data EEPROM, erase and set

WREN bit in NVMCON register.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM, due to unexpected code exe-

cution. The WREN bit should be kept clear at all times,

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

b) Write address of word to be erased into

NVMADRU/NVMADR.

c) Enable NVM interrupt (optional).

d) Write ‘55’ to NVMKEY.

After a write sequence has been initiated, clearing the

WREN bit will not affect the current write cycle. The WR

bit will be inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

e) Write ‘AA’ to NVMKEY.

f) Set the WR bit. This will begin erase cycle.

g) Either poll NVMIF bit or wait for NVMIF

interrupt.

h) The WR bit is cleared when the erase cycle

ends.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Non-Volatile Memory

Write Complete Interrupt Flag bit (NVMIF) is set. The

user may either enable this interrupt, or poll this bit.

NVMIF must be cleared by software.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a) Select word, data EEPROM, program, and

set WREN bit in NVMCON register.

7.3.1

WRITING A WORD OF DATA

EEPROM

b) Enable NVM write done interrupt (optional).

c) Write ‘55’ to NVMKEY.

Once the user has erased the word to be programmed,

then a table write instruction is used to write one write

latch, as shown in Example 7-4.

d) Write ‘AA’ to NVMKEY.

e) Set The WR bit. This will begin program

cycle.

f) Either poll NVMIF bit or wait for NVM

interrupt.

g) The WR bit is cleared when the write cycle

ends.

EXAMPLE 7-4:

DATA EEPROM WORD WRITE

; Point to data memory

MOV

#LOW_ADDR_WORD,W0

; Init pointer

MOV

#HIGH_ADDR_WORD,W1

MOV

W1 TBLPAG

,

MOV

#LOW(WORD),W2

; Get data

TBLWTL

W2 [ W0]

,

; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV #0x4004,W0

MOV W0 NVMCON

,

; Operate key to allow write operation

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

,

; Write the 0x55 key

#0xAA,W1

W1 NVMKEY

,

; Write the 0xAA key

NVMCON,#WR

; Initiate program sequence

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

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7.3.2

WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

program the block.

EXAMPLE 7-5:

DATA EEPROM BLOCK WRITE

MOV

#LOW_ADDR_WORD,W0 ; Init pointer

#HIGH_ADDR_WORD,W1

MOV

W1 TBLPAG

,

MOV

#data1,W2

; Get 1st data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data2,W2

; Get 2nd data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data3,W2

; Get 3rd data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data4,W2

; Get 4th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data5,W2

; Get 5th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data6,W2

; Get 6th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data7,W2

; Get 7th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data8,W2

; Get 8th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data9,W2

; Get 9th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data10,W2

; Get 10th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data11,W2

; Get 11th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data12,W2

; Get 12th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data13,W2

; Get 13th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data14,W2

; Get 14th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data15,W2

; Get 15th data

TBLWTL

MOV

W2 [ W0]++

,

; write data

#data16,W2

; Get 16th data

TBLWTL

MOV

W2 [ W0]++

,

; write data. The NVMADR captures last table access address.

; Select data EEPROM for multi word op

; Operate Key to allow program operation

; Block all interrupts with priority <7

; for next 5 instructions

#0x400A,W0

MOV

W0 NVMCON

,

DISI

#5

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

,

; Write the 0x55 key

#0xAA,W1

W1 NVMKEY

,

; Write the 0xAA key

; Start write cycle

NVMCON,#WR

7.4

Write Verify

7.5

Protection Against Spurious Write

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together,

help prevent an accidental write during brown-out,

power glitch or software malfunction.

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Writes to the latch, write the latch (LATx). Reads from

the port (PORTx), read the port pins, and writes to the

port pins, write the latch (LATx).

8.0

I/O PORTS

All of the device pins (except VDD, VSS, MCLR, and

OSC1/CLKIN) are shared between the peripherals and

the parallel I/O ports.

Any bit and its associated data and control registers

that are not valid for a particular device will be dis-

abled. That means the corresponding LATx and TRISx

registers and the port pin will read as zeros.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

8.1

Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

The format of the registers for PORTA are shown in

Table 8-1.

The TRISA (Data Direction Control) register controls

the direction of the RA<7:0> pins, as well as the INTx

pins and the V^REFpins. The LATA register supplies

data to the outputs, and is readable/writable. Reading

the PORTA register yields the state of the input pins,

while writing the PORTA register modifies the contents

of the LATA register.

All port pins have three registers directly associated

with the operation of the port pin. The data direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

FIGURE 8-1:

BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Dedicated Port Module

Read TRIS

I/O Cell

TRIS Latch

D

Q

Data Bus

WR TRIS

CK

Data Latch

I/O Pad

D

Q

WR LAT +

WR Port

CK

Read LAT

Read Port

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dsPIC30F

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 8-2 shows how ports are shared

with other peripherals, and the associated I/O cell (pad)

to which they are connected. Table 8-2 through

Table 8-7 show the formats of the registers for the

shared ports, PORTB through PORTG.

Note:

The actual bits in use vary between

devices.

FIGURE 8-2:

BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Output Multiplexers

Peripheral Module

Peripheral Input Data

Peripheral Module Enable

I/O Cell

Peripheral Output Enable

Peripheral Output Data

1

0

Output Enable

1

0

PIO Module

Output Data

Read TRIS

I/O Pad

Data Bus

WR TRIS

D

Q

CK

TRIS Latch

D

Q

WR LAT +

WR Port

CK

Data Latch

Read LAT

Input Data

Read Port

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins), may cause the

input buffer to consume current that exceeds the

device specifications.

8.2

Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (V^OHor VOL) will be

converted.

When reading the PORT register, all pins configured as

analog input channel will read as cleared (a low level).

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DS70082C-page 68

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Advance Information

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dsPIC30F

8.3

Input Change Notification Module

The Input Change Notification module provides the

dsPIC30F devices the ability to generate interrupt

requests to the processor in response to a change-of-

state on selected input pins. This module is capable of

detecting input change-of-states even in Sleep mode,

when the clocks are disabled. There are up to 22 exter-

nal signals (CN0 through CN21) that may be selected

(enabled) for generating an interrupt request on a

change-of-state.

TABLE 8-8:

INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)

SFR

Addr.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset State

Name

CNEN1

CNEN2

CNPU1

00C0

00C2

00C4

00C6

CN15IE

—

CN14IE

—

CN13IE

—

CN12IE

—

CN11IE

—

CN10IE

—

CN9IE

—

CN8IE

—

0000 0000 0000 0000

CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE

CNPU2

Legend:

—

u= uninitialized bit

TABLE 8-9:

INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)

SFR

Addr.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

Name

CNEN1

CNEN2

CNPU1

00C0

00C2

00C4

00C6

CN7IE

—

CN6IE

—

CN5IE

CN4IE

CN3IE

CN2IE

CN1IE

CN0IE

CN16IE

CN0PUE

0000 0000 0000 0000

CN21IE

CN20IE

CN19IE

CN18IE

CN17IE

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE

CNPU2

Legend:

CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE

—

u= uninitialized bit

DS70082C-page 70

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dsPIC30F

16-bit Timer Mode: In the 16-bit Timer mode, the timer

increments on every instruction cycle up to a match

value, preloaded into the period register PR1, then

resets to 0 and continues to count.

9.0

TIMER1 MODULE

This section describes the 16-bit General Purpose

(GP) Timer1 module and associated operational

modes. Figure 9-1 depicts the simplified block diagram

of the 16-bit Timer1 Module.

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless the TSIDL (T1CON<13>)

bit = 0. If TSIDL = 1, the timer module logic will resume

the incrementing sequence upon termination of the

CPU Idle mode.

The following sections provide a detailed description,

including setup and control registers along with associ-

ated block diagrams for the operational modes of the

timers.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in PR1,

then resets to 0 and continues.

The Timer1 module is a 16-bit timer which can serve as

the time counter for the real-time clock, or operate as a

free running interval timer/counter. The 16-bit timer has

the following modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless the respective TSIDL bit = 0.

If TSIDL = 1, the timer module logic will resume the

incrementing sequence upon termination of the CPU

Idle mode.

Further, the following operational characteristics are

supported:

• Timer gate operation

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal.

The timer counts up to a match value preloaded in PR1,

then resets to 0and continues.

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit period register match or falling

edge of external gate signal

When the timer is configured for the Asynchronous mode

of operation and the CPU goes into the Idle mode, the

timer will stop incrementing if TSIDL = 1.

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1

presents a block diagram of the 16-bit timer module.

FIGURE 9-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

PR1

Comparator x 16

TMR1

Equal

TSYNC

1

0

Sync

(3)

Reset

0

1

T1IF

Event Flag

Q

D

TGATE

CK

TGATE

TCKPS<1:0>

2

TON

SOSCO/

T1CK

1 X

0 1

0 0

Gate

Sync

Prescaler

LPOSCEN

1, 8, 64, 256

SOSCI

T^CY

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dsPIC30F

When the Gated Time Accumulation mode is enabled,

an interrupt will also be generated on the falling edge of

the gate signal (at the end of the accumulation cycle).

9.1

Timer Gate Operation

The 16-bit timer can be placed in the Gated Time Accu-

mulation mode. This mode allows the internal T^CYto

increment the respective timer when the gate input sig-

nal (T1CK pin) is asserted high. Control bit TGATE

(T1CON<6>) must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source set to internal (TCS = 0).

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

9.5

Real-Time Clock

When the CPU goes into the Idle mode, the timer will

stop incrementing, unless TSIDL = 0. If TSIDL = 1, the

timer will resume the incrementing sequence upon

termination of the CPU Idle mode.

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time-of-day and event time stamping

capabilities. Key operational features of the RTC are:

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

9.2

Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

Timer, has a prescale option of 1:1, 1:8, 1:64, and

1:256 selected by control bits TCKPS<1:0>

(T1CON<5:4>). The prescaler counter is cleared when

any of the following occurs:

• Low power

• Real-Time Clock Interrupts

• These Operating modes are determined by

setting the appropriate bit(s) in the T1CON

Control register

• a write to the TMR1 register

9.5.1

RTC OSCILLATOR OPERATION

• clearing of the TON bit (T1CON<15>)

• device Reset such as POR and BOR

When the TON = 1, TCS = 1and TGATE = 0, the timer

increments on the rising edge of the 32 kHz LP oscilla-

tor output signal, up to the value specified in the period

register, and is then reset to ‘0’.

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

TMR1 is not cleared when T1CON is written. It is

cleared by writing to the TMR1 register.

Enabling LPOSCEN (OSCCON<1>) will disable the

normal Timer and Counter modes and enable a timer

carry-out wake-up event.

9.3

Timer Operation During Sleep

Mode

When the CPU enters Sleep mode, the RTC will con-

tinue to operate, provided the 32 kHz external crystal

oscillator is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for RTC to continue operation in Idle mode.

During CPU Sleep mode, the timer will operate if:

• The timer module is enabled (TON = 1) and

• The timer clock source is selected as external

(TCS = 1) and

• The TSYNC bit (T1CON<2>) is asserted to a logic

0, which defines the external clock source as

asynchronous

9.5.2

RTC INTERRUPTS

When an interrupt event occurs, the respective inter-

rupt flag, T1IF, is asserted and an interrupt will be gen-

erated, if enabled. The T1IF bit must be cleared in

software. The respective Timer interrupt flag, T1IF, is

located in the IFS0 status register in the Interrupt

Controller.

When all three conditions are true, the timer will con-

tinue to count up to the period register and be reset to

0x0000.

When a match between the timer and the period regis-

ter occurs, an interrupt can be generated, if the

respective timer interrupt enable bit is asserted.

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The Timer interrupt

enable bit is located in the IEC0 control register in the

Interrupt Controller.

9.4

Timer Interrupt

The 16-bit timer has the ability to generate an interrupt

on period match. When the timer count matches the

period register, the T1IF bit is asserted and an interrupt

will be generated, if enabled. The T1IF bit must be

cleared in software. The timer interrupt flag T1IF is

located in the IFS0 control register in the Interrupt

Controller.

DS70082C-page 72

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NOTES:

DS70082C-page 74

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The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescaler output. This is useful for high frequency

external clock inputs.

10.0 TIMER2/3 MODULE

This section describes the 32-bit General Purpose

(GP) Timer module (Timer2/3) and associated opera-

tional modes. Figure 10-1 depicts the simplified block

diagram of the 32-bit Timer2/3 module. Figure 10-2

and Figure 10-3 show Timer2/3 configured as two

independent 16-bit timers; Timer2 and Timer3,

respectively.

32-bit Timer Mode: In the 32-bit Timer mode, the timer

increments on every instruction cycle up to a match

value, preloaded into the combined 32-bit period regis-

ter PR3/PR2, then resets to 0 and continues to count.

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the LS word (TMR2 register) will cause

the MS word to be read and latched into a 16-bit

holding register, termed TMR3HLD.

The Timer2/3 module is a 32-bit timer, which can be

configured as two 16-bit timers, with selectable operat-

ing modes. These timers are utilized by other

peripheral modules such as:

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 register, the contents of TMR3HLD

will be transferred and latched into the MSB of the

32-bit timer (TMR3).

• Input Capture

• Output Compare/Simple PWM

The following sections provide a detailed description,

including setup and control registers, along with asso-

ciated block diagrams for the operational modes of the

timers.

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal,

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combined 32-bit period register PR3/PR2, then resets

to ‘0’ and continues.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit Timer operation

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer will stop incrementing, unless the

TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer

module logic will resume the incrementing sequence

upon termination of the CPU Idle mode.

• Single 32-bit Synchronous Counter

Further, the following operational characteristics are

supported:

• ADC Event Trigger

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the LS

Word and Timer3 is the MS Word of the 32-bit timer.

Note:

For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer 2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and the interrupt is enabled with the

Timer3 interrupt enable bit (T3IE).

16-bit Mode: In the 16-bit mode, Timer2 and Timer3

can be configured as two independent 16-bit timers.

Each timer can be set up in either 16-bit Timer mode or

16-bit Synchronous Counter mode. See Section 9.0,

Timer1 Module, for details on these two operating

modes.

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dsPIC30F

FIGURE 10-1:

32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>

TMR3HLD

16

Write TMR2

Read TMR2

16

Reset

TMR3

TMR2

LSB

Sync

MSB

ADC Event Trigger

Comparator x 32

Equal

PR3

PR2

0

1

T3IF

Event Flag

Q

D

TGATE(T2CON<6>)

CK

TGATE

(T2CON<6>)

TCKPS<1:0>

2

TON

T2CK

1 X

Prescaler

Gate

Sync

1, 8, 64, 256

0 1

0 0

TCY

Note:

Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control

bits are respective to the T2CON register.

DS70082C-page 76

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dsPIC30F

FIGURE 10-2:

16-BIT TIMER2 BLOCK DIAGRAM

PR2

Equal

Comparator x 16

TMR2

Reset

Sync

0

T2IF

Event Flag

Q

D

TGATE

1

CK

TGATE

TCKPS<1:0>

2

TON

T2CK

1 X

0 1

0 0

Prescaler

Gate

Sync

1, 8, 64, 256

T^CY

FIGURE 10-3:

16-BIT TIMER3 BLOCK DIAGRAM

PR3

ADC Event Trigger

Equal

Comparator x 16

TMR3

Reset

0

1

T3IF

Event Flag

Q

D

TGATE

CK

TGATE

TCKPS<1:0>

2

TON

T3CK

Sync

1 X

Prescaler

1, 8, 64, 256

0 1

T^CY

0 0

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dsPIC30F

10.1 Timer Gate Operation

10.5 Timer Interrupt

The 32-bit timer can be placed in the Gated Time Accu-

mulation mode. This mode allows the internal T^CYto

increment the respective timer when the gate input sig-

nal (T2CK pin) is asserted high. Control bit TGATE

(T2CON<6>) must be set to enable this mode. When in

this mode, Timer2 is the originating clock source. The

TGATE setting is ignored for Timer3. The timer must be

enabled (TON = 1) and the timer clock source set to

internal (TCS = 0).

The 32-bit timer module can generate an interrupt on

period match, or on the falling edge of the external gate

signal. When the 32-bit timer count matches the

respective 32-bit period register, or the falling edge of

the external “gate” signal is detected, the T3IF bit

(IFS0<7>) is asserted and an interrupt will be gener-

ated if enabled. In this mode, the T3IF interrupt flag is

used as the source of the interrupt. The T3IF bit must

be cleared in software.

The falling edge of the external signal terminates the

count operation, but does not reset the timer. The user

must reset the timer in order to start counting from zero.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

10.2 ADC Event Trigger

When a match occurs between the 32-bit timer (TMR3/

TMR2) and the 32-bit combined period register (PR3/

PR2), a special ADC trigger event signal is generated

by Timer3.

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256

selected by control bits TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

originating clock source is Timer2. The prescaler oper-

ation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the following

occurs:

• a write to the TMR2/TMR3 register

• clearing either of the TON (T2CON<15> or

T3CON<15>) bits to ‘0’

• device Reset such as POR and BOR

However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset, since the prescaler

clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

10.4 Timer Operation During Sleep

Mode

During CPU Sleep mode, the timer will not operate,

because the internal clocks are disabled.

DS70082C-page 78

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NOTES:

DS70082C-page 80

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dsPIC30F

The operating modes of the Timer4/5 module are deter-

mined by setting the appropriate bit(s) in the 16-bit

T4CON and T5CON SFRs.

11.0 TIMER4/5 MODULE

This section describes the second 32-bit General Pur-

pose (GP) Timer module (Timer4/5) and associated

operational modes. Figure 11-1 depicts the simplified

block diagram of the 32-bit Timer4/5 Module.

Figure 11-2 and Figure 11-3 show Timer4/5 configured

as two independent 16-bit timers, Timer4 and Timer5,

respectively.

For 32-bit timer/counter operation, Timer4 is the LS

Word and Timer5 is the MS Word of the 32-bit timer.

Note:

For 32-bit timer operation, T5CON control

bits are ignored. Only T4CON control bits

are used for setup and control. Timer4

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer5 interrupt flag

(T5IF) and the interrupt is enabled with the

Timer5 interrupt enable bit (T5IE).

The Timer4/5 module is similar in operation to the

Timer 2/3 module. However, there are some differ-

ences, which are listed below:

• The Timer4/5 module does not support the ADC

Event Trigger feature

• Timer4/5 can not be utilized by other peripheral

modules such as Input Capture and Output

Compare

FIGURE 11-1:

32-BIT TIMER4/5 BLOCK DIAGRAM

Data Bus<15:0>

TMR5HLD

16

Write TMR4

Read TMR4

16

Reset

TMR5

MSB

TMR4

Sync

LSB

Comparator x 32

Equal

PR5

PR4

0

1

T5IF

Event Flag

Q

D

TGATE(T4CON<6>)

CK

TGATE

(T4CON<6>)

TCKPS<1:0>

TON

2

T4CK

1 X

Prescaler

Gate

Sync

1, 8, 64, 256

0 1

TCY

0 0

Note:

Timer configuration bit T32, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control

bits are respective to the T4CON register.

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FIGURE 11-2:

16-BIT TIMER4 BLOCK DIAGRAM

PR4

Comparator x 16

TMR4

Equal

Sync

Reset

0

1

T4IF

Event Flag

Q

D

TGATE

Q

CK

TGATE

TCKPS<1:0>

2

TON

T4CK

1 X

Prescaler

Gate

Sync

1, 8, 64, 256

0 1

TCY

0 0

FIGURE 11-3:

16-BIT TIMER5 BLOCK DIAGRAM

PR5

Equal

ADC Event Trigger

Comparator x 16

TMR5

Reset

0

1

T5IF

Event Flag

Q

D

TGATE

Q

CK

TGATE

TCKPS<1:0>

TON

2

Sync

1 X

T5CK

Prescaler

1, 8, 64, 256

0 1

TCY

0 0

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NOTES:

DS70082C-page 84

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dsPIC30F

The key operational features of the Input Capture

module are:

12.0 INPUT CAPTURE MODULE

This section describes the Input Capture module and

associated operational modes. The features provided

by this module are useful in applications requiring Fre-

quency (Period) and Pulse measurement. Figure 12-1

depicts a block diagram of the Input Capture module.

Input capture is useful for such modes as:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the ICxCON register (where x =

1,2,...,N). The dsPIC devices contain up to 8 capture

channels, (i.e., the maximum value of N is 8).

• Frequency/Period/Pulse Measurements

• Additional sources of External Interrupts

FIGURE 12-1:

INPUT CAPTURE MODE BLOCK DIAGRAM

T3_CNT

T2_CNT

From GP Timer Module

16

ICx

ICTMR

1

0

Edge

Detection

Logic

FIFO

R/W

Prescaler

1, 4, 16

Clock

Synchronizer

Logic

3

ICM<2:0>

Mode Select

ICxBUF

ICBNE, ICOV

ICI<1:0>

Interrupt

Logic

ICxCON

Data Bus

Set Flag

ICxIF

Note:

Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input

capture channels 1 through N.

12.1.2

CAPTURE BUFFER OPERATION

12.1 Simple Capture Event Mode

Each capture channel has an associated FIFO buffer,

which is four 16-bit words deep. There are two status

flags, which provide status on the FIFO buffer:

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• ICBFNE - Input Capture Buffer Not Empty

• ICOV - Input Capture Overflow

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

The ICBFNE will be set on the first input capture event

and remain set until all capture events have been read

from the FIFO. As each word is read from the FIFO, the

remaining words are advanced by one position within

the buffer.

These simple Input Capture modes are configured by

setting the appropriate bits ICM<2:0> (ICxCON<2:0>).

12.1.1

CAPTURE PRESCALER

There are four input capture prescaler settings, speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture channel is turned off, the prescaler counter will

be cleared. In addition, any Reset will clear the

prescaler counter.

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In the event that the FIFO is full with four capture

events and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition will occur and the

ICOV bit will be set to a logic ‘1’. The fifth capture event

is lost and is not stored in the FIFO. No additional

events will be captured till all four events have been

read from the buffer.

12.2.1

INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion with reduced functionality. In the CPU Sleep

mode, the ICI<1:0> bits are not applicable, and the

input capture module can only function as an external

interrupt source.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

The capture module must be configured for interrupt

only on the rising edge (ICM<2:0> = 111), in order for

the input capture module to be used while the device

is in Sleep mode. The prescale settings of 4:1 or 16:1

are not applicable in this mode.

12.1.3

TIMER2 AND TIMER3 SELECTION

MODE

The input capture module consists of up to 8 input cap-

ture channels. Each channel can select between one of

two timers for the time base, Timer2 or Timer3.

12.2.2

INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the interrupt

mode selected by the ICI<1:0> bits are applicable, as

well as the 4:1 and 16:1 capture prescale settings,

which are defined by control bits ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover, the

ICSIDL bit must be asserted to a logic ‘0’.

Selection of the timer resource is accomplished

through SFR bit ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

12.1.4

HALL SENSOR MODE

When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the fol-

lowing operations are performed by the input capture

logic:

If the input capture module is defined as ICM<2:0> =

111in CPU Idle mode, the input capture pin will serve

only as an external interrupt pin.

• The input capture interrupt flag is set on every

edge, rising and falling.

12.3 Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt, based upon the selected number of cap-

ture events. The selection number is set by control bits

ICI<1:0> (ICxCON<6:5>).

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored, since every capture

generates an interrupt.

• A capture overflow condition is not generated in

this mode.

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx Status register.

12.2 Input Capture Operation During

Sleep and Idle Modes

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture interrupt enable bit is located in the

corresponding IEC Control register.

An input capture event will generate a device wake-up

or interrupt, if enabled, if the device is in CPU Idle or

Sleep mode.

Independent of the timer being enabled, the input

capture module will wake-up from the CPU Sleep or

Idle mode when a capture event occurs, if ICM<2:0> =

111and the interrupt enable bit is asserted. The same

wake-up can generate an interrupt, if the conditions for

processing the interrupt have been satisfied. The

wake-up feature is useful as a method of adding extra

external pin interrupts.

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The key operational features of the Output Compare

module include:

13.0 OUTPUT COMPARE MODULE

This section describes the Output Compare module

and associated operational modes. The features pro-

vided by this module are useful in applications requiring

operational modes such as:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Generation of Variable Width Output Pulses

• Power Factor Correction

• Output Compare during Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

Figure 13-1 depicts a block diagram of the Output

Compare module.

These operating modes are determined by setting the

appropriate bits in the 16-bit OCxCON SFR (where x =

1,2,3,...,N). The dsPIC devices contain up to 8

compare channels, (i.e., the maximum value of N is 8).

OCxRS and OCxR in the figure represent the Dual

Compare registers. In the dual compare mode, the

OCxR register is used for the first compare and OCxRS

is used for the second compare.

FIGURE 13-1:

OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

Output

S

Q

OCxR

OCx

Logic

R

Output Enable

3

OCM<2:0>

Mode Select

OCFA

Comparator

(for x = 1, 2, 3 or 4)

OCTSEL

1

or OCFB

0

(for x = 5, 6, 7 or 8)

From GP Timer Module

T3P3_MATCH

TMR3<15:0> T2P2_MATCH

TMR2<15:0

Note:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 through N.

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13.3.2

CONTINUOUS PULSE MODE

13.1 Timer2 and Timer3 Selection Mode

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required:

Each output compare channel can select between one

of two 16-bit timers; Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3>). Timer2 is the default timer resource

for the Output Compare module.

• Determine instruction cycle time T^CY.

• Calculate desired pulse value based on T^CY.

• Calculate timer to start pulse width from timer start

value of 0x0000.

13.2 Simple Output Compare Match

Mode

• Write pulse width start and stop times into OCxR

and OCxRS (x denotes channel 1, 2, ...,N)

compare registers, respectively.

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 101.

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

• Enable timer, TON (TxCON<15>) = 1.

13.4 Simple PWM Mode

The OCxR register is used in these modes. The OCxR

register is loaded with a value and is compared to the

selected incrementing timer count. When a compare

occurs, one of these Compare Match modes occurs. If

the counter resets to zero before reaching the value in

OCxR, the state of the OCx pin remains unchanged.

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selected output compare channel is config-

ured for the PWM mode of operation. When configured

for the PWM mode of operation, OCxR is the Main latch

(read only) and OCxRS is the Secondary latch. This

enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

13.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selected output compare channel is config-

ured for one of two Dual Output Compare modes,

which are:

1. Set the PWM period by writing to the appropriate

period register.

2. Set the PWM duty cycle by writing to the OCxRS

register.

• Single Output Pulse mode

• Continuous Output Pulse mode

3. Configure the output compare module for PWM

operation.

13.3.1

SINGLE PULSE MODE

4. Set the TMRx prescale value and enable the

For the user to configure the module for the generation

of a single output pulse, the following steps are

required (assuming timer is off):

Timer, TON (TxCON<15>) = 1.

13.4.1

INPUT PIN FAULT PROTECTION

FOR PWM

• Determine instruction cycle time T^CY.

• Calculate desired pulse width value based on T^CY.

When control bits OCM<2:0> (OCxCON<2:0>) = 111,

the selected output compare channel is again config-

ured for the PWM mode of operation, with the addi-

tional feature of input fault protection. While in this

mode, if a logic 0 is detected on the OCFA/B pin, the

respective PWM output pin is placed in the high imped-

ance input state. The OCFLT bit (OCxCON<4>) indi-

cates whether a FAULT condition has occurred. This

state will be maintained until both of the following

events have occurred:

• Calculate time to start pulse from timer start value

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS compare registers (x denotes

channel 1, 2, ...,N).

• Set timer period register to value equal to, or

greater than, value in OCxRS compare register.

• Set OCM<2:0> = 100.

• Enable timer, TON (TxCON<15>) = 1.

• The external FAULT condition has been removed.

To initiate another single pulse, issue another write to

• The PWM mode has been re-enabled by writing

to the appropriate control bits.

set OCM<2:0> = 100.

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When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on

the next increment cycle:

13.4.2

PWM PERIOD

The PWM period is specified by writing to the PRx reg-

ister. The PWM period can be calculated using

Equation 13-1.

• TMRx is cleared.

• The OCx pin is set.

EQUATION 13-1: PWM PERIOD

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin will remain low.

PWM period = [(PRx) + 1] • 4 • T^OSC•

(TMRx prescale value)

- Exception 2: If duty cycle is greater than PRx,

the pin will remain high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

PWM frequency is defined as 1 / [PWM period].

• The corresponding timer interrupt flag is set.

See Figure 13-1 for key PWM period comparisons.

Timer3 is referred to in the figure for clarity.

FIGURE 13-1:

PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle (OCxR)

13.5 Output Compare Operation During

CPU Sleep Mode

13.7 Output Compare Interrupts

The output compare channels have the ability to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

When the CPU enters the Sleep mode, all internal

clocks are stopped. Therefore, when the CPU enters

the Sleep state, the output compare channel will drive

the pin to the active state that was observed prior to

entering the CPU Sleep state.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserted and an interrupt will be generated, if enabled.

The OCxIF bit is located in the corresponding IFS

Status register, and must be cleared in software. The

interrupt is enabled via the respective compare inter-

rupt enable (OCxIE) bit, located in the corresponding

IEC Control register.

For example, if the pin was high when the CPU

entered the Sleep state, the pin will remain high. Like-

wise, if the pin was low when the CPU entered the

Sleep state, the pin will remain low. In either case, the

output compare module will resume operation when

the device wakes up.

For the PWM mode, when an event occurs, the respec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt will be generated, if enabled. The IF bit is

located in the IFS0 Status register, and must be cleared

in software. The interrupt is enabled via the respective

timer interrupt enable bit (T2IE or T3IE), located in the

IEC0 Control register. The output compare interrupt

flag is never set during the PWM mode of operation.

13.6 Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel will operate during the

CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at

logic 0and the selected time base (Timer2 or Timer3)

is enabled and the TSIDL bit of the selected timer is

set to logic 0.

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• Three input channels for two phase signals and

index pulse

14.0 QUADRATURE ENCODER

INTERFACE (QEI) MODULE

• 16-bit up/down position counter

This section describes the Quadrature Encoder Inter-

face (QEI) module and associated operational modes.

The QEI module provides the interface to incremental

encoders for obtaining motor positioning data. Incre-

mental encoders are very useful in motor control

applications.

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Quadrature Encoder Interface interrupts

The Quadrature Encoder Interface (QEI) is a key fea-

ture requirement for several motor control applications,

such as Switched Reluctance (SR) and AC Induction

Motor (ACIM). The operational features of the QEI are,

but not limited to:

These operating modes are determined by setting the

appropriate bits QEIM<2:0> (QEICON<10:8>).

Figure 14-1 depicts the Quadrature Encoder Interface

block diagram.

FIGURE 14-1:

QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM

TQCKPS<1:0>

2

Sleep Input

TQCS

T^CY

0

1

Synchronize

Det

Prescaler

1, 8, 64, 256

1

0

QEIM<2:0>

QEIIF

D

Q

Event

Flag

TQGATE

CK

16-bit Up/Down Counter

(POSCNT)

2

Programmable

Digital Filter

QEA

Reset

Quadrature

Encoder

Interface Logic

UPDN_SRC

Comparator/

Zero Detect

Equal

QEICON<11>

0

3

QEIM<2:0>

Mode Select

1

Max Count Register

(MAXCNT)

Programmable

Digital Filter

QEB

Programmable

Digital Filter

INDX

3

PCDOUT

Existing Pin Logic

0

UPDN

Up/Down

1

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reset when the index pulse is detected. The position

counter will continue counting up or down, and will be

reset on the rollover or underflow condition.

14.1 Quadrature Encoder Interface

Logic

A typical incremental (a.k.a. optical) encoder has three

outputs: Phase A, Phase B, and an index pulse. These

signals are useful and often required in position and

speed control of ACIM and SR motors.

The interrupt is still generated on the detection of the

index pulse and not on the position counter overflow/

underflow.

14.2.3

COUNT DIRECTION STATUS

The two channels, Phase A (QEA) and Phase B (QEB),

have a unique relationship. If Phase A leads Phase B,

then the direction (of the motor) is deemed positive or

forward. If Phase A lags Phase B, then the direction (of

the motor) is deemed negative or reverse.

As mentioned in the previous section, the QEI logic

generates an UPDN signal, based upon the relation-

ship between Phase A and Phase B. In addition to the

output pin, the state of this internal UPDN signal is sup-

plied to a SFR bit UPDN (QEICON<11>) as a read only

bit. To place the state of this signal on an I/O pin, the

SFR bit PCDOUT (QEICON<6>) must be 1.

A third channel, termed index pulse, occurs once per

revolution and is used as a reference to establish an

absolute position. The index pulse coincides with

Phase A and Phase B, both low.

14.3 Position Measurement Mode

14.2 16-bit Up/Down Position Counter

Mode

There are two Measurement modes which are sup-

ported and are termed x2 and x4. These modes are

selected by the QEIM<2:0> mode select bits located in

SFR QEICON<10:8>.

The 16-bit Up/Down Counter counts up or down on

every count pulse, which is generated by the difference

of the Phase A and Phase B input signals. The counter

acts as an integrator, whose count value is proportional

to position. The direction of the count is determined by

the UPDN signal, which is generated by the

Quadrature Encoder Interface Logic.

When control bits QEIM<2:0> = 100 or 101, the x2

Measurement mode is selected and the QEI logic only

looks at the Phase A input for the position counter

increment rate. Every rising and falling edge of the

Phase A signal causes the position counter to be incre-

mented or decremented. The Phase B signal is still uti-

lized for the determination of the counter direction, just

as in the x4 mode.

14.2.1

POSITION COUNTER ERROR

CHECKING

Position count error checking in the QEI is provided for

and indicated by the CNTERR bit (QEICON<15>). The

error checking only applies when the position counter

is configured for Reset on the Index Pulse modes

(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the con-

tents of the POSCNT register is compared with the val-

ues (0xFFFFor MAXCNT+1, depending on direction).

If these values are detected, an error condition is gen-

erated by setting the CNTERR bit and a QEI count

error interrupt is generated. The QEI count error inter-

rupt can be disabled by setting the CEID bit (DFLT-

CON<8>). The position counter continues to count

encoder edges after an error has been detected. The

POSCNT register continues to count up/down until a

natural rollover/underflow. No interrupt is generated for

the natural rollover/underflow event. The CNTERR bit

is a read/write bit and reset in software by the user.

Within the x2 Measurement mode, there are two

variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEIM<2:0> = 100.

2. Position counter reset by match with MAXCNT,

QEIM<2:0> = 101.

When control bits QEIM<2:0> = 110 or 111, the x4

Measurement mode is selected and the QEI logic looks

at both edges of the Phase A and Phase B input sig-

nals. Every edge of both signals causes the position

counter to increment or decrement.

Within the x4 Measurement mode, there are two

variations of how the position counter is reset:

1. Position counter reset by detection of index

pulse, QEIM<2:0> = 110.

2. Position counter reset by match with MAXCNT,

14.2.2

POSITION COUNTER RESET

QEIM<2:0> = 111.

The position counter Reset enable bit, POSRES

(QEI<2>) controls whether the position counter is reset

when the index pulse is detected. This bit is only

applicable when QEIM<2:0> = ‘100’ or ‘110’.

The x4 Measurement mode provides for finer resolu-

tion data (more position counts) for determining motor

position.

If the POSRES bit is set to ‘1’, then the position counter

is reset when the index pulse is detected. If the

POSRES bit is set to ‘0’, then the position counter is not

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In addition, control bit UPDN_SRC (QEICON<0>)

determines whether the timer count direction state is

based on the logic state, written into the UPDN control/

status bit (QEICON<11>), or the QEB pin state. When

UPDN_SRC = 1, the timer count direction is controlled

from the QEB pin. Likewise, when UPDN_SRC = 0, the

timer count direction is controlled by the UPDN bit.

14.4 Programmable Digital Noise

Filters

The digital noise filter section is responsible for reject-

ing noise on the incoming capture or quadrature sig-

nals. Schmitt Trigger inputs and a three-clock cycle

delay filter combine to reject low level noise and large,

short duration noise spikes that typically occur in noise

prone applications, such as a motor system.

Note:

This Timer does not support the External

Asynchronous Counter mode of operation.

If using an external clock source, the clock

will automatically be synchronized to the

internal instruction cycle.

The filter ensures that the filtered output signal is not

permitted to change until a stable value has been

registered for three consecutive clock cycles.

For the QEA, QEB and INDX pins, the clock divide fre-

quency for the digital filter is programmed by bits

QECK<2:0> (DFLTCON<6:4>) and are derived from

the base instruction cycle T^CY.

14.6 QEI Module Operation During CPU

Sleep Mode

14.6.1

QEI OPERATION DURING CPU

SLEEP MODE

To enable the filter output for channels QEA, QEB and

INDX, the QEOUT bit must be ‘1’. The filter network for

all channels is disabled on POR and BOR.

The QEI module will be halted during the CPU Sleep

mode.

14.5 Alternate 16-bit Timer/Counter

14.6.2

TIMER OPERATION DURING CPU

SLEEP MODE

When the QEI module is not configured for the QEI

mode QEIM<2:0> = 001, the module can be configured

as a simple 16-bit timer/counter. The setup and control

of the auxiliary timer is accomplished through the

QEICON SFR register. This timer functions identically

to Timer1. The QEA pin is used as the timer clock input.

During CPU Sleep mode, the timer will not operate,

because the internal clocks are disabled.

14.7 QEI Module Operation During CPU

Idle Mode

When configured as a timer, the POSCNT register

serves as the Timer Count Register and the MAXCNT

register serves as the Period Register. When a timer/

period register match occur, the QEI interrupt flag will

be asserted.

Since the QEI module can function as a quadrature

encoder interface, or as a 16-bit timer, the following

section describes operation of the module in both

modes.

The only exception between the general purpose tim-

ers and this timer is the added feature of external Up/

Down input select. When the UPDN pin is asserted

high, the timer will increment up. When the UPDN pin

is asserted low, the timer will be decremented.

14.7.1

QEI OPERATION DURING CPU IDLE

MODE

When the CPU is placed in the Idle mode, the QEI

module will operate if the QEISIDL bit (QEICON<13>)

= 0. This bit defaults to a logic ‘0’ upon executing POR

and BOR. For halting the QEI module during the CPU

Idle mode, QEISIDL should be set to ‘1’.

Note:

Changing the operational mode (i.e., from

QEI to Timer or vice versa), will not affect

the Timer/Position Count Register con-

tents.

The UPDN control/status bit (QEICON<11>) can be

used to select the count direction state of the Timer reg-

ister. When UPDN = 1, the timer will count up. When

UPDN = 0, the timer will count down.

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14.7.2

TIMER OPERATION DURING CPU

IDLE MODE

14.8 Quadrature Encoder Interface

Interrupts

When the CPU is placed in the Idle mode and the QEI

module is configured in the 16-bit Timer mode, the

16-bit timer will operate if the QEISIDL bit

(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon

executing POR and BOR. For halting the timer module

during the CPU Idle mode, QEISIDL should be set

to ‘1’.

The quadrature encoder interface has the ability to

generate an interrupt on occurrence of the following

events:

• Interrupt on 16-bit up/down position counter

rollover/underflow

• Detection of qualified index pulse, or if CNTERR

bit is set

If the QEISIDL bit is cleared, the timer will function

normally, as if the CPU Idle mode had not been

entered.

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI interrupt flag bit, QEIIF, is asserted upon

occurrence of any of the above events. The QEIIF bit

must be cleared in software. QEIIF is located in the

IFS2 Status register.

Enabling an interrupt is accomplished via the respec-

tive enable bit, QEIIE. The QEIIE bit is located in the

IEC2 Control register.

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NOTES:

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• Output override control for Electrically

15.0 MOTOR CONTROL PWM

MODULE

Commutative Motor (ECM) operation

• ‘Special Event’ comparator for scheduling other

peripheral events

This module simplifies the task of generating multiple,

synchronized Pulse Width Modulated (PWM) outputs.

In particular, the following power and motion control

applications are supported by the PWM module:

• FAULT pins to optionally drive each of the PWM

output pins to a defined state

This module contains 4 duty cycle generators, num-

bered 1 through 4. The module has 8 PWM output pins,

numbered PWM1H/PWM1L through PWM4H/PWM4L.

The eight I/O pins are grouped into high/low numbered

pairs, denoted by the suffix H or L, respectively. For

complementary loads, the low PWM pins are always

the complement of the corresponding high I/O pin.

• Three Phase AC Induction Motor

• Switched Reluctance (SR) Motor

• Brushless DC (BLDC) Motor

• Uninterruptible Power Supply (UPS)

The PWM module has the following features:

• 8 PWM I/O pins with 4 duty cycle generators

• Up to 16-bit resolution

There are two versions of the PWM module depending

on the particular dsPIC30F device selected: an 8-out-

put PWM module and a 6-output PWM module.

• ‘On-the-Fly’ PWM frequency changes

• Edge and Center Aligned Output modes

• Single Pulse Generation mode

Simplified block diagrams of the 8-output and 6-output

Motor Control PWM modules are shown in Figure 15-1

and Figure 15-2, respectively.

• Interrupt support for asymmetrical updates in

Center Aligned mode

TABLE 15-1: FEATURE SUMMARY: 6-OUTPUT PWM VS. 8-OUTPUT PWM

Feature

6-Output PWM Module

8-Output PWM Module

I/O Pins

6

3

1

8

4

2

PWM Generators

FAULT Input Pins

Dead-Time Generators

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FIGURE 15-1:

8-OUTPUT PWM MODULE BLOCK DIAGRAM

PWMCON1

PWMCON2

DTCON1

PWM Enable and Mode SFRs

Dead-Time Control SFRs

DTCON2

FLTACON

FLTBCON

OVDCON

FAULT Pin Control SFRs

PWM Manual

Control SFR

PWM Generator #4

PDC4 Buffer

PDC4

PWM4H

PWM4L

Comparator

Channel 4 Dead-Time

Generator and

Override Logic

PWM Generator

#3

PWM3H

PWM3L

PTMR

Comparator

PTPER

Channel 3 Dead-Time

Generator and

Output

Driver

Block

Override Logic

PWM Generator

#2

PWM2H

PWM2L

Channel 2 Dead-Time

Generator and

Override Logic

PWM Generator

#1

PWM1H

PWM1L

Channel 1 Dead-Time

Generator and

Override Logic

PTPER Buffer

FLTA

FLTB

PTCON

Special Event

Postscaler

Comparator

Special Event Trigger

SEVTDIR

PTDIR

SEVTCMP

PWM time base

Note:

Details of PWM Generator #1, #2, and #3 not shown for clarity.

DS70082C-page 100

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dsPIC30F

FIGURE 15-2:

6-OUTPUT PWM BLOCK DIAGRAM

PWMCON1

PWM Enable and Mode SFRs

PWMCON2

DTCON1

FLTACON

OVDCON

Dead-Time Control SFR

FAULT Pin Control SFR

PWM Manual

Control SFR

PWM Generator #3

PDC3 Buffer

PDC3

PWM3H

PWM3L

Comparator

Channel 3 Dead-Time

Generator and=

Override Logic

PWM Generator

#2

Output

PWM2H

PTMR

Comparator

PTPER

Channel 2 Dead-Time

Generator and=

Driver

Override Logic

PWM2L

Block

PWM Generator

#1

PWM1H

PWM1L

Channel 1 Dead-Time

Generator and=

Override Logic

FLTA

PTPER Buffer

mq`lk

Special Event

Postscaler

Comparator

Special Event Trigger

SEVTDIR

PTDIR

SEVTCMP

PWM time base

Note: Details of PWM Generator #1 and #2 not shown for clarity.

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The PWM module allows several modes of operation

which are beneficial for specific power control applica-

tions.

the following input clock edge and the time base will

continue to count upwards as long as the PTEN bit

remains set.

When the PWM time base is in the Free Running mode

(PTMOD<1:0> = 00), an interrupt event is generated

each time a match with the PTPER register occurs and

the PTMR register is reset to zero. The postscaler

selection bits may be used in this mode of the timer to

reduce the frequency of the interrupt events.

15.1 PWM Time Base

The PWM time base is provided by a 15-bit timer with

a prescaler and postscaler. The time base is accessible

via the PTMR SFR. PTMR<15> is a read only status

bit, PTDIR, that indicates the present count direction of

the PWM time base. If PTDIR is cleared, PTMR is

counting upwards. If PTDIR is set, PTMR is counting

downwards. The PWM time base is configured via the

PTCON SFR. The time base is enabled/disabled by

setting/clearing the PTEN bit in the PTCON SFR.

PTMR is not cleared when the PTEN bit is cleared in

software.

15.1.2

SINGLE SHOT MODE

In the Single Shot Counting mode, the PWM time base

begins counting upwards when the PTEN bit is set.

When the value in the PTMR register matches the

PTPER register, the PTMR register will be reset on the

following input clock edge and the PTEN bit will be

cleared by the hardware to halt the time base.

The PTPER SFR sets the counting period for PTMR.

The user must write a 15-bit value to PTPER<14:0>.

When the value in PTMR<14:0> matches the value in

PTPER<14:0>, the time base will either reset to 0, or

reverse the count direction on the next occurring clock

cycle. The action taken depends on the operating

mode of the time base.

When the PWM time base is in the Single Shot mode

(PTMOD<1:0> = 01), an interrupt event is generated

when a match with the PTPER register occurs, the

PTMR register is reset to zero on the following input

clock edge, and the PTEN bit is cleared. The postscaler

selection bits have no effect in this mode of the timer.

Note:

If the period register is set to 0x0000, the

timer will stop counting, and the interrupt

and the special event trigger will not be

generated, even if the special event value

is also 0x0000. The module will not

update the period register, if it is already at

0x0000; therefore, the user must disable

the module in order to update the period

register.

15.1.3

CONTINUOUS UP/DOWN

COUNTING MODES

In the Continuous Up/Down Counting modes, the PWM

time base counts upwards until the value in the PTPER

register is matched. The timer will begin counting

downwards on the following input clock edge. The

PTDIR bit in the PTCON SFR is read only and indicates

the counting direction The PTDIR bit is set when the

timer counts downwards.

The PWM time base can be configured for four different

modes of operation:

In the Up/Down Counting mode (PTMOD<1:0> = 10),

an interrupt event is generated each time the value of

the PTMR register becomes zero and the PWM time

base begins to count upwards. The postscaler selec-

tion bits may be used in this mode of the timer to reduce

the frequency of the interrupt events.

• Free Running mode

• Single Shot mode

• Continuous Up/Down Count mode

• Continuous Up/Down Count mode with interrupts

for double updates

15.1.4

DOUBLE UPDATE MODE

These four modes are selected by the PTMOD<1:0>

bits in the PTCON SFR. The Up/Down Counting modes

support center aligned PWM generation. The Single

Shot mode allows the PWM module to support pulse

control of certain Electronically Commutative Motors

(ECMs).

In the Double Update mode (PTMOD<1:0> = 11), an

interrupt event is generated each time the PTMR regis-

ter is equal to zero, as well as each time a period match

occurs. The postscaler selection bits have no effect in

this mode of the timer.

The Double Update mode provides two additional func-

tions to the user. First, the control loop bandwidth is

doubled because the PWM duty cycles can be

updated, twice per period. Second, asymmetrical cen-

ter-aligned PWM waveforms can be generated, which

are useful for minimizing output waveform distortion in

certain motor control applications.

The interrupt signals generated by the PWM time base

depend on the mode selection bits (PTMOD<1:0>) and

the postscaler bits (PTOPS<3:0>) in the PTCON SFR.

15.1.1

FREE RUNNING MODE

In the Free Running mode, the PWM time base counts

upwards until the value in the Time Base Period regis-

ter (PTPER) is matched. The PTMR register is reset on

Note:

Programming a value of 0x0001 in the

period register could generate a continu-

ous interrupt pulse, and hence, must be

avoided.

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The maximum resolution (in bits) for a given device

oscillator and PWM frequency can be determined using

Equation 15-2:

15.1.5

PWM TIME BASE PRESCALER

The input clock to PTMR (FOSC/4), has prescaler

options of 1:1, 1:4, 1:16, or 1:64, selected by control

bits PTCKPS<1:0> in the PTCON SFR. The prescaler

counter is cleared when any of the following occurs:

EQUATION 15-2: PWM RESOLUTION

• a write to the PTMR register

• a write to the PTCON register

• any device Reset

^{log (2}• TPWM / TCY)

Resolution =

log (2)

The PTMR register is not cleared when PTCON is

written.

15.3 Edge Aligned PWM

Edge aligned PWM signals are produced by the module

when the PWM time base is in the Free Running or Sin-

gle Shot mode. For edge aligned PWM outputs, the out-

put has a period specified by the value in PTPER and a

duty cycle specified by the appropriate duty cycle regis-

ter (see Figure 15-3). The PWM output is driven active

at the beginning of the period (PTMR = 0) and is driven

inactive when the value in the duty cycle register

matches PTMR.

15.1.6

PWM TIME BASE POSTSCALER

The match output of PTMR can optionally be post-

scaled through a 4-bit postscaler (which gives a 1:1 to

1:16 scaling).

The postscaler counter is cleared when any of the

following occurs:

• a write to the PTMR register

• a write to the PTCON register

• any device Reset

If the value in a particular duty cycle register is zero,

then the output on the corresponding PWM pin will be

inactive for the entire PWM period. In addition, the out-

put on the PWM pin will be active for the entire PWM

period if the value in the duty cycle register is greater

than the value held in the PTPER register.

The PTMR register is not cleared when PTCON is written.

15.2 PWM Period

PTPER is a 15-bit register and is used to set the count-

ing period for the PWM time base. PTPER is a double

buffered register. The PTPER buffer contents are

loaded into the PTPER register at the following instants:

FIGURE 15-3:

EDGE ALIGNED PWM

New Duty Cycle Latched

• Free Running and Single Shot modes: When the

PTMR register is reset to zero after a match with

the PTPER register.

PTPER

PTMR

• Up/Down Counting modes: When the PTMR

register is zero.

Value

The value held in the PTPER buffer is automatically

loaded into the PTPER register when the PWM time

base is disabled (PTEN = 0).

0

The PWM period can be determined using

Equation 15-1:

Duty Cycle

Period

EQUATION 15-1: PWM PERIOD

T^CY• (PTPER + 1)

TPWM =

15.4 Center Aligned PWM

(PTMR Prescale Value)

Center aligned PWM signals are produced by the mod-

ule when the PWM time base is configured in an Up/

Down Counting mode (see Figure 15-4).

If the PWM time base is configured for one of the Up/

Down Count modes, the PWM period will be twice the

value provided by Equation 15-1.

The PWM compare output is driven to the active state

when the value of the duty cycle register matches the

value of PTMR and the PWM time base is counting

downwards (PTDIR = 1). The PWM compare output is

driven to the inactive state when the PWM time base is

counting upwards (PTDIR = 0) and the value in the

PTMR register matches the duty cycle value.

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If the value in a particular duty cycle register is zero,

then the output on the corresponding PWM pin will be

inactive for the entire PWM period. In addition, the out-

put on the PWM pin will be active for the entire PWM

period if the value in the duty cycle register is equal to

the value held in the PTPER register.

When the PWM time base is in the Up/Down Counting

mode with double updates, new duty cycle values are

updated when the value of the PTMR register is zero,

and when the value of the PTMR register matches the

value in the PTPER register. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

FIGURE 15-4:

CENTER ALIGNED PWM

Period/2

15.6 Complementary PWM Operation

PTPER

PTMR

Value

In the Complementary mode of operation, each pair of

PWM outputs is obtained by a complementary PWM

signal. A dead-time may be optionally inserted during

device switching, when both outputs are inactive for a

short period (Refer to Section 15.7).

Duty

Cycle

0

In Complementary mode, the duty cycle comparison

units are assigned to the PWM outputs as follows:

• PDC1 register controls PWM1H/PWM1L outputs

• PDC2 register controls PWM2H/PWM2L outputs

• PDC3 register controls PWM3H/PWM3L outputs

• PDC4 register controls PWM4H/PWM4L outputs

Period

The Complementary mode is selected for each PWM

I/O pin pair by clearing the appropriate PMODx bit in the

PWMCON1 SFR. The PWM I/O pins are set to

Complementary mode by default upon a device Reset.

15.5 PWM Duty Cycle Comparison

Units

There are four 16-bit special function registers (PDC1,

PDC2, PDC3 and PDC4) used to specify duty cycle

values for the PWM module.

15.7 Dead-Time Generators

The value in each duty cycle register determines the

amount of time that the PWM output is in the active

state. The duty cycle registers are 16-bits wide. The LS

bit of a duty cycle register determines whether the

PWM edge occurs in the beginning. Thus, the PWM

resolution is effectively doubled.

Dead-time generation may be provided when any of

the PWM I/O pin pairs are operating in the Comple-

mentary Output mode. The PWM outputs use Push-

Pull drive circuits. Due to the inability of the power out-

put devices to switch instantaneously, some amount of

time must be provided between the turn off event of one

PWM output in a complementary pair and the turn on

event of the other transistor.

15.5.1

DUTY CYCLE REGISTER BUFFERS

The four PWM duty cycle registers are double buffered

to allow glitchless updates of the PWM outputs. For

each duty cycle, there is a duty cycle register that is

accessible by the user and a second duty cycle register

that holds the actual compare value used in the present

PWM period.

The PWM module allows two different dead-times to be

programmed. These two dead-times may be used in

one of two methods described below to increase user

flexibility:

• The PWM output signals can be optimized for dif-

ferent turn off times in the high side and low side

transistors in a complementary pair of transistors.

The first dead-time is inserted between the turn

off event of the lower transistor of the complemen-

tary pair and the turn on event of the upper tran-

sistor. The second dead-time is inserted between

the turn off event of the upper transistor and the

turn on event of the lower transistor.

For edge aligned PWM output, a new duty cycle value

will be updated whenever a match with the PTPER reg-

ister occurs and PTMR is reset. The contents of the

duty cycle buffers are automatically loaded into the

duty cycle registers when the PWM time base is dis-

abled (PTEN = 0) and the UDIS bit is cleared in

PWMCON2.

When the PWM time base is in the Up/Down Counting

mode, new duty cycle values are updated when the

value of the PTMR register is zero and the PWM time

base begins to count upwards. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

• The two dead-times can be assigned to individual

PWM I/O pin pairs. This Operating mode allows

the PWM module to drive different transistor/load

combinations with each complementary PWM I/O

pin pair.

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15.7.1

DEAD-TIME GENERATORS

15.7.3

DEAD-TIME RANGES

Each complementary output pair for the PWM module

has a 6-bit down counter that is used to produce the

dead-time insertion. As shown in Figure 15-5, each

dead-time unit has a rising and falling edge detector

connected to the duty cycle comparison output.

The amount of dead-time provided by each dead-time

unit is selected by specifying the input clock prescaler

value and a 6-bit unsigned value. The amount of dead-

time provided by each unit may be set independently.

Four input clock prescaler selections have been pro-

vided to allow a suitable range of dead-times, based on

the device operating frequency. The clock prescaler

option may be selected independently for each of the

two dead-time values. The dead-time clock prescaler

values are selected using the DTAPS<1:0> and

DTBPS<1:0> control bits in the DTCON1 SFR. One of

four clock prescaler options (T^CY, 2TCY, 4TCY or 8TCY)

may be selected for each of the dead-time values.

15.7.2

DEAD-TIME ASSIGNMENT

The DTCON2 SFR contains control bits that allow the

dead-times to be assigned to each of the complemen-

tary outputs. Table 15-2 summarizes the function of

each dead-time selection control bit.

TABLE 15-2: DEAD-TIME SELECTION BITS

After the prescaler values are selected, the dead-time

for each unit is adjusted by loading two 6-bit unsigned

values into the DTCON1 SFR.

Bit

Function

DTS1A Selects PWM1L/PWM1H active edge dead-time.

DTS1I

Selects PWM1L/PWM1H inactive edge

dead-time.

The dead-time unit prescalers are cleared on the fol-

lowing events:

DTS2A Selects PWM2L/PWM2H active edge dead-time.

DTS2I

Selects PWM2L/PWM2H inactive edge

dead-time.

• On a load of the down timer due to a duty cycle

comparison edge event.

DTS3A Selects PWM3L/PWM3H active edge dead-time.

• On a write to the DTCON1 or DTCON2 registers.

• On any device Reset.

DTS3I

Selects PWM3L/PWM3H inactive edge

dead-time.

Note:

The user should not modify the DTCON1

or DTCON2 values while the PWM mod-

ule is operating (PTEN = 1). Unexpected

results may occur.

DTS4A Selects PWM4L/PWM4H active edge dead-time.

DTS4I

Selects PWM4L/PWM4H inactive edge

dead-time.

FIGURE 15-5:

DEAD-TIME TIMING DIAGRAM

Duty Cycle Generator

PWMxH

PWMxL

Time selected by DTSxA bit (A or B)

Time selected by DTSxI bit (A or B)

In the Independent mode, each duty cycle generator is

connected to both of the PWM I/O pins in an output

pair. By using the associated duty cycle register and

the appropriate bits in the OVDCON register, the user

may select the following signal output options for each

PWM I/O pin operating in the Independent mode:

15.8 Independent PWM Output

An independent PWM Output mode is required for driv-

ing certain types of loads. A particular PWM output pair

is in the Independent Output mode when the corre-

sponding PMOD bit in the PWMCON1 register is set.

No dead-time control is implemented between adjacent

PWM I/O pins when the module is operating in the

Independent mode and both I/O pins are allowed to be

active simultaneously.

• I/O pin outputs PWM signal

• I/O pin inactive

• I/O pin active

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states after a device Reset occurs. The PWMPIN con-

figuration fuse allows the PWM module outputs to be

optionally enabled on a device Reset. If PWMPIN = 0,

the PWM outputs will be driven to their inactive states

at Reset. If PWMPIN = 1 (default), the PWM outputs

will be tri-stated. The HPOL bit specifies the polarity for

the PWMxH outputs, whereas the LPOL bit specifies

the polarity for the PWMxL outputs.

15.9 Single Pulse PWM Operation

The PWM module produces single pulse outputs when

the PTCON control bits PTMOD<1:0> = 10. Only edge

aligned outputs may be produced in the Single Pulse

mode. In Single Pulse mode, the PWM I/O pin(s) are

driven to the active state when the PTEN bit is set.

When a match with a duty cycle register occurs, the

PWM I/O pin is driven to the inactive state. When a

match with the PTPER register occurs, the PTMR reg-

ister is cleared, all active PWM I/O pins are driven to

the inactive state, the PTEN bit is cleared, and an

interrupt is generated.

15.11.1 OUTPUT PIN CONTROL

The PEN<4:1>H and PEN<4:1>L control bits in the

PWMCON1 SFR enable each high PWM output pin

and each low PWM output pin, respectively. If a partic-

ular PWM output pin not enabled, it is treated as a

general purpose I/O pin.

15.10 PWM Output Override

The PWM output override bits allow the user to manu-

ally drive the PWM I/O pins to specified logic states,

independent of the duty cycle comparison units.

15.12 PWM FAULT Pins

There are two FAULT pins (FLTA and FLTB) associated

with the PWM module. When asserted, these pins can

optionally drive each of the PWM I/O pins to a defined

state.

All control bits associated with the PWM output over-

ride function are contained in the OVDCON register.

The upper half of the OVDCON register contains eight

bits, POVDxH<4:1> and POVDxL<4:1>, that determine

which PWM I/O pins will be overridden. The lower half

of the OVDCON register contains eight bits,

POUTxH<4:1> and POUTxL<4:1>, that determine the

state of the PWM I/O pins when a particular output is

overridden via the POVD bits.

15.12.1 FAULT PIN ENABLE BITS

The FLTACON and FLTBCON SFRs each have 4 con-

trol bits that determine whether a particular pair of

PWM I/O pins is to be controlled by the FAULT input

pin. To enable a specific PWM I/O pin pair for FAULT

overrides, the corresponding bit should be set in the

FLTACON or FLTBCON register.

15.10.1 COMPLEMENTARY OUTPUT MODE

When a PWMxL pin is driven active via the OVDCON

register, the output signal is forced to be the comple-

ment of the corresponding PWMxH pin in the pair.

Dead-time insertion is still performed when PWM

channels are overridden manually.

If all enable bits are cleared in the FLTACON or

FLTBCON registers, then the corresponding FAULT

input pin has no effect on the PWM module and the pin

may be used as a general purpose interrupt or I/O pin.

Note:

The FAULT pin logic can operate indepen-

dent of the PWM logic. If all the enable bits

in the FLTACON/FLTBCON register are

cleared, then the FAULT pin(s) could be

used as general purpose interrupt pin(s).

Each FAULT pin has an interrupt vector,

interrupt flag bit and interrupt priority bits

associated with it.

15.10.2 OVERRIDE SYNCHRONIZATION

If the OSYNC bit in the PWMCON2 register is set, all

output overrides performed via the OVDCON register

are synchronized to the PWM time base. Synchronous

output overrides occur at the following times:

• Edge Aligned mode, when PTMR is zero.

• Center Aligned modes, when PTMR is zero and

when the value of PTMR matches PTPER.

15.12.2 FAULT STATES

The FLTACON and FLTBCON special function regis-

ters have 8 bits each that determine the state of each

PWM I/O pin when it is overridden by a FAULT input.

When these bits are cleared, the PWM I/O pin is driven

to the inactive state. If the bit is set, the PWM I/O pin

will be driven to the active state. The active and inactive

states are referenced to the polarity defined for each

PWM I/O pin (HPOL and LPOL polarity control bits).

15.11 PWM Output and Polarity Control

There are three device configuration bits associated

with the PWM module that provide PWM output pin

control:

• HPOL configuration bit

• LPOL configuration bit

• PWMPIN configuration bit

A special case exists when a PWM module I/O pair is

in the Complementary mode and both pins are pro-

grammed to be active on a FAULT condition. The

PWMxH pin always has priority in the Complementary

mode, so that both I/O pins cannot be driven active

simultaneously.

These three bits in the FPORBOR configuration regis-

ter (see Section 21) work in conjunction with the four

PWM enable bits (PWMEN<4:1>) located in the

PWMCON1 SFR. The configuration bits and PWM

enable bits ensure that the PWM pins are in the correct

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15.12.3 FAULT PIN PRIORITY

15.14 PWM Special Event Trigger

If both FAULT input pins have been assigned to control

a particular PWM I/O pin, the FAULT state programmed

for the FAULT A input pin will take priority over the

FAULT B input pin.

The PWM module has a special event trigger that

allows A/D conversions to be synchronized to the PWM

time base. The A/D sampling and conversion time may

be programmed to occur at any point within the PWM

period. The special event trigger allows the user to min-

imize the delay between the time when A/D conversion

results are acquired and the time when the duty cycle

value is updated.

15.12.4 FAULT INPUT MODES

Each of the FAULT input pins has two modes of

operation:

• Latched Mode: When the FAULT pin is driven

low, the PWM outputs will go to the states defined

in the FLTACON/FLTBCON register. The PWM

outputs will remain in this state until the FAULT

pin is driven high and the corresponding interrupt

flag has been cleared in software. When both of

these actions have occurred, the PWM outputs

will return to normal operation at the beginning of

the next PWM cycle or half-cycle boundary. If the

interrupt flag is cleared before the FAULT condi-

tion ends, the PWM module will wait until the

FAULT pin is no longer asserted, to restore the

outputs.

The PWM special event trigger has an SFR named

SEVTCMP, and five control bits to control its operation.

The PTMR value for which a special event trigger

should occur is loaded into the SEVTCMP register.

When the PWM time base is in an Up/Down Counting

mode, an additional control bit is required to specify the

counting phase for the special event trigger. The count

phase is selected using the SEVTDIR control bit in the

SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-

cial event trigger will occur on the upward counting

cycle of the PWM time base. If the SEVTDIR bit is set,

the special event trigger will occur on the downward

count cycle of the PWM time base. The SEVTDIR

control bit has no effect unless the PWM time base is

configured for an Up/Down Counting mode.

• Cycle-by-Cycle Mode: When the FAULT input

pin is driven low, the PWM outputs remain in the

defined FAULT states for as long as the FAULT

pin is held low. After the FAULT pin is driven high,

the PWM outputs return to normal operation at the

beginning of the following PWM cycle or

half-cycle boundary.

15.14.1 SPECIAL EVENT TRIGGER

POSTSCALER

The PWM special event trigger has a postscaler that

allows a 1:1 to 1:16 postscale ratio. The postscaler is

configured by writing the SEVOPS<3:0> control bits in

the PWMCON2 SFR.

The Operating mode for each FAULT input pin is

selected using the FLTAM and FLTBM control bits in

the FLTACON and FLTBCON Special Function

Registers.

The special event output postscaler is cleared on the

following events:

Each of the FAULT pins can be controlled manually in

software.

• Any write to the SEVTCMP register

• Any device Reset

15.13 PWM Update Lockout

15.15 PWM Operation During CPU Sleep

Mode

For a complex PWM application, the user may need to

write up to four duty cycle registers and the time base

period register, PTPER, at a given time. In some appli-

cations, it is important that all buffer registers be written

before the new duty cycle and period values are loaded

for use by the module.

The FAULT A and FAULT B input pins have the ability

to wake the CPU from Sleep mode. The PWM module

generates an interrupt if either of the FAULT pins is

driven low while in Sleep.

The PWM update lockout feature is enabled by setting

the UDIS control bit in the PWMCON2 SFR. The UDIS

bit affects all duty cycle buffer registers and the PWM

time base period buffer, PTPER. No duty cycle

changes or period value changes will have effect while

UDIS = 1.

15.16 PWM Operation During CPU Idle

Mode

The PTCON SFR contains a PTSIDL control bit. This

bit determines if the PWM module will continue to

operate or stop when the device enters Idle mode. If

PTSIDL = 0, the module will continue to operate. If

PTSIDL = 1, the module will stop operation as long as

the CPU remains in Idle mode.

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In Slave mode, data is transmitted and received as

external clock pulses appear on SCK. Again, the inter-

rupt is generated when the last bit is latched. If SSx

control is enabled, then transmission and reception

are enabled only when SSx = low. The SDOx output

will be disabled in SSx mode with SSx high.

16.0 SPI™ MODULE

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface. It is useful for communicating

with other peripheral devices such as EEPROMs, shift

registers, display drivers and A/D converters, or other

microcontrollers. It is compatible with Motorola's SPI

and SIOP interfaces.

The clock provided to the module is (F^OSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on transi-

tion from active clock state to Idle clock state, or vice

versa. The CKP bit selects the Idle state (high or low)

for the clock.

16.1 Operating Function Description

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in

and out, and a buffer register, SPIxBUF. A control reg-

ister, SPIxCON, configures the module. Additionally, a

status register, SPIxSTAT, indicates various status

conditions.

16.1.1

WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPIxCON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.

16-bit operation is identical to 8-bit operation, except

that the number of bits transmitted is 16 instead of 8.

The serial interface consists of 4 pins: SDIx (serial

data input), SDOx (serial data output), SCKx (shift

clock input or output), and SSx (active low slave

select).

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

In Master mode operation, SCK is a clock output, but

in Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shifts

out bits from the SPIxSR to SDOx pin and simulta-

neously shifts in data from SDIx pin. An interrupt is

generated when the transfer is complete and the cor-

responding interrupt flag bit (SPI1IF or SPI2IF) is set.

This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

A basic difference between 8-bit and 16-bit operation is

that the data is transmitted out of bit 7 of the SPIxSR for

8-bit operation, and data is transmitted out of bit 15 of

the SPIxSR for 16-bit operation. In both modes, data is

shifted into bit 0 of the SPIxSR.

16.1.2

SDOx DISABLE

The receive operation is double buffered. When a

complete byte is received, it is transferred from

SPIxSR to SPIxBUF.

A control bit, DISSDO, is provided to the SPIxCON reg-

ister to allow the SDOx output to be disabled. This will

allow the SPI module to be connected in an input only

configuration. SDO can also be used for general

purpose I/O.

If the receive buffer is full when new data is being

transferred from SPIxSR to SPIxBUF, the module will

set the SPIROV bit, indicating an overflow condition.

The transfer of the data from SPIxSR to SPIxBUF will

not be completed and the new data will be lost. The

module will not respond to SCL transitions while

SPIROV is 1, effectively disabling the module until

SPIxBUF is read by user software.

16.2 Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit FRMEN enables

framed SPI support and causes the SSx pin to perform

the frame synchronization pulse (FSYNC) function.

The control bit SPIFSD determines whether the SSx

pin is an input or an output (i.e., whether the module

receives or generates the frame synchronization

pulse). The frame pulse is an active high pulse for a sin-

gle SPI clock cycle. When frame synchronization is

enabled, the data transmission starts only on the sub-

sequent transmit edge of the SPI clock.

Transmit writes are also double buffered. The user

writes to SPIxBUF. When the master or slave transfer

is completed, the contents of the shift register

(SPIxSR) is moved to the receive buffer. If any trans-

mit data has been written to the buffer register, the

contents of the transmit buffer are moved to SPIxSR.

The received data is thus placed in SPIxBUF and the

transmit data in SPIxSR is ready for the next transfer.

Note:

Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

In Master mode, the clock is generated by prescaling

the system clock. Data is transmitted as soon as a

value is written to SPIxBUF. The interrupt is generated

at the middle of the transfer of the last bit.

 2003 Microchip Technology Inc.

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dsPIC30F

FIGURE 16-1:

SPI BLOCK DIAGRAM

Internal

Data Bus

Read

Write

SPIxBUF

Transmit

SPIxBUF

Receive

SPIxSR

SDIx

bit0

SDOx

Shift

clock

SS & FSYNC

Control

Clock

Control

Edge

Select

SSx

Secondary

Prescaler

1,2,4,6,8

Primary

Prescaler

1, 4, 16, 64

F^OSC

SCKx

Enable Master Clock

Note: x = 1 or 2.

FIGURE 16-2:

SPI MASTER/SLAVE CONNECTION

SPI Master

SPI Slave

SDOx

SDIy

Serial Input Buffer

(SPIxBUF)

Serial Input Buffer

(SPIyBUF)

SDIx

SDOy

Shift Register

(SPIySR)

(SPIxSR)

LSb

MSb

LSb

Serial Clock

SCKx

SCKy

PROCESSOR 1

PROCESSOR 2

Note: x = 1 or 2, y = 1 or 2.

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16.3 Slave Select Synchronization

16.4 SPI Operation During CPU Sleep

Mode

The SSx pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode, with SSx

pin control enabled (SSEN = 1). When the SSx pin is

low, transmission and reception are enabled, and the

SDOx pin is driven. When SSx pin goes high, the SDOx

pin is no longer driven. Also, the SPI module is re-

synchronized, and all counters/control circuitry are

reset. Therefore, when the SSx pin is asserted low

again, transmission/reception will begin at the MS bit,

even if SSx had been de-asserted in the middle of a

transmit/receive.

During Sleep mode, the SPI module is shut-down. If

the CPU enters Sleep mode while an SPI transaction

is in progress, then the transmission and reception is

aborted.

The transmitter and receiver will stop in Sleep mode.

However, register contents are not affected by

entering or exiting Sleep mode.

16.5 SPI Operation During CPU Idle

Mode

When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPIxSTAT<13>)

selects if the SPI module will stop or continue on Idle.

If SPISIDL = 0, the module will continue to operate

when the CPU enters Idle mode. If SPISIDL = 1, the

module will stop when the CPU enters Idle mode.

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2

17.0 I C MODULE

17.1 Operating Function Description

2

The Inter-Integrated Circuit (I C) module provides

The hardware fully implements all the master and slave

2

functions of the I C Standard and Fast mode specifica-

complete hardware support for both Slave and Multi-

2

Master modes of the I C serial communication

tions, as well as 7 and 10-bit addressing.

2

Thus, the I C module can operate either as a slave or

standard, with a 16-bit interface.

2

a master on an I C bus.

This module offers the following key features:

2

• I C interface supporting both Master and Slave

2

VARIOUS I C MODES

17.1.1

operation.

2

The following types of I C operation are supported:

2

• I C Slave mode supports 7 and 10-bit address.

2

• I C Slave operation with 7-bit address

2

• I C Master mode supports 7 and 10-bit address.

2

• I C Slave operation with 10-bit address

2

• I C port allows bi-directional transfers between

2

• I C Master operation with 7 or 10-bit address

master and slaves.

2

• Serial clock synchronization for I C port can be

2

See the I C programmer’s model in Figure 17-1.

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

2

• I C supports Multi-Master operation; detects bus

collision and will arbitrate accordingly.

FIGURE 17-1:

PROGRAMMER’S MODEL

I2CRCV (8 bits)

bit 0

bit 7

I2CTRN (8 bits)

bit 0

bit 7

I2CBRG (9 bits)

bit 0

bit 8

I2CCON (16-bits)

bit 0

bit 15

I2CSTAT (16-bits)

bit 0

I2CADD (10-bits)

bit 0

bit 9

2

PIN CONFIGURATION IN I C MODE

The I2CADD register holds the slave address. A status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the baud rate generator reload value.

17.1.2

2

I C has a 2-pin interface; pin SCL is clock and pin SDA

is data.

In receive operations, I2CRSR and I2CRCV together

form a double buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and an interrupt pulse is generated. During transmis-

sion, the I2CTRN is not double buffered.

2

I C REGISTERS

17.1.3

I2CCON and I2CSTAT are control and status registers,

respectively. The I2CCON register is readable and writ-

able. The lower 6 bits of I2CSTAT are read only. The

remaining bits of the I2CSTAT are read/write.

Note:

Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit address.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer, as shown in Figure 16-1.

I2CTRN is the transmit register to which bytes are writ-

ten during a transmit operation, as shown in Figure 16-2.

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2

I C BLOCK DIAGRAM

FIGURE 17-2:

Internal

Data Bus

I2CRCV

Read

Shift

SCL

Clock

I2CRSR

LSB

SDA

Addr_Match

Match Detect

Write

I2CADD

Read

Start and

Stop bit Detect

Write

Start, Restart,

Stop bit Generate

Read

Collision

Detect

Write

Acknowledge

Generation

Read

Clock

Stretching

Write

I2CTRN

LSB

Shift

Read

Clock

Reload

Control

Write

I2CBRG

BRG Down

Counter

Read

FOSC

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2

17.2 I C Module Addresses

If the RBF flag is set, indicating that I2CRCV is still

holding data from a previous operation (RBF = 1), then

ACK is not sent; however, the interrupt pulse is gener-

ated. In the case of an overflow, the contents of the

I2CRSR are not loaded into the I2CRCV.

The I2CADD register contains the Slave mode

addresses. The register is a 10-bit register.

If the A10M bit (I2CCON<10>) is ‘0’, the address is

interpreted by the module as a 7-bit address. When an

address is received, it is compared to the 7 LS bits of

the I2CADD register.

Note:

The I2CRCV will be loaded if the I2COV

bit = 1and the RBF flag = 0. In this case,

a read of the I2CRCV was performed, but

the user did not clear the state of the

I2COV bit before the next receive

occurred. The acknowledgement is not

sent (ACK = 1) and the I2CRCV is

updated.

If the A10M bit is 1, the address is assumed to be a 10-

bit address. When an address is received, it will be

compared with the binary value ‘1 1 1 1 0 A9 A8’

(where A9, A8 are two Most Significant bits of

I2CADD). If that value matches, the next address will

be compared with the Least Significant 8-bits of

I2CADD, as specified in the 10-bit addressing protocol.

2

17.4 I C 10-bit Slave Mode Operation

2

17.3 I C 7-bit Slave Mode Operation

In 10-bit mode, the basic receive and transmit opera-

tions are the same as in the 7-bit mode. However, the

criteria for address match is more complex.

Once enabled (I2CEN = 1), the slave module will wait

2

for a Start bit to occur (i.e., the I C module is ‘Idle’). Fol-

2

The I C specification dictates that a slave must be

lowing the detection of a Start bit, 8 bits are shifted into

I2CRSR and the address is compared against

I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>

are compared against I2CRSR<7:1> and I2CRSR<0>

is the R_W bit. All incoming bits are sampled on the ris-

ing edge of SCL.

addressed for a write operation, with two address bytes

following a Start bit.

The A10M bit is a control bit that signifies that the

address in I2CADD is a 10-bit address rather than a

7-bit address. The address detection protocol for the

first byte of a message address is identical for 7-bit

and 10-bit messages, but the bits being compared are

different.

If an address match occurs, an acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is

set on the falling edge of the ninth (ACK) bit. The

address match does not affect the contents of the

I2CRCV buffer or the RBF bit.

I2CADD holds the entire 10-bit address. Upon receiv-

ing an address following a Start bit, I2CRSR <7:3> is

compared against a literal ‘11110’ (the default 10-bit

address) and I2CRSR<2:1> are compared against

I2CADD<9:8>. If a match occurs and if R_W = 0, the

interrupt pulse is sent. The ADD10 bit will be cleared to

indicate a partial address match. If a match fails or

R_W = 1, the ADD10 bit is cleared and the module

returns to the Idle state.

17.3.1

SLAVE TRANSMISSION

If the R_W bit received is a '1', then the serial port will

go into Transmit mode. It will send ACK on the ninth bit

and then hold SCL to '0' until the CPU responds by writ-

ing to I2CTRN. SCL is released by setting the SCLREL

bit, and 8 bits of data are shifted out. Data bits are

shifted out on the falling edge of SCL, such that SDA is

valid during SCL high (see timing diagram). The inter-

rupt pulse is sent on the falling edge of the ninth clock

pulse, regardless of the status of the ACK received

from the master.

The low byte of the address is then received and com-

pared with I2CADD<7:0>. If an address match occurs,

the interrupt pulse is generated and the ADD10 bit is

set, indicating a complete 10-bit address match. If an

address match did not occur, the ADD10 bit is cleared

and the module returns to the Idle state.

17.3.2

SLAVE RECEPTION

17.4.1

10-BIT MODE SLAVE

TRANSMISSION

If the R_W bit received is a '0' during an address match,

then Receive mode is initiated. Incoming bits are sam-

pled on the rising edge of SCL. After 8 bits are

received, if I2CRCV is not full or I2COV is not set,

I2CRSR is transferred to I2CRCV. ACK is sent on the

ninth clock.

Once a slave is addressed in this fashion, with the full

10-bit address (we will refer to this state as

"PRIOR_ADDR_MATCH"), the master can begin send-

ing data bytes for a slave reception operation.

17.4.2

10-BIT MODE SLAVE RECEPTION

Once addressed, the master can generate a Repeated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus initiating a

slave transmit operation.

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17.5 Automatic Clock Stretch

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

In the Slave modes, the module can synchronize buffer

reads and write to the master device by clock

stretching.

17.5.1

TRANSMIT CLOCK STRETCHING

2: The SCLREL bit can be set in software,

regardless of the state of the RBF bit. The

user should be careful to clear the RBF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock if the TBF bit is cleared, indicat-

ing the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit.

17.5.4

CLOCK STRETCHING DURING

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the falling edge of the ninth clock, and if the

TBF bit is still clear, then the SCLREL bit is automati-

cally cleared. The SCLREL being cleared to ‘0’ will

assert the SCL line low. The user’s ISR must set the

SCLREL bit before transmission is allowed to con-

tinue. By holding the SCL line low, the user has time to

service the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

register for the entire address, it is not necessary for

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence

as was described earlier.

17.6 Software Controlled Clock

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge

of the ninth clock, the SCLREL bit will not

be cleared and clock stretching will not

occur.

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to

the SCLREL bit with the SCL clock. Clearing the

SCLREL bit will not assert the SCL output until the

module detects a falling edge on the SCL output and

SCL is sampled low. If the SCLREL bit is cleared by

the user while the SCL line has been sampled low, the

SCL output will be asserted (held low). The SCL out-

put will remain low until the SCLREL bit is set, and all

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

17.5.2

RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at

the end of each data receive sequence.

2

other devices on the I C bus have de-asserted SCL.

This ensures that a write to the SCLREL bit will not

violate the minimum high time requirement for SCL.

17.5.3

CLOCK STRETCHING DURING

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

7-BIT ADDRESSING (STREN = 1)

When the STREN bit is set in Slave Receive mode,

the SCL line is held low when the buffer register is full.

The method for stretching the SCL output is the same

for both 7 and 10-bit Addressing modes.

17.7 Interrupts

2

The I C module generates two interrupt flags, MI2CIF

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing the

SCL output to be held low. The user’s ISR must set the

SCLREL bit before reception is allowed to continue. By

holding the SCL line low, the user has time to service

the ISR and read the contents of the I2CRCV before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring.

2

(I C Master Interrupt Flag) and SI2CIF (I C Slave Inter-

rupt Flag). The MI2CIF interrupt flag is activated on

completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

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condition. Since the Repeated Start condition is also

17.8 Slope Control

2

the beginning of the next serial transfer, the I C bus will

2

The I C standard requires slope control on the SDA

not be released.

and SCL signals for Fast Mode (400 kHz). The control

bit, DISSLW, enables the user to disable slew rate con-

trol, if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this case, the data direction bit (R_W) is logic 0. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted, an ACK bit is received. Start and Stop con-

ditions are output to indicate the beginning and the end

of a serial transfer.

17.9 IPMI Support

The control bit IPMIEN enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device (7

bits) and the data direction bit. In this case, the data

direction bit (R_W) is logic 1. Thus, the first byte trans-

mitted is a 7-bit slave address, followed by a ‘1’ to indi-

cate receive bit. Serial data is received via SDA, while

SCL outputs the serial clock. Serial data is received 8

bits at a time. After each byte is received, an ACK bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

17.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in the-

ory, respond with an acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all 0’s with R_W = 0.

The general call address is recognized when the Gen-

eral Call Enable (GCEN) bit is set (I2CCON<15> = 1).

Following a Start bit detection, 8 bits are shifted into

I2CRSR and the address is compared with I2CADD,

and is also compared with the general call address

which is fixed in hardware.

2

17.12.1 I C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address, or the sec-

ond half of a 10-bit address is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a WAIT

state. This action will set the buffer full flag (TBF) and

allow the baud rate generator to begin counting and

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

If a general call address match occurs, the I2CRSR is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set, and on the falling edge of the ninth bit

(ACK bit), the master event interrupt flag (MI2CIF) is

set.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific, or a general call address.

2

17.12.2 I C MASTER RECEPTION

Master mode reception is enabled by programming the

2

receive enable (RCEN) bit (I2CCON<11>). The I C

2

17.11 I C Master Support

module must be Idle before the RCEN bit is set, other-

wise the RCEN bit will be disregarded. The baud rate

generator begins counting, and on each rollover, the

state of the SCL pin toggles, and data is shifted in to the

I2CRSR on the rising edge of each clock.

As a Master device, six operations are supported.

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

17.12.3 BAUD RATE GENERATOR

2

In I C Master mode, the reload value for the BRG is

• Generate a Stop condition on SDA and SCL.

2

• Configure the I C port to receive data.

located in the I2CBRG register. When the BRG is

loaded with this value, the BRG counts down to 0 and

stops until another reload has taken place. If clock arbi-

tration is taking place, for instance, the BRG is reloaded

when the SCL pin is sampled high.

• Generate an ACK condition at the end of a

received byte of data.

2

17.12 I C Master Operation

2

As per the I C standard, FSCK may be 100 kHz or

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of 0or 1are illegal.

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If a Start, Restart, Stop or Acknowledge condition was

in progress when the bus collision occurred, the condi-

tion is aborted, the SDA and SCL lines are de-asserted,

and the respective control bits in the I2CCON register

are cleared to 0. When the user services the bus colli-

sion Interrupt Service Routine, and if the I²C bus is free,

the user can resume communication by asserting a

Start condition.

EQUATION 17-1: SERIAL CLOCK RATE

FSCK = FCY / I2CBRG

17.12.4 CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit, or Restart/Stop condition. When the

SCL pin is allowed to float high, the baud rate generator

(BRG) is suspended from counting until the SCL pin is

actually sampled high. When the SCL pin is sampled

high, the baud rate generator is reloaded with the con-

tents of I2CBRG and begins counting. This ensures

that the SCL high time will always be at least one BRG

rollover count in the event that the clock is held low by

an external device.

The Master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

A write to the I2CTRN will start the transmission of data

at the first data bit, regardless of where the transmitter

left off when bus collision occurred.

In a Multi-Master environment, the interrupt generation

on the detection of Start and Stop conditions allows the

2

determination of when the bus is free. Control of the I C

bus can be taken when the P bit is set in the I2CSTAT

register, or the bus is Idle and the S and P bits are

cleared.

17.12.5 MULTI-MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

Multi-Master operation support is achieved by bus arbi-

tration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a 1on SDA, by letting SDA float high

while another master asserts a 0. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a 1 and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The mas-

ter will set the MI2CIF pulse and reset the master por-

2

17.13 I C Module Operation During CPU

Sleep and Idle Modes

2

17.13.1 I C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission, and the

state machine is partially into a transmission as the

clocks stop, then the transmission is aborted. Similarly,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

2

tion of the I C port to its Idle state.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are de-asserted, and a

value can now be written to I2CTRN. When the user

2

17.13.2 I C OPERATION DURING CPU IDLE

2

services the I C master event Interrupt Service Rou-

2

tine, if the I C bus is free (i.e., the P bit is set) the user

MODE

2

For the I C, the I2CSIDL bit selects if the module will

can resume communication by asserting a Start

condition.

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue operation on assertion of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

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NOTES:

DS70082C-page 120

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• Fully integrated Baud Rate Generator with 16-bit

prescaler

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART) MODULE

• Baud rates range from 38 bps to 1.875 Mbps at a

30 MHz instruction rate

This section describes the Universal Asynchronous

Receiver/Transmitter Communications module.

• 4-word deep transmit data buffer

• 4-word deep receive data buffer

• Parity, Framing and Buffer Overrun error detection

18.1 UART Module Overview

• Support for Interrupt only on Address Detect

(9th bit = 1)

The key features of the UART module are:

• Separate Transmit and Receive Interrupts

• Full-duplex, 8 or 9-bit data communication

• Even, Odd or No Parity options (for 8-bit data)

• One or two Stop bits

• Loopback mode for diagnostic support

FIGURE 18-1:

UART TRANSMITTER BLOCK DIAGRAM

Internal Data Bus

Control and Status bits

Write

UTX8

UxTXREG Low Byte

Transmit Control

– Control TSR

– Control Buffer

– Generate Flags

– Generate Interrupt

Load TSR

UxTXIF

UTXBRK

Data

Transmit Shift Register (UxTSR)

‘0’ (Start)

‘1’ (Stop)

UxTX

16X Baud Clock

from Baud Rate

Generator

Parity

16 Divider

Parity

Generator

Control

Signals

Note: x = 1 or 2.

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dsPIC30F

FIGURE 18-2:

UART RECEIVER BLOCK DIAGRAM

Internal Data Bus

16

Write

Read

Read Read

Write

UxMODE

UxSTA

UxRXREG Low Byte

URX8

Receive Buffer Control

– Generate Flags

– Generate Interrupt

– Shift Data Characters

8-9

LPBACK

From UxTX

Load RSR

to Buffer

Receive Shift Register

(UxRSR)

1

Control

Signals

UxRX

0

· START bit Detect

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

16 Divider

16X Baud Clock from

Baud Rate Generator

UxRXIF

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18.2 Enabling and Setting Up UART

18.3 Transmitting Data

18.2.1

ENABLING THE UART

18.3.1

TRANSMITTING IN 8-BIT DATA

MODE

The UART module is enabled by setting the UARTEN

bit in the UxMODE register (where x = 1 or 2). Once

enabled, the UxTX and UxRX pins are configured as an

output and an input respectively, overriding the TRIS

and LATCH register bit settings for the corresponding

I/O port pins. The UxTX pin is at logic ‘1’ when no

transmission is taking place.

The following steps must be performed in order to

transmit 8-bit data:

1. Set up the UART:

First, the data length, parity and number of Stop

bits must be selected. Then, the Transmit and

Receive Interrupt enable and priority bits are

setup in the UxMODE and UxSTA registers.

Also, the appropriate baud rate value must be

written to the UxBRG register.

18.2.2

DISABLING THE UART

The UART module is disabled by clearing the

UARTEN bit in the UxMODE register. This is the

default state after any Reset. If the UART is disabled,

all I/O pins operate as port pins under the control of

the latch and TRIS bits of the corresponding port pins.

2. Enable the UART by setting the UARTEN bit

(UxMODE<15>).

3. Set the UTXEN bit (UxSTA<10>), thereby

enabling a transmission.

Disabling the UART module resets the buffers to

empty states. Any data characters in the buffers are

lost, and the baud rate counter is reset.

4. Write the byte to be transmitted to the lower byte

of UxTXREG. The value will be transferred to the

Transmit Shift register (UxTSR) immediately

and the serial bit stream will start shifting out

during the next rising edge of the baud clock.

Alternatively, the data byte may be written while

UTXEN = 0, following which, the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

All error and status flags associated with the UART

module are reset when the module is disabled. The

URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and

UTXBF bits are cleared, whereas RIDLE and TRMT

are set. Other control bits, including ADDEN,

URXISEL<1:0>, UTXISEL, as well as the UxMODE

and UxBRG registers, are not affected.

5. A Transmit interrupt will be generated depend-

ing on the value of the interrupt control bit

UTXISEL (UxSTA<15>).

Clearing the UARTEN bit while the UART is active will

abort all pending transmissions and receptions and

reset the module as defined above. Re-enabling the

UART will restart the UART in the same configuration.

18.3.2

TRANSMITTING IN 9-BIT DATA

MODE

18.2.3

ALTERNATE I/O

The sequence of steps involved in the transmission of

9-bit data is similar to 8-bit transmission, except that a

16-bit data word (of which the upper 7 bits are always

clear) must be written to the UxTXREG register.

The alternate I/O function is enabled by setting the

ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX

and UxARX pins (alternate transmit and alternate

receive pins, respectively) are used by the UART mod-

ule instead of the UxTX and UxRX pins. If ALTIO = 0,

the UxTX and UxRX pins are used by the UART

module.

18.3.3

TRANSMIT BUFFER (UXTXB)

The transmit buffer is 9-bits wide and 4 characters

deep. Including the Transmit Shift Register (UxTSR),

the user effectively has a 5-deep FIFO (First In First

Out) buffer. The UTXBF status bit (UxSTA<9>)

indicates whether the transmit buffer is full.

18.2.4

SETTING UP DATA, PARITY AND

STOP BIT SELECTIONS

Control bits PDSEL<1:0> in the UxMODE register are

used to select the data length and parity used in the

transmission. The data length may either be 8-bits with

even, odd or no parity, or 9-bits with no parity.

If a user attempts to write to a full buffer, the new data

will not be accepted into the FIFO, and no data shift

will occur within the buffer. This enables recovery from

a buffer overrun condition.

The STSEL bit determines whether one or two Stop bits

will be used during data transmission.

The FIFO is reset during any device Reset, but is not

affected when the device enters or wakes up from a

Power Saving mode.

The default (Power-on) setting of the UART is 8 bits, no

parity, 1 Stop bit (typically represented as 8, N, 1).

 2003 Microchip Technology Inc.

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18.3.4

TRANSMIT INTERRUPT

18.4.2

RECEIVE BUFFER (UXRXB)

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

The transmitter generates an edge to set the UxTXIF

bit. The condition for generating the interrupt depends

on UTXISEL control bit:

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0implies that the

buffer is empty. If a user attempts to read an empty

buffer, the old values in the buffer will be read and no

data shift will occur within the FIFO.

a) If UTXISEL = 0, an interrupt is generated when

a word is transferred from the Transmit buffer to

the Transmit Shift register (UxTSR). This implies

that the transmit buffer has at least one empty

word.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

Power Saving mode.

b) If UTXISEL = 1, an interrupt is generated when

a word is transferred from the Transmit buffer to

the Transmit Shift register (UxTSR) and the

Transmit buffer is empty.

18.4.3

RECEIVE INTERRUPT

The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register. The

interrupt flag is set by an edge generated by the

receiver. The condition for setting the receive interrupt

flag depends on the settings specified by the

URXISEL<1:0> (UxSTA<7:6>) control bits.

Switching between the two interrupt modes during

operation is possible and sometimes offers more

flexibility.

18.3.5

TRANSMIT BREAK

a) If URXISEL<1:0> = 00 or 01, an interrupt is

generated every time a data word is transferred

from the Receive Shift Register (UxRSR) to the

Receive Buffer. There may be one or more

characters in the receive buffer.

Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

b) If URXISEL<1:0> = 10, an interrupt is generated

when a word is transferred from the Receive

Shift Register (UxRSR) to the Receive Buffer,

which, as a result of the transfer, contains 3

characters.

To send a break character, the UTXBRK bit must be

set by software and must remain set for a minimum of

13 baud clock cycles. The UTXBRK bit is then cleared

by software to generate Stop bits. The user must wait

for a duration of at least one or two baud clock cycles

in order to ensure a valid Stop bit(s) before reloading

the UxTXB or starting other transmitter activity. Trans-

mission of a break character does not generate a

transmit interrupt.

c) If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift

Register (UxRSR) to the Receive Buffer, which,

as a result of the transfer, contains 4 characters

(i.e., becomes full).

Switching between the Interrupt modes during opera-

tion is possible, though generally not advisable during

normal operation.

18.4 Receiving Data

18.4.1

RECEIVING IN 8-BIT OR 9-BIT DATA

MODE

18.5 Reception Error Handling

The following steps must be performed while receiving

8-bit or 9-bit data:

18.5.1

RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

1. Set up the UART (see Section 18.3.1).

2. Enable the UART (see Section 18.3.1).

The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:

3. A receive interrupt will be generated when one

or more data words have been received,

depending on the receive interrupt settings

specified by the URXISEL bits (UxSTA<7:6>).

a) The receive buffer is full.

b) The receive shift register is full, but unable to

transfer the character to the receive buffer.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

c) The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

5. Read the received data from UxRXREG. The act

of reading UxRXREG will move the next word to

the top of the receive FIFO, and the PERR and

FERR values will be updated.

Once OERR is set, no further data is shifted in UxRSR

(until the OERR bit is cleared in software or a Reset

occurs). The data held in UxRSR and UxRXREG

remains valid.

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18.5.2

FRAMING ERROR (FERR)

18.6 Address Detect Mode

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read only FERR bit is buffered along with the received

data. It is cleared on any Reset.

Setting the ADDEN bit (UxSTA<5>) enables this spe-

cial mode, in which a 9th bit (URX8) value of ‘1’ identi-

fies the received word as an address rather than data.

This mode is only applicable for 9-bit data communica-

tion. The URXISEL control bit does not have any

impact on interrupt generation in this mode, since an

interrupt (if enabled) will be generated every time the

received word has the 9th bit set.

18.5.3

PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read only PERR bit is buffered along with the received

data bytes. It is cleared on any Reset.

18.7 Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the loopback mode, the UxRX

pin is disconnected from the internal UART receive

logic. However, the UxTX pin still functions as in a

normal operation.

18.5.4

IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the

completion of the Stop bit and detection of the next

Start bit, the RIDLE bit is ‘1’, indicating that the UART

is Idle.

To select this mode:

a) Configure UART for desired mode of operation.

b) Set LPBACK = 1to enable Loopback mode.

c) Enable transmission as defined in Section 18.3.

18.5.5

RECEIVE BREAK

The receiver will count and expect a certain number of

bit times based on the values programmed in the

PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)

bits.

18.8 Baud Rate Generator

The UART has a 16-bit baud rate generator to allow

maximum flexibility in baud rate generation. The baud

rate generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is

set, FERR is set, zeros are loaded into the receive

FIFO, interrupts are generated, if appropriate and the

RIDLE bit is set.

BRG = 16-bit value held in UxBRG register

(0 through 65535)

F^CY= Instruction Clock Rate (1/TCY)

The Baud Rate is given by Equation 18-1.

When the module receives a long break signal and the

receiver has detected the Start bit, the data bits and

the invalid Stop bit (which sets the FERR), the receiver

must wait for a valid Stop bit before looking for the next

Start bit. It cannot assume that the break condition on

the line is the next Start bit.

EQUATION 18-1: BAUD RATE

Baud Rate = F^CY/ (16*(BRG+1))

Therefore, maximum baud rate possible is

F^CY/16 (if BRG = 0),

Break is regarded as a character containing all 0’s,

with the FERR bit set. The break character is loaded

into the buffer. No further reception can occur until a

Stop bit is received. Note that RIDLE goes high when

the Stop bit has not been received yet.

and the minimum baud rate possible is

F^CY/ (16* 65536).

With a full 16-bit baud rate generator, at 30 MIPs

operation, the minimum baud rate achievable is

28.5 bps.

 2003 Microchip Technology Inc.

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18.10.2 UART OPERATION DURING CPU

IDLE MODE

18.9 Auto Baud Support

To allow the system to determine baud rates of

received characters, the input can be optionally linked

to a selected capture input. To enable this mode, the

user must program the input capture module to detect

the falling and rising edges of the Start bit.

For the UART, the USIDL bit selects if the module will

stop operation when the device enters Idle mode, or

whether the module will continue on Idle. If USIDL = 0,

the module will continue operation during Idle mode. If

USIDL = 1, the module will stop on Idle.

18.10 UART Operation During CPU

Sleep and Idle Modes

18.10.1 UART OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’. If

entry into Sleep mode occurs while a transmission is

in progress, then the transmission is aborted. The

UxTX pin is driven to logic ‘1’. Similarly, if entry into

Sleep mode occurs while a reception is in progress,

then the reception is aborted. The UxSTA, UxMODE,

transmit and receive registers and buffers, and the

UxBRG register are not affected by Sleep mode.

If the Wake bit (UxSTA<7>) is set before the device

enters Sleep mode, then a falling edge on the UxRX

pin will generate a receive interrupt. The Receive

Interrupt Select mode bit (URXISEL) has no effect for

this function. If the receive interrupt is enabled, then

this will wake-up the device from Sleep. The UARTEN

bit must be set in order to generate a wake-up

interrupt.

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NOTES:

DS70082C-page 128

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The CAN bus module consists of a protocol engine,

and message buffering/control. The CAN protocol

engine handles all functions for receiving and transmit-

ting messages on the CAN bus. Messages are trans-

mitted by first loading the appropriate data registers.

Status and errors can be checked by reading the

appropriate registers. Any message detected on the

CAN bus is checked for errors and then matched

against filters to see if it should be received and stored

in one of the receive registers.

19.0 CAN MODULE

19.1 Overview

The Controller Area Network (CAN) module is a serial

interface, useful for communicating with other CAN

modules or microcontroller devices. This interface/

protocol was designed to allow communications within

noisy environments.

The CAN module is a communication controller imple-

menting the CAN 2.0 A/B protocol, as defined in the

BOSCH specification. The module will support

CAN 1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B

Active versions of the protocol. The module implemen-

tation is a full CAN system. The CAN specification is

not covered within this data sheet. The reader may

refer to the BOSCH CAN specification for further

details.

19.2 Frame Types

The CAN module transmits various types of frames,

which include data messages or remote transmission

Requests initiated by the user as other frames that are

automatically generated for control purposes. The

following frame types are supported:

• Standard Data Frame

The module features are as follows:

A Standard Data Frame is generated by a node when

the node wishes to transmit data. It includes a 11-bit

Standard Identifier (SID) but not an 18-bit Extended

Identifier (EID).

• Implementation of the CAN protocol CAN 1.2,

CAN 2.0A and CAN 2.0B

• Standard and extended data frames

• 0-8 bytes data length

• Extended Data Frame

• Programmable bit rate up to 1 Mbit/sec

• Support for remote frames

An Extended Data Frame is similar to a Standard Data

Frame, but includes an Extended Identifier as well.

• Double buffered receiver with two prioritized

received message storage buffers (each buffer

may contain up to 8 bytes of data)

• Remote Frame

It is possible for a destination node to request the data

from the source. For this purpose, the destination node

sends a Remote Frame with an identifier that matches

the identifier of the required Data Frame. The appropri-

ate data source node will then send a Data Frame as a

response to this Remote request.

• 6 full (standard/extended identifier) acceptance

filters, 2 associated with the high priority receive

buffer, and 4 associated with the low priority

receive buffer

• 2 full acceptance filter masks, one each associ-

ated with the high and low priority receive buffers

• Error Frame

• Three transmit buffers with application specified

prioritization and abort capability (each buffer may

contain up to 8 bytes of data)

An Error Frame is generated by any node that detects

a bus error. An error frame consists of 2 fields: an Error

Flag field and an Error Delimiter field.

• Programmable wake-up functionality with

integrated low pass filter

• Overload Frame

An Overload Frame can be generated by a node as a

result of 2 conditions. First, the node detects a domi-

nant bit during lnterframe Space which is an illegal con-

dition. Second, due to internal conditions, the node is

not yet able to start reception of the next message. A

node may generate a maximum of 2 sequential

Overload Frames to delay the start of the next

message.

• Programmable Loopback mode supports self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to timer module for

time-stamping and network synchronization

• Low power Sleep and Idle mode

• Interframe Space

Interframe Space separates a proceeding frame (of

whatever type) from a following Data or Remote

Frame.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 129

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FIGURE 19-1:

CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Mask

RXM1

BUFFERS

Acceptance Filter

RXF2

A

c

e

p

t

Acceptance Mask

RXM0

Acceptance Filter

RXF3

TXB0

TXB1

TXB2

A

c

e

p

t

Acceptance Filter

RXF0

Acceptance Filter

RXF4

Acceptance Filter

RXF1

Acceptance Filter

RXF5

R

X

B

0

R

X

B

1

M

A

B

Identifier

Message

Queue

Control

Transmit Byte Sequencer

Data Field

Receive

RERRCNT

TERRCNT

Error

Counter

PROTOCOL

ENGINE

Transmit

Error

ErrPas

BusOff

Counter

Transmit Shift

Receive Shift

Protocol

Finite

CRC Check

CRC Generator

State

Machine

Bit

Timing

Logic

Transmit

Logic

Bit Timing

Generator

(1)

CiTX

CiRX

Note 1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2).

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The module can be programmed to apply a low-pass

filter function to the CiRX input line while the module or

the CPU is in Sleep mode. The WAKFIL bit

(CiCFG2<14>) enables or disables the filter.

19.3 Modes of Operation

The CAN Module can operate in one of several opera-

tion modes selected by the user. These modes include:

• Initialization Mode

• Disable Mode

Note:

Typically, if the CAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the CAN module has been

placed in that mode of operation, the mod-

ule waits for 11 consecutive recessive bits

on the bus before starting transmission. If

the user switches to Disable Mode within

this 11-bit period, then this transmission is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

• Normal Operation Mode

• Listen Only Mode

• Loop Back Mode

• Error Recognition Mode

Modes are requested by setting the REQOP<2:0> bits

(CiCTRL<10:8>), except the Error Recognition Mode

which is requested through the RXM<1:0> bits

(CiRXnCON<6:5>, where n = 0 or 1 represents a

particular receive buffer). Entry into a mode is acknowl-

edged by monitoring the OPMODE<2:0> bits

(CiCTRL<7:5>). The module will not change the mode

and the OPMODE bits until a change in mode is

acceptable, generally during bus idle time which is

defined as at least 11 consecutive recessive bits.

19.3.3

NORMAL OPERATION MODE

Normal operating mode is selected when

REQOP<2:0> = ‘000’. In this mode, the module is acti-

vated, the I/O pins will assume the CAN bus functions.

The module will transmit and receive CAN bus mes-

sages via the CxTX and CxRX pins.

19.3.1

INITIALIZATION MODE

In the Initialization mode, the module will not transmit or

receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to configuration registers that are access

restricted in other modes. The module will protect the

user from accidentally violating the CAN protocol

through programming errors. All registers which control

the configuration of the module can not be modified

while the module is on-line. The CAN module will not

be allowed to enter the configuration mode while a

transmission is taking place. The Configuration mode

serves as a lock to protect the following registers.

19.3.4

LISTEN ONLY MODE

If the listen only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to

the Port I/O function. The receive pins remain inputs.

For the receiver, no error flags or acknowledge signals

are sent. The error counters are deactivated in this

state. The listen only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is neces-

sary that there are at least two further nodes that com-

municate with each other.

19.3.5

ERROR RECOGNITION MODE

• All Module Control Registers

The module can be set to ignore all errors and receive

any message. The error recognition mode is activated

by setting the RXM<1:0> bits (CiRXnCON<6:5>) regis-

ters to ‘11’. In this mode the data which is in the mes-

sage assembly buffer until the time an error occurred,

is copied in the receive buffer and can be read via the

CPU interface.

• Baud Rate and interrupt Configuration Registers

• Bus Timing Registers

• Identifier Acceptance Filter Registers

• Identifier Acceptance Mask Registers

19.3.2

DISABLE MODE

In Disable Mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity, however any pending interrupts will

remain and the error counters will retain their value.

19.3.6

LOOP BACK MODE

If the loopback mode is activated, the module will con-

nect the internal transmit signal to the internal receive

signal at the module boundary. The transmit and

receive pins revert to their Port I/O function.

If the REQOP<2:0> bits (CiCTRL<10:8>) = ‘001’, the

module will enter the module disable mode. If the mod-

ule is active, the module will wait for 11 recessive bits

on the CAN bus, detect that condition as an idle bus,

then accept the module disable command. When the

OPMODE<2:0> bits (CiCTRL<7:5>) = ‘001’, that indi-

cates whether the module successfully went into mod-

ule disable mode. The I/O pins will revert to normal I/O

function when the module is in the module disable

mode.

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19.4.4

RECEIVE OVERRUN

19.4 Message Reception

An overrun condition occurs when the Message

Assembly Buffer (MAB) has assembled valid

19.4.1

RECEIVE BUFFERS

a

The CAN bus module has 3 receive buffers. However,

one of the receive buffers is always committed to mon-

itoring the bus for incoming messages. This buffer is

called the message assembly buffer (MAB). So there

are 2 receive buffers visible, RXB0 and RXB1, that can

received message, the message is accepted through

the acceptance filters, and when the receive buffer

associated with the filter has not been designated as

clear of the previous message.

The overrun error flag, RXnOVR (CiINTF<15> or

CiINTF<14>) and the ERRIF bit (CiINTF<5>) will be set

and the message in the MAB will be discarded.

essentially instantaneously receive

message from the protocol engine.

a

complete

All messages are assembled by the MAB, and are

transferred to the RXBn buffers only if the acceptance

filter criterion are met. When a message is received,

the RXnIF flag (CiINTF<0> or CiINRF<1>) will be set.

This bit can only be set by the module when a message

is received. The bit is cleared by the CPU when it has

completed processing the message in the buffer. If the

RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an inter-

rupt will be generated when a message is received.

If the DBEN bit is clear, RXB1 and RXB0 operate inde-

pendently. When this is the case, a message intended

for RXB0 will not be diverted into RXB1 if RXB0 con-

tains an unread message and the RX0OVR bit will be

set.

If the DBEN bit is set, the overrun for RXB0 is handled

differently. If a valid message is received for RXB0 and

RXFUL = 1indicates that RXB0 is full, and RXFUL = 0

indicates that RXB1 is empty, the message for RXB0

will be loaded into RXB1. An overrun error will not be

generated for RXB0. If a valid message is received for

RXB0 and RXFUL = 1, and RXFUL = 1indicating that

both RXB0 and RXB1 are full, the message will be lost

and an overrun will be indicated for RXB1.

RXF0 and RXF1 filters with RXM0 mask are associated

with RXB0. The filters RXF2, RXF3, RXF4, and RXF5

and the mask RXM1 are associated with RXB1.

19.4.2

MESSAGE ACCEPTANCE FILTERS

The message acceptance filters and masks are used to

determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

Message Assembly Buffer (MAB), the identifier fields of

the message are compared to the filter values. If there

is a match, that message will be loaded into the appro-

priate receive buffer.

19.4.5

RECEIVE ERRORS

The CAN module will detect the following receive

errors:

• Cyclic Redundancy Check (CRC) Error

• Bit Stuffing Error

• Invalid message receive error

The acceptance filter looks at incoming messages for

the RXIDE bit (CiRXnSID<0>) to determine how to

compare the identifiers. If the RXIDE bit is clear, the

message is a standard frame, and only filters with the

EXIDE bit (CiRXFnSID<0>) clear are compared. If the

RXIDE bit is set, the message is an extended frame,

and only filters with the EXIDE bit set are compared.

Configuring the RXM<1:0> bits to 01or 10can over-

ride the EXIDE bit.

These receive errors do not generate an interrupt.

However, the receive error counter is incremented by

one in case one of these errors occur. The RXWAR bit

(CiINTF<9>) indicates that the Receive Error Counter

has reached the CPU warning limit of 96 and an

interrupt is generated.

19.4.6

RECEIVE INTERRUPTS

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

19.4.3

MESSAGE ACCEPTANCE FILTER

MASKS

• Receive Interrupt

The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, then that bit

will automatically be accepted regardless of the filter

bit. There are 2 programmable acceptance filter masks

associated with the receive buffers, one for each buffer.

A message has been successfully received and loaded

into one of the receive buffers. This interrupt is acti-

vated immediately after receiving the End-of-Frame

(EOF) field. Reading the RXnIF flag will indicate which

receive buffer caused the interrupt.

• Wake-up interrupt

The CAN module has woken up from Disable Mode or

the device has woken up from Sleep mode.

• Receive Error Interrupts

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A receive error interrupt will be indicated by the ERRIF

bit. This bit shows that an error condition occurred. The

source of the error can be determined by checking the

bits in the CAN Interrupt Status Register CiINTF.

If the transmission completes successfully on the first

attempt, the TXREQ bit is cleared automatically and an

interrupt is generated if TXIE was set.

If the message transmission fails, one of the error con-

dition flags will be set and the TXREQ bit will remain set

indicating that the message is still pending for transmis-

sion. If the message encountered an error condition

during the transmission attempt, the TXERR bit will be

set and the error condition may cause an interrupt. If

the message loses arbitration during the transmission

attempt, the TXLARB bit is set. No interrupt is gener-

ated to signal the loss of arbitration.

• Invalid message received

• If any type of error occurred during reception of

the last message, an error will be indicated by the

IVRIF bit.

• Receiver overrun

• The RXnOVR bit indicates that an overrun condi-

tion occurred.

• Receiver warning

19.5.4

ABORTING MESSAGE

TRANSMISSION

• The RXWAR bit indicates that the Receive Error

Counter (RERRCNT<7:0>) has reached the

Warning limit of 96.

The system can also abort a message by clearing the

TXREQ bit associated with each message buffer. Set-

ting the ABAT bit (CiCTRL<12>) will request an abort of

all pending messages. If the message has not yet

started transmission, or if the message started but is

interrupted by loss of arbitration or an error, the abort

will be processed. The abort is indicated when the

module sets the TXABT bit, and the TXnIF flag is not

automatically set.

• Receiver error passive

• The RXEP bit indicates that the Receive Error

Counter has exceeded the Error Passive limit of

127 and the module has gone into Error Passive

state.

19.5 Message Transmission

19.5.1

TRANSMIT BUFFERS

19.5.5

TRANSMISSION ERRORS

The CAN module has three transmit buffers. Each of

the three buffers occupies 14 bytes of data. Eight of the

bytes are the maximum 8 bytes of the transmitted mes-

sage. Five bytes hold the standard and extended iden-

tifiers and other message arbitration information.

The CAN module will detect the following transmission

errors:

• Acknowledge Error

• Form Error

• Bit Error

19.5.2

TRANSMIT MESSAGE PRIORITY

These transmission errors will not necessarily generate

an interrupt but are indicated by the transmission error

counter. However, each of these errors will cause the

transmission error counter to be incremented by one.

Once the value of the error counter exceeds the value

of 96, the ERRIF (CiINTF<5>) and the TXWAR bit

(CiINTF<10>) are set. Once the value of the error

counter exceeds the value of 96, an interrupt is gener-

ated and the TXWAR bit in the error flag register is set.

Transmit priority is a prioritization within each node of the

pending transmittable messages. There are 4 levels of

transmit priority. If TXPRI<1:0> (CiTXnCON<1:0>, where

n = 0, 1 or 2 represents a particular transmit buffer) for a

particular message buffer is set to ‘11’, that buffer has the

highest priority. If TXPRI<1:0> for a particular message

buffer is set to ‘10’ or ‘01’, that buffer has an intermediate

priority. If TXPRI<1:0> for a particular message buffer is

‘00’, that buffer has the lowest priority.

19.5.6

TRANSMIT INTERRUPTS

19.5.3

TRANSMISSION SEQUENCE

Transmit interrupts can be divided into 2 major groups,

each including various conditions that generate inter-

rupts:

To initiate transmission of the message, the TXREQ bit

(CiTXnCON<3>) must be set. The CAN bus module

resolves any timing conflicts between setting of the

TXREQ bit and the Start of Frame (SOF), ensuring that

if the priority was changed, it is resolved correctly

before the SOF occurs. When TXREQ is set, the

TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>)

and TXERR (CiTXnCON<4>) flag bits are automati-

cally cleared.

• Transmit Interrupt

At least one of the three transmit buffers is empty (not

scheduled) and can be loaded to schedule a message

for transmission. Reading the TXnIF flags will indicate

which transmit buffer is available and caused the

interrupt.

Setting TXREQ bit simply flags a message buffer as

enqueued for transmission. When the module detects

an available bus, it begins transmitting the message

which has been determined to have the highest priority.

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• Transmit Error Interrupts

19.6.1

BIT TIMING

A transmission error interrupt will be indicated by the

ERRIF flag. This flag shows that an error condition

occurred. The source of the error can be determined by

checking the error flags in the CAN Interrupt Status reg-

ister, CiINTF. The flags in this register are related to

receive and transmit errors.

All controllers on the CAN bus must have the same

baud rate and bit length. However, different controllers

are not required to have the same master oscillator

clock. At different clock frequencies of the individual

controllers, the baud rate has to be adjusted by adjust-

ing the number of time quanta in each segment.

• Transmitter Warning Interrupt

The Nominal Bit Time can be thought of as being

divided into separate non-overlapping time segments.

These segments are shown in Figure 19-2.

• The TXWAR bit indicates that the Transmit Error

Counter has reached the CPU warning limit of 96.

• Transmitter Error Passive

•

Synchronization segment (Sync Seg)

Propagation time segment (Prop Seg)

Phase segment 1 (Phase1 Seg)

Phase segment 2 (Phase2 Seg)

• The TXEP bit (CiINTF<12>) indicates that the

Transmit Error Counter has exceeded the Error

Passive limit of 127 and the module has gone to

Error Passive state.

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

T^Q. By definition, the Nominal Bit Time has a minimum

of 8 T^Qand a maximum of 25 TQ. Also, by definition,

the minimum nominal bit time is 1 µsec, corresponding

to a maximum bit rate of 1 MHz.

• Bus Off

• The TXBO bit (CiINTF<13>) indicates that the

Transmit Error Counter has exceeded 255 and

the module has gone to Bus Off state.

19.6 Baud Rate Setting

All nodes on any particular CAN bus must have the

same nominal bit rate. In order to set the baud rate, the

following parameters have to be initialized:

• Synchronization Jump Width

• Baud rate prescaler

• Phase segments

• Length determination of Phase2 Seg

• Sample Point

• Propagation segment bits

FIGURE 19-2:

CAN BIT TIMING

Input Signal

Prop

Phase

Segment 1

Phase

Sync

Segment

Segment 2

Sample Point

TQ

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19.6.2

PRESCALER SETTING

19.6.6

SYNCHRONIZATION

There is a programmable prescaler, with integral val-

ues ranging from 1 to 64, in addition to a fixed divide-

by-2 for clock generation. The Time Quantum (T^Q) is a

fixed unit of time derived from the oscillator period, and

is given by Equation 19-1

To compensate for phase shifts between the oscillator

frequencies of the different bus stations, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time (Synchro-

nous Segment). The circuit will then adjust the values

of Phase1 Seg and Phase2 Seg. There are 2

mechanisms used to synchronize.

EQUATION 19-1: TIME QUANTUM FOR

CLOCK GENERATION

TQ = 2 ( BRP<5:0> + 1 ) / FCAN

19.6.6.1

Hard Synchronization

Hard Synchronization is only done whenever there is a

'recessive' to 'dominant' edge during Bus Idle, indicat-

ing the start of a message. After hard synchronization,

the bit time counters are restarted with the Synchro-

nous Segment. Hard synchronization forces the edge

which has caused the hard synchronization to lie within

the synchronization segment of the restarted bit time. If

a hard synchronization is done, there will not be a

re-synchronization within that bit time.

19.6.3

PROPAGATION SEGMENT

This part of the bit time is used to compensate physical

delay times within the network. These delay times con-

sist of the signal propagation time on the bus line and

the internal delay time of the nodes. The Propagation

Segment can be programmed from 1 T^Qto 8 TQ by

setting the PRSEG<2:0> bits (CiCFG2<2:0>).

19.6.4

PHASE SEGMENTS

19.6.6.2

Re-synchronization

The phase segments are used to optimally locate the

sampling of the received bit within the transmitted bit

time. The sampling point is between Phase1 Seg and

Phase2 Seg. These segments are lengthened or short-

ened by re-synchronization. The end of the Phase1

Seg determines the sampling point within a bit period.

The segment is programmable from 1 T^Qto 8 TQ.

Phase2 Seg provides delay to the next transmitted data

transition. The segment is programmable from 1 T^Qto

8 T^Q, or it may be defined to be equal to the greater of

Phase1 Seg or the Information Processing Time

(2 T^Q). The Phase1 Seg is initialized by setting bits

SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is ini-

tialized by setting SEG2PH<2:0> (CiCFG2<10:8>).

As a result of re-synchronization, Phase1 Seg may be

lengthened or Phase2 Seg may be shortened. The

amount of lengthening or shortening of the phase

buffer segment has an upper bound known as the Syn-

chronization Jump Width, and is specified by the

SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-

chronization jump width will be added to Phase1 Seg or

subtracted from Phase2 Seg. The re-synchronization

jump width is programmable between 1 T^Qand 4 TQ.

The following requirement must be fulfilled while setting

the SJW<1:0> bits:

• Phase2 Seg > Synchronization Jump Width

The following requirement must be fulfilled while setting

the lengths of the Phase Segments:

• Propagation Segment + Phase1 Seg > = Phase2

Seg

19.6.5

SAMPLE POINT

The Sample Point is the point of time at which the bus

level is read and interpreted as the value of that respec-

tive bit. The location is at the end of Phase1 Seg. If the

bit timing is slow and contains many T^Q, it is possible to

specify multiple sampling of the bus line at the sample

point. The level determined by the CAN bus then corre-

sponds to the result from the majority decision of three

values. The majority samples are taken at the sample

point and twice before with a distance of T^Q/2. The

CAN module allows the user to chose between sam-

pling three times at the same point or once at the same

point, by setting or clearing the SAM bit (CiCFG2<6>).

Typically, the sampling of the bit should take place at

about 60-70% through the bit time, depending on the

system parameters.

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NOTES:

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The A/D module has six 16-bit registers:

20.0 10-BIT HIGH SPEED ANALOG-

TO-DIGITAL CONVERTER (A/D)

MODULE

• A/D Control Register1 (ADCON1)

• A/D Control Register2 (ADCON2)

• A/D Control Register3 (ADCON3)

The10-bit high-speed analog-to-digital converter (A/D)

allows conversion of an analog input signal to a 10-bit

digital number. This module is based on a Successive

Approximation Register (SAR) architecture, and pro-

vides a maximum sampling rate of 500 ksps. The A/D

module has up to 16 analog inputs which are multi-

plexed into four sample and hold amplifiers. The output

of the sample and hold is the input into the converter,

which generates the result. The analog reference volt-

ages are software selectable to either the device sup-

ply voltage (AV^DD/AVSS) or the voltage level on the

(V^REF+/VREF-) pin. The A/D converter has a unique

feature of being able to operate while the device is in

Sleep mode.

• A/D Input Select Register (ADCHS)

• A/D Port Configuration Register (ADPCFG)

• A/D Input Scan Selection Register (ADCSSL)

The ADCON1, ADCON2 and ADCON3 registers con-

trol the operation of the A/D module. The ADCHS reg-

ister selects the input channels to be converted. The

ADPCFG register configures the port pins as analog

inputs or as digital I/O. The ADCSSL register selects

inputs for scanning.

Note:

The SSRC<2:0>, ASAM, SIMSAM,

SMPI<3:0>, BUFM and ALTS bits, as well

as the ADCON3 and ADCSSL registers,

must not be written to while ADON = 1.

This would lead to indeterminate results.

The block diagram of the A/D module is shown in

Figure 20-1.

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FIGURE 20-1:

10-BIT HIGH SPEED A/D FUNCTIONAL BLOCK DIAGRAM

AV^SS

AVDD

VREF+

VREF-

AN0

AN3

AN0

AN1

AN2

+

CH1

ADC

S/H

AN6

AN9

-

10-bit Result

Conversion Logic

AN1

AN4

+

CH2

S/H

AN7

-

AN10

16-word, 10-bit

Dual Port

Buffer

AN2

AN5

+

CH3

S/H

AN8

CH1,CH2,

CH3,CH0

-

AN11

Sample/Sequence

Control

sample

AN0

AN1

AN2

AN3

input

switches

Input Mux

Control

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN10

AN11

AN12

AN13

AN14

AN15

+

CH0

S/H

-

AN1

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The CHPS bits selects how many channels are sam-

pled. This can vary from 1, 2 or 4 channels. If CHPS

selects 1 channel, the CH0 channel will be sampled at

the sample clock and converted. The result is stored in

the buffer. If CHPS selects 2 channels, the CH0 and

CH1 channels will be sampled and converted. If CHPS

selects 4 channels, the CH0, CH1, CH2 and CH3

channels will be sampled and converted.

20.1 A/D Result Buffer

The module contains a 16-word dual port read-only

buffer, called ADCBUF0...ADCBUFF, to buffer the A/D

results. The RAM is 10-bits wide, but is read into different

format 16-bit words. The contents of the sixteen A/D

conversion result buffer registers, ADCBUF0 through

ADCBUFF, cannot be written by user software.

The SMPI bits select the number of acquisition/conver-

sion sequences that would be performed before an

interrupt occurs. This can vary from 1 sample per

interrupt to 16 samples per interrupt.

20.2 Conversion Operation

After the A/D module has been configured, the sample

acquisition is started by setting the SAMP bit. Various

sources, such as a programmable bit, timer time-outs and

external events, will terminate acquisition and start a con-

version. When the A/D conversion is complete, the result

is loaded into ADCBUF0...ADCBUFF, and the A/D

interrupt flag ADIF and the DONE bit are set after the

number of samples specified by the SMPI bit.

The user cannot program a combination of CHPS and

SMPI bits that specifies more than 16 conversions per

interrupt, or 8 conversions per interrupt, depending on

the BUFM bit. The BUFM bit, when set, will split the

16--word results buffer (ADCBUF0...ADCBUFF) into

two 8-word groups. Writing to the 8-word buffers will be

alternated on each interrupt event. Use of the BUFM bit

will depend on how much time is available for moving

data out of the buffers after the interrupt, as determined

by the application.

The following steps should be followed for doing an

A/D conversion:

1. Configure the A/D module:

- Configure analog pins, voltage reference and

digital I/O

If the processor can quickly unload a full buffer within

the time it takes to acquire and convert one channel,

the BUFM bit can be ‘0’ and up to 16 conversions may

be done per interrupt. The processor will have one

sample and conversion time to move the sixteen

conversions.

- Select A/D input channels

- Select A/D conversion clock

- Select A/D conversion trigger

- Turn on A/D module

2. Configure A/D interrupt (if required):

- Clear ADIF bit

If the processor cannot unload the buffer within the

acquisition and conversion time, the BUFM bit should

be ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) =

0111, then eight conversions will be loaded into 1/2 of

the buffer, following which an interrupt occurs. The next

eight conversions will be loaded into the other 1/2 of the

buffer. The processor will have the entire time between

interrupts to move the eight conversions.

- Select A/D interrupt priority

3. Start sampling.

4. Wait the required acquisition time.

5. Trigger acquisition end, start conversion

6. Wait for A/D conversion to complete, by either:

- Waiting for the A/D interrupt

The ALTS bit can be used to alternate the inputs

selected during the sampling sequence. The input mul-

tiplexer has two sets of sample inputs: MUX A and

MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are

selected for sampling. If the ALTS bit is ‘1’ and

SMPI<3:0> = 0000, on the first sample/convert

sequence, the MUX A inputs are selected, and on the

next acquire/convert sequence, the MUX B inputs are

selected.

7. Read A/D result buffer, clear ADIF if required.

20.3 Selecting the Conversion

Sequence

Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold

channels, converts channels, writes the buffer memory,

and generates interrupts. The sequence is controlled

by the sampling clocks.

The CSCNA bit (ADCON2<10>) will allow the CH0

channel inputs to be alternately scanned across a

selected number of analog inputs for the MUX A group.

The inputs are selected by the ADCSSL register. If a

particular bit in the ADCSSL register is ‘1’, the corre-

sponding input is selected. The inputs are always

scanned from lower to higher numbered inputs, starting

after each interrupt. If the number of inputs selected is

greater than the number of samples taken per interrupt,

the higher numbered inputs are unused.

The SIMSAM bit controls the acquire/convert

sequence for multiple channels. If the SIMSAM bit is

‘0’, the two or four selected channels are acquired and

converted sequentially, with two or four sample clocks.

If the SIMSAM bit is ‘1’, two or four selected channels

are acquired simultaneously, with one sample clock.

The channels are then converted sequentially. Obvi-

ously, if there is only 1 channel selected, the SIMSAM

bit is not applicable.

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If the clearing of the ADON bit coincides with an auto

start, the clearing has a higher priority.

20.4 Programming the Start of

Conversion Trigger

After the A/D conversion is aborted, a 2 T^ADwait is

required before the next sampling may be started by

setting the SAMP bit.

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the

conversion trigger.

If sequential sampling is specified, the A/D will continue

at the next sample pulse which corresponds with the

next channel converted. If simultaneous sampling is

specified, the A/D will continue with the next

multi-channel group conversion sequence.

The SSRC bits provide for up to 5 alternate sources of

conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the conversion trigger.

20.6 Selecting the A/D Conversion

Clock

When SSRC<2:0> = 111 (Auto Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acquisition and the start of conversion. This provides

the fastest conversion rates on multiple channels.

SAMC must always be at least 1 clock cycle.

The A/D conversion requires 13 TAD. The source of the

A/D conversion clock is software selected using a six

bit counter. There are 64 possible options for T^AD.

EQUATION 20-1: A/D CONVERSION CLOCK

Other trigger sources can come from timer modules,

Motor Control PWM module, or external interrupts.

TAD = TCY * (0.5*(ADCS<5:0> +1))

20.5 Aborting a Conversion

The internal RC oscillator is selected by setting the

ADRC bit.

Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling sequenc-

ing. The ADCBUF will not be updated with the partially

completed A/D conversion sample. That is, the

ADCBUF will continue to contain the value of the last

completed conversion (or the last value written to the

ADCBUF register).

For correct A/D conversions, the A/D conversion clock

(T^AD) must be selected to ensure a minimum TAD time

of 154 nsec. Table 20-1 shows the resultant T^ADtimes

derived from the device operating frequencies and the

A/D clock source selected, (for V^DD= 5V).

TABLE 20-1: TYPICAL TAD VS. DEVICE OPERATING FREQUENCIES

A/D Clock Period (TAD Values)

A/D Clock Source Select

A/D

ADRC ADCS<5:0>

Device FCY

30 MHz

25 MHz

12.5 MHz

6.25 MHz

1 MHz

Clock

(2)

T^CY/2

T^CY

0

000000

000001

000011

000111

001111

011111

111111

16.67 ns

33.33 ns

66.66 ns

20 ns

40 ns

80 ns

500 ns

(2)

40 ns

(2)

80 ns

160 ns

320 ns

1.0 µs

(2)

80 ns

(3)

2 T^CY

4 TCY

8 TCY

16 TCY

32 TCY

160 ns

320 ns

2.0 µs

4.0 µs

8.0 µs

(2)

(3)

133.32 ns

160 ns

320 ns

640 ns

(3)

266.64 ns

640 ns

1.28 µs

(3)

533.28 ns

640 ns

1.28 µs

2.56 µs

16.0 µs

32.0 µs

(3)

1066.56 ns

1280 ns

2.56 µs

5.12 µs

(1,4)

200-400 ns

(1,4)

200-400 ns

(1,4)

200-400 ns

(1,4)

200-400 ns

(1)

RC

1

xxxxxx

200-400 ns

Note 1: The RC source has a typical T^ADtime of 300 ns for VDD > 3.0V.

2: These values violate the minimum required TAD time of 154 ns.

3: For faster conversion times, the selection of another clock source is recommended.

4: A/D cannot meet full accuracy with RC clock source and F^OSC> 20 MHz.

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EQUATION 20-2: A/D SAMPLING TIME

EQUATIONS

20.7 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (C^HOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 20-2. The

source impedance (R^S) and the internal sampling

switch (R^SS) impedance directly affect the time

required to charge the capacitor C^HOLD. The sampling

switch (R^SS) impedance varies over the device voltage

(V^DD), see Figure 20-2. The impedance for analog

sources must be small enough to meet accuracy

requirements at the given speed. After the analog input

channel is selected (changed), this sampling must be

done before the conversion can acquisition sampling

time, Equation 20-2 may be used. This equation

assumes that the input is stepped some multiple (n) of

the LSB step size and the output must be captured to

within 1/2 LSb error (2096 steps for 10-bit A/D).

(-T^C/CHOLD (RIC+RSS+RS))

∆VO

=

∆VI • (1 – e

)

(-T^C/CHOLD (RIC+RSS+RS))

1 – (∆V^O/ ∆VI)

∆V^I

e

VIN – VREF-

∆V^O

n • LSB – 1/2 LSB

(n • LSB – 1/2 LSB) / n • LSB

1 / 2n

∆V^O/ ∆VI

1 – (∆V^O/ ∆VI)

1 / 2n

(-T^C/CHOLD (RIC+RSS+RS))

e

TC

CHOLD • (RIC+RSS+RS) • -In(1/2 • n)

TSMP

Amplifier Settling Time

+ Holding Capacitor Charging Time (T^C)

+ Temperature Coefficient

† The temperature coefficient is only required for

temperatures > 25°C.

†

TSMP

= 0.5 µs

+ C^HOLD• (RIC+RSS+RS) • -In(1/2 • n)

+ [(Temp – 25°C)(0.05 µs/°C)]

The C^HOLDis 4.4 pF for the A/D converter.

FIGURE 20-2:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

R^IC≤ 250Ω

R^SS

Rs

CHOLD

CPIN

= DAC capacitance

= 4.4 pF

VA

I leakage

500 nA

V^T= 0.6V

5 pF

V^SS

Sampling

3.5

3.0

Legend: CPIN

= input capacitance

= threshold voltage

I leakage = leakage current at the pin due to

various junctions

Switch

(Rss kΩ)

VT

2.5

2.0

1.5

R^IC

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

1.0

0.5

0

SS

C^HOLD

2

3

4

5

6

VDD (V)

Note: Values shown here are untested typical values, for reference only. Exact electrical specifications are to be determined.

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If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the A/D

module will then be turned off, although the ADON bit

will remain set.

20.8 Module Power-down Modes

The module has 3 internal power modes. When the

ADON bit is ‘1’, the module is in Active mode; it is fully

powered and functional. When ADON is ‘0’, the module

is in Off mode. The digital and analog portions of the

circuit are disabled for maximum current savings. In

order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

20.9.2

A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will con-

tinue operation on assertion of Idle mode. If ADSIDL =

1, the module will stop on Idle.

20.9 A/D Operation During CPU Sleep

and Idle Modes

20.10 Effects of a Reset

20.9.1

A/D OPERATION DURING CPU

SLEEP MODE

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off, and any

conversion and acquisition sequence is aborted. The

values that are in the ADCBUF registers are not modi-

fied. The A/D result register will contain unknown data

after a Power-on Reset.

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the con-

version is aborted. The converter will not continue with

a partially completed conversion on exit from Sleep

mode.

20.11 Output Formats

Register contents are not affected by the device

entering or leaving Sleep mode.

The A/D result is 10-bits wide. The data buffer RAM is

also 10-bits wide. The 10-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

The A/D module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the

RC clock source is selected, the A/D module waits one

instruction cycle before starting the conversion. This

allows the SLEEP instruction to be executed, which

eliminates all digital switching noise from the conver-

sion. When the conversion is complete, the CONV bit

will be cleared and the result loaded into the ADCBUF

register.

Write data will always be in right justified (integer)

format.

FIGURE 20-3:

A/D OUTPUT DATA FORMATS

RAM Contents:

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional (1.15)

Fractional (1.15)

Signed Integer

Integer

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0

d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

DS70082C-page 146

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dsPIC30F

20.12 Configuring Analog Port Pins

20.13 Connection Considerations

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (V^OHor VOL) will be

converted.

The analog inputs have diodes to VDD and VSS as ESD

protection. This requires that the analog input be

between V^DDand VSS. If the input voltage exceeds this

range by greater than 0.3V (either direction), one of the

diodes becomes forward biased and it may damage the

device if the input current specification is exceeded.

The A/D operation is independent of the state of the

CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.

An external RC filter is sometimes added for anti-

aliasing of the input signal. The R component should be

selected to ensure that the sampling time requirements

are satisfied. Any external components connected (via

high impedance) to an analog input pin (capacitor,

zener diode, etc.) should have very little leakage

current at the pin.

When reading the PORT register, all pins configured as

analog input channels will read as cleared.

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins), may cause the

input buffer to consume current that exceeds the

device specifications.

 2003 Microchip Technology Inc.

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dsPIC30F

DS70082C-page 148

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 2003 Microchip Technology Inc.

dsPIC30F

Sleep mode is designed to offer a very low current

Power-down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up or

through an interrupt. Several oscillator options are also

made available to allow the part to fit a wide variety of

applications. In the Idle mode, the clock sources are

still active, but the CPU is shut-off. The RC oscillator

option saves system cost, while the LP crystal option

saves power.

21.0 SYSTEM INTEGRATION

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide Power Saving Operating

modes and offer code protection:

• Oscillator Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Programmable Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• Power Saving modes (Sleep and Idle)

• Code Protection

21.1 Oscillator System Overview

The dsPIC30F oscillator system has the following

modules and features:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to boost internal operating

frequency

• Unit ID Locations

• In-Circuit Serial Programming (ICSP)

• A clock switching mechanism between various

clock sources

dsPIC30F devices have a Watchdog Timer, which is

permanently enabled via the configuration bits, or can

be software controlled. It runs off its own RC oscillator

for added reliability. There are two timers that offer nec-

essary delays on power-up. One is the Oscillator Start-

up Timer (OST), intended to keep the chip in Reset until

the crystal oscillator is stable. The other is the Power-

up Timer (PWRT), which provides a delay on power-up

only, designed to keep the part in Reset while the

power supply stabilizes. With these two timers on-chip,

most applications need no external Reset circuitry.

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• Clock Control Register OSCCON

• Configuration bits for main oscillator selection

Table 21-1 provides a summary of the dsPIC30F

Oscillator Operating modes. A simplified diagram of the

oscillator system is shown in Figure 21-1.

TABLE 21-1: OSCILLATOR OPERATING MODES

Oscillator Mode

Description

XTL

200 kHz-4 MHz crystal on OSC1:OSC2.

4 MHz-10 MHz crystal on OSC1:OSC2.

XT

XT w/ PLL 4x

XT w/ PLL 8x

XT w/ PLL 16x

LP

4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled.

4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled.

(1)

4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled

.

(2)

32 kHz crystal on SOSCO:SOSCI

10 MHz-25 MHz crystal.

.

HS

EC

External clock input (0-40 MHz).

ECIO

External clock input (0-40 MHz). OSC2 pin is I/O.

(1)

EC w/ PLL 4x

EC w/ PLL 8x

EC w/ PLL 16x

ERC

External clock input (0-40 MHz). OSC2 pin is I/O. 4x PLL enabled

External clock input (0-40 MHz). OSC2 pin is I/O. 8x PLL enabled

.

(1)

External clock input (0-40 MHz). OSC2 pin is I/O. 16x PLL enabled

.

(3)

External RC oscillator. OSC2 pin is F^OSC/4 output

.

(3)

ERCIO

External RC oscillator. OSC2 pin is I/O

8 MHz internal RC Oscillator.

.

FRC

LPRC

512 kHz internal RC Oscillator.

Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.

2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.

3: Requires external R and C. Frequency operation up to 4 MHz.

 2003 Microchip Technology Inc.

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dsPIC30F

Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).

Thereafter, the clock source can be changed between

permissible clock sources. The OSCCON register con-

trols the clock switching and reflects system clock

related status bits.

FIGURE 21-1:

OSCILLATOR SYSTEM BLOCK DIAGRAM

Oscillator Configuration bits

PWRSAVInstruction

Wake-up Request

F^PLL

OSC1

OSC2

PLL

Primary

Oscillator

PLL

x4, x8, x16

Lock

COSC<1:0>

Primary Osc

NOSC<1:0>

OSWEN

Primary

Oscillator

Stability Detector

Oscillator

Start-up

Timer

POR Done

Clock

Switching

and Control

Programmable

Clock Divider

Secondary Osc

System

Clock

Block

SOSCO

SOSCI

Secondary

Oscillator

32 kHz LP

Oscillator

2

Stability Detector

POST<1:0>

FRC

Internal Fast RC

Oscillator (FRC)

Internal Low

Power RC

LPRC

Oscillator (LPRC)

CF

Fail-Safe Clock

Monitor (FSCM)

FCKSM<1:0>

2

Oscillator Trap

to Timer1

DS70082C-page 150

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dsPIC30F

21.2 Oscillator Configurations

21.2.1

INITIAL CLOCK SOURCE

SELECTION

While coming out of Power-on Reset or Brown-out

Reset, the device selects its clock source based on:

a) FOS<1:0> configuration bits that select one of

four oscillator groups.

b) AND FPR<3:0> configuration bits that select

one of 13 oscillator choices within the primary

group.

The selection is as shown in Table 21-2.

TABLE 21-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator

OSC2

FPR0

Function

Oscillator Mode

FOS1

FOS0

FPR3

FPR2

FPR1

Source

Primary

EC

1

0

1

0

1

0

1

0

1

0

1

0

CLKO

I/O

ECIO

Primary

Secondary

Internal FRC

EC w/ PLL 4x

EC w/ PLL 8x

EC w/ PLL 16x

ERC

1

0

1

I/O

1

0

I/O

1

I/O

1

0

1

CLKO

I/O

ERCIO

1

0

XT

0

1

0

OSC2

(Notes 1, 2)

XT w/ PLL 4x

XT w/ PLL 8x

XT w/ PLL 16x

XTL

0

1

0

1

0

1

0

1

0

X

HS

0

1

X

LP

—

FRC

LPRC

Internal

LPRC

Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>).

2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock

source is selected at all times.

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21.2.2

OSCILLATOR START-UP TIMER

(OST)

21.2.5

FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (8 MHz nominal) internal

RC oscillator. This oscillator is intended to provide rea-

sonable device operating speeds without the use of an

external crystal, ceramic resonator, or RC network.

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an oscillator

start-up timer is included. It is a simple 10-bit counter

that counts 1024 T^OSCcycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as T^OST. The TOST time is involved

every time the oscillator has to restart (i.e., on POR,

BOR and wake-up from Sleep). The oscillator start-up

timer is applied to the LP Oscillator, XT, XTL, and HS

modes (upon wake-up from Sleep, POR and BOR) for

the primary oscillator.

The dsPIC30F operates from the FRC oscillator when-

ever the Current Oscillator Selection Control bits in the

OSCCON register (OSCCON<13:12>) are set to ‘01’.

21.2.6

LOW POWER RC OSCILLATOR

(LPRC)

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT and clock

monitor circuits. It may also be used to provide a low

frequency clock source option for applications where

power consumption is critical, and timing accuracy is

not required.

21.2.3

LP OSCILLATOR CONTROL

Enabling the LP oscillator is controlled with two

elements:

1. The current oscillator group bits COSC<1:0>.

2. The LPOSCEN bit (OSCON register).

The LPRC oscillator is always enabled at a Power-on

Reset, because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will remain

ON if one of the following is TRUE:

The LP oscillator is ON (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

•

COSC<1:0> = 00(LP selected as main oscillator)

and

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

•

LPOSCEN = 1

Keeping the LP oscillator ON at all times allows for a

fast switch to the 32 kHz system clock for lower power

operation. Returning to the faster main oscillator will

still require a start-up time

• The LPRC oscillator is selected as the system

clock via the COSC<1:0> control bits in the

OSCCON register

If one of the above conditions is not true, the LPRC will

shut-off after the PWRT expires.

21.2.4

PHASE LOCKED LOOP (PLL)

The PLL multiplies the clock which is generated by the

primary oscillator. The PLL is selectable to have either

gains of x4, x8, and x16. Input and output frequency

ranges are summarized in Table 21-3.

Note 1: OSC2 pin function is determined by the

Primary Oscillator mode selection

(FPR<3:0>).

2: Note that OSC1 pin cannot be used as an

I/O pin, even if the secondary oscillator or

an internal clock source is selected at all

times.

TABLE 21-3: PLL FREQUENCY RANGE

PLL

Fin

Fout

Multiplier

4 MHz-10 MHz

4 MHz-7.5 MHz

x4

x8

16 MHz-40 MHz

32 MHz-80 MHz

64 MHz-160 MHz

x16

The PLL features a lock output, which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read only LOCK bit in the OSCCON register.

DS70082C-page 152

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dsPIC30F

The OSCCON register holds the CONTROL and STA-

TUS bits related to clock switching.

21.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM configuration bits (Clock

Switch and Monitor Selection bits) in the F^OSCdevice

configuration register. If the FSCM function is enabled,

the LPRC Internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control

by the SWDTEN bit.

• COSC<1:0>: Read only status bits always reflect

the current oscillator group in effect.

• NOSC<1:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<1:0> and

NOSC<1:0> are both loaded with the

Configuration bit values FOS<1:0>.

• LOCK: The LOCK status bit indicates a PLL lock.

In the event of an oscillator failure, the FSCM will gen-

erate a Clock Failure Trap event and will switch the sys-

tem clock over to the FRC oscillator. The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the Trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) status bit (OSCCON<3>) is

also set whenever a clock failure is recognized.

• CF: Read only status bit indicating if a clock fail

detect has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If configuration bits FCKSM<1:0> = 1x, then the clock

switching and fail-safe clock monitor functions are dis-

abled. This is the default configuration bit setting.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If clock switching is disabled, then the FOS<1:0> and

FPR<3:0> bits directly control the oscillator selection

and the COSC<1:0> bits do not control the clock

selection. However, these bits will reflect the clock

source selection.

If the oscillator has a very slow start-up time coming

out of POR, BOR or Sleep, it is possible that the

PWRT timer will expire before the oscillator has

started. In such cases, the FSCM will be activated and

the FSCM will initiate a Clock Failure Trap, and the

COSC<1:0> bits are loaded with FRC oscillator selec-

tion. This will effectively shut-off the original oscillator

that was trying to start.

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 KHz when the fail-safe clock monitor is

enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast RC

oscillator.

The user may detect this situation and restart the

oscillator in the Clock Fail Trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC Oscillator as follows:

1. The COSC bits (OSCCON<13:12>) are loaded

with the FRC Oscillator selection value.

21.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

2. CF bit is set (OSCCON<3>).

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

3. OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

1. Primary

2. Secondary

3. Internal FRC

4. Internal LPRC

• ByteWrite“0x46” to OSCCON low

• Byte Write “0x57” to OSCCON low

Byte Write is allowed for one instruction cycle. Write the

The user can switch between these functional groups,

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group is always determined by the FPR<3:0>

configuration bits.

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

• Byte Write“0x78” to OSCCON high

• Byte Write“0x9A” to OSCCON high

Byte Write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

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dsPIC30F

Different registers are affected in different ways by var-

ious Reset conditions. Most registers are not affected

by a WDT wake-up, since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

register are set or cleared differently in different Reset

situations, as indicated in Table 21-4. These bits are

used in software to determine the nature of the Reset.

21.3 Reset

The dsPIC30F differentiates between various kinds of

Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

A block diagram of the on-chip Reset circuit is shown in

Figure 21-2.

d) Watchdog Timer (WDT) Reset (during normal

operation)

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

Internally generated RESETS do not drive MCLR pin

low.

g) Reset cause by trap lockup (TRAPR)

h) Reset caused by illegal opcode, or by using an

uninitialized W register as an address pointer

(IOPUWR)

FIGURE 21-2:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Digital

Glitch Filter

MCLR

Sleep or Idle

WDT

Module

POR

VDD Rise

S

Detect

VDD

Brown-out

Reset

BOR

BOREN

Q

R

SYSRST

TRAP Conflict

Illegal Opcode/

Uninitialized W Register

The POR circuit inserts a small delay, T^POR, which is

nominally 10 µs and ensures that the device bias cir-

cuits are stable. Furthermore, a user selected power-

up time-out (T^PWRT) is applied. The TPWRT parameter

is based on device configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms or 64 ms. The total delay is at

device power-up T^POR+ TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock, and the PC will jump to

the Reset vector.

21.3.1

POR: POWER-ON RESET

A power-on event will generate an internal POR pulse

when a V^DDrise is detected. The Reset pulse will occur

at the POR circuit threshold voltage (V^POR), which is

nominally 1.85V. The device supply voltage character-

istics must meet specified starting voltage and rise rate

requirements. The POR pulse will reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the oscil-

lator configuration fuses.

The timing for the SYSRST signal is shown in

Figure 21-3 through Figure 21-5.

DS70082C-page 154

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dsPIC30F

FIGURE 21-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

Vaa

j`io

INTERNAL POR

Tlpq

lpq=qfjbJlrq

Tmtoq

mtoq=qfjbJlrq

fkqbok^i=oÉëÉí

FIGURE 21-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TOST

OST TIME-OUT

TPWRT

PWRT TIME-OUT

INTERNAL Reset

FIGURE 21-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TOST

OST TIME-OUT

TPWRT

PWRT TIME-OUT

INTERNAL Reset

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A BOR will generate a Reset pulse which will reset the

device. The BOR will select the clock source, based on

the device configuration bit values (FOS<1:0> and

FPR<3:0>). Furthermore, if an Oscillator mode is

selected, the BOR will activate the Oscillator Start-up

Timer (OST). The system clock is held until OST

expires. If the PLL is used, then the clock will be held

until the LOCK bit (OSCCON<5>) is “1”.

21.3.1.1

POR with Long Crystal Start-up Time

(with FSCM Enabled)

The oscillator start-up circuitry is not linked to the POR

circuitry. Some crystal circuits (especially low fre-

quency crystals) will have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the POR timer and the PWRT have

expired:

Concurrently, the POR time-out (T^POR) and the PWRT

time-out (T^PWRT) will be applied before the internal

Reset is released. If T^PWRT= 0and a crystal oscillator

is being used, then a nominal delay of T^FSCM= 100 µs

is applied. The total delay in this case is (T^POR+

T^FSCM).

• The oscillator circuit has not begun to oscillate.

• The oscillator start-up timer has NOT expired (if a

crystal oscillator is used).

• The PLL has not achieved a LOCK (if PLL is

used).

If the FSCM is enabled and one of the above conditions

is true, then a Clock Failure Trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap ISR.

The BOR status bit (RCON<1>) will be set to indicate

that a BOR has occurred. The BOR circuit, if enabled,

will continue to operate while in Sleep or Idle modes

and will reset the device should V^DDfall below the BOR

threshold voltage.

21.3.1.2

Operating without FSCM and PWRT

FIGURE 21-6:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW V^DDPOWER-UP)

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rap-

idly from Reset on power-up. If the clock source is

FRC, LPRC, EXTRC or EC, it will be active

immediately.

V^DD

D

R

If the FSCM is disabled and the system clock has not

started, the device will be in a frozen state at the Reset

vector until the system clock starts. From the user’s

perspective, the device will appear to be in Reset until

a system clock is available.

R1

MCLR

dsPIC30F

C

Note 1: External Power-on Reset circuit is

required only if the V^DDpower-up slope

is too slow. The diode D helps discharge

the capacitor quickly when V^DDpowers

down.

21.3.2

BOR: PROGRAMMABLE

BROWN-OUT RESET

The BOR (Brown-out Reset) module is based on an

internal voltage reference circuit. The main purpose of

the BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (i.e.,

missing portions of the AC cycle waveform due to bad

power transmission lines or voltage sags due to exces-

sive current draw when a large inductive load is turned

on).

2: R should be suitably chosen so as to

make sure that the voltage drop across

R does not violate the device’s electrical

specification.

3: R1 should be suitably chosen so as to

limit any current flowing into MCLR from

external capacitor C, in the event of

MCLR/VPP pin breakdown due to Elec-

trostatic Discharge (ESD) or Electrical

Overstress (EOS).

The BOR module allows selection of one of the follow-

ing voltage trip points:

• 2.0V

• 2.7V

• 4.2V

• 4.5V

Note:

Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset cir-

cuit.

Note:

The BOR voltage trip points indicated here

are nominal values provided for design

guidance only.

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Table 21-4 shows the Reset conditions for the RCON

Register. Since the control bits within the RCON regis-

ter are R/W, the information in the table implies that all

the bits are negated prior to the action specified in the

condition column.

TABLE 21-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1

Program

Condition

Power-on Reset

TRAPR IOPUWR EXTR SWR WDTO Idle

Sleep POR BOR

Counter

0x000000

0

1

0

1

0

1

0

Brown-out Reset

MCLR Reset during normal

operation

Software Reset during

normal operation

0x000000

0

1

0

MCLR Reset during Sleep

MCLR Reset during Idle

WDT Time-out Reset

WDT Wake-up

0x000000

PC + 2

0

1

0

1

0

1

0

1

0

1

0

(1)

Interrupt Wake-up from

Sleep

PC + 2

Clock Failure Trap

Trap Reset

0x000004

0x000000

0

1

0

1

0

Illegal Operation Trap

Legend:

u= unchanged, x= unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

Table 21-5 shows a second example of the bit

conditions for the RCON Register. In this case, it is not

assumed the user has set/cleared specific bits prior to

action specified in the condition column.

TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2

Program

Condition

Power-on Reset

TRAPR IOPUWR EXTR SWR WDTO Idle

Sleep POR BOR

Counter

0x000000

0

u

0

u

0

u

1

0

u

0

u

0

u

0

u

0

1

0

u

1

u

Brown-out Reset

MCLR Reset during normal

operation

Software Reset during

normal operation

0x000000

u

0

1

0

u

MCLR Reset during Sleep

MCLR Reset during Idle

WDT Time-out Reset

WDT Wake-up

0x000000

PC + 2

u

1

0

u

0

u

0

1

u

0

1

0

u

1

0

1

u

(1)

PC + 2

Interrupt Wake-up from

Sleep

Clock Failure Trap

Trap Reset

0x000004

0x000000

u

1

u

1

u

Illegal Operation Reset

Legend:

u= unchanged, x= unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 157

dsPIC30F

21.4

Watchdog Timer (WDT)

21.6 Power Saving Modes

There are two power saving states that can be entered

21.4.1

WATCHDOG TIMER OPERATION

through the execution of a special instruction, PWRSAV.

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software mal-

function. The WDT is a free running timer, which runs

off an on-chip RC oscillator, requiring no external com-

ponent. Therefore, the WDT timer will continue to oper-

ate even if the main processor clock (e.g., the crystal

oscillator) fails.

These are: Sleep and Idle.

The format of the PWRSAVinstruction is as follows:

PWRSAV <parameter>, where ‘parameter’ defines

Idle or Sleep mode.

21.6.1

SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is

shutdown. If an on-chip oscillator is being used, it is

shutdown.

21.4.2

ENABLING AND DISABLING THE

WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a configuration bit (FWDTEN) in the

configuration register FWDT.

The fail-safe clock monitor is not functional during

Sleep, since there is no clock to monitor. However,

LPRC clock remains active if WDT is operational during

Sleep.

Setting FWDTEN = 1 enables the Watchdog Timer.

The enabling is done when programming the device.

By default, after chip-erase, FWDTEN bit = 1. Any

device programmer capable of programming

dsPIC30F devices allows programming of this and

other configuration bits.

The Brown-out protection circuit and the Low Voltage

Detect circuit, if enabled, will remain functional during

Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

If enabled, the WDT will increment until it overflows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR, BOR and MCLR)

• WDT time-out

If a WDT times out during Sleep, the device will wake-

up. The WDTO bit in the RCON register will be cleared

to indicate a wake-up resulting from a WDT time-out.

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry

into Sleep mode. When clock switching is enabled,

bits COSC<1:0> will determine the oscillator source

that will be used on wake-up. If clock switch is

disabled, then there is only one system clock.

Setting FWDTEN = 0allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

Note:

If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<1:0>

and FPR<3:0> configuration bits.

21.5 Low Voltage Detect

The Low Voltage Detect (LVD) module is used to detect

when the V^DDof the device drops below a threshold

value V^LVD, which is determined by the LVDL<3:0> bits

(RCON<11:8>) and is thus user-programmable. The

internal voltage reference circuitry requires a nominal

amount of time to stabilize, and the BGST bit

(RCON<13>) indicates when the voltage reference has

stabilized.

If the clock source is an oscillator, the clock to the

device will be held off until OST times out (indicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1(indicating that the PLL is sta-

ble). In either case, T^POR, TLOCK and TPWRT delays are

applied.

If EC, FRC, LPRC or EXTRC oscillators are used, then

a delay of T^POR(~ 10 µs) is applied. This is the smallest

delay possible on wake-up from Sleep.

In some devices, the LVD threshold voltage may be

applied externally on the LVDIN pin.

The LVD module is enabled by setting the LVDEN bit

(RCON<12>).

Moreover, if LP oscillator was active during Sleep, and

LP is the oscillator used on wake-up, then the start-up

delay will be equal to T^POR. PWRT delay and OST

timer delay are not applied. In order to have the small-

est possible start-up delay when waking up from Sleep,

one of these faster wake-up options should be selected

before entering Sleep.

DS70082C-page 158

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 2003 Microchip Technology Inc.

dsPIC30F

Any interrupt that is individually enabled (using the cor-

responding IE bit) and meets the prevailing priority

level will be able to wake-up the processor. The proces-

sor will process the interrupt and branch to the ISR.

The Sleep status bit in RCON register is set upon

wake-up.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-up the processor. The processor will process the

interrupt and branch to the ISR. The Idle status bit in

RCON register is set upon wake-up.

Any Reset, other than POR, will set the Idle status bit.

On a POR, the Idle bit is cleared.

Note:

In spite of various delays applied (TPOR,

T^LOCKand TPWRT), the crystal oscillator

(and PLL) may not be active at the end of

the time-out (e.g., for low frequency crys-

tals. In such cases), if FSCM is enabled,

then the device will detect this as a clock

failure and process the Clock Failure Trap,

the FRC oscillator will be enabled, and the

user will have to re-enable the crystal

oscillator. If FSCM is not enabled, then the

device will simply suspend execution of

code until the clock is stable, and will

remain in Sleep until the oscillator clock

has started.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

21.7 Device Configuration Registers

The configuration bits in each device configuration reg-

ister specify some of the device modes and are pro-

grammed by a device programmer, or by using the In-

Circuit Serial Programming™ (ICSP™) feature of the

device. Each device configuration register is a 24-bit

register, but only the lower 16 bits of each register are

used to hold configuration data. There are four device

configuration registers available to the user:

All RESETS will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep

status bit. In a POR, the Sleep bit is cleared.

If Watchdog Timer is enabled, then the processor will

wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO status bits are both set.

1. F^OSC(0xF80000): Oscillator Configuration

Register

2. FWDT (0xF80002): Watchdog Timer

Configuration Register

21.6.2

IDLE MODE

3. FBORPOR (0xF80004): BOR and POR

Configuration Register

In Idle mode, the clock to the CPU is shutdown while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

4. FGS (0xF8000A): General Code Segment

Configuration Register

Several peripherals have a control bit in each module,

that allows them to operate during Idle.

The placement of the configuration bits is automatically

handled when you select the device in your device pro-

grammer. The desired state of the configuration bits

may be specified in the source code (dependent on the

language tool used), or through the programming inter-

face. After the device has been programmed, the appli-

cation software may read the configuration bit values

through the table read instructions. For additional infor-

mation, please refer to the programming specifications

of the device.

LPRC fail-safe clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions is true:

• on any interrupt that is individually enabled (IE bit

is ‘1’) and meets the required priority level

• on any Reset (POR, BOR, MCLR)

• on WDT time-out

Note:

If the code protection configuration fuse

bits (FGS<GCP> and FGS<GWRP>)

have been programmed, an erase of the

entire code-protected device is only

possible at voltages V^DD≥ 4.5V.

Upon wake-up from Idle mode, the clock is re-applied

to the CPU and instruction execution begins immedi-

ately, starting with the instruction following the PWRSAV

instruction.

 2003 Microchip Technology Inc.

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DS70082C-page 159

dsPIC30F

21.8 Peripheral Module Disable (PMD)

Registers

21.9 In-Circuit Debugger

When MPLAB ICD2 is selected as a Debugger, the In-

Circuit Debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. When the device has this feature enabled,

some of the resources are not available for general

use. These resources include the first 80 bytes of Data

RAM and two I/O pins.

The Peripheral Module Disable (PMD) registers pro-

vide a method to disable a peripheral module by stop-

ping all clock sources supplied to that module. When a

peripheral is disabled via the appropriate PMD control

bit, the peripheral is in a minimum power consumption

state. The control and status registers associated with

the peripheral will also be disabled, so writes to those

registers will have no effect and read values will be

invalid.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC, EMUD1/

EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.

A peripheral module will only be enabled if both the

associated bit in the PMD register is cleared, and the

peripheral is supported by the specific dsPIC variant. If

the peripheral is present in the device, it is enabled in

the PMD register by default.

In each case, the selected EMUD pin is the Emulation/

Debug Data line, and the EMUC pin is the Emulation/

Debug Clock line. These pins will interface to the

MPLAB ICD 2 module available from Microchip. The

selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send and receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD, and the selected EMUDx/EMUCx pin pair.

Note:

If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of 1 instruction

cycle. Similarly, if a PMD bit is cleared, the

corresponding module is enabled after a

delay of 1 instruction cycle (assuming the

module control registers are already con-

figured to enable module operation).

This gives rise to two possibilities:

1. If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/

EMUC3 is selected as the Debug I/O pin pair,

then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

DS70082C-page 160

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 2003 Microchip Technology Inc.

dsPIC30F

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 161

dsPIC30F

NOTES:

DS70082C-page 162

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

The literal instructions that involve data movement may

use some of the following operands:

22.0 INSTRUCTION SET SUMMARY

The dsPIC30F instruction set adds many

• A literal value to be loaded into a W register or file

register (specified by the value of ’k’)

®

enhancements to the previous PICmicro instruction

sets, while maintaining an easy migration from

PICmicro instruction sets.

• The W register or file register where the literal

value is to be loaded (specified by ’Wb’ or ’f’)

Most instructions are a single program memory word

(24-bits). Only three instructions require two program

memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ’Wb’

without any address modifier

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode which specifies the instruction

type, and one or more operands which further specify

the operation of the instruction.

• The second source operand, which is a literal

value

• The destination of the result (only if not the same

as the first source operand), which is typically a

register ’Wd’ with or without an address modifier

The instruction set is highly orthogonal and is grouped

into five basic categories:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

The MACclass of DSP instructions may use some of the

following operands:

• The accumulator (A or B) to be used (required

operand)

• DSP operations

• Control operations

• The W registers to be used as the two operands

• The X and Y address space pre-fetch operations

• The X and Y address space pre-fetch destinations

• The accumulator write back destination

Table 22-1 shows the general symbols used in describ-

ing the instructions.

The dsPIC30F instruction set summary in Table 22-2

lists all the instructions along with the status flags

affected by each instruction.

The other DSP instructions do not involve any

multiplication, and may include:

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The accumulator to be used (required)

• The source or destination operand (designated as

Wso or Wdo, respectively) with or without an

address modifier

• The first source operand, which is typically a

register ’Wb’ without any address modifier

• The amount of shift, specified by a W register

’Wn’ or a literal value

• The second source operand, which is typically a

register ’Ws’ with or without an address modifier

The control instructions may use some of the following

operands:

• The destination of the result, which is typically a

register ’Wd’ with or without an address modifier

• A program memory address

However, word or byte-oriented file register instructions

have two operands:

• The mode of the Table Read and Table Write

instructions

• The file register specified by the value ’f’

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all the required information is

available in these 48-bits. In the second word, the

8 MSb’s are 0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

• The destination, which could either be the file

register ’f’ or the W0 register, which is denoted as

’WREG’

Most bit oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address modi-

fier) or file register (specified by the value of ’Ws’

or ’f’)

• The bit in the W register or file register

(specified by a literal value, or indirectly by the

contents of register ’Wb’)

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 163

dsPIC30F

Most single word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all

Table Reads and Writes and RETURN/RETFIEinstruc-

tions, which are single word instructions, but take two

or three cycles. Certain instructions that involve skip-

ping over the subsequent instruction, require either two

or three cycles if the skip is performed, depending on

whether the instruction being skipped is a single word

or two-word instruction. Moreover, double-word moves

require two cycles. The double-word instructions

execute in two instruction cycles.

Note:

For more details on the instruction set,

refer to the Programmer’s Reference

Manual.

TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text

Means literal defined by “text“

Means “content of text“

Means “the location addressed by text”

Optional field or operation

Register bit field

(text)

[text]

{

}

<n:m>

.b

Byte mode selection

.d

Double-word mode selection

Shadow register select

.S

.w

Word mode selection (default)

One of two accumulators {A, B}

Acc

AWB

bit4

Accumulator write back destination address register ∈ {W13, [W13]+=2}

4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

MCU status bits: Carry, Digit Carry, Negative, Overflow, Zero

Absolute address, label or expression (resolved by the linker)

File register address ∈ {0x0000...0x1FFF}

1-bit unsigned literal ∈ {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal ∈ {0...15}

lit5

5-bit unsigned literal ∈ {0...31}

lit8

8-bit unsigned literal ∈ {0...255}

lit10

lit14

lit16

lit23

None

10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal ∈ {0...16384}

16-bit unsigned literal ∈ {0...65535}

23-bit unsigned literal ∈ {0...8388608}; LSB must be 0

Field does not require an entry, may be blank

DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate

Program Counter

OA, OB, SA, SB

PC

Slit10

Slit16

Slit6

10-bit signed literal ∈ {-512...511}

16-bit signed literal ∈ {-32768...32767}

6-bit signed literal ∈ {-16...16}

DS70082C-page 164

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

Wb

Base W register ∈ {W0..W15}

Wd

Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wm*Wm

Dividend, Divisor working register pair (direct addressing)

Multiplicand and Multiplier working register pair for Square instructions ∈

{W4*W4,W5*W5,W6*W6,W7*W7}

Wm*Wn

Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}

Wn

One of 16 working registers ∈ {W0..W15}

Wnd

Wns

WREG

Ws

One of 16 destination working registers ∈ {W0..W15}

One of 16 source working registers ∈ {W0..W15}

W0 (working register used in file register instructions)

Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso

Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx

X data space pre-fetch address register for DSP instructions

∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,

[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,

[W9+W12],none}

Wxd

Wy

X data space pre-fetch destination register for DSP instructions ∈ {W4..W7}

Y data space pre-fetch address register for DSP instructions

∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,

[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,

[W11+W12], none}

Wyd

Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7}

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 165

dsPIC30F

TABLE 22-2: INSTRUCTION SET OVERVIEW

Bas

# of

cycle

s

eIns Assembly

Assembly Syntax

# of

Status Flags

Affected

Description

tr

Mnemonic

words

#

1

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

BTG

Acc

Add Accumulators

1

OA,OB,SA,SB

C,DC,N,OV,Z

OA,OB,SA,SB

C,DC,N,OV,Z

N,Z

f

f = f + WREG

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

f

WREG = f + WREG

Wd = lit10 + Wd

Wd = Wb + Ws

Wd = Wb + lit5

16-bit Signed Add to Accumulator

f = f + WREG + (C)

2

3

4

ADDC

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

AND

f = f .AND. WREG

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

N,Z

Wd = Wb .AND. lit5

N,Z

ASR

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

C,N,OV,Z

N,Z

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

N,Z

5

6

BCLR

BRA

None

Ws,#bit4

C,Expr

Bit Clear Ws

None

Branch if Carry

1 (2) None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

Branch if unsigned less than

Branch if Negative

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OA,Expr

OB,Expr

OV,Expr

SA,Expr

SB,Expr

Expr

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if accumulator A overflow

Branch if accumulator B overflow

Branch if Overflow

Branch if accumulator A saturated

Branch if accumulator B saturated

Branch Unconditionally

Branch if Zero

2

None

Z,Expr

1 (2) None

Wn

Computed Branch

2

1

None

7

8

9

BSET

BSW

BTG

f,#bit4

Bit Set f

Ws,#bit4

Ws,Wb

Bit Set Ws

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

Ws,Wb

f,#bit4

Ws,#bit4

Bit Toggle Ws

DS70082C-page 166

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 2003 Microchip Technology Inc.

dsPIC30F

TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Bas

# of

eIns Assembly

# of

Status Flags

Affected

Assembly Syntax

Description

cycle

s

tr

Mnemonic

words

#

10

BTSC

BTSS

f,#bit4

Bit Test f, Skip if Clear

Bit Test Ws, Skip if Clear

Bit Test f, Skip if Set

1

(2 or

3)

None

Ws,#bit4

1

(2 or

3)

11

12

13

BTSS

BTST

BTSTS

f,#bit4

1

(2 or

3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

(2 or

3)

BTST

f,#bit4

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Ws,#bit4

Ws,Wb

f,#bit4

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

C

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call subroutine

C

Z

14

15

CALL

CLR

CALL

CLR

CLRWDT

COM

CP

lit23

None

Wn

Call indirect subroutine

f = 0x0000

None

f

None

WREG

WREG = 0x0000

None

Ws

Ws = 0x0000

None

Acc,Wx,Wxd,Wy,Wyd,AWB

Clear Accumulator

Clear Watchdog Timer

f = f

OA,OB,SA,SB

WDTO,Sleep

N,Z

16

17

CLRWDT

COM

f

f,WREG

WREG = f

N,Z

Ws,Wd

Wd = Ws

N,Z

18

CP

f

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb - Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with 0xFFFF

Compare Ws with 0xFFFF

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C,DC,N,OV,Z

CP

Wb,#lit5

CP

Wb,Ws

19

20

21

CP0

CP1

CPB

CP0

CP1

CPB

f

Ws

f

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb - Ws - C)

22

23

24

25

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb, Wn

Compare Wb with Wn, skip if =

Compare Wb with Wn, skip if >

Compare Wb with Wn, skip if <

^{Compare Wb with Wn, skip if}≠

1

(2 or

3)

None

1

(2 or

3)

1

(2 or

3)

1

(2 or

3)

26

27

DAW

DEC

DAW

DEC

Wn

Wn = decimal adjust Wn

f = f -1

1

C

f

C,DC,N,OV,Z

f,WREG

Ws,Wd

WREG = f -1

Wd = Ws - 1

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 167

dsPIC30F

TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Bas

# of

cycle

s

eIns Assembly

# of

Status Flags

Affected

Assembly Syntax

Description

tr

Mnemonic

words

#

28

DEC2

DISI

f

f = f -2

1

2

1

C,DC,N,OV,Z

None

f,WREG

Ws,Wd

WREG = f -2

Wd = Ws - 2

1

29

30

DISI

DIV

#lit14

Disable Interrupts for k instruction cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Signed 16/16-bit Fractional Divide

Do code to PC+Expr, lit14+1 times

Do code to PC+Expr, (Wn)+1 times

Euclidean Distance ( no accumulate)

1

DIV.S

DIV.SD

DIV.U

DIV.UD

DIVF

DO

Wm,Wn

18

2

N,Z,C, OV

None

Wm,Wn

31

32

DIVF

DO

Wm,Wn

#lit14,Expr

Wn,Expr

DO

2

None

33

34

ED

Wm*Wm,Acc,Wx,Wy,Wxd

1

OA,OB,OAB,

SA,SB,SAB

EDAC

Wm*Wm,Acc,Wx,Wy,Wxd

Euclidean Distance

1

OA,OB,OAB,

SA,SB,SAB

35

36

37

38

39

EXCH

FBCL

FF1L

EXCH

FBCL

FF1L

FF1R

GOTO

INC

Wns,Wnd

Ws,Wnd

Expr

Swap Wns with Wnd

Find Bit Change from Left (MSb) Side

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to address

1

2

1

2

1

None

C

FF1R

GOTO

C

None

Wn

Go to indirect

None

40

41

42

INC

f

f = f + 1

C,DC,N,OV,Z

N,Z

INC

f,WREG

Ws,Wd

f

WREG = f + 1

INC

Wd = Ws + 1

INC2

IOR

f = f + 2

f,WREG

Ws,Wd

f

WREG = f + 2

Wd = Ws + 2

IOR

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

Wd = Wb .IOR. Ws

Wd = Wb .IOR. lit5

Load Accumulator

N,Z

IOR

N,Z

IOR

N,Z

IOR

N,Z

43

LAC

OA,OB,OAB,

SA,SB,SAB

44

45

LNK

LSR

LNK

LSR

MAC

#lit14

Link frame pointer

1

None

f

f = Logical Right Shift f

C,N,OV,Z

N,Z

f,WREG

Ws,Wd

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Multiply and Accumulate

Wb,Wns,Wnd

Wb,#lit5,Wnd

N,Z

46

MAC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,

AWB

OA,OB,OAB,

SA,SB,SAB

MAC

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Square and Accumulate

1

OA,OB,OAB,

SA,SB,SAB

47

MOV

f,Wn

Move f to Wn

1

2

1

None

N,Z

MOV

f

Move f to f

MOV

f,WREG

#lit16,Wn

#lit8,Wn

Wn,f

Move f to WREG

N,Z

MOV

Move 16-bit literal to Wn

Move 8-bit literal to Wn

Move Wn to f

None

N,Z

MOV.b

MOV

Wso,Wdo

WREG,f

Wns,Wd

Ws,Wnd

Move Ws to Wd

MOV

Move WREG to f

MOV.D

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

Pre-fetch and store accumulator

None

48

MOVSAC

MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB

DS70082C-page 168

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Bas

# of

eIns Assembly

# of

Status Flags

Affected

Assembly Syntax

Description

cycle

s

tr

Mnemonic

words

#

49

MPY

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

Multiply Wm by Wn to Accumulator

Square Wm to Accumulator

1

OA,OB,OAB,

SA,SB,SAB

OA,OB,OAB,

SA,SB,SAB

50

51

MPY.N

MSC

MPY.N

MSC

-(Multiply Wm by Wn) to Accumulator

Multiply and Subtract from Accumulator

1

None

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,

AWB

OA,OB,OAB,

SA,SB,SAB

52

MUL

MUL.SS

MUL.SU

MUL.US

MUL.UU

Wb,Ws,Wnd

{Wnd+1, Wnd} = signed(Wb) * signed(Ws)

{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)

{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)

1

None

{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(Ws)

MUL.SU

MUL.UU

Wb,#lit5,Wnd

{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)

1

None

{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(lit5)

MUL

NEG

f

W3:W2 = f * WREG

Negate Accumulator

1

None

53

NEG

Acc

OA,OB,OAB,

SA,SB,SAB

NEG

NOP

NOPR

POP

f

f = f + 1

1

2

C,DC,N,OV,Z

None

f,WREG

Ws,Wd

WREG = f + 1

Wd = Ws + 1

54

55

NOP

POP

No Operation

None

f

Pop f from top-of-stack (TOS)

Pop from top-of-stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from top-of-stack (TOS) to

W(nd):W(nd+1)

None

POP.S

PUSH

PUSH.D

PUSH.S

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

Pop Shadow Registers

1

2

1

2

1

All

56

PUSH

f

Push f to top-of-stack (TOS)

Push Wso to top-of-stack (TOS)

Push W(ns):W(ns+1) to top-of-stack (TOS)

Push Shadow Registers

None

WDTO,Sleep

None

Wso

Wns

57

58

PWRSAV

RCALL

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

Computed Call

59

REPEAT

#lit14

Wn

Repeat Next Instruction lit14+1 times

Repeat Next Instruction (Wn)+1 times

Software device Reset

60

61

62

63

64

RESET

RETFIE

RETLW

RETURN

RLC

Return from interrupt

3 (2) None

#lit10,Wn

Return with literal in Wn

Return from Subroutine

f

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Store Accumulator

1

C,N,Z

N,Z

RLC

f,WREG

Ws,Wd

f

RLC

65

66

67

RLNC

RRC

f,WREG

Ws,Wd

f

N,Z

RRC

C,N,Z

N,Z

RRC

f,WREG

Ws,Wd

f

RRC

RRNC

SAC

f,WREG

Ws,Wd

Acc,#Slit4,Wdo

Ws,Wnd

N,Z

68

69

SAC

SE

None

C,N,Z

SAC.R

SE

Store Rounded Accumulator

Wnd = sign extended Ws

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 169

dsPIC30F

TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Bas

# of

cycle

s

eIns Assembly

# of

Status Flags

Affected

Assembly Syntax

Description

tr

Mnemonic

words

#

70

SETM

SFTAC

f

f = 0xFFFF

1

None

WREG

Ws

WREG = 0xFFFF

Ws = 0xFFFF

71

SFTAC

Acc,Wn

Arithmetic Shift Accumulator by (Wn)

OA,OB,OAB,

SA,SB,SAB

SFTAC

Acc,#Slit6

Arithmetic Shift Accumulator by Slit6

1

OA,OB,OAB,

SA,SB,SAB

72

SL

f

f = Left Shift f

1

C,N,OV,Z

N,Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

Acc

WREG = Left Shift f

Wd = Left Shift Ws

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

Subtract Accumulators

SL

N,Z

73

SUB

OA,OB,OAB,

SA,SB,SAB

SUB

f

f = f - WREG

1

2

1

C,DC,N,OV,Z

None

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f - WREG

Wn = Wn - lit10

SUB

Wd = Wb - Ws

SUB

Wd = Wb - lit5

74

SUBB

SUBR

SUBBR

SWAP.b

SWAP

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

f = f - WREG - (C)

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f - WREG - (C)

Wn = Wn - lit10 - (C)

Wd = Wb - Ws - (C)

Wd = Wb - lit5 - (C)

f = WREG - f

75

76

77

SUBR

SUBBR

SWAP

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = WREG - f

Wd = Ws - Wb

Wd = lit5 - Wb

f = WREG - f - (C)

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG -f - (C)

Wd = Ws - Wb - (C)

Wd = lit5 - Wb - (C)

Wn = nibble swap Wn

Wn = byte swap Wn

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink frame pointer

f = f .XOR. WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

Wd = Wb .XOR. lit5

Wnd = Zero-Extend Ws

Wn

None

78

79

80

81

82

83

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

Ws,Wd

None

XOR

f

N,Z

XOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N,Z

XOR

N,Z

XOR

N,Z

XOR

N,Z

84

ZE

C,Z,N

DS70082C-page 170

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

23.1 MPLAB Integrated Development

Environment Software

23.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• An interface to debugging tools

- simulator

- MPLAB C17 and MPLAB C18 C Compilers

- programmer (sold separately)

- emulator (sold separately)

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

• Customizable data windows with direct edit of

contents

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

• Emulators

• High level source code debugging

• Mouse over variable inspection

• Extensive on-line help

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

- MPLAB ICD 2

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Development Programmer

• Low Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM.net^TMDemonstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM LIN Demonstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

(automatically updates all project information)

• Debug using:

- source files (assembly or C)

- absolute listing file (mixed assembly and C)

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increasing flexibility

and power.

23.2 MPASM Assembler

®

- KEELOQ

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

- PICDEM MSC

- microID^®

- CAN

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol ref-

erence, absolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

- PowerSmart^®

- Analog

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User defined macros to streamline assembly code

• Conditional assembly for multi-purpose source

files

• Directives that allow complete control over the

assembly process

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 171

dsPIC30F

23.3 MPLAB C17 and MPLAB C18

C Compilers

23.6 MPLAB ASM30 Assembler, Linker,

and Librarian

The MPLAB C17 and MPLAB C18 Code Development

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

Systems are complete ANSI

C

compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

23.4 MPLINK Object Linker/

MPLIB Object Librarian

• Rich directive set

• Flexible macro language

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from pre-compiled libraries, using

directives from a linker script.

• MPLAB IDE compatibility

23.7 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any pin. The execu-

tion can be performed in Single-Step, Execute Until

Break, or Trace mode.

The MPLIB object librarian manages the creation and

modification of library files of pre-compiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

23.5 MPLAB C30 C Compiler

23.8 MPLAB SIM30 Software Simulator

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command-

line options and language extensions to take full

advantage of the dsPIC30F device hardware capabili-

ties, and afford fine control of the compiler code

generator.

The MPLAB SIM30 software simulator allows code

development in a PC hosted environment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler. The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been vali-

dated and conform to the ANSI C library standard. The

library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keeping, and math functions (trigonometric, exponen-

tial and hyperbolic). The compiler provides symbolic

information for high level source debugging with the

MPLAB IDE.

DS70082C-page 172

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

23.9 MPLAB ICE 2000

High Performance Universal

23.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low cost, run-time development tool,

connecting to the host PC via an RS-232 or high speed

USB interface. This tool is based on the Flash

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the FLASH devices. This feature, along with

In-Circuit Emulator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

Microchip’s In-Circuit Serial Programming^TM(ICSP^TM

)

protocol, offers cost effective in-circuit FLASH debug-

ging from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro devices.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

23.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maximum reliability. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II device programmer can read, verify, and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

23.10 MPLAB ICE 4000

High Performance Universal

In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for high-

end PICmicro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environment.

23.13 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, up to 2 Mb of emulation memory, and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were cho-

sen to best make these features available in a simple,

unified application.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 173

dsPIC30F

23.14 PICDEM 1 PICmicro

Demonstration Board

23.17 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 1 demonstration board demonstrates the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provided with the PICDEM 1 demonstration board can

be programmed with a PRO MATE II device program-

mer, or a PICSTART Plus development programmer.

The PICDEM 1 demonstration board can be connected

to the MPLAB ICE in-circuit emulator for testing. A pro-

totype area extends the circuitry for additional applica-

tion components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and software is included to run

the demonstration programs.

23.18 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8-, 14-, and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-

ily of microcontrollers. PICDEM 4 is intended to show-

case the many features of these low pin count parts,

including LIN and Motor Control using ECCP. Special

provisions are made for low power operation with the

supercapacitor circuit, and jumpers allow on-board

hardware to be disabled to eliminate current draw in

this mode. Included on the demo board are provisions

for Crystal, RC or Canned Oscillator modes, a five volt

regulator for use with a nine volt wall adapter or battery,

DB-9 RS-232 interface, ICD connector for program-

ming via ICSP and development with MPLAB ICD 2,

2x16 liquid crystal display, PCB footprints for H-Bridge

motor driver, LIN transceiver and EEPROM. Also

included are: header for expansion, eight LEDs, four

potentiometers, three push buttons and a prototyping

area. Included with the kit is a PIC16F627A and a

PIC18F1320. Tutorial firmware is included along with

the User’s Guide.

23.15 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface, and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

23.19 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A pro-

grammed sample is included. The PRO MATE II device

programmer, or the PICSTART Plus development pro-

grammer, can be used to reprogram the device for user

tailored application development. The PICDEM 17

demonstration board supports program download and

execution from external on-board FLASH memory. A

generous prototype area is available for user hardware

expansion.

23.16 PICDEM 2 Plus

Demonstration Board

The PICDEM 2 Plus demonstration board supports

many 18-, 28-, and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary hardware and software is included to run the dem-

onstration programs. The sample microcontrollers

provided with the PICDEM 2 demonstration board can

be programmed with a PRO MATE II device program-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB ICD 2 and MPLAB ICE in-circuit emulators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display, a piezo speaker, an on-board temperature

sensor, four LEDs, and sample PIC18F452 and

PIC16F877 FLASH microcontrollers.

DS70082C-page 174

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

23.20 PICDEM 18R PIC18C601/801

Demonstration Board

23.23 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/De-multiplexed and 16-bit

Memory modes. The board includes 2 Mb external

FLASH memory and 128 Kb SRAM memory, as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

The PICDEM USB Demonstration Board shows off the

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

23.24 Evaluation and

Programming Tools

In addition to the PICDEM series of circuits, Microchip

has a line of evaluation kits and demonstration software

for these products.

23.21 PICDEM LIN PIC16C43X

Demonstration Board

• KEELOQ evaluation and programming tools for

The powerful LIN hardware and software kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

on-board LIN transceivers. A PIC16F874 FLASH

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN bus communication.

Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network

applications

• Analog design boards and filter design software

• PowerSmart battery charging evaluation/

calibration kits

• IrDA^®development kit

• microID development and rfLab^TMdevelopment

software

23.22 PICkit^TM1 FLASH Starter Kit

• SEEVAL^®designer kit for memory evaluation and

endurance calculations

A complete "development system in a box", the PICkit

FLASH Starter Kit includes a convenient multi-section

board for programming, evaluation, and development

of 8/14-pin FLASH PIC^®microcontrollers. Powered via

USB, the board operates under a simple Windows GUI.

The PICkit 1 Starter Kit includes the user's guide (on

CD ROM), PICkit 1 tutorial software and code for vari-

ous applications. Also included are MPLAB^®IDE (Inte-

grated Development Environment) software, software

and hardware "Tips 'n Tricks for 8-pin FLASH PIC^®

Microcontrollers" Handbook and a USB Interface

Cable. Supports all current 8/14-pin FLASH PIC

microcontrollers, as well as many future planned

devices.

• PICDEM MSC demo boards for Switching mode

power supply, high power IR driver, delta sigma

ADC, and flow rate sensor

Check the Microchip web page and the latest Product

Line Card for the complete list of demonstration and

evaluation kits.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 175

dsPIC30F

NOTES:

DS70082C-page 176

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

24.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future

revisions of this document as it becomes available.

For detailed information about the dsPIC30F architecture and core, refer to dsPIC30F Family Reference Manual

(DS70046).

Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for

extended periods may affect device reliability. Functional operation of the device at these or any other conditions above

the parameters indicated in the operation listings of this specification is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Voltage on MCLR with respect to VSS (Note 1) ......................................................................................... 0V to +13.25V

Total power dissipation (Note 2) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).......................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)................................................................................................... 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

†

NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific

devices, please refer the the Family Cross Reference Table.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 177

dsPIC30F

24.1 DC Characteristics

TABLE 24-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

VDD Range

Temp Range

dsPIC30FXXX-30I

dsPIC30FXXX-20I

dsPIC30FXXX-20E

4.5-5.5V

3.0-3.6V

2.5-3.0V

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

30

20

15

20

10

15

7.5

TABLE 24-2: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Typ

Max Units

Conditions

(2)

Operating Voltage

DC10

DC11

DC12

DC16

VDD

VDR

VPOR

Supply Voltage

2.5

—

5.5

—

V

Industrial temperature

Extended temperature

Supply Voltage

(3)

RAM Data Retention Voltage

1.5

VSS

VDD Start Voltage

to ensure internal

—

Power-on Reset signal

DC17

SVDD

VDD Rise Rate

0.05

V/ms 0-5V in 0.1 sec

0-3V in 60 ms

to ensure internal

Power-on Reset signal

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: This is the limit to which VDD can be lowered without losing RAM data.

DS70082C-page 178

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-3: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Operating Current (IDD)

DC20

—

4

—

mA

-40°C

25°C

DC20a

DC20b

DC20c

DC20d

DC20e

DC20f

DC20g

DC21

3V

5V

3V

5V

3V

5V

3 V

5V

—

7

85°C

125°C

-40°C

25°C

1 MIPS EC mode

—

8

85°C

125°C

-40°C

25°C

DC21a

DC21b

DC21c

DC21d

DC21e

DC21f

DC21g

DC22

—

15

—

13

—

22

—

85°C

125°C

-40°C

25°C

2.5 MIPS EC mode

85°C

125°C

-40°C

25°C

DC22a

DC22b

DC22c

DC22d

DC22e

DC22f

DC22g

DC23

85°C

125°C

-40°C

25°C

10 MIPS EC mode

85°C

125°C

-40°C

25°C

DC23a

DC23b

DC23c

DC23d

DC23e

DC23f

DC23g

85°C

125°C

-40°C

25°C

4 MIPS EC mode, 4X PLL

85°C

125°C

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are operational. No peripheral modules are operating.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 179

dsPIC30F

TABLE 24-3: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

(1)

Typical

Max

Units

Conditions

No.

(2)

Operating Current (IDD)

DC24

—

29

—

50

—

23

—

41

—

39

—

70

—

50

—

90

—

mA

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

-40°C

25°C

85°C

125°C

DC24a

DC24b

DC24c

DC24d

DC24e

DC24f

DC24g

DC25

3V

5V

3V

5V

3V

10 MIPS EC mode, 4X PLL

DC25a

DC25b

DC25c

DC25d

DC25e

DC25f

DC25g

DC26

8 MIPS EC mode, 8X PLL

DC26a

DC26b

DC26c

DC26d

DC26e

DC26f

DC26g

DC27

15 MIPS EC mode, 8X PLL

5V

3V

5V

DC27a

DC27b

DC27c

DC27d

DC27e

DC27f

20 MIPS EC mode, 8X PLL

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are operational. No peripheral modules are operating.

DS70082C-page 180

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-3: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Operating Current (IDD)

DC28

—

42

—

76

—

146

—

7.0

—

12

—

1.5

—

2.5

—

mA

-40°C

25°C

85°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

DC28a

DC28b

DC28c

DC28d

DC28e

DC28f

DC29

3V

16 MIPS EC mode, 16X PLL

5V

DC29a

DC29b

DC29c

DC30

5V

3V

5V

3V

5 V

30 MIPS EC mode, 16X PLL

DC30a

DC30b

DC30c

DC30d

DC30e

DC30f

DC30g

DC31

FRC (~ 2 MIPS)

DC31a

DC31b

DC31c

DC31d

DC31e

DC31f

DC31g

LPRC (~ 512 kHz)

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are operational. No peripheral modules are operating.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 181

dsPIC30F

TABLE 24-4: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Idle Current (IIDLE): Core OFF Clock ON Base Current

DC40

—

3

—

mA

-40°C

25°C

DC40a

DC40b

DC40c

DC40d

DC40e

DC40f

DC40g

DC41

3V

5V

3V

5V

3V

5V

3V

5V

—

5

85°C

125°C

-40°C

25°C

1 MIPS EC mode

—

4.8

—

8.6

—

7.7

—

13

—

85°C

125°C

-40°C

25°C

DC41a

DC41b

DC41c

DC41d

DC41e

DC41f

DC41g

DC42

85°C

125°C

-40°C

25°C

2.5 MIPS EC mode

85°C

125°C

-40°C

25°C

DC42a

DC42b

DC42c

DC42d

DC42e

DC42f

DC42g

DC43

85°C

125°C

-40°C

25°C

10 MIPS EC mode

85°C

125°C

-40°C

25°C

DC43a

DC43b

DC43c

DC43d

DC43e

DC43f

DC43g

85°C

125°C

-40°C

25°C

4 MIPS EC mode, 4X PLL

85°C

125°C

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

DS70082C-page 182

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-4: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Idle Current (IIDLE): Core OFF Clock ON Base Current

DC44

—

15

—

29

—

13

—

24

—

22

—

40

—

29

—

52

—

mA

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

-40°C

25°C

85°C

125°C

DC44a

DC44b

DC44c

DC44d

DC44e

DC44f

DC44g

DC45

3V

5V

3V

5V

3V

10 MIPS EC mode, 4X PLL

DC45a

DC45b

DC45c

DC45d

DC45e

DC45f

DC45g

DC46

8 MIPS EC mode, 8X PLL

DC46a

DC46b

DC46c

DC46d

DC46e

DC46f

DC46g

DC47

15 MIPS EC mode, 8X PLL

5V

3V

5V

DC47a

DC47b

DC47c

DC47d

DC47e

DC47f

20 MIPS EC mode, 8X PLL

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 183

dsPIC30F

TABLE 24-4: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

(1)

Typical

Max

Units

Conditions

No.

(2)

Idle Current (IIDLE): Core OFF Clock ON Base Current

DC48

—

24

—

43

—

73

—

4.0

—

7.0

—

1.0

—

1.5

—

mA

-40°C

25°C

85°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

-40°C

25°C

85°C

125°C

DC48a

DC48b

DC48c

DC48d

DC48e

DC48f

DC49

3V

16 MIPS EC mode, 16X PLL

5V

DC49a

DC49b

DC49c

DC50

5V

3V

5V

3V

5 V

30 MIPS EC mode, 16X PLL

DC50a

DC50b

DC50c

DC50d

DC50e

DC50f

DC50g

DC51

FRC (~ 2 MIPS)

DC51a

DC51b

DC51c

DC51d

DC51e

DC51f

DC51g

LPRC (~ 512 kHz)

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

DS70082C-page 184

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-5: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Power Down Current (IPD)

DC60

—

50

—

100

—

10

—

20

—

40

—

50

—

µA

-40°C

25°C

DC60a

DC60b

DC60c

DC60d

DC60e

DC60f

DC60g

DC61

3V

5V

3V

5V

3V

5V

3 V

5V

85°C

125°C

-40°C

25°C

(3)

Base Power Down Current

85°C

125°C

-40°C

25°C

DC61a

DC61b

DC61c

DC61d

DC61e

DC61f

DC61g

DC62

85°C

125°C

-40°C

25°C

(3)

Watchdog Timer Current: ∆IWDT

85°C

125°C

-40°C

25°C

DC62a

DC62b

DC62c

DC62d

DC62e

DC62f

DC62g

DC63

85°C

125°C

-40°C

25°C

(3)

Timer 1 w/32 kHz Crystal: ∆ITI32

85°C

125°C

-40°C

25°C

DC63a

DC63b

DC63c

DC63d

DC63e

DC63f

DC63g

85°C

125°C

-40°C

25°C

(3)

BOR On: ∆IBOR

85°C

125°C

Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. LVD, BOR, WDT, etc. are all switched off.

3: The ∆ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 185

dsPIC30F

TABLE 24-5: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Parameter

(1)

Typical

Max

Units

Conditions

No.

(2)

Power Down Current (IPD)

DC64

—

25

—

30

—

µA

-40°C

25°C

DC64a

DC64b

DC64c

DC64d

DC64e

DC64f

DC64g

DC65

3V

5V

3V

5V

3V

5V

85°C

125°C

-40°C

25°C

(3)

10-bit ADC: ∆IADC10

85°C

125°C

-40°C

25°C

DC65a

DC65b

DC65c

DC65d

DC65e

DC65f

DC65g

DC66

85°C

125°C

-40°C

25°C

(3)

12-bit ADC: ∆IADC12

85°C

125°C

-40°C

25°C

DC66a

DC66b

DC66c

DC66d

DC66e

DC66f

DC66g

85°C

125°C

-40°C

25°C

(3)

Low Voltage Detect: ∆ILVD

85°C

125°C

Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. LVD, BOR, WDT, etc. are all switched off.

3: The ∆ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

DS70082C-page 186

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-6: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Typ

Max

Units

Conditions

(2)

VIL

Input Low Voltage

DI10

I/O pins:

with Schmitt Trigger buffer

VSS

TBD

—

0.2 VDD

0.3 VDD

TBD

V

DI15

DI16

DI17

DI18

DI19

MCLR

OSC1 (in XT, HS and LP modes)

(3)

OSC1 (in RC mode)

SDA, SCL

SM bus disabled

SM bus enabled

TBD

(2)

VIH

Input High Voltage

DI20

I/O pins:

with Schmitt Trigger buffer

0.8 VDD

—

VDD

TBD

V

DI25

DI26

DI27

DI28

DI29

MCLR

OSC1 (in XT, HS and LP modes) 0.7 VDD

(3)

OSC1 (in RC mode)

0.9 VDD

TBD

SDA, SCL

SM bus disabled

SM bus enabled

SDA, SCL

TBD

(2)

ICNPU

CNXX Pull-up Current

DI30

DI31

50

250

400

µA VDD = 5V, VPIN = VSS

µA VDD = 3V, VPIN = VSS

TBD

(2)(4)(5)

IIL

Input Leakage Current

DI50

I/O ports

—

0.01

1

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

DI55

DI56

MCLR

OSC1

—

0.05

5

VSS ≤ VPIN ≤ VDD

µA VSS ≤ VPIN ≤ VDD, XT, HS

and LP Osc mode

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that

the dsPIC30F device be driven with an external clock while in RC mode.

4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

5: Negative current is defined as current sourced by the pin.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 187

dsPIC30F

TABLE 24-7: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

Symbol

Characteristic

Min

Typ

Max Units

Conditions

No.

(2)

VOL

Output Low Voltage

DO10

DO16

I/O ports

—

0.6

TBD

0.6

V

IOL = 8.5 mA, VDD = 5V

IOL = 2.0 mA, VDD = 3V

IOL = 1.6 mA, VDD = 5V

IOL = 2.0 mA, VDD = 3V

OSC2/CLKOUT

(RC or EC Osc mode)

TBD

(2)

VOH

Output High Voltage

DO20

DO26

I/O ports

VDD – 0.7

TBD

—

V

IOH = -3.0 mA, VDD = 5V

IOH = -2.0 mA, VDD = 3V

IOH = -1.3 mA, VDD = 5V

IOH = -2.0 mA, VDD = 3V

OSC2/CLKOUT

VDD – 0.7

TBD

(RC or EC Osc mode)

Capacitive Loading Specs

(2)

on Output Pins

DO50 COSC2

OSC2/SOSC2 pin

—

15

pF In XTL, XT, HS and LP modes

when external clock is used to

drive OSC1.

DO56 CIO

DO58 CB

All I/O pins and OSC2

SCL, SDA

—

50

pF RC or EC Osc mode

2

pF In I C mode

400

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

FIGURE 24-1:

LOW-VOLTAGE DETECT CHARACTERISTICS

VDD

LV10

LVDIF

(LVDIF set by hardware)

DS70082C-page 188

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-8: ELECTRICAL CHARACTERISTICS: LVDL

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Typ

Max Units Conditions

(2)

LV10

VPLVD

LVDL Voltage on VDD transition LVDL = 0000

high to low

—

V

(2)

LVDL = 0001

LVDL = 0010

LVDL = 0011

LVDL = 0100

LVDL = 0101

LVDL = 0110

LVDL = 0111

LVDL = 1000

LVDL = 1001

LVDL = 1010

LVDL = 1011

LVDL = 1100

LVDL = 1101

LVDL = 1110

—

V

—

2.50

2.70

2.80

3.00

3.30

3.50

3.60

3.80

4.00

4.20

4.50

—

2.65

2.86

2.97

3.18

3.50

3.71

3.82

4.03

4.24

4.45

4.77

—

LV15

VLVDIN

External LVD input pin

threshold voltage

LVDL = 1111

Note 1: These parameters are characterized but not tested in manufacturing.

2: These values not in usable operating range.

FIGURE 24-2:

BROWN-OUT RESET CHARACTERISTICS

VDD

(Device not in Brown-out Reset)

BO15

BO10

(Device in Brown-out Reset)

RESET (due to BOR)

Power Up Time-out

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 189

dsPIC30F

TABLE 24-9: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min Typ

Max Units

Conditions

(2)

(3)

BO10

VBOR

BOR Voltage on

VDD transition high to

low

BORV = 00

—

V

Not in operating

range

BORV = 01

BORV = 10

BORV = 11

2.7

4.2

4.5

—

5

2.86

4.46

4.78

—

V

BO15

VBHYS

mV

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: 00values not in usable operating range.

TABLE 24-10: DC CHARACTERISTICS: PROGRAM AND EEPROM

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

Symbol

Characteristic

Min Typ

Max

Units

Conditions

No.

(2)

Data EEPROM Memory

Byte Endurance

D120

D121

ED

100K

1M

—

E/W -40°C ≤ TA ≤ +85°C

VDRW

VDD for Read/Write

VMIN

5.5

V

Using EECON to read/write

VMIN = Minimum operating

voltage

D122

D123

TDEW

Erase/Write Cycle Time

Characteristic Retention

—

2

—

ms

TRETD

40

100

Year Provided no other specifications

are violated

(2)

Program FLASH Memory

D130

D131

EP

Cell Endurance

10K

100K

—

E/W -40°C ≤ TA ≤ +85°C

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

D133

D134

D135

VEB

VDD for Block Erase

VDD for Erase/Write

3.0

—

5.5

—

V

VPEW

TPEW

TRETD

Erase/Write Cycle Time

Characteristic Retention

2

ms

40

100

—

Year Provided no other specifications

are violated

D136

TEB

ICSP Block Erase Time

—

4

—

ms

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

2: These parameters are characterized but not tested in manufacturing.

DS70082C-page 190

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

24.2 AC Characteristics and Timing Parameters

The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 24-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Operating voltage VDD range as described in DC Spec Section 24.0.

FIGURE 24-3:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 - for all pins except OSC2

Load Condition 2 - for OSC2

VDD/2

CL

RL

VSS

CL

RL = 464 Ω

CL = 50 pF for all pins except OSC2

5 pF for OSC2 output

VSS

FIGURE 24-4:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1

OS20

OS30 OS30

OS31 OS31

OS25

CLKOUT

OS40

OS41

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 191

dsPIC30F

TABLE 24-12: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Typ

Max

Units

Conditions

(2)

OS10 FOSC

External CLKIN Frequency

DC

4

—

40

10

7.5

MHz EC

(External clocks allowed only

in EC mode)

MHz EC with 4x PLL

MHz EC with 8x PLL

MHz EC with 16x PLL

4

(2)

Oscillator Frequency

DC

0.4

4

—

8

4

MHz RC

MHz XTL

10

7.5

25

33

—

MHz XT

4

MHz XT with 4x PLL

MHz XT with 8x PLL

MHz XT with 16x PLL

MHz HS

4

10

31

—

kHz

LP

MHz FRC internal

512

kHz

—

LPRC internal

OS20 TOSC

TOSC = 1/FOSC

—

See parameter OS10 for

FOSC value

(2)(3)

OS25 TCY

Instruction Cycle Time

33

—

DC

ns

See Table 24-14

(2)

External Clock in (OSC1)

OS30 TosL,

TosH

TBD

—

ns

µs

ns

XTL osc

XT osc

LP osc

HS osc

High or Low Time

(2)

External Clock in (OSC1)

OS31 TosR,

TosF

—

TBD

ns

XTL osc

XT osc

LP osc

HS osc

Rise or Fall Time

(2)(4)

OS40 TckR

OS41 TckF

CLKOUT Rise Time

—

6

10

ns

(2)(4)

CLKOUT Fall Time

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“Max.” cycle time limit is “DC” (no clock) for all devices.

4: Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin.

CLKOUT is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

DS70082C-page 192

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-13: PLL CLOCK TIMING SPECIFICATIONS (V^DD= 2.5 TO 5.5 V)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

(1)

(2)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

(2)

OS50

OS51

OS52

OS53

FPLLI

FSYS

TLOC

DCLK

PLL Input Frequency Range

4

16

—

20

1

10

120

50

MHz EC, XT modes with PLL

µs

(2)

On-chip PLL Output

PLL Start-up Time (Lock Time)

CLKOUT Stability (Jitter)

—

TBD

%

Measured over 100 ms

period

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

TABLE 24-14: INTERNAL CLOCK TIMING EXAMPLES

Clock

(3)

FOSC

(1)

(MHz)

MIPS

(2)

Oscillator

Mode

TCY (µsec)

w/o PLL

w PLL x4

w PLL x8

w PLL x16

EC

0.200

4

20.0

1.0

0.05

1.0

—

4.0

10.0

—

8.0

20.0

—

16.0

—

10

25

4

0.4

2.5

0.16

1.0

25.0

1.0

—

XT

4.0

10.0

8.0

20.0

16.0

—

10

0.4

2.5

Note 1: Assumption: Oscillator Postscaler is divide by 1.

2: Instruction Execution Cycle Time: TCY = 1 / MIPS.

3: Instruction Execution Frequency: MIPS = (FOSC * PLLx) / 4 [since there are 4 Q clocks per instruction

cycle].

TABLE 24-15: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Characteristic

Min

Typ

Max

Units

Conditions

No.

(1)

FRC @ Freq = 8 MHz

F14

TBD

+/-1

—

TBD

%

+25°C

VDD = 3V

VDD = 5V

F15

F16

F17

F18

F19

-10°C to +85°C

-40°C to +85°C

+25°C

—

+/-1

—

-10°C to +85°C

-40°C to +85°C

—

(2)

LPRC @ Freq = 512 kHz

F20

F21

TBD

—

TBD

%

-40°C to +85°C

VDD = 3V

VDD = 5V

Note 1: Frequency calibrated at 25°C. TUN bits can be used to compensate for temperature drift.

2: LPRC frequency after calibration.

3: Change of LPRC frequency as VDD changes.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 193

dsPIC30F

FIGURE 24-5:

CLKOUT AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

New Value

Old Value

(Output)

DO31

DO32

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-16: CLKOUT AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)(2)(3)

(4)

Typ

Characteristic

Min

Max

Units

Conditions

DO31

DO32

DI35

TIOR

TIOF

TINP

TRBP

Port output rise time

Port output fall time

—

10

—

25

—

ns

—

INTx pin high or low time (output)

CNx high or low time (input)

20

DI40

2 TCY

Note 1: These parameters are asynchronous events not related to any internal clock edges

2: Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x TOSC.

3: These parameters are characterized but not tested in manufacturing.

4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70082C-page 194

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

SY12

MCLR

SY10

Internal

POR

SY11

PWRT

Time-out

SY30

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

SY20

SY13

I/O Pins

SY35

FSCM

Delay

Note: Refer to Figure 24-3 for load conditions.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 195

dsPIC30F

TABLE 24-17: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

Characteristic

Min

Typ

Max Units

Conditions

No.

SY10

SY11

TmcL

MCLR Pulse Width (low)

Power-up Timer Period

2

—

µs

-40°C to +85°C

TPWRT

TBD

0

4

TBD

ms

-40°C to +85°C

User programmable

16

64

SY12

SY13

TPOR

TIOZ

Power On Reset Delay

3

10

—

30

µs

-40°C to +85°C

I/O Hi-impedance from MCLR

Low or Watchdog Timer Reset

—

100

ns

SY20

TWDT1

Watchdog Timer Time-out Period

(No Prescaler)

1.8

2.0

2.2

ms VDD = 5V, -40°C to +85°C

TWDT2

TBOR

TOST

1.9

100

—

2.1

—

2.3

—

ms VDD = 3V, -40°C to +85°C

(3)

SY25

SY30

SY35

Brown-out Reset Pulse Width

µs

—

µs

VDD ≤ VBOR (D034)

TOSC = OSC1 period

-40°C to +85°C

Oscillation Start-up Timer Period

Fail-Safe Clock Monitor Delay

1024 TOSC

100

TFSCM

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Refer to Figure 24-2 and Table 24-9 for BOR.

FIGURE 24-7:

BAND GAP START-UP TIME CHARACTERISTICS

VBGAP

0V

Enable Band Gap

(see Note)

Band Gap

Stable

SY40

Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.

TABLE 24-18: BAND GAP START-UP TIME REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

(2)

Characteristic

Min Typ

Max Units

Conditions

SY40

TBGAP

Band Gap Start-up Time

—

20

50

µs Defined as the time between the

instant that the band gap is enabled

and the moment that the band gap

reference voltage is stable.

RCON<13>Status bit

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70082C-page 196

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-8:

TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx1

Tx15

OS60

Tx2

TMRX

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-19: TYPE A TIMER EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

Characteristic

Min

Typ

Max Units

Conditions

No.

TA11

TTXH

TxCK High Time

Synchronous,

0.5 TCY + 20

—

ns Must also meet

parameter TA15

no prescaler

Synchronous,

with prescaler

10

—

ns

Asynchronous

10

—

ns

TA10

TTXL

TxCK Low Time

Synchronous,

no prescaler

0.5 TCY + 20

ns Must also meet

parameter TA15

Synchronous,

with prescaler

10

—

ns

Asynchronous

10

—

ns

TA15

TTXP

TxCK Input Period Synchronous,

no prescaler

TCY + 10

Synchronous,

with prescaler

Greater of:

20 ns or

—

N = prescale

value

(TCY + 40)/N

(1, 8, 64, 256)

Asynchronous

20

—

ns

OS60

Ft1

SOSC1/T1CK oscillator input

DC

50

kHz

frequency range (oscillator enabled

by setting bit TCS (T1CON, bit 1))

TA20

TCKEXTMRL Delay from External TQCK Clock

2 TOSC

6 TOSC

—

Edge to Timer Increment

Note:

Timer1 is a Type A.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 197

dsPIC30F

TABLE 24-20: TYPE B TIMER EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

TtxH

Characteristic

Min

Typ

Max

Units

Conditions

No.

TB11

TxCK High Time Synchronous, 0.5 TCY + 20

no prescaler

—

ns

Must also meet

parameter TB15

Synchronous,

with prescaler

10

—

ns

TB10

TtxL

TxCK Low Time

Synchronous, 0.5 TCY + 20

no prescaler

Must also meet

parameter TB15

Synchronous,

with prescaler

10

TB15

TtxP

TxCK Input Period Synchronous,

no prescaler

TCY + 10

N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TB20

TCKEXTMRL Delay from External TQCK Clock

2 TOSC

—

6 TOSC

—

Edge to Timer Increment

Note:

Timer2 and Timer4 are Type B.

TABLE 24-21: TYPE C TIMER EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max Units

Conditions

TtxH

TtxL

TtxP

TC11

TC10

TC15

TxCK High Time

Synchronous

0.5 TCY + 20

—

ns Must also meet

parameter TC15

TxCK Low Time

0.5 TCY + 20

—

ns Must also meet

parameter TC15

TxCK Input Period Synchronous,

no prescaler

TCY + 10

ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TC20

TCKEXTMRL Delay from External TQCK Clock

2 TOSC

—

6 TOSC

—

Edge to Timer Increment

Note:

Timer3 and Timer5 are Type C.

DS70082C-page 198

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-9:

TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS

QEB

TQ1

TQ15

TQ2

POSCNT

TABLE 24-22: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Typ

Max

Units

Conditions

TQ11

TtQH

TQCK High Time Synchronous,

with prescaler

TCY + 20

—

ns Must also meet

parameter TQ15

TQ10 TtQL

TQ15 TtQP

TQCK Low Time

Synchronous,

with prescaler

TCY + 20

—

ns Must also meet

parameter TQ15

TQCP Input Period Synchronous, 2 * TCY + 40

ns

—

with prescaler

TQ20

TCKEXTMRL Delay from External TQCK Clock

Tosc

5 Tosc

ns

—

Edge to Timer Increment

Note 1: These parameters are characterized but not tested in manufacturing.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 199

dsPIC30F

FIGURE 24-10:

INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICX

IC10

IC11

IC15

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-23: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Max

Units

Conditions

IC10

IC11

IC15

TccL

TccH

TccP

ICx Input Low Time No Prescaler

With Prescaler

0.5 TCY + 20

10

—

ns

ICx Input High Time No Prescaler

With Prescaler

0.5 TCY + 20

10

ICx Input Period

(2 TCY + 40)/N

N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 24-11:

OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx

(Output Compare

or PWM Mode)

OC10

OC11

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

(2)

Characteristic

Min

Typ

Max

Units

Conditions

OC10 TccF

OC11 TccR

OCx Output Fall Time

OCx Output Rise Time

—

10

25

ns

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70082C-page 200

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-12:

OCFA/OCFB

OCx

OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OC15

TABLE 24-25: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

No.

OC15 TFD

Fault Input to PWM I/O

Change

—

25

TBD

50

ns

VDD = 3V

VDD = 5V

VDD = 3V

VDD = 5V

-40°C to +85°C

OC20 TFLT

Fault Input Pulse Width

—

-40°C to +85°C

TBD

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 201

dsPIC30F

FIGURE 24-13:

MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS

MP30

FLTA/B

MP20

PWMx

FIGURE 24-14:

MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS

MP11 MP10

PWMx

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-26: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

-40°C to +85°C

No.

VDD = 5V

VDD = 3V

VDD = 5V

VDD = 3V

VDD = 5V

MP10

MP11

MP12

MP13

TFPWM

TRPWM

TFPWM

TRPWM

TFD

PWM Output Fall Time

PWM Output Rise Time

PWM Output Fall Time

PWM Output Rise Time

—

10

25

ns

-40°C to +85°C

TBD

—

TBD

25

Fault Input to PWM

I/O Change

MP20

MP30

TBD

50

TFH

Fault Input Hold Time

—

-40°C to +85°C

TBD

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70082C-page 202

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-15:

QEA/QEB INPUT CHARACTERISTICS

TQ36

QEA

(input)

TQ3

TQ35

QEB

(input)

TQ4

TQ3

QEB

Internal

TABLE 24-27: QUADRATURE DECODER TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

(2)

Characteristic

Typ

Max

Units

Conditions

TQ30

TQ31

TQ35

TQ36

TQ40

TQUL

Quadrature Input Low Time

Quadrature Input High Time

Quadrature Input Period

Quadrature Phase Period

6 TCY

—

ns

—

TQUH

TQUIN

TQUP

TQUFL

12 TCY

3 TCY

Filter Time to Recognize Low,

with Digital Filter

3 * N * TCY

N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

TQ41

TQUFH

Filter Time to Recognize High,

with Digital Filter

3 * N * TCY

—

ns

N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

Note 1: These parameters are characterized but not tested in manufacturing.

2: N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder

Interface (QEI)” in the dsPIC30F Family Reference Manual.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 203

dsPIC30F

FIGURE 24-16:

QEI MODULE INDEX PULSE TIMING CHARACTERISTICS

QEA

(input)

QEB

(input)

Ungated

Index

TQ50

TQ51

Index Internal

TQ55

Position

TABLE 24-28: QEI INDEX PULSE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Characteristic

Min

Max

Units

Conditions

TQ50

TQ51

TQ55

TqIL

Filter Time to Recognize Low,

with Digital Filter

3 * N * TCY

—

ns

N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

TqiH

Tqidxr

Filter Time to Recognize High,

with Digital Filter

3 * N * TCY

—

ns

N = 1, 2, 4, 16, 32, 64,

128 and 256 (Note 2)

Index Pulse Recognized to Position

Counter Reset (Ungated Index)

3 TCY

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Alignment of Index Pulses to QEA and QEB is shown for Position Counter reset timing only. Shown for

forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but

Index Pulse recognition occurs on falling edge.

DS70082C-page 204

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

2

DCI MODULE (MULTICHANNEL, I S MODES) TIMING CHARACTERISTICS

FIGURE 24-17:

CSCK

(SCKE =

1)

CS11

CS10

CS21

CS20

CSCK

(SCKE =

0)

CS21

CS20

COFS

CS55 CS56

CS35

70

CS51

CS50

LSb

HIGH-Z

MSb

CSDO

CS30

CS31

LSb IN

MSb IN

CSDI

CS40 CS41

Note: Refer to Figure 24-3 for load conditions.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 205

dsPIC30F

2

TABLE 24-29: DCI MODULE (MULTICHANNEL, I S MODES) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

No.

CS10

TcSCKL

CSCK Input Low Time

(CSCK pin is an input)

TCY / 2 + 20

—

10

—

ns

—

(3)

CSCK Output Low Time

30

—

25

ns

—

(CSCK pin is an output)

CS11

TcSCKH

CSCK Input High Time

(CSCK pin is an input)

TCY / 2 + 20

(3)

CSCK Output High Time

30

—

(CSCK pin is an output)

(4)

CS20

CS21

TcSCKF

TcSCKR

CSCK Output Fall Time

(CSCK pin is an output)

(4)

CSCK Output Rise Time

(CSCK pin is an output)

(4)

CS30

CS31

CS35

CS36

CS40

TcSDOF

TcSDOR

TDV

CSDO Data Output Fall Time

—

10

20

10

—

25

10

20

—

ns

—

(4)

CSDO Data Output Rise Time

Clock edge to CSDO data valid

Clock edge to CSDO tri-stated

TDIV

TCSDI

Setup time of CSDI data input to

CSCK edge (CSCK pin is input

or output)

CS41

THCSDI

Hold time of CSDI data input to

CSCK edge (CSCK pin is input

or output)

20

—

ns

—

CS50

CS51

CS55

CS56

TcoFSF

TcoFSR

TscoFS

THCOFS

COFS Fall Time

—

20

10

—

25

—

ns

Note 1

(COFS pin is output)

COFS Rise Time

Note 1

(COFS pin is output)

Setup time of COFS data input to

CSCK edge (COFS pin is input)

—

Hold time of COFS data input to

CSCK edge (COFS pin is input)

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all DCI pins.

DS70082C-page 206

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-18:

DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS

BIT_CLK

(CSCK)

CS62

CS61

CS60

CS21

CS20

CS71

CS70

CS72

SYNC

(COFS)

CS76

CS75

CS80

MSb

LSb

SDO

(CSDO)

CS76

CS75

MSb IN

SDI

(CSDI)

CS65 CS66

TABLE 24-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)(2)

(3)

Characteristic

Min

Typ

Max

Units

Conditions

CS60

CS61

CS62

CS65

TBCLKL

TBCLKH

TBCLK

TSACL

BIT_CLK Low Time

BIT_CLK High Time

BIT_CLK Period

36

—

40.7

81.4

—

45

—

10

ns

—

Bit clock is input

—

Input Setup Time to

Falling Edge of BIT_CLK

CS66

THACL

Input Hold Time from

—

10

ns

—

Falling Edge of BIT_CLK

CS70

CS71

CS72

CS75

CS76

CS77

CS78

CS80

TSYNCLO SYNC Data Output Low Time

—

19.5

1.3

—

µs

ns

Note 1

TSYNCHI

TSYNC

TRACL

TFACL

TRACL

TFACL

SYNC Data Output High Time

SYNC Data Output Period

Note 1

20.8

10

—

Note 1

Rise Time, SYNC, SDATA_OUT

Fall Time, SYNC, SDATA_OUT

Rise Time, SYNC, SDATA_OUT

Fall Time, SYNC, SDATA_OUT

25

CLOAD = 50 pF, VDD = 5V

CLOAD = 50 pF, VDD = 3V

—

10

25

TBD

—

TBD

15

TOVDACL Output valid delay from rising

edge of BIT_CLK

Note 1: These parameters are characterized but not tested in manufacturing.

2: These values assume BIT_CLK frequency is 12.288 MHz.

3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 207

dsPIC30F

FIGURE 24-19:

SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx

(CKP = 0)

SP11

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP21

SP20

BIT14 - - - - - -1

MSb

LSb

SDOx

SP31

SP30

SDIx

MSb IN

SP40

LSb IN

BIT14 - - - -1

SP41

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

(2)

Characteristic

Min

Typ

Max

Units

Conditions

(3)

SP10

SP11

SP20

SP21

SP30

SP31

SP35

TscL

TscH

TscF

TscR

TdoF

TdoR

SCKX Output Low Time

TCY / 2

—

10

—

25

30

ns

—

SCKX Output High Time

(4

SCKX Output Fall Time

SCKX Output Rise Time

(4)

—

(4)

SDOX Data Output Fall Time

—

(4)

SDOX Data Output Rise Time

—

TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge

—

SP40

SP41

TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL to SCKX Edge

20

—

ns

—

TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

DS70082C-page 208

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-20:

SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS

SP36

SCKX

(CKP = 0)

SP11

SP10

SP21

SP20

SCK^X

(CKP = 1)

SP35

SP21

SP20

LSb

MSb

BIT14 - - - - - -1

SDO^X

SP40

SP30,SP31

SDIX

MSb IN

BIT14 - - - -1

LSb IN

SP41

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(3)

(2)

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

No.

SP10

SP11

SP20

SP21

SP30

SP31

SP35

TscL

SCKX output low time

TCY / 2

—

10

—

25

30

ns

—

(3)

(4)

TscH

TscF

TscR

TdoF

TdoR

SCKX output high time

SCKX output fall time

(4)

SCKX output rise time

—

(4)

SDOX data output fall time

—

(4)

SDOX data output rise time

—

TscH2doV, SDOX data output valid after

TscL2doV SCKX edge

—

SP36

SP40

SP41

TdoV2sc, SDOX data output setup to

TdoV2scL first SCKX edge

30

20

—

ns

—

TdiV2scH, Setup time of SDIX data input

TdiV2scL to SCKX edge

TscH2diL, Hold time of SDIX data input

TscL2diL

to SCKX edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 209

dsPIC30F

FIGURE 24-21:

SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP52

SP50

SCKX

(CKP =

0)

SP11

SP10

SP21

SP20

SCKX

(CKP =

1)

SP21

SP20

SP35

MSb

LSb

BIT14 - - - - - -1

SDO

X

SP51

SP30,SP31

BIT14 - - - -1

SDIX

MSb IN

SP41

LSb IN

SP40

Note: Refer to Figure 24-3 for load conditions.

TABLE 24-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

TscL

Characteristic

Min

Typ

Max

Units

Conditions

No.

SP10

SCKX Input Low Time

SCKX Input High Time

30

—

10

—

25

30

ns

—

SP11

SP20

SP21

SP30

SP31

SP35

TscH

TscF

TscR

TdoF

TdoR

(3)

SCKX Output Fall Time

(3)

SCKX Output Rise Time

(3)

SDOX Data Output Fall Time

(3)

SDOX Data Output Rise Time

TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge

SP40

SP41

SP50

SP51

TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL to SCKX Edge

20

—

50

ns

—

TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge

TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input

120

10

TssL2scL

TssH2doZ SSX↑ to SDOX Output

(3)

Hi-Impedance

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Assumes 50 pF load on all SPI pins.

DS70082C-page 210

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

(2)

Characteristic

Min

Typ

Max

Units

Conditions

SP52

TscH2ssH SSX after SCK Edge

TscL2ssH

1.5 TCY +40

—

ns

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Assumes 50 pF load on all SPI pins.

FIGURE 24-22:

SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60

SSX

SP52

SP50

SCKX

(CKP = 0)

SP11

SP10

SP21

SP20

SCK^X

(CKP = 1)

SP35

SP21

SP20

LSb

SP52

MSb

BIT14 - - - - - -1

SDO^X

SP30,SP31

SP51

SDIX

MSb IN

SP41

BIT14 - - - -1

LSb IN

SP40

Note: Refer to Figure 24-3 for load conditions.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 211

dsPIC30F

TABLE 24-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

(1)

(2)

Symbol

TscL

Characteristic

Min

Typ

Max

Units

Conditions

No.

SP10

SP11

SP20

SP21

SP30

SP31

SP35

SCKX Input Low Time

SCKX Input High Time

30

—

10

—

25

30

ns

—

TscH

TscF

TscR

TdoF

TdoR

(3)

SCKX Output Fall Time

(3)

SCKX Output Rise Time

(3)

SDOX Data Output Fall Time

(3)

SDOX Data Output Rise Time

TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge

SP40

SP41

SP50

SP51

SP52

SP60

TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL to SCKX Edge

20

—

50

—

50

ns

—

TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge

20

TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input

120

TssL2scL

TssH2doZ SS↑ to SDOX Output

10

1.5 TCY + 40

—

(4)

Hi-Impedance

TscH2ssH SSX↑ after SCKX Edge

TscL2ssH

TssL2doV SDOX Data Output Valid after

SCKX Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

DS70082C-page 212

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

2

I C BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 24-23:

SCL

IM31

IM34

IM30

IM33

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 24-3 for load conditions.

2

I C BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 24-24:

IM20

IM21

IM11

IM10

SCL

IM11

IM26

IM10

IM33

IM25

SDA

In

IM45

IM40

SDA

Out

Note: Refer to Figure 24-3 for load conditions.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 213

dsPIC30F

2

TABLE 24-35: I C BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

(1)

Min

Characteristic

Max

Units

Conditions

IM10

IM11

IM20

IM21

IM25

IM26

IM30

IM31

IM33

IM34

IM40

IM45

IM50

TLO:SCL Clock Low Time 100 kHz mode TCY / 2 (BRG + 1)

—

ms

ns

—

400 kHz mode TCY / 2 (BRG + 1)

(2)

1 MHz mode

TCY / 2 (BRG + 1)

—

THI:SCL Clock High Time 100 kHz mode TCY / 2 (BRG + 1)

—

400 kHz mode TCY / 2 (BRG + 1)

—

(2)

1 MHz mode

100 kHz mode

400 kHz mode

TCY / 2 (BRG + 1)

—

TF:SCL

SDA and SCL

Fall Time

—

300

100

1000

300

—

CB is specified to be

from 10 to 400 pF

20 + 0.1 CB

ns

(2)

1 MHz mode

—

ns

TR:SCL

SDA and SCL

Rise Time

100 kHz mode

400 kHz mode

—

ns

CB is specified to be

from 10 to 400 pF

20 + 0.1 CB

ns

(2)

1 MHz mode

—

250

100

TBD

0

ns

TSU:DAT Data Input

100 kHz mode

400 kHz mode

ns

—

Setup Time

—

ns

(2)

1 MHz mode

—

ns

THD:DAT Data Input

100 kHz mode

400 kHz mode

—

ns

—

Hold Time

0

0.9

—

ms

ns

(2)

1 MHz mode

TBD

TSU:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1)

—

ms

ns

Only relevant for

repeated Start

condition

Setup Time

400 kHz mode TCY / 2 (BRG + 1)

—

(2)

1 MHz mode

TCY / 2 (BRG + 1)

—

THD:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1)

—

After this period the

first clock pulse is

generated

Hold Time

400 kHz mode TCY / 2 (BRG + 1)

—

(2)

1 MHz mode

TCY / 2 (BRG + 1)

—

TSU:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1)

—

Setup Time

400 kHz mode TCY / 2 (BRG + 1)

—

(2)

1 MHz mode

TCY / 2 (BRG + 1)

—

THD:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1)

—

Hold Time

400 kHz mode TCY / 2 (BRG + 1)

—

ns

(2)

1 MHz mode

100 kHz mode

400 kHz mode

TCY / 2 (BRG + 1)

—

ns

TAA:SCL Output Valid

—

3500

1000

—

ns

—

From Clock

ns

(2)

1 MHz mode

—

ns

TBF:SDA Bus Free Time 100 kHz mode

4.7

1.3

TBD

—

ms

pF

Time the bus must be

free before a new

400 kHz mode

—

transmission can start

(2)

1 MHz mode

—

CB

Bus Capacitive Loading

400

2 2

Note 1: BRG is the value of the I C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ (I C)”

in the dsPIC30F Family Reference Manual.

2

2: Maximum pin capacitance = 10 pF for all I C pins (for 1 MHz mode only).

DS70082C-page 214

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

2

I C BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 24-25:

SCL

IS34

IS31

IS30

IS33

SDA

Stop

Condition

Start

Condition

2

I C BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 24-26:

IS20

IS21

IS11

IS10

SCL

IS30

IS26

IS31

IS33

IS25

SDA

In

IS45

IS40

SDA

Out

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 215

dsPIC30F

2

TABLE 24-36: I C BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

Characteristic

Min

Max Units

Conditions

No.

IS10

TLO:SCL Clock Low Time 100 kHz mode

4.7

—

µs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

Device must operate at a

minimum of 10 MHz.

(1)

1 MHz mode

0.5

4.0

—

µs

—

IS11

THI:SCL

Clock High Time 100 kHz mode

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

µs

Device must operate at a

minimum of 10 MHz

(1)

1 MHz mode

0.5

—

300

100

1000

300

—

µs

ns

µs

ns

µs

pF

—

IS20

IS21

IS25

IS26

IS30

IS31

IS33

IS34

IS40

IS45

IS50

TF:SCL

SDA and SCL

Fall Time

100 kHz mode

400 kHz mode

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

(1)

1 MHz mode

—

TR:SCL

SDA and SCL

Rise Time

100 kHz mode

400 kHz mode

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

—

(1)

1 MHz mode

TSU:DAT Data Input

100 kHz mode

400 kHz mode

250

100

0

—

Setup Time

—

(1)

1 MHz mode

—

THD:DAT Data Input

100 kHz mode

400 kHz mode

—

Hold Time

0

0.9

0.3

—

(1)

1 MHz mode

0

TSU:STA Start Condition

100 kHz mode

400 kHz mode

4.7

0.6

0.25

4.0

0.6

0.25

4.7

0.6

4000

600

250

0

Only relevant for repeated

Start condition

Setup Time

—

(1)

1 MHz mode

—

THD:STA Start Condition

100 kHz mode

400 kHz mode

—

After this period the first

clock pulse is generated

Hold Time

—

(1)

1 MHz mode

—

TSU:STO Stop Condition

100 kHz mode

400 kHz mode

—

Setup Time

—

(1)

1 MHz mode

—

THD:STO Stop Condition

100 kHz mode

400 kHz mode

—

Hold Time

—

(1)

1 MHz mode

TAA:SCL

Output Valid From 100 kHz mode

3500

1000

350

—

Clock

400 kHz mode

0

(1)

1 MHz mode

0

TBF:SDA Bus Free Time

100 kHz mode

400 kHz mode

4.7

1.3

0.5

—

Time the bus must be free

before a new transmission

can start

—

(1)

1 MHz mode

—

CB

Bus Capacitive

Loading

400

—

2

Note 1: Maximum pin capacitance = 10 pF for all I C pins (for 1 MHz mode only).

DS70082C-page 216

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-27:

CAN MODULE I/O TIMING CHARACTERISTICS

CXTX Pin

New Value

Old Value

(output)

CA10 CA11

CXRX Pin

(input)

CA20

TABLE 24-37: CAN MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

(1)

(2)

Characteristic

Min

Typ

Max

Units

Conditions

TioF

TioR

Tcwf

CA10

CA11

CA20

Port Output Fall Time

Port Output Rise Time

—

10

25

ns

—

Pulse Width to Trigger

CAN Wakeup Filter

500

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 217

dsPIC30F

TABLE 24-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01

AD02

AVDD

Module VDD Supply

Greater of

VDD - 0.3

or 2.7

Lesser of

VDD + 0.3

or 5.5

V

—

AVSS

Module VSS Supply

Vss - 0.3

Reference Inputs

AVss+2.7

VSS + 0.3

AD05

AD06

AD07

AD08

VREFH

VREFL

VREF

IREF

Reference Voltage High

Reference Voltage Low

AVDD

V

—

AVss

AVDD - 2.7

AVDD + 0.3

Absolute Reference Voltage AVss - 0.3

Current Drain

—

200

.001

300

3

µA A/D operating

µA A/D off

Analog Input

VREFL

AD10

AD11

AD12

VINH-VINL Full-Scale Input Span

VREFH

AVDD + 0.3

0.244

V

—

VIN

Absolute Input Voltage

Leakage Current

AVSS - 0.3

—

0.001

µA VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

Source Impedance =

10 kW

AD13

—

Leakage Current

—

0.001

0.244

µA VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Source Impedance =

10 kW

AD15

AD16

AD17

RSS

Switch Resistance

—

5K

—

Ω

pF

Ω

—

CSAMPLE Sample Capacitor

RIN Recommended Impedance

2.5

10K

Of Analog Voltage Source

DC Accuracy

10 data bits

0.5

AD20 Nr

AD21 INL

Resolution

bits

—

Integral Nonlinearity

—

< 1

TBD

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD21A INL

AD22 DNL

AD22A DNL

Integral Nonlinearity

Differential Nonlinearity

Gain Error

0.5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

0.5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD23

GERR

0.75

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD23A GERR

Gain Error

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

DS70082C-page 218

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic

Offset Error

Min.

Typ

Max.

Units

Conditions

AD24

EOFF

—

0.75

TBD

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V

AD24A EOFF

Offset Error

Monotonicity

—

0.75

TBD

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

(2)

AD25

—

dB

Guaranteed

AD26 CMRR

AD27 PSRR

Common-Mode Rejection

TBD

—

Power Supply Rejection

Ratio

AD28 CTLK

Channel to Channel

Crosstalk

—

TBD

—

dB

—

Dynamic Performance

AD30 THD

Total Harmonic Distortion

—

TBD

—

dB

—

AD31 SINAD

Signal to Noise and

Distortion

AD32 SFDR

Spurious Free Dynamic

Range

—

TBD

—

dB

—

AD33

FNYQ

Input Signal Bandwidth

Effective Number of Bits

—

250

kHz

bits

—

AD34 ENOB

TBD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 219

dsPIC30F

FIGURE 24-28:

HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS

(CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)

AD50

ADCLK

Instruction

Execution

BSF SAMP

BCF SAMP

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

AD61

AD60

TSAMP

AD55

DONE

ADIF

ADRES(0)

ADRES(1)

1

2

3

4

5

6

8

9

5

6

8

9

- Software sets ADCON. SAMP to start sampling.

- Sampling starts after discharge period.

1

2

TSAMP is described in the dsPIC30F MCU Family Reference Manual, Section 17.

- Software clears ADCON. SAMP to start conversion.

- Sampling ends, conversion sequence starts.

- Convert bit 9.

3

4

5

6

8

9

- Convert bit 8.

- Convert bit 0.

- One T^ADfor end of conversion.

DS70082C-page 220

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-29:

HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS

(CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)

AD50

ADCLK

Instruction

Execution

BSF ADON

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

TSAMP

AD55

TCONV

DONE

ADIF

ADRES(0)

ADRES(1)

1

2

3

4

5

6

7

3

4

5

6

8

3

4

- Software sets ADCON. ADON to start AD operation.

- Convert bit 0.

1

2

5

- Sampling starts after discharge period.

TSAMP is described in the dsPIC30F

Family Reference Manual, Section 17.

- One TAD for end of conversion.

6

7

8

- Begin conversion of next channel

- Sample for time specified by SAMC.

TSAMP is described in the dsPIC30F

Family Reference Manual, Section 17.

- Convert bit 9.

- Convert bit 8.

3

4

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 221

dsPIC30F

TABLE 24-39: HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50 TAD

A/D Clock Period

154

833

ns

VDD = 5V (Note 1)

VDD = 2.7V (Note 1)

AD51 tRC

A/D Internal RC Oscillator Period

Conversion Rate

13 TAD

700

900

1100

—

AD55 tCONV

AD56 FCNV

Conversion Time

ns

—

Throughput Rate

500

100

ksps VDD = VREF = 5V

ksps VDD = VREF = 2.7V

Timing Parameters

AD60 tPCS

AD61 tPSS

Conversion Start from Sample

Trigger

—

0.5 TAD

—

TAD

1.5 TAD

TBD

ns

µs

—

Sample Start from Setting

Sample (SAMP) Bit

—

AD62

t

Conversion Completion to

CSS

Sample Start (ASAM = 1)

AD63 tDPU

Time to Stabilize Analog Stage

from A/D Off to A/D On

—

TBD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

DS70082C-page 222

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

TABLE 24-40: 12-BIT LOW-SPEED A/D MODULE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

Module VDD Supply

Greater of

VDD - 0.3

or 2.7

—

Lesser of

VDD + 0.3

or 5.5

V

—

AD02 AVSS

Module VSS Supply

VSS - 0.3

—

VSS + 0.3

Reference Inputs

AD05

AD06

AD07

VREFH

VREFL

VREF

Reference Voltage High

Reference Voltage Low

AVSS + 2.7

AVSS

—

AVDD

V

—

AVDD - 2.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS - 0.3

AD08

IREF

Current Drain

—

200

300

3

µA

A/D operating

.001

A/D off

Analog Input

VREFL

AD10 VINH-VINL Full-Scale Input Span

VREFH

AVDD + 0.3

0.610

V

See Note

AD11

AD12

VIN

Absolute Input Voltage

Leakage Current

AVSS - 0.3

—

0.001

µA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Source Impedance =

1 kW

AD13

—

Leakage Current

—

0.001

0.610

µA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Source Impedance =

1 kW

AD15

RSS

Switch Resistance

—

5K

18

—

Ω

pF

W

—

AD16 CSAMPLE Sample Capacitor

AD17

RIN

Recommended Impedance

of Analog Voltage Source

1K

DC Accuracy

12 data bits

0.75

AD20 Nr

Resolution

bits

AD21 INL

Integral Nonlinearity

—

TBD

1

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD21A INL

AD22 DNL

AD22A DNL

Integral Nonlinearity

Differential Nonlinearity

Gain Error

0.75

0.5

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

0.5

1

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD23

GERR

1.25

TBD

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD23A GERR

Gain Error

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 223

dsPIC30F

TABLE 24-40: 12-BIT LOW-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

Characteristic

Offset Error

Min.

Typ

Max.

Units

Conditions

No.

AD24

EOFF

—

1.25

TBD

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD24A EOFF

Offset Error

Monotonicity

—

1.25

TBD

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

(1)

AD25

—

dB

Guaranteed

AD26 CMRR

AD27 PSRR

Common-Mode Rejection

TBD

—

Power Supply Rejection

Ratio

—

AD28 CTLK

Channel to Channel

Crosstalk

—

TBD

—

dB

—

Dynamic Performance

AD30 THD

Total Harmonic Distortion

—

dB

—

AD31 SINAD

Signal to Noise and

Distortion

TBD

AD32 SFDR

Spurious Free Dynamic

Range

—

TBD

—

dB

—

AD33

FNYQ

Input Signal Bandwidth

Effective Number of Bits

—

50

kHz

bits

—

AD34 ENOB

TBD

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

DS70082C-page 224

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

FIGURE 24-30:

LOW-SPEED A/D CONVERSION TIMING CHARACTERISTICS

(ASAM = 0, SSRC = 000)

AD50

ADCLK

Instruction

BSF SAMP

BCF SAMP

Execution

SAMP

ch0_dischrg

ch0_samp

eoc

AD61

AD60

TSAMP

AD55

DONE

ADIF

ADRES(0)

1

2

3

4

5

6

7

8

9

- Software sets ADCON. SAMP to start sampling.

- Sampling starts after discharge period.

1

2

TSAMP is described in the dsPIC30F Family Reference Manual, Section 18.

- Software clears ADCON. SAMP to start conversion.

- Sampling ends, conversion sequence starts.

- Convert bit 11.

3

4

5

6

7

8

9

- Convert bit 10.

- Convert bit 1.

- Convert bit 0.

- One T^ADfor end of conversion.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 225

dsPIC30F

TABLE 24-41: LOW-SPEED A/D CONVERSION TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50

AD51

TAD

tRC

A/D Clock Period

667

1.4

—

ns

VDD = 5V (Note 1)

µs

VDD = 2.7V (Note 1)

A/D Internal RC Oscillator Period

1.2

1.5

1.8

µs

—

Conversion Rate

AD55

AD56

tCONV

FCNV

Conversion Time

Throughput Rate

—

15 TAD

ns

—

100

50

ksps

VDD = VREF = 5V

VDD = VREF = 2.7V

Timing Parameters

AD60

AD61

AD62

AD63

tPCS

tPSS

tCSS

tDPU

Conversion Start from Sample

Trigger

—

0.5 TAD

—

TAD

1.5 TAD

TBD

ns

µs

—

Sample Start from Setting

Sample (SAMP) Bit

Conversion Completion to

Sample Start (ASAM = 1)

Time to Stabilize Analog Stage

from A/D Off to A/D On

—

TBD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

DS70082C-page 226

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

25.0 PACKAGING INFORMATION

25.1 Package Marking Information

28-Lead PDIP (Skinny DIP)

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

dsPIC30F3010-I/SP

0348017

28-Lead SOIC

Example

XXXXXXXXXXXXXXXXXXXX

dsPIC30F4012-I/SO

YYWWNNN

0348017

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

dsPIC30F4011-I/P

YYWWNNN

0348017

Legend: XX...X Customer specific information*

Y

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

YY

WW

NNN

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard device marking consists of Microchip part number, year code, week code, and traceability

code. For device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 227

dsPIC30F

25.1 Package Marking Information (Continued)

44-Lead TQFP

Example

dsPIC30F

XXXXXXXXXX

YYWWNNN

4011-I/PT

0348017

64-Lead TQFP

Example

XXXXXXXXXX

YYWWNNN

dsPIC30F

5015-I/PT

0336017

64-Lead TQFP

Example

XXXXXXXXXXXX

dsPIC30F

5015-I/PT

YYWWNNN

0336017

80-Lead TQFP

Example

XXXXXXXXXXXX

YYWWNNN

dsPIC30F6010

-I/PT

0336017

DS70082C-page 228

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

B1

β

A1

eB

p

B

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

28

.100

.150

.130

2.54

3.81

3.30

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A

A2

A1

E

.140

.160

3.56

4.06

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

.135

3.18

0.38

7.62

6.99

34.16

3.18

0.20

1.02

3.43

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

E1

D

34.67

3.30

Tip to Seating Plane

Lead Thickness

L

c

0.29

Upper Lead Width

B1

B

1.33

Lower Lead Width

0.41

8.13

5

0.48

8.89

10

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

5

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 229

dsPIC30F

28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E

E1

p

D

B

2

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

28

.050

.099

.091

.008

.407

.295

.704

.020

.033

4

1.27

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

Overall Height

A

.093

.104

2.36

2.64

Molded Package Thickness

Standoff

A2

A1

E

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle Top

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

DS70082C-page 230

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

Top to Seating Plane

8

.100

.155

.130

2.54

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 231

dsPIC30F

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

φ

β

A1

A2

L

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

44

.031

11

0.80

11

Pins per Side

Overall Height

n1

A

.039

.037

.002

.018

.043

.039

.004

.024

.039

3.5

.047

1.00

0.95

1.10

1.00

0.10

0.60

1.20

Molded Package Thickness

Standoff

A2

A1

L

.041

.006

.030

1.05

0.15

0.75

§

0.05

0.45

1.00

0

Foot Length

(F)

φ

Footprint (Reference)

Foot Angle

0

.463

.390

.004

.012

.025

5

7

.482

.398

.008

.017

.045

15

3.5

12.00

10.00

0.15

0.38

0.89

10

7

12.25

10.10

0.20

0.44

1.14

15

Overall Width

E

D

.472

.394

.006

.015

.035

10

11.75

9.90

0.09

0.30

0.64

5

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

Lead Width

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

DS70082C-page 232

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

A2

L

φ

β

A1

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

64

MAX

n

p

Number of Pins

Pitch

64

.020

16

0.50

16

Pins per Side

Overall Height

n1

A

.039

.043

.039

.006

.024

.039

3.5

.047

1.00

0.95

1.10

1.00

0.15

0.60

1.00

3.5

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.041

.010

.030

1.05

0.25

0.75

§

0.05

0.45

Foot Length

(F)

φ

Footprint (Reference)

Foot Angle

0

.463

.390

.005

.007

.025

5

7

.482

.398

.009

.011

.045

15

0

11.75

9.90

0.13

0.17

0.64

5

7

12.25

10.10

0.23

0.27

1.14

15

Overall Width

E

D

.472

.394

.007

.009

.035

10

12.00

10.00

0.18

0.22

0.89

10

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

Lead Width

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-085

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 233

dsPIC30F

64-Lead Plastic Thin Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

A2

L

φ

β

A1

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

64

MAX

n

p

Number of Pins

Pitch

64

.032

16

0.80

16

Pins per Side

Overall Height

n1

A

.047

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.039

.041

.006

.030

0.95

0.05

0.45

1.00

1.05

0.15

0.75

§

.002

.018

Foot Length

.024

.039

0.60

1.00

(F)

φ

Footprint (Reference)

Foot Angle

0

7

0

7

Overall Width

E

D

.630

.551

16.00

14.00

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

.004

.019

.008

.018

0.09

0.30

0.20

0.45

Lead Width

B

CH

α

.013

0.32

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

11

13

11

13

β

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-085

DS70082C-page 234

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

B

1

n

°

CH x 45

A

α

c

A2

φ

β

L

A1

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

80

MAX

n

p

Number of Pins

Pitch

80

.020

20

0.50

20

Pins per Side

Overall Height

n1

A

.039

.037

.002

.018

.043

.039

.004

.024

.039

3.5

.047

1.00

0.95

1.10

1.00

0.10

0.60

1.00

3.5

1.20

Molded Package Thickness

Standoff

A2

A1

L

.041

.006

.030

1.05

0.15

0.75

§

0.05

0.45

Foot Length

(F)

φ

Footprint (Reference)

Foot Angle

0

.541

.463

.004

.007

.025

5

7

.561

.482

.008

.011

.045

15

0

13.75

11.75

0.09

0.17

0.64

5

7

14.25

12.25

0.20

0.27

1.14

15

Overall Width

E

D

.551

.472

.006

.009

.035

10

14.00

12.00

0.15

0.22

0.89

10

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

Lead Width

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-092

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 235

dsPIC30F

80-Lead Plastic Thin Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

B

1

n

°

CH x 45

A

α

c

A2

φ

β

L

A1

(F)

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

80

MAX

n

p

Number of Pins

Pitch

80

.026

20

0.65

20

Pins per Side

Overall Height

n1

A

.047

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.039

.041

.006

.030

0.95

0.05

0.45

1.00

1.05

0.15

0.75

§

Foot Length

.024

.039

0.60

1.00

(F)

φ

Footprint (Reference)

Foot Angle

0

7

0

7

Overall Width

E

D

.630

.551

16.00

14.00

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

.

.004

.009

.008

.015

0.09

0.22

0.20

0.38

Lead Width

B

CH

α

.013

0.32

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

11

13

11

13

β

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-092

DS70082C-page 236

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

INDEX

Block Diagrams

Numerics

10-bit High Speed A/D Functional ............................ 142

16-bit Timer1 Module.................................................. 71

16-bit Timer4 .............................................................. 82

16-bit Timer5 .............................................................. 82

32-bit Timer4/5 ........................................................... 81

8-Output PWM Module............................................. 100

CAN Buffers and Protocol Engine ............................ 130

Dedicated Port Structure ............................................ 65

DSP Engine................................................................ 25

dsPIC30F6010............................................................ 12

External Power-on Reset Circuit .............................. 156

10-bit High Speed A/D

Aborting a Conversion .............................................. 144

ADCHS ..................................................................... 141

ADCON1................................................................... 141

ADCON2................................................................... 141

ADCON3................................................................... 141

ADCSSL.................................................................... 141

ADPCFG................................................................... 141

Analog Input Model................................................... 145

Configuring Analog Port Pins.................................... 147

Connection Considerations....................................... 147

Conversion Operation............................................... 143

Effects of a Reset...................................................... 146

Operation During CPU Idle Mode ............................. 146

Operation During CPU Sleep Mode.......................... 146

Output Formats......................................................... 146

Power-down Modes .................................................. 146

Programming the Start of Conversion Trigger .......... 144

Register Map............................................................. 148

Result Buffer ............................................................. 143

Sampling Requirements............................................ 145

Selecting the Conversion Clock................................ 144

Selecting the Conversion Sequence......................... 143

T^ADvs. Device Operating Frequencies Table........... 144

10-bit High Speed Analog-to-Digital Converter. See A/D

16-bit Integer and Fractional Modes Example .................... 26

16-bit Up/Down Position Counter Mode.............................. 94

Count Direction Status................................................ 94

Error Checking............................................................ 94

6-Ouput PWM

2

I C ............................................................................ 114

Input Capture Mode.................................................... 85

Oscillator System...................................................... 150

Output Compare Mode............................................... 89

Quadrature Encoder Interface.................................... 93

Reset System ........................................................... 154

Shared Port Structure................................................. 67

SPI............................................................................ 110

SPI Master/Slave Connection................................... 110

UART Receiver......................................................... 122

UART Transmitter..................................................... 121

BOR Characteristics ......................................................... 188

BOR. See Brown-out Reset

Brown-out Reset

Characteristics.......................................................... 187

Timing Requirements ............................................... 194

Brown-out Reset (BOR).................................................... 149

C

C Compilers

Register Map............................................................. 108

6-Ouput PWM vs. 8-Output PWM

MPLAB C17.............................................................. 170

MPLAB C18.............................................................. 170

MPLAB C30.............................................................. 170

CAN Module ..................................................................... 129

CAN1 Register Map.................................................. 136

CAN2 Register Map.................................................. 138

I/O Timing Characteristics ........................................ 215

I/O Timing Requirements.......................................... 215

Overview................................................................... 129

Center Aligned PWM ........................................................ 103

CLKOUT and I/O Timing

Feature Summary ....................................................... 99

8-Output PWM

Register Map............................................................. 108

A

A/D.................................................................................... 141

AC Characteristics ............................................................ 189

Load Conditions........................................................ 189

AC Temperature and Voltage Specifications.................... 189

Address Generator Units .................................................... 41

Alternate 16-bit Timer/Counter............................................ 95

Alternate Vector Table ........................................................ 53

Assembler

Characteristics.......................................................... 192

Requirements ........................................................... 192

Code Examples

Data EEPROM Block Erase ....................................... 62

Data EEPROM Block Write ........................................ 64

Data EEPROM Read.................................................. 61

Data EEPROM Word Erase ....................................... 62

Data EEPROM Word Write ........................................ 63

Erasing a Row of Program Memory ........................... 57

Initiating a Programming Sequence ........................... 59

Loading Write Latches................................................ 58

Code Protection................................................................ 149

Complementary PWM Operation...................................... 104

Configuring Analog Port Pins.............................................. 67

Control Registers................................................................ 56

NVMADR.................................................................... 56

NVMADRU ................................................................. 56

NVMCON.................................................................... 56

NVMKEY .................................................................... 56

MPASM Assembler................................................... 169

Automatic Clock Stretch.................................................... 116

During 10-bit Addressing (STREN = 1)..................... 116

During 7-bit Addressing (STREN = 1)....................... 116

Receive Mode........................................................... 116

Transmit Mode.......................................................... 116

B

Bandgap Start-up Time

Requirements............................................................ 194

Timing Characteristics .............................................. 194

Barrel Shifter....................................................................... 28

Bit-Reversed Addressing .................................................... 47

Example...................................................................... 47

Implementation ........................................................... 47

Modifier Values (table)................................................ 48

Sequence Table (16-Entry)......................................... 48

 2003 Microchip Technology Inc.

Advance Information

DS70082C-page 237

dsPIC30F

Core Architecture

Device Configuration Registers ........................................ 159

FBORPOR................................................................ 159

FGS .......................................................................... 159

FOSC........................................................................ 159

FWDT ....................................................................... 159

Device Overview................................................................. 11

Divide Support .................................................................... 23

DSP Engine ........................................................................ 24

Multiplier ..................................................................... 26

Dual Output Compare Match Mode.................................... 90

Continuous Pulse Mode.............................................. 90

Single Pulse Mode...................................................... 90

Overview.....................................................................17

Core Register Map..............................................................38

D

Data Accumulators and Adder/ .....................................27, 28

Data Address Space ...........................................................33

Access RAM ...............................................................35

Alignment....................................................................34

Alignment (Figure) ......................................................34

Effect of Invalid Memory Accesses.............................34

MCU and DSP (MAC Class) Instructions Example.....37

Memory Map...............................................................34

Memory Map Example................................................36

Spaces........................................................................33

Width...........................................................................34

Data EEPROM Memory......................................................61

Erasing........................................................................62

Erasing, Block.............................................................62

Erasing, Word .............................................................62

Protection Against Spurious Write ..............................64

Reading.......................................................................61

Write Verify .................................................................64

Writing.........................................................................63

Writing, Block..............................................................64

Writing, Word ..............................................................63

Data Space Organization....................................................41

DC and AC Characteristics Graphs and Tables................225

DC Characteristics ............................................................176

BOR ..........................................................................188

Brown-out Reset .......................................................187

I/O Pin Input Specifications.......................................185

I/O Pin Output Specifications....................................186

Idle Current (I^IDLE) ....................................................180

Low-Voltage Detect...................................................186

LVDL.........................................................................187

Operating Current (I^DD).............................................177

Power-Down Current (I^PD)........................................183

Program and EEPROM.............................................188

Temperature and Voltage Specifications..................176

DCI Module

E

Edge Aligned PWM........................................................... 103

EEPROM Memory Characteristics ................................... 188

Electrical Characteristics .................................................. 175

AC............................................................................. 189

DC ............................................................................ 176

Equations

A/D Conversion Clock............................................... 144

A/D Sampling Time................................................... 145

Baud Rate......................................................... 125, 135

PWM Period.............................................................. 103

PWM Resolution....................................................... 103

Serial Clock Rate...................................................... 118

Errata.................................................................................... 9

Evaluation and Programming Tools.................................. 173

Exception Processing ......................................................... 49

Interrupt Priority.......................................................... 50

Natural Order Priority (table)....................................... 50

Exception Sequence

Trap Sources .............................................................. 51

External Clock Timing Characteristics

Type A, B and C Timer............................................. 195

External Clock Timing Requirements ............................... 190

Type A Timer............................................................ 195

Type B Timer............................................................ 196

Type C Timer............................................................ 196

External Interrupt Requests................................................ 53

F

Timing Characteristics

Fast Context Saving ........................................................... 53

Firmware Instructions ....................................................... 161

Flash Program Memory ...................................................... 55

In-Circuit Serial Programming (ICSP)......................... 55

Run Time Self-Programming (RTSP) ......................... 55

Table Instruction Operation Summary........................ 55

AC-Link Mode ...................................................205

2

Multichannel, I S Modes...................................203

Timing Requirements

AC-Link Mode ...................................................205

2

Multichannel, I S Modes...................................204

Dead-Time Generators .....................................................104

Assignment ...............................................................105

Ranges......................................................................105

Selection Bits ............................................................105

Demonstration Boards

I

I/O Pin Specifications

Input.......................................................................... 185

Output....................................................................... 186

I/O Ports.............................................................................. 65

Parallel I/O (PIO) ........................................................ 65

PICDEM 1.................................................................172

PICDEM 17...............................................................172

PICDEM 18R PIC18C601/801..................................173

PICDEM 2 Plus.........................................................172

PICDEM 3 PIC16C92X.............................................172

PICDEM 4.................................................................172

PICDEM LIN PIC16C43X .........................................173

PICDEM USB PIC16C7X5........................................173

PICDEM.net Internet/Ethernet ..................................172

Development Support .......................................................169

Device Configuration

2

I C..................................................................................... 113

2

I C 10-bit Slave Mode Operation...................................... 115

Reception ................................................................. 115

Transmission ............................................................ 115

2

I C 7-bit Slave Mode Operation........................................ 115

2

I C 7-bit Slave Mode Operation

Reception ................................................................. 115

Transmission ............................................................ 115

2

I C Master Mode

Register Map.............................................................160

Baud Rate Generator ............................................... 117

Clock Arbitration ....................................................... 118

DS70082C-page 238

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 2003 Microchip Technology Inc.

dsPIC30F

Multi-Master Communication, Bus Collision

Pipeline - 2-Word, 2-Cycle DO, DOW (Figure)........... 22

Pipeline - 2-Word, 2-Cycle GOTO, CALL (Figure) ..... 21

Instruction Set................................................................... 161

Instruction Set Overview................................................... 163

Instruction Stalls ................................................................. 43

Introduction................................................................. 43

Raw Dependency Detection....................................... 43

and Bus Arbitration ........................................... 118

Reception.................................................................. 117

Transmission............................................................. 117

2

I C Module........................................................................ 113

Addresses................................................................. 115

Bus Data Timing Characteristics

2

Inter-Integrated Circuit. See I C

Master Mode..................................................... 211

Slave Mode....................................................... 213

Bus Data Timing Requirements

Internal Clock Timing Examples ....................................... 191

Interrupt Controller

Master Mode..................................................... 212

Slave Mode....................................................... 214

Bus Start/Stop Bits Timing Characteristics

Register Map .............................................................. 54

Interrupt Priority

Traps .......................................................................... 51

Interrupt Sequence............................................................. 52

Interrupt Stack Frame................................................. 53

Master Mode..................................................... 211

Slave Mode....................................................... 213

General Call Address Support .................................. 117

Interrupts................................................................... 116

IPMI Support............................................................. 117

Master Operation ...................................................... 117

Master Support ......................................................... 117

Operating Function Description ................................ 113

Operation During CPU Sleep and Idle Modes .......... 118

Pin Configuration ...................................................... 113

Register Map............................................................. 119

Registers................................................................... 113

Slope Control ............................................................ 117

Software Controlled Clock Stretching (STREN = 1).. 116

Various Modes.......................................................... 113

L

Load Conditions................................................................ 189

Low-Voltage Detect Characteristics.................................. 186

LVDL Characteristics........................................................ 187

M

Memory Organization ......................................................... 29

Modulo Addressing............................................................. 44

Applicability................................................................. 46

Decrementing Buffer Operation Example................... 46

Incrementing Buffer Operation Example .................... 45

Restrictions................................................................. 46

Start and End Address ............................................... 44

W Address Register Selection.................................... 45

Motor Control PWM Module ............................................... 99

Fault Timing Characteristics..................................... 200

Timing Characteristics.............................................. 200

Timing Requirements ............................................... 200

MPLAB ASM30 Assembler, Linker, Librarian................... 170

MPLAB ICD 2 In-Circuit Debugger ................................... 171

MPLAB ICE 2000 High Performance Universal

2

I C Module

Programmer’s Model................................................. 113

Idle Current (I^IDLE) ............................................................ 180

In-Circuit Serial Programming (ICSP)............................... 149

Independent PWM Output ................................................ 105

Initialization Condition for RCON Register Case 1 ........... 157

Initialization Condition for RCON Register Case 2 ........... 157

Initialization Condition for RCON Register, Case 1 .......... 157

Input Capture (CAPX) Timing Characteristics .................. 198

Input Capture Interrupts...................................................... 86

Register Map............................................................... 87

Input Capture Module ......................................................... 85

In CPU Sleep Mode .................................................... 86

Simple Capture Event Mode....................................... 85

Input Capture Timing Requirements................................. 198

Input Change Notification Module....................................... 70

Register Map (bit 15-8) ............................................... 70

Register Map (bits 15-8) ............................................. 70

Register Map (bits 7-0) ............................................... 70

Input Characteristics

In-Circuit Emulator.................................................... 171

MPLAB ICE 4000 High Performance Universal

In-Circuit Emulator.................................................... 171

MPLAB Integrated Development Environment Software.. 169

MPLINK Object Linker/MPLIB Object Librarian................ 170

O

OC/PWM Module Timing Characteristics ......................... 199

Operating Current (I^DD) .................................................... 177

Operating Frequency vs Voltage

dsPIC30Fxxxx-20 (Extended)................................... 176

Oscillator Configurations................................................... 151

Fail-Safe Clock Monitor ............................................ 153

Fast RC (FRC).......................................................... 152

Initial Clock Source Selection................................... 151

Low Power RC (LPRC)............................................. 152

LP Oscillator Control................................................. 152

Phase Locked Loop (PLL)........................................ 152

Start-up Timer (OST)................................................ 152

Oscillator Operating Modes Table .................................... 149

Oscillator Selection........................................................... 149

Oscillator Start-up Timer

QEA/QEB.................................................................. 201

Instruction Addressing Modes............................................. 41

File Register Instructions ............................................ 42

Fundamental Modes Supported.................................. 41

MAC Instructions......................................................... 42

MCU Instructions ........................................................ 42

Move and Accumulator Instructions............................ 42

Other Instructions........................................................ 42

Instruction Flow................................................................... 20

Pipeline - 1-Word, 1-Cycle (Figure) ............................ 20

Pipeline - 1-Word, 2-Cycle (Figure) ............................ 20

Pipeline - 1-Word, 2-Cycle MOV.D Operations

Timing Characteristics.............................................. 193

Timing Requirements ............................................... 194

Output Compare Interrupts................................................. 91

Output Compare Mode

(Figure) ............................................................... 21

Pipeline - 1-Word, 2-Cycle Table Operations

(Figure) ............................................................... 21

Pipeline - 1-Word, 2-Cycle with Instruction Stall

Register Map .............................................................. 92

(Figure) ............................................................... 22

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DS70082C-page 239

dsPIC30F

Output Compare Module.....................................................89

Timing Characteristics ..............................................198

Timing Requirements................................................198

Output Compare Operation During CPU Idle Mode............91

Output Compare Sleep Mode Operation.............................91

Programming Operations.................................................... 56

Algorithm for Program Flash....................................... 56

Erasing a Row of Program Memory............................ 57

Initiating the Programming Sequence......................... 59

Loading Write Latches................................................ 58

Programming, Device Instructions.................................... 161

Protection Against Accidental Writes to OSCCON........... 153

PWM Duty Cycle Comparison Units................................. 104

Duty Cycle Register Buffers...................................... 104

PWM FAULT Pins............................................................. 106

Enable Bits ............................................................... 106

FAULTStates ............................................................ 106

Modes....................................................................... 107

Cycle-by-Cycle ................................................. 107

P

Packaging Information ......................................................227

Marking .....................................................................227

Peripheral Module Display (PMD) Registers.....................159

PICkit 1 Flash Starter Kit...................................................173

PICSTART Plus Development Programmer .....................171

Pinout Descriptions .............................................................13

PLL Clock Timing Specifications.......................................191

POR. See Power-on Reset

Latched............................................................. 107

PORTA

Priority ...................................................................... 107

PWM Operation During CPU Idle Mode ........................... 107

PWM Operation During CPU Sleep Mode........................ 107

PWM Output and Polarity Control..................................... 106

Output Pin Control .................................................... 106

PWM Output Override ...................................................... 106

Complementary Output Mode................................... 106

Synchronization ........................................................ 106

PWM Period...................................................................... 103

PWM Special Event Trigger.............................................. 107

Postscaler................................................................. 107

PWM Time-Base............................................................... 102

Continuous Up/Down Counting Modes..................... 102

Double Update Mode................................................ 102

Free Running Mode.................................................. 102

Postscaler................................................................. 103

Prescaler .................................................................. 103

Single Shot Mode ..................................................... 102

PWM Update Lockout....................................................... 107

Register Map...............................................................66

PORTB

Register Map...............................................................68

PORTC

Register Map...............................................................68

PORTD

Register Map...............................................................68

PORTE

Register Map...............................................................68

PORTF

Register Map...............................................................68

PORTG

Register Map...............................................................69

Position Measurement Mode ..............................................94

Power Saving Modes ........................................................158

Idle ............................................................................159

Sleep.........................................................................158

Power Saving Modes (Sleep and Idle)..............................149

Power-Down Current (I^PD) ................................................183

Power-on Reset (POR) .....................................................149

Oscillator Start-up Timer (OST) ................................149

Power-up Timer (PWRT) ..........................................149

Power-up Timer

Q

QEA/QEB Input Characteristics........................................ 201

QEI Module

External Clock Timing Requirements ....................... 197

Index Pulse Timing Characteristics .......................... 202

Index Pulse Timing Requirements............................ 202

Operation During CPU Idle Mode............................... 95

Operation During CPU Sleep Mode............................ 95

Register Map .............................................................. 97

Timer Operation During CPU Idle Mode..................... 96

Timer Operation During CPU Sleep Mode ................. 95

Quadrature Decoder Timing Requirements...................... 201

Quadrature Encoder Interface (QEI) Module...................... 93

Quadrature Encoder Interface Interrupts............................ 96

Quadrature Encoder Interface Logic................................... 94

Timing Characteristics ..............................................193

Timing Requirements................................................194

PRO MATE II Universal Device Programmer ...................171

Product Identification System............................................245

Program Address Space.....................................................29

Alignment and Data Access Using

Table Instructions................................................30

Construction................................................................29

Data Access from, Address Generation......................29

Memory Map...............................................................33

Table Instructions

TBLRDH..............................................................30

TBLRDL ..............................................................30

TBLWTH .............................................................30

TBLWTL..............................................................30

Program and EEPROM Characteristics............................188

Program Counter.................................................................18

Program Data Table Access ...............................................31

Program Flash Memory Characteristics............................188

Program Space Visibility

R

Reset ........................................................................ 149, 154

Reset Sequence ................................................................. 51

Reset Sources ............................................................ 51

Reset Timing Characteristics............................................ 193

Reset Timing Requirements ............................................. 194

Resets

BOR, Programmable ................................................ 156

POR.......................................................................... 154

Operating without FSCM and PWRT................ 156

POR with Long Crystal Start-up Time....................... 156

RTSP Operation ................................................................. 56

Window into Program Space Operation......................32

Program Space Visibility from Data Space .........................31

Programmable...................................................................149

Programmable Digital Noise Filters.....................................95

Programmer’s Model...........................................................18

Diagram ......................................................................19

DS70082C-page 240

Advance Information

 2003 Microchip Technology Inc.

dsPIC30F

Real-Time Clock......................................................... 72

RTC Interrupts.................................................... 72

RTC Oscillator Operation ................................... 72

Register Map .............................................................. 73

Timer2 and Timer 3 Selection Mode................................... 90

Timer2/3 Module................................................................. 75

32-bit Synchronous Counter Mode............................. 75

32-bit Timer Mode ...................................................... 75

ADC Event Trigger ..................................................... 78

Gate Operation........................................................... 78

Interrupt ...................................................................... 78

Operation During Sleep Mode.................................... 78

Register Map .............................................................. 79

Timer Prescaler .......................................................... 78

Timer4/5 Module................................................................. 81

Register Map .............................................................. 83

TimerQ (QEI Module) External Clock

S

Sales and Support ............................................................ 245

Serial Peripheral Interface. See SPI

Simple Capture Event Mode

Capture Buffer Operation............................................ 85

Capture Prescaler....................................................... 85

Hall Sensor Mode ....................................................... 86

Input Capture in CPU Idle Mode................................. 86

Timer2 and Timer3 Selection Mode............................ 86

Simple OC/PWM Mode Timing Requirements.................. 199

Simple Output Compare Match Mode................................. 90

Simple PWM Mode ............................................................. 90

Input Pin FAULT Protection ........................................ 90

Period.......................................................................... 91

Single Pulse PWM Operation ........................................... 106

Software Simulator (MPLAB SIM)..................................... 170

Software Simulator (MPLAB SIM30)................................. 170

Software Stack Pointer, Frame Pointer............................... 18

CALL Stack Frame...................................................... 35

SPI .................................................................................... 109

SPI Mode

Timing Characteristics.............................................. 197

Timing Characteristics

A/D Conversion

High-speed (CHPS = 01, SIMSAM = 0,

ASAM = 0, SSRC = 000) ......................... 218

High-speed (CHPS = 01, SIMSAM = 0,

Slave Select Synchronization ................................... 111

SPI1 Register Map.................................................... 112

SPI2 Register Map.................................................... 112

SPI Module ....................................................................... 109

Framed SPI Support ................................................. 109

Operating Function Description ................................ 109

SDOx Disable ........................................................... 109

Timing Characteristics

ASAM = 1, SSRC = 111,

SAMC = 00001)....................................... 219

Low-speed (ASAM = 0, SSRC = 000) ............. 223

Bandgap Start-up Time ............................................ 194

CAN Module I/O ....................................................... 215

CLKOUT and I/O ...................................................... 192

DCI Module

Master Mode (CKE = 0).................................... 206

Master Mode (CKE = 1).................................... 207

Slave Mode (CKE = 1).............................. 208, 209

Timing Requirements

AC-Link Mode................................................... 205

2

Multichannel, I S Modes................................... 203

External Clock .......................................................... 189

2

I C Bus Data

Master Mode (CKE = 0).................................... 206

Master Mode (CKE = 1).................................... 207

Slave Mode (CKE = 0)...................................... 208

Slave Mode (CKE = 1)...................................... 210

Word and Byte Communication ................................ 109

SPI Operation During CPU Idle Mode .............................. 111

SPI Operation During CPU Sleep Mode........................... 111

STATUS Register ............................................................... 18

Sticky Z (SZ) Status Bit............................................... 18

Subtractor ........................................................................... 27

Data Space Write Saturation ...................................... 28

Overflow and Saturation ............................................. 27

Round Logic................................................................ 28

Write Back................................................................... 28

Symbols used in Roadrunner Opcode Descriptions ......... 162

System Integration............................................................ 149

Overview................................................................... 149

Register Map............................................................. 160

Master Mode..................................................... 211

Slave Mode ...................................................... 213

2

I C Bus Start/Stop Bits

Master Mode..................................................... 211

Slave Mode ...................................................... 213

Input Capture (CAPX)............................................... 198

Motor Control PWM Module ..................................... 200

Motor Control PWM Module Falult ........................... 200

OC/PWM Module...................................................... 199

Oscillator Start-up Timer........................................... 193

Output Compare Module .......................................... 198

Power-up Timer........................................................ 193

QEI Module Index Pulse........................................... 202

Reset ........................................................................ 193

SPI Module

Master Mode (CKE = 0) ................................... 206

Master Mode (CKE = 1) ................................... 207

Slave Mode (CKE = 0) ..................................... 208

Slave Mode (CKE = 1) ..................................... 209

TimerQ (QEI Module) External Clock....................... 197

Type A, B and C Timer External Clock..................... 195

Watchdog Timer ....................................................... 193

Timing Diagrams

T

Temperature and Voltage Specifications

AC............................................................................. 189

DC............................................................................. 176

Timer1 Module.................................................................... 71

16-bit Asynchronous Counter Mode ........................... 71

16-bit Synchronous Counter Mode ............................. 71

16-bit Timer Mode....................................................... 71

Gate Operation ........................................................... 72

Interrupt....................................................................... 72

Operation During Sleep Mode .................................... 72

Prescaler..................................................................... 72

Center Aligned PWM................................................ 104

Dead-Time................................................................ 105

Edge Aligned PWM .................................................. 103

PWM Output............................................................... 91

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 1 ..................... 155

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Advance Information

DS70082C-page 241

dsPIC30F

Time-out Sequence on Power-up

U

(MCLR Not Tied to VDD), Case 2......................155

UART

Address Detect Mode ............................................... 125

Time-out Sequence on Power-up

(MCLR Tied to VDD)..........................................155

Timing Diagrams and Specifications

Auto Baud Support ................................................... 126

Baud Rate Generator ............................................... 125

Enabling and Setting Up UART ................................ 123

Alternate I/O ..................................................... 123

Disabling........................................................... 123

Enabling............................................................ 123

Setting Up Data, Parity and STOP Bit Selections ..

123

DC Characteristics - Internal RC Accuracy...............191

Timing Diagrams.See Timing Characteristics

Timing Requirements

A/D Conversion

High-speed........................................................220

Low-speed ........................................................224

Bandgap Start-up Time.............................................194

Brown-out Reset .......................................................194

CAN Module I/O........................................................215

CLKOUT and I/O.......................................................192

DCI Module

Loopback Mode........................................................ 125

Module Overview...................................................... 121

Operation During CPU Sleep and Idle Modes.......... 126

Receiving Data ......................................................... 124

In 8-bit or 9-bit Data Mode................................ 124

Interrupt ............................................................ 124

Receive Buffer (UxRCB)................................... 124

Reception Error Handling ......................................... 124

Framing Error (FERR) ...................................... 125

Idle Status......................................................... 125

Parity Error (PERR).......................................... 125

Receive Break .................................................. 125

Receive Buffer Overrun Error (OERR Bit)........ 124

Transmittin Data

AC-Link Mode ...................................................205

2

Multichannel, I S Modes...................................204

External Clock...........................................................190

2

I C Bus Data (Master Mode).....................................212

2

I C Bus Data (Slave Mode).......................................214

Input Capture ............................................................198

Motor Control PWM Module......................................200

Oscillator Start-up Timer...........................................194

Output Compare Module...........................................198

Power-up Timer ........................................................194

QEI Module

In 8-bit Data Mode............................................ 123

Transmitting Data ..................................................... 123

In 9-bit Data Mode............................................ 123

Interrupt ............................................................ 124

Transmit Buffer (UxTXB) .................................. 123

UART1 Register Map................................................ 127

UART2 Register Map................................................ 127

Unit ID Locations .............................................................. 149

Universal Asynchronous Receiver Transmitter. See UART.

External Clock...................................................197

Index Pulse .......................................................202

Quadrature Decoder .................................................201

Reset.........................................................................194

Simple OC/PWM Mode.............................................199

SPI Module

Master Mode (CKE = 0)....................................206

Master Mode (CKE = 1)....................................207

Slave Mode (CKE = 0)......................................208

Slave Mode (CKE = 1)......................................210

Type A Timer External Clock ....................................195

Type B Timer External Clock ....................................196

Type C Timer External Clock ....................................196

Watchdog Timer........................................................194

Timing Specifications

W

Wake-up from Sleep......................................................... 149

Wake-up from Sleep and Idle ............................................. 53

Watchdog Timer

Timing Characteristics .............................................. 193

Timing Requirements................................................ 194

Watchdog Timer (WDT)............................................ 149, 158

Enabling and Disabling............................................. 158

Operation.................................................................. 158

WWW, On-Line Support ....................................................... 9

PLL Clock..................................................................191

DS70082C-page 242

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 2003 Microchip Technology Inc.

dsPIC30F

ON-LINE SUPPORT

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

Microchip provides on-line support on the Microchip

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DS70082C-page 243

dsPIC30F

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

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dsPIC30F

DS70082C

Literature Number:

Device:

Questions:

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DS70082C-page 244

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dsPIC30F

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales officeK

dsPIC30LF1001ATP-I/PT-000

Custom ID

Package

Trademark

Family

PT = TQFP 10x10

PT = TQFP 12x12

PT = TQFP 14x14

SO = SOIC

L = Low Voltage

SP = SDIP

Memory

Type

P

= DIP

S

= Die (Waffle Pack)

= Die (Wafers)

Flash = F

Memory Size in Bytes

W

0 = ROMless

1 = 1K to 6K

Temperature

2 = 7K to 12K

I = Industrial -40°C to +85°C

3 = 13K to 24K

4 = 25K to 48K

5 = 49K to 96K

6 = 97K to 192K

7 = 193K to 384K

8 = 385K to 768K

9 = 769K and Up

E = Extended High Temp -40°C to +125°C

P = Pilot

T = Tape and Reel

A,B,C… = Revision

Device ID

Examples:

a) dsPIC30F2011ATP-E/SO = Extended temp., SOIC package, Rev. B.

b) dsPIC30F6010ATP-I/PT = Industrial temp., TQFP package, Rev. B.

c) dsPIC30F3011ATP-I/P = Industrial temp., PDIP package, Rev. B.

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of

each oscillator type.

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Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

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DS70082C-page 245

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Tel: 86-10-85282100

Fax: 86-10-85282104

3780 Mansell Road, Suite 130

Alpharetta, GA 30022

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

Boston

Min Chuan 2nd Road

Kaohsiung 806, Taiwan

Tel: 886-7-536-4818

Fax: 886-7-536-4803

China - Chengdu

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848

Fax: 978-692-3821

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Taiwan

Chengdu 610016, China

Tel: 86-28-86766200

Taiwan Branch

Chicago

11F-3, No. 207

333 Pierce Road, Suite 180

Itasca, IL 60143

Fax: 86-28-86766599

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

China - Fuzhou

Tel: 630-285-0071

Fax: 630-285-0075

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Dallas

Fuzhou 350001, China

Tel: 86-591-7503506

Fax: 86-591-7503521

EUROPE

4570 Westgrove Drive, Suite 160

Addison, TX 75001

Tel: 972-818-7423

Fax: 972-818-2924

Austria

Durisolstrasse 2

China - Hong Kong SAR

A-4600 Wels

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Austria

Detroit

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250

Fax: 852-2401-3431

Regus Business Centre

Lautrup hoj 1-3

China - Shanghai

Room 701, Bldg. B

Fax: 248-538-2260

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Kokomo

France

2767 S. Albright Road

Kokomo, IN 46902

Tel: 765-864-8360

Fax: 765-864-8387

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Tel: 86-21-6275-5700

Fax: 86-21-6275-5060

China - Shenzhen

Los Angeles

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-755-82901380

18201 Von Karman, Suite 1090

Irvine, CA 92612

Germany

Tel: 949-263-1888

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Fax: 949-263-1338

Fax: 86-755-8295-1393

Phoenix

China - Shunde

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966

Fax: 480-792-4338

Room 401, Hongjian Building

No. 2 Fengxiangnan Road, Ronggui Town

Shunde City, Guangdong 528303, China

Tel: 86-765-8395507 Fax: 86-765-8395571

Italy

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

China - Qingdao

San Jose

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

Rm. B505A, Fullhope Plaza,

1300 Terra Bella Avenue

Mountain View, CA 94043

Tel: 650-215-1444

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Tel: 86-532-5027355 Fax: 86-532-5027205

P. A. De Biesbosch 14

NL-5152 SC Drunen, Netherlands

Tel: 31-416-690399

Toronto

India

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Fax: 905-673-6509

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

11/24/03

DS70082C-page 246

Advance Information

 2003 Microchip Technology Inc.


型号：	DSPIC30F3011AP-I/PT
厂家：	MICROCHIP
描述：	Digital Signal Processor
文件：	总248页 (文件大小：7388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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