DSPIC30F3013AT30I/SO

dsPIC30F2011/2012/3012/3013

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

DS70139E

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PIC, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

8-bit MCUs, KEELOQ^®code hopping devices, Serial EEPROMs,

microperipherals, nonvolatile memory and analog products. In addition,

Microchip’s quality system for the design and manufacture of

development systems is ISO 9001:2000 certified.

DS70139E-page ii

dsPIC30F2011/2012/3012/3013

dsPIC30F2011/2012/3012/3013 High-Performance

Digital Signal Controllers

• 16-bit Compare/PWM output functions

Note: This data sheet summarizes features of this group

• 3-wire SPI modules (supports four Frame modes)

• I²C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

• Up to two addressable UART modules with FIFO

buffers

Analog Features:

High-Performance Modified RISC CPU:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 ksps conversion rate

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

- Up to 10 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Reset

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 24 Kbytes on-chip Flash program space

• Up to 2 Kbytes of on-chip data RAM

• Up to 1 Kbytes of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

- DC to 40 MHz external clock input

• Data EEPROM memory:

- 4 MHz - 10 MHz oscillator input with

PLL active (4x, 8x, 16x)

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Up to 21 interrupt sources:

- 8 user-selectable priority levels

- 3 external interrupt sources

- 4 processor trap sources

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip low-

power RC oscillator for reliable operation

DSP Features:

• Fail-Safe Clock Monitor operation:

• Dual data fetch

- Detects clock failure and switches to on-chip

low-power RC oscillator

• Modulo and Bit-Reversed modes

• Programmable code protection

• Two 40-bit wide accumulators with optional

saturation logic

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

• 17-bit x 17-bit single-cycle hardware fractional/

integer multiplier

• All DSP instructions are single cycle

- Multiply-Accumulate (MAC) operation

• single-cycle ±16 shift

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low-power consumption

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25 mA

• Three 16-bit timers/counters; optionally pair up

16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

DS70139E-page 1

dsPIC30F2011/2012/3012/3013

dsPIC30F2011/2012/3012/3013 Sensor Family

Program Memory

Output

Comp/Std

PWM

SRAM EEPROM Timer Input

A/D 12-bit

200 Ksps

Device

Pins

Bytes

16-bit Cap

Bytes Instructions

dsPIC30F2011

dsPIC30F3012

dsPIC30F2012

dsPIC30F3013

18

28

12K

24K

12K

24K

4K

8K

4K

8K

1024

2048

1024

2048

–

3

2

8 ch

1

2

1

1024

–

10 ch

1024

Pin Diagrams

18-Pin PDIP and SOIC

MCLR

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

AVDD

AVSS

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN6/SCK1/INT0/OCFA/RB6

EMUD2/AN7/OC2/IC2/INT2/RB7

VDD

VSS

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

EMUC2/OC1/IC1/INT1/RD0

OSC1/CLKI

OSC2/CLKO/RC15

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

28-Pin PDIP and SOIC

MCLR

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

AVDD

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

CN17/RF4

AN4/CN6/RB4

AN5/CN7/RB5

VSS

CN18/RF5

OSC1/CLKI

OSC2/CLKO/RC15

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

VSS

9

20

19

18

17

16

15

10

11

12

13

14

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

28-Pin SPDIP and SOIC

MCLR

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AVDD

AVSS

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

U2RX/CN17/RF4

U2TX/CN18/RF5

VDD

AN4/CN6/RB4

AN5/CN7/RB5

VSS

OSC1/CLKI

9

OSC2/CLKO/RC15

VSS

10

11

12

13

14

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

VDD

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

SCK1/INT0/RF6

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139E-page 2

dsPIC30F2011/2012/3012/3013

Pin Diagrams

28-Pin QFN

AN2/SS1/LVDIN/CN4/RB2

NC

20 NC

19 NC

1

2

3

4

5

6

7

21

AN3/CN5/RB3

NC

VSS

dsPIC30F2011

NC

VDD

VSS

18

17

16

15

OSC1/CLKI

OSC2/CLKO/RC15

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139E-page 3

dsPIC30F2011/2012/3012/3013

Pin Diagrams

28-Pin QFN

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

VSS

1

2

3

4

5

6

7

21

AN8/OC1/RB8

20 AN9/OC2/RB9

19 CN17/RF4

18

17 VDD

16

15

dsPIC30F2012

CN18/RF5

OSC1/CLKI

OSC2/CLKO/RC15

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139E-page 4

dsPIC30F2011/2012/3012/3013

Pin Diagram

44-Pin QFN

44 43 42 41 40 39 38 37 36 35 34

1

2

3

4

5

6

7

8

9

33

32

31

30

29

28

27

26

25

24

23

OSC2/CLKO/RC15

OSC1/CLKI

VSS

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

VSS

NC

VDD

NC

VSS

NC

dsPIC30F3012

AN3/CN5/RB3

NC

AN2/SS1/LVDIN/CN4/RB2

10

11

12 13 14 15 16 17 18 19 20 21 22

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139E-page 5

dsPIC30F2011/2012/3012/3013

Pin Diagrams

44-Pin QFN

OSC2/CLKO/RC15

OSC1/CLKI

VSS

PGC/EMUC/U1RX/SDI1/SDA/RF2

1

2

3

33

32

31

30

VSS

NC

VDD

4

VSS

5

29 NC

NC

6

7

8

9

10

11

28

27

26

25

24

23

NC

dsPIC30F3013

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

NC

U2TX/CN18/RF5

NC

U2RX/CN17/RF4

AN9/OC2/RB9

AN8/OC1/RB8

AN2/SS1/LVDIN/CN4/RB2

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

DS70139E-page 6

dsPIC30F2011/2012/3012/3013

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 CPU Architecture Overview........................................................................................................................................................ 17

3.0 Memory Organization................................................................................................................................................................. 27

4.0 Address Generator Units............................................................................................................................................................ 41

5.0 Flash Program Memory.............................................................................................................................................................. 47

6.0 Data EEPROM Memory ............................................................................................................................................................. 53

7.0 I/O Ports ..................................................................................................................................................................................... 57

8.0 Interrupts .................................................................................................................................................................................... 63

9.0 Timer1 Module ........................................................................................................................................................................... 71

10.0 Timer2/3 Module ........................................................................................................................................................................ 75

11.0 Input Capture Module................................................................................................................................................................. 81

12.0 Output Compare Module............................................................................................................................................................ 85

13.0 SPI Module................................................................................................................................................................................. 89

14.0 I2C Module................................................................................................................................................................................. 93

15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 101

16.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 109

17.0 System Integration ................................................................................................................................................................... 119

18.0 Instruction Set Summary.......................................................................................................................................................... 133

19.0 Development Support............................................................................................................................................................... 141

20.0 Electrical Characteristics.......................................................................................................................................................... 145

21.0 Packaging Information.............................................................................................................................................................. 183

Index .................................................................................................................................................................................................. 193

The Microchip Web Site..................................................................................................................................................................... 199

Customer Change Notification Service .............................................................................................................................................. 199

Customer Support.............................................................................................................................................................................. 199

Reader Response.............................................................................................................................................................................. 200

Product Identification System ............................................................................................................................................................ 201

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS70139E-page 7

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 8

dsPIC30F2011/2012/3012/3013

This data sheet contains information specific to the

dsPIC30F2011, dsPIC30F2012, dsPIC30F3012 and

1.0

DEVICE OVERVIEW

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual“ (DS70157).

dsPIC30F3013 Digital Signal Controllers (DSC). These

devices contain extensive Digital Signal Processor

(DSP) functionality within a high-performance 16-bit

microcontroller (MCU) architecture.

The following block diagrams depict the architecture for

these devices:

• Figure 1-1 illustrates the dsPIC30F2011

• Figure 1-2 illustrates the dsPIC30F2012

• Figure 1-3 illustrates the dsPIC30F3012

• Figure 1-4 illustrates the dsPIC30F3013

Following the block diagrams, Table 1-1 relates the I/O

functions to pinout information.

DS70139E-page 9

dsPIC30F2011/2012/3012/3013

FIGURE 1-1:

dsPIC30F2011 BLOCK DIAGRAM

Y Data Bus

X Data Bus

16 16

16

Data Latch

Interrupt

Controller

PSV & Table

Data Access

Control Block

X Data

RAM

(512 bytes)

Address

Latch

Y Data

RAM

(512 bytes)

Address

Latch

8

16

24

16

24

16

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

AN6/SCK1/INT0/OCFA/RB6

X RAGU

X WAGU

Y AGU

PCH PCL

PCU

Program Counter

Loop

Control

Logic

Stack

Control

Logic

Address Latch

Program Memory

(12 Kbytes)

EMUD2/AN7/OC2/IC2/INT2/RB7

Data Latch

Effective Address

PORTB

16

ROM Latch

16

24

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

IR

16

16 x 16

W Reg Array

Decode

PORTC

Instruction

Decode &

Control

16 16

DSP

Engine

Divide

Unit

Power-up

Timer

EMUC2/OC1/IC1/INT1/RD0

Timing

Generation

Oscillator

Start-up Timer

OSC1/CLKI

ALU<16>

16

POR/BOR

Reset

16

PORTD

Watchdog

Timer

MCLR

Low-Voltage

Detect

VDD, VSS

AVDD, AVSS

Input

Capture

Module

Output

Compare

Module

I²C™

12-bit ADC

Timers

SPI1

UART1

DS70139E-page 10

dsPIC30F2011/2012/3012/3013

FIGURE 1-2:

dsPIC30F2012 BLOCK DIAGRAM

Y Data Bus

X Data Bus

16

Data Latch

Interrupt

Controller

PSV & Table

Data Access

Control Block

X Data

RAM

(512 bytes)

Address

Latch

Y Data

RAM

(512 bytes)

Address

Latch

8

16

24

16

24

16

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

X RAGU

X WAGU

Y AGU

PCH PCL

PCU

Program Counter

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

Stack

Control

Logic

Loop

Control

Logic

Address Latch

Program Memory

(12 Kbytes)

Data Latch

Effective Address

16

PORTB

ROM Latch

16

24

IR

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

16

16 x 16

W Reg Array

PORTC

Decode

Instruction

Decode &

Control

16 16

DSP

Engine

Divide

Unit

Power-up

Timer

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

Timing

Generation

Oscillator

Start-up Timer

OSC1/CLKI

ALU<16>

16

POR/BOR

Reset

PORTD

16

Watchdog

Timer

MCLR

Low-Voltage

Detect

VDD, VSS

AVDD, AVSS

Input

Capture

Module

Output

Compare

Module

I²C™

12-bit ADC

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

CN17/RF4

CN18/RF5

SCK1/INT0/RF6

Timers

SPI1

UART1

PORTF

DS70139E-page 11

dsPIC30F2011/2012/3012/3013

FIGURE 1-3:

dsPIC30F3012 BLOCK DIAGRAM

Y Data Bus

X Data Bus

16 16

16

Data Latch

Interrupt

Controller

PSV & Table

Data Access

Control Block

X Data

RAM

(1 Kbytes)

Address

Latch

Y Data

RAM

(1 Kbytes)

Address

Latch

8

16

24

16

24

16

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4

PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5

AN6/SCK1/INT0/OCFA/RB6

X RAGU

X WAGU

Y AGU

PCH PCL

PCU

Program Counter

Stack

Control

Logic

Loop

Control

Logic

Address Latch

Program Memory

(24 Kbytes)

EMUD2/AN7/OC2/IC2/INT2/RB7

Data EEPROM

(1 Kbytes)

Effective Address

PORTB

16

Data Latch

ROM Latch

16

24

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

IR

16

16 x 16

W Reg Array

Decode

PORTC

Instruction

Decode &

Control

16 16

DSP

Engine

Divide

Unit

Power-up

Timer

EMUC2/OC1/IC1/INT1/RD0

Timing

Generation

Oscillator

Start-up Timer

OSC1/CLKI

ALU<16>

16

POR/BOR

Reset

16

PORTD

Watchdog

Timer

MCLR

Low-Voltage

Detect

VDD, VSS

AVDD, AVSS

Input

Capture

Module

Output

Compare

Module

I²C™

12-bit ADC

Timers

SPI1

UART1

DS70139E-page 12

dsPIC30F2011/2012/3012/3013

FIGURE 1-4:

dsPIC30F3013 BLOCK DIAGRAM

Y Data Bus

X Data Bus

16

Data Latch

Interrupt

Controller

PSV & Table

Data Access

Control Block

X Data

RAM

(1 Kbytes)

Address

Latch

Y Data

RAM

(1 Kbytes)

Address

Latch

8

16

24

16

24

16

EMUD3/AN0/VREF+/CN2/RB0

EMUC3/AN1/VREF-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

X RAGU

X WAGU

Y AGU

PCH PCL

PCU

Address Latch

Program Counter

AN3/CN5/RB3

AN4/CN6/RB4

AN5/CN7/RB5

AN6/OCFA/RB6

EMUD2/AN7/RB7

AN8/OC1/RB8

AN9/OC2/RB9

Stack

Control

Logic

Loop

Control

Logic

Program Memory

(24 Kbytes)

Data EEPROM

(1 Kbytes)

Data Latch

Effective Address

16

PORTB

ROM Latch

16

24

IR

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13

EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14

OSC2/CLKO/RC15

16

16 x 16

W Reg Array

PORTC

Decode

Instruction

Decode &

Control

16 16

DSP

Engine

Divide

Unit

Power-up

Timer

EMUC2/IC1/INT1/RD8

IC2/INT2/RD9

Timing

Generation

Oscillator

Start-up Timer

OSC1/CLKI

ALU<16>

16

POR/BOR

Reset

PORTD

16

Watchdog

Timer

MCLR

Low-Voltage

Detect

VDD, VSS

AVDD, AVSS

Input

Capture

Module

Output

Compare

Module

I²C™

12-bit ADC

PGC/EMUC/U1RX/SDI1/SDA/RF2

PGD/EMUD/U1TX/SDO1/SCL/RF3

U2RX/CN17/RF4

U2TX/CN18/RF5

SCK1/INT0/RF6

UART1,

UART2

SPI1

Timers

PORTF

DS70139E-page 13

dsPIC30F2011/2012/3012/3013

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1:

PINOUT I/O DESCRIPTIONS

Type

Buffer

Type

Pin Name

Description

AN0 - AN9

AVDD

I

Analog

Analog input channels.

P

I

P

Positive supply for analog module.

Ground reference for analog module.

AVSS

CLKI

ST/CMOS

External clock source input. Always associated with OSC1 pin

function.

CLKO

O

—

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes. Always associated with OSC2 pin function.

CN0 - CN7

I

ST

Input change notification inputs.

Can be software programmed for internal weak pull-ups on all

inputs.

EMUD

EMUC

I/O

ST

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

IC1 - IC2

I

ST

Capture inputs 1 through 2.

INT0

INT1

INT2

I

ST

External interrupt 0.

External interrupt 1.

External interrupt 2.

LVDIN

MCLR

I

Analog

ST

Low-Voltage Detect Reference Voltage Input pin.

I/P

Master Clear (Reset) input or programming voltage input. This

pin is an active-low Reset to the device.

OC1-OC2

OCFA

O

I

—

ST

Compare outputs 1 through 2.

Compare Fault A input.

OSC1

I

ST/CMOS

Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.

OSC2

I/O

—

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes.

PGD

PGC

I/O

I

ST

In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RB0 - RB9

I/O

ST

PORTB is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

PORTD is a bidirectional I/O port.

PORTF is a bidirectional I/O port.

RC13 - RC15

RD0, RD8 - RD9

RF2 - RF5

SCK1

SDI1

SDO1

SS1

I/O

ST

—

Synchronous serial clock input/output for SPI1.

SPI1 Data In.

SPI1 Data Out.

I

O

I

ST

SPI1 Slave Synchronization.

Legend: CMOS = CMOS compatible input or output

Analog = Analog input

ST

I

=

Schmitt Trigger input with CMOS levels

Input

O

P

=

Output

Power

DS70139E-page 14

dsPIC30F2011/2012/3012/3013

TABLE 1-1:

PINOUT I/O DESCRIPTIONS (CONTINUED)

Type

Buffer

Type

Pin Name

Description

2

SCL

SDA

I/O

ST

Synchronous serial clock input/output for I C™.

2

Synchronous serial data input/output for I C.

SOSCO

SOSCI

O

I

—

32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when

configured in RC mode; CMOS otherwise.

ST/CMOS

T1CK

T2CK

I

ST

Timer1 external clock input.

Timer2 external clock input.

U1RX

U1TX

U1ARX

U1ATX

U2RX

U2TX

I

O

I

O

I

ST

—

ST

—

ST

—

UART1 Receive.

UART1 Transmit.

UART1 Alternate Receive.

UART1 Alternate Transmit.

UART2 Receive.

O

UART2 Transmit.

VDD

P

I

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

Analog Voltage Reference (High) input.

Analog Voltage Reference (Low) input.

Analog = Analog input

VSS

—

VREF+

VREF-

Analog

I

Legend: CMOS = CMOS compatible input or output

ST

I

=

Schmitt Trigger input with CMOS levels

Input

O

P

=

Output

Power

DS70139E-page 15

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 16

dsPIC30F2011/2012/3012/3013

Two ways to access data in program memory are:

2.0

CPU ARCHITECTURE

OVERVIEW

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

program space at any 16K program word bound-

ary, defined by the 8-bit Program Space Visibility

Page (PSVPAG) register. Thus any instruction

can access program space as if it were data

space, with a limitation that the access requires

an additional cycle. Only the lower 16 bits of each

instruction word can be accessed using this

method.

This section is an overview of the CPU architecture of

the dsPIC30F. The core has a 24-bit instruction word.

The Program Counter (PC) is 23 bits wide with the

Least Significant bit (LSb) always clear (see

Section 3.1 “Program Address Space”). The Most

Significant bit (MSb) is ignored during normal program

execution, except for certain specialized instructions.

Thus, the PC can address up to 4M instruction words

of user program space. An instruction prefetch mecha-

nism helps maintain throughput. Program loop con-

structs, free from loop count management overhead,

are supported using the DO and REPEATinstructions,

both of which are interruptible at any point.

• Linear indirect access of 32K word pages within

program space is also possible using any working

register, via table read and write instructions.

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination effective addresses to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 “Address Generator Units” for

details on Modulo and Bit-Reversed Addressing.

2.1

Core Overview

The working register array consists of 16 x 16-bit regis-

ters, each of which can act as data, address or offset

registers. One working register (W15) operates as a

Software Stack Pointer for interrupts and calls.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct, Register Direct, Register

Indirect, Register Offset and Literal Offset Addressing

modes. Instructions are associated with pre-defined

addressing modes, depending upon their functional

requirements.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory, AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device specific and cannot be

altered by the user. Each data word consists of 2 bytes

and most instructions can address data either as words

or bytes.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3 operand instructions are supported, allowing

C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capability and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bidirectional barrel shifter. Data in the accumula-

tor or any working register can be shifted up to 15 bits

right, or 16 bits left in a single cycle. The DSP instruc-

tions operate seamlessly with all other instructions and

have been designed for optimal real-time performance.

The MAC class of instructions can concurrently fetch

two data operands from memory while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear is for all others. This has been

achieved in a transparent and flexible manner, by ded-

icating certain working registers to each address space

for the MAC class of instructions.

DS70139E-page 17

dsPIC30F2011/2012/3012/3013

The core does not support a multi-stage instruction

pipeline. However, a single-stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle with certain

exceptions.

2.2.1

SOFTWARE STACK POINTER/

FRAME POINTER

The dsPIC^®DSC devices contain a software stack.

W15 is the dedicated Software Stack Pointer (SP),

which is automatically modified by exception process-

ing and subroutine calls and returns. However, W15

can be referenced by any instruction in the same man-

ner as all other W registers. This simplifies the reading,

writing and manipulation of the Stack Pointer (e.g., cre-

ating stack frames).

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are reserved) and 54 interrupts. Each interrupt

is prioritized based on a user-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest), in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities ranging from 8 to 15.

Note:

In order to protect against misaligned

stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

2.2

Programmer’s Model

W14 has been dedicated as a Stack Frame Pointer, as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

The programmer’s model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through

W15), 2 x 40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

2.2.2

STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register

(SR), the LSB of which is referred to as the SR Low

byte (SRL) and the MSB as the SR High byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation Status flags

(including the Z bit), as well as the CPU Interrupt Prior-

ity Level Status bits, IPL<2:0>, and the Repeat Active

Status bit, RA. During exception processing, SRL is

concatenated with the MSB of the PC to form a com-

plete word value which is then stacked.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary holding register

and can transfer its contents to or from its host register

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

The upper byte of the STATUS register contains the

DSP Adder/Subtracter Status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) Status bit.

• PUSH.Sand POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

2.2.3

PROGRAM COUNTER

The program counter is 23 bits wide; bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

• DOinstruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start and popped on loop end.

When a byte operation is performed on a working reg-

ister, only the Least Significant Byte (LSB) of the target

register is affected. However, a benefit of memory

mapped working registers is that both the Least and

Most Significant Bytes (MSB) can be manipulated

through byte-wide data memory space accesses.

DS70139E-page 18

dsPIC30F2011/2012/3012/3013

FIGURE 2-1:

PROGRAMMER’S MODEL

D15

D0

W0/WREG

W1

PUSH.SShadow

DOShadow

W2

W3

Legend

W4

DSP Operand

Registers

W5

W6

W7

Working Registers

W8

W9

DSP Address

Registers

W10

W11

W12/DSP Offset

W13/DSP Write-Back

W14/Frame Pointer

W15/Stack Pointer

SPLIM

Stack Pointer Limit Register

AD0

AD15

AD39

ACCA

AD31

DSP

Accumulators

ACCB

PC22

PC0

0

Program Counter

0

7

TABPAG

TBLPAG

Data Table Page Address

7

0

PSVPAG

Program Space Visibility Page Address

15

0

RCOUNT

REPEATLoop Counter

DOLoop Counter

15

DCOUNT

22

0

DOSTART

DOEND

DOLoop Start Address

DOLoop End Address

22

15

0

Core Configuration Register

CORCON

OA OB

SA SB OAB SAB DA DC

SRH

IPL0 RA

N

OV

Z

C

IPL2 IPL1

STATUS register

SRL

DS70139E-page 19

dsPIC30F2011/2012/3012/3013

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g., a

series of discrete divide instructions) will not function

correctly because the instruction flow depends on

RCOUNT. The divide instruction does not automatically

set up the RCOUNT value and it must, therefore, be

explicitly and correctly specified in the REPEATinstruc-

tion, as shown in Table 2-1 (REPEATexecutes the tar-

get instruction {operand value+1} times). The REPEAT

loop count must be setup for 18 iterations of the DIV/

DIVF instruction. Thus, a complete divide operation

requires 19 cycles.

2.3

Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fractional divide operation, as well as 32/16-bit and 16/

16-bit signed and unsigned integer divide operations, in

the form of single instruction iterative divides. The fol-

lowing instructions and data sizes are supported:

1. DIVF- 16/16 signed fractional divide

2. DIV.sd- 32/16 signed divide

3. DIV.ud- 32/16 unsigned divide

4. DIV.s- 16/16 signed divide

5. DIV.u- 16/16 unsigned divide

Note:

The divide flow is interruptible. However,

the user needs to save the context as

appropriate.

The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or

sign-extended during the first iteration.

TABLE 2-1:

Instruction

DIVIDE INSTRUCTIONS

Function

DIVF

Signed fractional divide: Wm/Wn → W0; Rem → W1

Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

Signed divide: Wm/Wn → W0; Rem → W1

Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

Unsigned divide: Wm/Wn → W0; Rem → W1

DIV.sd

DIV.s

DIV.ud

DIV.u

DS70139E-page 20

dsPIC30F2011/2012/3012/3013

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

2.4

DSP Engine

The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

1. Fractional or integer DSP multiply (IF).

2. Signed or unsigned DSP multiply (US).

3. Conventional or convergent rounding (RND).

4. Automatic saturation on/off for ACCA (SATA).

5. Automatic saturation on/off for ACCB (SATB).

The DSP engine also has the capability to perform

inherent

which require no additional data. These instructions are

accumulator-to-accumulator

operations,

ADD, SUBand NEG.

6. Automatic saturation on/off for writes to data

memory (SATDW).

The dsPIC30F is a single-cycle instruction flow archi-

tecture, therefore, concurrent operation of the DSP

engine with MCU instruction flow is not possible.

However, some MCU ALU and DSP engine resources

may be used concurrently by the same instruction (e.g.,

ED, EDAC). See Table 2-2.

7. Accumulator Saturation mode selection

(ACCSAT).

Note:

For CORCON layout, see Table 3-3.

A block diagram of the DSP engine is shown in

Figure 2-2.

TABLE 2-2:

DSP INSTRUCTION SUMMARY

Algebraic Operation

Instruction

ACC WB?

CLR

ED

A = 0

Yes

No

A = (x – y)²

A = A + (x – y)²

A = A + (x * y)

A = A + x²

EDAC

MAC

No

Yes

No

MAC

MOVSAC

MPY

No change in A

A = x * y

Yes

No

MPY.N

MSC

A = – x * y

No

A = A – x * y

Yes

DS70139E-page 21

dsPIC30F2011/2012/3012/3013

FIGURE 2-2:

DSP ENGINE BLOCK DIAGRAM

S

a

40

16

40-bit Accumulator A

40-bit Accumulator B

40

t

Round

Logic

u

r

a

t

Carry/Borrow Out

Saturate

e

Adder

Carry/Borrow In

Negate

40

Barrel

Shifter

16

40

Sign-Extend

32

16

Zero Backfill

32

33

17-bit

Multiplier/Scaler

16

To/From W Array

DS70139E-page 22

dsPIC30F2011/2012/3012/3013

2.4.1

MULTIPLIER

2.4.2.1

Adder/Subtracter, Overflow and

Saturation

The 17 x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the mul-

tiplier input value. The output of the 17 x 17-bit multi-

plier/scaler is a 33-bit value which is sign-extended to

40 bits. Integer data is inherently represented as a

signed two’s complement value, where the MSB is

defined as a sign bit. Generally speaking, the range of

an N-bit two’s complement integer is -2^N-1to 2^N-1– 1.

For a 16-bit integer, the data range is -32768 (0x8000)

to 32767 (0x7FFF) including ‘0’. For a 32-bit integer,

the data range is -2,147,483,648 (0x8000 0000) to

2,147,483,645 (0x7FFF FFFF).

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtraction, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow Status bits SA/SB and OA/OB,

which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction, where the MSB is defined as a sign bit and the

radix point is implied to lie just after the sign bit (QX for-

mat). The range of an N-bit two’s complement fraction

with this implied radix point is -1.0 to (1 – 2^1-N). For a

16-bit fraction, the Q15 data range is -1.0 (0x8000) to

0.999969482 (0x7FFF) including ‘0’ and has a preci-

sion of 3.01518x10^-5. In Fractional mode, the 16x16

multiply operation generates a 1.31 product, which has

The adder has an additional saturation block which

controls accumulator data saturation if selected. It uses

the result of the adder, the overflow Status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow. They are:

1. OA:

a precision of 4.65661 x 10^-10

.

ACCA overflowed into guard bits

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies.

2. OB:

ACCB overflowed into guard bits

3. SA:

The MUL instruction can be directed to use byte or

word-sized operands. Byte operands direct a 16-bit

result. Word operands direct a 32-bit result to the spec-

ified register(s) in the W array.

ACCA saturated (bit 31 overflow and saturation)

or

ACCA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

4. SB:

2.4.2

DATA ACCUMULATORS AND

ADDER/SUBTRACTER

ACCB saturated (bit 31 overflow and saturation)

or

ACCB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

The data accumulator consists of a 40-bit adder/

subtracter with automatic sign extension logic. It can

select one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADDand LACinstructions, the data to be

accumulated or loaded can be optionally scaled via the

barrel shifter prior to accumulation.

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATE, OVBTE) in

the INTCON1 register (refer to Section 8.0 “Inter-

rupts”) is set. This allows the user to take immediate

action, for example, to correct system gain.

DS70139E-page 23

dsPIC30F2011/2012/3012/3013

The SA and SB bits are modified each time data

passes through the adder/subtracter but can only be

cleared by the user. When set, they indicate that the

accumulator has overflowed its maximum range (bit 31

for 32-bit saturation or bit 39 for 40-bit saturation) and

will be saturated if saturation is enabled. When satura-

tion is not enabled, SA and SB default to bit 39 overflow

and thus indicate that a catastrophic overflow has

occurred. If the COVTE bit in the INTCON1 register is

set, SA and SB bits generate an arithmetic warning trap

when saturation is disabled.

2.4.2.2

Accumulator ‘Write-Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator that is not targeted by the instruction

into data space memory. The write is performed across

the X bus into combined X and Y address space. The

following addressing modes are supported:

1. W13, Register Direct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

The overflow and saturation Status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA and OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). This allows programmers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either accumulator has saturated. This would be useful

for complex number arithmetic which typically uses

both the accumulators.

2. [W13]+=2, Register Indirect with Post-Increment:

The rounded contents of the non-target accumu-

lator are written into the address pointed to by

W13 as

incremented by 2 (for a word write).

a

1.15 fraction. W13 is then

2.4.2.3

Round Logic

The round logic is a combinational block which per-

forms a conventional (biased) or convergent (unbi-

ased) round function during an accumulator write

(store). The Round mode is determined by the state of

the RND bit in the CORCON register. It generates a 16-

bit, 1.15 data value, which is passed to the data space

write saturation logic. If rounding is not indicated by the

instruction, a truncated 1.15 data value is stored and

the least significant word (lsw) is simply discarded.

The device supports three saturation and overflow

modes:

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic loads the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumula-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and adds it to the ACCxH word (bits 16

through 31 of the accumulator). If the ACCxL word

(bits 0 through 15 of the accumulator) is between

0x8000 and 0xFFFF (0x8000 included), ACCxH is

incremented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this algo-

rithm is that over a succession of random rounding

operations, the value tends to be biased slightly

positive.

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally posi-

tive 1.31 value (0x007FFFFFFF) or maximally

negative 1.31 value (0x0080000000) into the

target accumulator. The SA or SB bit is set and

remains set until cleared by the user. When this

Saturation mode is in effect, the guard bits are

not used, so the OA, OB or OAB bits are never

set.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000. If this is the case, the LSb

(bit 16 of the accumulator) of ACCxH is examined. If it

is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not

modified. Assuming that bit 16 is effectively random in

nature, this scheme will remove any rounding bias that

may accumulate.

3. Bit 39 Catastrophic Overflow:

The bit 39 overflow Status bit from the adder is

used to set the SA or SB bit which remains set

until cleared by the user. No saturation operation

is performed and the accumulator is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic

overflow can initiate a trap exception.

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the contents

of the target accumulator to data memory via the X bus

(subject to data saturation, see Section 2.4.2.4 “Data

Space Write Saturation”). Note that for the MACclass

of instructions, the accumulator write-back operation

functions in the same manner, addressing combined

MCU (X and Y) data space though the X bus. For this

class of instructions, the data is always subject to

rounding.

DS70139E-page 24

dsPIC30F2011/2012/3012/3013

2.4.2.4

Data Space Write Saturation

2.4.3

BARREL SHIFTER

In addition to adder/subtracter saturation, writes to data

space may also be saturated but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combined and used to select the appropriate 1.15

fractional value as output to write to data space

memory.

The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators, or the X bus (to support multi-bit

shifts of register or memory data).

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

If the SATDW bit in the CORCON register is set, data

(after rounding or truncation) is tested for overflow and

adjusted accordingly. For input data greater than

0x007FFF, data written to memory is forced to the max-

imum positive 1.15 value, 0x7FFF. For input data less

than 0xFF8000, data written to memory is forced to the

maximum negative 1.15 value, 0x8000. The MSb of the

source (bit 39) is used to determine the sign of the

operand being tested.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right shifts, and bit positions 0 to 16 for left shifts.

If the SATDW bit in the CORCON register is not set, the

input data is always passed through unmodified under

all conditions.

DS70139E-page 25

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 26

dsPIC30F2011/2012/3012/3013

Program memory is addressable by a 24-bit value from

3.0

MEMORY ORGANIZATION

either the 23-bit PC, table instruction Effective Address

(EA), or data space EA, when program space is

mapped into data space as defined by Table 3-1. Note

that the program space address is incremented by two

between successive program words in order to provide

compatibility with data space addressing.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual “ (DS70157).

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for all accesses other than TBLRD/TBLWT,

which uses TBLPAG<7> to determine user or configu-

ration space access. In Table 3-1, Program Space

Address Construction, bit 23 allows access to the

Device ID, the User ID and the Configuration bits.

Otherwise, bit 23 is always clear.

3.1

Program Address Space

The program address space is 4M instruction words.

The program space memory map for the dsPI30F2011/

2012 is shown in Figure 3-1. The program space

memory map for the dsPI30F3012/3013 is shown in

Figure 3-2.

DS70139E-page 27

dsPIC30F2011/2012/3012/3013

FIGURE 3-1:

dsPIC30F2011/2012

PROGRAM SPACE

MEMORY MAP

FIGURE 3-2:

dsPIC30F3012/3013

PROGRAM SPACE

MEMORY MAP

Reset - GOTOInstruction

Reset - Target Address

Reset - GOTOInstruction

Reset - Target Address

000000

000002

000004

000000

000002

000004

Interrupt Vector Table

Vector Tables

00007E

000080

000084

00007E

000080

Reserved

Alternate Vector Table

000084

0000FE

000100

0000FE

000100

User Flash

Program Memory

(4K instructions)

(8K instructions)

001FFE

002000

003FFE

004000

Reserved

(Read ‘0’s)

Reserved

7FFBFE

7FFC00

(Read ‘0’s)

Data EEPROM

(1 Kbyte)

7FFFFE

800000

7FFFFE

800000

Reserved

8005BE

8005C0

8005BE

8005C0

UNITID (32 instr.)

Reserved

UNITID (32 instr.)

Reserved

8005FE

800600

8005FE

800600

F7FFFE

Device Configuration

Registers

Device Configuration

Registers

F80000

F8000E

F80010

F80000

F8000E

F80010

Reserved

DEVID (2)

Reserved

DEVID (2)

FEFFFE

FF0000

FFFFFE

FEFFFE

FF0000

FFFFFE

DS70139E-page 28

dsPIC30F2011/2012/3012/3013

TABLE 3-1:

PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

User

(TBLPAG<7> = 0)

0

PC<22:1>

0

TBLRD/TBLWT

TBLPAG<7:0>

PSVPAG<7:0>

Data EA<15:0>

TBLRD/TBLWT

Configuration

(TBLPAG<7> = 1)

Program Space Visibility User

0

Data EA<14:0>

FIGURE 3-3:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

23 bits

Using

Program

Counter

Program Counter

0

Select

1

EA

Using

Program

Space

PSVPAG Reg

8 bits

Visibility

15 bits

EA

Using

1/0

TBLPAG Reg

8 bits

Table

Instruction

16 bits

User/

Configuration

Space

Select

Byte

Select

24-bit EA

Note:

Program space visibility cannot be used to access bits <23:16> of a word in program memory.

DS70139E-page 29

dsPIC30F2011/2012/3012/3013

A set of table instructions are provided to move byte or

word-sized data to and from program space. See Fig-

ure 3-4 and Figure 3-5.

3.1.1

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

1. TBLRDL:Table Read Low

Word: Read the LS Word of the program address;

P<15:0> maps to D<15:0>.

This architecture fetches 24-bit wide program memory.

Consequently, instructions are always aligned.

However, as the architecture is modified Harvard, data

can also be present in program space.

Byte: Read one of the LSB of the program

address;

There are two methods by which program space can

be accessed: via special table instructions, or through

the remapping of a 16K word program space page into

the upper half of data space (see Section 3.1.2 “Data

Access from Program Memory Using Program

Space Visibility”). The TBLRDLand TBLWTLinstruc-

tions offer a direct method of reading or writing the lsw

of any address within program space, without going

through data space. The TBLRDHand TBLWTHinstruc-

tions are the only method whereby the upper 8 bits of a

program space word can be accessed as data.

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> maps to the destination byte when byte

select = 1.

2. TBLWTL:Table Write Low (refer to Section 5.0

“Flash Program Memory” for details on Flash

Programming)

3. TBLRDH:Table Read High

Word: Read the MS Word of the program address;

P<23:16> maps to D<7:0>; D<15:8> will always

be = 0.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the lsw, and TBLRDH

and TBLWTH access the space which contains the

MSB.

Byte: Read one of the MSB of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH:Table Write High (refer to Section 5.0

“Flash Program Memory” for details on Flash

Programming)

Figure 3-3 shows how the EA is created for table oper-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

FIGURE 3-4:

PROGRAM DATA TABLE ACCESS (lsw)

PC Address

23

8

16

0

0x000000

0x000002

0x000004

0x000006

00000000

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

Program Memory

‘Phantom’ Byte

(read as ‘0’)

TBLRDL.B (Wn<0> = 1)

DS70139E-page 30

dsPIC30F2011/2012/3012/3013

FIGURE 3-5:

PROGRAM DATA TABLE ACCESS (MSB)

TBLRDH.W

PC Address

23

8

0

16

0x000000

0x000002

0x000004

0x000006

00000000

TBLRDH.B (Wn<0> = 0)

Program Memory

‘Phantom’ Byte

(read as ‘0’)

TBLRDH.B (Wn<0> = 1)

Note that by incrementing the PC by 2 for each

program memory word, the LS 15 bits of data space

addresses directly map to the LS 15 bits in the corre-

sponding program space addresses. The remaining

bits are provided by the Program Space Visibility Page

register, PSVPAG<7:0>, as shown in Figure 3-6.

3.1.2

DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/Hinstructions).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”.

For instructions that use PSV which are executed

outside a REPEATloop:

• The following instructions require one instruction

cycle in addition to the specified execution time:

- MACclass of instructions with data operand

prefetch

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetches are required.

- MOVinstructions

- MOV.Dinstructions

• All other instructions require two instruction cycles

in addition to the specified execution time of the

instruction.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP operation uses program space mapping to access

this memory region, Y data space should typically con-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) data.

For instructions that use PSV which are executed

inside a REPEATloop:

• The following instances require two instruction

cycles in addition to the specified execution time

of the instruction:

Although each data space address, 0x8000 and higher,

maps directly into a corresponding program memory

address (see Figure 3-6), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits should be programmed to force an illegal

instruction to maintain machine robustness. Refer to

the “dsPIC30F/33F Programmer’s Reference Manual”

(DS70157) for details on instruction encoding.

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interrupt is serviced

• Any other iteration of the REPEATloop allow the

instruction accessing data, using PSV, to execute

in a single cycle.

DS70139E-page 31

dsPIC30F2011/2012/3012/3013

FIGURE 3-6:

DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

Data Space

Program Space

0x0000

0x000000

PSVPAG⁽¹⁾

15

EA<15> =

0

0x00

8

16

Data

Space

EA

0x8000

23

15

0

Address

EA<15> = 1

0x001200

0x001FFF

Concatenation

15

23

Upper Half of Data

Space is Mapped

into Program Space

0xFFFF

Data Read

BSET CORCON,#2 ; Set PSV bit

MOV

#0x0, W0

W0, PSVPAG

; Set PSVPAG register

0x9200, W0 ; Access program memory location

; using a data space access

Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address.

DS70139E-page 32

dsPIC30F2011/2012/3012/3013

When executing any instruction other than one of the

MACclass of instructions, the X block consists of the 64-

3.2

Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), or as one unified linear address range (for MCU

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions,

the X block consists of the 64-Kbyte data address

space, excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one composite address space.

The MACclass instructions extract the Y address space

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

addressed using W8 and W9. Both address spaces are

concurrently accessed only with the MAC class

instructions.

3.2.1

DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent Linear

Addressing space, X and Y spaces have contiguous

addresses.

The data space memory map for the dsPIC30F2011

and dsPIC30F2012 is shown in Figure 3-7. The data

space memory map for the dsPIC30F3012 and

dsPIC30F3013 is shown in Figure 3-8.

FIGURE 3-7:

dsPIC30F2011/2012 DATA SPACE MEMORY MAP

LSB

Address

MSB

Address

16 bits

MSB

LSB

0x0000

0x0001

2 Kbyte

SFR Space

0x07FE

0x0800

0x07FF

0x0801

8 Kbyte

Near

Data

X Data RAM (X)

Y Data RAM (Y)

0x09FF

0x0A01

0x09FE

0x0A00

1 Kbyte

SRAM Space

Space

0x0BFF

0x0C01

0x0BFE

0x0C00

0x1FFF

0x1FFE

0x8001

0x8000

X Data

Unimplemented (X)

Optionally

Mapped

into Program

Memory

0xFFFF

0xFFFE

DS70139E-page 33

dsPIC30F2011/2012/3012/3013

FIGURE 3-8:

dsPIC30F3012/3013 DATA SPACE MEMORY MAP

LSB

Address

MSB

Address

16 bits

MSB

LSB

SFR Space

0x0000

0x0001

2 Kbyte

SFR Space

0x07FE

0x0800

0x07FF

0x0801

8 Kbyte

Near

Data

X Data RAM (X)

Y Data RAM (Y)

0x0BFF

0x0C01

0x0BFE

0x0C00

2 Kbyte

SRAM Space

Space

0x0FFF

0x1001

0x0FFE

0x1000

0x1FFF

0x1FFE

0x8001

0x8000

X Data

Unimplemented (X)

Optionally

Mapped

into Program

Memory

0xFFFF

0xFFFE

DS70139E-page 34

dsPIC30F2011/2012/3012/3013

FIGURE 3-9:

DATA SPACE FOR MCU AND DSP (MACCLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

UNUSED

Y SPACE

UNUSED

(Y SPACE)

UNUSED

Non-MACClass Ops (Read/Write)

MACClass Ops (Write)

MACClass Ops (Read)

Indirect EA using any W

Indirect EA using W8, W9 Indirect EA using W10, W11

DS70139E-page 35

dsPIC30F2011/2012/3012/3013

3.2.2

DATA SPACES

3.2.3

DATA SPACE WIDTH

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The core data width is 16 bits. All internal registers are

organized as 16-bit wide words. Data space memory is

organized in byte addressable, 16-bit wide blocks.

3.2.4

DATA ALIGNMENT

To help maintain backward compatibility with PIC^®

MCU devices and improve data space memory usage

efficiency, the dsPIC30F instruction set supports both

word and byte operations. Data is aligned in data mem-

ory and registers as words, but all data space EAs

resolve to bytes. Data byte reads read the complete

word that contains the byte, using the LSb of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

accesses are possible from the Y data path as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

The X data space also supports Modulo Addressing for

all instructions, subject to Addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to

provide two concurrent data read paths. No writes

occur across the Y bus. This class of instructions dedi-

cates two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address space is considered a combination of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

As a consequence of this byte accessibility, all Effective

Address calculations (including those generated by the

DSP operations which are restricted to word-sized

data) are internally scaled to step through word-aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode

[Ws++] results in a value of Ws + 1 for byte operations

and Ws + 2 for word operations.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automated circular buffers. Of course, all other instruc-

tions can access the Y data address space through the

X data path as part of the composite linear space.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Should a mis-

aligned read or write be attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed, whereas if it

occurred on a write, the instruction is executed, but the

write does not occur. In either case, a trap is then exe-

cuted, allowing the system and/or user to examine the

machine state prior to execution of the address fault.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-8 and is not user pro-

grammable. Should an EA point to data outside its own

assigned address space, or to a location outside phys-

ical memory, an all zero word/byte is returned. For

example, although Y address space is visible by all

non-MAC instructions using any addressing mode, an

attempt by a MAC instruction to fetch data from that

space using W8 or W9 (X space pointers) returns

0x0000.

FIGURE 3-10:

MSB

DATA ALIGNMENT

LSB

TABLE 3-2:

EFFECT OF INVALID

MEMORY ACCESSES

15

8 7

0

0000

0002

0004

0001

0003

0005

Byte 1

Byte 3

Byte 5

Byte 0

Byte 2

Byte 4

Attempted Operation

Data Returned

EA = an unimplemented address

0x0000

W8 or W9 used to access Y data

space in a MACinstruction

W10 or W11 used to access X

0x0000

data space in a MACinstruction

All Effective Addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

DS70139E-page 36

dsPIC30F2011/2012/3012/3013

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

There is a Stack Pointer Limit register (SPLIM) associ-

ated with the Stack Pointer. SPLIM is uninitialized at

Reset. As is the case for the Stack Pointer, SPLIM<0>

is forced to ‘0’ because all stack operations must be

word aligned. Whenever an Effective Address (EA) is

generated using W15 as a source or destination

pointer, the address thus generated is compared with

the value in SPLIM. If the contents of the Stack Pointer

(W15) and the SPLIM register are equal, and a push

operation is performed, a stack error trap does not

occur. The stack error trap occurs on a subsequent

push operation. Thus, for example, if it is desirable to

cause a stack error trap when the stack grows beyond

address 0x2000 in RAM, initialize the SPLIM with the

value, 0x1FFE.

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words.

3.2.5

NEAR DATA SPACE

An 8-Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly addressable via a 13-bit absolute address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

addressable indirectly. Additionally, the whole of X data

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

3.2.6

SOFTWARE STACK

The dsPIC DSC devices contain a software stack. W15

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word and grows from lower addresses towards

higher addresses. It pre-decrements for stack pops

and post-increments for stack pushes, as shown in

Figure 3-11. Note that for a PC push during any CALL

instruction, the MSB of the PC is zero-extended before

the push, ensuring that the MSB is always clear.

Note:

A PC push during exception processing

concatenates the SRL register to the MSB

of the PC prior to the push.

FIGURE 3-11:

CALLSTACK FRAME

0x0000

15

0

PC<15:0>

000000000

W15 (before CALL)

PC<22:16>

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

DS70139E-page 37

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 40

dsPIC30F2011/2012/3012/3013

4.1.1

FILE REGISTER INSTRUCTIONS

4.0

ADDRESS GENERATOR UNITS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

register instructions employ a working register, W0,

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a register or register pair. The

MOV instruction allows additional flexibility and can

access the entire data space during file register

operation.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual“ (DS70157).

The dsPIC DSC core contains two independent

address generator units: the X AGU and Y AGU. The Y

AGU supports word-sized data reads for the DSP MAC

class of instructions only. The dsPIC DSC AGUs sup-

port three types of data addressing:

4.1.2

MCU INSTRUCTIONS

• Linear Addressing

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

• Modulo (Circular) Addressing

• Bit-Reversed Addressing

where Operand 1 is always a working register (i.e., the

addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory or a 5-bit literal. The result

location can be either a W register or an address

location. The following addressing modes are

supported by MCU instructions:

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressing is only applicable to data space addresses.

4.1

Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of

the addressing modes optimized to support the specific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

Note:

Not all instructions support all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

TABLE 4-1:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

Description

The address of the File register is specified explicitly.

Addressing Mode

File Register Direct

Register Direct

The contents of a register are accessed directly.

The contents of Wn forms the EA.

Register Indirect

Register Indirect Post-modified

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

Register Indirect with Literal Offset

The sum of Wn and a literal forms the EA.

DS70139E-page 41

dsPIC30F2011/2012/3012/3013

In summary, the following addressing modes are

supported by the MACclass of instructions:

4.1.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

• Register Indirect

Move instructions and the DSP accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

addressing modes supported by most MCU instruc-

tions, move and accumulator instructions also support

Register Indirect with Register Offset Addressing

mode, also referred to as Register Indexed mode.

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5

OTHER INSTRUCTIONS

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (register offset)

field is shared between both source and

destination (but typically only used by

one).

Besides the various addressing modes outlined above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as NOP, do not have any

operands.

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direct

4.2

Modulo Addressing

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

Modulo Addressing is a method of providing an auto-

mated means to support circular data buffers using

hardware. The objective is to remove the need for soft-

ware to perform data address boundary checks when

executing tightly looped code, as is typical in many

DSP algorithms.

• 16-bit Literal

Modulo Addressing can operate in either data or pro-

gram space (since the data pointer mechanism is

essentially the same for both). One circular buffer can

be supported in each of the X (which also provides the

pointers into program space) and Y data spaces. Mod-

ulo Addressing can operate on any W register pointer.

However, it is not advisable to use W14 or W15 for Mod-

ulo Addressing since these two registers are used as

the Stack Frame Pointer and Stack Pointer, respec-

tively.

Note:

Not all instructions support all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

4.1.4

MACINSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also

referred to as MACinstructions, utilize a simplified set of

addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

In general, any particular circular buffer can only be

configured to operate in one direction, as there are cer-

tain restrictions on the buffer Start address (for incre-

menting buffers), or end address (for decrementing

buffers) based upon the direction of the buffer.

The two source operand prefetch registers must belong

to the set {W8, W9, W10, W11}. For data reads, W8

and W9 are always directed to the X RAGU. W10 and

W11 are always directed to the Y AGU. The effective

addresses generated (before and after modification)

must, therefore, be valid addresses within X data space

for W8 and W9 and Y data space for W10 and W11.

The only exception to the usage restrictions is for buff-

ers that have a power-of-2 length. As these buffers sat-

isfy the Start and end address criteria, they can operate

in a Bidirectional mode (i.e., address boundary checks

are performed on both the lower and upper address

boundaries).

Note:

Register Indirect with Register Offset

addressing is only available for W9 (in X

space) and W11 (in Y space).

DS70139E-page 42

dsPIC30F2011/2012/3012/3013

4.2.1

START AND END ADDRESS

4.2.2

W ADDRESS REGISTER

SELECTION

The Modulo Addressing scheme requires that a start-

ing and an ending address be specified and loaded

into the 16-bit Modulo Buffer Address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The Modulo and Bit-Reversed Addressing Control reg-

ister, MODCON<15:0>, contains enable flags as well

as a W register field to specify the W address registers.

The XWM and YWM fields select which registers oper-

ate with Modulo Addressing. If XWM = 15, X RAGU

and X WAGU Modulo Addressing is disabled. Similarly,

if YWM = 15, Y AGU Modulo Addressing is disabled.

Note:

Y space Modulo Addressing EA calcula-

tions assume word-sized data (LSb of

every EA is always clear).

The X Address Space Pointer W register (XWM), to

which Modulo Addressing is to be applied, is stored in

MODCON<3:0> (see Table 3-3). Modulo Addressing is

enabled for X data space when XWM is set to any value

other than ‘15’ and the XMODEN bit is set at

MODCON<15>.

The length of a circular buffer is not directly specified. It

is determined by the difference between the corre-

sponding Start and end addresses. The maximum pos-

sible length of the circular buffer is 32K words

(64 Kbytes).

The Y Address Space Pointer W register (YWM), to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo Addressing is enabled for Y

data space when YWM is set to any value other than

‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1:

MODULO ADDRESSING OPERATION EXAMPLE

Byte

Address

MOV

#0x1100,W0

W0,XMODSRT

#0x1163,W0

W0,MODEND

#0x8001,W0

W0,MODCON

;set modulo start address

;set modulo end address

;enable W1, X AGU for modulo

;W0 holds buffer fill value

;point W1 to buffer

0x1100

MOV

#0x0000,W0

#0x1110,W1

DO

AGAIN,#0x31 ;fill the 50 buffer locations

MOV

W0,[W1++]

;fill the next location

;increment the fill value

AGAIN: INC W0,W0

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

DS70139E-page 43

dsPIC30F2011/2012/3012/3013

If the length of a bit-reversed buffer is M = 2^Nbytes,

then the last ‘N’ bits of the data buffer Start address

must be zeros.

4.2.3

MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W regis-

ter. It is important to realize that the address bound-

aries check for addresses less than, or greater than the

upper (for incrementing buffers), and lower (for decre-

menting buffers) boundary addresses (not just equal

to). Address changes may, therefore, jump beyond

boundaries and still be adjusted correctly.

XB<14:0> is the bit-reversed address modifier or ‘pivot

point’ which is typically a constant. In the case of an

FFT computation, its value is equal to half of the FFT

data buffer size.

Note:

All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note:

The modulo corrected Effective Address is

written back to the register only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the Effective Address.

When an address offset (e.g., [W7+W2]) is

used, Modulo address correction is per-

formed, but the contents of the register

remain unchanged.

When enabled, Bit-Reversed Addressing is only exe-

cuted for register indirect with pre-increment or post-

increment addressing and word-sized data writes. It

does not function for any other addressing mode or for

byte-sized data. Normal addresses are generated

instead. When Bit-Reversed Addressing is active, the

W address pointer is always added to the address

modifier (XB) and the offset associated with the Regis-

ter Indirect Addressing mode is ignored. In addition, as

word-sized data is a requirement, the LSb of the EA is

ignored (and always clear).

4.3

Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

re-ordering for radix-2 FFT algorithms. It is supported

by the X AGU for data writes only.

Note:

Modulo Addressing and Bit-Reversed

Addressing should not be enabled

together. In the event that the user attempts

to do this, Bit-Reversed Addressing

assumes priority when active for the X

WAGU, and X WAGU Modulo Addressing

is disabled. However, Modulo Addressing

continues to function in the X RAGU.

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed. The

address source and destination are kept in normal order.

Thus, the only operand requiring reversal is the modifier.

4.3.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the bit-reversed pointer.

1. BWM (W register selection) in the MODCON

register is any value other than ‘15’ (the stack

cannot be accessed using Bit-Reversed

Addressing) and

2. the BREN bit is set in the XBREV register and

3. the addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

DS70139E-page 44

dsPIC30F2011/2012/3012/3013

FIGURE 4-2:

BIT-REVERSED ADDRESS EXAMPLE

Sequential Address

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1

0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

b2 b3 b4

0

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1

Bit-Reversed Address

Pivot Point

XB = 0x0008 for a 16-word Bit-Reversed Buffer

TABLE 4-2:

BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3

A2

A1

A0

Decimal

A3

A2

A1

A0

Decimal

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

2

4

3

12

2

4

5

10

6

7

14

1

8

9

10

11

12

13

14

15

5

13

3

11

7

15

TABLE 4-3:

BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size (Words)

XB<14:0> Bit-Reversed Address Modifier Value

1024

512

256

128

64

32

16

8

0x0200

0x0100

0x0080

0x0040

0x0020

0x0010

0x0008

0x0004

0x0002

0x0001

4

2

DS70139E-page 45

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 46

dsPIC30F2011/2012/3012/3013

5.2

Run-Time Self-Programming

(RTSP)

5.0

FLASH PROGRAM MEMORY

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

RTSP is accomplished using TBLRD (table read) and

TBLWT(table write) instructions.

With RTSP, the user may erase program memory, 32

instructions (96 bytes) at a time and can write program

memory data, 32 instructions (96 bytes) at a time.

The dsPIC30F family of devices contains internal pro-

gram Flash memory for executing user code. There are

two methods by which the user can program this

memory:

5.3

Table Instruction Operation

Summary

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

Word or Byte mode.

1. Run-Time Self-Programming (RTSP)

2. In-Circuit Serial Programming™ (ICSP™)

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan access program memory in Word or

Byte mode.

5.1

In-Circuit Serial Programming

(ICSP)

dsPIC30F devices can be serially programmed while in

the end application circuit. This is simply done with two

lines for Programming Clock and Programming Data

(which are named PGC and PGD respectively), and

three other lines for Power (VDD), Ground (VSS) and

Master Clear (MCLR). This allows customers to manu-

facture boards with unprogrammed devices, and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

A 24-bit program memory address is formed using

bits<7:0> of the TBLPAG register and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

FIGURE 5-1:

ADDRESSING FOR TABLE AND NVM REGISTERS

24 bits

Using

Program

Counter

Program Counter

0

NVMADR Reg EA

Using

NVMADR

Addressing

1/0 NVMADRU Reg

8 bits

16 bits

Working Reg EA

Using

Table

Instruction

1/0

TBLPAG Reg

8 bits

16 bits

Byte

Select

User/Configuration

Space Select

24-bit EA

DS70139E-page 47

dsPIC30F2011/2012/3012/3013

5.4

RTSP Operation

5.5

Control Registers

The dsPIC30F Flash program memory is organized

into rows and panels. Each row consists of 32 instruc-

tions or 96 bytes. Each panel consists of 128 rows or

4K x 24 instructions. RTSP allows the user to erase one

row (32 instructions) at a time and to program four

instructions at one time. RTSP may be used to program

multiple program memory panels, but the Table Pointer

must be changed at each panel boundary.

The four SFRs used to read and write the program

Flash memory are:

• NVMCON

• NVMADR

• NVMADRU

• NVMKEY

5.5.1

NVMCON REGISTER

Each panel of program memory contains write latches

that hold 32 instructions of programming data. Prior to

the actual programming operation, the write data must

be loaded into the panel write latches. The data to be

programmed into the panel is loaded in sequential

order into the write latches; instruction 0, instruction 1,

etc. The instruction words loaded must always be from

a 32 address boundary.

The NVMCON register controls which blocks are to be

erased, which memory type is to be programmed, and

start of the programming cycle.

5.5.2

NVMADR REGISTER

The NVMADR register is used to hold the lower two

bytes of the Effective Address. The NVMADR register

captures the EA<15:0> of the last table instruction that

has been executed and selects the row to write.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the write latches. Programming is performed by

setting the special bits in the NVMCON register. 32

TBLWTL and four TBLWTH instructions are required to

load the 32 instructions. If multiple panel programming

is required, the Table Pointer needs to be changed and

the next set of multiple write latches written.

5.5.3

NVMADRU REGISTER

The NVMADRU register is used to hold the upper byte

of the Effective Address. The NVMADRU register cap-

tures the EA<23:16> of the last table instruction that

has been executed.

All of the table write operations are single-word writes

(2 instruction cycles), because only the table latches

are written. A programming cycle is required for

programming each row.

5.5.4

NVMKEY REGISTER

NVMKEY is a write-only register that is used for write

protection. To start a programming or an erase

sequence, the user must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 5.6

“Programming Operations” for further details.

The Flash Program Memory is readable, writable and

erasable during normal operation over the entire VDD

range.

Note:

The user can also directly write to the

NVMADR and NVMADRU registers to

specify a program memory address for

erasing or programming.

DS70139E-page 48

dsPIC30F2011/2012/3012/3013

4. Write 32 instruction words of data from data

5.6

Programming Operations

RAM “image” into the program Flash write

latches.

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 2 msec in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation and the WR bit is automatically

cleared when the operation is finished.

5. Program 32 instruction words into program

Flash.

a) Setup NVMCON register for multi-word,

program Flash, program, and set WREN

bit.

b) Write ‘55’ to NVMKEY.

5.6.1

PROGRAMMING ALGORITHM FOR

PROGRAM FLASH

c) Write ‘AA’ to NVMKEY.

d) Set the WR bit. This begins program cycle.

e) CPU stalls for duration of the program cycle.

The user can erase or program one row of program

Flash memory at a time. The general process is:

f) The WR bit is cleared by the hardware

when program cycle ends.

1. Read one row of program Flash (32 instruction

words) and store into data RAM as a data

“image”.

6. Repeat steps 1 through 5 as needed to program

desired amount of program Flash memory.

2. Update the data image with the desired new

data.

5.6.2

ERASING A ROW OF PROGRAM

MEMORY

3. Erase program Flash row.

Example 5-1 shows a code sequence that can be used

to erase a row (32 instructions) of program memory.

a) Setup NVMCON register for multi-word,

program Flash, erase, and set WREN bit.

b) Write address of row to be erased into

NVMADRU/NVMDR.

c) Write ‘55’ to NVMKEY.

d) Write ‘AA’ to NVMKEY.

e) Set the WR bit. This begins erase cycle.

f) CPU stalls for the duration of the erase cycle.

g) The WR bit is cleared when erase cycle

ends.

EXAMPLE 5-1:

ERASING A ROW OF PROGRAM MEMORY

; Setup NVMCON for erase operation, multi word write

; program memory selected, and writes enabled

MOV

#0x4041,W0

W0 NVMCON

;

; Init NVMCON SFR

,

; Init pointer to row to be ERASED

MOV

DISI

#tblpage(PROG_ADDR),W0

;

W0 NVMADRU

; Initialize PM Page Boundary SFR

; Intialize in-page EA[15:0] pointer

; Initialize NVMADR SFR

; Block all interrupts with priority <7 for

; next 5 instructions

,

#tbloffset(PROG_ADDR),W0

W0, NVMADR

#5

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

; Write the 0x55 key

;

; Write the 0xAA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

,

#0xAA,W1

W1 NVMKEY

,

NVMCON,#WR

DS70139E-page 49

dsPIC30F2011/2012/3012/3013

5.6.3

LOADING WRITE LATCHES

5.6.4

INITIATING THE PROGRAMMING

SEQUENCE

Example 5-2 shows a sequence of instructions that

can be used to load the 96 bytes of write latches. 32

TBLWTL and 32 TBLWTH instructions are needed to

load the write latches selected by the Table Pointer.

For protection, the write initiate sequence for NVMKEY

must be used to allow any erase or program operation

to proceed. After the programming command has been

executed, the user must wait for the programming time

until programming is complete. The two instructions fol-

lowing the start of the programming sequence should

be NOPs as shown in Example 5-3.

EXAMPLE 5-2:

LOADING WRITE LATCHES

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000,W0

;

W0 TBLPAG

; Initialize PM Page Boundary SFR

; An example program memory address

,

#0x6000,W0

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0,W2

#HIGH_BYTE_0,W3

;

TBLWTL W2 [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

,

TBLWTH W3 [W0++]

,

; 1st_program_word

MOV

#LOW_WORD_1,W2

#HIGH_BYTE_1,W3

;

TBLWTL W2 [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

,

TBLWTH W3 [W0++]

,

;

2nd_program_word

MOV

#LOW_WORD_2,W2

#HIGH_BYTE_2,W3

;

TBLWTL W2 [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

,

TBLWTH W3 [W0++]

,

•

; 31st_program_word

MOV

#LOW_WORD_31,W2

#HIGH_BYTE_31,W3

;

TBLWTL W2 [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

,

TBLWTH W3 [W0++]

,

Note: In Example 5-2, the contents of the upper byte of W3 has no effect.

EXAMPLE 5-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7 for

; next 5 instructions

;

; Write the 0x55 key

;

; Write the 0xAA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

,

#0xAA,W1

W1 NVMKEY

,

NVMCON,#WR

DS70139E-page 50

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 52

dsPIC30F2011/2012/3012/3013

Control bit WR initiates write operations similar to pro-

6.0

DATA EEPROM MEMORY

gram Flash writes. This bit cannot be cleared, only set,

in software. They are cleared in hardware at the com-

pletion of the write operation. The inability to clear the

WR bit in software prevents the accidental or

premature termination of a write operation.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual“ (DS70157).

The WREN bit, when set, allows a write operation. On

power-up, the WREN bit is clear. The WRERR bit is set

when a write operation is interrupted by a MCLR Reset

or a WDT Time-out Reset during normal operation. In

these situations, following Reset, the user can check

the WRERR bit and rewrite the location. The address

register NVMADR remains unchanged.

The data EEPROM memory is readable and writable

during normal operation over the entire VDD range. The

data EEPROM memory is directly mapped in the

program memory address space.

The four SFRs used to read and write the program

Flash memory are used to access data EEPROM

memory, as well. As described in Section 5.5 “Control

Registers”, these registers are:

Note:

Interrupt flag bit NVMIF in the IFS0 regis-

ter is set when write is complete. It must be

cleared in software.

• NVMCON

• NVMADR

• NVMADRU

• NVMKEY

6.1

Reading the Data EEPROM

A TBLRD instruction reads a word at the current pro-

gram word address. This example uses W0 as a

pointer to data EEPROM. The result is placed in

register W4 as shown in Example 6-1.

The EEPROM data memory allows read and write of

single words and 16-word blocks. When interfacing to

data memory, NVMADR, in conjunction with the

NVMADRU register, are used to address the

EEPROM location being accessed. TBLRDL and

TBLWTLinstructions are used to read and write data

EEPROM. The dsPIC30F devices have up to 8 Kbytes

(4K words) of data EEPROM with an address range

from 0x7FF000 to 0x7FFFFE.

EXAMPLE 6-1:

DATA EEPROM READ

MOV

#LOW_ADDR_WORD,W0 ; Init Pointer

#HIGH_ADDR_WORD,W1

W1 TBLPAG

,

TBLRDL [ W0 ], W4

; read data EEPROM

A word write operation should be preceded by an erase

of the corresponding memory location(s). The write typ-

ically requires 2 ms to complete, but the write time

varies with voltage and temperature.

A program or erase operation on the data EEPROM

does not stop the instruction flow. The user is respon-

sible for waiting for the appropriate duration of time

before initiating another data EEPROM write/erase

operation. Attempting to read the data EEPROM while

a programming or erase operation is in progress results

in unspecified data.

DS70139E-page 53

dsPIC30F2011/2012/3012/3013

6.2

Erasing Data EEPROM

6.2.1

ERASING A BLOCK OF DATA

EEPROM

In order to erase a block of data EEPROM, the

NVMADRU and NVMADR registers must initially point

to the block of memory to be erased. Configure

NVMCON for erasing a block of data EEPROM and

set the WR and WREN bits in the NVMCON register.

Setting the WR bit initiates the erase, as shown in

Example 6-2.

EXAMPLE 6-2:

DATA EEPROM BLOCK ERASE

; Select data EEPROM block, WR, WREN bits

MOV

#0x4045,W0

W0 NVMCON

; Initialize NVMCON SFR

,

; Start erase cycle by setting WR after writing key sequence

DISI

#5

; Block all interrupts with priority <7 for

; next 5 instructions

MOV

BSET

NOP

#0x55,W0

;

W0 NVMKEY

; Write the 0x55 key

;

; Write the 0xAA key

; Initiate erase sequence

,

#0xAA,W1

W1 NVMKEY

,

NVMCON,#WR

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

6.2.2

ERASING A WORD OF DATA

EEPROM

The NVMADRU and NVMADR registers must point to

the block. Select WR a block of data Flash and set the

WR and WREN bits in the NVMCON register. Setting

the WR bit initiates the erase, as shown in Example 6-

3.

EXAMPLE 6-3:

DATA EEPROM WORD ERASE

; Select data EEPROM word, WR, WREN bits

MOV

#0x4044,W0

W0 NVMCON

,

; Start erase cycle by setting WR after writing key sequence

DISI

#5

; Block all interrupts with priority <7 for

; next 5 instructions

MOV

BSET

NOP

#0x55,W0

;

W0 NVMKEY

; Write the 0x55 key

;

; Write the 0xAA key

; Initiate erase sequence

,

#0xAA,W1

W1 NVMKEY

,

NVMCON,#WR

; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete

DS70139E-page 54

dsPIC30F2011/2012/3012/3013

The write does not initiate if the above sequence is not

6.3

Writing to the Data EEPROM

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

To write an EEPROM data location, the following

sequence must be followed:

1. Erase data EEPROM word.

a) Select word, data EEPROM erase, and set

WREN bit in NVMCON register.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution. The WREN bit should be kept clear at all times

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

b) Write address of word to be erased into

NVMADR.

c) Enable NVM interrupt (optional).

d) Write ‘55’ to NVMKEY.

After a write sequence has been initiated, clearing the

WREN bit does not affect the current write cycle. The

WR bit is inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

e) Write ‘AA’ to NVMKEY.

f) Set the WR bit. This begins erase cycle.

g) Either poll NVMIF bit or wait for NVMIF

interrupt.

h) The WR bit is cleared when the erase cycle

ends.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Nonvolatile Memory Write

Complete Interrupt Flag bit (NVMIF) is set. The user

may either enable this interrupt or poll this bit. NVMIF

must be cleared by software.

2. Write data word into data EEPROM write

latches.

3. Program 1 data word into data EEPROM.

a) Select word, data EEPROM program, and

set WREN bit in NVMCON register.

6.3.1

WRITING A WORD OF DATA

EEPROM

b) Enable NVM write done interrupt (optional).

c) Write ‘55’ to NVMKEY.

Once the user has erased the word to be programmed,

then a table write instruction is used to write one write

latch, as shown in Example 6-4.

d) Write ‘AA’ to NVMKEY.

e) Set the WR bit. This begins program cycle.

f) Either poll NVMIF bit or wait for NVM

interrupt.

6.3.2

WRITING A BLOCK OF DATA

EEPROM

g) The WR bit is cleared when the write cycle

ends.

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

program the block.

EXAMPLE 6-4:

DATA EEPROM WORD WRITE

; Point to data memory

MOV

#LOW_ADDR_WORD,W0

#HIGH_ADDR_WORD,W1

; Init pointer

MOV

W1 TBLPAG

,

MOV

#LOW(WORD),W2

; Get data

TBLWTL

W2 [ W0]

; Write data

,

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV

#0x4004,W0

W0 NVMCON

,

; Operate key to allow write operation

DISI

#5

; Block all interrupts with priority <7 for

; next 5 instructions

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

; Write the 0x55 key

,

#0xAA,W1

W1 NVMKEY

; Write the 0xAA key

; Initiate program sequence

,

NVMCON,#WR

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

DS70139E-page 55

dsPIC30F2011/2012/3012/3013

EXAMPLE 6-5:

DATA EEPROM BLOCK WRITE

MOV

#LOW_ADDR_WORD,W0 ; Init pointer

#HIGH_ADDR_WORD,W1

MOV

W1 TBLPAG

,

MOV

#data1,W2

; Get 1st data

TBLWTL

MOV

W2 [ W0]++

#data2,W2

; write data

; Get 2nd data

,

TBLWTL

MOV

W2 [ W0]++

#data3,W2

; write data

; Get 3rd data

,

TBLWTL

MOV

W2 [ W0]++

#data4,W2

; write data

; Get 4th data

,

TBLWTL

MOV

W2 [ W0]++

#data5,W2

; write data

; Get 5th data

,

TBLWTL

MOV

W2 [ W0]++

#data6,W2

; write data

; Get 6th data

,

TBLWTL

MOV

W2 [ W0]++

#data7,W2

; write data

; Get 7th data

,

TBLWTL

MOV

W2 [ W0]++

#data8,W2

; write data

; Get 8th data

,

TBLWTL

MOV

W2 [ W0]++

#data9,W2

; write data

; Get 9th data

,

TBLWTL

MOV

W2 [ W0]++

#data10,W2

; write data

; Get 10th data

,

TBLWTL

MOV

W2 [ W0]++

#data11,W2

; write data

; Get 11th data

,

TBLWTL

MOV

W2 [ W0]++

#data12,W2

; write data

; Get 12th data

,

TBLWTL

MOV

W2 [ W0]++

#data13,W2

; write data

; Get 13th data

,

TBLWTL

MOV

W2 [ W0]++

#data14,W2

; write data

; Get 14th data

,

TBLWTL

MOV

W2 [ W0]++

#data15,W2

; write data

; Get 15th data

,

TBLWTL

MOV

W2 [ W0]++

#data16,W2

; write data

; Get 16th data

,

TBLWTL

MOV

W2 [ W0]++

#0x400A,W0

; write data. The NVMADR captures last table access address.

; Select data EEPROM for multi word op

; Operate Key to allow program operation

; Block all interrupts with priority <7 for

; next 5 instructions

,

W0 NVMCON

,

DISI

#5

MOV

BSET

NOP

#0x55,W0

W0 NVMKEY

; Write the 0x55 key

,

#0xAA,W1

W1 NVMKEY

; Write the 0xAA key

; Start write cycle

,

NVMCON,#WR

6.4

Write Verify

6.5

Protection Against Spurious Write

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared;

also, the Power-up Timer prevents EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

DS70139E-page 56

dsPIC30F2011/2012/3012/3013

Any bit and its associated data and Control registers

that are not valid for a particular device are disabled.

7.0

I/O PORTS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual “ (DS70046).

That means the corresponding LATx and TRISx

registers and the port pin read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 7-1 shows how ports are shared

with other peripherals and the associated I/O cell (pad)

to which they are connected.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

7.1

Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is disabled. If a peripheral is enabled, but the peripheral

is not actively driving a pin, that pin can be driven by a

port.

The format of the registers for the shared ports,

(PORTB, PORTC, PORTD and PORTF) are shown in

Table 7-1 through Table 7-6.

Note:

The actual bits in use vary between

devices.

All port pins have three registers directly associated

with the operation of the port pin. The Data Direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch (LATx). Reads from

the port (PORTx), read the port pins and writes to the

port pins, write the latch (LATx).

FIGURE 7-1:

BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

Output Multiplexers

Peripheral Module

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O Cell

1

0

Output Enable

1

0

Output Data

PIO Module

Read TRIS

I/O Pad

Data Bus

WR TRIS

D

Q

CK

TRIS Latch

D

Q

WR LAT +

WR Port

CK

Data Latch

Read LAT

Read Port

Input Data

DS70139E-page 57

dsPIC30F2011/2012/3012/3013

7.2.1

I/O PORT WRITE/READ TIMING

7.2

Configuring Analog Port Pins

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) is

converted.

EXAMPLE 7-1:

PORT WRITE/READ

EXAMPLE

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level).

MOV #0xF0, W0; Configure PORTB<7:4>

; as inputs

MOV W0, TRISB; and PORTB<3:0> as outputs

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

NOP

; additional instruction cycle

btss PORTB, #7; bit test RB7 and skip if set

DS70139E-page 58

dsPIC30F2011/2012/3012/3013

7.3

Input Change Notification Module

The input change notification module provides the

dsPIC30F devices the ability to generate interrupt

requests to the processor, in response to a change of

state on selected input pins. This module is capable of

detecting input change of states even in Sleep mode,

when the clocks are disabled. There are up to 10 exter-

nal signals (CN0 through CN7, CN17 and CN18) that

may be selected (enabled) for generating an interrupt

request on a change of state.

TABLE 7-7:

INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2011/3012 (BITS 7-0)

SFR

Name

Addr.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

CNEN1

CNEN2

CNPU1

CNPU2

00C0

00C2

00C4

00C6

CN7IE

—

CN6IE

—

CN5IE

—

CN4IE

—

CN3IE

—

CN2IE

—

CN1IE

—

CN0IE

—

0000 0000 0000 0000

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE

CN0PUE 0000 0000 0000 0000

0000 0000 0000 0000

—

TABLE 7-8:

INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2012/3013 (BITS 7-0)

SFR

Name

Addr.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

CNEN1

CNEN2

CNPU1

CNPU2

00C0

00C2

00C4

00C6

CN7IE

—

CN6IE

—

CN5IE

—

CN4IE

—

CN3IE

—

CN2IE

CN1IE

CN0IE

—

0000 0000 0000 0000

CN18IE

CN17IE

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE

CN18PUE CN17PUE

CN0PUE 0000 0000 0000 0000

0000 0000 0000 0000

—

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

DS70139E-page 61

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 62

dsPIC30F2011/2012/3012/3013

• INTCON1<15:0>, INTCON2<15:0>

Global interrupt control functions are derived from

8.0

INTERRUPTS

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external

interrupt request signal behavior and the use of

the alternate vector table.

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit. User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

The dsPIC30F sensor family has up to 21 interrupt

sources and 4 processor exceptions (traps) which must

be arbitrated based on a priority scheme.

The CPU is responsible for reading the Interrupt Vector

Table (IVT) and transferring the address contained in

the interrupt vector to the program counter. The inter-

rupt vector is transferred from the program data bus

into the program counter via a 24-bit wide multiplexer

on the input of the program counter.

All interrupt sources can be user assigned to one of 7

priority levels, 1 through 7, via the IPCx registers. Each

interrupt source is associated with an interrupt vector,

as shown in Table 8-1. Levels 7 and 1 represent the

highest and lowest maskable priorities, respectively.

The Interrupt Vector Table (IVT) and Alternate Interrupt

Vector Table (AIVT) are placed near the beginning of

program memory (0x000004). The IVT and AIVT are

shown in Figure 8-1.

Note:

Assigning a priority level of ‘0’ to an inter-

rupt source is equivalent to disabling that

interrupt.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prevented. Thus, if an interrupt is currently

being serviced, processing of a new interrupt is pre-

vented even if the new interrupt is of higher priority than

the one currently being serviced.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions

before they are presented to the processor core. The

peripheral interrupts and traps are enabled, prioritized

and controlled using centralized Special Function Reg-

isters:

Note:

The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals and they are

cleared via software.

Certain interrupts have specialized control bits for fea-

tures like edge or level triggered interrupts, interrupt-

on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All interrupt enable control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

• IPC0<15:0>... IPC10<7:0>

When an interrupt is serviced, the PC is loaded with the

address stored in the vector location in program mem-

ory that corresponds to the interrupt. There are 63 dif-

ferent vectors within the IVT (refer to Table 8-1). These

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Table 8-1).

These locations contain 24-bit addresses, and in order

to preserve robustness, an address error trap takes

place if the PC attempts to fetch any of these words

during normal execution. This prevents execution of

random data as a result of accidentally decrementing a

PC into vector space, accidentally mapping a data

space address into vector space, or the PC rolling over

to 0x000000 after reaching the end of implemented

program memory space. Execution of a GOTOinstruc-

tion to this vector space also generates an address

error trap.

The user assignable priority level associated with

each of these 41 interrupts is held centrally in

these eleven registers.

• IPL<3:0>

The current CPU priority level is explicitly stored

in the IPL bits. IPL<3> is present in the CORCON

register, whereas IPL<2:0> are present in the

STATUS register (SR) in the processor core.

DS70139E-page 63

dsPIC30F2011/2012/3012/3013

TABLE 8-1:

INTERRUPT VECTOR TABLE

8.1

Interrupt Priority

INT

Vector

The user assignable interrupt priority (IP<2:0>) bits for

each individual interrupt source are located in the LS

3 bits of each nibble within the IPCx register(s). Bit 3 of

each nibble is not used and is read as a ‘0’. These bits

define the priority level assigned to a particular interrupt

by the user.

Interrupt Source

Number Number

Highest Natural Order Priority

0

1

8

INT0 — External Interrupt 0

IC1 — Input Capture 1

OC1 — Output Compare 1

T1 — Timer 1

9

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Note:

The user selectable priority levels start at

0 as the lowest priority and level 7 as the

highest priority.

3

4

IC2 — Input Capture 2

OC2 — Output Compare 2

T2 — Timer 2

5

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

6

7

T3 — Timer 3

8

SPI1

9

U1RX — UART1 Receiver

U1TX — UART1 Transmitter

ADC — ADC Convert Done

NVM — NVM Write Complete

10

11

12

13

14

15

16

17-22

23

24

25

26-41

42

43-53

Table 8-1 lists the interrupt numbers and interrupt

sources for the dsPIC30F2011/2012/3012/3013

devices and their associated vector numbers.

2

SI2C — I C™ Slave Interrupt

2

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

MI2C — I C Master Interrupt

Input Change Interrupt

INT1 — External Interrupt 1

2: The natural order priority number is the

25-30 Reserved

same as the INT number.

31

32

33

INT2 — External Interrupt 2

The ability for the user to assign every interrupt to one

of seven priority levels means that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low

Voltage Detect) can be given a priority of 7. The INT0

(External Interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

U2RX* — UART2 Receiver

U2TX* — UART2 Transmitter

34-49 Reserved

50

LVD — Low-Voltage Detect

51-61 Reserved

Lowest Natural Order Priority

*

Only the dsPIC30F3013 has UART2 and the U2RX,

U2TX interrupts. These locations are reserved for

the dsPIC30F2011/2012/3012.

DS70139E-page 64

dsPIC30F2011/2012/3012/3013

8.2

Reset Sequence

8.3

Traps

A Reset is not a true exception because the interrupt

controller is not involved in the Reset process. The pro-

cessor initializes its registers in response to a Reset

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion immediately followed by the address target for the

GOTOinstruction. The processor executes the GOTOto

the specified address and then begins operation at the

specified target (start) address.

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority as shown in Figure 8-1. They

are intended to provide the user a means to correct

erroneous operation during debug and when operating

within the application.

Note:

If the user does not intend to take correc-

tive action in the event of a trap error

condition, these vectors must be loaded

with the address of a default handler that

simply contains the RESET instruction. If,

on the other hand, one of the vectors

containing an invalid address is called, an

address error trap is generated.

8.2.1

RESET SOURCES

In addition to external Reset and Power-on Reset

(POR), there are 6 sources of error conditions which

‘trap’ to the Reset vector.

Note that many of these trap conditions can only be

detected when they occur. Consequently, the question-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

• Watchdog Time-out:

The watchdog has timed out, indicating that the

processor is no longer executing the correct flow

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer causes a Reset.

There are 8 fixed priority levels for traps: Level 8

through Level 15, which implies that the IPL3 is always

set during processing of a trap.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes

results in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

If the user is not currently executing a trap, and he sets

the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all

interrupts are disabled, but traps can still be processed.

8.3.1

TRAP SOURCES

• Brown-out Reset (BOR):

The following traps are provided with increasing prior-

ity. However, since all traps can be nested, priority has

little effect.

A momentary dip in the power supply to the

device has been detected which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap conditions

simultaneously causes a Reset.

Math Error Trap:

The math error trap executes under the following three

circumstances:

1. If an attempt is made to divide by zero, the

divide operation is aborted on a cycle boundary

and the trap is taken.

2. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes an overflow from bit 31 and the accu-

mulator guard bits are not utilized.

3. If enabled, a math error trap is taken when an

arithmetic operation on either accumulator A or

B causes a catastrophic overflow from bit 39 and

all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap occurs.

DS70139E-page 65

dsPIC30F2011/2012/3012/3013

Address Error Trap:

Stack Error Trap:

This trap is initiated when any of the following

circumstances occurs:

This trap is initiated under the following conditions:

1. The Stack Pointer is loaded with a value which

is greater than the (user programmable) limit

value written into the SPLIM register (stack

overflow).

1. A misaligned data word access is attempted.

2. A data fetch from our unimplemented data

memory location is attempted.

2. The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

Note:

In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

8.3.2

HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 8-2 is implemented,

which may require the user to check if other traps are

pending, in order to completely correct the Fault.

5. Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruction, where literal

is an unimplemented program memory address.

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

‘Soft’ traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be acknowledged

before code execution of any type can continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict occurs.

The device is automatically Reset in a hard trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

DS70139E-page 66

dsPIC30F2011/2012/3012/3013

FIGURE 8-1:

TRAP VECTORS

FIGURE 8-2:

INTERRUPT STACK

FRAME

Reset - GOTOInstruction

Reset - GOTOAddress

0x000000

0x000002

0x000004

0x0000 15

0

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Vector

IVT

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

W15 (before CALL)

W15 (after CALL)

PC<15:0>

SRL IPL3 PC<22:16>

0x000014

—

Interrupt 52 Vector

Interrupt 53 Vector

Reserved

POP :[--W15]

PUSH:[W15++]

0x00007E

0x000080

0x000082

Reserved

0x000084

Reserved

Oscillator Fail Trap Vector

Stack Error Trap Vector

Address Error Trap Vector

Math Error Trap Vector

Reserved Vector

Note 1: The user can always lower the priority

level by writing a new value into SR. The

Interrupt Service Routine must clear the

interrupt flag bits in the IFSx register

before lowering the processor interrupt

priority, in order to avoid recursive

interrupts.

AIVT

Reserved Vector

0x000094

0x0000FE

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

2: The IPL3 bit (CORCON<3>) is always

clear when interrupts are being pro-

cessed. It is set only during execution of

traps.

8.4

Interrupt Sequence

All interrupt event flags are sampled in the beginning of

each instruction cycle by the IFSx registers. A pending

Interrupt Request (IRQ) is indicated by the flag bit

being equal to a ‘1’ in an IFSx register. The IRQ causes

an interrupt to occur if the corresponding bit in the Inter-

rupt Enable (IECx) register is set. For the remainder of

the instruction cycle, the priorities of all pending inter-

rupt requests are evaluated.

The RETFIE(return from interrupt) instruction unstacks

the program counter and STATUS registers to return

the processor to its state prior to the interrupt

sequence.

8.5

Alternate Vector Table

In program memory, the Interrupt Vector Table (IVT) is

followed by the Alternate Interrupt Vector Table (AIVT),

as shown in Figure 8-1. Access to the alternate vector

table is provided by the ALTIVT bit in the INTCON2 reg-

ister. If the ALTIVT bit is set, all interrupt and exception

processes use the alternate vectors instead of the

default vectors. The alternate vectors are organized in

the same manner as the default vectors. The AIVT sup-

ports emulation and debugging efforts by providing a

means to switch between an application and a support

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between applications for evaluation of different

software algorithms at run time.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor is interrupted.

The processor then stacks the current program counter

and the low byte of the processor STATUS register

(SRL), as shown in Figure 8-2. The low byte of the

STATUS register contains the processor priority level at

the time prior to the beginning of the interrupt cycle.

The processor then loads the priority level for this inter-

rupt into the STATUS register. This action disables all

lower priority interrupts until the completion of the

Interrupt Service Routine.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

DS70139E-page 67

dsPIC30F2011/2012/3012/3013

8.6

Fast Context Saving

8.7

External Interrupt Requests

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z and C bits in SR, and the registers W0 through

W3. The shadows are only one level deep. The shadow

registers are accessible using the PUSH.Sand POP.S

instructions only.

The interrupt controller supports three external inter-

rupt request signals, INT0-INT2. These inputs are edge

sensitive; they require a low-to-high or a high-to-low

transition to generate an interrupt request. The

INTCON2 register has three bits, INT0EP-INT2EP, that

select the polarity of the edge detection circuitry.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

8.8

Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority ISR should not include the same instruc-

tions. Users must save the key registers in software

during a lower priority interrupt if the higher priority ISR

uses fast context saving.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor wakes up from Sleep or Idle

and begin execution of the Interrupt Service Routine

(ISR) needed to process the interrupt request.

DS70139E-page 68

dsPIC30F2011/2012/3012/3013

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1

9.0

TIMER1 MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual “ (DS70046).

presents a block diagram of the 16-bit timer module.

16-bit Timer Mode: In the 16-bit Timer mode, the timer

increments on every instruction cycle up to a match

value preloaded into the Period register PR1, then

resets to ‘0’ and continues to count.

This section describes the 16-bit general purpose

Timer1 module and associated operational modes.

Figure 9-1 depicts the simplified block diagram of the

16-bit Timer1 module. The following sections provide

detailed descriptions including setup and Control regis-

ters, along with associated block diagrams for the oper-

ational modes of the timers.

When the CPU goes into the Idle mode, the timer stops

incrementing unless the TSIDL (T1CON<13>) bit = 0.

If TSIDL = 1, the timer module logic resumes the incre-

menting sequence on termination of CPU Idle mode.

16-bit Synchronous Counter Mode: In the 16-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in PR1,

then resets to ‘0’ and continues.

The Timer1 module is a 16-bit timer that serves as the

time counter for the real-time clock or operates as a

free-running interval timer/counter. The 16-bit timer has

the following modes:

When the CPU goes into the Idle mode, the timer stops

incrementing unless the respective TSIDL bit = 0. If

TSIDL = 1, the timer module logic resumes the incre-

menting sequence upon termination of the CPU Idle

mode.

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

These operational characteristics are supported:

16-bit Asynchronous Counter Mode: In the 16-bit

Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal.

The timer counts up to a match value preloaded in PR1,

then resets to ‘0’ and continues.

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of external gate signal

When the timer is configured for the Asynchronous

mode of operation and the CPU goes into the Idle

mode, the timer stops incrementing if TSIDL = 1.

FIGURE 9-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

PR1

Comparator x 16

TMR1

Equal

Reset

TSYNC

1

0

Sync

0

1

T1IF

Event Flag

Q

D

TGATE

CK

TGATE

TCKPS<1:0>

2

TON

SOSCO/

T1CK

1x

01

00

Prescaler

1, 8, 64, 256

Gate

Sync

LPOSCEN

SOSCI

TCY

DS70139E-page 71

dsPIC30F2011/2012/3012/3013

9.1

Timer Gate Operation

9.4

Timer Interrupt

The 16-bit timer can be placed in the Gated Time Accu-

mulation mode. This mode allows the internal TCY to

increment the respective timer when the gate input sig-

nal (T1CK pin) is asserted high. Control bit, TGATE

(T1CON<6>), must be set to enable this mode. The

timer must be enabled (TON = 1) and the timer clock

source set to internal (TCS = 0).

The 16-bit timer has the ability to generate an interrupt-

on-period match. When the timer count matches the

Period register, the T1IF bit is asserted and an interrupt

is generated, if enabled. The T1IF bit must be cleared in

software. The timer interrupt flag, T1IF, is located in the

IFS0 Control register in the interrupt controller.

When the Gated Time Accumulation mode is enabled,

an interrupt is also generated on the falling edge of the

gate signal (at the end of the accumulation cycle).

When the CPU goes into the Idle mode, the timer stops

incrementing unless TSIDL = 0. If TSIDL = 1, the timer

resumes the incrementing sequence upon termination

of the CPU Idle mode.

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 Control register in the

interrupt controller.

9.2

Timer Prescaler

The input clock (FOSC/4 or external clock) to the 16-bit

Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,

selected by control bits, TCKPS<1:0> (T1CON<5:4>).

The prescaler counter is cleared when any of the

following occurs:

9.5

Real-Time Clock

Timer1, when operating in Real-Time Clock (RTC)

mode, provides time of day and event time-stamping

capabilities. Key operational features of the RTC are:

• a write to the TMR1 register

• Operation from 32 kHz LP oscillator

• 8-bit prescaler

• a write to the T1CON register

• device Reset, such as POR and BOR

• Low power

However, if the timer is disabled (TON = 0), then the

timer prescaler cannot be reset since the prescaler

clock is halted.

• Real-Time Clock interrupts

These operating modes are determined by setting the

appropriate bit(s) in the T1CON Control register.

TMR1 is not cleared when T1CON is written. It is

cleared by writing to the TMR1 register.

FIGURE 9-2:

RECOMMENDED

COMPONENTS FOR

TIMER1 LP OSCILLATOR

RTC

9.3

Timer Operation During Sleep

Mode

The timer operates during CPU Sleep mode if:

C1

• The timer module is enabled (TON = 1), and

SOSCI

• The timer clock source is selected as external

(TCS = 1), and

32.768 kHz

XTAL

dsPIC30FXXXX

• The TSYNC bit (T1CON<2>) is asserted to a logic

‘0’ which defines the external clock source as

asynchronous.

SOSCO

C2

R

When all three conditions are true, the timer continues

to count up to the Period register and be reset to

0x0000.

C1 = C2 = 18 pF; R = 100K

When a match between the timer and the Period regis-

ter occurs, an interrupt can be generated if the

respective timer interrupt enable bit is asserted.

DS70139E-page 72

dsPIC30F2011/2012/3012/3013

9.5.1

RTC OSCILLATOR OPERATION

9.5.2

RTC INTERRUPTS

When the TON = 1, TCS = 1and TGATE = 0, the timer

increments on the rising edge of the 32 kHz LP oscilla-

tor output signal, up to the value specified in the Period

register and is then reset to ‘0’.

When an interrupt event occurs, the respective interrupt

flag, T1IF, is asserted and an interrupt is generated if

enabled. The T1IF bit must be cleared in software. The

respective Timer interrupt flag, T1IF, is located in the

IFS0 register in the interrupt controller.

The TSYNC bit must be asserted to a logic ‘0’

(Asynchronous mode) for correct operation.

Enabling an interrupt is accomplished via the respec-

tive timer interrupt enable bit, T1IE. The timer interrupt

enable bit is located in the IEC0 Control register in the

interrupt controller.

Enabling LPOSCEN (OSCCON<1>) disables the

normal Timer and Counter modes and enables a timer

carry-out wake-up event.

When the CPU enters Sleep mode, the RTC continues

to operate, provided the 32 kHz external crystal oscilla-

tor is active and the control bits have not been

changed. The TSIDL bit should be cleared to ‘0’ in

order for RTC to continue operation in Idle mode.

DS70139E-page 73

dsPIC30F2011/2012/3012/3013

16-bit Timer Mode: In the 16-bit mode, Timer2 and

Timer3 can be configured as two independent 16-bit

10.0 TIMER2/3 MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual “(DS70046).

timers. Each timer can be set up in either 16-bit Timer

mode or 16-bit Synchronous Counter mode. See

Section 9.0 “Timer1 Module” for details on these two

operating modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescaler output. This is useful for high frequency

external clock inputs.

This section describes the 32-bit general purpose

Timer module (Timer2/3) and associated Operational

modes. Figure 10-1 depicts the simplified block dia-

gram of the 32-bit Timer2/3 module. Figure 10-2 and

Figure 10-3 show Timer2/3 configured as two

independent 16-bit timers, Timer2 and Timer3,

respectively.

32-bit Timer Mode: In the 32-bit Timer mode, the timer

increments on every instruction cycle, up to a match

value preloaded into the combined 32-bit Period

register PR3/PR2, then resets to ‘0’ and continues to

count.

The Timer2/3 module is a 32-bit timer (which can be

configured as two 16-bit timers) with selectable

operating modes. These timers are utilized by other

peripheral modules, such as:

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the ls word (TMR2 register) causes the ms

word to be read and latched into a 16-bit holding regis-

ter, termed TMR3HLD.

• Input Capture

• Output Compare/Simple PWM

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 register, the contents of TMR3HLD

is transferred and latched into the MSB of the 32-bit

timer (TMR3).

The following sections provide a detailed description,

including setup and Control registers, along with asso-

ciated block diagrams for the operational modes of the

timers.

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combined 32-bit period register, PR3/PR2, then resets

to ‘0’ and continues.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit timer operation

• Single 32-bit synchronous counter

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer stops incrementing unless the

TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer

module logic resumes the incrementing sequence

upon termination of the CPU Idle mode.

Further, the following operational characteristics are

supported:

• ADC event trigger

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the ls word

and Timer3 is the ms word of the 32-bit timer.

Note:

For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and the interrupt is enabled with the

Timer3 interrupt enable bit (T3IE).

DS70139E-page 75

dsPIC30F2011/2012/3012/3013

FIGURE 10-1:

32-BIT TIMER2/3 BLOCK DIAGRAM

Data Bus<15:0>

TMR3HLD

16

Write TMR2

Read TMR2

16

Reset

Sync

TMR3

MSB

TMR2

LSB

ADC Event Trigger

Comparator x 32

Equal

PR3

PR2

0

1

T3IF

Event Flag

Q

D

TGATE (T2CON<6>)

CK

TGATE

(T2CON<6>)

TCKPS<1:0>

2

TON

T2CK

1x

Prescaler

1, 8, 64, 256

Gate

Sync

01

00

TCY

Note:

Timer Configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control

bits are respective to the T2CON register.

DS70139E-page 76

dsPIC30F2011/2012/3012/3013

FIGURE 10-2:

16-BIT TIMER2 BLOCK DIAGRAM

PR2

Comparator x 16

TMR2

Equal

Reset

Sync

0

1

T2IF

Event Flag

TGATE

Q

D

Q

CK

TGATE

TCKPS<1:0>

2

TON

T2CK

1x

Prescaler

1, 8, 64, 256

Gate

Sync

01

00

TCY

FIGURE 10-3:

16-BIT TIMER3 BLOCK DIAGRAM

PR3

ADC Event Trigger

Equal

Comparator x 16

TMR3

Reset

0

1

T3IF

Event Flag

TGATE

Q

D

CK

TGATE

TCKPS<1:0>

2

TON

T3CK

Sync

TCY

1x

Prescaler

1, 8, 64, 256

01

00

DS70139E-page 77

dsPIC30F2011/2012/3012/3013

10.1 Timer Gate Operation

10.4 Timer Operation During Sleep

Mode

The 32-bit timer can be placed in the Gated Time Accu-

mulation mode. This mode allows the internal TCY to

increment the respective timer when the gate input sig-

nal (T2CK pin) is asserted high. Control bit, TGATE

(T2CON<6>), must be set to enable this mode. When

in this mode, Timer2 is the originating clock source.

The TGATE setting is ignored for Timer3. The timer

must be enabled (TON = 1) and the timer clock source

set to internal (TCS = 0).

The timer does not operate during CPU Sleep mode

because the internal clocks are disabled.

10.5 Timer Interrupt

The 32-bit timer module can generate an interrupt-on-

period match or on the falling edge of the external gate

signal. When the 32-bit timer count matches the

respective 32-bit period register, or the falling edge of

the external “gate” signal is detected, the T3IF bit

(IFS0<7>) is asserted and an interrupt is generated if

enabled. In this mode, the T3IF interrupt flag is used as

the source of the interrupt. The T3IF bit must be

cleared in software.

The falling edge of the external signal terminates the

count operation but does not reset the timer. The user

must reset the timer in order to start counting from zero.

10.2 ADC Event Trigger

When a match occurs between the 32-bit timer (TMR3/

TMR2) and the 32-bit combined period register (PR3/

PR2), or between the 16-bit timer TMR3 and the 16-bit

period register PR3, a special ADC trigger event signal

is generated by Timer3.

Enabling an interrupt is accomplished via the

respective timer interrupt enable bit, T3IE (IEC0<7>).

10.3 Timer Prescaler

The input clock (FOSC/4 or external clock) to the timer

has a prescale option of 1:1, 1:8, 1:64, and 1:256,

selected by control bits, TCKPS<1:0> (T2CON<5:4>

and T3CON<5:4>). For the 32-bit timer operation, the

originating clock source is Timer2. The prescaler oper-

ation for Timer3 is not applicable in this mode. The

prescaler counter is cleared when any of the following

occurs:

• a write to the TMR2/TMR3 register

• a write to the T2CON/T3CON register

• device Reset, such as POR and BOR

However, if the timer is disabled (TON = 0), then the

Timer 2 prescaler cannot be reset since the prescaler

clock is halted.

TMR2/TMR3 is not cleared when T2CON/T3CON is

written.

DS70139E-page 78

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 80

dsPIC30F2011/2012/3012/3013

These operating modes are determined by setting the

11.0 INPUT CAPTURE MODULE

appropriate bits in the IC1CON and IC2CON registers.

The dsPIC30F2011/2012/3012/3013 devices have two

capture channels.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

11.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

This section describes the input capture module and

associated operational modes. The features provided

by this module are useful in applications requiring fre-

quency (period) and pulse measurement.

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

Figure 11-1 depicts a block diagram of the input cap-

ture module. Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

These simple Input Capture modes are configured by

setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).

Important operational features of the input capture

module are:

11.1.1

CAPTURE PRESCALER

• Simple Capture Event mode

There are four input capture prescaler settings speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture channel is turned off, the prescaler counter is

cleared. In addition, any Reset clears the prescaler

counter.

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

FIGURE 11-1:

INPUT CAPTURE MODE BLOCK DIAGRAM

T3_CNT

16

From GP Timer Module

T2_CNT

16

ICTMR

1

0

ICx pin

Edge

Detection

Logic

FIFO

R/W

Logic

Prescaler

1, 4, 16

Clock

Synchronizer

ICM<2:0>

Mode Select

3

ICxBUF

ICBNE, ICOV

ICI<1:0>

Interrupt

Logic

ICxCON

Data Bus

Set Flag

ICxIF

Note:

Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channel (1 or 2).

DS70139E-page 81

dsPIC30F2011/2012/3012/3013

11.1.2

CAPTURE BUFFER OPERATION

11.2 Input Capture Operation During

Sleep and Idle Modes

Each capture channel has an associated FIFO buffer

which is four 16-bit words deep. There are two status

flags which provide status on the FIFO buffer:

An input capture event generates a device wake-up or

interrupt, if enabled, if the device is in CPU Idle or Sleep

mode.

• ICBNE — Input Capture Buffer Not Empty

• ICOV — Input Capture Overflow

Independent of the timer being enabled, the input cap-

ture module wakes up from the CPU Sleep or Idle mode

when a capture event occurs if ICM<2:0> = 111and the

interrupt enable bit is asserted. The same wake-up can

generate an interrupt if the conditions for processing the

interrupt have been satisfied. The wake-up feature is

useful as a method of adding extra external pin inter-

rupts.

The ICBNE is set on the first input capture event and

remains set until all capture events have been read

from the FIFO. As each word is read from the FIFO, the

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events, and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition occurs and the ICOV

bit is set to a logic ‘1’. The fifth capture event is lost and

is not stored in the FIFO. No additional events are cap-

tured until all four events have been read from the

buffer.

11.2.1

INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module opera-

tion with reduced functionality. In the CPU Sleep mode,

the ICI<1:0> bits are not applicable and the input cap-

ture module can only function as an external interrupt

source.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

The capture module must be configured for interrupt

only on rising edge (ICM<2:0> = 111) in order for the

input capture module to be used while the device is in

Sleep mode. The prescale settings of 4:1 or 16:1 are

not applicable in this mode.

11.1.3

TIMER2 AND TIMER3 SELECTION

MODE

The input capture module consists of up to 8 input cap-

ture channels. Each channel can select between one of

two timers for the time base, Timer2 or Timer3.

11.2.2

INPUT CAPTURE IN CPU IDLE

MODE

Selection of the timer resource is accomplished

through SFR bit, ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Inter-

rupt mode selected by the ICI<1:0> bits is applicable,

as well as the 4:1 and 16:1 capture prescale settings

which are defined by control bits ICM<2:0>. This mode

requires the selected timer to be enabled. Moreover,

the ICSIDL bit must be asserted to a logic ‘0’.

11.1.4

HALL SENSOR MODE

When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the fol-

lowing operations are performed by the input capture

logic:

If the input capture module is defined as

ICM<2:0> = 111 in CPU Idle mode, the input capture

pin serves only as an external interrupt pin.

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored since every capture

generates an interrupt.

11.3 Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt based upon the selected number of cap-

ture events. The selection number is set by control bits,

ICI<1:0> (ICxCON<6:5>).

• A capture overflow condition is not generated in

this mode.

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx register.

Enabling an interrupt is accomplished via the respec-

tive capture channel interrupt enable (ICxIE) bit. The

capture interrupt enable bit is located in the

corresponding IEC Control register.

DS70139E-page 82

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 84

dsPIC30F2011/2012/3012/3013

The key operational features of the output compare

module include:

12.0 OUTPUT COMPARE MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

This section describes the output compare module and

associated operational modes. The features provided

by this module are useful in applications requiring oper-

ational modes, such as:

These operating modes are determined by setting the

appropriate bits in the 16-bit OC1CON and OC2CON

registers. The dsPIC30F2011/2012/3012/3013 devices

have 2 compare channels.

• Generation of Variable Width Output Pulses

• Power Factor Correction

OCxRS and OCxR in Figure 12-1 represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the first compare and OCxRS

is used for the second compare.

Figure 12-1 depicts a block diagram of the output

compare module.

FIGURE 12-1:

OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR

Output

Logic

S

R

Q

OCx

Output

Enable

3

OCM<2:0>

Mode Select

Comparator

OCFA

(for x = 1, 2, 3 or 4)

OCTSEL

0

1

0

1

From GP

Timer Module

TMR2<15:0

TMR3<15:0> T2P2_MATCH

T3P3_MATCH

Note:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channel (1 or 2).

DS70139E-page 85

dsPIC30F2011/2012/3012/3013

12.3.2

CONTINUOUS PULSE MODE

12.1 Timer2 and Timer3 Selection Mode

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required:

Each output compare channel can select between one

of two 16-bit timers, Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3>). Timer2 is the default timer resource

for the output compare module.

• Determine instruction cycle time TCY.

• Calculate desired pulse value based on TCY.

• Calculate timer to start pulse width from timer start

value of 0x0000.

12.2 Simple Output Compare Match

Mode

• Write pulse width start and stop times into OCxR

and OCxRS (x denotes channel 1, 2, ...,N)

Compare registers, respectively.

When control bits OCM<2:0> (OCxCON<2:0>) = 001,

010 or 011, the selected output compare channel is

configured for one of three simple Output Compare

Match modes:

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 101.

• Compare forces I/O pin low

• Compare forces I/O pin high

• Compare toggles I/O pin

• Enable timer, TON (TxCON<15>) = 1.

12.4 Simple PWM Mode

The OCxR register is used in these modes. The OCxR

register is loaded with a value and is compared to the

selected incrementing timer count. When a compare

occurs, one of these Compare Match modes occurs. If

the counter resets to zero before reaching the value in

OCxR, the state of the OCx pin remains unchanged.

When control bits OCM<2:0> (OCxCON<2:0>) = 110

or 111, the selected output compare channel is config-

ured for the PWM mode of operation. When configured

for the PWM mode of operation, OCxR is the main latch

(read-only) and OCxRS is the secondary latch. This

enables glitchless PWM transitions.

The user must perform the following steps in order to

configure the output compare module for PWM

operation:

12.3 Dual Output Compare Match Mode

When control bits OCM<2:0> (OCxCON<2:0>) = 100

or 101, the selected output compare channel is config-

ured for one of two Dual Output Compare modes,

which are:

1. Set the PWM period by writing to the appropriate

period register.

2. Set the PWM duty cycle by writing to the OCxRS

register.

• Single Output Pulse mode

• Continuous Output Pulse mode

3. Configure the output compare module for PWM

operation.

12.3.1

SINGLE PULSE MODE

4. Set the TMRx prescale value and enable the

For the user to configure the module for the generation

of a single output pulse, the following steps are

required (assuming timer is off):

Timer, TON (TxCON<15>) = 1.

12.4.1

INPUT PIN FAULT PROTECTION

FOR PWM

• Determine instruction cycle time TCY.

• Calculate desired pulse width value based on TCY.

When control bits OCM<2:0> (OCxCON<2:0>) = 111,

the selected output compare channel is again config-

ured for the PWM mode of operation with the additional

feature of input Fault protection. While in this mode, if

a logic ‘0’ is detected on the OCFA/B pin, the respective

PWM output pin is placed in the high impedance input

state. The OCFLT bit (OCxCON<4>) indicates whether

a Fault condition has occurred. This state is maintained

until both of the following events have occurred:

• Calculate time to start pulse from timer start value

of 0x0000.

• Write pulse width start and stop times into OCxR

and OCxRS Compare registers (x denotes

channel 1, 2, ...,N).

• Set Timer Period register to value equal to or

greater than value in OCxRS Compare register.

• Set OCM<2:0> = 100.

• The external Fault condition has been removed.

• Enable timer, TON (TxCON<15>) = 1.

• The PWM mode has been re-enabled by writing

to the appropriate control bits.

To initiate another single pulse, issue another write to

set OCM<2:0> = 100.

DS70139E-page 86

dsPIC30F2011/2012/3012/3013

When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on

the next increment cycle:

12.4.2

PWM PERIOD

The PWM period is specified by writing to the PRx

register. The PWM period can be calculated using

Equation 12-1.

• TMRx is cleared.

• The OCx pin is set.

EQUATION 12-1:

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin remains low.

PWM period = [(PRx) + 1] • 4 • TOSC •

(TMRx prescale value)

- Exception 2: If duty cycle is greater than PRx,

the pin remains high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

PWM frequency is defined as 1/[PWM period].

• The corresponding timer interrupt flag is set.

See Figure 12-2 for key PWM period comparisons.

Timer3 is referred to in Figure 12-2 for clarity.

FIGURE 12-2:

PWM OUTPUT TIMING

Period

Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = Duty Cycle

(OCxR)

TMR3 = Duty Cycle

(OCxR)

12.5 Output Compare Operation During

CPU Sleep Mode

12.7 Output Compare Interrupts

The output compare channels have the ability to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the

Sleep state, the output compare channel drives the pin

to the active state that was observed prior to entering

the CPU Sleep state.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserted and an interrupt is generated if enabled. The

OCxIF bit is located in the corresponding IFS register

and must be cleared in software. The interrupt is

enabled via the respective compare interrupt enable

(OCxIE) bit located in the corresponding IEC Control

register.

For example, if the pin was high when the CPU entered

the Sleep state, the pin remains high. Likewise, if the

pin was low when the CPU entered the Sleep state, the

pin remains low. In either case, the output compare

module resumes operation when the device wakes up.

For the PWM mode, when an event occurs, the respec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt is generated if enabled. The IF bit is

located in the IFS0 register and must be cleared in soft-

ware. The interrupt is enabled via the respective timer

interrupt enable bit (T2IE or T3IE) located in the IEC0

Control register. The output compare interrupt flag is

never set during the PWM mode of operation.

12.6 Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel operates during the CPU

Idle mode if the OCSIDL bit (OCxCON<13>) is at logic

‘0’ and the selected time base (Timer2 or Timer3) is

enabled and the TSIDL bit of the selected timer is set

to logic ‘0’.

DS70139E-page 87

dsPIC30F2011/2012/3012/3013

• SS1 (active-low slave select).

13.0 SPI MODULE

In Master mode operation, SCK1 is a clock output. In

Slave mode, it is a clock input.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual “ (DS70046).

A series of eight (8) or sixteen (16) clock pulses shift

out bits from the SPI1SR to SDO1 pin and simulta-

neously shift in data from SDI1 pin. An interrupt is

generated when the transfer is complete and the

interrupt flag bit (SPI1IF) is set. This interrupt can be

disabled through the interrupt enable bit, SPI1IE.

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface. It is useful for communicating

with other peripheral devices, such as EEPROMs, shift

registers, display drivers and A/D converters, or other

microcontrollers. It is compatible with Motorola's SPI

and SIOP interfaces. The dsPIC30F2011/2012/3012/

3013 devices feature one SPI module, SPI1.

The receive operation is double-buffered. When a com-

plete byte is received, it is transferred from SPI1SR to

SPI1BUF.

If the receive buffer is full when new data is being trans-

ferred from SPI1SR to SPI1BUF, the module will set the

SPIROV bit indicating an overflow condition. The trans-

fer of the data from SPI1SR to SPI1BUF is not com-

pleted and the new data is lost. The module will not

respond to SCL transitions while SPIROV is ‘1’, effec-

tively disabling the module until SPI1BUF is read by

user software.

13.1 Operating Function Description

Figure 13-1 is a simplified block diagram of the SPI

module, which consists of a 16-bit shift register,

SPI1SR , used for shifting data in and out, and a buffer

register, SPI1BUF. Control register SPI1CON (not

shown) configures the module. Additionally, status reg-

ister SPI1STAT (not shown) indicates various status

conditions.

Transmit writes are also double-buffered. The user

writes to SPI1BUF. When the master or slave transfer

is completed, the contents of the shift register

(SPI1SR) are moved to the receive buffer. If any trans-

mit data has been written to the buffer register, the con-

tents of the transmit buffer are moved to SPI1SR. The

received data is thus placed in SPI1BUF and the trans-

mit data in SPI1SR is ready for the next transfer.

Note:

See “dsPIC30F Family Reference Man-

ual” (DS70046) for detailed information on

the control and status registers.

Four I/O pins comprise the serial interface:

• SDI1 (serial data input)

Note:

Both the transmit buffer (SPI1TXB) and

the receive buffer (SPI1RXB) are mapped

to the same register address, SPI1BUF.

• SDO1 (serial data output)

• SCK1 (shift clock input or output)

FIGURE 13-1:

SPI BLOCK DIAGRAM

Internal

Data Bus

Read

Write

SPIxBUF

Transmit

SPIxBUF

Receive

SPI1SR

bit 0

SDI1

SDO1

Shift

Clock

Control

Edge

Select

SS & FSYNC

Control

SS1

Secondary

Prescaler

1:1 – 1:8

Primary

Prescaler

1, 4, 16, 64

FCY

SCK1

Enable Master Clock

DS70139E-page 89

dsPIC30F2011/2012/3012/3013

Figure 13-2 depicts the a master/slave connection

between two processors. In Master mode, the clock is

generated by prescaling the system clock. Data is

transmitted as soon as a value is written to SPI1BUF.

The interrupt is generated at the middle of the transfer

of the last bit.

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is

that the data is transmitted out of bit 7 of the SPI1SR

for 8-bit operation, and data is transmitted out of bit 15

of the SPI1SR for 16-bit operation. In both modes, data

is shifted into bit 0 of the SPI1SR.

In Slave mode, data is transmitted and received as

external clock pulses appear on SCK. Again, the inter-

rupt is generated when the last bit is latched. If SS1

control is enabled, then transmission and reception are

enabled only when SS1 = low. The SDO1 output will be

disabled in SS1 mode with SS1 high.

13.1.2

SDO1 DISABLE

A control bit, DISSDO, is provided to the SPI1CON reg-

ister to allow the SDO1 output to be disabled. This will

allow the SPI module to be connected in an input only

configuration. SDO1 can also be used for general

purpose I/O.

The clock provided to the module is (FOSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on transi-

tion from active clock state to Idle clock state, or vice

versa. The CKP bit selects the Idle state (high or low)

for the clock.

13.2 Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit, FRMEN,

enables framed SPI support and causes the SS1 pin to

perform the Frame Synchronization Pulse (FSYNC)

function. The control bit, SPIFSD, determines whether

the SS1 pin is an input or an output (i.e., whether the

module receives or generates the Frame Synchroniza-

tion Pulse). The frame pulse is an active-high pulse for

a single SPI clock cycle. When Frame Synchronization

is enabled, the data transmission starts only on the

subsequent transmit edge of the SPI clock.

13.1.1

WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPI1CON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.

16-bit operation is identical to 8-bit operation except

that the number of bits transmitted is 16 instead of 8.

FIGURE 13-2:

SPI MASTER/SLAVE CONNECTION

SPI Master

SPI Slave

SDO1

SDI1

Serial Input Buffer

(SPI1BUF)

Serial Input Buffer

(SPI1BUF)

SDI1

SDO1

Shift Register

(SPI1SR)

LSb

MSb

LSb

Serial Clock

SCK1

PROCESSOR 1

PROCESSOR 2

DS70139E-page 90

dsPIC30F2011/2012/3012/3013

13.3 Slave Select Synchronization

13.5 SPI Operation During CPU Idle

Mode

The SS1 pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode with SS1

pin control enabled (SSEN = 1). When the SS1 pin is

low, transmission and reception are enabled and the

SDOx pin is driven. When SS1 pin goes high, the

SDOx pin is no longer driven. Also, the SPI module is

resynchronized, and all counters/control circuitry are

reset. Therefore, when the SS1 pin is asserted low

again, transmission/reception will begin at the MSb

even if SS1 had been de-asserted in the middle of a

transmit/receive.

When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPI1STAT<13>)

selects if the SPI module will stop or continue on idle. If

SPISIDL = 0, the module will continue to operate when

the CPU enters Idle mode. If SPISIDL = 1, the module

will stop when the CPU enters Idle mode.

13.4 SPI Operation During CPU Sleep

Mode

During Sleep mode, the SPI module is shut down. If the

CPU enters Sleep mode while an SPI transaction is in

progress, then the transmission and reception is

aborted.

The transmitter and receiver will stop in Sleep mode.

However, register contents are not affected by entering

or exiting Sleep mode.

DS70139E-page 91

dsPIC30F2011/2012/3012/3013

2

14.1.1

VARIOUS I²C MODES

14.0 I C™ MODULE

The following types of I²C operation are supported:

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

• I²C slave operation with 7-bit address

• I²C slave operation with 10-bit address

• I²C master operation with 7 or 10-bit address

See the I²C programmer’s model (Figure 14-1).

The Inter-Integrated Circuit (I²C^TM) module provides

complete hardware support for both Slave and Multi-

Master modes of the I²C serial communication

standard, with a 16-bit interface.

14.1.2

PIN CONFIGURATION IN I²C MODE

I²C has a 2-pin interface: the SCL pin is clock and the

SDA pin is data.

This module offers the following key features:

• I²C interface supporting both master and slave

operation.

• I²C Slave mode supports 7 and 10-bit address.

• I²C Master mode supports 7 and 10-bit address.

• I²C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I²C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

• I²C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

14.1.3

I²C REGISTERS

I2CCON and I2CSTAT are control and status registers,

respectively. The I2CCON register is readable and writ-

able. The lower 6 bits of I2CSTAT are read-only. The

remaining bits of the I2CSTAT are read/write.

I2CRSR is the shift register used for shifting data,

whereas I2CRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CRCV is the receive buffer as shown in Figure 14-1.

I2CTRN is the transmit register to which bytes are

written during a transmit operation, as shown in

Figure 14-2.

The I2CADD register holds the slave address. A Status

bit, ADD10, indicates 10-bit Address mode. The

I2CBRG acts as the Baud Rate Generator reload

value.

14.1 Operating Function Description

The hardware fully implements all the master and slave

functions of the I²C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

In receive operations, I2CRSR and I2CRCV together

Thus, the I²C module can operate either as a slave or

a master on an I²C bus.

form

a double-buffered receiver. When I2CRSR

receives a complete byte, it is transferred to I2CRCV

and an interrupt pulse is generated. During

transmission, the I2CTRN is not double-buffered.

Note:

Following a Restart condition in 10-bit

mode, the user only needs to match the

first 7-bit address.

FIGURE 14-1:

PROGRAMMER’S MODEL

I2CRCV (8 bits)

Bit 0

Bit 7

I2CTRN (8 bits)

Bit 0

Bit 7

Bit 8

I2CBRG (9 bits)

Bit 0

I2CCON (16 bits)

Bit 0

Bit 15

I2CSTAT (16 bits)

Bit 0

I2CADD (10 bits)

Bit 0

Bit 9

DS70139E-page 93

dsPIC30F2011/2012/3012/3013

FIGURE 14-2:

I²C™ BLOCK DIAGRAM

Internal

Data Bus

I2CRCV

Read

Shift

Clock

SCL

SDA

I2CRSR

LSB

Addr_Match

Match Detect

I2CADD

Write

Read

Start and

Stop bit Detect

Write

Read

Start, Restart,

Stop bit Generate

Collision

Detect

Write

Read

Acknowledge

Generation

Clock

Stretching

Write

Read

I2CTRN

LSB

Shift

Clock

Reload

Control

Write

Read

I2CBRG

BRG Down

Counter

FCY

DS70139E-page 94

dsPIC30F2011/2012/3012/3013

2

14.3.2

SLAVE RECEPTION

14.2 I C Module Addresses

If the R_W bit received is a ‘0’ during an address

match, then Receive mode is initiated. Incoming bits

are sampled on the rising edge of SCL. After 8 bits are

received, if I2CRCV is not full or I2COV is not set,

I2CRSR is transferred to I2CRCV. ACK is sent on the

ninth clock.

The I2CADD register contains the Slave mode

addresses. The register is a 10-bit register.

If the A10M bit (I2CCON<10>) is ‘0’, the address is

interpreted by the module as a 7-bit address. When an

address is received, it is compared to the 7 LSb of the

I2CADD register.

If the RBF flag is set, indicating that I2CRCV is still

holding data from a previous operation (RBF = 1), then

ACK is not sent; however, the interrupt pulse is gener-

ated. In the case of an overflow, the contents of the

I2CRSR are not loaded into the I2CRCV.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will be

compared with the binary value ‘11110 A9 A8’ (where

A9and A8are two Most Significant bits of I2CADD). If

that value matches, the next address will be compared

with the Least Significant 8 bits of I2CADD, as specified

in the 10-bit addressing protocol.

Note:

The I2CRCV will be loaded if the I2COV

bit = 1and the RBF flag = 0. In this case,

a read of the I2CRCV was performed but

the user did not clear the state of the

I2COV bit before the next receive

occurred. The acknowledgement is not

sent (ACK = 1) and the I2CRCV is

updated.

The 7-bit I²C Slave Addresses supported by the

dsPIC30F are shown in Table 14-1.

TABLE 14-1: 7-BIT I²C™ SLAVE

ADDRESSES

0x00

General call address or start byte

Reserved

0x01-0x03

0x04-0x07

0x04-0x77

0x78-0x7b

2

14.4 I C 10-bit Slave Mode Operation

Hs-mode Master codes

Valid 7-bit addresses

In 10-bit mode, the basic receive and transmit opera-

tions are the same as in the 7-bit mode. However, the

criteria for address match is more complex.

The I²C specification dictates that a slave must be

addressed for a write operation with two address bytes

following a Start bit.

Valid 10-bit addresses (lower 7

bits)

0x7c-0x7f

Reserved

2

14.3 I C 7-bit Slave Mode Operation

The A10M bit is a control bit that signifies that the

address in I2CADD is a 10-bit address rather than a 7-bit

address. The address detection protocol for the first byte

of a message address is identical for 7-bit and 10-bit

messages, but the bits being compared are different.

Once enabled (I2CEN = 1), the slave module will wait

for a Start bit to occur (i.e., the I²C module is ‘Idle’). Fol-

lowing the detection of a Start bit, 8 bits are shifted into

I2CRSR and the address is compared against

I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>

are compared against I2CRSR<7:1> and I2CRSR<0>

is the R_W bit. All incoming bits are sampled on the ris-

ing edge of SCL.

I2CADD holds the entire 10-bit address. Upon receiv-

ing an address following a Start bit, I2CRSR <7:3> is

compared against a literal ‘11110’ (the default 10-bit

address) and I2CRSR<2:1> are compared against

I2CADD<9:8>. If a match occurs and if R_W = 0, the

interrupt pulse is sent. The ADD10 bit will be cleared to

indicate a partial address match. If a match fails or

R_W = 1, the ADD10 bit is cleared and the module

returns to the Idle state.

If an address match occurs, an acknowledgement will

be sent, and the slave event interrupt flag (SI2CIF) is

set on the falling edge of the ninth (ACK) bit. The

address match does not affect the contents of the

I2CRCV buffer or the RBF bit.

The low byte of the address is then received and com-

pared with I2CADD<7:0>. If an address match occurs,

the interrupt pulse is generated and the ADD10 bit is

set, indicating a complete 10-bit address match. If an

address match did not occur, the ADD10 bit is cleared

and the module returns to the Idle state.

14.3.1

SLAVE TRANSMISSION

If the R_W bit received is a ‘1’, then the serial port will

go into Transmit mode. It will send ACK on the ninth bit

and then hold SCL to ‘0’ until the CPU responds by writ-

ing to I2CTRN. SCL is released by setting the SCLREL

bit, and 8 bits of data are shifted out. Data bits are

shifted out on the falling edge of SCL, such that SDA is

valid during SCL high. The interrupt pulse is sent on the

falling edge of the ninth clock pulse, regardless of the

status of the ACK received from the master.

DS70139E-page 95

dsPIC30F2011/2012/3012/3013

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing

the SCL output to be held low. The user’s ISR must set

the SCLREL bit before reception is allowed to continue.

By holding the SCL line low, the user has time to ser-

vice the ISR and read the contents of the I2CRCV

before the master device can initiate another receive

sequence. This will prevent buffer overruns from

occurring.

14.4.1

10-BIT MODE SLAVE

TRANSMISSION

Once a slave is addressed in this fashion with the full

10-bit address (we will refer to this state as

“PRIOR_ADDR_MATCH”), the master can begin

sending data bytes for a slave reception operation.

14.4.2

10-BIT MODE SLAVE RECEPTION

Once addressed, the master can generate a Repeated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus initiating a

slave transmit operation.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

14.5 Automatic Clock Stretch

In the Slave modes, the module can synchronize buffer

reads and write to the master device by clock stretching.

2: The SCLREL bit can be set in software

regardless of the state of the RBF bit. The

user should be careful to clear the RBF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

14.5.1

TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared, indicat-

ing the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed irrespective of the STREN bit.

14.5.4

CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the falling edge of the ninth clock and if the

TBF bit is still clear, then the SCLREL bit is automati-

cally cleared. The SCLREL being cleared to ‘0’ will

assert the SCL line low. The user’s ISR must set the

SCLREL bit before transmission is allowed to continue.

By holding the SCL line low, the user has time to ser-

vice the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

register for the entire address, it is not necessary for

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence as

was described earlier.

14.6 Software Controlled Clock

Stretching (STREN = 1)

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge

of the ninth clock, the SCLREL bit will not

be cleared and clock stretching will not

occur.

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to the

SCLREL bit with the SCL clock. Clearing the SCLREL

bit will not assert the SCL output until the module

detects a falling edge on the SCL output and SCL is

sampled low. If the SCLREL bit is cleared by the user

while the SCL line has been sampled low, the SCL out-

put will be asserted (held low). The SCL output will

remain low until the SCLREL bit is set, and all other

devices on the I²C bus have de-asserted SCL. This

ensures that a write to the SCLREL bit will not violate

the minimum high time requirement for SCL.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

14.5.2

RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at the

end of each data receive sequence.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

14.5.3

CLOCK STRETCHING DURING

7-BIT ADDRESSING (STREN = 1)

When the STREN bit is set in Slave Receive mode, the

SCL line is held low when the buffer register is full. The

method for stretching the SCL output is the same for

both 7 and 10-bit addressing modes.

DS70139E-page 96

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2

14.7 Interrupts

14.11 I C Master Support

The I²C module generates two interrupt flags, MI2CIF

(I²C Master Interrupt Flag) and SI2CIF (I²C Slave Inter-

rupt Flag). The MI2CIF interrupt flag is activated on

completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

As a master device, six operations are supported:

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Configure the I²C port to receive data.

14.8 Slope Control

• Generate an ACK condition at the end of a

received byte of data.

The I²C standard requires slope control on the SDA

and SCL signals for Fast mode (400 kHz). The control

bit, DISSLW, enables the user to disable slew rate con-

trol if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

2

14.12 I C Master Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

14.9 IPMI Support

The control bit, IPMIEN, enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the data direction bit. In

this case, the data direction bit (R_W) is logic ‘0’. Serial

data is transmitted 8 bits at a time. After each byte is

transmitted, an ACK bit is received. Start and Stop con-

ditions are output to indicate the beginning and the end

of a serial transfer.

14.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R_W = 0.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the data direction bit. In this case, the data

direction bit (R_W) is logic ‘1’. Thus, the first byte trans-

mitted is a 7-bit slave address, followed by a ‘1’ to indi-

cate receive bit. Serial data is received via SDA while

SCL outputs the serial clock. Serial data is received

8 bits at a time. After each byte is received, an ACK bit

is transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The general call address is recognized when the Gen-

eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).

Following a Start bit detection, 8 bits are shifted into

I2CRSR and the address is compared with I2CADD,

and is also compared with the general call address

which is fixed in hardware.

If a general call address match occurs, the I2CRSR is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set and on the falling edge of the ninth bit

(ACK bit), the master event interrupt flag (MI2CIF) is

set.

14.12.1 I²C MASTER TRANSMISSION

Transmission of a data byte, a 7-bit address, or the sec-

ond half of a 10-bit address, is accomplished by simply

writing a value to I2CTRN register. The user should

only write to I2CTRN when the module is in a WAIT

state. This action will set the Buffer Full Flag (TBF) and

allow the Baud Rate Generator to begin counting and

start the next transmission. Each bit of address/data

will be shifted out onto the SDA pin after the falling

edge of SCL is asserted. The Transmit Status Flag,

TRSTAT (I2CSTAT<14>), indicates that a master

transmit is in progress.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific or a general call address.

DS70139E-page 97

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14.12.2 I²C MASTER RECEPTION

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the TBF flag is

cleared, the SDA and SCL lines are de-asserted and a

value can now be written to I2CTRN. When the user

services the I²C master event Interrupt Service Rou-

tine, if the I²C bus is free (i.e., the P bit is set), the user

can resume communication by asserting a Start

condition.

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (I2CCON<3>). The I²C

module must be Idle before the RCEN bit is set, other-

wise the RCEN bit will be disregarded. The Baud Rate

Generator begins counting and on each rollover, the

state of the SCL pin ACK and data are shifted into the

I2CRSR on the rising edge of each clock.

If a Start, Restart, Stop or Acknowledge condition was

in progress when the bus collision occurred, the condi-

tion is aborted, the SDA and SCL lines are de-asserted,

and the respective control bits in the I2CCON register

are cleared to ‘0’. When the user services the bus col-

lision Interrupt Service Routine, and if the I²C bus is

free, the user can resume communication by asserting

a Start condition.

14.12.3 BAUD RATE GENERATOR

In I²C Master mode, the reload value for the BRG is

located in the I2CBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock arbi-

tration is taking place, for instance, the BRG is reloaded

when the SCL pin is sampled high.

The master will continue to monitor the SDA and SCL

pins, and if a Stop condition occurs, the MI2CIF bit will

be set.

As per the I²C standard, FSCK may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.

A write to the I2CTRN will start the transmission of data

at the first data bit regardless of where the transmitter

left off when bus collision occurred.

EQUATION 14-1: SERIAL CLOCK RATE

In a multi-master environment, the interrupt generation

on the detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the I2CSTAT

register, or the bus is Idle and the S and P bits are

cleared.

FCY

FSCL

FCY

1,111,111

I2CBRG =

– 1

–

(

)

14.12.4 CLOCK ARBITRATION

Clock arbitration occurs when the master de-asserts

the SCL pin (SCL allowed to float high) during any

receive, transmit, or Restart/Stop condition. When the

SCL pin is allowed to float high, the Baud Rate Gener-

ator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the Baud Rate Generator is reloaded with

the contents of I2CBRG and begins counting. This

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

2

14.13 I C Module Operation During CPU

Sleep and Idle Modes

14.13.1 I²C OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’. If

Sleep occurs in the middle of a transmission and the

state machine is partially into a transmission as the

clocks stop, then the transmission is aborted. Similarly,

if Sleep occurs in the middle of a reception, then the

reception is aborted.

14.12.5 MULTI-MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

14.13.2 I²C OPERATION DURING CPU IDLE

MODE

For the I²C, the I2CSIDL bit selects if the module will

stop on Idle or continue on Idle. If I2CSIDL = 0, the

module will continue operation on assertion of the Idle

mode. If I2CSIDL = 1, the module will stop on Idle.

Multi-master operation support is achieved by bus arbi-

tration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA by letting SDA float high

while another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA

pin = 0, then a bus collision has taken place. The

master will set the MI2CIF pulse and reset the master

portion of the I²C port to its Idle state.

DS70139E-page 98

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NOTES:

DS70139E-page 100

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15.1 UART Module Overview

15.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART) MODULE

The key features of the UART module are:

• Full-duplex, 8 or 9-bit data communication

• Even, odd or no parity options (for 8-bit data)

• One or two Stop bits

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

• Fully integrated Baud Rate Generator with 16-bit

prescaler

• Baud rates range from 38 bps to 1.875 Mbps at a

30 MHz instruction rate

This section describes the Universal Asynchronous

Receiver/Transmitter Communications module. The

dsPIC30F2011/2012/3012 processors have one UART

module (UART1). The dsPIC30F3013 processor has

two UART modules (UART1 and UART2).

• 4-word deep transmit data buffer

• 4-word deep receive data buffer

• Parity, framing and buffer overrun error detection

• Support for interrupt only on address detect

(9th bit = 1)

• Separate transmit and receive interrupts

• Loopback mode for diagnostic support

• Alternate receive and transmit pins for UART1

FIGURE 15-1:

UART TRANSMITTER BLOCK DIAGRAM

Internal Data Bus

Control and Status bits

Write

UTX8 UxTXREG Low Byte

Transmit Control

– Control TSR

– Control Buffer

– Generate Flags

– Generate Interrupt

Load TSR

UxTXIF

UTXBRK

Data

Transmit Shift Register (UxTSR)

‘0’ (Start)

‘1’ (Stop)

UxTX

16x Baud Clock

from Baud Rate

Generator

Parity

Generator

16 Divider

Parity

Control

Signals

Note:

x = 1 or 2.

DS70139E-page 101

dsPIC30F2011/2012/3012/3013

FIGURE 15-2:

UART RECEIVER BLOCK DIAGRAM

Internal Data Bus

16

Read

Write

Read Read

Write

UxMODE

UxSTA

UxRXREG Low Byte

URX8

Receive Buffer Control

– Generate Flags

– Generate Interrupt

– Shift Data Characters

8-9

LPBACK

From UxTX

Load RSR

to Buffer

Receive Shift Register

(UxRSR)

1

0

Control

Signals

UxRX

· Start bit Detect

· Parity Check

· Stop bit Detect

· Shift Clock Generation

· Wake Logic

16 Divider

16x Baud Clock from

Baud Rate Generator

UxRXIF

DS70139E-page 102

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15.2 Enabling and Setting Up UART

15.3 Transmitting Data

15.2.1 ENABLING THE UART

15.3.1 TRANSMITTING IN 8-BIT DATA

MODE

The UART module is enabled by setting the UARTEN

bit in the UxMODE register (where x = 1 or 2). Once

enabled, the UxTX and UxRX pins are configured as an

output and an input respectively, overriding the TRIS

and LAT register bit settings for the corresponding I/O

port pins. The UxTX pin is at logic ‘1’ when no

transmission is taking place.

The following steps must be performed in order to

transmit 8-bit data:

1. Set up the UART:

First, the data length, parity and number of Stop

bits must be selected. Then, the transmit and

receive interrupt enable and priority bits are

setup in the UxMODE and UxSTA registers.

Also, the appropriate baud rate value must be

written to the UxBRG register.

15.2.2

DISABLING THE UART

The UART module is disabled by clearing the UARTEN

bit in the UxMODE register. This is the default state

after any Reset. If the UART is disabled, all I/O pins

operate as port pins under the control of the LAT and

TRIS bits of the corresponding port pins.

2. Enable the UART by setting the UARTEN bit

(UxMODE<15>).

3. Set the UTXEN bit (UxSTA<10>), thereby

enabling a transmission.

Disabling the UART module resets the buffers to empty

states. Any data characters in the buffers are lost and

the baud rate counter is reset.

4. Write the byte to be transmitted to the lower byte

of UxTXREG. The value will be transferred to the

Transmit Shift register (UxTSR) immediately

and the serial bit stream will start shifting out

during the next rising edge of the baud clock.

Alternatively, the data byte may be written while

UTXEN = 0, following which, the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

All error and status flags associated with the UART

module are reset when the module is disabled. The

URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and

UTXBF bits are cleared, whereas RIDLE and TRMT

are set. Other control bits, including ADDEN,

URXISEL<1:0>, UTXISEL, as well as the UxMODE

and UxBRG registers, are not affected.

5. A transmit interrupt will be generated, depend-

ing on the value of the interrupt control bit

UTXISEL (UxSTA<15>).

Clearing the UARTEN bit while the UART is active will

abort all pending transmissions and receptions and

reset the module as defined above. Re-enabling the

UART will restart the UART in the same configuration.

15.3.2

TRANSMITTING IN 9-BIT DATA

MODE

15.2.3

ALTERNATE I/O

The sequence of steps involved in the transmission of

9-bit data is similar to 8-bit transmission, except that a

16-bit data word (of which the upper 7 bits are always

clear) must be written to the UxTXREG register.

The alternate I/O function is enabled by setting the

ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX

and UxARX pins (alternate transmit and alternate

receive pins, respectively) are used by the UART mod-

ule instead of the UxTX and UxRX pins. If ALTIO = 0,

the UxTX and UxRX pins are used by the UART

module.

15.3.3

TRANSMIT BUFFER (UXTXB)

The transmit buffer is 9 bits wide and 4 characters

deep. Including the Transmit Shift register (UxTSR),

the user effectively has a 5-deep FIFO (First-In, First-

Out) buffer. The UTXBF bit (UxSTA<9>) indicates

whether the transmit buffer is full.

15.2.4

SETTING UP DATA, PARITY AND

STOP BIT SELECTIONS

Control bits PDSEL<1:0> in the UxMODE register are

used to select the data length and parity used in the

transmission. The data length may either be 8 bits with

even, odd or no parity, or 9 bits with no parity.

If a user attempts to write to a full buffer, the new data

will not be accepted into the FIFO and no data shift will

occur within the buffer. This enables recovery from a

buffer overrun condition.

The STSEL bit determines whether one or two Stop bits

will be used during data transmission.

The FIFO is reset during any device Reset, but is not

affected when the device enters or wakes up from a

Power Saving mode.

The default (power-on) setting of the UART is 8 bits, no

parity and 1 Stop bit (typically represented as 8, N, 1).

DS70139E-page 103

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15.3.4

TRANSMIT INTERRUPT

15.4.2

RECEIVE BUFFER (UXRXB)

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

The transmitter generates an edge to set the UxTXIF

bit. The condition for generating the interrupt depends

on the UTXISEL control bit:

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0implies that the

buffer is empty. If a user attempts to read an empty

buffer, the old values in the buffer will be read and no

data shift will occur within the FIFO.

a) If UTXISEL = 0, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR). This means

that the transmit buffer has at least one empty

word.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

Power Saving mode.

b) If UTXISEL = 1, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR) and the

transmit buffer is empty.

15.4.3

RECEIVE INTERRUPT

The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register. The

interrupt flag is set by an edge generated by the

receiver. The condition for setting the receive interrupt

flag depends on the settings specified by the

URXISEL<1:0> (UxSTA<7:6>) control bits.

Switching between the two Interrupt modes during

operation is possible and sometimes offers more

flexibility.

15.3.5

TRANSMIT BREAK

a) If URXISEL<1:0> = 00or 01, an interrupt is gen-

erated every time a data word is transferred

from the Receive Shift register (UxRSR) to the

receive buffer. There may be one or more

characters in the receive buffer.

Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

b) If URXISEL<1:0> = 10, an interrupt is generated

when a word is transferred from the Receive Shift

register (UxRSR) to the receive buffer, which as a

result of the transfer, contains 3 characters.

To send a Break character, the UTXBRK bit must be set

by software and must remain set for a minimum of 13

baud clock cycles. The UTXBRK bit is then cleared by

software to generate Stop bits. The user must wait for

a duration of at least one or two baud clock cycles in

order to ensure a valid Stop bit(s) before reloading the

UxTXB, or starting other transmitter activity. Transmis-

sion of a Break character does not generate a transmit

interrupt.

c) If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift reg-

ister (UxRSR) to the receive buffer, which as a

result of the transfer, contains 4 characters (i.e.,

becomes full).

Switching between the Interrupt modes during opera-

tion is possible, though generally not advisable during

normal operation.

15.4 Receiving Data

15.4.1

RECEIVING IN 8-BIT OR 9-BIT

DATA MODE

15.5 Reception Error Handling

The following steps must be performed while receiving

8-bit or 9-bit data:

15.5.1

RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

1. Set up the UART (see Section 15.3.1 “Trans-

mitting in 8-bit data mode”).

The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:

2. Enable the UART (see Section 15.3.1 “Trans-

mitting in 8-bit data mode”).

a) The receive buffer is full.

3. A receive interrupt will be generated when one

or more data words have been received,

depending on the receive interrupt settings

specified by the URXISEL bits (UxSTA<7:6>).

b) The Receive Shift register is full, but unable to

transfer the character to the receive buffer.

c) The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

Once OERR is set, no further data is shifted in UxRSR

(until the OERR bit is cleared in software or a Reset

occurs). The data held in UxRSR and UxRXREG

remains valid.

5. Read the received data from UxRXREG. The act

of reading UxRXREG will move the next word to

the top of the receive FIFO, and the PERR and

FERR values will be updated.

DS70139E-page 104

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15.5.2

FRAMING ERROR (FERR)

15.6 Address Detect Mode

The FERR bit (UxSTA<2>) is set if a ‘0’ is detected

instead of a Stop bit. If two Stop bits are selected, both

Stop bits must be ‘1’, otherwise FERR will be set. The

read-only FERR bit is buffered along with the received

data. It is cleared on any Reset.

Setting the ADDEN bit (UxSTA<5>) enables this spe-

cial mode in which a 9th bit (URX8) value of ‘1’ identi-

fies the received word as an address, rather than data.

This mode is only applicable for 9-bit data communica-

tion. The URXISEL control bit does not have any

impact on interrupt generation in this mode since an

interrupt (if enabled) will be generated every time the

received word has the 9th bit set.

15.5.3

PARITY ERROR (PERR)

The PERR bit (UxSTA<3>) is set if the parity of the

received word is incorrect. This error bit is applicable

only if a Parity mode (odd or even) is selected. The

read-only PERR bit is buffered along with the received

data bytes. It is cleared on any Reset.

15.7 Loopback Mode

Setting the LPBACK bit enables this special mode in

which the UxTX pin is internally connected to the UxRX

pin. When configured for the Loopback mode, the

UxRX pin is disconnected from the internal UART

receive logic. However, the UxTX pin still functions as

in a normal operation.

15.5.4

IDLE STATUS

When the receiver is active (i.e., between the initial

detection of the Start bit and the completion of the Stop

bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-

pletion of the Stop bit and detection of the next Start bit,

the RIDLE bit is ‘1’, indicating that the UART is Idle.

To select this mode:

a) Configure UART for desired mode of operation.

b) Set LPBACK = 1to enable Loopback mode.

15.5.5

RECEIVE BREAK

c) Enable transmission as defined in Section 15.3

“Transmitting Data”.

The receiver will count and expect a certain number of

bit times based on the values programmed in the

PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)

bits.

15.8 Baud Rate Generator

The UART has a 16-bit Baud Rate Generator to allow

maximum flexibility in baud rate generation. The Baud

Rate Generator register (UxBRG) is readable and

writable. The baud rate is computed as follows:

If the break is longer than 13 bit times, the reception is

considered complete after the number of bit times

specified by PDSEL and STSEL. The URXDA bit is set,

FERR is set, zeros are loaded into the receive FIFO,

interrupts are generated if appropriate and the RIDLE

bit is set.

BRG = 16-bit value held in UxBRG register

(0 through 65535)

When the module receives a long break signal and the

receiver has detected the Start bit, the data bits and the

invalid Stop bit (which sets the FERR), the receiver

must wait for a valid Stop bit before looking for the next

Start bit. It cannot assume that the break condition on

the line is the next Start bit.

FCY = Instruction Clock Rate (1/TCY)

The baud rate is given by Equation 15-1.

EQUATION 15-1: BAUD RATE

Baud Rate = FCY / (16*(BRG+1))

Break is regarded as a character containing all ‘0’s with

the FERR bit set. The Break character is loaded into

the buffer. No further reception can occur until a Stop bit

is received. Note that RIDLE goes high when the Stop

bit has not yet been received.

Therefore, the maximum baud rate possible is:

FCY /16 (if BRG = 0),

and the minimum baud rate possible is:

FCY / (16* 65536).

With a full 16-bit Baud Rate Generator at 30 MIPS

operation, the minimum baud rate achievable is

28.5 bps.

DS70139E-page 105

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15.10.2 UART OPERATION DURING CPU

15.9 Auto-Baud Support

IDLE MODE

To allow the system to determine baud rates of

received characters, the input can be optionally linked

to a selected capture input (IC1 for UART1 and IC2 for

UART2). To enable this mode, you must program the

input capture module to detect the falling and rising

edges of the Start bit.

For the UART, the USIDL bit selects if the module will

stop operation when the device enters Idle mode or

whether the module will continue on Idle. If USIDL = 0,

the module will continue operation during Idle mode. If

USIDL = 1, the module will stop on Idle.

15.10 UART Operation During CPU

Sleep and Idle Modes

15.10.1 UART OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’. If

entry into Sleep mode occurs while a transmission is in

progress, then the transmission is aborted. The UxTX

pin is driven to logic ‘1’. Similarly, if entry into Sleep

mode occurs while a reception is in progress, then the

reception is aborted. The UxSTA, UxMODE, transmit

and receive registers and buffers, and the UxBRG

register are not affected by Sleep mode.

If the WAKE bit (UxMODE<7>) is set before the device

enters Sleep mode, then a falling edge on the UxRX pin

will generate a receive interrupt. The Receive Interrupt

Select mode bit (URXISEL) has no effect for this func-

tion. If the receive interrupt is enabled, then this will

wake-up the device from Sleep. The UARTEN bit must

be set in order to generate a wake-up interrupt.

DS70139E-page 106

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 108

dsPIC30F2011/2012/3012/3013

The ADC module has six 16-bit registers:

16.0 12-BIT ANALOG-TO-DIGITAL

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

• A/D Control Register 3 (ADCON3)

• A/D Input Select Register (ADCHS)

• A/D Port Configuration Register (ADPCFG)

• A/D Input Scan Selection Register (ADCSSL)

CONVERTER (ADC) MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

The ADCON1, ADCON2 and ADCON3 registers

control the operation of the ADC module. The ADCHS

register selects the input channels to be converted. The

ADPCFG register configures the port pins as analog

inputs or as digital I/O. The ADCSSL register selects

inputs for scanning.

The 12-bit Analog-to-Digital Converter allows conver-

sion of an analog input signal to a 12-bit digital number.

This module is based on a Successive Approximation

Register (SAR) architecture and provides a maximum

sampling rate of 200 ksps. The ADC module has up to

10 analog inputs which are multiplexed into a sample

and hold amplifier. The output of the sample and hold

is the input into the converter which generates the

result. The analog reference voltage is software select-

able to either the device supply voltage (AVDD/AVSS) or

the voltage level on the (VREF+/VREF-) pin. The ADC

has a unique feature of being able to operate while the

device is in Sleep mode with RC oscillator selection.

Note:

The SSRC<2:0>, ASAM, SMPI<3:0>,

BUFM and ALTS bits, as well as the

ADCON3 and ADCSSL registers, must

not be written to while ADON = 1. This

would lead to indeterminate results.

The block diagram of the 12-bit ADC module is shown

in Figure 16-1.

FIGURE 16-1:

12-BIT ADC FUNCTIONAL BLOCK DIAGRAM

AVDD/VREF+

AVSS/VREF-

Comparator

DAC

0000

AN0

0001

0010

0011

AN1

AN2

AN3

12-bit SAR

Conversion Logic

0100

0101

0110

0111

1000

1001

AN4

AN5

AN6

AN7

AN8

AN9

16-word, 12-bit

Dual Port

Buffer

Sample/Sequence

Control

Sample

CH0

S/H

Input

Switches

Input MUX

Control

DS70139E-page 109

dsPIC30F2011/2012/3012/3013

16.1 A/D Result Buffer

16.3 Selecting the Conversion

Sequence

The module contains a 16-word dual port read-only

buffer, called ADCBUF0...ADCBUFF, to buffer the A/D

results. The RAM is 12 bits wide but the data obtained

is represented in one of four different 16-bit data for-

mats. The contents of the sixteen A/D Conversion

Result Buffer registers, ADCBUF0 through ADCBUFF,

cannot be written by user software.

Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold

channel, converts a channel, writes the buffer memory

and generates interrupts.

The sequence is controlled by the sampling clocks.

The SMPI bits select the number of acquisition/

conversion sequences that would be performed before

an interrupt occurs. This can vary from 1 sample per

interrupt to 16 samples per interrupt.

16.2 Conversion Operation

After the ADC module has been configured, the sample

acquisition is started by setting the SAMP bit. Various

sources, such as a programmable bit, timer time-outs

and external events, will terminate acquisition and start

a conversion. When the A/D conversion is complete,

the result is loaded into ADCBUF0...ADCBUFF, and

the DONE bit and the A/D interrupt flag, ADIF, are set

after the number of samples specified by the SMPI bit.

The ADC module can be configured for different inter-

rupt rates as described in Section 16.3 “Selecting the

Conversion Sequence”.

The BUFM bit will split the 16-word results buffer into

two 8-word groups. Writing to the 8-word buffers will be

alternated on each interrupt event.

Use of the BUFM bit will depend on how much time is

available for the moving of the buffers after the

interrupt.

If the processor can quickly unload a full buffer within

the time it takes to acquire and convert one channel,

the BUFM bit can be ‘0’ and up to 16 conversions (cor-

responding to the 16 input channels) may be done per

interrupt. The processor will have one acquisition and

conversion time to move the sixteen conversions.

The following steps should be followed for doing an

A/D conversion:

1. Configure the ADC module:

If the processor cannot unload the buffer within the

acquisition and conversion time, the BUFM bit should be

‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,

then eight conversions will be loaded into 1/2 of the

buffer, following which an interrupt occurs. The next

eight conversions will be loaded into the other 1/2 of the

buffer. The processor will have the entire time between

interrupts to move the eight conversions.

• Configure analog pins, voltage reference and

digital I/O

• Select A/D input channels

• Select A/D conversion clock

• Select A/D conversion trigger

• Turn on ADC module

2. Configure A/D interrupt (if required):

• Clear ADIF bit

The ALTS bit can be used to alternate the inputs

selected during the sampling sequence. The input

multiplexer has two sets of sample inputs: MUX A and

MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are

selected for sampling. If the ALTS bit is ‘1’ and

SMPI<3:0> = 0000 on the first sample/convert

sequence, the MUX A inputs are selected and on the

next acquire/convert sequence, the MUX B inputs are

selected.

• Select A/D interrupt priority

3. Start sampling

4. Wait the required acquisition time

5. Trigger acquisition end, start conversion

6. Wait for A/D conversion to complete, by either:

• Waiting for the A/D interrupt, or

• Waiting for the DONE bit to get set

7. Read A/D result buffer; clear ADIF if required

The CSCNA bit (ADCON2<10>) will allow the multi-

plexer input to be alternately scanned across a

selected number of analog inputs for the MUX A group.

The inputs are selected by the ADCSSL register. If a

particular bit in the ADCSSL register is ‘1’, the corre-

sponding input is selected. The inputs are always

scanned from lower to higher numbered inputs, starting

after each interrupt. If the number of inputs selected is

greater than the number of samples taken per interrupt,

the higher numbered inputs are unused.

DS70139E-page 110

dsPIC30F2011/2012/3012/3013

The internal RC oscillator is selected by setting the

ADRC bit.

16.4 Programming the Start of

Conversion Trigger

For correct ADC conversions, the ADC conversion

clock (TAD) must be selected to ensure a minimum TAD

time of 334 nsec (for VDD = 5V). Refer to Section 20.0

“Electrical Characteristics” for minimum TAD under

other operating conditions.

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the conver-

sion trigger. The SSRC bits provide for up to 4 alternate

sources of conversion trigger.

Example 16-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the conversion trigger.

EXAMPLE 16-1:

ADC CONVERSION

CLOCK AND SAMPLING

RATE CALCULATION

When SSRC<2:0> = 111(Auto-Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acquisition and the start of conversion. This provides

the fastest conversion rates on multiple channels.

SAMC must always be at least 1 clock cycle.

Minimum TAD = 334 nsec

TCY = 33 .33 nsec (30 MIPS)

TAD

TCY

334 nsec

33.33 nsec

Other trigger sources can come from timer modules or

external interrupts.

ADCS<5:0> = 2

– 1

= 2 •

– 1

16.5 Aborting a Conversion

= 19.04

Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling sequenc-

ing until the next sampling trigger. The ADCBUF will not

be updated with the partially completed A/D conversion

sample. That is, the ADCBUF will continue to contain

the value of the last completed conversion (or the last

value written to the ADCBUF register).

Therefore,

Set ADCS<5:0> = 19

TCY

2

Actual TAD =

(ADCS<5:0> + 1)

33.33 nsec

2

=

(19 + 1)

If the clearing of the ADON bit coincides with an auto-

start, the clearing has a higher priority and a new

conversion will not start.

= 334 nsec

If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’

After the A/D conversion is aborted, a 2 TAD wait is

required before the next sampling may be started by

setting the SAMP bit.

Since,

Sampling Time = Acquisition Time + Conversion Time

= 1 TAD + 14 TAD

= 15 x 334 nsec

16.6 Selecting the ADC Conversion

Clock

Therefore,

1

Sampling Rate =

(15 x 334 nsec)

The ADC conversion requires 14 TAD. The source of

the ADC conversion clock is software selected, using a

six-bit counter. There are 64 possible options for TAD.

= ~200 kHz

EQUATION 16-1: ADC CONVERSION

CLOCK

TAD = TCY * (0.5*(ADCS<5:0> + 1))

DS70139E-page 111

dsPIC30F2011/2012/3012/3013

16.7

ADC Speeds

The dsPIC30F 12-bit ADC specifications permit a max-

imum of 200 ksps sampling rate. Table 16-1 summa-

rizes the conversion speeds for the dsPIC30F 12-bit

ADC and the required operating conditions.

Figure 16-2 depicts the recommended circuit for the

conversion rates above 200 ksps. The dsPIC30F2011

is shown as an example.

TABLE 16-1: 12-BIT ADC EXTENDED CONVERSION RATES

dsPIC30F 12-bit ADC Conversion Rates

TAD

Sampling

Speed

R_sMax

VDD

Temperature

Channels Configuration

Minimum Time Min

Up to 200

ksps⁽¹⁾

334 ns

668 ns

1 TAD

2.5 kΩ

4.5V to 5.5V -40°C to +85°C

V

REF- VREF+

CHX

ANx

S/H

ADC

Up to 100

ksps

2.5 kΩ

3.0V to 5.5V -40°C to +125°C

VREF

-

V

REF

or

+

or

AVSS AVDD

CHX

ANx

S/H

ADC

ANx or VREF

-

Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure 16-2 for recommended

circuit.

FIGURE 16-2:

ADC VOLTAGE REFERENCE SCHEMATIC

VDD

See Note 1:

R2

10

VDD

C2

0.1 μF

C1

0.01 μF

VDD

C8

1 μF

C7

0.1 μF

C6

0.01 μF

R1

10

1

2

3

4

21

20

19

18

VDD

dsPIC30F2011

AVDD

VSS

6

7

VSS

15

C5

1 μF

C4

0.1 μF

C3

0.01 μF

VDD

Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.

DS70139E-page 112

dsPIC30F2011/2012/3012/3013

The configuration procedures below give the required

setup values for the conversion speeds above 100

ksps.

The following figure shows the timing diagram of the

ADC running at 200 ksps. The TAD selection in conjunc-

tion with the guidelines described above allows a con-

version speed of 200 ksps. See Example 16-1 for code

example.

16.7.1

200 KSPS CONFIGURATION

GUIDELINE

16.8 A/D Acquisition Requirements

The following configuration items are required to

achieve a 200 ksps conversion rate.

The analog input model of the 12-bit ADC is shown in

Figure 16-3. The total sampling time for the A/D is a

function of the internal amplifier settling time and the

holding capacitor charge time.

• Comply with conditions provided in Table 16-1.

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 16-2.

• Set SSRC<2.0> = 111in the ADCON1 register to

enable the auto convert option.

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the voltage level on the analog input pin. The

source impedance (RS), the interconnect impedance

(RIC), and the internal sampling switch (RSS) imped-

ance combine to directly affect the time required to

charge the capacitor CHOLD. The combined imped-

ance of the analog sources must therefore be small

enough to fully charge the holding capacitor within the

chosen sample time. To minimize the effects of pin

leakage currents on the accuracy of the ADC, the max-

imum recommended source impedance, RS, is 2.5 kΩ.

After the analog input channel is selected (changed),

this sampling function must be completed prior to start-

ing the conversion. The internal holding capacitor will

be in a discharged state prior to each sample opera-

tion.

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register.

• Write the SMPI<3.0> control bits in the ADCON2

register for the desired number of conversions

between interrupts.

• Configure the ADC clock period to be:

1

= 334 ns

(14 + 1) x 200,000

by writing to the ADCS<5:0> control bits in the

ADCON3 register.

• Configure the sampling time to be 1 TAD by

writing: SAMC<4:0> = 00001.

FIGURE 16-3:

12-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC ≤ 250Ω

RSS ≤ 3 kΩ

Sampling

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

CPIN

= DAC capacitance

VA

I leakage

500 nA

= 18 pF

VSS

Legend: CPIN

= input capacitance

= threshold voltage

VT

I leakage = leakage current at the pin due to

various junctions

RIC

= interconnect resistance

RSS

= sampling switch resistance

= sample/hold capacitance (from DAC)

CHOLD

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ.

DS70139E-page 113

dsPIC30F2011/2012/3012/3013

inates all digital switching noise from the conversion.

When the conversion is complete, the CONV bit will be

cleared and the result loaded into the ADCBUF register.

16.9 Module Power-Down Modes

The module has 2 internal power modes.

When the ADON bit is ‘1’, the module is in Active mode;

it is fully powered and functional.

If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the ADC

module will then be turned off, although the ADON bit

will remain set.

When ADON is ‘0’, the module is in Off mode. The dig-

ital and analog portions of the circuit are disabled for

maximum current savings.

16.10.2 A/D OPERATION DURING CPU IDLE

MODE

In order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will con-

tinue operation on assertion of Idle mode. If ADSIDL =

1, the module will stop on Idle.

16.10 A/D Operation During CPU Sleep

and Idle Modes

16.10.1 A/D OPERATION DURING CPU

SLEEP MODE

16.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the ADC module to be turned off, and any

conversion and sampling sequence is aborted. The val-

ues that are in the ADCBUF registers are not modified.

The A/D Result register will contain unknown data after

a Power-on Reset.

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the con-

version is aborted. The converter will not continue with

a partially completed conversion on exit from Sleep

mode.

Register contents are not affected by the device

entering or leaving Sleep mode.

16.12 Output Formats

The A/D result is 12 bits wide. The data buffer RAM is

also 12 bits wide. The 12-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

The ADC module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the RC

clock source is selected, the ADC module waits one

instruction cycle before starting the conversion. This

allows the SLEEPinstruction to be executed which elim-

FIGURE 16-4:

RAM Contents:

Read to Bus:

A/D OUTPUT DATA FORMATS

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Signed Fractional

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0

Fractional

Signed Integer

Integer

d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

DS70139E-page 114

dsPIC30F2011/2012/3012/3013

16.13 Configuring Analog Port Pins

16.14 Connection Considerations

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

The analog inputs have diodes to VDD and VSS as ESD

protection. This requires that the analog input be

between VDD and VSS. If the input voltage exceeds this

range by greater than 0.3V (either direction), one of the

diodes becomes forward biased and it may damage the

device if the input current specification is exceeded.

The A/D operation is independent of the state of the

CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.

An external RC filter is sometimes added for anti-

aliasing of the input signal. The R component should be

selected to ensure that the sampling time requirements

are satisfied. Any external components connected (via

high-impedance) to an analog input pin (capacitor,

zener diode, etc.) should have very little leakage

current at the pin.

When reading the PORT register, all pins configured as

analog input channels will read as cleared.

Pins configured as digital inputs will not convert an ana-

log input. Analog levels on any pin that is defined as a

digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

DS70139E-page 115

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 118

dsPIC30F2011/2012/3012/3013

17.1 Oscillator System Overview

17.0 SYSTEM INTEGRATION

The dsPIC30F oscillator system has the following

modules and features:

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to boost internal operating

frequency

• A clock switching mechanism between various

clock sources

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide Power Saving Operating

modes and offer code protection:

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• Oscillator Selection

• Reset

• Clock Control register (OSCCON)

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Programmable Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• Low-Voltage Detect

• Configuration bits for main oscillator selection

Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).

Thereafter, the clock source can be changed between

permissible clock sources. The OSCCON register con-

trols the clock switching and reflects system clock

related status bits.

• Power-Saving Modes (Sleep and Idle)

• Code Protection

Table 17-1 provides a summary of the dsPIC30F Oscil-

lator Operating modes. A simplified diagram of the

oscillator system is shown in Figure 17-1.

• Unit ID Locations

• In-Circuit Serial Programming (ICSP)

dsPIC30F devices have a Watchdog Timer which is

permanently enabled via the Configuration bits or can

be software controlled. It runs off its own RC oscillator

for added reliability. There are two timers that offer

necessary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

Reset until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT) which provides a delay on

power-up only, designed to keep the part in Reset while

the power supply stabilizes. With these two timers

on-chip, most applications need no external Reset

circuitry.

Sleep mode is designed to offer a very low current

Power-Down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit a wide variety of

applications. In the Idle mode, the clock sources are

still active but the CPU is shut-off. The RC oscillator

option saves system cost while the LP crystal option

saves power.

DS70139E-page 119

dsPIC30F2011/2012/3012/3013

TABLE 17-1: OSCILLATOR OPERATING MODES

Oscillator Mode

XTL

Description

200 kHz-4 MHz crystal on OSC1:OSC2.

4 MHz-10 MHz crystal on OSC1:OSC2.

XT

XT w/PLL 4x

XT w/PLL 8x

XT w/PLL 16x

LP

4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled.

4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled.

4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled⁽¹⁾

.

32 kHz crystal on SOSCO:SOSCI⁽²⁾

.

HS

10 MHz-25 MHz crystal.

HS/2 w/PLL 4x

HS/2 w/PLL 8x

HS/2 w/PLL 16x

HS/3 w/PLL 4x

HS/3 w/PLL 8x

HS/3 w/PLL 16x

EC

10 MHz -20 MHz crystal, divide by 2, 4x PLL enabled.

10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled.

10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled⁽¹⁾

12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled.

12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled.

.

12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled⁽¹⁾

.

External clock input (0-40 MHz).

ECIO

External clock input (0-40 MHz), OSC2 pin is I/O.

EC w/PLL 4x

EC w/PLL 8x

EC w/PLL 16x

ERC

External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled.

External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled.

External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled⁽¹⁾

.

External RC oscillator, OSC2 pin is FOSC/4 output⁽³⁾

.

ERCIO

External RC oscillator, OSC2 pin is I/O⁽³⁾

7.37 MHz internal RC oscillator.

.

FRC

FRC w/PLL 4x

FRC w/PLL 8x

FRC w/PLL 16x

LPRC

7.37 MHz Internal RC oscillator, 4x PLL enabled.

7.37 MHz Internal RC oscillator, 8x PLL enabled.

7.37 MHz Internal RC oscillator, 16x PLL enabled.

512 kHz internal RC oscillator.

Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.

2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1.

3: Requires external R and C. Frequency operation up to 4 MHz.

DS70139E-page 120

dsPIC30F2011/2012/3012/3013

FIGURE 17-1:

OSCILLATOR SYSTEM BLOCK DIAGRAM

Oscillator Configuration bits

PWRSAVInstruction

Wake-up Request

FPLL

OSC1

OSC2

Primary

PLL

Oscillator

x4, x8, x16

PLL

Lock

Primary Osc

COSC<2:0>

NOSC<2:0>

OSWEN

Internal FRC Osc

Primary

Oscillator

Internal Fast RC

Oscillator (FRC)

Stability Detector

Oscillator

Start-up

Timer

POR Done

Clock

Programmable

Switching

and Control

Block

Secondary Osc

Clock Divider

System

Clock

SOSCO

SOSCI

Secondary

Oscillator

Stability Detector

32 kHz LP

Oscillator

2

POST<1:0>

LPRC

Internal Low

Power RC

Oscillator (LPRC)

CF

Fail-Safe Clock

Monitor (FSCM)

FCKSM<1:0>

2

Oscillator Trap

To Timer1

DS70139E-page 121

dsPIC30F2011/2012/3012/3013

17.2.2

OSCILLATOR START-UP TIMER

(OST)

17.2 Oscillator Configurations

17.2.1

INITIAL CLOCK SOURCE

SELECTION

In order to ensure that a crystal oscillator (or ceramic

resonator) has started and stabilized, an Oscillator

Start-up Timer is included. It is a simple 10-bit counter

that counts 1024 TOSC cycles before releasing the

oscillator clock to the rest of the system. The time-out

period is designated as TOST.

While coming out of Power-on Reset or Brown-out

Reset, the device selects its clock source based on:

a) FOS<2:0> Configuration bits that select one of

four oscillator groups,

The TOST time is involved every time the oscillator has

to restart (i.e., on POR, BOR and wake-up from Sleep).

The Oscillator Start-up Timer is applied to the LP oscil-

lator, XT, XTL and HS modes (upon wake-up from

Sleep, POR and BOR) for the primary oscillator.

b) and FPR<4:0> Configuration bits that select one

of 15 oscillator choices within the primary group.

The selection is as shown in Table 17-2.

TABLE 17-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator

OSC2

Function

Oscillator Mode

FOS<2:0>

FPR<4:0>

Source

ECIO w/PLL 4x

PLL

1

0

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

I/O

ECIO wPLL 8x

ECIO w/ PLL 16x

FRC w/PLL 4X

FRC w/PLL 8x

FRC w/PLL 16x

XT wPLL 4x

XT w/PLL 8x

XT w/PLL 16x

HS2 w/PLL 4x

HS2 wPLL 8x

HS2 w/ PLL 16x

HS3 w/PLL 4x

HS3 w/PLL 8x

HS3 w/PLL 16x

ECIO

PLL

I/O

PLL

I/O

PLL

I/O

PLL

I/O

PLL

OSC2

I/O

PLL

External

Secondary

Internal FRC

Internal LPRC

XT

OSC2

CLKO

I/O

HS

EC

ERC

ERCIO

XTL

OSC2

(Note 1, 2)

LP

FRC

LPRC

Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<4:0>).

2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is

selected at all times.

DS70139E-page 122

dsPIC30F2011/2012/3012/3013

17.2.3

LP OSCILLATOR CONTROL

Note:

When a 16x PLL is used, the FRC fre-

quency must not be tuned to a frequency

greater than 7.5 MHz.

Enabling the LP oscillator is controlled with two elements:

1. The current oscillator group bits COSC<2:0>.

2. The LPOSCEN bit (OSCCON register).

TABLE 17-4: FRC TUNING

TUN<3:0>

The LP oscillator is on (even during Sleep mode) if

LPOSCEN = 1. The LP oscillator is the device clock if:

FRC Frequency

Bits

• COSC<2:0> = 000(LP selected as main oscillator)

0111

0110

0101

0100

0011

0010

0001

0000

+ 10.5%

+ 9.0%

+ 7.5%

+ 6.0%

+ 4.5%

+ 3.0%

+ 1.5%

and

• LPOSCEN = 1

Keeping the LP oscillator on at all times allows for a fast

switch to the 32 kHz system clock for lower power oper-

ation. Returning to the faster main oscillator will still

require a start-up time

17.2.4

PHASE LOCKED LOOP (PLL)

Center Frequency (oscillator is

running at calibrated frequency)

The PLL multiplies the clock which is generated by the

primary oscillator or Fast RC oscillator. The PLL is

selectable to have either gains of x4, x8, and x16. Input

and output frequency ranges are summarized in

Table 17-3.

1111

1110

1101

1100

1011

1010

1001

1000

- 1.5%

- 3.0%

- 4.5%

- 6.0%

- 7.5%

- 9.0%

- 10.5%

- 12.0%

TABLE 17-3: PLL FREQUENCY RANGE

PLL

FIN

FOUT

Multiplier

4 MHz-10 MHz

4 MHz-7.5 MHz

x4

x8

16 MHz-40 MHz

32 MHz-80 MHz

64 MHz-120 MHz

17.2.6

LOW-POWER RC OSCILLATOR

(LPRC)

x16

The PLL features a lock output which is asserted when

the PLL enters a phase locked state. Should the loop

fall out of lock (e.g., due to noise), the lock signal will be

rescinded. The state of this signal is reflected in the

read-only LOCK bit in the OSCCON register.

The LPRC oscillator is a component of the Watchdog

Timer (WDT) and oscillates at a nominal frequency of

512 kHz. The LPRC oscillator is the clock source for

the Power-up Timer (PWRT) circuit, WDT and clock

monitor circuits. It may also be used to provide a low-

frequency clock source option for applications where

power consumption is critical and timing accuracy is

not required.

17.2.5

FAST RC OSCILLATOR (FRC)

The FRC oscillator is a fast (7.37 MHz ±2% nominal)

internal RC oscillator. This oscillator is intended to pro-

vide reasonable device operating speeds without the

use of an external crystal, ceramic resonator, or RC

network. The FRC oscillator can be used with the PLL

to obtain higher clock frequencies.

The LPRC oscillator is always enabled at a Power-on

Reset because it is the clock source for the PWRT.

After the PWRT expires, the LPRC oscillator will

remain on if one of the following is true:

• The Fail-Safe Clock Monitor is enabled

• The WDT is enabled

The dsPIC30F operates from the FRC oscillator when-

ever the current oscillator selection control bits in the

OSCCON register (OSCCON<14:12>) are set to ‘001’.

• The LPRC oscillator is selected as the system

clock via the COSC<2:0> control bits in the

OSCCON register

The four bit field specified by TUN<3:0> (OSCTUN

<3:0>) allows the user to tune the internal fast RC

oscillator (nominal 7.37 MHz). The user can tune the

FRC oscillator within a range of +10.5% (840 kHz)

and -12% (960 kHz) in steps of 1.50% around the

factory-calibrated setting, see Table 17-4.

If one of the above conditions is not true, the LPRC will

shut-off after the PWRT expires.

Note 1: OSC2 pin function is determined by the

Primary Oscillator mode selection

(FPR<4:0>).

If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are

set to ‘00001’, ‘01010’ or ‘00011’, then a PLL

multiplier of 4, 8 or 16 (respectively) is applied.

2: OSC1 pin cannot be used as an I/O pin

even if the secondary oscillator or an

internal clock source is selected at all

times.

DS70139E-page 123

dsPIC30F2011/2012/3012/3013

The OSCCON register holds the Control and Status

bits related to clock switching.

17.2.7

FAIL-SAFE CLOCK MONITOR

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by appropriately

programming the FCKSM Configuration bits (clock

switch and monitor selection bits) in the FOSC Device

Configuration register. If the FSCM function is enabled,

the LPRC internal oscillator will run at all times (except

during Sleep mode) and will not be subject to control by

the SWDTEN bit.

• COSC<2:0>: Read-only bits always reflect the

current oscillator group in effect.

• NOSC<2:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<2:0> and

NOSC<2:0> are both loaded with the Config-

uration bit values FOS<2:0>.

• LOCK: The LOCK bit indicates a PLL lock.

In the event of an oscillator failure, the FSCM will gen-

erate a clock failure trap event and will switch the sys-

tem clock over to the FRC oscillator. The user will then

have the option to either attempt to restart the oscillator

or execute a controlled shutdown. The user may decide

to treat the trap as a warm Reset by simply loading the

Reset address into the oscillator fail trap vector. In this

event, the CF (Clock Fail) bit (OSCCON<3>) is also set

whenever a clock failure is recognized.

• CF: Read-only bit indicating if a clock fail detect

has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If Configuration bits FCKSM<1:0> = 1x, then the clock

switching and Fail-Safe Clock monitoring functions are

disabled. This is the default Configuration bit setting.

In the event of a clock failure, the WDT is unaffected

and continues to run on the LPRC clock.

If clock switching is disabled, then the FOS<2:0> and

FPR<4:0> bits directly control the oscillator selection

and the COSC<2:0> bits do not control the clock selec-

tion. However, these bits will reflect the clock source

selection.

If the oscillator has a very slow start-up time coming out

of POR, BOR or Sleep, it is possible that the PWRT

timer will expire before the oscillator has started. In

such cases, the FSCM will be activated and the FSCM

will initiate a clock failure trap, and the COSC<2:0> bits

are loaded with FRC oscillator selection. This will effec-

tively shut-off the original oscillator that was trying to

start.

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 kHz when the Fail-Safe Clock Monitor

is enabled. If such clock switching is

performed, the device may generate an

oscillator fail trap and switch to the Fast RC

oscillator.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC oscillator as follows:

1. The COSC bits (OSCCON<14:12>) are loaded

with the FRC oscillator selection value.

17.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

2. CF bit is set (OSCCON<3>).

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

3. OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

1. Primary (with or without PLL)

2. Secondary

3. Internal FRC

Byte Write “0x46” to OSCCON low

Byte Write “0x57” to OSCCON low

4. Internal LPRC

The user can switch between these functional groups

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group is always determined by the FPR<4:0> Configu-

ration bits.

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

Byte Write“0x78” to OSCCON high

Byte Write“0x9A” to OSCCON high

Byte write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

DS70139E-page 124

dsPIC30F2011/2012/3012/3013

Different registers are affected in different ways by var-

ious Reset conditions. Most registers are not affected

17.3 Reset

The PIC18F1220/1320 differentiates between various

kinds of Reset:

by a WDT wake-up since this is viewed as the resump-

tion of normal operation. Status bits from the RCON

register are set or cleared differently in different Reset

situations, as indicated in Table 17-5. These bits are

used in software to determine the nature of the Reset.

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

A block diagram of the On-Chip Reset Circuit is shown

in Figure 17-2.

d) Watchdog Timer (WDT) Reset (during normal

operation)

A MCLR noise filter is provided in the MCLR Reset

path. The filter detects and ignores small pulses.

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

Internally generated Resets do not drive MCLR pin low.

g) Reset caused by trap lockup (TRAPR)

h) Reset caused by illegal opcode or by using an

uninitialized W register as an address pointer

(IOPUWR)

FIGURE 17-2:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Digital

Glitch Filter

MCLR

Sleep or Idle

WDT

Module

POR

VDD Rise

Detect

S

VDD

Brown-out

Reset

BOR

BOREN

Q

R

SYSRST

Trap Conflict

Illegal Opcode/

Uninitialized W Register

The POR circuit inserts a small delay, TPOR, which is

nominally 10 μs and ensures that the device bias cir-

cuits are stable. Furthermore, a user selected power-

up time-out (TPWRT) is applied. The TPWRT parameter

is based on device Configuration bits and can be 0 ms

(no delay), 4 ms, 16 ms or 64 ms. The total delay is at

device power-up, TPOR + TPWRT. When these delays

have expired, SYSRST will be negated on the next

leading edge of the Q1 clock and the PC will jump to the

Reset vector.

17.3.1

POR: POWER-ON RESET

A power-on event will generate an internal POR pulse

when a VDD rise is detected. The Reset pulse will occur

at the POR circuit threshold voltage (VPOR) which is

nominally 1.85V. The device supply voltage character-

istics must meet specified starting voltage and rise rate

requirements. The POR pulse will reset a POR timer

and place the device in the Reset state. The POR also

selects the device clock source identified by the

oscillator configuration fuses.

The timing for the SYSRST signal is shown in

Figure 17-3 through Figure 17-5.

DS70139E-page 125

dsPIC30F2011/2012/3012/3013

FIGURE 17-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TOST

OST TIME-OUT

TPWRT

PWRT TIME-OUT

INTERNAL Reset

FIGURE 17-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TOST

OST TIME-OUT

TPWRT

PWRT TIME-OUT

INTERNAL Reset

FIGURE 17-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TOST

OST TIME-OUT

TPWRT

PWRT TIME-OUT

INTERNAL Reset

DS70139E-page 126

dsPIC30F2011/2012/3012/3013

selected, the BOR will activate the Oscillator Start-up

Timer (OST). The system clock is held until OST

expires. If the PLL is used, then the clock will be held

until the LOCK bit (OSCCON<5>) is ‘1’.

17.3.1.1

POR with Long Crystal Start-up Time

(with FSCM Enabled)

The oscillator start-up circuitry is not linked to the POR

circuitry. Some crystal circuits (especially low fre-

quency crystals) will have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the POR timer and the PWRT have

expired:

Concurrently, the POR time-out (TPOR) and the PWRT

time-out (TPWRT) will be applied before the internal Reset

is released. If TPWRT = 0and a crystal oscillator is being

used, then a nominal delay of TFSCM = 100 μs is applied.

The total delay in this case is (TPOR + TFSCM).

• The oscillator circuit has not begun to oscillate.

The BOR Status bit (RCON<1>) will be set to indicate

that a BOR has occurred. The BOR circuit, if enabled,

will continue to operate while in Sleep or Idle modes

and will reset the device should VDD fall below the BOR

threshold voltage.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a LOCK (if PLL is

used).

If the FSCM is enabled and one of the above conditions

is true, then a clock failure trap will occur. The device

will automatically switch to the FRC oscillator and the

user can switch to the desired crystal oscillator in the

trap ISR.

FIGURE 17-6:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

VDD

17.3.1.2

Operating without FSCM and PWRT

D

If the FSCM is disabled and the Power-up Timer

(PWRT) is also disabled, then the device will exit rap-

idly from Reset on power-up. If the clock source is

FRC, LPRC, ERC or EC, it will be active immediately.

R

R1

MCLR

dsPIC30F

C

If the FSCM is disabled and the system clock has not

started, the device will be in a frozen state at the Reset

vector until the system clock starts. From the user’s

perspective, the device will appear to be in Reset until

a system clock is available.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R should be suitably chosen so as to make

sure that the voltage drop across R does not

violate the device’s electrical specifications.

3: R1 should be suitably chosen so as to limit

any current flowing into MCLR from external

capacitor C, in the event of MCLR/VPP pin

breakdown due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

17.3.2

BOR: PROGRAMMABLE

BROWN-OUT RESET

The BOR (Brown-out Reset) module is based on an

internal voltage reference circuit. The main purpose of

the BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (i.e.,

missing portions of the AC cycle waveform due to bad

power transmission lines, or voltage sags due to exces-

sive current draw when a large inductive load is turned

on).

Note:

Dedicated supervisory devices, such as

the MCP1XX and MCP8XX, may also be

used as an external Power-on Reset

circuit.

The BOR module allows selection of one of the

following voltage trip points (see Table 20-11):

• 2.6V-2.71V

• 4.1V-4.4V

• 4.58V-4.73V

Note:

The BOR voltage trip points indicated here

are nominal values provided for design

guidance only. Refer to the Electrical

Specifications in the specific device data

sheet for BOR voltage limit specifications.

A BOR will generate a Reset pulse which will reset the

device. The BOR will select the clock source based on

the device Configuration bit values (FOS<2:0> and

FPR<4:0>). Furthermore, if an Oscillator mode is

DS70139E-page 127

dsPIC30F2011/2012/3012/3013

Table 17-5 shows the Reset conditions for the RCON

register. Since the control bits within the RCON register

are R/W, the information in the table means that all the

bits are negated prior to the action specified in the

condition column.

TABLE 17-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1

Program

Condition

TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Counter

Power-on Reset

Brown-out Reset

0x000000

0

1

0

1

0

1

0

MCLR Reset during normal 0x000000

operation

Software Reset during

normal operation

0x000000

0

1

0

MCLR Reset during Sleep

MCLR Reset during Idle

WDT Time-out Reset

WDT Wake-up

0x000000

PC + 2

0

1

0

1

0

1

0

1

0

1

0

Interrupt Wake-up from

Sleep

PC + 2⁽¹⁾

Clock Failure Trap

Trap Reset

0x000004

0x000000

0

1

0

1

0

Illegal Operation Trap

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

Table 17-6 shows a second example of the bit

conditions for the RCON register. In this case, it is not

assumed the user has set/cleared specific bits prior to

action specified in the condition column.

TABLE 17-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2

Program

Condition

TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR

Counter

Power-on Reset

0x000000

0

u

0

u

0

u

1

0

u

0

u

0

u

0

u

0

1

0

u

1

u

Brown-out Reset

MCLR Reset during normal

operation

Software Reset during

normal operation

0x000000

u

0

1

0

u

MCLR Reset during Sleep

MCLR Reset during Idle

WDT Time-out Reset

WDT Wake-up

0x000000

PC + 2

u

1

0

u

0

u

0

1

u

0

1

0

u

1

0

1

u

Interrupt Wake-up from

Sleep

PC + 2⁽¹⁾

Clock Failure Trap

Trap Reset

0x000004

0x000000

u

1

u

1

u

Illegal Operation Reset

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’

Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.

DS70139E-page 128

dsPIC30F2011/2012/3012/3013

17.4 Watchdog Timer (WDT)

17.6 Power-Saving Modes

There are two power-saving states that can be entered

through the execution of a special instruction, PWRSAV;

17.4.1 WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software mal-

function. The WDT is a free-running timer which runs

off an on-chip RC oscillator, requiring no external com-

ponent. Therefore, the WDT timer will continue to oper-

ate even if the main processor clock (e.g., the crystal

oscillator) fails.

these are Sleep and Idle.

The format of the PWRSAVinstruction is as follows:

PWRSAV <parameter>, where ‘parameter’ defines

Idle or Sleep mode.

17.6.1

SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is

shut down. If an on-chip oscillator is being used, it is

shut down.

17.4.2

ENABLING AND DISABLING

THE WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register, FWDT.

The Fail-Safe Clock Monitor is not functional during

Sleep since there is no clock to monitor. However,

LPRC clock remains active if WDT is operational during

Sleep.

Setting FWDTEN = 1enables the Watchdog Timer. The

enabling is done when programming the device. By

default, after chip erase, FWDTEN bit = 1. Any device

programmer capable of programming dsPIC30F

devices allows programming of this and other Configu-

ration bits.

The brown-out protection circuit and the Low-Voltage

Detect circuit, if enabled, will remain functional during

Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

If enabled, the WDT will increment until it overflows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR, BOR and MCLR)

• WDT time-out

If a WDT times out during Sleep, the device will wake-

up. The WDTO bit in the RCON register will be cleared

to indicate a wake-up resulting from a WDT time-out.

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry into

Sleep mode. When clock switching is enabled, bits

COSC<2:0> will determine the oscillator source that

will be used on wake-up. If clock switch is disabled,

then there is only one system clock.

Setting FWDTEN = 0 allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

Note:

If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<2:0>

and FPR<4:0> Configuration bits.

17.5 Low Voltage Detect

The Low Voltage Detect (LVD) module is used to detect

when the VDD of the device drops below a threshold

value, VLVD, which is determined by the LVDL<3:0>

bits (RCON<11:8>) and is thus user programmable.

The internal voltage reference circuitry requires a nom-

inal amount of time to stabilize, and the BGST bit

(RCON<13>) indicates when the voltage reference has

stabilized.

If the clock source is an oscillator, the clock to the

device will be held off until OST times out (indicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1 (indicating that the PLL is

stable). In either case, TPOR, TLOCK and TPWRT delays

are applied.

If EC, FRC, LPRC or ERC oscillators are used, then a

delay of TPOR (~ 10 μs) is applied. This is the smallest

delay possible on wake-up from Sleep.

In some devices, the LVD threshold voltage may be

applied externally on the LVDIN pin.

Moreover, if LP oscillator was active during Sleep and

LP is the oscillator used on wake-up, then the start-up

delay will be equal to TPOR. PWRT delay and OST

timer delay are not applied. In order to have the small-

est possible start-up delay when waking up from Sleep,

one of these faster wake-up options should be selected

before entering Sleep.

The LVD module is enabled by setting the LVDEN bit

(RCON<12>).

DS70139E-page 129

dsPIC30F2011/2012/3012/3013

Any interrupt that is individually enabled (using the cor-

responding IE bit) and meets the prevailing priority level

will be able to wake-up the processor. The processor will

process the interrupt and branch to the ISR. The Sleep

Status bit in the RCON register is set upon wake-up.

Any interrupt that is individually enabled (using IE bit)

and meets the prevailing priority level will be able to

wake-up the processor. The processor will process the

interrupt and branch to the ISR. The Idle Status bit in

the RCON register is set upon wake-up.

Any Reset other than POR will set the Idle Status bit.

On a POR, the Idle bit is cleared.

Note:

In spite of various delays applied (TPOR,

TLOCK and TPWRT), the crystal oscillator

(and PLL) may not be active at the end of

the time-out (e.g., for low-frequency crys-

tals). In such cases, if FSCM is enabled,

then the device will detect this as a clock

failure and process the clock failure trap, the

FRC oscillator will be enabled and the user

will have to re-enable the crystal oscillator. If

FSCM is not enabled, then the device will

simply suspend execution of code until the

clock is stable and will remain in Sleep until

the oscillator clock has started.

If Watchdog Timer is enabled, then the processor will

wake-up from Idle mode upon WDT time-out. The Idle

and WDTO Status bits are both set.

Unlike wake-up from Sleep, there are no time delays

involved in wake-up from Idle.

17.7 Device Configuration Registers

The Configuration bits in each device Configuration

register specify some of the device modes and are

programmed by a device programmer, or by using the

In-Circuit Serial Programming™ (ICSP™) feature of

the device. Each device Configuration register is a

24-bit register, but only the lower 16 bits of each regis-

ter are used to hold configuration data. There are four

device Configuration registers available to the user:

All Resets will wake-up the processor from Sleep

mode. Any Reset, other than POR, will set the Sleep

Status bit. In a POR, the Sleep bit is cleared.

If the Watchdog Timer is enabled, then the processor

will wake-up from Sleep mode upon WDT time-out. The

Sleep and WDTO Status bits are both set.

1. FOSC (0xF80000): Oscillator Configuration

Register

17.6.2

IDLE MODE

2. FWDT (0xF80002): Watchdog Timer

Configuration Register

In Idle mode, the clock to the CPU is shut down while

peripherals keep running. Unlike Sleep mode, the clock

source remains active.

3. FBORPOR (0xF80004): BOR and POR

Configuration Register

4. FGS (0xF8000A): General Code Segment

Configuration Register

Several peripherals have a control bit in each module

that allows them to operate during Idle.

The placement of the Configuration bits is automati-

cally handled when you select the device in your device

programmer. The desired state of the Configuration bits

may be specified in the source code (dependent on the

language tool used), or through the programming

interface. After the device has been programmed, the

application software may read the Configuration bit

values through the table read instructions. For addi-

tional information, please refer to the Programming

Specifications of the device.

LPRC Fail-Safe Clock remains active if clock failure

detect is enabled.

The processor wakes up from Idle if at least one of the

following conditions has occurred:

• any interrupt that is individually enabled (IE bit is

‘1’) and meets the required priority level

• any Reset (POR, BOR, MCLR)

• WDT time-out

Upon wake-up from Idle mode, the clock is re-applied

to the CPU and instruction execution begins immedi-

ately, starting with the instruction following the PWRSAV

instruction.

Note:

If the code protection Configuration fuse

bits (FGS<GCP> and FGS<GWRP>)

have been programmed, an erase of the

entire code-protected device is only

possible at voltages VDD ≥ 4.5V.

DS70139E-page 130

dsPIC30F2011/2012/3012/3013

17.8 Peripheral Module Disable (PMD)

17.9 In-Circuit Debugger

Registers

When MPLAB^®ICD2 is selected as a Debugger, the In-

Circuit Debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. When the device has this feature enabled,

some of the resources are not available for general

use. These resources include the first 80 bytes of Data

RAM and two I/O pins.

The Peripheral Module Disable (PMD) registers pro-

vide a method to disable a peripheral module by stop-

ping all clock sources supplied to that module. When a

peripheral is disabled via the appropriate PMD control

bit, the peripheral is in a minimum power consumption

state. The Control and Status registers associated with

the peripheral will also be disabled so writes to those

registers will have no effect and read values will be

invalid.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC, EMUD1/

EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.

A peripheral module will only be enabled if both the

associated bit in the the PMD register is cleared and

the peripheral is supported by the specific dsPIC DSC

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

In each case, the selected EMUD pin is the Emulation/

Debug Data line, and the EMUC pin is the Emulation/

Debug Clock line. These pins will interface to the

MPLAB ICD 2 module available from Microchip. The

selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send and receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD and the selected EMUDx/EMUCx pin pair.

Note:

If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of 1 instruction

cycle. Similarly, if a PMD bit is cleared, the

corresponding module is enabled after a

delay of 1 instruction cycle (assuming the

module Control registers are already

configured to enable module operation).

This gives rise to two possibilities:

1. If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

Note:

In the dsPIC30F2011, dsPIC30F3012 and

dsPIC30F2012 devices, the U2MD bit is

readable and writable and will be read as

‘1’ when set.

2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/

EMUC3 is selected as the Debug I/O pin pair,

then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

DS70139E-page 131

dsPIC30F2011/2012/3012/3013

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

18.0 INSTRUCTION SET SUMMARY

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F

Programmer’s Reference Manual” (DS70030).

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

The literal instructions that involve data movement may

use some of the following operands:

The dsPIC30F instruction set adds many

enhancements to the previous PIC^®MCU instruction

sets, while maintaining an easy migration from

MCU instruction sets.

PIC

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode which specifies the instruction

type, and one or more operands which further specify

the operation of the instruction.

• The first source operand which is a register ‘Wb’

without any address modifier

• The second source operand which is a literal

value

The instruction set is highly orthogonal and is grouped

into five basic categories:

• The destination of the result (only if not the same

as the first source operand) which is typically a

register ‘Wd’ with or without an address modifier

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

The MACclass of DSP instructions may use some of the

following operands:

• DSP operations

• The accumulator (A or B) to be used (required

operand)

• Control operations

Table 18-1 shows the general symbols used in

describing the instructions.

• The W registers to be used as the two operands

• The X and Y address space prefetch operations

• The X and Y address space prefetch destinations

• The accumulator write-back destination

The dsPIC30F instruction set summary in Table 18-2

lists all the instructions, along with the status flags

affected by each instruction.

The other DSP instructions do not involve any

multiplication, and may include:

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The accumulator to be used (required)

• The first source operand which is typically a

register ‘Wb’ without any address modifier

• The source or destination operand (designated as

Wso or Wdo, respectively) with or without an

address modifier

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The amount of shift specified by a W register ‘Wn’

or a literal value

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

The control instructions may use some of the following

operands:

However, word or byte-oriented file register instructions

have two operands:

• A program memory address

• The file register specified by the value ‘f’

• The mode of the table read and table write

instructions

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

DS70139E-page 133

dsPIC30F2011/2012/3012/3013

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

which are single-word instructions but take two or three

cycles. Certain instructions that involve skipping over

the subsequent instruction require either two or three

cycles if the skip is performed, depending on whether

the instruction being skipped is a single-word or two-

word instruction. Moreover, double-word moves

require two cycles. The double-word instructions

execute in two instruction cycles.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes, and RETURN/RETFIE instructions,

Note:

For more details on the instruction set,

refer to the Programmer’s Reference

Manual.

TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

Register bit field

<n:m>

.b

Byte mode selection

.d

Double-Word mode selection

Shadow register select

.S

.w

Word mode selection (default)

One of two accumulators {A, B}

Acc

AWB

bit4

Accumulator write-back destination address register ∈ {W13, [W13]+=2}

4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address ∈ {0x0000...0x1FFF}

C, DC, N, OV, Z

Expr

f

lit1

1-bit unsigned literal ∈ {0,1}

lit4

4-bit unsigned literal ∈ {0...15}

lit5

5-bit unsigned literal ∈ {0...31}

lit8

8-bit unsigned literal ∈ {0...255}

lit10

10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal ∈ {0...16384}

lit14

lit16

16-bit unsigned literal ∈ {0...65535}

lit23

23-bit unsigned literal ∈ {0...8388608}; LSB must be 0

Field does not require an entry, may be blank

DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

Program Counter

None

OA, OB, SA, SB

PC

Slit10

Slit16

Slit6

10-bit signed literal ∈ {-512...511}

16-bit signed literal ∈ {-32768...32767}

6-bit signed literal ∈ {-16...16}

DS70139E-page 134

dsPIC30F2011/2012/3012/3013

TABLE 18-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field

Description

Wb

Base W register ∈ {W0..W15}

Wd

Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Dividend, Divisor working register pair (direct addressing)

Wm*Wm

Multiplicand and Multiplier working register pair for Square instructions ∈

{W4*W4,W5*W5,W6*W6,W7*W7}

Wm*Wn

Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}

Wn

One of 16 working registers ∈ {W0..W15}

Wnd

Wns

WREG

Ws

One of 16 destination working registers ∈ {W0..W15}

One of 16 source working registers ∈ {W0..W15}

W0 (working register used in file register instructions)

Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso

Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx

X data space prefetch address register for DSP instructions

∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,

[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,

[W9+W12],none}

Wxd

Wy

X data space prefetch destination register for DSP instructions ∈ {W4..W7}

Y data space prefetch address register for DSP instructions

∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,

[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,

[W11+W12], none}

Wyd

Y data space prefetch destination register for DSP instructions ∈ {W4..W7}

DS70139E-page 135

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

1

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

Acc

Add Accumulators

1

OA,OB,SA,SB

C,DC,N,OV,Z

OA,OB,SA,SB

C,DC,N,OV,Z

N,Z

f

f = f + WREG

f,WREG

WREG = f + WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

16-bit Signed Add to Accumulator

f = f + WREG + (C)

1

2

3

4

ADDC

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

Wd = Wb + lit5 + (C)

1

AND

f = f .AND. WREG

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

1

N,Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N,Z

Wd = Wb .AND. Ws

1

N,Z

Wd = Wb .AND. lit5

1

N,Z

ASR

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C,N,OV,Z

N,Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N,Z

5

6

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

None

Branch if unsigned less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OA,Expr

OB,Expr

OV,Expr

SA,Expr

SB,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Accumulator A overflow

Branch if Accumulator B overflow

Branch if Overflow

None

Branch if Accumulator A saturated

Branch if Accumulator B saturated

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

7

8

BSET

BSW

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

1

None

Ws,Wb

1

None

DS70139E-page 136

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

9

BTG

f,#bit4

Ws,#bit4

f,#bit4

Bit Toggle f

1

None

BTG

Bit Toggle Ws

10

11

12

BTSC

Bit Test f, Skip if Clear

Bit Test Ws, Skip if Clear

Bit Test f, Skip if Set

1

(2 or 3)

BTSC

BTSS

Ws,#bit4

f,#bit4

Ws,#bit4

1

None

(2 or 3)

BTSS

BTST

1

(2 or 3)

Bit Test Ws, Skip if Set

1

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

C

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Ws,Wb

Z

13

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call subroutine

C

Z

14

15

CALL

CLR

CALL

CLR

CLRWDT

COM

CP

lit23

None

Wn

Call indirect subroutine

f = 0x0000

None

f

None

WREG

WREG = 0x0000

None

Ws

Ws = 0x0000

None

Acc,Wx,Wxd,Wy,Wyd,AWB

Clear Accumulator

Clear Watchdog Timer

f = f

OA,OB,SA,SB

WDTO,Sleep

N,Z

16

17

CLRWDT

COM

f

f,WREG

Ws,Wd

f

WREG = f

N,Z

Wd = Ws

N,Z

18

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb - Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C,DC,N,OV,Z

CP

Wb,#lit5

Wb,Ws

f

CP

19

20

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb - Ws - C)

21

22

23

24

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb, Wn

Compare Wb with Wn, skip if =

Compare Wb with Wn, skip if >

Compare Wb with Wn, skip if <

Compare Wb with Wn, skip if ≠

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

25

26

DAW

DEC

DAW

Wn

Wn = decimal adjust Wn

1

C

DEC

f

f = f -1

C,DC,N,OV,Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f -1

DEC

Wd = Ws - 1

27

28

DEC2

DISI

DEC2

DISI

f = f -2

f,WREG

Ws,Wd

#lit14

WREG = f -2

Wd = Ws - 2

Disable Interrupts for k instruction cycles

DS70139E-page 137

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

29

DIV

DIV.S

DIV.SD

DIV.U

DIV.UD

DIVF

DO

Wm,Wn

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Signed 16/16-bit Fractional Divide

Do code to PC+Expr, lit14+1 times

Do code to PC+Expr, (Wn)+1 times

Euclidean Distance (no accumulate)

1

2

1

18

2

N,Z,C,OV

None

Wm,Wn

30

31

DIVF

DO

Wm,Wn

#lit14,Expr

Wn,Expr

DO

2

None

32

33

ED

Wm*Wm,Acc,Wx,Wy,Wxd

1

OA,OB,OAB,

SA,SB,SAB

EDAC

Wm*Wm,Acc,Wx,Wy,Wxd

Euclidean Distance

1

OA,OB,OAB,

SA,SB,SAB

34

35

36

37

38

EXCH

FBCL

FF1L

EXCH

FBCL

FF1L

FF1R

GOTO

INC

Wns,Wnd

Ws,Wnd

Expr

Swap Wns with Wnd

Find Bit Change from Left (MSb) Side

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to address

1

2

1

2

1

None

C

FF1R

GOTO

C

None

Wn

Go to indirect

None

39

40

41

INC

f

f = f + 1

C,DC,N,OV,Z

N,Z

INC

f,WREG

Ws,Wd

WREG = f + 1

INC

Wd = Ws + 1

INC2

IOR

INC2

IOR

f

f = f + 2

f,WREG

Ws,Wd

WREG = f + 2

Wd = Ws + 2

f

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

Wd = Wb .IOR. Ws

Wd = Wb .IOR. lit5

Load Accumulator

N,Z

IOR

N,Z

IOR

N,Z

IOR

N,Z

42

LAC

OA,OB,OAB,

SA,SB,SAB

43

44

LNK

LSR

LNK

LSR

MAC

#lit14

Link frame pointer

1

None

C,N,OV,Z

N,Z

f

f = Logical Right Shift f

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

N,Z

45

46

MAC

MOV

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate

,

AWB

OA,OB,OAB,

SA,SB,SAB

MAC

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate

1

OA,OB,OAB,

SA,SB,SAB

MOV

f,Wn

Move f to Wn

1

2

1

None

N,Z

MOV

f

Move f to f

MOV

f,WREG

Move f to WREG

N,Z

MOV

#lit16,Wn

#lit8,Wn

Wn,f

Move 16-bit literal to Wn

Move 8-bit literal to Wn

Move Wn to f

None

N,Z

MOV.b

MOV

Wso,Wdo

Move Ws to Wd

MOV

WREG,f

Move WREG to f

MOV.D

MOVSAC

Wns,Wd

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

Prefetch and store accumulator

None

Ws,Wnd

47

MOVSAC

Acc,Wx,Wxd,Wy,Wyd,AWB

DS70139E-page 138

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

48

MPY

Multiply Wm by Wn to Accumulator

Square Wm to Accumulator

1

OA,OB,OAB,

SA,SB,SAB

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

MPY

OA,OB,OAB,

SA,SB,SAB

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

49

50

MPY.N

MSC

MPY.N

-(Multiply Wm by Wn) to Accumulator

None

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

MSC

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator

OA,OB,OAB,

SA,SB,SAB

,

AWB

51

MUL

MUL.SS

MUL.SU

MUL.US

MUL.UU

Wb,Ws,Wnd

{Wnd+1, Wnd} = signed(Wb) * signed(Ws)

{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)

{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)

1

None

{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(Ws)

MUL.SU

MUL.UU

Wb,#lit5,Wnd

{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)

1

None

{Wnd+1, Wnd} = unsigned(Wb) *

unsigned(lit5)

MUL

NEG

f

W3:W2 = f * WREG

Negate Accumulator

1

None

52

NEG

Acc

OA,OB,OAB,

SA,SB,SAB

NEG

f

f = f + 1

1

2

C,DC,N,OV,Z

None

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

53

54

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from top-of-stack (TOS)

Pop from top-of-stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from top-of-stack (TOS) to

W(nd):W(nd+1)

None

POP.S

PUSH

Pop Shadow Registers

1

All

None

WDTO,Sleep

None

C,N,Z

N,Z

55

PUSH

f

Push f to top-of-stack (TOS)

Push Wso to top-of-stack (TOS)

Push W(ns):W(ns+1) to top-of-stack (TOS)

Push Shadow Registers

1

PUSH

Wso

Wns

1

PUSH.D

PUSH.S

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

2

1

56

57

PWRSAV

RCALL

#lit1

Expr

Go into Sleep or Idle mode

Relative Call

1

2

Wn

Computed Call

2

58

REPEAT

#lit14

Wn

Repeat Next Instruction lit14+1 times

Repeat Next Instruction (Wn)+1 times

Software device Reset

1

59

60

61

62

63

RESET

RETFIE

RETLW

RETURN

RLC

1

Return from interrupt

3 (2)

#lit10,Wn

Return with literal in Wn

3 (2)

Return from Subroutine

3 (2)

1

f

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

RLC

f,WREG

Ws,Wd

f

1

RLC

1

64

65

RLNC

RRC

RLNC

1

RLNC

f,WREG

Ws,Wd

f

1

N,Z

RLNC

1

N,Z

RRC

1

C,N,Z

RRC

f,WREG

Ws,Wd

1

RRC

1

DS70139E-page 139

dsPIC30F2011/2012/3012/3013

TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

66

RRNC

SAC

f

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Store Accumulator

1

N,Z

f,WREG

Ws,Wd

N,Z

67

SAC

Acc,#Slit4,Wdo

None

C,N,Z

None

SAC.R

SE

Acc,#Slit4,Wdo

Store Rounded Accumulator

Wnd = sign-extended Ws

f = 0xFFFF

68

69

SE

Ws,Wnd

f

SETM

SFTAC

WREG

Ws

WREG = 0xFFFF

Ws = 0xFFFF

70

71

SFTAC

SL

Acc,Wn

Arithmetic Shift Accumulator by (Wn)

OA,OB,OAB,

SA,SB,SAB

SFTAC

Acc,#Slit6

Arithmetic Shift Accumulator by Slit6

1

OA,OB,OAB,

SA,SB,SAB

SL

SUB

f

f = Left Shift f

1

C,N,OV,Z

N,Z

f,WREG

Ws,Wd

WREG = Left Shift f

Wd = Left Shift Ws

Wb,Wns,Wnd

Wb,#lit5,Wnd

Acc

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

Subtract Accumulators

N,Z

72

SUB

OA,OB,OAB,

SA,SB,SAB

SUB

f

f = f - WREG

1

2

1

C,DC,N,OV,Z

None

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f - WREG

Wn = Wn - lit10

SUB

Wd = Wb - Ws

SUB

Wd = Wb - lit5

73

SUBB

SUBR

SUBBR

SWAP.b

SWAP

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

f = f - WREG - (C)

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f - WREG - (C)

Wn = Wn - lit10 - (C)

Wd = Wb - Ws - (C)

Wd = Wb - lit5 - (C)

f = WREG - f

74

75

76

SUBR

SUBBR

SWAP

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = WREG - f

Wd = Ws - Wb

Wd = lit5 - Wb

f = WREG - f - (C)

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG -f - (C)

Wd = Ws - Wb - (C)

Wd = lit5 - Wb - (C)

Wn = nibble swap Wn

Wn = byte swap Wn

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink frame pointer

f = f .XOR. WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

Wd = Wb .XOR. lit5

Wnd = Zero-extend Ws

Wn

None

77

78

79

80

81

82

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

Ws,Wd

None

Ws,Wd

None

Ws,Wd

None

Ws,Wd

None

XOR

f

N,Z

XOR

f,WREG

N,Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N,Z

XOR

N,Z

XOR

N,Z

83

ZE

C,Z,N

DS70139E-page 140

dsPIC30F2011/2012/3012/3013

19.1 MPLAB Integrated Development

Environment Software

19.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS70139E-page 141

dsPIC30F2011/2012/3012/3013

19.2 MPASM Assembler

19.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

19.6 MPLAB SIM Software Simulator

19.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

19.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS70139E-page 142

dsPIC30F2011/2012/3012/3013

19.7 MPLAB ICE 2000

High-Performance

19.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers. Software control of the MPLAB ICE 2000

In-Circuit Emulator is advanced by the MPLAB Inte-

grated Development Environment, which allows edit-

ing, building, downloading and source debugging from

a single environment.

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

19.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

19.8 MPLAB ICE 4000

High-Performance

In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PIC MCUs and dsPIC DSCs. Software control of the

MPLAB ICE 4000 In-Circuit Emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

DS70139E-page 143

dsPIC30F2011/2012/3012/3013

19.11 PICSTART Plus Development

Programmer

19.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

19.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC18F families of Flash memory microcontrollers.

The PICkit 2 Starter Kit includes a prototyping develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC™ Lite C compiler, and is designed to

help get up to speed quickly using PIC^®micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS70139E-page 144

dsPIC30F2011/2012/3012/3013

20.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future

revisions of this document as it becomes available.

For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”

(DS70046).

Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for

extended periods may affect device reliability. Functional operation of the device at these or any other conditions above

the parameters indicated in the operation listings of this specification is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1).................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V

Voltage on MCLR with respect to VSS........................................................................................................ 0V to +13.25V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 2)................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 2)....................................................................................................200 mA

Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

2: Maximum allowable current is a function of device maximum power dissipation. See Table 20-2 for PDMAX.

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific

devices, please refer to the Family Cross Reference Table.

20.1 DC Characteristics

TABLE 20-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

VDD Range

Temp Range

dsPIC30FXXX-30I

dsPIC30FXXX-20E

4.5-5.5V

3.0-3.6V

2.5-3.0V

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

30

—

20

—

10

—

20

—

15

—

DS70139E-page 145

dsPIC30F2011/2012/3012/3013

TABLE 20-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

dsPIC30F201x-30I

dsPIC30F301x-30I

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

+125

+85

°C

dsPIC30F201x-20E

dsPIC30F301x-20E

Operating Junction Temperature Range

Operating Ambient Temperature Range

Power Dissipation:

TJ

TA

-40

+150

+125

°C

Internal chip power dissipation:

P^INT= V^DD× (I^DD– ∑

)

IOH

PD

PINT + PI/O

W

I/O Pin power dissipation:

=

({ _{VDD – VOH}} × _IOH) + _∑

(

)

V^OL× I^OL

P^I/O

∑

Maximum Allowed Power Dissipation

PDMAX

(TJ - TA) / θJA

W

TABLE 20-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 18-pin PDIP (P)

Package Thermal Resistance, 18-pin SOIC (SO)

Package Thermal Resistance, 28-pin SPDIP (SP)

Package Thermal Resistance, 28-pin (SOIC)

Package Thermal Resistance, 44-pin QFN

θ^JA

θJA

θ^JA

θJA

44

57

42

49

28

—

°C/W

1

Note 1: Junction to ambient thermal resistance, Theta-ja (θ^JA) numbers are achieved by package simulations.

TABLE 20-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

Operating Voltage⁽²⁾

DC10

DC11

DC12

DC16

VDD

VDR

VPOR

Supply Voltage

2.5

3.0

—

5.5

—

V

Industrial temperature

Extended temperature

Supply Voltage

RAM Data Retention Voltage⁽³⁾

1.5

VSS

VDD Start Voltage (to ensure

—

internal Power-on Reset signal)

DC17

SVDD

VDD Rise Rate (to ensure

internal Power-on Reset signal)

0.05

V/ms 0-5V in 0.1 sec

0-3V in 60 ms

Note 1: “Typ” column data is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: This is the limit to which VDD can be lowered without losing RAM data.

DS70139E-page 146

dsPIC30F2011/2012/3012/3013

TABLE 20-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC31a

DC31b

DC31c

DC31e

DC31f

DC31g

DC30a

DC30b

DC30c

DC30e

DC30f

DC30g

DC23a

DC23b

DC23c

DC23e

DC23f

DC23g

DC24a

DC24b

DC24c

DC24e

DC24f

DC24g

DC27a

DC27b

DC27d

DC27e

DC27f

DC29a

DC29b

1.6

3.0

mA

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

25°C

85°C

125°C

25°C

85°C

3.3V

5V

1.6

3.0

0.128 MIPS

LPRC ( 512 kHz)

3.6

6.0

3.3

6.0

3.2

6.0

3.0

5.0

3.0

5.0

3.3V

5V

3.1

5.0

(1.8 MIPS)

FRC (7.37 MHz)

6.0

9.0

5.8

9.0

5.7

9.0

15.0

24.0

33.0

56.0

60.0

90.0

140.0

10.0

16.0

22.0

37.0

41.0

40.0

68.0

67.0

66.0

96.0

94.0

3.3V

5V

4 MIPS

3.3V

10 MIPS

5V

3.3V

5V

20 MIPS

30 MIPS

5V

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.

MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data

Memory are operational. No peripheral modules are operating.

DS70139E-page 147

dsPIC30F2011/2012/3012/3013

TABLE 20-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC51a

DC51b

DC51c

DC51e

DC51f

DC51g

DC50a

DC50b

DC50c

DC50e

DC50f

DC50g

DC43a

DC43b

DC43c

DC43e

DC43f

DC43g

DC44a

DC44b

DC44c

DC44e

DC44f

DC44g

DC47a

DC47b

DC47d

DC47e

DC47f

DC49a

DC49b

1.3

2.5

mA

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

25°C

85°C

125°C

25°C

85°C

3.3V

5V

1.2

2.5

0.128 MIPS

LPRC ( 512 kHz)

3.2

5.0

2.9

5.0

2.8

5.0

3.0

5.0

3.0

5.0

3.3V

5V

3.0

5.0

(1.8 MIPS)

FRC (7.37 MHz)

6.0

9.0

5.8

9.0

5.7

9.0

5.2

8.0

5.3

8.0

3.3V

5V

5.4

8.0

4 MIPS

9.7

15.0

17.0

29.0

30.0

35.0

50.0

70.0

9.6

9.5

11.0

19.0

20.0

21.0

35.0

36.0

51.0

3.3V

10 MIPS

5V

3.3V

5V

20 MIPS

30 MIPS

5V

Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IIDLE current is measured with Core off, Clock on and all modules turned off.

DS70139E-page 148

dsPIC30F2011/2012/3012/3013

TABLE 20-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Power-Down Current (IPD)⁽²⁾

DC60a

DC60b

DC60c

DC60e

DC60f

DC60g

DC61a

DC61b

DC61c

DC61e

DC61f

DC61g

DC62a

DC62b

DC62c

DC62e

DC62f

DC62g

DC63a

DC63b

DC63c

DC63e

DC63f

DC63g

DC66a

DC66b

DC66c

DC66e

DC66f

DC66g

0.3

1.3

—

μA

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

25°C

85°C

125°C

30.0

60.0

—

3.3V

5V

16.0

0.5

Base Power-Down Current⁽³⁾

3.7

45.0

90.0

9.0

25.0

6.0

9.0

3.3V

5V

6.0

9.0

(3)

Watchdog Timer Current: ΔIWDT

13.0

12.0

4.0

20.0

10.0

15.0

53.0

62.0

40.0

44.0

5.0

3.3V

5V

4.0

Timer1 w/32 kHz Crystal: ΔITI32⁽³⁾

4.0

6.0

5.0

33.0

35.0

19.0

38.0

41.0

21.0

26.0

27.0

25.0

27.0

29.0

3.3V

5V

(3)

BOR On: ΔIBOR

3.3V

5V

(3)

Low-Voltage Detect: ΔILVD

Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. LVD, BOR, WDT, etc. are all switched off.

3: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

DS70139E-page 149

dsPIC30F2011/2012/3012/3013

TABLE 20-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Input Low Voltage⁽²⁾

VIL

DI10

I/O pins:

with Schmitt Trigger buffer

VSS

—

0.2 VDD

0.3 VDD

0.2 VDD

V

DI15

DI16

DI17

DI18

DI19

MCLR

OSC1 (in XT, HS and LP modes)

OSC1 (in RC mode)⁽³⁾

SDA, SCL

SM bus disabled

SM bus enabled

SDA, SCL

VIH

Input High Voltage⁽²⁾

DI20

I/O pins:

with Schmitt Trigger buffer

0.8 VDD

—

VDD

V

DI25

DI26

DI27

DI28

DI29

MCLR

OSC1 (in XT, HS and LP modes) 0.7 VDD

OSC1 (in RC mode)⁽³⁾

0.9 VDD

0.7 VDD

0.8 VDD

SDA, SCL

SM bus disabled

SM bus enabled

SDA, SCL

ICNPU

IIL

CNXX Pull-up Current⁽²⁾

DI30

50

250

400

μA VDD = 5V, VPIN = VSS

Input Leakage Current^(2)(4)(5)

DI50

DI51

I/O ports

—

0.01

0.50

±1

—

μA VSS ≤ VPIN ≤ VDD,

Pin at high impedance

Analog input pins

μA VSS ≤ VPIN ≤ VDD,

Pin at high impedance

DI55

DI56

MCLR

OSC1

—

0.05

±5

μA

VSS ≤ VPIN ≤ VDD

μA VSS ≤ VPIN ≤ VDD, XT, HS

and LP Osc mode

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that

the dsPIC30F device be driven with an external clock while in RC mode.

4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

5: Negative current is defined as current sourced by the pin.

DS70139E-page 150

dsPIC30F2011/2012/3012/3013

TABLE 20-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

VOL

Output Low Voltage⁽²⁾

DO10

DO16

I/O ports

—

0.6

TBD

0.6

V

IOL = 8.5 mA, VDD = 5V

IOL = 2.0 mA, VDD = 3V

IOL = 1.6 mA, VDD = 5V

IOL = 2.0 mA, VDD = 3V

OSC2/CLKO

(RC or EC Osc mode)

Output High Voltage⁽²⁾

I/O ports

TBD

VOH

DO20

DO26

VDD – 0.7

TBD

—

V

IOH = -3.0 mA, VDD = 5V

IOH = -2.0 mA, VDD = 3V

IOH = -1.3 mA, VDD = 5V

IOH = -2.0 mA, VDD = 3V

OSC2/CLKO

VDD – 0.7

TBD

(RC or EC Osc mode)

Capacitive Loading Specs

on Output Pins⁽²⁾

DO50 COSC2

OSC2/SOSC2 pin

—

15

pF In XTL, XT, HS and LP modes

when external clock is used to

drive OSC1.

DO56 CIO

DO58 CB

All I/O pins and OSC2

SCL, SDA

—

50

pF RC or EC Osc mode

pF In I²C mode

400

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

DS70139E-page 151

dsPIC30F2011/2012/3012/3013

FIGURE 20-1:

LOW-VOLTAGE DETECT CHARACTERISTICS

VDD

LV10

LVDIF

(LVDIF set by hardware)

TABLE 20-10: ELECTRICAL CHARACTERISTICS: LVDL

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max Units Conditions

LV10

VPLVD

LVDL Voltage on VDD transition LVDL = 0000⁽²⁾

—

V

high-to-low

LVDL = 0001⁽²⁾

LVDL = 0010⁽²⁾

LVDL = 0011⁽²⁾

LVDL = 0100

LVDL = 0101

LVDL = 0110

LVDL = 0111

LVDL = 1000

LVDL = 1001

LVDL = 1010

LVDL = 1011

LVDL = 1100

LVDL = 1101

LVDL = 1110

—

V

—

2.50

2.70

2.80

3.00

3.30

3.50

3.60

3.80

4.00

4.20

4.50

—

2.65

2.86

2.97

3.18

3.50

3.71

3.82

4.03

4.24

4.45

4.77

—

LV15

VLVDIN

External LVD input pin

threshold voltage

LVDL = 1111

Note 1: These parameters are characterized but not tested in manufacturing.

2: These values not in usable operating range.

DS70139E-page 152

dsPIC30F2011/2012/3012/3013

FIGURE 20-2:

BROWN-OUT RESET CHARACTERISTICS

VDD

(Device not in Brown-out Reset)

BO15

BO10

(Device in Brown-out Reset)

RESET (due to BOR)

Power-Up Time-out

TABLE 20-11: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min Typ⁽¹⁾Max Units

Conditions

BO10

VBOR

BOR Voltage⁽²⁾on

VDD transition high to

low

BORV = 11⁽³⁾

—

V

Not in operating

range

BORV = 10

BORV = 01

BORV = 00

2.6

4.1

4.58

—

5

2.71

4.4

V

4.73

—

V

BO15

VBHYS

mV

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: 11values not in usable operating range.

DS70139E-page 153

dsPIC30F2011/2012/3012/3013

TABLE 20-12: DC CHARACTERISTICS: PROGRAM AND EEPROM

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min Typ⁽¹⁾

Max

Units

Conditions

Data EEPROM Memory⁽²⁾

Byte Endurance

D120

D121

ED

100K

VMIN

1M

—

E/W -40°C ≤ TA ≤ +85°C

VDRW

VDD for Read/Write

5.5

V

Using EECON to Read/Write

VMIN = Minimum operating

voltage

D122

D123

TDEW

Erase/Write Cycle Time

Characteristic Retention

—

2

—

ms

TRETD

40

100

Year Provided no other specifications

are violated

D124

IDEW

IDD During Programming

Program Flash Memory⁽²⁾

Cell Endurance

—

10

30

mA Row Erase

D130

D131

EP

10K

100K

—

E/W -40°C ≤ TA ≤ +85°C

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

D133

D134

D135

VEB

VDD for Bulk Erase

4.5

3.0

—

5.5

—

V

VPEW

TPEW

TRETD

VDD for Erase/Write

Erase/Write Cycle Time

Characteristic Retention

2

ms

40

100

—

Year Provided no other specifications

are violated

D136

D137

D138

TEB

IPEW

IEB

ICSP™ Block Erase Time

IDD During Programming

—

4

—

30

ms

10

mA Row Erase

mA Bulk Erase

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

2: These parameters are characterized but not tested in manufacturing.

DS70139E-page 154

dsPIC30F2011/2012/3012/3013

20.2 AC Characteristics and Timing Parameters

The information contained in this section defines dsPIC30F AC characteristics and timing parameters.

TABLE 20-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Operating voltage VDD range as described in Section 20.0 “Electrical

Characteristics”.

FIGURE 20-3:

Load Condition 1 — for all pins except OSC2

VDD/2

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 2 — for OSC2

CL

RL

VSS

CL

Legend:

RL = 464 Ω

CL = 50 pF for all pins except OSC2

VSS

5 pF for OSC2 output

FIGURE 20-4:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1

CLKO

OS20

OS30 OS30

OS25

OS31 OS31

OS40

OS41

DS70139E-page 155

dsPIC30F2011/2012/3012/3013

TABLE 20-14: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10 FOSC

External CLKN Frequency⁽²⁾

(External clocks allowed only

in EC mode)

DC

4

—

40

10

7.5

MHz

EC

EC with 4x PLL

EC with 8x PLL

EC with 16x PLL

4

Oscillator Frequency⁽²⁾

DC

0.4

4

—

4

MHz

kHz

RC

XTL

XT

10

7.5

25

20

15

25

22.5

33

—

XT with 4x PLL

XT with 8x PLL

XT with 16x PLL

HS

HS/2 with 4x PLL

HS/2 with 8x PLL

HS/2 with 16x PLL

HS/3 with 4x PLL

HS/3 with 8x PLL

HS/3 with 16x PLL

LP

4

10

12

31

—

7.37

512

MHz

kHz

FRC internal

—

FRC internal w/4x PLL

FRC internal w/8x PLL

FRC internal w/16x PLL

LPRC internal

OS20 TOSC

OS25 TCY

TOSC = 1/FOSC

—

See parameter OS10

for FOSC value

Instruction Cycle Time⁽²⁾⁽³⁾

External Clock⁽²⁾in (OSC1)

High or Low Time

33

—

DC

—

ns

See Table 20-17

EC

OS30 TosL,

TosH

.45 x

TOSC

OS31 TosR,

TosF

External Clock⁽²⁾in (OSC1)

Rise or Fall Time

—

20

ns

EC

OS40 TckR

OS41 TckF

CLKO Rise Time⁽²⁾⁽⁴⁾

CLKO Fall Time⁽²⁾⁽⁴⁾

—

ns

See parameter DO31

See parameter DO32

Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: These parameters are characterized but not tested in manufacturing.

3: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“Max.” cycle time limit is “DC” (no clock) for all devices.

4: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is

low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

DS70139E-page 156

dsPIC30F2011/2012/3012/3013

TABLE 20-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OS50

FPLLI

PLL Input Frequency Range⁽²⁾

4

—

10

MHz EC with 4x PLL

MHz EC with 8x PLL

MHz EC with 16x PLL

MHz XT with 4x PLL

MHz XT with 8x PLL

MHz XT with 16x PLL

MHz HS/2 with 4x PLL

MHz HS/2 with 8x PLL

MHz HS/2 with 16x PLL

7.5⁽⁴⁾

10

4

7.5⁽⁴⁾

10

5⁽³⁾

4

10

7.5⁽⁴⁾

8.33⁽³⁾MHz HS/3 with 4x PLL

8.33⁽³⁾MHz HS/3 with 8x PLL

4

7.5⁽⁴⁾

120

MHz HS/3 with 16x PLL

OS51

OS52

FSYS

TLOC

On-Chip PLL Output⁽²⁾

16

—

MHz EC, XT, HS/2, HS/3

modes with PLL

PLL Start-up Time (Lock Time)

—

20

50

μs

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Limited by oscillator frequency range.

4: Limited by device operating frequency range.

TABLE 20-16: PLL JITTER

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature

AC CHARACTERISTICS

-40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

-40°C ≤ TA ≤ +85°C

OS61

x4 PLL

—

0.251 0.413

%

VDD = 3.0 to 3.6V

VDD = 4.5 to 5.5V

VDD = 3.0 to 3.6V

VDD = 4.5 to 5.5V

VDD = 3.0 to 3.6V

VDD = 4.5 to 5.5V

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

0.256

0.47

x8 PLL

0.355 0.584

0.362 0.664

x16 PLL

0.67

0.92

0.632 0.956

Note 1: These parameters are characterized but not tested in manufacturing.

DS70139E-page 157

dsPIC30F2011/2012/3012/3013

TABLE 20-17: INTERNAL CLOCK TIMING EXAMPLES

Clock

FOSC

MIPS⁽³⁾

w PLL x4

MIPS⁽³⁾

w PLL x8

MIPS⁽³⁾

w PLL x16

Oscillator

Mode

TCY (μsec)⁽²⁾

(MHz)⁽¹⁾

w/o PLL

EC

XT

0.200

4

20.0

1.0

0.05

1.0

—

4.0

10.0

—

8.0

20.0

—

16.0

—

10

25

4

0.4

2.5

0.16

1.0

6.25

1.0

—

4.0

10.0

8.0

20.0

16.0

—

10

0.4

2.5

Note 1: Assumption: Oscillator Postscaler is divide by 1.

2: Instruction Execution Cycle Time: TCY = 1/MIPS.

3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction

cycle].

DS70139E-page 158

dsPIC30F2011/2012/3012/3013

TABLE 20-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY⁽²⁾

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Jitter @ FRC Freq. = 7.37 MHz⁽¹⁾

OS62

FRC

—

+0.04 +0.16

+0.07 +0.23

+0.31 +0.62

+0.34 +0.77

+0.44 +0.87

+0.48 +1.08

+0.71 +1.23

%

-40°C ≤ TA ≤ +85°C

VDD = 3.0-3.6V

VDD = 4.5-5.5V

VDD = 3.0-3.6V

VDD = 4.5-5.5V

VDD = 3.0-3.6V

VDD = 4.5-5.5V

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

FRC with 4x PLL

FRC with 8x PLL

FRC with 16x PLL

Internal FRC Accuracy @ FRC Freq. = 7.37 MHz⁽¹⁾

FRC +1.50

Internal FRC Drift @ FRC Freq. = 7.37 MHz⁽¹⁾

OS63

OS64

—

%

-40°C ≤ TA ≤ +125°C

VDD = 3.0-5.5V

-0.7

—

0.5

0.7

0.5

0.7

%

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

VDD = 3.0-3.6V

VDD = 4.5-5.5V

Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to

compensate for temperature drift.

2: Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift

percentages.

TABLE 20-19: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

LPRC @ Freq. = 512 kHz⁽¹⁾

OS65

-35

—

+35

%

—

Note 1: Change of LPRC frequency as VDD changes.

DS70139E-page 159

dsPIC30F2011/2012/3012/3013

FIGURE 20-5:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-20: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic^(1)(2)(3)

Min

Typ⁽⁴⁾

Max

Units

Conditions

DO31

DO32

DI35

TIOR

TIOF

TINP

TRBP

Port output rise time

—

7

20

—

ns

—

Port output fall time

INTx pin high or low time (output)

CNx high or low time (input)

20

—

DI40

2 TCY

Note 1: These parameters are asynchronous events not related to any internal clock edges

2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.

3: These parameters are characterized but not tested in manufacturing.

4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70139E-page 160

dsPIC30F2011/2012/3012/3013

FIGURE 20-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

SY12

MCLR

SY10

Internal

POR

SY11

PWRT

Time-out

SY30

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

SY20

SY13

I/O Pins

SY35

FSCM

Delay

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max Units

Conditions

SY10

SY11

TmcL

MCLR Pulse Width (low)

Power-up Timer Period

2

—

μs

ms

-40°C to +85°C

TPWRT

3

4

6

-40°C to +85°C

12

50

16

64

22

90

User programmable

SY12

SY13

TPOR

TIOZ

Power On Reset Delay

3

10

30

μs

-40°C to +85°C

I/O high impedance from MCLR

Low or Watchdog Timer Reset

—

0.8

1.0

SY20

TWDT1

WatchdogTimerTime-outPeriod

(No Prescaler)

1.4

2.1

2.8

ms

VDD = 5V, -40°C to +85°C

TWDT2

TBOR

TOST

1.4

100

—

2.1

—

2.8

—

ms

μs

—

VDD = 3V, -40°C to +85°C

VDD ≤ VBOR (D034)

TOSC = OSC1 period

-40°C to +85°C

SY25

SY30

SY35

Brown-out Reset Pulse Width⁽³⁾

Oscillation Start-up Timer Period

Fail-Safe Clock Monitor Delay

1024 TOSC

500

—

TFSCM

—

900

μs

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Refer to Figure 20-2 and Table 20-11 for BOR.

DS70139E-page 161

dsPIC30F2011/2012/3012/3013

FIGURE 20-7:

BAND GAP START-UP TIME CHARACTERISTICS

VBGAP

0V

Enable Band Gap

(see Note)

Band Gap

Stable

SY40

Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.

TABLE 20-22: BAND GAP START-UP TIME REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic⁽¹⁾

Band Gap Start-up Time

Min Typ⁽²⁾Max Units

Conditions

SY40

TBGAP

—

40 65

µs Defined as the time between the

instant that the band gap is enabled

and the moment that the band gap

reference voltage is stable.

RCON<13> bit

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

DS70139E-page 162

dsPIC30F2011/2012/3012/3013

FIGURE 20-8:

TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx11

Tx10

Tx15

OS60

Tx20

TMRX

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TTXH

Characteristic

Synchronous,

Min

Typ

Max Units

Conditions

TA10

TxCK High Time

0.5 TCY + 20

—

ns

Must also meet

parameter TA15

no prescaler

Synchronous,

with prescaler

10

—

Asynchronous

10

—

ns

TA11

TA15

TTXL

TTXP

TxCK Low Time

Synchronous,

no prescaler

0.5 TCY + 20

Must also meet

parameter TA15

Synchronous,

with prescaler

10

—

ns

Asynchronous

10

—

ns

TxCK Input Period Synchronous,

no prescaler

TCY + 10

Synchronous,

with prescaler

Greater of:

20 ns or

—

N = prescale

value

(TCY + 40)/N

(1, 8, 64, 256)

Asynchronous

20

—

ns

OS60

Ft1

SOSC1/T1CK oscillator input

DC

50

kHz

frequency range (oscillator enabled

by setting bit TCS (T1CON, bit 1))

TA20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

—

1.5 TCY

—

Note:

Timer1 is a Type A.

DS70139E-page 163

dsPIC30F2011/2012/3012/3013

TABLE 20-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TtxH

Characteristic

Min

Typ

Max

Units

Conditions

TB10

TxCK High Time Synchronous, 0.5 TCY + 20

no prescaler

—

ns

Must also meet

parameter TB15

Synchronous,

with prescaler

10

—

ns

TB11

TB15

TtxL

TtxP

TxCK Low Time

Synchronous, 0.5 TCY + 20

no prescaler

Must also meet

parameter TB15

Synchronous,

with prescaler

10

TxCK Input Period Synchronous,

no prescaler

TCY + 10

N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TB20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

—

1.5 TCY

—

Note:

Timer2 and Timer4 are Type B.

TABLE 20-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TtxH

Characteristic

Min

Typ

Max Units

Conditions

TC10

TxCK High Time

TxCK Low Time

Synchronous

0.5 TCY + 20

—

ns

Must also meet

parameter TC15

TC11

TC15

TtxL

TtxP

0.5 TCY + 20

TCY + 10

—

Must also meet

parameter TC15

TxCK Input Period Synchronous,

no prescaler

N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TC20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

—

1.5

TCY

—

Note:

Timer3 and Timer5 are Type C.

DS70139E-page 164

dsPIC30F2011/2012/3012/3013

FIGURE 20-9:

INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICX

IC10

IC11

IC15

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-26: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Max

Units

Conditions

IC10

IC11

IC15

TccL

TccH

TccP

ICx Input Low Time No Prescaler

With Prescaler

0.5 TCY + 20

10

—

ns

ICx Input High Time No Prescaler

With Prescaler

0.5 TCY + 20

10

ICx Input Period

(2 TCY + 40)/N

N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

DS70139E-page 165

dsPIC30F2011/2012/3012/3013

FIGURE 20-10:

OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx

(Output Compare

or PWM Mode)

OC10

OC11

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OC10 TccF

OC11 TccR

OCx Output Fall Time

OCx Output Rise Time

—

ns

See Parameter DO32

See Parameter DO31

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70139E-page 166

dsPIC30F2011/2012/3012/3013

FIGURE 20-11:

OCFA/OCFB

OCx

OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OC15

TABLE 20-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

No.

Symbol

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OC15

OC20

OC15 TFD

Fault Input to PWM I/O

Change

—

50

ns

—

OC20 TFLT

Fault Input Pulse Width

50

—

ns

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70139E-page 167

dsPIC30F2011/2012/3012/3013

FIGURE 20-12:

SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx

(CKP = 0)

SP11

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP31

SP21

LSb

SP20

BIT 14 - - - - - -1

MSb

SDOx

SDIx

SP30

MSb IN

SP40

LSb IN

BIT 14 - - - -1

SP41

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-29: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP10

SP11

SP20

TscL

TscH

TscF

SCKX Output Low Time⁽³⁾

SCKX Output High Time⁽³⁾

SCKX Output Fall Time⁽⁴

TCY/2

—

ns

—

See parameter

DO32

SP21

SP30

SP31

SP35

SP40

SP41

TscR

TdoF

TdoR

SCKX Output Rise Time⁽⁴⁾

—

20

—

30

—

ns

See parameter

DO31

SDOX Data Output Fall Time⁽⁴⁾

SDOX Data Output Rise Time⁽⁴⁾

See parameter

DO32

See parameter

DO31

TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge

—

TdiV2scH, Setup Time of SDIX Data Input

TdiV2scL

TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge

Note 1: These parameters are characterized but not tested in manufacturing.

to SCKX Edge

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

DS70139E-page 168

dsPIC30F2011/2012/3012/3013

FIGURE 20-13:

SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS

SP36

SCKX

(CKP = 0)

SP11

SP10

SP21

SP20

SP21

SCKX

(CKP = 1)

SP35

SP20

LSb

MSb

SP40

BIT 14 - - - - - -1

SDOX

SDIX

SP30,SP31

BIT 14 - - - -1

MSb IN

SP41

LSb IN

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-30: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscL

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP10

SP11

SP20

SCKX output low time⁽³⁾

SCKX output high time⁽³⁾

SCKX output fall time⁽⁴⁾

TCY/2

—

ns

—

TscH

TscF

See parameter

DO32

SP21

SP30

SP31

SP35

SP36

SP40

SP41

TscR

TdoF

TdoR

SCKX output rise time⁽⁴⁾

—

30

20

—

30

—

ns

See parameter

DO31

SDOX data output fall time⁽⁴⁾

SDOX data output rise time⁽⁴⁾

See parameter

DO32

See parameter

DO31

TscH2doV, SDOX data output valid after

TscL2doV SCKX edge

—

TdoV2sc, SDOX data output setup to

TdoV2scL first SCKX edge

TdiV2scH, Setup time of SDIX data input

TdiV2scL to SCKX edge

TscH2diL, Hold time of SDIX data input

TscL2diL

to SCKX edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

DS70139E-page 169

dsPIC30F2011/2012/3012/3013

FIGURE 20-14:

SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP52

SP50

SCK

(CKP =

X

0

)

SP71

SP70

SP72

SP73

SCK

(CKP =

X

1

SP73

LSb

SP72

SP35

MSb

BIT 14 - - - - - -1

SDOX

SP51

SP30,SP31

BIT 14 - - - -1

SDIX

MSb IN

SP41

LSb IN

SP40

Note: Refer to Figure 20-3 for load conditions.

TABLE 20-31: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C

≤

T

TA

A

≤

+85°C for Industrial

+125°C for Extended

-40°C

Param

No.

Symbol

TscL

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP70

SP71

SP72

SP73

SP30

SP31

SP35

SCKX Input Low Time

30

—

10

—

25

—

30

ns

—

TscH

TscF

TscR

TdoF

TdoR

SCKX Input High Time

—

SCKX Input Fall Time⁽³⁾

SCKX Input Rise Time⁽³⁾

SDOX Data Output Fall Time⁽³⁾

SDOX Data Output Rise Time⁽³⁾

—

See DO32

See DO31

—

TscH2doV,

TscL2doV

SDOX Data Output Valid after

SCKX Edge

SP40

SP41

SP50

SP51

SP52

TdiV2scH,

TdiV2scL

Setup Time of SDIX Data Input

to SCKX Edge

20

—

50

—

ns

—

TscH2diL,

TscL2diL

Hold Time of SDIX Data Input

to SCKX Edge

TssL2scH,

TssL2scL

SSX↓ to SCKX↑ or SCKX↓ Input

120

10

TssH2doZ

SSX↑ to SDOX Output

high impedance⁽³⁾

TscH2ssH SSX after SCK Edge

TscL2ssH

1.5 TCY

+40

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Assumes 50 pF load on all SPI pins.

DS70139E-page 170

dsPIC30F2011/2012/3012/3013

FIGURE 20-15:

SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60

SSX

SP52

SP50

SCKX

(CKP = 0)

SP71

SP70

SP72

SP73

SCKX

(CKP = 1)

SP35

SP72

LSb

SP52

BIT 14 - - - - - -1

MSb

SDOX

SDIX

SP30,SP31

BIT 14 - - - -1

SP51

MSb IN

SP41

LSb IN

SP40

Note: Refer to Figure 20-3 for load conditions.

DS70139E-page 171

dsPIC30F2011/2012/3012/3013

TABLE 20-32: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscL

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP70

SP71

SP72

SP73

SP30

SCKX Input Low Time

30

—

10

—

25

—

ns

—

TscH

TscF

TscR

TdoF

SCKX Input High Time

SCKX Input Fall Time⁽³⁾

SCKX Input Rise Time⁽³⁾

SDOX Data Output Fall Time⁽³⁾

Seeparameter

DO32

SP31

SP35

SP40

SP41

SP50

SP51

SP52

SP60

TdoR

SDOX Data Output Rise Time⁽³⁾

—

30

—

50

—

50

ns

Seeparameter

DO31

TscH2doV, SDOX Data Output Valid after

TscL2doV SCKX Edge

—

TdiV2scH, Setup Time of SDIX Data Input

20

TdiV2scL

TscH2diL, Hold Time of SDIX Data Input

TscL2diL to SCKX Edge

to SCKX Edge

20

TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input

TssL2scL

120

TssH2doZ SS↑ to SDOX Output

10

1.5 TCY + 40

—

high impedance⁽⁴⁾

TscH2ssH SSX↑ after SCKX Edge

TscL2ssH

TssL2doV SDOX Data Output Valid after

SCKX Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI pins.

DS70139E-page 172

dsPIC30F2011/2012/3012/3013

FIGURE 20-16:

I²C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCL

SDA

IM31

IM34

IM30

IM33

Stop

Condition

Start

Condition

Note: Refer to Figure 20-3 for load conditions.

FIGURE 20-17:

I²C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20

IM21

IM11

IM10

SCL

IM11

IM26

IM10

IM33

IM25

SDA

In

IM45

IM40

SDA

Out

Note: Refer to Figure 20-3 for load conditions.

DS70139E-page 173

dsPIC30F2011/2012/3012/3013

I

TABLE 20-33: I²C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min⁽¹⁾

Max

Units

Conditions

IM10

IM11

IM20

IM21

IM25

IM26

IM30

IM31

IM33

IM34

IM40

IM45

IM50

TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)

400 kHz mode TCY/2 (BRG + 1)

—

μs

ns

μs

ns

μs

ns

μs

pF

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)

—

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TF:SCL

TR:SCL

SDA and SCL

Fall Time

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

—

300

100

1000

300

—

CB is specified to be

from 10 to 400 pF

20 + 0.1 CB

—

SDA and SCL

Rise Time

—

CB is specified to be

from 10 to 400 pF

20 + 0.1 CB

—

250

100

TBD

0

TSU:DAT Data Input

Setup Time

—

THD:DAT Data Input

Hold Time

—

0

0.9

—

TBD

TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)

—

Only relevant for

Repeated Start

condition

Setup Time

400 kHz mode TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)

—

After this period the

first clock pulse is

generated

Hold Time

400 kHz mode TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)

—

Setup Time

400 kHz mode TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STO Stop Condition

Hold Time

100 kHz mode TCY/2 (BRG + 1)

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TAA:SCL Output Valid

From Clock

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

—

3500

1000

—

TBF:SDA Bus Free Time 100 kHz mode

4.7

1.3

TBD

—

Time the bus must be

free before a new

transmission can start

400 kHz mode

1 MHz mode⁽²⁾

—

CB

Bus Capacitive Loading

400

Note 1: BRG is the value of the I²C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ (I²C)”

in the “dsPIC30F Family Reference Manual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I²C™ pins (for 1 MHz mode only).

DS70139E-page 174

dsPIC30F2011/2012/3012/3013

FIGURE 20-18:

I²C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCL

SDA

IS34

IS31

IS30

IS33

Stop

Condition

Start

Condition

FIGURE 20-19:

I²C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20

IS21

IS11

IS10

SCL

IS30

IS26

IS31

IS33

IS25

SDA

In

IS45

IS40

SDA

Out

2

TABLE 20-34: I C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

No.

Symbol

Characteristic

Min

Max Units

Conditions

IS10

TLO:SCL Clock Low Time 100 kHz mode

400 kHz mode

4.7

—

μs

Device must operate at a

minimum of 1.5 MHz

1.3

Device must operate at a

minimum of 10 MHz.

1 MHz mode⁽¹⁾

0.5

4.0

—

μs

—

IS11

THI:SCL

Clock High Time 100 kHz mode

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

μs

Device must operate at a

minimum of 10 MHz

1 MHz mode⁽¹⁾

0.5

—

300

100

1000

300

μs

ns

—

IS20

IS21

TF:SCL

TR:SCL

SDA and SCL

Fall Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

—

SDA and SCL

Rise Time

—

20 + 0.1 CB

—

CB is specified to be from

10 to 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I²C™ pins (for 1 MHz mode only).

DS70139E-page 175

dsPIC30F2011/2012/3012/3013

2

TABLE 20-34: I C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Max Units

Conditions

IS25

TSU:DAT Data Input

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

250

100

0

—

0.9

0.3

—

ns

μs

ns

μs

pF

—

Setup Time

IS26

IS30

IS31

IS33

IS34

IS40

IS45

IS50

THD:DAT Data Input

Hold Time

—

0

TSU:STA Start Condition

Setup Time

4.7

0.6

0.25

4.0

0.6

0.25

4.7

0.6

4000

600

250

0

Only relevant for Repeated

Start condition

THD:STA Start Condition

Hold Time

After this period the first

clock pulse is generated

TSU:STO Stop Condition

Setup Time

—

THD:STO Stop Condition

Hold Time

TAA:SCL

Output Valid

From Clock

3500

1000

350

—

0

TBF:SDA Bus Free Time

4.7

1.3

0.5

—

Time the bus must be free

before a new transmission

can start

—

CB

Bus Capacitive

Loading

400

—

Note 1: Maximum pin capacitance = 10 pF for all I²C™ pins (for 1 MHz mode only).

DS70139E-page 176

dsPIC30F2011/2012/3012/3013

FIGURE 20-20:

CAN MODULE I/O TIMING CHARACTERISTICS

CXTX Pin

(output)

New Value

Old Value

CA10 CA11

CA20

CXRX Pin

(input)

TABLE 20-35: CAN MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

TioF

TioR

Tcwf

CA10

CA11

CA20

Port Output Fall Time

Port Output Rise Time

—

10

—

25

—

ns

—

Pulse Width to Trigger

CAN Wake-up Filter

500

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70139E-page 177

dsPIC30F2011/2012/3012/3013

TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

AD02 AVSS

Module VDD Supply

Module VSS Supply

Greater of

VDD - 0.3

or 2.7

—

Lesser of

VDD + 0.3

or 5.5

V

—

VSS - 0.3

VSS + 0.3

Reference Inputs

AD05

AD06

AD07

VREFH

VREFL

VREF

Reference Voltage High

Reference Voltage Low

AVSS + 2.7

AVSS

—

AVDD

V

—

AVDD - 2.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS - 0.3

AD08

IREF

Current Drain

—

200

.001

300

2

μA

A/D operating

A/D off

Analog Input

AD10 VINH-VINL Full-Scale Input Span

VREFL

AVSS - 0.3

—

VREFH

AVDD + 0.3

±0.610

V

See Note 1

AD11

AD12

VIN

—

Absolute Input Voltage

Leakage Current

—

±0.001

μA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Source Impedance =

2.5 kΩ

AD13

—

Leakage Current

Switch Resistance

—

±0.001

±0.610

μA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Source Impedance =

2.5 kΩ

AD15 RSS

—

3.2K

18

—

Ω

pF

Ω

—

AD16 CSAMPLE Sample Capacitor

AD17 RIN

Recommended Impedance

of Analog Voltage Source

—

2.5K

DC Accuracy⁽²⁾

12 data bits

AD20 Nr

Resolution

bits

AD21 INL

Integral Nonlinearity

—

<±1

+3

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD21A INL

AD22 DNL

AD22A DNL

Integral Nonlinearity

Differential Nonlinearity

Gain Error

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD23

GERR

+1.25

+1.5

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

AD23A GERR

Gain Error

+3

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.

DS70139E-page 178

dsPIC30F2011/2012/3012/3013

TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Offset Error

Min.

Typ

Max.

Units

Conditions

AD24

AD24A EOFF

AD25

EOFF

-2

-1.5

-1.25

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Offset Error

-2

-1.5

—

-1.25

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

—

Monotonicity⁽¹⁾

—

Guaranteed

Dynamic Performance

AD30 THD

Total Harmonic Distortion

—

-71

68

—

dB

—

AD31 SINAD

Signal to Noise and

Distortion

—

AD32 SFDR

Spurious Free Dynamic

Range

—

83

—

dB

—

AD33

FNYQ

Input Signal Bandwidth

Effective Number of Bits

—

100

—

kHz

bits

—

AD34 ENOB

10.95

11.1

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references.

DS70139E-page 179

dsPIC30F2011/2012/3012/3013

FIGURE 20-21:

12-BIT A/D CONVERSION TIMING CHARACTERISTICS

(ASAM = 0, SSRC = 000)

AD50

ADCLK

Instruction

Execution

Set SAMP

Clear SAMP

SAMP

ch0_dischrg

ch0_samp

eoc

AD61

AD60

TSAMP

AD55

DONE

ADIF

ADRES(0)

1

2

3

4

5

6

7

8

9

- Software sets ADCON. SAMP to start sampling.

- Sampling starts after discharge period.

1

2

TSAMP is described in the “dsPIC30F Family Reference Manual”, (DS70046), Section 18.

- Software clears ADCON. SAMP to Start conversion.

- Sampling ends, conversion sequence starts.

- Convert bit 11.

3

4

5

6

7

8

9

- Convert bit 10.

- Convert bit 1.

- Convert bit 0.

- One TAD for end of conversion.

DS70139E-page 180

dsPIC30F2011/2012/3012/3013

TABLE 20-37: 12-BIT A/D CONVERSION TIMING REQUIREMENTS

Standard Operating Conditions: 2.7V to 5.5V

(unless otherwise stated)

AC CHARACTERISTICS

TABLE 20-38: OPERATING TEMPERATURE-40°C ≤

TA ≤ +85°C FOR INDUSTRIAL

-40°C ≤ TA ≤ +125°C FOR EXTENDED

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50

AD51

TAD

tRC

A/D Clock Period

A/D Internal RC Oscillator Period

—

334

1.5

—

ns

VDD = 3-5.5V (Note 1)

1.2

1.8

μs

—

Conversion Rate

AD55

AD56

AD57

tCONV

FCNV

Conversion Time

Throughput Rate

Sampling Time

—

14 TAD

200

ns

ksps

ns

—

VDD = VREF = 5V

TSAMP

1 TAD

VDD = 3-5.5V source

resistance

RS = 0-2.5 kΩ

Timing Parameters

AD60

AD61

AD62

AD63

tPCS

tPSS

tCSS

tDPU

Conversion Start from Sample

Trigger

—

0.5 TAD

—

1 TAD

—

ns

μs

—

Sample Start from Setting

Sample (SAMP) Bit

—

1.5

TAD

Conversion Completion to

Sample Start (ASAM = 1)

0.5 TAD

20

—

Time to Stabilize Analog Stage

from A/D Off to A/D On

—

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: These parameters are characterized but not tested in manufacturing.

DS70139E-page 181

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 182

dsPIC30F2011/2012/3012/3013

21.0 PACKAGING INFORMATION

21.1 Package Marking Information

18-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

dsPIC30F3012

30I/P

0610017

e

3

18-Lead SOIC

Example

XXXXXXXXXXXX

dsPIC30F2011

30I/SO

e

3

YYWWNNN

0610017

28-Lead SPDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

dsPIC30F2012

30I/SP

0610017

e

3

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS70139E-page 183

dsPIC30F2011/2012/3012/3013

21.2 Package Marking Information (Continued)

28-Lead SOIC (.300”)

Example

XXXXXXXXXXXXXXXXXXXX

dsPIC30F3013

30I/SO

e

3

YYWWNNN

0610017

28-Lead QFN

Example

XXXXXXX

30F2011

30I/MM

e

3

YYWWNNN

0610017

44-Lead QFN

Example

dsPIC

XXXXXXXXXX

YYWWNNN

30F3013

30I/ML

e

3

0610017

DS70139E-page 184

dsPIC30F2011/2012/3012/3013

18-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

α

n

1

E

A2

L

A

c

A1

B1

β

p

B

eB

Units

INCHES*

NOM

18

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

18

MAX

n

p

Number of Pins

Pitch

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.890

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

22.61

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.898

.130

.012

.058

.018

.370

10

.325

.260

.905

.135

.015

.070

.022

.430

15

7.94

6.35

22.80

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

22.99

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-007

DS70139E-page 185

dsPIC30F2011/2012/3012/3013

18-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

p

E1

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

18

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

18

MAX

n

p

Number of Pins

Pitch

.050

.099

.091

.008

.407

.295

.454

.020

.033

4

1.27

Overall Height

A

.093

.104

2.36

2.24

2.50

2.31

0.20

10.34

7.49

11.53

0.50

0.84

4

2.64

2.39

0.30

10.67

7.59

11.73

0.74

1.27

8

Molded Package Thickness

A2

A1

E

.088

.004

.394

.291

.446

.010

.016

0

.094

.012

.420

.299

.462

.029

.050

8

Standoff

§

0.10

10.01

7.39

11.33

0.25

0.41

0

Overall Width

Molded Package Width

Overall Length

Chamfer Distance

Foot Length

E1

D

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.012

.020

15

0.23

0.36

0

0.27

0.42

12

0.30

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-051

DS70139E-page 186

dsPIC30F2011/2012/3012/3013

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

n

1

α

E

A2

L

A

c

B1

β

A1

eB

B

p

Units

INCHES

*

MILLIMETERS

Dimension Limits

MIN

NOM

28

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.140

.150

.130

.160

3.56

3.18

3.81

3.30

4.06

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

.135

3.43

0.38

7.62

6.99

34.16

3.18

0.20

1.02

0.41

8.13

5

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

34.67

3.30

0.29

1.33

0.48

8.89

10

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

5

β

5

10

15

5

10

15

*

Controlling Parameter

§

Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

DS70139E-page 187

dsPIC30F2011/2012/3012/3013

28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

B

2

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

28

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.050

1.27

Overall Height

A

.093

.099

.091

.008

.407

.295

.704

.020

.033

4

.104

2.36

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

2.64

Molded Package Thickness

A2

A1

E

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

Standoff

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

c

Foot Angle Top

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

DS70139E-page 188

dsPIC30F2011/2012/3012/3013

28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body [QFN-S]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

E2

E

b

2

1

2

1

K

N

L

NOTE 1

TOP VIEW

BOTTOM VIEW

A

A3

A1

Units

MILLIMETERS

NOM

Dimension Limits

MAX

MIN

28

Number of Pins

Pitch

N

e

0.65 BSC

0.90

0.80

0.00

Overall Height

Standoff

A

1.00

0.05

0.02

A1

A3

E

0.20 REF

6.00 BSC

3.70

Contact Thickness

Overall Width

3.65

Exposed Pad Width

Overall Length

E2

D

4.70

6.00 BSC

3.70

3.65

0.23

0.30

0.20

Exposed Pad Length

Contact Width

D2

b

4.70

0.43

0.50

—

0.38

0.40

Contact Length §

Contact-to-Exposed Pad §

L

—

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–124, Sept. 8, 2006

DS70139E-page 189

dsPIC30F2011/2012/3012/3013

44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

E

E2

b

2

1

2

1

N

K

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A3

A1

Units

MILLIMETERS

Dimension Limits

NOM

44

MAX

MIN

Number of Pins

Pitch

N

e

0.65 BSC

0.90

0.80

0.00

Overall Height

Standoff

A

1.00

0.05

0.02

A1

A3

E

0.20 REF

8.00 BSC

6.45

Contact Thickness

Overall Width

6.30

Exposed Pad Width

Overall Length

E2

D

6.80

8.00 BSC

6.45

6.30

0.25

0.30

0.20

Exposed Pad Length

Contact Width

D2

b

6.80

0.38

0.50

—

0.30

0.40

Contact Length §

Contact-to-Exposed Pad §

L

—

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Package is saw singulated

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–103, Sept. 8, 2006

DS70139E-page 190

dsPIC30F2011/2012/3012/3013

APPENDIX A: REVISION HISTORY

Revision D (August 2006)

Previous versions of this data sheet contained

Advance or Preliminary Information. They were distrib-

uted with incomplete characterization data.

This revision reflects these updates:

• Supported I²C Slave Addresses

(see Table 14-1)

• ADC Conversion Clock selection to allow

200 kHz sampling rate (see Section 16.0 “12-bit

Analog-to-Digital Converter (ADC) Module”)

• Operating Current (IDD) Specifications

(see Table 20-5)

• Idle Current (IIDLE) Specifications

(see Table 20-6)

• Power-Down Current (IPD) Specifications

(see Table 20-7)

• I/O pin Input Specifications

(see Table 20-8)

• BOR voltage limits

(see Table 20-11)

• Watchdog Timer time-out limits

(see Table 20-21)

Revision E (December 2006)

This revision includes updates to the packaging

diagrams.

DS70139E-page 191

dsPIC30F2011/2012/3012/3013

NOTES:

DS70139E-page 192

dsPIC30F2011/2012/3012/3013

2

I C .............................................................................. 94

INDEX

Input Capture Mode.................................................... 81

Oscillator System...................................................... 121

Output Compare Mode............................................... 85

Numerics

12-bit Analog-to-Digital Converter (A/D) Module .............. 109

Reset System ........................................................... 125

Shared Port Structure................................................. 57

SPI.............................................................................. 89

SPI Master/Slave Connection..................................... 90

UART Receiver......................................................... 102

UART Transmitter..................................................... 101

BOR Characteristics ......................................................... 153

BOR. See Brown-out Reset.

A

A/D.................................................................................... 109

Aborting a Conversion .............................................. 111

ADCHS Register....................................................... 109

ADCON1 Register..................................................... 109

ADCON2 Register..................................................... 109

ADCON3 Register..................................................... 109

ADCSSL Register ..................................................... 109

ADPCFG Register..................................................... 109

Configuring Analog Port Pins.............................. 58, 115

Connection Considerations....................................... 115

Conversion Operation............................................... 110

Effects of a Reset...................................................... 114

Operation During CPU Idle Mode ............................. 114

Operation During CPU Sleep Mode.......................... 114

Output Formats......................................................... 114

Power-Down Modes.................................................. 114

Programming the Sample Trigger............................. 111

Register Map............................................................. 117

Result Buffer ............................................................. 110

Sampling Requirements............................................ 113

Selecting the Conversion Sequence......................... 110

AC Characteristics ............................................................ 155

Load Conditions........................................................ 155

AC Temperature and Voltage Specifications.................... 155

ADC

Brown-out Reset

Characteristics.......................................................... 153

Timing Requirements ............................................... 161

C

C Compilers

MPLAB C18.............................................................. 142

MPLAB C30.............................................................. 142

CAN Module

I/O Timing Characteristics ........................................ 177

I/O Timing Requirements.......................................... 177

CLKOUT and I/O Timing

Characteristics.......................................................... 160

Requirements ........................................................... 160

Code Examples

Data EEPROM Block Erase ....................................... 54

Data EEPROM Block Write ........................................ 56

Data EEPROM Read.................................................. 53

Data EEPROM Word Erase ....................................... 54

Data EEPROM Word Write ........................................ 55

Erasing a Row of Program Memory ........................... 49

Initiating a Programming Sequence ........................... 50

Loading Write Latches................................................ 50

Code Protection................................................................ 119

Control Registers................................................................ 48

NVMADR.................................................................... 48

NVMADRU ................................................................. 48

NVMCON.................................................................... 48

NVMKEY .................................................................... 48

Core Architecture

Selecting the Conversion Clock................................ 111

ADC Conversion Speeds.................................................. 112

Address Generator Units .................................................... 41

Alternate Vector Table ........................................................ 67

Analog-to-Digital Converter. See ADC.

Assembler

MPASM Assembler................................................... 142

Automatic Clock Stretch...................................................... 96

During 10-bit Addressing (STREN = 1)....................... 96

During 7-bit Addressing (STREN = 1)......................... 96

Receive Mode............................................................. 96

Transmit Mode............................................................ 96

Overview..................................................................... 17

CPU Architecture Overview................................................ 17

Customer Change Notification Service............................. 199

Customer Notification Service .......................................... 199

Customer Support............................................................. 199

B

Bandgap Start-up Time

Requirements............................................................ 162

Timing Characteristics .............................................. 162

Barrel Shifter ....................................................................... 25

Bit-Reversed Addressing .................................................... 44

Example...................................................................... 45

Implementation ........................................................... 44

Modifier Values Table ................................................. 45

Sequence Table (16-Entry)......................................... 45

Block Diagrams

D

Data Accumulators and Adder/Subtractor .......................... 23

Data Space Write Saturation...................................... 25

Overflow and Saturation............................................. 23

Round Logic ............................................................... 24

Write-Back.................................................................. 24

Data Address Space........................................................... 33

Alignment.................................................................... 36

Alignment (Figure)...................................................... 36

Effect of Invalid Memory Accesses (Table) ................ 36

MCU and DSP (MAC Class) Instructions Example .... 35

Memory Map......................................................... 33, 34

Near Data Space........................................................ 37

Software Stack ........................................................... 37

Spaces........................................................................ 36

Width .......................................................................... 36

Data EEPROM Memory...................................................... 53

Erasing ....................................................................... 54

12-bit ADC Functional............................................... 109

16-bit Timer1 Module.................................................. 71

16-bit Timer2............................................................... 77

16-bit Timer3............................................................... 77

32-bit Timer2/3............................................................ 76

DSP Engine ................................................................ 22

dsPIC30F2011............................................................ 10

dsPIC30F2012............................................................ 11

dsPIC30F3013............................................................ 13

External Power-on Reset Circuit............................... 127

DS70139E-page 193

dsPIC30F2011/2012/3012/3013

Erasing, Block.............................................................54

Erasing, Word .............................................................54

I

I/O Pin Specifications

Protection Against Spurious Write ..............................56

Input.......................................................................... 151

Reading.......................................................................53

Write Verify .................................................................56

Writing.........................................................................55

Writing, Block..............................................................55

Writing, Word ..............................................................55

DC Characteristics ............................................................145

BOR ..........................................................................153

Brown-out Reset .......................................................153

I/O Pin Input Specifications.......................................151

I/O Pin Output Specifications ....................................151

Idle Current (IIDLE) ....................................................148

Low-Voltage Detect...................................................152

LVDL .........................................................................152

Operating Current (IDD).............................................147

Power-Down Current (IPD) ........................................149

Program and EEPROM.............................................154

Temperature and Voltage Specifications..................145

Development Support .......................................................141

Device Configuration

Output....................................................................... 151

I/O Ports.............................................................................. 57

Parallel (PIO) .............................................................. 57

2

I C 10-bit Slave Mode Operation........................................ 95

Reception ................................................................... 96

Transmission .............................................................. 96

I C 7-bit Slave Mode Operation.......................................... 95

2

Reception ................................................................... 95

Transmission .............................................................. 95

I C Master Mode Operation................................................ 97

2

Baud Rate Generator ................................................. 98

Clock Arbitration ......................................................... 98

Multi-Master Communication, Bus Collision and

Bus Arbitration.................................................... 98

Reception ................................................................... 98

Transmission .............................................................. 97

2

I C Master Mode Support................................................... 97

I C Module

2

Addresses................................................................... 95

Bus Data Timing Characteristics

Master Mode..................................................... 173

Slave Mode....................................................... 175

Bus Data Timing Requirements

Master Mode..................................................... 174

Slave Mode....................................................... 175

Bus Start/Stop Bits Timing Characteristics

Register Map.............................................................132

Device Configuration Registers

FBORPOR ................................................................130

FGS...........................................................................130

FOSC ........................................................................130

FWDT........................................................................130

Device Overview .............................................................9, 17

Disabling the UART...........................................................103

Divide Support.....................................................................20

Instructions (Table) .....................................................20

DSP Engine.........................................................................21

Multiplier......................................................................23

Dual Output Compare Match Mode ....................................86

Continuous Pulse Mode..............................................86

Single Pulse Mode ......................................................86

Master Mode..................................................... 173

Slave Mode....................................................... 175

General Call Address Support.................................... 97

Interrupts .................................................................... 97

IPMI Support............................................................... 97

Operating Function Description .................................. 93

Operation During CPU Sleep and Idle Modes............ 98

Pin Configuration ........................................................ 93

Programmer’s Model .................................................. 93

Register Map .............................................................. 99

Registers .................................................................... 93

Slope Control.............................................................. 97

Software Controlled Clock Stretching (STREN = 1) ... 96

Various Modes............................................................ 93

Idle Current (IIDLE) ............................................................ 148

In-Circuit Serial Programming (ICSP)......................... 47, 119

Input Capture (CAPX) Timing Characteristics .................. 165

Input Capture Module ......................................................... 81

Interrupts .................................................................... 82

Register Map .............................................................. 83

Input Capture Operation During Sleep and Idle Modes...... 82

CPU Idle Mode ........................................................... 82

CPU Sleep Mode........................................................ 82

Input Capture Timing Requirements................................. 165

Input Change Notification Module....................................... 61

dsPIC30F2012/3013 Register Map (Bits 7-0)............. 61

Instruction Addressing Modes ............................................ 41

File Register Instructions............................................ 41

Fundamental Modes Supported ................................. 41

MAC Instructions ........................................................ 42

MCU Instructions ........................................................ 41

Move and Accumulator Instructions............................ 42

Other Instructions ....................................................... 42

Instruction Set

E

Electrical Characteristics

AC .............................................................................155

DC.............................................................................145

Enabling and Setting Up UART

Alternate I/O..............................................................103

Setting Up Data, Parity and Stop Bit Selections .......103

Enabling the UART ...........................................................103

Equations

ADC Conversion Clock .............................................111

Baud Rate.................................................................105

Serial Clock Rate ........................................................98

Errata ....................................................................................7

Exception Sequence

Trap Sources ..............................................................65

External Clock Timing Characteristics

Type A, B and C Timer .............................................163

External Clock Timing Requirements................................156

Type A Timer ............................................................163

Type B Timer ............................................................164

Type C Timer ............................................................164

External Interrupt Requests ................................................68

F

Fast Context Saving............................................................68

Flash Program Memory.......................................................47

Overview................................................................... 136

Summary .................................................................. 133

DS70139E-page 194

dsPIC30F2011/2012/3012/3013

Internal Clock Timing Examples ....................................... 158

Internet Address................................................................ 199

Interrupt Controller

P

Packaging Information...................................................... 183

Marking............................................................. 183, 184

Peripheral Module Disable (PMD) Registers.................... 131

PICSTART Plus Development Programmer..................... 144

Pinout Descriptions............................................................. 14

PLL Clock Timing Specifications ...................................... 157

POR. See Power-on Reset.

Port Write/Read Example ................................................... 58

PORTB

Register Map for dsPIC30F2011/3012....................... 59

Register Map for dsPIC30F2012/3013....................... 59

PORTC

Register Map......................................................... 69, 70

Interrupt Priority .................................................................. 64

Traps........................................................................... 65

Interrupt Sequence ............................................................. 67

Interrupt Stack Frame ................................................. 67

Interrupts............................................................................. 63

L

Load Conditions................................................................ 155

Low Voltage Detect (LVD) ................................................ 129

Low-Voltage Detect Characteristics.................................. 152

LVDL Characteristics ........................................................ 152

Register Map for dsPIC30F2011/2012/3012/3013..... 59

PORTD

Register Map for dsPIC30F2011/3012....................... 59

Register Map for dsPIC30F2012/3013....................... 60

PORTF

Register Map for dsPIC30F2012/3013....................... 60

Power Saving Modes........................................................ 129

Idle............................................................................ 130

Sleep ........................................................................ 129

Sleep and Idle........................................................... 119

Power-Down Current (IPD)................................................ 149

Power-up Timer

Timing Characteristics.............................................. 161

Timing Requirements ............................................... 161

Program Address Space..................................................... 27

Construction ............................................................... 29

Data Access from Program Memory Using

M

Memory Organization.......................................................... 27

Core Register Map...................................................... 37

Microchip Internet Web Site.............................................. 199

Modulo Addressing ............................................................. 42

Applicability................................................................. 44

Incrementing Buffer Operation Example..................... 43

Start and End Address................................................ 43

W Address Register Selection .................................... 43

MPLAB ASM30 Assembler, Linker, Librarian ................... 142

MPLAB ICD 2 In-Circuit Debugger ................................... 143

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator .................................................... 143

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator .................................................... 143

MPLAB Integrated Development Environment Software .. 141

MPLAB PM3 Device Programmer .................................... 143

MPLINK Object Linker/MPLIB Object Librarian ................ 142

Program Space Visibility..................................... 31

Data Access From Program Memory Using

Table Instructions ............................................... 30

Data Access from, Address Generation ..................... 29

Data Space Window into Operation ........................... 32

Data Table Access (LS Word).................................... 30

Data Table Access (MS Byte) .................................... 31

Memory Map............................................................... 28

Table Instructions

N

NVM

Register Map............................................................... 51

O

TBLRDH ............................................................. 30

TBLRDL.............................................................. 30

TBLWTH............................................................. 30

TBLWTL ............................................................. 30

Program and EEPROM Characteristics............................ 154

Program Counter................................................................ 18

Programmable .................................................................. 119

Programmer’s Model .......................................................... 18

Diagram...................................................................... 19

Programming Operations.................................................... 49

Algorithm for Program Flash....................................... 49

Erasing a Row of Program Memory ........................... 49

Initiating the Programming Sequence ........................ 50

Loading Write Latches................................................ 50

Protection Against Accidental Writes to OSCCON........... 124

OC/PWM Module Timing Characteristics.......................... 167

Operating Current (IDD)..................................................... 147

Operating Frequency vs Voltage

dsPIC30FXXXX-20 (Extended)................................. 145

Oscillator

Configurations........................................................... 122

Fail-Safe Clock Monitor .................................... 124

Fast RC (FRC).................................................. 123

Initial Clock Source Selection ........................... 122

Low-Power RC (LPRC)..................................... 123

LP Oscillator Control......................................... 123

Phase Locked Loop (PLL) ................................ 123

Start-up Timer (OST) ........................................ 122

Operating Modes (Table).......................................... 120

System Overview...................................................... 119

Oscillator Selection ........................................................... 119

Oscillator Start-up Timer

R

Reader Response............................................................. 200

Reset ........................................................................ 119, 125

BOR, Programmable ................................................ 127

Brown-out Reset (BOR)............................................ 119

Oscillator Start-up Timer (OST)................................ 119

POR

Timing Characteristics .............................................. 161

Timing Requirements................................................ 161

Output Compare Interrupts ................................................. 87

Output Compare Module..................................................... 85

Register Map............................................................... 88

Timing Characteristics .............................................. 166

Timing Requirements................................................ 166

Output Compare Operation During CPU Idle Mode............ 87

Output Compare Sleep Mode Operation ............................ 87

Operating without FSCM and PWRT................ 127

With Long Crystal Start-up Time ...................... 127

POR (Power-on Reset)............................................. 125

DS70139E-page 195

dsPIC30F2011/2012/3012/3013

Power-on Reset (POR).............................................119

Power-up Timer (PWRT) ..........................................119

Reset Sequence..................................................................65

Reset Sources ............................................................65

Reset Sources

Brown-out Reset (BOR)..............................................65

Illegal Instruction Trap.................................................65

Trap Lockout...............................................................65

Uninitialized W Register Trap .....................................65

Watchdog Time-out.....................................................65

Reset Timing Characteristics ............................................161

Reset Timing Requirements..............................................161

Run-Time Self-Programming (RTSP) .................................47

Interrupt ...................................................................... 72

Operation During Sleep Mode .................................... 72

Prescaler .................................................................... 72

Real-Time Clock ......................................................... 72

Interrupts ............................................................ 73

Oscillator Operation............................................ 73

Register Map .............................................................. 74

Timer2 and Timer3 Selection Mode.................................... 86

Timer2/3 Module

16-bit Timer Mode....................................................... 75

32-bit Synchronous Counter Mode............................. 75

32-bit Timer Mode....................................................... 75

ADC Event Trigger...................................................... 78

Gate Operation ........................................................... 78

Interrupt ...................................................................... 78

Operation During Sleep Mode .................................... 78

Register Map .............................................................. 79

Timer Prescaler .......................................................... 78

Timing Characteristics

S

Simple Capture Event Mode ...............................................81

Buffer Operation..........................................................82

Hall Sensor Mode .......................................................82

Prescaler.....................................................................81

Timer2 and Timer3 Selection Mode............................82

Simple OC/PWM Mode Timing Requirements..................167

Simple Output Compare Match Mode.................................86

Simple PWM Mode .............................................................86

Input Pin Fault Protection............................................86

Period..........................................................................87

Software Simulator (MPLAB SIM).....................................142

Software Stack Pointer, Frame Pointer...............................18

CALL Stack Frame......................................................37

SPI Module..........................................................................89

Framed SPI Support ...................................................90

Operating Function Description ..................................89

Operation During CPU Idle Mode ...............................91

Operation During CPU Sleep Mode............................91

SDOx Disable .............................................................90

Slave Select Synchronization .....................................91

SPI1 Register Map......................................................92

Timing Characteristics

A/D Conversion

Low-speed (ASAM = 0, SSRC = 000) .............. 180

Bandgap Start-up Time............................................. 162

CAN Module I/O........................................................ 177

CLKOUT and I/O ...................................................... 160

External Clock........................................................... 155

2

I C Bus Data

Master Mode..................................................... 173

Slave Mode....................................................... 175

I C Bus Start/Stop Bits

2

Master Mode..................................................... 173

Slave Mode....................................................... 175

Input Capture (CAPX)............................................... 165

OC/PWM Module...................................................... 167

Oscillator Start-up Timer........................................... 161

Output Compare Module .......................................... 166

Power-up Timer........................................................ 161

Reset ........................................................................ 161

SPI Module

Master Mode (CKE = 0) ....................................168

Master Mode (CKE = 1) ....................................169

Slave Mode (CKE = 1) .............................. 170, 171

Timing Requirements

Master Mode (CKE = 0).................................... 168

Master Mode (CKE = 1).................................... 169

Slave Mode (CKE = 0)...................................... 170

Slave Mode (CKE = 1)...................................... 171

Type A, B and C Timer External Clock..................... 163

Watchdog Timer ....................................................... 161

Timing Diagrams

Master Mode (CKE = 0) ....................................168

Master Mode (CKE = 1) ....................................169

Slave Mode (CKE = 0) ......................................170

Slave Mode (CKE = 1) ......................................172

Word and Byte Communication ..................................90

Status Bits, Their Significance and the Initialization

Condition for RCON Register, Case 1 ......................128

Status Bits, Their Significance and the Initialization

Condition for RCON Register, Case 2 ......................128

Status Register....................................................................18

Symbols Used in Opcode Descriptions.............................134

System Integration

PWM Output Timing ................................................... 87

Time-out Sequence on Power-up (MCLR Not

Tied to VDD), Case 1 ........................................ 126

Time-out Sequence on Power-up (MCLR Not

Tied to VDD), Case 2 ........................................ 126

Time-out Sequence on Power-up (MCLR

Tied to VDD)...................................................... 126

Timing Diagrams and Specifications

Register Map.............................................................132

DC Characteristics - Internal RC Accuracy............... 158

Timing Diagrams.See Timing Characteristics

Timing Requirements

T

Table Instruction Operation Summary ................................47

Temperature and Voltage Specifications

A/D Conversion

Low-speed........................................................ 181

Bandgap Start-up Time............................................. 162

Brown-out Reset....................................................... 161

CAN Module I/O........................................................ 177

CLKOUT and I/O ...................................................... 160

External Clock........................................................... 156

AC .............................................................................155

DC.............................................................................145

Timer 2/3 Module ................................................................75

Timer1 Module ....................................................................71

16-bit Asynchronous Counter Mode ...........................71

16-bit Synchronous Counter Mode .............................71

16-bit Timer Mode.......................................................71

Gate Operation ...........................................................72

2

I C Bus Data (Master Mode) .................................... 174

2

I C Bus Data (Slave Mode) ...................................... 175

DS70139E-page 196

dsPIC30F2011/2012/3012/3013

Input Capture ............................................................ 165

Oscillator Start-up Timer........................................... 161

Output Compare Module........................................... 166

Power-up Timer ........................................................ 161

Reset......................................................................... 161

Simple OC/PWM Mode............................................. 167

SPI Module

Master Mode (CKE = 0).................................... 168

Master Mode (CKE = 1).................................... 169

Slave Mode (CKE = 0)...................................... 170

Slave Mode (CKE = 1)...................................... 172

Type A Timer External Clock .................................... 163

Type B Timer External Clock .................................... 164

Type C Timer External Clock.................................... 164

Watchdog Timer........................................................ 161

Timing Specifications

PLL Clock.................................................................. 157

Trap Vectors ....................................................................... 67

U

UART Module

Address Detect Mode ............................................... 105

Auto-Baud Support ................................................... 106

Baud Rate Generator................................................ 105

Enabling and Setting Up ........................................... 103

Framing Error (FERR)............................................... 105

Idle Status................................................................. 105

Loopback Mode ........................................................ 105

Operation During CPU Sleep and Idle Modes .......... 106

Overview................................................................... 101

Parity Error (PERR) .................................................. 105

Receive Break........................................................... 105

Receive Buffer (UxRXB) ........................................... 104

Receive Buffer Overrun Error (OERR Bit) ................ 104

Receive Interrupt....................................................... 104

Receiving Data.......................................................... 104

Receiving in 8-bit or 9-bit Data Mode........................ 104

Reception Error Handling.......................................... 104

Transmit Break.......................................................... 104

Transmit Buffer (UxTXB)........................................... 103

Transmit Interrupt...................................................... 104

Transmitting Data...................................................... 103

Transmitting in 8-bit Data Mode................................ 103

Transmitting in 9-bit Data Mode................................ 103

UART1 Register Map................................................ 107

UART2 Register Map................................................ 107

UART Operation

Idle Mode .................................................................. 106

Sleep Mode............................................................... 106

Unit ID Locations............................................................... 119

Universal Asynchronous Receiver Transmitter

(UART) Module......................................................... 101

W

Wake-up from Sleep ......................................................... 119

Wake-up from Sleep and Idle ............................................. 68

Watchdog Timer

Timing Characteristics .............................................. 161

Timing Requirements................................................ 161

Watchdog Timer (WDT) ............................................ 119, 129

Enabling and Disabling ............................................. 129

Operation .................................................................. 129

WWW Address.................................................................. 199

WWW, On-Line Support ....................................................... 7

DS70139E-page 197

dsPIC30F2011/2012/3012/3013

DS70139E-page 198

dsPIC30F2011/2012/3012/3013

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS70139E-page 199

dsPIC30F2011/2012/3012/3013

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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dsPIC30F2011/2012/3012/

DS70139E

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS70139E-page 200

dsPIC30F2011/2012/3012/3013

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

dsPIC30F3013AT-30I/SP-ES

Custom ID (3 digits) or

Engineering Sample (ES)

Trademark

Architecture

Package

= DIP

SO = SOIC

P

Flash

SP = SPDIP

ML = QFN (8x8)

Memory Size in Bytes

0 = ROMless

1 = 1K to 6K

2 = 7K to 12K

3 = 13K to 24K

4 = 25K to 48K

5 = 49K to 96K

6 = 97K to 192K

7 = 193K to 384K

8 = 385K to 768K

9 = 769K and Up

Temperature

I = Industrial -40°C to +85°C

E = Extended High Temp -40°C to +125°C

Speed

20 = 20 MIPS

30 = 30 MIPS

Device ID

T = Tape and Reel

A,B,C… = Revision Level

Example:

dsPIC30F3013AT-30I/SP = 30 MIPS, Industrial temp., SPDIP package, Rev. A

DS70139E-page 201

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-3910

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

08/29/06

DS70139E-page 202