DSPIC30F3020AT-30IW [MICROCHIP]
28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers; 44分之28引脚高性能开关电源数字信号控制器型号: | DSPIC30F3020AT-30IW |
厂家: | MICROCHIP |
描述: | 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers |
文件: | 总286页 (文件大小:4333K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
dsPIC30F1010/202X
Data Sheet
28/44-Pin High-Performance
Switch Mode Power Supply
Digital Signal Controllers
© 2006 Microchip Technology Inc.
Preliminary
DS70178C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
DS70178C-page ii
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
28/44-Pin dsPIC30F1010/202X Enhanced Flash
SMPS 16-Bit Digital Signal Controller
Peripheral Features:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
• High-current sink/source I/O pins: 25 mA/25 mA
reference source. For more information on the CPU,
• Three 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
• One 16-bit Capture input functions
• Two 16-bit Compare/PWM output functions
- Dual Compare mode available
High-Performance Modified RISC CPU:
• 3-wire SPI modules (supports 4 Frame modes)
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• UART Module:
• 83 base instructions with flexible addressing
modes
- Supports RS-232, RS-485 and LIN 1.2
- Supports IrDA® with on-chip hardware endec
- Auto wake-up on Start bit
- Auto-Baud Detect
• 24-bit wide instructions, 16-bit wide data path
• 12 Kbytes on-chip Flash program space
• 512 bytes on-chip data RAM
- 4-level FIFO buffer
• 16 x 16-bit working register array
• Up to 30 MIPS operation:
Power Supply PWM Module Features:
- Dual Internal RC
- 9.7 and 14.55 MHz (±1%) Industrial Temp
- 6.4 and 9.7 MHz (±1%) Extended Temp
- 32X PLL with 480 MHz VCO
• Four PWM generators with 8 outputs
• Each PWM generator has independent time base
and duty cycle
- PLL inputs ±3%
• Duty cycle resolution of 1.1 ns at 30 MIPS
• Individual dead time for each PWM generator:
- Dead-time resolution 4.2 ns at 30 MIPS
- Dead time for rising and falling edges
• Phase-shift resolution of 4.2 ns @ 30 MIPS
• Frequency resolution of 8.4 ns @ 30 MIPS
• PWM modes supported:
- External EC clock 6.0 to 14.55 MHz
- HS Crystal mode 6.0 to 14.55 MHz
• 32 interrupt sources
• Three external interrupt sources
• 8 user-selectable priority levels for each interrupt
• 4 processor exceptions and software traps
- Complementary
DSP Engine Features:
- Push-Pull
- Multi-Phase
• Modulo and Bit-Reversed modes
- Variable Phase
• Two 40-bit wide accumulators with optional
saturation logic
- Current Reset
- Current-Limit
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• Independent Current-Limit and Fault Inputs
• Output Override Control
• Single-cycle Multiply-Accumulate (MAC)
operation
• Special Event Trigger
• 40-stage Barrel Shifter
• Dual data fetch
• PWM generated ADC Trigger
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 1
dsPIC30F1010/202X
Analog Features:
Special Microcontroller Features:
ADC
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100k (typical)
• 10-bit resolution
• 2000 Ksps conversion rate
• Up to 12 input channels
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• “Conversion pairing” allows simultaneous conver-
sion of two inputs (i.e., current and voltage) with a
single trigger
• Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
• PWM control loop:
• Fail-Safe clock monitor operation
- Up to six conversion pairs available
• Detects clock failure and switches to on-chip low
power RC oscillator
- Each conversion pair has up to four PWM
and seven other selectable trigger sources
• Programmable code protection
• Interrupt hardware supports up to 1M interrupts
per second
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes
COMPARATOR
• Four Analog Comparators:
- 20 ns response time
CMOS Technology:
- 10-bit DAC reference generator
- Programmable output polarity
- Selectable input source
- ADC sample and convert capable
• PWM module interface
- PWM Duty Cycle Control
- PWM Period Control
• Low-power, high-speed Flash technology
• 3.3V and 5.0V operation (±10%)
• Industrial and Extended temperature ranges
• Low power consumption
- PWM Fault Detect
• Special Event Trigger
• PWM-generated ADC Trigger
dsPIC30F SWITCH MODE POWER SUPPLY FAMILY
Product
dsPIC30F1010 28 SDIP
dsPIC30F1010 28 SOIC
dsPIC30F1010 28 QFN-S
dsPIC30F2020 28 SDIP
dsPIC30F2020 28 SOIC
dsPIC30F2020 28 QFN-S
dsPIC30F2023 44 QFN
dsPIC30F2023 44 TQFP
6K
6K
256
256
256
512
512
512
512
512
2
2
2
3
3
3
3
3
0
0
0
1
1
1
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2x2
2x2
2x2
4x2
4x2
4x2
4x2
4x2
1
1
1
1
1
1
1
1
3
3
3
5
5
5
5
5
6 ch
6 ch
6 ch
8 ch
8 ch
8 ch
12 ch
12 ch
2
2
2
4
4
4
4
4
21
21
21
21
21
21
35
35
6K
12K
12K
12K
12K
12K
DS70178C-page 2
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Pin Diagrams
28-Pin SDIP and SOIC
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
VSS
OSC1/CLKI/RB6
OSC2/CLKO/RB7
PGD1/EMUD1/T2CK/U1ATX/CN1/RE7
PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6
RE5
VDD
9
VSS
10
11
12
13
14
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
VDD
PGD2/EMUD2/SCK1/SFLT3/INT2/RF6
PGC2/EMUC2/OC1/SFLT1/INT1/RD0
28-Pin QFN-S
28272625242322
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
1
2
3
4
5
6
7
21
PWM2L/RE2
20 PWM2H/RE3
19 RE4
AN5/CMP2D/CN7/RB5
dsPIC30F1010
RE5
VDD
18
17
16
15
VSS
OSC1/CLKI/RB6
OSC2/CLKO/RB7
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
8
9 10 111213 14
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 3
dsPIC30F1010/202X
Pin Diagrams
28-Pin SDIP and SOIC
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
VSS
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
V
DD
9
20
19
18
17
16
15
VSS
10
11
12
13
14
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6
VDD
PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6
PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0
28-Pin QFN-S
28272625242322
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
1
2
3
4
5
6
7
21
20 PWM2H/RE3
PWM2L/RE2
19
18
17
16
15
PWM3L/RE4
PWM3H/RE5
dsPIC30F2020
VSS
VDD
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
8
9 1011 121314
DS70178C-page 4
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Pin Diagrams
44-PIN QFN
44 43 42 41 40 39 38 37 36 35 34
PGC/EMUC/SDI1/RF7
SYNCO/SS1/RF15
SFLT3/RA10
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN8/CMP4C/RB8
SFLT4/RA11
SDA/RG3
VSS
VDD
dsPIC30F2023
VSS
AN10/IFLT4/RB10
AN11/IFLT2/RB11
AN5/CMP2D/CMP3B/CN7/RB5
AN4/CMP2C/CMP3A/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
10
11
12 13 14 15 16 17 18 19 20 21 22
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 5
dsPIC30F1010/202X
Pin Diagrams
44-Pin TQFP
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN8/CMP4C/RB8
PGC/EMUC/SDI1/RF7
SYNCO/SS1/RF15
SFLT3/RA10
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
VSS
SFLT4/RA11
SDA/RG3
VDD
dsPIC30F2023
AN10/IFLT4/RB10
AN11/IFLT2/RB11
VSS
VDD
AN5/CMP2D/CMP3B/CN7/RB5
AN4/CMP2C/CMP3A/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
9
10
11
25
24
23
DS70178C-page 6
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 19
3.0 Memory Organization................................................................................................................................................................. 29
4.0 Address Generator Units............................................................................................................................................................ 41
5.0 Interrupts .................................................................................................................................................................................... 47
6.0 I/O Ports ..................................................................................................................................................................................... 77
7.0 Flash Program Memory.............................................................................................................................................................. 81
8.0 Timer1 Module ........................................................................................................................................................................... 87
9.0 Timer2/3 Module ........................................................................................................................................................................ 91
10.0 Input Capture Module................................................................................................................................................................. 97
11.0 Output Compare Module.......................................................................................................................................................... 101
12.0 Power Supply PWM ................................................................................................................................................................. 107
13.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 145
14.0 I2C™ Module ........................................................................................................................................................................... 153
15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 161
16.0 10-bit 2 Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169
17.0 SMPS Comparator Module ...................................................................................................................................................... 191
18.0 System Integration ................................................................................................................................................................... 197
19.0 Instruction Set Summary.......................................................................................................................................................... 219
20.0 Development Support............................................................................................................................................................... 227
21.0 Electrical Characteristics.......................................................................................................................................................... 231
22.0 Package Marking Information................................................................................................................................................... 267
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 7
dsPIC30F1010/202X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS70178C-page 8
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
This document contains device specific information for
the dsPIC30F1010/202X SMPS devices. These devices
contain extensive Digital Signal Processor (DSP) func-
tionality within a high-performance 16-bit microcontroller
(MCU) architecture, as reflected in the following block
diagrams. Figure 1-1 and Table 1-1 describe the
dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2
describe the dsPIC30F2020 device and Figure 1-3 and
Table 1-3 describe the dsPIC30F2023 SMPS device.
1.0
DEVICE OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 9
dsPIC30F1010/202X
FIGURE 1-1:
dsPIC30F1010 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
16
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
Data Latch
Interrupt
Controller
PSV & Table
Data Access
Control Block
X Data
RAM
(256 bytes)
Address
Latch
8
16
24
24
SFLT2/INT0/OCFLTA/RA9
24
PORTA
16
16
16
X RAGU
X WAGU
Y AGU
PCH PCL
PCU
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
OSC1/CLKI/RB6
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
(12 Kbytes)
Effective Address
OSC2/CLKO/RB7
16
Data Latch
PORTB
ROM Latch
16
24
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
PGC2/EMUC2/OC1/SFLT1/
INT1/RD0
OSC1/CLK1
ALU<16>
16
POR
Reset
PORTD
16
Watchdog
Timer
MCLR
Output
Compare
Module
Comparator
Module
I2C™
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
10-bit ADC
PWM2H/RE3
RE4
RE5
PGC1/EMUC1/EXTREF/T1CK/
U1ARX/CN0/RE6
PGD1/EMUD1/T2CK/U1ATX/
CN1/RE7
Input
Change
Notification
SMPS
PWM
SPI1
Timers
UART1
PORTE
PORTF
PGD2/EMUD2/SCK1/SFLT3/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
DS70178C-page 10
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Table 1-1 provides a brief description of device I/O
pinouts for the dsPIC30F1010 and the functions that
may be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010
Pin
Buffer
Type
Description
Type
AN0-AN5
AVDD
I
Analog
Analog input channels.
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
AVSS
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
PWM1L
PWM1H
PWM2L
PWM2H
I
I
I
O
O
O
O
ST
ST
ST
—
—
—
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
—
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1
O
I
—
Compare outputs.
OCFLTA
ST
Output Compare Fault Pin
OSC1
OSC2
I
CMOS
—
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
I/O
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/0
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
RB0-RB7
RA9
I/O
I/O
I/O
ST
ST
ST
PORTB is a bidirectional I/O port.
PORTA is a bidirectional I/O port.
PORTD is a bidirectional I/O port.
RD0
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 11
dsPIC30F1010/202X
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED)
Pin
Buffer
Type
Description
Type
RE0-RE7
I/O
I/O
ST
ST
PORTE is a bidirectional I/O port.
RF6, RF7, RF8
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
O
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
P
I
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
External reference to Comparator DAC
VSS
EXTREF
Analog
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
DS70178C-page 12
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 1-2:
dsPIC30F2020 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
16
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
Data Latch
Interrupt
Controller
PSV & Table
Data Access
Control Block
X Data
RAM
(256 bytes)
Address
Latch
8
16
24
24
SFLT2/INT0/OCFLTA/RA9
24
PORTA
16
16
16
X RAGU
X WAGU
Y AGU
PCH PCL
PCU
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
Program Counter
Stack
Control
Logic
Loop
Control
Logic
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
Address Latch
Program Memory
(12 Kbytes)
Effective Address
OSC1/CLKI/RB6
16
Data Latch
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
PORTB
ROM Latch
16
24
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
PGC2/EMUC2/OC1/SFLT1/IC1/
INT1/RD0
OSC1/CLK1
ALU<16>
16
POR
Reset
PORTD
16
Watchdog
Timer
MCLR
Input
Capture
Module
Output
Compare
Module
Comparator
Module
I2C™
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
10-bit ADC
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PGC1/EMUC1/EXTREF/PWM4L/
Input
Change
Notification
SMPS
PWM
T1CK/ U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/
U1ATX/CN1/RE7
SPI1
Timers
UART1
PORTE
PORTF
PGD2/EMUD2/SCK1/SFLT3/OC2/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 13
dsPIC30F1010/202X
Table 1-2 provides a brief description of device I/O
pinouts for the dsPIC30F2020 and the functions that
may be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-2:
Pin Name
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020
Pin
Buffer
Type
Description
Type
AN0-AN7
AVDD
I
Analog
Analog input channels.
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
AVSS
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1
I
ST
Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
I
I
I
ST
ST
ST
—
—
—
—
—
—
—
—
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
O
O
O
O
O
O
O
O
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA
O
I
—
Compare outputs.
Output Compare Fault pin
OSC1
OSC2
I
CMOS
—
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
I/O
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
I
I/O
I
I/O
I
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
DS70178C-page 14
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 1-2:
Pin Name
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED)
Pin
Buffer
Type
Description
Type
RB0-RB7
RA9
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
PORTB is a bidirectional I/O port.
PORTA is a bidirectional I/O port.
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RD0
RE0-RE7
RF6, RF7, RF8
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
ST
—
ST
O
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
O
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
P
I
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
External reference to Comparator DAC
VSS
EXTREF
Analog
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 15
dsPIC30F1010/202X
FIGURE 1-3:
dsPIC30F2023 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
16
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
Data Latch
Interrupt
Controller
PSV & Table
Data Access
Control Block
X Data
RAM
(256 bytes)
Address
Latch
SFLT1/RA8
SFLT2/INT0/OCFLTA/RA9
SFLT3/RA10
8
16
24
24
24
SFLT4/RA11
16
16
16
PORTA
X RAGU
X WAGU
Y AGU
PCH PCL
PCU
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
Program Counter
Loop
Control
Logic
Stack
Control
Logic
Address Latch
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
Program Memory
(12 Kbytes)
Effective Address
OSC1/CLKI/RB6
16
Data Latch
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
AN8/CMP4C/RB8
AN9/EXTREF/CMP4D/RB9
AN10/IFLT4/RB10
ROM Latch
16
24
AN11/IFLT2/RB11
IR
PORTB
PORTD
16
16
16 x 16
W Reg Array
PGC2/EMUC2/OC1/IC1/INT1/
RD0
OC2/RD1
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
DSP
Engine
Divide
Unit
Power-up
Timer
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
Timing
Generation
Oscillator
Start-up Timer
OSC1/CLK1
ALU<16>
16
POR
Reset
16
Watchdog
Timer
MCLR
PGC1/EMUC1/PWM4L/T1CK/
U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/
U1ATX/CN1/RE7
PORTE
Input
Capture
Module
Output
Compare
Module
Comparator
Module
I2C™
10-bit ADC
U1RX/RF2
U1TX/RF3
PGD2/EMUD2/SCK1/INT2/RF6
PGC/EMUC/SDI1/RF7
PGD/EMUD/SD01/RF8
SYNCI/RF14
Input
Change
Notification
Power Supply
PWM
SYNCO/SSI/RF15
SPI1
Timers
UART1
PORTF
PORTG
SCL/RG2
SDA/RG3
DS70178C-page 16
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Table 1-3 provides a brief description of device I/O
pinouts for the dsPIC30F2023 and the functions that
may be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-3:
Pin Name
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023
Pin
Buffer
Type
Description
Type
AN0-AN11
AVDD
I
Analog
Analog input channels.
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
AVSS
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1
I
ST
Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
I
I
I
ST
ST
ST
ST
ST
ST
—
—
—
—
—
Shared Fault 1
Shared Fault 2
Shared Fault 3
Shared Fault 4
Independent Fault 2
Independent Fault 4
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
I
O
O
O
O
O
O
O
O
—
—
—
SYNCO
SYNCI
O
I
—
ST
PWM SYNC output
PWM SYNC input
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA
O
I
—
ST
Compare outputs.
Output Compare Fault condition.
OSC1
OSC2
I
CMOS
—
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
I/O
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 17
dsPIC30F1010/202X
TABLE 1-3:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED)
Pin
Type
Buffer
Type
Pin Name
Description
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
I
I/O
I
I/O
I
RA8-RA11
RB0-RB11
RD0,RD1
RE0-RE7
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
PORTA is a bidirectional I/O port.
PORTB is a bidirectional I/O port.
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RF2, RF3,
RF6-RF8, RF14,
RF15
RG2, RG3
I/O
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
I
O
I
ST
SPI #1 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit
O
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
Comparator 4 Channel C
Comparator 4 Channel D
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
P
I
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
External reference to Comparator DAC
VSS
EXTREF
Analog
Legend: CMOS
=
=
=
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
ST
I
DS70178C-page 18
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
2.0
CPU ARCHITECTURE
OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Overhead-free circular buffers (modulo addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing
mode on destination effective addresses, to greatly
simplify input or output data reordering for radix-2 FFT
algorithms. Refer to Section 4.0 “Address Generator
Units” for details on modulo and Bit-Reversed
Addressing.
2.1
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are sup-
ported using the DOand REPEAT instructions, both of
which are interruptible at any point.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
The working register array consists of 16x16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer for interrupts and calls.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula-
tor or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by
dedicating certain working registers to each address
space for the MAC class of instructions.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
There are two methods of accessing data stored in
program memory:
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
• The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction access
program space as if it were data space, with a limita-
tion that the access requires an additional cycle.
Moreover, only the lower 16 bits of each instruction
word can be accessed using this method.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 19
dsPIC30F1010/202X
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated software Stack Pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned
stack accesses, W15<0> is always clear.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
• PUSH.Sand POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS Register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
• DOinstruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSBs) can be manipulated
through byte wide data memory space accesses.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level Status bits, IPL<2:0>, and the REPEAT active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value, which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
DS70178C-page 20
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 2-1:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD0
AD15
AD39
AD31
DSP
Accumulators
ACCA
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
DOLoop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
OA OB
SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV
Z
C
IPL2 IPL1
STATUS Register
SRL
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 21
dsPIC30F1010/202X
The divide instructions must be executed within a
REPEATloop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT.
The divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly
and correctly specified in the REPEAT instruction, as
shown in Table 2-1 (REPEAT will execute the target
instruction {operand value + 1} times). The REPEAT
loop count must be set up for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1. DIVF– 16/16 signed fractional divide
2. DIV.sd– 32/16 signed divide
3. DIV.ud– 32/16 unsigned divide
4. DIV.sw– 16/16 signed divide
5. DIV.uw– 16/16 unsigned divide
Note:
The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm / Wn → W0; Rem → W1
DIV.sd
DIV.ud
DIV.sw
DIV.uw
Unsigned divide: Wm / Wn → W0; Rem → W1
DS70178C-page 22
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
2.4
DSP Engine
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/sub-
tracter (with two target accumulators, round and
saturation logic).
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for ACCA (SATA).
5. Automatic saturation on/off for ACCB (SATB).
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUBand NEG.
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
Note:
For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
DSP INSTRUCTION SUMMARY
Algebraic Operation
A = 0
Instruction
ACC WB?
CLR
Yes
No
ED
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
EDAC
MAC
No
Yes
No
MAC
MOVSAC
MPY
No change in A
A = x * y
Yes
No
MPY.N
MSC
A = – x * y
No
A = A – x * y
Yes
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 23
dsPIC30F1010/202X
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
S
a
40
16
40-bit Accumulator A
40-bit Accumulator B
40
t
Round
Logic
u
r
a
t
Carry/Borrow Out
Saturate
e
Adder
Carry/Borrow In
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70178C-page 24
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
2.4.1
MULTIPLIER
2.4.2.1
Adder/Subtracter, Overflow and
Saturation
The 17x17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the mul-
tiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to 40
bits. Integer data is inherently represented as a signed
two’s complement value, where the MSB is defined as
a sign bit. Generally speaking, the range of an N-bit
two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-
bit integer, the data range is -32768 (0x8000) to 32767
(0x7FFF), including 0. For a 32-bit integer, the data
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow Status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
range
is
-2,147,483,648
(0x8000 0000)
to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX for-
mat). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1-21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF), including 0, and has a preci-
sion of 3.01518x10-5. In Fractional mode, a 16x16 mul-
tiply operation generates a 1.31 product, which has a
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow Status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1. OA:
precision of 4.65661x10-10
.
ACCA overflowed into guard bits
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
2. OB:
ACCB overflowed into guard bits
3. SA:
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4. SB:
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADDand LACinstructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 5.0 “Inter-
rupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 25
dsPIC30F1010/202X
The SA and SB bits are modified each time data passes
through the adder/subtracter, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit sat-
uration, or bit 39 for 40-bit saturation) and will be satu-
rated (if saturation is enabled). When saturation is not
enabled, SA and SB default to bit 39 overflow and thus
indicate that a catastrophic overflow has occurred. If the
COVTE bit in the INTCON1 register is set, SA and SB
bits will generate an arithmetic warning trap when
saturation is disabled.
2.4.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
The overflow and saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS Register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
the accumulators.
2. [W13] + = 2, Register Indirect with Post-Incre-
ment: The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block, which per-
forms a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least
significant word (lsw) is simply discarded.
The device supports three Saturation and Overflow
modes.
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data or unexpected algorithm problems
(e.g., gain calculations).
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incre-
mented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this
algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bits are never set).
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb (bit
16 of the accumulator) of ACCxH is examined. If it is ‘1’,
ACCxH is incremented. If it is ‘0’, ACCxH is not modi-
fied. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
3. Bit 39 Catastrophic Overflow
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MACclass
of instructions, the accumulator write back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
DS70178C-page 26
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15 frac-
tional value as output to write to data space memory.
The barrel shifter is capable of performing up to 15-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the max-
imum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is pre-
sented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 15 for left shifts.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 27
dsPIC30F1010/202X
NOTES:
DS70178C-page 28
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 3-1:
PROGRAM SPACE MEMORY
MAP FOR dsPIC30F1010/
202X
3.0
MEMORY ORGANIZATION
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Reset – GOTOInstruction
000000
000002
000004
Reset – Target Address
Reserved
Ext. Osc. Fail Trap
Address Error Trap
Stack Error Trap
Arithmetic Warn. Trap
Reserved
Vector Tables
Reserved
3.1
Program Address Space
Reserved
Vector 0
000014
Vector 1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
Vector 52
Vector 53
00007E
000080
0000FE
000100
Alternate Vector Table
User Flash
Program Memory
(4K instructions)
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
001FFE
002000
Reserved
(Read 0’s)
7FFFFE
800000
Note:
The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Reserved
8005BE
8005C0
UNITID (32 instr.)
Reserved
8005FE
800600
F7FFFE
Device Configuration
Registers
F80000
F8000E
F80010
Reserved
DEVID (2)
FEFFFE
FF0000
FFFFFE
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 29
dsPIC30F1010/202X
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
User
User
(TBLPAG<7> = 0)
0
PC<22:1>
0
TBLRD/TBLWT
TBLPAG<7:0>
TBLPAG<7:0>
PSVPAG<7:0>
Data EA <15:0>
Data EA <15:0>
TBLRD/TBLWT
Configuration
(TBLPAG<7> = 1)
Program Space Visibility User
0
Data EA <14:0>
FIGURE 3-2:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
0
0
Select
1
EA
Using
Program
Space
PSVPAG Reg
Visibility
8 bits
15 bits
EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/
Configuration
Space
Byte
24-bit EA
Select
Select
Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.
DS70178C-page 30
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
A set of Table Instructions is provided to move byte or
word sized data to and from program space.
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
1. TBLRDL:Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDLand TBLWTLinstruc-
tions offer a direct method of reading or writing the least
significant word (lsw) of any address within program
space, without going through data space. The TBLRDH
and TBLWTHinstructions are the only method whereby
the upper 8 bits of a program space word can be
accessed as data.
2. TBLWTL:Table Write Low (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
3. TBLRDH:Table Read High
Word: Read the most significant word of the
program address;
P<23:16> maps to D<7:0>; D<15:8> always
be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the Least Significant
Data Word, and TBLRDH and TBLWTH access the
space which contains the Most Significant Data Byte.
4. TBLWTH:Table Write High (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
Figure 3-2 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
23
8
16
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte
(Read as ‘0’).
TBLRDL.B (Wn<0> = 1)
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 31
dsPIC30F1010/202X
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
TBLRDH.W
PC Address
23
8
0
16
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
TBLRDH.B (Wn<0> = 1)
Note that by incrementing the PC by 2 for each pro-
gram memory word, the Least Significant 15 bits of
data space addresses directly map to the Least Signif-
icant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the Pro-
gram Space Visibility Page register, PSVPAG<7:0>, as
shown in Figure 3-5.
3.1.2
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/Hinstructions).
Note:
PSV access is temporarily disabled during
Table Reads/Writes.
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
For instructions that use PSV which are executed
outside a REPEATloop:
• The following instructions will require one instruc-
tion cycle in addition to the specified execution
time:
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
- MACclass of instructions with data operand
prefetch
- MOVinstructions
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically con-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
- MOV.Dinstructions
• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEATloop:
• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “dsPIC30F/33F Programmer’s Reference Manual”
(DS70157) for details on instruction encoding.
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEATloop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
DS70178C-page 32
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x100100
0x0000
PSVPAG(1)
0x00
8
15
15
EA<15> =
0
Data
Space
16
0x8000
23
15
0
EA
Address
Concatenation
EA<15> = 1
0x001200
0x001FFE
15
23
Upper half of Data
Space is mapped
into Program Space
0xFFFF
BSET CORCON,#2
; PSV bit set
MOV
MOV
MOV
#0x00, W0
W0, PSVPAG
0x9200, W0
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
256 byte data address space (including all
Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 256 bytes data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
A data space memory map is shown in Figure 3-6.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 33
dsPIC30F1010/202X
FIGURE 3-6:
DATA SPACE MEMORY MAP
LSB
Address
MSB
Address
16 bits
MSB
LSB
0x0000
0x0001
SFR Space
(Note)
SFR Space
0x07FE
0x0800
0x07FF
0x0801
2560 bytes
Near
Data
X Data RAM (X)
256 bytes
Space
512 bytes
0x08FF
0x0901
0x08FE
0x0900
SRAM Space
Y Data RAM (Y)
256 bytes
0x09FF
0x8001
0x09FE
0x0A00
(See Note)
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFE
0xFFFF
Note: Unimplemented SFR or SRAM locations read as ‘0’.
DS70178C-page 34
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 3-7:
DATA SPACE FOR MCU AND DSP (MACCLASS) INSTRUCTIONS
SFR SPACE
SFR SPACE
UNUSED
Y SPACE
UNUSED
(Y SPACE)
UNUSED
Non-MACClass Ops (Read/Write)
MACClass Ops (Write)
MACClass Ops Read-Only
Indirect EA using any W
Indirect EA using W10, W11 Indirect EA using W8, W9
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 35
dsPIC30F1010/202X
3.2.2
DATA SPACES
3.2.3
DATA SPACE WIDTH
The X data space is used by all instructions and sup-
ports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data mem-
ory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC,MAC,MOVSAC, MPY,MPY.Nand MSC) to pro-
vide two concurrent data read paths. No writes occur
across the Y bus. This class of instructions dedicates
two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X data path, as part of the composite linear space.
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
FIGURE 3-8:
DATA ALIGNMENT
LSB
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
MSB
15
8 7
0
Attempted Operation
Data Returned
0000
0002
0004
0001
Byte 1
Byte 3
Byte 5
Byte 0
Byte 2
Byte 4
EA = an unimplemented address
0x0000
0x0000
0003
0005
W8 or W9 used to access Y data
space in a MACinstruction
W10 or W11 used to access X
0x0000
data space in a MACinstruction
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70178C-page 36
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap will not occur.
The stack error trap will occur on a subsequent push
operation. Thus, for example, if it is desirable to cause
a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
Similarly, a Stack Pointer Underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
3.2.5
NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
CALLSTACK FRAME
0x0000
15
0
3.2.6
SOFTWARE STACK
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
PC<15:0>
000000000PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
POP: [--W15]
PUSH: [W15++]
3.2.7
DATA RAM PROTECTION
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
The dsPIC30F1010/202X devices support data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot Code
Segment Security. BSRAM (Secure RAM segment for
BS) is accessible only from the Boot Segment Flash
code when enabled. See Table 3-3 for the BSRAM
SFR.
There is a Stack Pointer Limit register (SPLIM) associ-
ated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM<0>
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 37
TABLE 3-3:
CORE REGISTER MAP
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
W0
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032
0034
0036
0038
003A
W0/WREG
W1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
0000 0000 0000 0000
0000 0000 0010 0000
W1
W2
W2
W3
W3
W4
W4
W5
W5
W6
W6
W7
W7
W8
W8
W9
W9
W10
W10
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
Sign-Extension (ACCA<39>)
Sign-Extension (ACCB<39>)
ACCAU
ACCBL
ACCBH
ACCBU
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCH
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
0
0
DOSTARTH 003C
—
—
—
—
—
—
—
—
DOENDL
—
—
DOSTARTH
DOENDL
DOENDH
SR
003E
0040
0042
0044
—
OA
—
—
OB
—
—
SA
—
—
SB
US
—
—
—
DA
—
DOENDH
N
OAB
EDT
SAB
DL2
DC
IPL2
SATA
IPL1
IPL0
RA
OV
Z
C
CORCON
DL1
DL0
SATB SATDW ACCSAT
IPL3
PSV
RND
IF
Legend: u= uninitialized bit
TABLE 3-3:
CORE REGISTER MAP (CONTINUED)
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
MODCON
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
0046 XMODEN YMODEN
—
BWM<3:0>
YWM<3:0>
XWM<3:0>
0000 0000 0000 0000
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0048
004A
004C
004E
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
0
1
0
1
0050
0052
0750
BREN
—
XB<14:0>
DISICNT
—
—
DISICNT<13:0>
BSRAM
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR IR_BSR RL_BSR
Legend: u= uninitialized bit
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 40
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
4.1
Instruction Addressing Modes
4.0
ADDRESS GENERATOR UNITS
The Addressing modes in Table 4-1 form the basis of
the Addressing modes optimized to support the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
4.1.1
FILE REGISTER INSTRUCTIONS
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
TABLE 4-1:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
Register Direct
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
Register Indirect
Register Indirect Post-modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 41
dsPIC30F1010/202X
4.1.2
MCU INSTRUCTIONS
4.1.4
MACINSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
The dual source operand DSP instructions (CLR,ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MACinstructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following Addressing modes are
supported by MCU instructions:
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• 5-bit or 10-bit Literal
Note:
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
In summary, the following Addressing modes are
supported by the MACclass of instructions:
• Register Indirect
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
• Register Indirect Post-modified by 2
• Register Indirect Post-modified by 4
• Register Indirect Post-modified by 6
• Register Indirect with Register Offset (Indexed)
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
4.1.5
OTHER INSTRUCTIONS
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADDAcc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
In summary, the following Addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
DS70178C-page 42
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
4.2.1
START AND END ADDRESS
4.2
Modulo Addressing
The modulo addressing scheme requires that a
starting and an end address be specified and loaded
into the 16-bit modulo buffer address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Note:
Y-space modulo addressing EA calcula-
tions assume word sized data (LSb of
every EA is always clear).
Modulo addressing can operate in either data or pro-
gram space (since the data pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
addressing can operate on any W register pointer. How-
ever, it is not advisable to use W14 or W15 for modulo
addressing, since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
The length of a circular buffer is not directly specified. It
is determined by the difference between the corre-
sponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.2.2
W ADDRESS REGISTER
SELECTION
In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer-
tain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The Modulo and Bit-Reversed Addressing Control reg-
ister MODCON<15:0> contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X RAGU
and X WAGU modulo addressing are disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode, (i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries).
The X Address Space Pointer W register (XWM) to
which modulo addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which modulo addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON<14>.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 43
dsPIC30F1010/202X
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DO
#0x1100,W0
W0, XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
#0x0000,W0
#0x1110,W1
AGAIN,#0x31
W0, [W1++]
;set modulo start address
;set modulo end address
0x1100
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
MOV
AGAIN: INC
W0,W0
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS70178C-page 44
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the Effective
Address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries check for addresses less than or greater than the
upper (for incrementing buffers) and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All Bit-Reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is per-
formed, but the contents of the register
remains unchanged.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other Addressing mode or for
byte sized data, and normal addresses will be gener-
ated instead. When Bit-Reversed Addressing is active,
the W Address Pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
4.3
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
Note:
Modulo addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing will assume priority when active for the
X WAGU, and X WAGU modulo address-
ing will be disabled. However, modulo
addressing will continue to function in the
X RAGU.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
1. BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed
Addressing) and
2. the BREN bit is set in the XBREV register and
3. the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b2 b3 b4
0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16 word Bit-Reversed Buffer
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 45
dsPIC30F1010/202X
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal
Address
Bit-Reversed
Address
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Decimal
A3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Decimal
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
TABLE 4-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
XB<14:0> Bit-Reversed Address Modifier Value(1)
Buffer Size (Words)
32768
16384
8192
4096
2048
1024
512
256
128
64
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
32
16
8
4
2
Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device
DS70178C-page 46
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
• The INTTREG register contains the associated
interrupt vector number and the new CPU inter-
rupt priority level, which are latched into vector
number (VECNUM<6:0>) and Interrupt level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
5.0
INTERRUPTS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
Interrupt flag bits get set when an Interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The dsPIC30F1010/202X device has up to 35 interrupt
sources and 4 processor exceptions (traps), which
must be arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vec-
tor Table (IVT) and transferring the address contained
in the interrupt vector to the Program Counter (PC).
The interrupt vector is transferred from the program
data bus into the Program Counter, via a 24-bit wide
multiplexer on the input of the Program Counter.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Figure 5-1. Levels 7 and 1 repre-
sent the highest and lowest maskable priorities,
respectively.
The Interrupt Vector Table and Alternate Interrupt Vec-
tor Table (AIVT) are placed near the beginning of pro-
gram memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
Note:
Assigning a priority level of 0 to an inter-
rupt source is equivalent to disabling that
interrupt.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled, priori-
tized and controlled using centralized special function
registers:
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Note:
The IPL bits become read-only whenever
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module that generates the
interrupt.
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
• IPC0<15:0>... IPC11<7:0>
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program Mem-
ory that corresponds to the interrupt. There are 63 dif-
ferent vectors within the IVT (refer to Figure 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Figure 5-1).
These locations contain 24-bit addresses, and, in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally decre-
menting a PC into vector space, accidentally mapping
a data space address into vector space, or the PC roll-
ing over to 0x000000 after reaching the end of imple-
mented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
• IPL<3:0> The current CPU priority level is explic-
itly stored in the IPL bits. IPL<3> is present in the
CORCON register, whereas IPL<2:0> are present
in the STATUS Register (SR) in the processor
core.
• INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external inter-
rupt request signal behavior and the use of the
alternate vector table.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 47
dsPIC30F1010/202X
TABLE 5-1:
dsPIC30F1010/202X
INTERRUPT VECTOR TABLE
5.1
Interrupt Priority
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble, within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
INT
Vector
Interrupt Source
Number Number
Highest Natural Order Priority
0
1
8
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer 1
9
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Note:
The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
3
4
Reserved
5
OC2 – Output Compare 2
T2 – Timer 2
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
6
7
T3 – Timer 3
8
SPI1
9
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45-53
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same user-
assigned priority become pending at the same time.
2
SI2C – I C™ Slave Event
2
MI2C – I C Master Event
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
Reserved
INT1 – External Interrupt 1
INT2 – External Interrupt 2
PWM Special Event Trigger
PWM Gen#1
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
PWM Gen#2
2: The natural order priority number is the
PWM Gen#3
same as the INT number.
PWM Gen#4
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. The INT0 (external interrupt
0) may be assigned to priority level 1, thus giving it a
very low effective priority.
Reserved
Reserved
Reserved
Reserved
CN – Input Change Notification
Reserved
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
Reserved
Reserved
Reserved
Reserved
ADC Pair 0 Conversion Done
ADC Pair 1 Conversion Done
ADC Pair 2 Conversion Done
ADC Pair 3 Conversion Done
ADC Pair 4 Conversion Done
ADC Pair 5 Conversion Done
Reserved
Reserved
53-61 Reserved
Lowest Natural Order Priority
DS70178C-page 48
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
5.2
Reset Sequence
5.3
Traps
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The pro-
cessor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion, immediately followed by the address target for the
GOTOinstruction. The processor executes the GOTOto
the specified address and then begins operation at the
specified target (start) address.
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
If the user does not intend to take correc-
tive action in the event of a Trap Error con-
dition, these vectors must be loaded with
the address of a default handler that sim-
ply contains the RESET instruction. If, on
the other hand, one of the vectors contain-
ing an invalid address is called, an
address error trap is generated.
5.2.1
RESET SOURCES
In addition to External Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the question-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
• Trap Lockout:
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Occurrence of multiple Trap conditions
simultaneously will cause a Reset.
Math Error Trap:
The Math Error trap executes under the following four
circumstances:
1. Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
2. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3. If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
4. If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 49
dsPIC30F1010/202X
Address Error Trap:
5.3.2
HARD AND SOFT TRAPS
This trap is initiated when any of the following
circumstances occurs:
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-1 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
1. A misaligned data word access is attempted.
2. A data fetch from our unimplemented data
memory location is attempted.
3. A data access of an unimplemented program
memory location is attempted.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
4. An instruction fetch from vector space is
attempted.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Note:
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
5. Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
6. Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
Stack Error Trap:
FIGURE 5-1:
TRAP VECTORS
This trap is initiated under the following conditions:
Reset - GOTOInstruction
Reset - GOTOAddress
0x000000
0x000002
0x000004
1. The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
2. The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
IVT
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
0x000014
Oscillator Fail Trap:
—
—
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
0x00007E
0x000080
0x000082
Reserved
0x000084
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
AIVT
Reserved Vector
Reserved Vector
0x000094
0x0000FE
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
DS70178C-page 50
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
5.4
Interrupt Sequence
5.5
Alternate Vector Table
In Program Memory, the IVT is followed by the AIVT, as
shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and excep-
tion processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a sup-
port environment, without requiring the interrupt vec-
tors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program
Counter and the low byte of the processor STATUS
Register (SRL), as shown in Figure 5-2. The low byte
of the STATUS register contains the processor priority
level at the time, prior to the beginning of the interrupt
cycle. The processor then loads the priority level for
this interrupt into the STATUS register. This action will
disable all lower priority interrupts until the completion
of the Interrupt Service Routine (ISR).
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.Sand POP.S
instructions only.
FIGURE 5-2:
INTERRUPT STACK
FRAME
0x0000 15
0
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
PC<15:0>
SRL IPL3 PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
POP : [--W15]
PUSH : [W15++]
5.7
External Interrupt Requests
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
The interrupt controller supports three external inter-
rupt request signals, INT0-INT2. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The
INTCON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
The RETFIE (Return from Interrupt) instruction will
unstack the Program Counter and status registers to
return the processor to its state prior to the interrupt
sequence.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine needed to process the interrupt request.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 51
dsPIC30F1010/202X
REGISTER 5-1:
R/W-0
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
MATHERR ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B enabled
0= Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divided by zero
0= Math error trap was not caused by an invalid accumulator shift
bit 5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Status bit
1= Overflow trap has occurred
0= Overflow trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
DS70178C-page 52
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-1:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 53
dsPIC30F1010/202X
REGISTER 5-2:
R/W-0
INTCON2: INTERRUPT CONTROL REGISTER 2
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ALTIVT
DISI
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
DS70178C-page 54
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-3:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
R/W-0
R/W-0
R/W-0
SPI1IF
MI2CIF
SI2CIF
NVMIF
U1TXIF
U1RXIF
bit 15
bit 8
R/W-0
T3IF
R/W-0
T2IF
R/W-0
OC2IF
U-0
—
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
MI2CIF: I2C Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
bit 10
bit 9
SI2CIF: I2C Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
NVMIF: Nonvolatile Memory Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADIF: ADC Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 55
dsPIC30F1010/202X
REGISTER 5-3:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70178C-page 56
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-4:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
AC3IF
R/W-0
AC2IF
R/W-0
AC1IF
U-0
—
R/W-0
CNIF
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IF
R/W-0
INT1IF
PWM4IF
PWM3IF
PWM2IF
PWM1IF
PSEMIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
AC3IF: Analog Comparator #3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
AC2IF: Analog Comparator #2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
AC1IF: Analog Comparator #1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
Unimplemented: Read as ‘0’
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10-7
bit 6
Unimplemented: Read as ‘0’
PWM4IF: Pulse Width Modulation Generator #4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PWM3IF: Pulse Width Modulation Generator #3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
PWM2IF: Pulse Width Modulation Generator #2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
PWM1IF: Pulse Width Modulation Generator #1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 57
dsPIC30F1010/202X
REGISTER 5-5:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-00
R/W-0
ADCP5IF
ADCP4IF
ADCP3IF
bit 15
bit 8
R/W-0
ADCP2IF
bit 7
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
AC4IF
ADCP1IF
ADCP0IF
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 9
bit 8
bit 7
bit 6
bit 5
ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4-1
bit 0
Unimplemented: Read as ‘0’
AC4IF: Analog Comparator #4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70178C-page 58
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-6:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
R/W-0
R/W-0
R/W-0
MI2CIE
SI2CIE
NVMIE
U1TXIE
U1RXIE
SPI1IE
bit 15
bit 8
R/W-0
T3IE
R/W-0
T2IE
R/W-0
OC2IE
U-0
—
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
MI2CIE: I2C Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
bit 11
bit 10
bit 9
SI2CIE: I2C Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
NVMIE: Nonvolatile Memory Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADIE: ADC Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 59
dsPIC30F1010/202X
REGISTER 5-6:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70178C-page 60
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-7:
R/W-0
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
AC2IE
R/W-0
AC1IE
U-0
—
R/W-0
CNIE
U-0
—
U-0
—
U-0
—
AC3IE
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWM4IE
PWM3IE
PWM2IE
PWM1IE
PSEMIE
INT2IE
INT1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
AC3IE: Analog Comparator #3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
AC2IE: Analog Comparator #2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
AC1IE: Analog Comparator #1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12
bit 11
Unimplemented: Read as ‘0’
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 10-7
bit 6
Unimplemented: Read as ‘0’
PWM4IE: Pulse Width Modulation Generator #4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PWM3IE: Pulse Width Modulation Generator #3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
PWM2IE: Pulse Width Modulation Generator #2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
PWM1IE: Pulse Width Modulation Generator #1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
PSEMIE: PWM Special Event Match Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 61
dsPIC30F1010/202X
REGISTER 5-8:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ADCP5IE
ADCP4IE
ADCP3IE
bit 15
bit 8
R/W-0
ADCP2IE
bit 7
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
AC4IE
ADCP1IE
ADCP0IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
ADCP5IE: ADC Pair 5 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 9
bit 8
bit 7
bit 6
bit 5
ADCP4IE: ADC Pair 4 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADCP3IE: ADC Pair 3 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADCP2IE: ADC Pair 2 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADCP1IE: ADC Pair 1 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADCP0IE: ADC Pair 0 Conversion done Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
AC4IE: Analog Comparator #4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70178C-page 62
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-9:
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
IC1IP<2:0>
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 63
dsPIC30F1010/202X
REGISTER 5-10: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T3IP<2:0>
T2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
OC2IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T3IP<2:0>: Timer3 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
T2IP<2:0>: Timer2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70178C-page 64
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-11: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
ADIP<2:0>
U1TXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
U1RXIP<2:0>
SPI1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADIP<2:0>: ADC Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 65
dsPIC30F1010/202X
REGISTER 5-12: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
MI2CIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
SI2CIP<2:0>
NVMIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
MI2CIP<2:0>: I2C Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2CIP<2:0>: I2C Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
NVMIP<2:0>: Nonvolatile Memory Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70178C-page 66
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-13: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
PWM1IP<2:0>
PSEMIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
INT2IP<2:0>
INT1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
PWM1IP<2:0>: PWM Generator #1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PSEMIP<2:0>: PWM Special Event Match Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 67
dsPIC30F1010/202X
REGISTER 5-14: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
PWM4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
PWM3IP<2:0>
PWM2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
PWM4IP<2:0>: PWM Generator #4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWM3IP<2:0>: PWM Generator #3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PWM2IP<2:0>: PWM Generator #2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70178C-page 68
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-15: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CNIP<2:0>
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 69
dsPIC30F1010/202X
REGISTER 5-16: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
AC3IP<2:0>
AC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
AC1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70178C-page 70
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-17: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
AC4IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 71
dsPIC30F1010/202X
REGISTER 5-18: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
ADCP2IP<2:0>
ADCP1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
ADCP0IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70178C-page 72
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-19: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
ADCP5IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
ADCP4IP<2:0>
ADCP3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10 - 8
Unimplemented: Read as ‘0’
ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 73
dsPIC30F1010/202X
REGISTER 5-20: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
Unimplemented: Read as ‘0’
bit 7
bit 6-0
VECNUM: Vector Number of Pending Interrupt bits
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
DS70178C-page 74
Preliminary
© 2006 Microchip Technology Inc.
TABLE 5-2:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
ADR Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
INTCON1
INTCON2
IFS0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0100 0100 0100 0100
0100 0100 0100 0000
0100 0100 0100 0100
0000 0100 0100 0100
0100 0100 0100 0100
0000 0100 0100 0100
0100 0000 0000 0000
0100 0100 0100 0000
0000 0000 0000 0100
0100 0100 0100 0000
0000 0100 0100 0100
0000 0000 0000 0000
NSTDIS OVAERR OVBERR COVAERR COVBERR
OVATE
—
OVBTE
—
COVTE
—
SFTACERR DIV0ERR
—
—
MATHERR ADDRERR STKERR OSCFAIL
0080
0082
0084
0086
0088
0094
0096
0098
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00B8
00E0
—
ALTIVT
—
DISI
MI2CIF
AC2IF
—
—
SI2CIF
AC1IF
—
NVMIF
—
—
ADIF
CNIF
—
—
T3IF
—
—
—
—
—
T1IF
PWM1IF
—
INT2EP
OC1IF
PSEMIF
—
INT1EP INT0EP
U1TXIF
—
U1RXIF
—
SPI1IF
—
T2IF
OC2IF
PWM3IF
IC1IF
INT2IF
INT0IF
INT1IF
AC4IF
INT0IE
INT1IE
AC4IE
IFS1
AC3IF
—
PWM4IF
PWM2IF
—
IFS2
—
—
ADCP5IF ADCP4IF ADCP3IF
ADCP2IF
T3IE
—
ADCP1IF ADCP0IF
—
IEC0
—
MI2CIE
AC2IE
—
SI2CIE
AC1IE
NVMIE
—
ADIE
CNIE
—
U1TXIE
—
U1RXIE
—
SPI1IE
—
T2IE
OC2IE
—
T1IE
PWM1IE
—
OC1IE
PSEMIE
—
IC1IE
IEC1
AC3IE
—
PWM4IE
PWM3IE
PWM2IE
—
INT2IE
IEC2
—
—
ADCP5IE ADCP4IE ADCP3IE ADCP2IE
ADCP1IE ADCP0IE
IC1IP<2:0>
—
IPC0
—
T1IP<2:0>
T31P<2:0>
ADIP<2:0>
—
—
OC1IP<2:0>
T2IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>
—
IPC1
—
—
OC2IP<2:0>
—
—
—
IPC2
—
—
U1TXIP<2:0>
MI2CIP<2:0>
PSEMIP<2:0>
PWM4IP<2:0>
—
U1RXIP<2:0>
SI2CIP<2:0>
—
SPI1IP<2:0>
NVMIP<2:0>
INT1IP<2:0>
IPC3
—
—
—
—
—
—
—
IPC4
—
PWM1IP<2:0>
—
—
INT2IP<2:0>
—
IPC5
—
—
PWM3IP<2:0>
—
PWM2IP<2:0>
IPC6
—
CNIP<2:0>
AC3IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IPC7
—
—
AC2IP<2:0>
—
AC1IP<2:0>
—
—
IPC8
—
—
—
—
—
AC4IP<2:0>
—
IPC9
—
ADCP2IP<2:0>
—
—
ADCP1IP<2:0>
ADCP5IP<2:0>
ADCP0IP<2:0>
ADCP4IP<2:0>
—
—
—
IPC10
INTTREG
—
—
—
—
—
—
—
ADCP3IP<2:0>
—
—
ILR<3:0>
VECNUM<6:0>
Note:
Refer to the “dsPIC30F/33F Family Reference Manual” (DS70157) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 76
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
6.0
I/O PORTS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
A Parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 6-1 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 6-1 and Table 6-2
show the register formats for the shared ports, PORTA
through PORTF, for the dsPIC30F1010/2020 and
PORTA through PORTG for the dsPIC30F2023 device,
respectively.
6.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
FIGURE 6-1:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
Peripheral Output Data
1
Output Enable
0
1
PIO Module
Output Data
0
Read TRIS
I/O Pad
Data Bus
WR TRIS
D
Q
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 77
dsPIC30F1010/202X
6.2
Configuring Analog Port Pins
6.3
Input Change Notification
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The input change notification function of the I/O ports
allows the dsPIC30F1010/202X devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature is
capable of detecting input change-of-states even in
Sleep mode, when the clocks are disabled. There are
8 external signals (CN0 through CN7) that can be
selected (enabled) for generating an interrupt request
on a change-of-state.
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
There are two control registers associated with the CN
module. The CNEN1 register contain the CN interrupt
enable (CNxIE) control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
6.2.1
I/O PORT WRITE/READ TIMING
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
register, which contain the weak pull-up enable (CNx-
PUE) bits for each of the CN pins. Setting any of the
control bits enables the weak pull-ups for the
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 6-1:
PORT WRITE/READ
EXAMPLE
corresponding pins.
MOV 0xFF00, W0; Configure PORTB<15:8>
; as inputs
MOV W0, TRISBB; and PORTB<7:0> as outputs
Note: Pull-ups on change notification pins should
always be disabled whenever the port pin is
configured as a digital output.
NOP
; Delay 1 cycle
BTSS PORTB, #13; Next Instruction
DS70178C-page 78
Preliminary
© 2006 Microchip Technology Inc.
TABLE 6-1:
dsPIC30F1010/2020 PORT REGISTER MAP
Bit
12
Bit
11
SFR Name
Addr.
Bit 15
Bit 14 Bit 13
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TRISA
PORTA
LATA
02C0
02C2
02C4
02C6
02C8
02CA
02D2
02D4
02D6
02D8
02DA
02DC
02DE
02E0
02E2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA9
RA9
LAT9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0010 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TRISB
PORTB
LATB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111
—
RB7
LATB7
—
RB6
LATB6
—
RB5
LATB5
—
RB4
LATB4
—
RB3
LATB3
—
RB2
LATB2
—
RB1
LATB1
—
RB0
0000 0000 0000 0000
0000 0000 0000 0000
—
LATB0
TRISD
PORTD
LATD
—
TRISD0 0000 0000 0000 0001
—
—
—
—
—
—
—
—
RD0
0000 0000 0000 0000
0000 0000 0000 0000
—
—
—
—
—
—
—
—
LATD0
TRISE
PORTE
LATE
—
TRSE7 TRSE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0000 1111 1111
—
RE7
RE6
RE5
LATE5
—
RE4
LATE4
—
RE3
LATE3
—
RE2
LATE2
—
RE1
LATE1
—
RE0
LATE0
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 1100 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
LATE7
LATE6
TRISF
PORTF
LATF
—
TRISF8 TRISF7 TRISF6
—
RF8
RF7
RF6
—
—
—
—
—
—
—
LATF8
LATF7
LATF6
—
—
—
—
—
—
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
TABLE 6-2:
dsPIC30F2023 PORT REGISTER MAP
SFR
Name
Bit
12
Addr.
Bit 15
Bit 14
Bit 13
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TRISA
02C0
02C2
02C4
02C6
02C8
02CA
02D2
02D4
02D6
02D8
02DA
02DC
02DE
02E0
02E2
02E4
02E6
02E8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA11 TRISA10 TRIS9 TRISA8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 1111 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
PORTA
LATA
RA11
RA10
RA9
RA8
LATA11 LATA10 LATA9
LATA8
TRISB
PORTB
LATB
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRIS6
RB11 RB10 RB9 RB8 RB7 RB6
LATB11 LATB10 LATB9 LATB8 LATB7 LATB6
RB5
LATB5
—
RB4
LATB4
—
RB3
RB2
RB1
LATB1
TRISD1
RD1
RB0
LATB3 LATB2
LATB0
TRISD
PORTD
LATD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD0 0000 0000 0000 0011
0000 0000 0000 0000
—
—
RD0
0000 0000 0000 0000
LATD1
—
—
LATD0
TRISE
PORTE
LATE
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
TRSE7 TRSE6
RE7 RE6
LATE7 LATE6
0000 0000 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
1100 0001 1100 1100
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 1100
0000 0000 0000 0000
0000 0000 0000 0000
RE5
LATE5
—
RE4
LATE4
—
RE3
RE2
RE1
LATE1
—
RE0
LATE0
—
LATE3 LATE2
TRISF3 TRISF2
TRISF
PORTF
LATF
TRISF15 TRISF14
TRISF8 TRISF7 TRISF6
RF3
RF2
RF15
LATF15
—
RF14
LATF14
—
RF8
LATF8
—
RF7
RF6
—
—
—
—
LATF3
LATF2
LATF7 LATF6
—
—
—
—
TRISG
PORTG
LATG
TRISG3 TRISG2
RG3 RG2
LATG3 LATG2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
TABLE 6-3:
dsPIC30F1010/202X INPUT CHANGE NOTIFICATION REGISTER MAP
SFR
Name
Bit
12
Addr. Bit 15
Bit 14 Bit 13
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CN1IE
Bit 0
CN0IE
Reset State
CNEN1
CNPU1
0060
0064
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
0000 0000 0000 0000
0000 0000 0000 0000
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
7.2
Run-Time Self-Programming
(RTSP)
7.0
FLASH PROGRAM MEMORY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT(table write) instructions.
With RTSP, the user may erase program memory 32
instructions (96 bytes) at a time and can write program
memory data 32 instructions (96 bytes) at a time.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
7.3
Table Instruction Operation Summary
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits <15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
Word or Byte mode.
1. In-Circuit Serial Programming™ (ICSP™)
programming capability
The TBLRDHand TBLWTHinstructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTHcan access program memory in Word or
Byte mode.
2. Run-Time Self-Programming (RTSP)
7.1
In-Circuit Serial Programming
(ICSP)
A 24-bit program memory address is formed using bits
<7:0> of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 7-1.
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manu-
facture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 7-1:
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
16 bits
Byte
Select
User/Configuration
Space Select
24-bit EA
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 81
dsPIC30F1010/202X
7.4
RTSP Operation
7.5
Control Registers
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program 32
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
The four SFRs used to read and write the program
Flash memory are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
7.5.1
NVMCON REGISTER
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction ‘0’, instruction
‘1’, etc. The instruction words loaded must always be
from a group of 32 boundary.
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
7.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWTinstructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
7.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been executed.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
7.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 7.6
“Programming Operations” for further details.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
Note:
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
DS70178C-page 82
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
7.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
5. Program 32 instruction words into program
Flash.
a) Setup NVMCON register for multi-word,
program Flash, program and set WREN bit.
b) Write ‘55’ to NVMKEY.
c) Write ‘AA’ to NVMKEY.
7.6.1
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
d) Set the WR bit. This will begin program
cycle.
The user can erase and program one row of program
Flash memory at a time. The general process is:
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
1. Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
6. Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
2. Update the data image with the desired new
data.
7.6.2
ERASING A ROW OF PROGRAM
MEMORY
3. Erase program Flash row.
a) Setup NVMCON register for multi-word,
program Flash, erase and set WREN bit.
Example 7-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write ‘55’ to NVMKEY.
d) Write ‘AA’ to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 7-1:
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV
MOV
#0x4041,W0
W0 NVMCON
;
; Init NVMCON SFR
,
; Init pointer to row to be ERASED
MOV
MOV
MOV
MOV
DISI
#tblpage(PROG_ADDR),W0
;
W0 NVMADRU
; Initialize PM Page Boundary SFR
; Intialize in-page EA<15:0> pointer
; Intialize NVMADR SFR
; Block all interrupts with priority <7
; for next 5 instructions
,
#tbloffset(PROG_ADDR),W0
W0, NVMADR
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 83
dsPIC30F1010/202X
7.6.3
LOADING WRITE LATCHES
Example 7-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches. 32
TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the table pointer.
EXAMPLE 7-2:
LOADING WRITE LATCHES
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000,W0
;
W0 TBLPAG
; Initialize PM Page Boundary SFR
; An example program memory address
,
#0x6000,W0
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0,W2
#HIGH_BYTE_0,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
; 1st_program_word
MOV
MOV
#LOW_WORD_1,W2
#HIGH_BYTE_1,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
;
2nd_program_word
MOV
MOV
#LOW_WORD_2,W2
#HIGH_BYTE_2,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
•
•
•
; 31st_program_word
MOV
MOV
#LOW_WORD_31,W2
#HIGH_BYTE_31,W3
;
;
TBLWTL W2 [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
,
TBLWTH W3 [W0++]
,
Note: In Example 7-2, the contents of the upper byte of W3 have no effect.
7.6.4
INITIATING THE PROGRAMMING
SEQUENCE
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.
EXAMPLE 7-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0 NVMKEY
; Write the 0x55 key
;
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
,
#0xAA,W1
W1 NVMKEY
,
NVMCON,#WR
DS70178C-page 84
Preliminary
© 2006 Microchip Technology Inc.
TABLE 7-1:
NVM REGISTER MAP
Bit
11
Bit
10
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All RESETS
NVMCON
NVMADR
NVMADRU
NVMKEY
0760
0762
0764
0766
WR
WREN
WRERR
—
—
—
—
TWRI
—
PROGOP<6:0>
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
NVMADR<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMADR<23:16>
KEY<7:0>
Legend:
Note:
u= uninitialized bit
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 86
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register PR1, then
resets to 0 and continues to count.
8.0
TIMER1 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
This section describes the 16-bit General Purpose
Timer1 module and associated operational modes.
Figure 8-1 depicts the simplified block diagram of the
16-bit Timer1 Module.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
Note:
Timer1 is a ‘Type A’ timer. Please refer to
the specifications for a Type A timer in
Section 21.0 “Electrical Characteris-
tics” of this document.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
The following sections provide a detailed description of
the operational modes of the timers, including setup
and control registers along with associated block
diagrams.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free running interval timer/counter. The 16-bit timer has
the following modes:
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
When the timer is configured for the Asynchronous mode
of operation and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
Further, the following operational characteristics are
supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit period register match or falling
edge of external gate signal
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 8-1
presents a block diagram of the 16-bit timer module.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 87
dsPIC30F1010/202X
FIGURE 8-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
PR1
Comparator x 16
TMR1
Equal
Reset
TSYNC
1
Sync
0
0
1
T1IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
T1CK
1 X
Gate
Sync
Prescaler
1, 8, 64, 256
0 1
0 0
TCY
8.1
Timer Gate Operation
8.3
Timer Operation During Sleep
Mode
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 1) and
• The TSYNC bit (T1CON<2>) is asserted to a logic
‘0’, which defines the external clock source as
asynchronous
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
When all three conditions are true, the timer will
continue to count up to the period register and be reset
to 0x0000.
8.2
Timer Prescaler
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.
The input clock (FOSC/2 or external clock) to the 16-bit
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256 selected by control bits TCKPS<1:0>
(T1CON<5:4>). The prescaler counter is cleared when
any of the following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
DS70178C-page 88
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
8.4
Timer Interrupt
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 89
TABLE 8-1:
TIMER1 REGISTER MAP
SFR Name Addr.
Bit 15
Bit 14 Bit 13
Bit 12
Bit 11
Bit 10 Bit 9
Bit 8
Timer 1 Register
Period Register 1
TGATE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TMR1
PR1
0100
0102
0104
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
T1CON
Legend:
Note:
TON
—
TSIDL
—
—
—
—
—
—
TCKPS<1:0>
—
TSYNC
TCS
—
u= uninitialized bit
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
For 32-bit timer/counter operation, Timer2 is the least
significant word and Timer3 is the most significant word
of the 32-bit timer.
9.0
TIMER2/3 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Note:
For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer 2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer3 interrupt flag
(T3IF) and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
This section describes the 32-bit General Purpose
Timer module (Timer2/3) and associated operational
modes. Figure 9-1 depicts the simplified block diagram
of the 32-bit Timer2/3 module. Figure 9-2 and Figure 9-
3 show Timer2/3 configured as two independent 16-bit
timers: Timer2 and Timer3, respectively.
16-bit Mode: In the 16-bit mode, Timer2 and Timer3
can be configured as two independent 16-bit timers.
Each timer can be set up in either 16-bit Timer mode or
16-bit Synchronous Counter mode. See Section 8.0
“Timer1 Module” for details on these two operating
modes.
Note:
The dsPIC30F1010 device does not fea-
ture Timer3. Timer2 is a ‘Type B’ timer and
Timer3 is a ‘Type C’ timer. Please refer to
the appropriate timer type in Section 21.0
“Electrical Characteristics” of this
document.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high-frequency
external clock inputs.
The Timer2/3 module is a 32-bit timer, which can be
configured as two 16-bit timers, with selectable operat-
ing modes. These timers are utilized by other
peripheral modules such as:
32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the combined 32-bit period regis-
ter PR3/PR2, then resets to ‘0’ and continues to count.
• Input Capture
• Output Compare/Simple PWM
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the least significant word (TMR2 register)
will cause the most significant word to be read and
The following sections provide a detailed description,
including setup and control registers, along with asso-
ciated block diagrams for the operational modes of the
timers.
latched into
TMR3HLD.
a
16-bit holding register, termed
The 32-bit timer has the following modes:
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the
32-bit timer (TMR3).
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
• Single 32-bit Timer operation
• Single 32-bit Synchronous Counter
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register, PR3/PR2, then resets
to ‘0’ and continues.
Further, the following operational characteristics are
supported:
• ADC Event Trigger
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-bit Period Register Match
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer will stop incrementing, unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU Idle mode.
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 91
dsPIC30F1010/202X
FIGURE 9-1:
32-BIT TIMER2/3 BLOCK DIAGRAM
Data Bus<15:0>
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3
TMR2
LSB
Sync
MSB
ADC Event Trigger
Comparator x 32
Equal
PR3
PR2
0
1
T3IF
Event Flag
Q
Q
D
TGATE(T2CON<6>)
CK
TGATE
(T2CON<6>)
TCKPS<1:0>
2
TON
T2CK
1 X
Prescaler
1, 8, 64, 256
Gate
Sync
0 1
0 0
TCY
Note:
Timer Configuration bit T32, (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
DS70178C-page 92
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 9-2:
16-BIT TIMER2 BLOCK DIAGRAM
PR2
Equal
Comparator x 16
TMR2
Reset
Sync
0
T2IF
Event Flag
Q
Q
D
TGATE
1
CK
TGATE
TCKPS<1:0>
2
TON
T2CK
1 X
0 1
0 0
Prescaler
1, 8, 64, 256
Gate
Sync
TCY
FIGURE 9-3:
16-BIT TIMER3 BLOCK DIAGRAM
PR3
ADC Event Trigger
Equal
Reset
Comparator x 16
TMR3
0
1
T3IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
Sync
TCY
1 X
0 1
0 0
Prescaler
1, 8, 64, 256
Note:
The dsPIC30F202X does not have an external pin input to TIMER3. The following modes should not be used:
1. TCS = 1
2. TCS = 0and TGATE = 1(gated time accumulation)
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 93
dsPIC30F1010/202X
9.1
Timer Gate Operation
9.4
Timer Operation During Sleep
Mode
The 32-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
9.5
Timer Interrupt
The 32-bit timer module can generate an interrupt on
period match, or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener-
ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.
The falling edge of the external signal terminates the
count operation, but does not reset the timer. The user
must reset the timer in order to start counting from zero.
9.2
ADC Event Trigger
When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
9.3
Timer Prescaler
The input clock (FOSC/2 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• clearing either of the TON (T2CON<15> or
T3CON<15>) bits to ‘0’
• device Reset such as POR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70178C-page 94
Preliminary
© 2006 Microchip Technology Inc.
TABLE 9-1:
TIMER2/3 REGISTER MAP
SFR
Name
Bit
10
Addr.
Bit 15
Bit 14 Bit 13
Bit 12
Bit 11
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TMR2
0106
Timer2 Register
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
TMR3HLD 0108
Timer3 Holding Register (For 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
Period Register 2
PR3
Period Register 3
T2CON
T3CON
Legend:
Note:
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
u= uninitialized bit
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 96
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
The key operational features of the Input Capture
module are:
10.0 INPUT CAPTURE MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where x =
1,2,...,N). The dsPIC DSC devices contain up to 8
capture channels, (i.e., the maximum value of N is 8).
This section describes the Input Capture module and
associated operational modes. The features provided
by this module are useful in applications requiring Fre-
quency (Period) and Pulse measurement. Figure 10-1
depicts a block diagram of the Input Capture module.
Input capture is useful for such modes as:
Note:
The dsPIC30F1010 devices does not fea-
ture Input Capture module. The
a
dsPIC30F202X devices have one capture
input – IC1. The naming of this capture
channel is intentional and preserves soft-
ware compatibility with other dsPIC DSC
devices.
• Frequency/Period/Pulse Measurements
• Additional sources of External Interrupts
FIGURE 10-1:
INPUT CAPTURE MODE BLOCK DIAGRAM
T3_CNT
16
T2_CNT
From General Purpose Timer Module
16
ICx
Pin
ICTMR
1
0
Edge
Detection
Logic
FIFO
R/W
Logic
Prescaler
1, 4, 16
Clock
Synchronizer
3
ICM<2:0>
Mode Select
ICxBUF
ICBNE, ICOV
ICI<1:0>
Interrupt
Logic
ICxCON
Data Bus
Set Flag
ICxIF
Note:
Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 97
dsPIC30F1010/202X
10.1.3
TIMER2 AND TIMER3 SELECTION
MODE
10.1 Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
The input capture module consists of up to 8 input cap-
ture channels. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.
• Capture every falling edge
• Capture every rising edge
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
10.1.4
HALL SENSOR MODE
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the fol-
lowing operations are performed by the input capture
logic:
10.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
• The input capture interrupt flag is set on every
edge, rising and falling.
• The Interrupt on Capture mode setting bits,
ICI<1:0>, are ignored, since every capture
generates an interrupt.
10.1.2
CAPTURE BUFFER OPERATION
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
• A Capture Overflow condition is not generated in
this mode.
• ICBFNE – Input Capture Buffer Not Empty
• ICOV – Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an Overflow condition will occur and the
ICOV bit will be set to a logic ‘1’. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured until all four events have been
read from the buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
DS70178C-page 98
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
10.2.2
INPUT CAPTURE IN CPU IDLE
MODE
10.2 Input Capture Operation During
Sleep and Idle Modes
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Inter-
rupt mode selected by the ICI<1:0> bits are applicable,
as well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU Sleep or
Idle mode when a capture event occurs, if ICM<2:0> =
111and the interrupt enable bit is asserted. The same
wake-up can generate an interrupt, if the conditions for
processing the interrupt have been satisfied. The
wake-up feature is useful as a method of adding extra
external pin interrupts.
If the input capture module is defined as ICM<2:0> =
111in CPU Idle mode, the input capture pin will serve
only as an external interrupt pin.
10.3 Input Capture Interrupts
10.2.1
INPUT CAPTURE IN CPU SLEEP
MODE
The input capture channels have the ability to generate
an interrupt, based upon the selected number of cap-
ture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).
CPU Sleep mode allows input capture module opera-
tion with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx STATUS register.
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111), in order for
the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
are not applicable in this mode.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 99
TABLE 10-1: INPUT CAPTURE REGISTER MAP
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Input 1 Capture Register
ICTMR
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
IC1BUF
IC1CON
Legend:
Note:
0140
0142
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
—
—
ICSIDL
—
—
—
—
—
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
u= uninitialized bit
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
The key operational features of the Output Compare
module include:
11.0 OUTPUT COMPARE MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
This section describes the Output Compare module
and associated operational modes. The features pro-
vided by this module are useful in applications requiring
operational modes such as:
These operating modes are determined by setting
the appropriate bits in the 16-bit OCxCON SFR (where
x = 1 and 2).
• Generation of Variable Width Output Pulses
• Power Factor Correction
OCxRS and OCxR in the figure represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
Figure 11-1 depicts a block diagram of the Output
Compare module.
FIGURE 11-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
S
R
Q
OCx
Output Enable
3
OCM<2:0>
Mode Select
OCFLTA
Comparator
OCTSEL
1
1
0
0
From General Pupose
Timer Module
T3P3_MATCH
TMR3<15:0>
T2P2_MATCH
TMR2<15:0
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 and 2.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 101
dsPIC30F1010/202X
11.3.2
CONTINUOUS PULSE MODE
11.1 Timer2 and Timer3 Selection Mode
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
Each output compare channel can select between one
of two 16-bit timers: Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the Output Compare module.
• Determine instruction cycle time TCY.
• Calculate desired pulse value based on TCY.
• Calculate timer to start pulse width from timer start
value of 0x0000.
11.2 Simple Output Compare Match
Mode
• Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2) compare
registers, respectively.
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
• Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 101.
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
• Enable timer, TON (TxCON<15>) = 1.
11.4 Simple PWM Mode
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config-
ured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the Main latch
(read-only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
11.3 Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config-
ured for one of two Dual Output Compare modes,
which are:
1. Set the PWM period by writing to the appropriate
period register.
2. Set the PWM duty cycle by writing to the OCxRS
register.
• Single Output Pulse mode
• Continuous Output Pulse mode
3. Configure the output compare module for PWM
operation.
11.3.1
SINGLE PULSE MODE
4. Set the TMRx prescale value and enable the
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming the timer is off):
Timer, TON (TxCON<15>) = 1.
• Determine instruction cycle time TCY.
• Calculate desired pulse width value based on TCY.
• Calculate time to start pulse from timer start value
of 0x0000.
• Write pulse width start and stop times into OCxR
and OCxRS compare registers (x denotes
channel 1, 2).
• Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 100.
• Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
DS70178C-page 102
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
11.4.1
PWM PERIOD
11.5 Output Compare Operation During
CPU Sleep Mode
The PWM period is specified by writing to the PRx reg-
ister. The PWM period can be calculated using
Equation 11-1.
When the CPU enters the Sleep mode, all internal
clocks are stopped. Therefore, when the CPU enters
the Sleep state, the output compare channel will drive
the pin to the active state that was observed prior to
entering the CPU Sleep state.
EQUATION 11-1: PWM PERIOD
PWM period = [(PRx) + 1] • 4 • TOSC •
(TMRx prescale value)
For example, if the pin was high when the CPU
entered the Sleep state, the pin will remain high. Like-
wise, if the pin was low when the CPU entered the
Sleep state, the pin will remain low. In either case, the
output compare module will resume operation when
the device wakes up.
PWM frequency is defined as 1/[PWM period].
When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
• TMRx is cleared.
11.6 Output Compare Operation During
CPU Idle Mode
• The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
The output compare channel will operate during the
CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at
logic ‘0’ and the selected time base (Timer2 or Timer3)
is enabled and the TSIDL bit of the selected timer is
set to logic ‘0’.
• The PWM duty cycle is latched from OCxRS into
OCxR.
• The corresponding timer interrupt flag is set.
See Figure 11-1 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
11.4.2
PWM WITH FAULT PROTECTION
INPUT PIN
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
Fault protection is enabled via the OCFLTA pin. If the a
logic ‘0’ is detected on the OCFLTA pin, the output pins
are placed in a high-impedance state. The state
remains until:
•
the external Fault condition has been removed
and
•
the PWM mode is reenabled by writing to the
appropriate control bits
As a result of the Fault condition, the OCxIF interrupt is
asserted, and an interrupt will be generated, if enabled.
Upon detection of the Fault condition, the OCFLTx bit
in the OCxCON register is asserted high. This bit is a
read-only bit and will be cleared once the external Fault
condition has been removed, and the PWM mode is
reenabled by writing the appropriate mode bits,
OCM<2:0> in the OCxCON register.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 103
dsPIC30F1010/202X
FIGURE 11-1:
PWM OUTPUT TIMING
Period
Duty Cycle
TMR3 = PR3
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
OCxR = OCxRS
TMR3 = Duty Cycle (OCxR)
TMR3 = Duty Cycle (OCxR)
11.7 Output Compare Interrupts
The output compare channels have the ability to gener-
ate an interrupt on a compare match, for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
STATUS register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 STATUS register, and must be
cleared in software. The interrupt is enabled via the
respective timer interrupt enable bit (T2IE or T3IE),
located in the IEC0 Control register. The output com-
pare interrupt flag is never set during the PWM mode of
operation.
DS70178C-page 104
Preliminary
© 2006 Microchip Technology Inc.
TABLE 11-1: OUTPUT COMPARE REGISTER MAP
SFR Name Addr. Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
Output Compare 1 Slave Register
Output Compare 1 Master Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
OC1CON
OC2RS
OC2R
—
—
—
—
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
Output Compare 2 Slave Register
Output Compare 2 Master Register
OC2CON
—
—
—
—
Note:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 106
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.2 Description
12.0 POWER SUPPLY PWM
The PWM module is designed for applications that
require (a) high resolution at high PWM frequencies,
(b) the ability to drive standard push-pull or half bridge
converters or (c) the ability to create multi-phase PWM
outputs.
The Power Supply PWM (PS PWM) module on the
dsPIC30F1010/202X device supports a wide variety of
PWM modes and output formats. This PWM module is
ideal for power conversion applications such as:
• DC/DC converters
Two common, medium-power converter topologies are
Push-Pull and Half-Bridge. These designs require the
PWM output signal to be switched between alternate
pins, as provided by the Push-Pull PWM mode.
• AC/DC power supplies
• Uninterruptable Power Supply (UPS)
12.1 Features Overview
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specifiable and changeable.
The PS PWM module incorporates these features:
• Four PWM generators with eight I/O
• Four Independent time bases
• Duty cycle resolution of 1.1 nsec @ 30 MIPS
• Dead-time resolution of 4.2 nsec @ 30 MIPS
• Phase-shift resolution of 4.2 nsec @ 30 MIPS
• Frequency resolution of 8.4 nsec @ 30 MIPS
• Supported PWM modes:
Multi-Phase PWM is often used to improve DC-DC
converter load transient response, and reduce the size
of output filter capacitors and inductors. Multiple DC/
DC converters are often operated in parallel but phase
shifted in time. A single PWM output operating at 250
KHz has a period of 4 µsec. But an array of four PWM
channels, staggered by 1 µsec each, yields an effective
switching frequency of 1 MHz. Multi-phase PWM appli-
cations typically use a fixed-phase relationship.
- Standard Edge-Aligned PWM
- Complementary PWM
- Push-Pull PWM
Variable Phase PWM is useful in Zero Voltage Transi-
tion (ZVT) power converters. Here the PWM duty cycle
is always 50%, and the power flow is controlled by
varying the relative phase shift between the two PWM
generators.
- Multi-Phase PWM
- Variable Phase PWM
- Fixed Off-Time PWM
- Current Reset PWM
- Current-Limit PWM
- Independent Time Base PWM
• On-the-Fly changes to:
Note: The PLL must be enabled for the PS PWM
module to function. This is achieved by using the
FNOSC<1:0> bits in the FOSCSEL Configuration
register.
- PWM frequency
- PWM duty cycle
- PWM phase shift
• Output override control
• Independent current-limit and Fault inputs
• Special event comparator for scheduling other
peripheral events
• Each PWM generator has comparator for
triggering ADC conversions.
Figure 12-1 conceptualizes the PWM module in a sim-
plified block diagram. Figure 12-2 illustrates how the
module hardware is partitioned for each PWM output
pair for the Complementary PWM mode. Each func-
tional unit of the PWM module is discussed in
subsequent sections.
The PWM module contains four PWM generators. The
module has eight PWM output pins: PWM1H, PWM1L,
PWM2H, PWM2L, PWM3H, PWM3L, PWM4H and
PWM4L. For complementary outputs, these eight I/O
pins are grouped into H/L pairs.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 107
dsPIC30F1010/202X
FIGURE 12-1:
SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF POWER SUPPLY PWM
PWMCONx
LEBCONx
Pin and mode control
Control for blanking external input signals
ADC Trigger Control
Dead-time Control
TRGCONx
ALTDTRx, DTRx
PTCON
PWM enable and mode control
MDC
Master Duty Cycle Reg
PDC1
MUX
Latch
PWM GEN #1
PWM1H
PWM1L
Channel 1
Dead-time Generator
Comparator
Timer
Phase
PDC2
MUX
Latch
PWM GEN #2
PWM2H
PWM2L
Channel 2
Dead-time Generator
Comparator
Timer
Phase
PDC3
MUX
Latch
PWM GEN #3
PWM3H
PWM3L
Channel 3
Dead-time Generator
Comparator
Timer
Phase
PDC4
MUX
Latch
PWM GEN #4
PWM4H
PWM4L
Channel 4
Dead-time Generator
Comparator
Timer
Timer Period
Phase
Fault Control
Logic
SFLTX
IFLTX
Master Time Base
PTPER
External Time Base
SYNCO
SYNCI
PTMR
Synchronization
Special Event
Trigger
Special Event
Postscaler
Comparator
Special event
SEVTCMP
IOCONx
comparison value
Pin override control
Fault mode and pin control
FLTCONx
DS70178C-page 108
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 12-2:
PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE
Phase Offset
TMR < PDC
Dead
Time
Logic
PWM
M
U
X
PWMXH
PWMXL
Timer/Counter
Override
Logic
Duty Cycle Comparator
M
U
X
Channel override values
PWM Duty Cycle Register
Fault Override Values
Fault Active
Fault Pin Assignment Logic
Fault Pin
12.3 Control Registers
The following registers control the operation of the
Power Supply PWM Module.
• PTCON: PWM Time Base Control Register
• PTPER: Primary Time Base Register
• SEVTCMP: PWM Special Event Compare Regis-
ter
• MDC: PWM Master Duty Cycle Register
• PWMCONx: PWM Control Register
• PDCx: PWM Generator Duty Cycle Register
• PHASEx: PWM Phase-Shift Register
(PWM Period Register when module is
configured for individual period mode)
• DTRx: PWM Dead-Time Register
• ALTDTRx: PWM Alternate Dead-Time Register
• TRGCONx: PWM TRIGGER Control Register
• IOCONx: PWM I/O Control Register
• FCLCONx: PWM Fault Current-Limit Control
Register
• TRIGx: PWM Trigger Compare Value Register
• LEBCONx: Leading Edge Blanking Control Register
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 109
dsPIC30F1010/202X
REGISTER 12-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
U-0
—
R/W-0
R/W-0
R/W-0
SEIEN
R/W-0
EIPU
R/W-0
R/W-0
PTSIDL
SESTAT
SYNCPOL SYNCOEN
bit 8
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
SYNCEN
SYNCSRC<2:0>
SEVTPS<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1= PWM time base halts in CPU Idle mode
0= PWM time base runs in CPU Idle mode
bit 12
bit 11
bit 10
bit 9
SESTAT: Special Event Interrupt Status bit
1= Special Event Interrupt is pending
0= Special Event Interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1= Special Event Interrupt is enabled
0= Special Event Interrupt is disabled
EIPU: Enable Immediate Period Updates bit
1= Active Period register is updated immediately
0= Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input Polarity bit
1= SYNCIN polarity is inverted (low active)
0= SYNCIN is high active
bit 8
SYNCOEN: Primary Time Base Sync Enable bit
1= SYNCO output is enabled
0= SYNCO output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit
1= External synchronization of primary time base is enabled
0= External synchronization of primary time base is disabled
bit 6-4
SYNCSRC<2:0>: Sync Source Selection bits
000= SYNCI
001= Reserved
.
.
111= Reserved
bit 3-0
SEVTPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
| |
| |
1111= 1:16 Postscale
DS70178C-page 110
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 12-2: PTPER: PRIMARY TIME BASE REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
PTPER <15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
PTPER <7:3>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Primary Time Base (PTMR) Period Value bits
Unimplemented: Read as ‘0’
REGISTER 12-3: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP <15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
SEVTCMP <7:3>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Special Event Compare Count Value bits
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 111
dsPIC30F1010/202X
REGISTER 12-4: MDC: PWM MASTER DUTY CYCLE REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
MDC<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
MDC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(1)
bit 15-0
Master PWM Duty Cycle Value bits
Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
REGISTER 12-5: PWMCONx: PWM CONTROL REGISTER
HS/HC-0
FLTSTAT
HS/HC-0
CLSTAT
HS/HC-0
R/W-0
R/W-0
CLIEN
R/W-0
R/W-0
ITB
R/W-0
MDCS
TRGSTAT
FLTIEN
TRGIEN
bit 15
bit 8
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
IUE
DTC<1:0>
XPRES
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
FLTSTAT: Fault Interrupt Status
1= Fault Interrupt is pending
0= No Fault Interrupt is pending
This bit is cleared by setting FLTIEN = 0.
Note:
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
CLSTAT: Current-Limit Interrupt Status bit
1= Current-limit interrupt is pending
0= No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
Note:
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
bit 13
bit 12
TRGSTAT: Trigger Interrupt Status bit
1= Trigger interrupt is pending
0= No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1= Fault interrupt enabled
0= Fault interrupt disabled and FLTSTAT bit is cleared
DS70178C-page 112
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 12-5: PWMCONx: PWM CONTROL REGISTER (CONTINUED)
bit 11
bit 10
bit 9
CLIEN: Current-Limit Interrupt Enable bit
1= Current-limit interrupt enabled
0= Current-limit interrupt disabled and CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1= A trigger event generates an interrupt request
0= Trigger event interrupts are disabled and TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit
1= Phasex register provides time base period for this PWM generator
0= Primary time base provides timing for this PWM generator
bit 8
MDCS: Master Duty Cycle Register Select bit
1= MDC register provides duty cycle information for this PWM generator
0= DCx register provides duty cycle information for this PWM generator
bit 7-6
DTC<1:0>: Dead-time Control bits
00= Positive dead time actively applied for all output modes
01= Negative dead time actively applied for all output modes
10= Dead-time function is disabled
11= Reserved
bit 5-2
bit 1
Unimplemented: Read as ‘0’
XPRES: External PWM Reset Control bit
1= Current-limit source resets time base for this PWM generator if it is in independent time base
mode
0= External pins do not affect PWM time base
bit 0
IUE: Immediate Update Enable bit
1= Updates to the active PDC registers are immediate
0= Updates to the active PDC registers are synchronized to the PWM time base
REGISTER 12-6: PDCx: PWM GENERATOR DUTY CYCLE REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PDCx<15:8>
R/W-0
R/W-0
R/W-0
PDCx<7:0>
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(1)
bit 15-0
PWM Generator #x Duty Cycle Value bits
Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 113
dsPIC30F1010/202X
REGISTER 12-7: PHASEx: PWM PHASE-SHIFT REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
PHASEx<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
PHASEx<7:2>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1-0
PHASEx<15:2>: PWM Phase-Shift Value or Independent Time Base Period for this PWM Generator bits
Note: If used as an independent time base, bits <3:2> are not used.
Unimplemented: Read as ‘0’
REGISTER 12-8: DTRx: PWM DEAD-TIME REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx<13:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
DTRx<7:2>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-2
bit 1-0
Unimplemented: Read as ‘0’
DTRx<13:2>: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit bits
Unimplemented: Read as ‘0’
DS70178C-page 114
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 12-9: ALTDTRx: PWM ALTERNATE DEAD-TIME REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
ALTDTRx<13:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
ALTDTR <7:2>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-2
Unimplemented: Read as ‘0’
ALTDTRx<13:2>: Unsigned 12-bit Dead-Time Value bits for PWMx Dead-Time Unit
bits
bit 1-0
Unimplemented: Read as ‘0’
REGISTER 12-10: TRGCONx: PWM TRIGGER CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
TRGDIV<2:0>
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
TRGSTRT<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
TRGDIV<2:0>: Trigger Output Divider bits
000= Trigger output for every trigger event
001= Trigger output for every 2nd trigger event
010= Trigger output for every 3rd trigger event
011= Trigger output for every 4th trigger event
100= Trigger output for every 5th trigger event
101= Trigger output for every 6th trigger event
110= Trigger output for every 7th trigger event
111= Trigger output for every 8th trigger event
bit 12-6
bit 5-0
Unimplemented: Read as ‘0’
TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
This value specifies the ROLL counter value needed for a match that will then enable the trigger
postscaler logic to begin counting trigger events.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 115
dsPIC30F1010/202X
REGISTER 12-11: IOCONx: PWM I/O CONTROL REGISTER
R/W-0
PENH
R/W-0
PENL
R/W-0
POLH
R/W-0
POLL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMOD<1:0>
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
OVRDAT<1:0>
FLTDAT<1:0>
CLDAT<1:0>
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PENH: PWMH Output Pin Ownership bit
1= PWM module controls PWMxH pin
0= GPIO module controls PWMxH pin
bit 14
PENL: PWML Output Pin Ownership bit
1= PWM module controls PWMxL pin
0= GPIO module controls PWMxL pin
bit 13
POLH: PWMH Output Pin Polarity bit
1= PWMxH pin is low active
0= PWMxH pin is high active
bit 12
POLL: PWML Output Pin Polarity bit
1= PWMxL pin is low active
0= PWMxL pin is high active
bit 11-10
PMOD<1:0>: PWM #x I/O Pin Mode bits
00= PWM I/O pin pair is in the Complementary Output mode
01= PWM I/O pin pair is in the Independent Output mode
10= PWM I/O pin pair is in the Push-Pull Output mode
11= Reserved
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1= OVRDAT<1> provides data for output on PWMxH pin
0= PWM generator provides data for PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1= OVRDAT<0> provides data for output on PWMxL pin
0= PWM generator provides data for PWMxL pin
bit 7-6
bit 5-4
bit 3-2
OVRDAT<1:0>: Data for PWMxH,L Pins if Override is Enabled bits
If OVERENH = 1then OVRDAT<1> provides data for PWMxH
If OVERENL = 1then OVRDAT<0> provides data for PWMxL
FLTDAT<1:0>: Data for PWMxH,L Pins if FLTMODE is Enabled bits
If Fault active, then FLTDAT<1> provides data for PWMxH
If Fault active, then FLTDAT<0> provides data for PWMxL
CLDAT<1:0>: Data for PWMxH,L Pins if CLMODE is Enabled bits
If current limit active, then CLDAT<1> provides data for PWMxH
If current limit active, then CLDAT<0> provides data for PWMxL
bit 1
bit 0
Unimplemented: Read as ‘0’
OSYNC: Output Override Synchronization bit
1= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0= Output overrides via the OVDDAT<1:0> bits occur on next clock boundary
DS70178C-page 116
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 12-12: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLSRC<3:0>
CLPOL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLMODE
FLTSRC<3:0>
FLTPOL
FLTMOD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-9
Unimplemented: Read as ‘0’
CLSRC<3:0>: Current-Limit Control Signal Source Select for PWM #X Generator bits
0000= Analog Comparator #1
0001= Analog Comparator #2
0010= Analog Comparator #3
0011= Analog Comparator #4
0100= Reserved
0101= Reserved
0110= Reserved
0111= Reserved
1000= Shared Fault #1 (SFLT1)
1001= Shared Fault #2 (SFLT2)
1020= Shared Fault #3 (SFLT3)
1011= Shared Fault #4 (SFLT4)
1100= Reserved
1101= Independent Fault #2 (IFLT2)
1110= Reserved
1111= Independent Fault #4 (IFLT4)
bit 8
bit 7
CLPOL: Current-Limit Polarity for PWM Generator #X bit
1= The selected current-limit source is low active
0= The selected current-limit source is high active
CLMODE: Current-Limit Mode Enable for PWM Generator #X bit
1= Current-limit function is enabled
0= Current-limit function is disabled
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 117
dsPIC30F1010/202X
REGISTER 12-12: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED)
bit 6-3
FLTSRC<3:0>: Fault Control Signal Source Select for PWM Generator #X bits
0000= Analog Comparator #1
0001= Analog Comparator #2
0010= Analog Comparator #3
0011= Analog Comparator #4
0100= Reserved
0101= Reserved
0110= Reserved
0111= Reserved
1000= Shared Fault #1 (SFLT1)
1001= Shared Fault #2 (SFLT2)
1020= Shared Fault #3 (SFLT3)
1011= Shared Fault #4 (SFLT4)
1100= Reserved
1101= Independent Fault #2 (IFLT2)
1110= Reserved
1111= Independent Fault #4 (IFLT4)
bit 2
FLTPOL: Fault Polarity for PWM Generator #X bit
1= The selected Fault source is low active
0= The selected Fault source is high active
bit 1-0
FLTMOD<1:0>: Fault Mode for PWM Generator #x bits
00= The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
01= The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
10= Reserved
11= Fault input is disabled
DS70178C-page 118
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 12-13: TRIGx: PWM TRIGGER COMPARE VALUE REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
TRGCMP<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
TRGCMP<7:3>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 15-3
TRGCMP<15:3>: Trigger Control Value bits
Register contains the compare value for PWMx time base for generating a trigger to the ADC module
for initiating a sample and conversion process, or generating a trigger interrupt.
bit 2-0
Unimplemented: Read as ‘0’
Note 1: The minimum usable value for this register is 0x0008
A value of 0x0000 does not produce a trigger.
If the TRIGx value is being calculated based on duty cycle value, you must ensure that a minimum TRIGx
value is written into the register at all times.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 119
dsPIC30F1010/202X
REGISTER 12-14: LEBCONx: LEADING EDGE BLANKING CONTROL REGISTER
R/W-0
PHR
R/W-0
PHF
R/W-0
PLR
R/W-0
PLF
R/W-0
R/W-0
R/W-0
R/W-0
FLTLEBEN
CLLEBEN
LEB<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
LEB<7:3>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
PHR: PWMH Rising Edge Trigger Enable bit
1= Rising edge of PWMH will trigger LEB counter
0= LEB ignores rising edge of PWMH
PHL: PWMH Falling Edge Trigger Enable bit
1= Falling edge of PWMH will trigger LEB counter
0= LEB ignores falling edge of PWMH
PLR: PWML Rising Edge Trigger Enable bit
1= Rising edge of PWML will trigger LEB counter
0= LEB ignores rising edge of PWML
PLF: PWML Falling Edge Trigger Enable bit
1= Falling edge of PWML will trigger LEB counter
0= LEB ignores falling edge of PWML
FLTLEBEN: Fault Input Leading Edge Blanking Enable bit
1= Leading Edge Blanking is applied to selected Fault Input
0= Leading Edge Blanking is not applied to selected Fault Input
CLLEBEN: Current-Limit Leading Edge Blanking Enable bit
1= Leading Edge Blanking is applied to selected Current-Limit Input
0= Leading Edge Blanking is not applied to selected Current-Limit Input
bit 9-3
bit 2-0
LEB: Leading Edge Blanking for Current-Limit and Fault Inputs bits
Value is 8 nsec increments
Unimplemented: Read as ‘0’
DS70178C-page 120
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.4.2
COMPLEMENTARY PWM MODE
12.4 Module Functionality
Complementary PWM is generated in a manner similar
to standard Edge-Aligned PWM. Complementary mode
provides a second PWM output signal on the PWML
pin that is the complement of the primary PWM signal
(PWMH). Complementary mode PWM is shown in
Figure 12-4.
The PS PWM module is a very high-speed design that
provides capabilities not found in other PWM genera-
tors. The module supports these PWM modes:
• Standard Edge-Aligned PWM mode
• Complementary PWM mode
• Push-Pull PWM mode
FIGURE 12-4:
COMPLEMENTARY PWM
• Multi-Phase PWM mode
• Variable Phase PWM mode
• Current-Limit PWM mode
Timer Resets
Duty Cycle Match
• Constant Off-time PWM mode
• Current Reset PWM mode
• Independent Time Base PWM mode
Period
Value
Timer
Value
12.4.1
STANDARD EDGE-ALIGNED PWM
MODE
Standard Edge-Aligned mode (Figure 12-3) is the basic
PWM mode used by many power converter topologies
such as “Buck”, “Boost” and “Forward”. To create the
edge-aligned PWM, a timer/counter circuit counts
upward from zero to a specified maximum value for the
Period. Another register contains the value for Duty
Cycle, which is constantly compared to the timer
(Period) value. While the timer/counter value is less
than or equal to the duty cycle value, the PWM output
signal is asserted. When the timer value exceeds the
duty cycle value, the PWM signal is deasserted. When
the timer is greater than the period value, the timer is
reset, and the process repeats.
0
PWMH
Duty Cycle
Period
PWML
(Period)-(Duty Cycle)
12.4.3
PUSH-PULL PWM MODE
The Push-Pull mode shown in Figure 12-5 is a version
of the standard Edge-Aligned PWM mode where the
active PWM signal is alternately outputted on one of
two PWM pins. There is no complementary PWM out-
put available. This mode is useful in transformer-based
power converters. Transformer-based circuits must
avoid any direct currents that will cause their cores to
saturate. The Push-Pull mode ensures that the duty
cycle of the two phases is identical, thus yielding a net
DC bias of zero.
FIGURE 12-3:
EDGE-ALIGNED PWM
Timer Resets
Duty Cycle Match
Period
Value
Timer
Value
FIGURE 12-5:
PUSH-PULL PWM
Timer Resets
Duty Cycle Match
0
PWMH
Period
Value
Duty Cycle
Period
Timer
Value
0
PWMH
Duty Cycle
Period
PWML
Duty Cycle
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 121
dsPIC30F1010/202X
12.4.4
MULTI-PHASE PWM MODE
12.4.6
CURRENT-LIMIT PWM MODE
Multi-Phase PWM, as shown in Figure 12-6, uses
phase-shift values in the Phase registers to shift the
PWM outputs relative to the primary time base.
Because the phase-shift values are added to the pri-
mary time base, the phase-shifted outputs occur earlier
than a PWM channel that specifies zero phase shift. In
Multi-Phase mode, the specified phase shift is fixed by
the application’s design.
Figure 12-8 shows Cycle-by-Cycle Current-Limit
mode. This mode truncates the asserted PWM signal
when the selected external Fault signal is asserted.
The PWM output values are specified by the Fault
override bits (FLTDAT<1:0>) in the IOCONx register.
The override output remains in effect until the begin-
ning of the next PWM cycle. This mode is sometimes
used in Power Factor Correction (PFC) circuits where
the inductor current controls the PWM on time. This is
a constant frequency PWM mode.
FIGURE 12-6:
MULTI-PHASE PWM
PTMR=0
FIGURE 12-8:
CYCLE-BY-CYCLE
CURRENT-LIMIT PWM
MODE
PWM1H
Duty Cycle
Phase2
FLTx Negates PWM
FLTx Negates PWM
PWM2H
Duty Cycle
Period
Value
Phase3
Duty
Cycle
PWM3H
Duty Cycle
Timer
Value
Phase4
Duty Cycle
0
PWM4H
PWMH
Programmed
Duty Cycle
Programmed
Duty Cycle
Period
PWMH
Actual
Duty Cycle
Actual
Duty Cycle
12.4.5
VARIABLE PHASE PWM MODE
Figure 12-7 shows the waveforms for Variable Phase-
Shift PWM. Power-converter circuits constantly change
the phase shift among PWM channels as a means to
control the flow of power, in contrast to most PWM cir-
cuits that vary the duty cycle of PWM signals to control
power flow. Often, in variable phase applications, the
PWM duty cycle is maintained at 50%. The phase-shift
value should be updated when the PWM signal is not
asserted. Complementary outputs are available in Vari-
able Phase-Shift mode.
FIGURE 12-7:
VARIABLE PHASE PWM
Duty Cycle
PWM1H
PWM2H
Duty Cycle
Phase2 (new value)
Phase2 (old value)
Duty Cycle
Duty Cycle
Period
DS70178C-page 122
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Typically, in the converter application, an energy stor-
age inductor is charged with current while the PWM
signal is asserted, and the inductor current is dis-
charged by the load when the PWM signal is deas-
serted. In this application of current reset PWM, an
external current measurement circuit determines when
the inductor is discharged, and then generates a signal
that the PWM module uses to reset the time base
counter. In Current Reset mode, complementary
outputs are available.
12.4.7
CONSTANT OFF-TIME PWM
Constant Off-Time mode is shown in Figure 12-9.
Constant Off-Time PWM is a variable-frequency mode
where the actual PWM period is less than or equal to
the specified period value. The PWM time base is
externally reset some time after the PWM signal duty
cycle value has been reached, and the PWM signal has
been deasserted. This mode is implemented by
enabling the On-Time PWM mode (Current Reset
mode) and using the complementary output.
12.4.9
INDEPENDENT TIME BASE PWM
FIGURE 12-9:
CONSTANT OFF-TIME
PWM
Independent Time Base PWM, as shown in
Figure 12-11, is often used when the dsPIC DSC is
controlling different power converter subcircuits such
as the Power Factor Correction circuit, which may use
100 kHz PWM, and the full-bridge forward converter
section may use 250 kHz PWM.
Programmed Period
External Timer Reset
External Timer Reset
Period
Value
Timer
FIGURE 12-11:
INDEPENDENT TIME
BASE PWM
Value
Duty Cycle
0
PWML
PWM1H
PWM2H
Period 1
Duty Cycle
Duty Cycle
Duty Cycle
Actual Period
Period 2
Note: Duty Cycle represents off time
PWM3H
PWM4H
Duty Cycle
Period 3
12.4.8
CURRENT RESET PWM MODE
Current Reset PWM is shown in Figure 12-10. Current
Reset PWM uses a Variable-Frequency mode where
the actual PWM period is less than or equal to the spec-
ified period value. The PWM time base is externally
reset some time after the PWM signal duty cycle value
has been reached and the PWM signal has been deas-
serted. Current Reset PWM is a constant on-time PWM
mode.
Duty Cycle
Period 4
Note:
With independent time bases,
PWM signals are no longer
phase related to each other.
FIGURE 12-10:
CURRENT RESET PWM
Programmed Period
External Timer Reset
External Timer Reset
Period
Value
Timer
Value
0
PWMH
Duty Cycle
Actual Period
Duty Cycle
Programmed Period
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 123
dsPIC30F1010/202X
12.5 Primary PWM Time Base
12.6 Primary PWM Time Base Roll
Counter
There is a Primary Time Base (PTMR) counter for the
entire PWM module, In addition, each PWM generator
has an individual time base counter.
The primary time base has an additional 6-bit counter
that counts the period matches of the primary time
base. This ROLL counter enables the PWM genera-
tors to stagger their trigger events in time to the ADC
module. This counter is not accessible for reading.
Each PWM generator has six bits (TRGSTRT<5:0>) in
the TRGCONx registers. These bits are used to spec-
ify the start enable for each TRIGx postscaler con-
trolled by the TRGDIV<2:0> bits in the TRGCONx
registers.
The PTMR determines when the individual time base
counters are to update their duty cycle and phase-shift
registers. The master time base is also responsible for
generating the Special Event Triggers and timer-based
interrupts. Figure 12-12 shows a block diagram of the
primary time base logic.
FIGURE 12-12:
PTMR BLOCK DIAGRAM
The TRGDIV bits specify how frequently a trigger
pulse is generated, and the ROLL bits specify when
the sequence begins. Once the TRIG postscaler is
enabled, the ROLL bits and the TRGSTRT bits have
no further effect until the PWM module is disabled and
then reenabled.
PERIOD
13
Equality Comparator
>
The purpose of the ROLL counter and the TRGSTRT
bits is to allow the user to spread the system work load
over a series of PWM cycles.
PR_MATCH
Clk
13
An additional use of the ROLL counter is to allow the
internal FRC oscillator to be varied on a PWM cycle
basis to reduce peak EMI emissions generated by
switching transistors in the power conversion
application.
Reset
PTMR
The ROLL counter is cleared when the PWM module
is disabled (PTEN = 0), and the TRIGx postscalers are
disabled, requiring a new ROLL versus TRGSTRT
match to begin counting again.
The primary time base may be reset by an external
signal specified via the SYNCSRC<2:0> bits in the
PTCON register. The external reset feature is enabled
via the SYNCEN bit in the PTCON register. The pri-
mary time base reset feature supports synchronization
of the primary time base with another SMPS dsPIC
DSC device or other circuitry in the user’s application.
The primary time base logic also provides an output
signal when a period match occurs that can be used to
synchronize an external device such as another
SMPS dsPIC DSC.
12.7 Individual PWM Time Base(s)
Each PWM generator also has its own PWM time
base. Figure 12-13 shows a block diagram for the indi-
vidual time base circuits. With a time base per PWM
generator, the PWM module can generate PWM out-
puts that are phase shifted relative to each other, or
totally independent of each other. The individual PWM
timers (TMRx) provide the time base values that are
compared to the duty cycle registers to create the
PWM signals. The user may initialize these individual
time base counters before or during operation via the
phase-shift registers. The primary (PTMR) and the
individual timers (TMRx) are not user readable.
12.5.1
PTMR SYNCHRONIZATION
Because absolute synchronization is not possible, the
user should program the time base period of the sec-
ondary (slave) device to be slightly larger than the pri-
mary device time base to ensure that the two time
bases will reset at the same time.
DS70178C-page 124
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 12-13:
TMRx BLOCK DIAGRAM
12.9 PWM Frequency and Duty Cycle
Resolution
15
3
15
3
The PWM Duty cycle resolution is 1.05 nsec per LSB
@ 30 MIPS. The PWM period resolution is 8.4 nsec @
30 MIPS. Table 12-1 shows the duty cycle resolution
versus PWM frequencies for 30 MIPS execution speed.
PTPER
PHASEx
0
1
MUX
ITBx
TABLE 12-1: AVAILABLE PWM
FREQUENCIES AND
13
RESOLUTIONS @ 30 MIPS
Comparator
13
>
PWM Duty
MIPS
Cycle
PWM Frequency
Resolution
15
3
30
30
30
30
30
30
30
30
30
16 bits
15 bits
14 bits
13 bits
12 bits
11 bits
10 bits
9 bits
14.6 KHz
29.3 KHz
58.6 KHz
117.2 KHz
234.4 KHz
468.9 KHz
937.9 KHz
1.87 MHz
3.75 MHz
Reset
Clk
TMRx
Normally, the Primary Time Base (PTMR) provides
synchronization control to the individual timer/counters
so they count in lock-step unison.
8 bits
If the PWM phase-shift feature is used, then the PTMR
provides the synchronization signal to each individual
timer/counter that causes them to reinitialize with their
individual phase-shift values.
TABLE 12-2: AVAILABLE PWM
FREQUENCIES AND
RESOLUTIONS @ 20 MIPS
If a PWM generator is operating in Independent Time
Base mode, the individual timer/counters count
upward until their count values match the value stored
in their phase registers, then they reset and the cycle
repeats.
PWM Duty
MIPS
Cycle
PWM Frequency
Resolution
20
20
20
20
14 bits
12 bits
10 bits
8 bits
39 KHz
156 KHz
624 KHz
2.5 MHz
The primary time base and the individual time bases
are implemented as 13-bit counters. The timers/
counters are clocked at 120 MHz @ 30 MIPS, which
provides a frequency resolution of 8.4 nsec.
All of the timer/counters are enabled/disabled by set-
ting/clearing the PTEN bit in the PTCON SFR. The
timers are cleared when the PTEN bit is cleared in
software.
Notice the reduction in available resolution for a given
PWM frequency is due to the reduced clock rate and
the fact that the LSB of duty cycle resolution is derived
from a fixed-delay element. At operating frequencies
below 30 MIPS, the contribution of the fixed-delay
element to the output resolution becomes less than
1 LSB.
The PTPER register sets the counting period for
PTMR. The user must write a 13-bit value to
PTPER<15:3>. When the value in PTMR<15:3>
matches the value in PTPER<15:3>, the primary time
base is reset to ‘0’, and the individual time base
counters are reinitialized to their phase values (except
if in Independent Time Base mode).
For frequency resonant mode power conversion appli-
cations, it is desirable to know the available PWM fre-
quency resolution. The available frequency resolution
varies with the PWM frequency. The PWM time base
clocks at 120 MHz @ 30 MIPS. The following equation
provides the frequency resolution versus PWM period:
12.8 PWM Period
Frequency Resolution = 120 MHz/(Period)
where Period = PTPER<15:3>
PTPER holds the 13-bit value that specifies the count-
ing period for the primary PWM time base. The timer
period can be updated at any time by the user. The
PWM period can be determined from the following
formula:
Period Duration = (PTPER + 1)/120 MHz @ 30 MIPS
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 125
dsPIC30F1010/202X
12.10 PWM Duty Cycle Comparison
Units
12.11 Complementary PWM Outputs
Complementary PWM Output mode provides true and
inverted PWM outputs on the pair of PWM output pins.
The complement PWM signal is generated by inverting
the active PWM signal. Complementary outputs are
normally available with all of the different PWM modes
except Push-Pull PWM and Independent PWM Output
modes.
The PWM module has two to four PWM duty cycle
generators. Three to five 16-bit special function regis-
ters are used to specify duty cycle values for the PWM
module:
• MDC (Master Duty Cycle)
• PDC1, ..., PDC4 (Duty Cycle)
Each PWM generator has its own duty cycle register
(PDCx), and there is a Master Duty Cycle (MDC) reg-
ister. The MDC register can be used instead of individ-
ual duty cycle registers. The MDC register enables
multiple PWM generators to share a common duty
cycle register to reduce the CPU overhead required in
updating multiple duty cycle registers. Multi-phase
power converters are an application where the use of
the MDC feature saves valuable processor time.
12.12 Independent PWM Outputs
Independent PWM Output mode simply replicates the
active PWM output signal on both output pins
associated with a PWM generator.
12.13 Duty Cycle Limits
The duty cycle generators are limited to the range of
allowable values. A value of 0x0008 is the minimum
duty cycle value that will produce an output pulse. This
value represents 8.4 nsec at 30 MIPS. This minimum
range limitation is not a problem in a real world appli-
cation because of the slew-rate limitation of the PWM
output buffers, external FET drivers, and the power
transistors. The application control loop requires larger
duty cycle values to achieve minimum transistor on
times.
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The PWM time base counters are 13 bits wide
and increment twice per instruction cycle. The PWM
output is asserted when the timer/counter is less than
or equal to the Most Significant 13 bits of the duty
cycle register value. Each of the duty cycle registers
allows a 16-bit duty cycle to be specified. The Least
Significant 3 bits of the duty cycle registers are sent to
additional logic for further adjustment of the PWM
signal edge.
The maximum duty cycle value is also limited to
0xFFEF.
The user is responsible for limiting the duty cycle
values to the allowable range of 0x0008 to 0xFFEF.
Figure 12-14 is a block diagram of a duty cycle
comparison unit.
Note:
A duty cycle of 0x0000 will produce a zero
PWM output, and a 0xFFFF duty cycle
value will produce a high on the PWM
output.
FIGURE 12-14:
DUTY CYCLE
COMPARISON
15
0
Clk
TMRx
PWMx signal
Compare Logic
MUX
<=
MDCx select
0
1
15
0
PDCx Register
15
0
MDC Register
The duty cycle values can be updated at any time. The
updated duty cycle values optionally can be held until
the next rollover of the primary time base before
becoming active.
DS70178C-page 126
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 12-16:
DEAD-TIME CONTROL
UNITS BLOCK DIAGRAM
12.14 Dead-Time Generation
Dead time refers to a programmable period of time,
specified by the Dead-Time Register (DTR) or the ALT-
DTR register, which prevent a PWM output from being
asserted until its complementary PWM signal has been
deasserted for the specified time. Figure 12-15 shows
the insertion of dead time in a complementary pair of
PWM outputs. Figure 12-16 shows the four dead-time
units that each have their own dead-time value.
DTR1
ALTDR1
PWM1H
PWM1L
Dead-Time Unit
#1
PWM1 in
DTR2
ALTDTR2
PWM2H
PWM2L
Dead-Time Unit
#2
PWM2 in
Dead-time generation can be provided when any of the
PWM I/O pin pairs are operating in any output mode.
DTR3
PWM3H
PWM3L
Dead-Time Unit
#3
ALTDTR3
Many power-converter circuits require dead time
because the power transistors cannot switch instanta-
neously. To prevent current “shoot-through” some
amount of time must be provided between the turn-off
event of one PWM output in a complementary pair and
the turn-on event of the other transistor.
PWM3 in
DTR4
ALTDTR4
PWM4H
PWM4L
Dead-Time Unit
#4
PWM4 in
The PWM module can also provide negative dead time.
Negative dead time is the forced overlap of the PWMH
and PWML signals. There are certain converter tech-
niques that require a limited amount of
12.14.1 DEAD-TIME GENERATORS
current “shoot-through”.
Each complementary output pair for the PWM module
has 12-bit down counters to produce the dead-time
insertion. Each dead-time unit has a rising and falling
edge detector connected to the duty cycle comparison
output.
The dead-time feature can be disabled for each PWM
generator. The dead-time functionality is controlled by
the DTC<1:0> bits in the PWMCON register.
Note:
If zero dead time is required, the dead time
feature must be explicitly disabled in the
DTC<1:0> bit in the PWMCON register
Depending on whether the edge is rising or falling, one
of the transitions on the complementary outputs is
delayed until the associated timer counts down to
zero. A timing diagram indicating the dead-time inser-
tion for one pair of PWM outputs is shown in
Figure 12-15.
FIGURE 12-15:
DEAD-TIME INSERTION
FOR COMPLEMENTARY
PWM
tda
tda
12.14.2 ALTERNATE DEAD-TIME SOURCE
The alternate dead time refers to the dead time speci-
fied by the ALTDTR register that is applied to the com-
plementary PWM output. Figure 12-17 shows a dual
dead-time insertion using the ALTDTR register.
PWM
Generator #1
Output
PWM1H
PWM1L
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 127
dsPIC30F1010/202X
FIGURE 12-17:
DUAL DEAD-TIME
WAVEFORMS
12.14.3 DEAD-TIME RANGES
The amount of dead time provided by each dead-time
unit is selected by specifying a 12-bit unsigned value in
the DTRx registers. The 12-bit dead-time counters
clock at four times the instruction execution rate. The
Least Significant one bit of the dead-time value are
processed by the Fine Adjust PWM module.
No dead time
PWMH
PWML
Table 12-3 shows example dead-time ranges as a
function of the device operating frequency.
Positive dead time
PWMH
TABLE 12-3: EXAMPLE DEAD-TIME
RANGES
PWML
MIPS
Resolution
Dead-Time Range
Negative dead time
PWMH
30
20
4.16 ns
6.25 ns
0-17.03 µsec
0-25.59 µsec
PWML
DTRx
12.14.4 DEAD-TIME INSERTION TIMING
ALTDTRx
Figure 12-18 shows how the dead-time insertion for
complementary signals is accomplished.
12.14.5 DEAD-TIME DISTORTION
For small PWM duty cycles, the ratio of dead time to the
active PWM time may become large. In this case, the
inserted dead time introduces distortion into wave-
forms produced by the PWM module. The user can
ensure that dead-time distortion is minimized by keep-
ing the PWM duty cycle at least three times larger than
the dead time.
A similar effect occurs for duty cycles at or near 100%.
The maximum duty cycle used in the application should
be chosen such that the minimum inactive time of the
signal is at least three times larger than the dead time.
FIGURE 12-18:
DEAD-TIME INSERTION (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED)
CLOCK
1
2
3
4
6
PTMR
9
0
5
7
8
1
DEAD-TIME VALUE
<10:4>
4
DUTY CYCLE REG
<15:4>
RAW PWMH
RAW PWML
PWMH OUTPUT
PWML OUTPUT
DS70178C-page 128
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.17.1 SPECIAL EVENT TRIGGER ENABLE
12.15 Configuring a PWM Channel
The PWM module always produces Special Event Trig-
ger pulses. This signal can optionally be used by the
ADC module.
Example 12-1 is a code example for configuring PWM
channel 1 to operate in complementary mode at 400
kHz, with a dead-time value of approximately 64 nsec.
It is assumed that the dsPIC30F1010/202X is operating
on the internal fast RC oscillator with PLL in the high-
frequency range (14.55 MHz input to the PLL,
12.17.2 SPECIAL EVENT TRIGGER
POSTSCALER
assuming industrial temperature rated part).
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVTPS<3:0> control bits in
the PTCON register.
12.16 Speed Limits of PWM Output
Circuitry
The special event output postscaler is cleared on the
following events:
The PWM output I/O buffers, and any attached circuits
such as FET drivers and power FETs, have limited
slew-rate capability. For very small PWM duty cycles,
the PWM output signal is low-pass filtered; no pulse
makes it through all of the circuitry.
• Any write to the SEVTCMP register.
• Any device reset.
12.18 Individual PWM Triggers
A similar effect happens for duty cycle values near
100%. Before 100% duty cycle is reached, the output
PWM signal appears to saturate at 100%.
The PWM module also features an additional ADC trig-
ger output for each PWM generator. This feature is very
useful when the PWM generators are operating in
Independent Time Base mode.
Users need to take such behavior into account in their
applications. In normal power conversion applications,
duty cycle values near 0% or 100% are avoided
because to reach these values is to operate in a Dis-
continuous mode or a Saturated mode where the
control loop may be non functional.
A block diagram of a trigger circuit is shown in
Figure 12-19. The user specifies a match value in the
TRIGx register. When the local time base counter value
matches the TRIGx value, an ADC trigger signal is
generated.
12.17 PWM Special Event Trigger
Trigger signals are always generated regardless of the
TRIGx value as long as the TRIGx value is less than or
equal to the PWM period value for the local time base.
If the TRGIEN bit is set in the PWMCONx register, then
an interrupt request is generated.
The PWM module has a Special Event Trigger that
allows A/D conversions to be synchronized to the PWM
time base. The A/D sampling and conversion time can
be programmed to occur at any point within the PWM
period. The Special Event Trigger allows the user to
minimize the delay between the time when A/D conver-
sion results are acquired and the time when the duty
cycle value is updated.
The individual trigger outputs can be divided per the
TRGDIV<2:0> bits in the TRGCONx registers, which
allows the trigger signals to the ADC to be generated
once for every 1, 2, 3 ..., 7 trigger events.
The Special Event Trigger is based on the primary
PWM time base.
The trigger divider allows the user to tailor the ADC
sample rates to the requirements of the control loop.
The PWM Special Event Trigger has one register
(SEVTCMP) and four additional control bits
(SEVTPS<3:0> in PTCON) to control its operation. The
PTMR value that causes a Special Event Trigger is
loaded into the SEVTCMP register.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 129
dsPIC30F1010/202X
EXAMPLE 12-1:
.
CODE EXAMPLE FOR CONFIGURING PWM CHANNEL 1
Note:
This code example does not illustrate configuration of various fault modes for the PWM module.
It is intended as a quick start guide for setting up the PWM Module.
mov #0x0400, w0
mov w0, PTCON
; PWM Module is disabled, continue operation in
; idle mode, special event interrupt disabled,
; immediate period updates enabled, no external
; synchronization
; Set the PWM Period
mov #0x094D, w0
mov w0, PTPER
; Select period to be approximately 2.5usec
; PLL Frequency is ~480MHz. This equates to a
; clocke period of 2.1nsec. The PWM period and
; duty cycle registers are triggered on both +ve
; and -ve edges of the PLL clock. Therefore,
; one count of the PTPER and PDCx registers
; equals 1.05nsec.
; So, to achieve a PWM period of 2.5usec, we
; choose PTPER = 0x094D
mov #0x0000, w0
mov w0, PHASE1
; no phase shift for this PWM Channel
; This register is used for generating variable
; phase PWM
; Select individual Duty Cycle Control
mov #0x0001, w0
mov w0, PWMCON1
; Fault interrupt disabled, Current Limit
; interrupt disabled, trigger interrupt,
; disabled, Primary time base provides timing,
; DC1 provides duty cycle information, positive
; dead time applied, no external PWM reset,
; Enable immediate duty cycle updates
; Code for PWM Current Limit and Fault Inputs
mov #0x0003, w0
mov w0, FCLCON1
; Disable current limit and fault inputs
; Code for PWM Output Control
mov #0xC000, w0
mov w0, IOCON1
; PWM1H and PWM1L is controlled by PWM module
; Output polarities are active high, override
; disabled
; Duty Cycle Setting
mov #0x04A6, w0
mov w0, PDC1
; To achieve a duty cycle of 50%, we choose
; the PDC1 value = 0.5*(PWM Period)
; The ON time for the PWM = 1.25usec
; The Duty Cycle Register will provide
; positive duty cycle to the PWMxH outputs
; when output polarities are active high
; (see IOCON1 register)
; Dead Time Setting
mov #0x0040, w0
mov w0, DTR1
; Dead time ~ 67nsec
; Hex(40) = decimal(64)
; So, Dead time = 64*1.05nsec = 67.2nsec
; Note that the last 2 bits are unimplemented,
; therefore the dead time register can achieve a
; a resolution of about 4nsec.
mov w0, ALTDTR1
bset PTCON, #15
; Load the same value in ALTDTR1 register
; turn ON PWM module
DS70178C-page 130
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 12-19:
PWM TRIGGER BLOCK DIAGRAM
PDI
15
3
Clk
PTMRx
Pulse
PWMx Trigger
Compare Logic
=
Divider
15
3
TRIGx Write
TRIGx Register
PDI
TRGDIV<2:0>
12.19 PWM Interrupts
12.21 PWM Fault and Current-Limit Pins
The PWM module can generate interrupts based on
internal timing or based on external signals via the cur-
rent-limit and Fault inputs. The primary time base mod-
ule can generate an interrupt request when a special
event occurs. Each PWM generator module has its
own interrupt request signal to the interrupt controller.
The interrupt for each PWM generator is an OR of the
trigger event interrupt request, the current-limit input
event or the Fault input event for that module.
The PWM module supports multiple Fault pins for each
PWM generator. These pins are labeled SFLTx
(Shared Fault) or IFLTx (Individual Fault). The Shared
Fault pins can be seen and used by any of the PWM
generators. The Individual Fault pins are usable by
specific PWM generators.
Each PWM generator can have one pin for use as a
cycle-by-cycle current limit, and another pin for use as
either a cycle-by-cycle current limit or a latching current
Fault disable function.
There are four interrupt request signals to the interrupt
control plus another interrupt request from the primary
time base on special events.
12.22 Leading Edge Blanking
Each PWM generator supports “Leading Edge Blank-
ing” of the current-limit and Fault inputs via the
LEB<9:3> bits and the PHR, PHF, PLR, PLF, FLTLE-
BEN and CLLEBEN bits in the LEBCONx registers.
The purpose of leading edge blanking is to mask the
transients that occur on the application printed circuit
board when the power transistors are turned on and off.
12.20 PWM Time Base Interrupts
The PWM module can generate interrupts based on
the primary time base and/or the individual time bases
in each PWM generator. The interrupt timing is speci-
fied by the Special Event Comparison Register
(SEVTCMP) for the primary time base, and by the
TRIGx registers for the individual time bases in the
PWM generator modules.
The LEB bits support the blanking (ignoring) of the cur-
rent-limit and Fault inputs for a period of 0 to 1024 nsec
in 8.4 nsec increments following any specified rising or
falling edge of the coarse PWMH and PWML signals.
The coarse PWM signal (signal prior to the PWM fine
tuning) has resolution of 8.4 nsec (at 30 MIPS), which
is the same time resolution as the LEB counters.
The primary time base special event interrupt is
enabled via the SEIEN bit in the PTCON register. The
individual time base interrupts generated by the trigger
logic in each PWM generator are controlled by the
TRGIEN bit in the PWMCONx registers.
The PHR, PHF, PLR and PLF bits select which edge of
the PWMH and PLWL signals will start the blanking
timer. If a new selected edge triggers the LEB timer
while the timer is still active from a previously selected
PWM edge, the timer reinitializes and continues
counting.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 131
dsPIC30F1010/202X
The FLTLEBEN and CLLEBEN bits enable the applica-
tion of the blanking period to the selected Fault and
current-limit inputs.
The Fault pins actually serve two different purposes.
First is generation of Fault overrides for the PWM out-
puts. The action of overriding the PWM outputs and
generating an interrupt is performed asynchronously in
hardware so that Fault events can be managed quickly.
Second, the Fault pin inputs can be used to implement
either Current-Limit PWM mode or Current Force
mode.
The
LEB
duration
@
30
MIPS
=
(LEB<9:3> + 1)/120 MHz.
There is a blanking period offset of 8.4 nsec. Therefore
a LEB<9:3> value of zero yields an effective blanking
period of 8.4 ns.
PWM Fault condition states are available on the FLT-
STAT bit in the PWMCONx registers. The FLTSTAT bits
displays the Fault IRQ latch if the FIE bit is set. If Fault
interrupts are not enabled, then the FSTATx bits display
the status of the selected FLTx input in positive logic
format. When the Fault input pins are not used in asso-
ciation with a PWM generator, these pins become
general purpose I/O or interrupt input pins.
If a current-limit or Fault inputs are active at the end of
the previous PWM cycle, and they are still active at the
start of the new PWM cycle and the dead time is non-
zero, the Fault or current limit will be detected
regardless of the LEB counter configuration.
12.23 PWM Fault Pins
The FLTx pins are normally active high. The FLTPOL
bit in FCLCONx registers, if set to one, invert the
selected Fault input signal so that it is an active low.
Each PWM generator can select its own Fault input
source from a selection of up to 12 Fault/current-limit
pins. In the FCLCONx registers, each PWM generator
has control bits that specify the source for its Fault input
signal. These are the FLTSRC<3:0> bits. Additionally,
each PWM generator has a FLTIEN bit in the PWM-
CONx register that enables the generation of Fault
interrupt requests. Each PWM generator has an asso-
ciated Fault Polarity bit (FLTPOL) in the FCLCONx reg-
ister that selects the active level of the selected Fault
input.
The Fault pins are also readable through the PORT I/O
logic when the PWM module is enabled. This allows
the user to poll the state of the Fault pins in software.
Figure 12-20 is a diagram of the PWM Fault control
logic.
FIGURE 12-20:
PWM FAULT CONTROL LOGIC DIAGRAM
PWMxH,L
2
Signals
0
1
PWMx
Generator
2
PWMxH,L
MUX
2
Analog Comparator
Module
FLTDAT<1:0>
FLTSTAT
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
‘0000’
‘0001’
‘0010’
‘0011’
CMP1x
CMP2x
CMP3x
CMP4x
PTMR
Fault
Mode
Selection
Logic
Shared Fault # 1
Shared Fault # 2
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
MUX
‘1000’
‘1001’
Shared Fault # 3
‘1010’
‘1011’
‘1101’
Shared Fault # 4
FLTMOD<1:0>
Independent Fault # 2
Independent Fault # 4
FLTMOD<1:0> = 00– FLTSTAT signal is latched until Reset in software
FLTMOD<1:0> = 01– FLTSTAT signal is Reset by PTMR every PWM cycle
FLTMOD<1:0> = 11– FLTSTAT signal is disabled
‘1111’
FLTSRC<3:0>
DS70178C-page 132
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.23.1 FAULT INTERRUPTS
12.23.4 FAULT ENTRY
The FLTIENx bits in the PWMCONx registers deter-
mine if an interrupt will be generated when the FLTx
input is asserted high. The FLTMOD bits in the
FCLCONx register determines how the PWM genera-
tor and its outputs respond to the selected Fault input
pin. The FLTDAT<1:0> bits in the IOCONx registers
supply the data values to be assigned to the PWMxH,L
pins in the advent of a Fault.
The response of the PWM pins to the Fault input pins
is always asynchronous with respect to the device
clock signals. That is, the PWM outputs should imme-
diately go to the states defined in the FLTDAT register
bits without any interaction from the dsPIC DSC device
or software.
Refer to Section 12.28 “Fault and Current-Limit
Override Issues with Dead-Time Logic” for informa-
tion regarding data sensitivity and behavior in response
to current-limit or Fault events.
The Fault pin logic can operate separately from the
PWM logic as an external interrupt pin. If the faults are
disabled from affecting the PWM generators in the
FCLCONx register, then the Fault pin can be used as a
general purpose interrupt pin.
12.23.5 FAULT EXIT
The restoration of the PWM signals after a Fault condi-
tion has ended must occur at a PWM cycle boundary to
ensure proper synchronization of PWM signal edges
and manual signal overrides. The next PWM cycle
begins when the PTMRx value is zero.
12.23.2 FAULT STATES
The IOCONx register has two bits that determine the
state of each PWMx I/O pin when they are overridden
by a Fault input. When these bits are cleared, the
PWM I/O pin is driven to the inactive state. If the bit is
set, the PWM I/O pin is driven to the active state. The
active and inactive states are referenced to the polarity
defined for each PWM I/O pin (HPOL and LPOL
polarity control bits).
12.23.6 FAULT EXIT WITH PTMR DISABLED
There is a special case for exiting a Fault condition
when the PWM time base is disabled (PTEN = 0).
When a Fault input is programmed for Cycle-by-Cycle
mode, the PWM outputs are immediately restored to
normal operation when the Fault input pin is deas-
serted. The PWM outputs should return to their default
programmed values. (The time base is disabled, so
there is no reason to wait for the beginning of the next
PWM cycle.)
12.23.3 FAULT INPUT MODES
The Fault input pin has two modes of operation:
• Latched Mode: When the Fault pin is asserted,
the PWM outputs go to the states defined in the
FLTDAT bits in the IOCONx registers. The PWM
outputs remain in this state until the Fault pin is
deasserted AND the corresponding interrupt flag
has been cleared in software. When both of these
actions have occurred, the PWM outputs return to
normal operation at the beginning of the next
PWM cycle boundary. If the FLTSTAT bit is
cleared before the Fault condition ends, the PWM
module waits until the Fault pin is no longer
asserted to restore the outputs. Software can
clear the FLTSTAT bit by writing a zero to the
FLTIEN bit.
When a Fault input is programmed for Latched mode,
the PWM outputs are restored immediately when the
Fault input pin is deasserted AND the FSTAT bit has
been cleared in software.
12.23.7 FAULT PIN SOFTWARE CONTROL
The Fault pin can be controlled manually in software.
Since the Fault input is shared with a PORT I/O pin, the
PORT pin can be configured as an output by clearing
the corresponding TRIS bit. When the PORT bit for the
pin is cleared, the Fault input will be activated.
Note:
The user should use caution when control-
ling the Fault inputs in software. If the
TRIS bit for the Fault pin is cleared and the
PORT bit is set high, then the Fault input
cannot be driven externally.
• Cycle-by-Cycle Mode: When the Fault input pin
is asserted, the PWM outputs remain in the deas-
serted PWM state for as long as the Fault pin is
asserted. For Complementary Output modes,
PWMH is low (deasserted) and PWML is high
(asserted). After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle.
The operating mode for each Fault input pin is selected
using the FLTMOD<1:0> control bits in the FCLCONx
register.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 133
dsPIC30F1010/202X
12.24.1 CURRENT-LIMIT INTERRUPTS
12.24 PWM Current-Limit Pins
The state of the PWM current-limit conditions is avail-
able on the CLSTAT bits in the PWMCONx registers.
The CLSTAT bits display the current-limit IRQ flag if
the CLIEN bit is set. If current-limit interrupts are not
enabled, then the CLSTAT bits display the status of the
selected current-limit inputs in positive logic format.
When the current-limit input pin associated with a
PWM generator is not used, these pins become
general purpose I/O or interrupt input pins.
Each PWM generator can select its own current-limit
input source from up to12 current-limit/Fault pins. In the
FCLCONx registers, each PWM generator has control
bits (CLSRC<3:0>) that specify the source for its cur-
rent-limit input signal. Additionally, each PWM genera-
tor has a CLIEN bit in the PWMCONx register that
enables the generation of current-limit interrupt
requests. Each PWM generator has an associated
Fault polarity bit CLPOL in the FCLCONx register.
Figure 12-21 is a diagram of the PWM Current-Limit
control logic.
The current-limit pins are normally active high. If set to
‘1’, the CLPOL bit in FCLCONx registers inverts the
selected current-limit input signal to active high.
The current-limit pins actually serve two different pur-
poses. They can be used to implement either Current-
Limit PWM mode or Current Reset PWM mode.
The interrupts generated by the selected current-limit
signals are combined to create a single interrupt
request signal to the interrupt controller, which has its
own interrupt vector, interrupt flag bit, interrupt enable
bit and interrupt priority bits associated with it.
1. When the CLIEN bit is set in the PWMCONx
registers, the PWMxH,L outputs are forced to
the values specified by the CLDAT<1:0> bits in
the IOCONx register, if the selected current-limit
input signal is asserted.
The Fault pins are also readable through the PORT I/O
logic when the PWM module is enabled. This allows
the user to poll the state of the Fault pins in software.
2. When the CLMOD bit is zero AND the XPRES
bit in the PWMCONx register is ‘01’ AND the
PWM generator is in Independent Time Base
mode (ITB
= 1), then a current-limit signal
resets the time base for the affected PWM gen-
erator. This behavior is called Current Reset
mode, which is used in some Power Factor
Correction (PFC) applications.
FIGURE 12-21:
PWM CURRENT-LIMIT CONTROL LOGIC DIAGRAM
PWMxH,L
Signals
2
0
1
PWMx
Generator
PWM Period
Reset
2
PWMxH,L
MUX
EN
2
CLDAT<1:0>
CLMOD
EN
XPRES
CLSTAT
Analog Comparator
Module
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
CMP1x
CMP2x
CMP3x
CMP4x
‘0000’
‘0001’
‘0010’
‘0011’
Shared Fault # 1
Shared Fault # 2
MUX
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
‘1000’
‘1001’
‘1010’
‘1011’
‘1101’
‘1111’
Shared Fault # 3
Shared Fault # 4
Independent Fault # 2
Independent Fault # 4
CLSRC<3:0>
DS70178C-page 134
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.25 Simultaneous PWM Faults and
Current Limits
12.29 Asserting Outputs via Current
Limit
The current-limit override function, if enabled and
active, forces the PWMxH,L pins to the values speci-
fied by the CLDAT<1:0> bits in the IOCONx registers
UNLESS the Fault function is enabled and active. If the
selected Fault input is active, the PWMxH,L outputs
assume the values specified by the FLTDAT<1:0> bits
in the IOCONx registers.
It is possible to use the CLDAT bits to assert the
PWMxH,L outputs in response to a current-limit event.
Such behavior could be used as a current “force” fea-
ture in response to an external current or voltage mea-
surement that indicates a sudden sharp increase in the
load on the power-converter output. Forcing the PWM
“ON” could be viewed as a “Feed-Forward” term that
allows quick system response to unexpected load
increases without waiting for the digital control loop to
respond.
12.26 PWM Fault and Current-Limit TRG
Outputs To ADC
The Fault and current-limit source selection fields in the
FCLCONx registers (FLTSRC<3:0> and CLSRC<3:0>)
control multiplexers in each PWM generator module.
The control multiplexers select the desired Fault and
current-limit signals for their respective modules. The
selected Fault and current-limit signals are also avail-
able to the ADC module as trigger signals that initiate
ADC sampling and conversion operations.
12.30 PWM Immediate Update
For high-performance PWM control-loop applications,
the user may want to force the duty cycle updates to
occur immediately. Setting the IUE bit in the
PWMCONx register enables this feature.
In a closed-loop control application, any delay between
the sensing of a system’s state and the subsequent
outputting of PWM control signals that drive the appli-
cation reduces the loop stability. Setting the IUE bit
minimizes the delay between writing the duty cycle reg-
isters and the response of the PWM generators to that
change.
12.27 PWM Output Override Priority
If the PWM module is enabled, the priority of PWMx pin
ownership is:
1. PWM Generator (lowest priority)
2. Output Override
3. Current-Limit Override
4. Fault Override
5. PENx (GPIO/PWM) ownership (highest priority)
12.31 PWM Output Override
All control bits associated with the PWM output
override function are contained in the IOCONx register.
If the PENH, PENL bits are set, the PWM module
controls the PWMx output pins.
If the PWM module is disabled, the GPIO module
controls the PWMx pins.
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states
independent of the duty cycle comparison units.
12.28 Fault and Current-Limit Override
Issues with Dead-Time Logic
The OVRDAT<1:0> bits in the IOCONx register deter-
mine the state of the PWM I/O pins when a particular
output is overridden via the OVRENH,L bits.
The PWMxH and PWMxL outputs are immediately
driven low (deasserted) as specified by the
CLDAT<1:0> and the FLTDAT<1:0> bits when a
current-limit or a Fault event occurs.
The OVRENH, OVRENL bits are active high control
bits. When the OVREN bits are set, the corresponding
OVRDAT bit overrides the PWM output from the PWM
generator.
The override data is gated with the PWM signals going
into the dead-time logic block, and at the output of the
PWM module, just ahead of the PWM pin output
buffers.
12.31.1 COMPLEMENTARY OUTPUT MODE
Many applications require fast response to current
shutdown for accurate current control and/or to limit
circuitry damage to Fault currents.
When the PWM is in Complementary Output mode, the
dead-time generator is still active with overrides. The
output overrides and Fault overrides generate control
signals used by the dead-time unit to set the outputs as
requested, including dead time.
Some applications will set the complementary
PWM outputs high in synchronous rectifier
designs when
a Fault or current-limit event
Dead-time insertion can be performed when PWM
channels are overridden manually.
occurs. If the CLDAT or FLTDAT bits are set to ‘1’,
and their associated event occurs, then these
asserted outputs will be delayed by clocked logic
in the dead-time circuitry.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 135
dsPIC30F1010/202X
12.31.2 OVERRIDE SYNCHRONIZATION
12.32.3 CPU IDLE MODE
If the OSYNC bit in the IOCONx register is set, the out-
put overrides performed via the OVRENH,L and the
OVDDAT<1:0> bits are synchronized to the PWM time
base. Synchronous output overrides occur when the
time base is zero.
The dsPIC30F202X module has a PTSIDL control bit in
the PTCON register. This bit determines if the PWM
module continues to operate or stops when the device
enters Idle mode. Stopped Idle mode functions like
Sleep mode, and Fault pins are asynchronously active.
If PTEN = 0, meaning the timer is not running, writes to
• PTSIDL = 1(Stop module when in Idle mode)
IOCON take effect on the next TCY boundary.
• PTSIDL = 0(Don't stop module when in Idle
mode)
12.32 Functional Exceptions
It is recommended that the user disable the PWM out-
puts prior to entering Idle mode. If the PWM module is
controlling a power-conversion application, the action
of putting the device into Idle will cause any control
loops to be disabled, and most applications will likely
experience issues unless they are explicitly designed
to operate in an Open-Loop mode.
12.32.1 POWER RESET CONDITIONS
All registers associated with the PWM module are reset
to the states given in Table 12-4 upon a Power-on
Reset. On a device reset, the PWM output pins are
tri-stated.
12.32.2 SLEEP MODE
12.33 Register Bit Alignment
The selected Fault input pin has the ability to wake the
CPU from Sleep mode. The PWM module should gen-
erate an asynchronous interrupt if any of the selected
Fault pins is driven low while in Sleep.
Table 12-4 on page 142 shows the registers for the PS
PWM module. All time-based data for the module is
always bit-aligned with respect to time. For example: bit
3 in the period register, the duty cycle registers, the
dead-time registers, the trigger registers and the phase
registers always represents a value of 8.4 nsec,
assuming 30 MIPS operation. Unused portions of reg-
isters always read as zeros.
It is recommended that the user disable the PWM out-
puts prior to entering Sleep mode. If the PWM module
is controlling a power conversion application, the action
of putting the device into Sleep will cause any control
loops to be disabled, and most applications will likely
experience issues unless they are explicitly designed
to operate in an Open-Loop mode.
The use of data alignment makes it easier to write soft-
ware because it eliminates the need to shift time values
to fit into registers. It also eases the computation and
understanding of time allotment within a PWM cycle.
DS70178C-page 136
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.34.2 APPLICATION OF COMPLEMENTARY
PWM MODE
12.34 APPLICATION EXAMPLES:
12.34.1 STANDARD PWM MODE
Complementary mode PWM is often used in circuits
that use two transistors in a bridge configuration where
transformers are not used, as shown in Figure 12-23.
If transformers are used, then some means must be
provided to ensure that no net DC currents flow
through the transformer to prevent core saturation.
In standard PWM mode, the PWM output is typically
connected to a single transistor, which charges an
inductor, as shown in Figure 12-22. Buck and Boost
converters typically use standard PWM mode.
FIGURE 12-22:
APPLICATIONS OF
STANDARD PWM MODE
FIGURE 12-23:
APPLICATIONS OF
COMPLEMENTARY PWM
MODE
Period
Dead Time
Dead Time
Dead Time
PWM1H
PWM1H
PWM1L
T
ON
TOFF
Inductor charges during TON
ON versus Period controls power flow
T
Period
+VIN
Series Resonant Half Bridge Converter
Buck Converter
L1
VOUT
+VIN
PWM1H
PWM1L
CR
LR
T1
VOUT
+
+
PWM1H
Synchronous Buck Converter
Boost Converter
L1
VOUT
+VIN
L1
VOUT
+VIN
+
+
PWM1H
PWM1L
PWM1H
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 137
dsPIC30F1010/202X
12.34.3 APPLICATION OF PUSH-PULL PWM
MODE
12.34.4 APPLICATION OF MULTI-PHASE PWM
MODE
Push-Pull PWM mode is typically used in transformer
coupled circuits to ensure that no net DC currents flow
through the transformer. Push-Pull mode ensures that
the same duty cycle PWM pulse is applied to the
transformer windings in alternate directions, as shown
in Figure 12-24.
Multi-Phase PWM mode is often used in DC/DC con-
verters that must handle very fast load current tran-
sients and fit into tight spaces. A multi-phase converter
is essentially a parallel array of buck converters that
are operated slightly out of phase of each other, as
shown in Figure 12-25. The multiple phases create an
effective switching speed equal to the sum of the indi-
vidual converters. If a single phase is operating with a
333 KHz PWM frequency, then the effective switching
frequency for the circuit is 1 MHz. This high switching
frequency greatly reduces output capacitor size
requirements and improves load transient response.
FIGURE 12-24:
APPLICATIONS OF PUSH-
PULL PWM MODE
TON
TOFF
PWM1H
PWM1L
TON
FIGURE 12-25:
APPLICATIONS OF MULTI-
PHASE PWM MODE
TOFF
Period
Period
PWM1H
PWM1L
Dead Time
PWM1H
Dead Time
Dead Time
PWM2H
PWM2L
+VIN
Half Bridge Converter
L1
+
VOUT
T1
PWM3H
PWM3L
+
+
PWM1L
Multiphase DC/DC
Converter
+VIN
PWM1H
PWM2H
PWM3H
PWM1H
Push-Pull Buck Converter
L1
VOUT
VOUT
T1
L1
+
+VIN
L2
+
L3
PWM1L
PWM1L
PWM1L
PWM1L
+VIN
Full Bridge Converter
PWH1H
PWH1L
PWH1L
T1
L1
VOUT
+
PWH1H
DS70178C-page 138
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
12.34.5 APPLICATION OF VARIABLE PHASE PWM
MODE
12.34.6 APPLICATION OF CURRENT RESET PWM
MODE
Variable phase PWM is used in newer power conver-
sion topologies that are designed to reduce switching
losses. In standard PWM methods, any time a transis-
tor switches between the conducting state and the
nonconducting state (and vice versa), the transistor is
exposed to the full current and voltage condition for
the period of time it takes the transistor to turn on or
off. The power loss (V * I * Tsw * FPWM) becomes
appreciable at high frequencies. The Zero Voltage
Switching (ZVS) and Zero Current Switching (ZVC) cir-
cuit topologies attempt to use quasi-resonant tech-
niques to shift either the voltage or current waveforms
relative to each other. This action either makes the
voltage or the current zero at the time the transistor
turns on or off. If either the current or the voltage is
zero, then there is no switching loss generated.
In Current Reset PWM mode, the PWM frequency var-
ies with the load current. This mode is different than
most PWM modes because the user sets the maxi-
mum PWM period, but an external circuit measures
the inductor current. When the inductor current falls
below a specified value, the external current compara-
tor circuit generates a signal that resets the PWM time
base counter. The user specifies a PWM “on” time,
and then some time after the PWM signal becomes
inactive, the inductor current falls below a specified
value and the PWM counter is reset earlier than the
programmed PWM period. This mode is sometimes
called Constant On-Time.
This mode should not be confused with cycle-by-cycle
current-limiting PWM, where the PWM is asserted, an
external circuit generates a current Fault and the PWM
signal is turned off before its programmed duty cycle
would normally turn it off. In this mode, shown in
Figure 12-27, the PWM frequency is fixed per the time
base period.
In variable phase PWM modes, the duty cycle is fixed
at 50%, and the power flow is controlled by varying the
phase relationship between the PWM channels, as
shown in Figure 12-26.
FIGURE 12-26:
APPLICATION OF
VARIABLE PHASE PWM
MODE
FIGURE 12-27:
APPLICATION OF
CURRENT RESET PWM
MODE
PWM1H
PWM1L
Programmed Period
TOFF
PWM1H
TON
PWM2H
PWM2L
IL
PWM1H
Variable Phase Shift
Actual Period
External current comparator resets PWM counter
PWM cycle restarts early
+VIN
This is a variable frequency PWM mode
Full Bridge ZVT Converter
T1
PWM1H
L
D
VOUT
VOUT
IL
+
ACIN
+
+
COUT
CIN
PWM1H
PWM1H
PWM1H
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 139
dsPIC30F1010/202X
12.35.4 METHOD #4: FREQUENCY MODULATION
12.35 METHODS TO REDUCE EMI
This method varies the frequency at which the PWM
cycle is varied (dithered). The frequency modulation
process is similar (mathematically speaking) to Phase
Modulation when analyzed over a small time window.
The goal is to move the PWM edges around in time to
spread the EMI energy over a range of frequencies to
reduce the peak energy at any given frequency during
the EMI measurement process, which measures long
term averages.
The PWM module has the capability to phase modu-
late the PWM signals via the phase offset registers.
Phase modulation has the advantage that the software
is simpler and faster because multiple multiply opera-
tions (used for dithering frequency by scaling period
and duty cycles) are replaced with fewer additions or
simple updates of phase offset
The EMI measurement process integrates the EMI
energy into 9 kHz wide frequency bins. Assuming that
the carrier (PWM) frequency is 150 kHz, a 6% dither
will yield a 9 kHz wide dither.
12.35.1 METHOD #1: PROGRAMMABLE FRC
DITHER
values into the phase registers.
This method also has these advantages:
This method dithers all of the PWM outputs and the
system clock. The advantage of this method is that no
CPU resources are required. It is automatic once it is
setup. The user can periodically update these values
to simulate a more random frequency pattern.
1. Multi-phase and variable phase PWM modes
could still be created.
2. The PWM generators can still use the common
time base, which simplifies determining when a
“quiet time” is available for measuring current.
12.35.2 METHOD #2: SOFTWARE CONTROLLED
DITHER
This method has one disadvantage: the phase modu-
lation has to be at a relatively high update rate to
achieve usable frequency spreading.
This method uses software to dither individual PWM
channels by scaling the duty cycle and period. This
method consumes CPU resources:
12.35.5 INDEPENDENT PWM CHANNEL
DITHERING ISSUES:
Assume:
4 PWM channels updated @ 150 kHz rate:
600 kHz x (5 clocks (2 mul, 1 tblrdl, 1 mov))
= 3 MIPS additional work load
Issues for multi-phase or variable phase designs using
independent output dithering must consider these
issues:
1. The phases are no longer phase aligned.
12.35.3 METHOD #3: SOFTWARE SCALING OF
TIME BASE PERIOD
2. Control of current sharing among phases is
more difficult.
This method used software to scale just the time base
period. Assuming that the dither rate is relatively slow
(about 250 Hz), the application control loop should be
able to compensate for the changes in PWM period
and adjust the duty cycle accordingly.
DS70178C-page 140
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
The TRGDIV<2:0> bits in each TRGCONx register will
be set to ‘111’, which selects that every 8th trigger
comparison match will generate a trigger signal to the
ADC to capture data and begin a conversion process.
12.36 EXTERNAL SYNCHRONIZATION
FEATURES
In large power conversion systems, it is often desir-
able to be able to synchronize multiple power control-
lers to ensure that “beat frequencies” are not
generated within the system, or as a means to ensure
“quiet” periods during which current and voltage mea-
surements can be made.
If the stagger-in-time feature did not exist, all of the
requests from all of the PWM trigger registers might
occur at the same time. If this “pile-up” were to hap-
pen, some data sample might become stale (outdated)
by the time the data for all four channels can be
processed.
dsPIC30F202X devices (excluding 28-pin packages)
have input and/or output pins that provide the capabil-
ity to either synchronize the SMPS dsPIC DSC device
with an external device or have external devices syn-
chronized to the SMPS dsPIC DSC. These synchro-
nizing features are enabled via the SYNCIEN and
SYNCOEN bits in the PTCON control register in the
PWM module.
With the stagger-in-time feature, the trigger signals are
spaced out over time (during succeeding PWM peri-
ods) so that all of the data is processed in an orderly
manner.
The ROLL counter is a counter connected to the pri-
mary time base counter. The ROLL counter is incre-
mented each time the primary time base counter
reaches terminal count (period rollover).
The SYNCPOL bit in the PTCON register selects
whether the rising edge or the falling edge of the
SYNCI signal is the active edge. The SYNCPOL bit in
the PTCON register also selects whether the SYNCO
output pulse is low active or high active.
The stagger-in-time feature is controlled by the
TRGSTRT<5:0> bits in the TRGCONx registers. The
TRGSTRT<5:0> bits specify the count value of the
ROLL counter that must be matched before an individ-
ual trigger comparison module in each of the PWM
generators can begin to count the trigger comparison
events as specified by the TRGDIV<2:0> bits in the
PWMCONx registers.
The SYNCSRC<2:0> bits in the PTCON register
specify the source for the SYNCI signal.
If the SYNCI feature is enabled, the primary time base
counter is reset when an active SYNCI edge is
detected. If the SYNCO feature is enabled, an output
pulse is generated when the primary time base
counter rolls over at the end of a PWM cycle.
So, in our example with the four PWM generators, the
first PWM’s TRGSTRT<5:0> bits would be ‘000’, the
second PWM’s TRGSTRT bits would be set to ‘010’,
the third PWM’s TRGSTRT bits would be set to ‘100’
and the fourth PWM’s TRGSTRT bits would be set to
‘110’. Therefore, over a total of eight PWM cycles, the
four separate control loops could be run each with
their own 2-µsec time period.
The recommended SYNCI pulse width should be more
than 100 nsec. The expected SYNCO output pulse
width will be approximately 100 nsec.
When using the SYNCI feature, it is recommended
that the user program the period register with a period
value that is slightly longer than the expected period of
the external synchronization input signal. This pro-
vides protection in case the SYNCI signal is not
received due to noise or external component failure.
With a reasonable period value programmed into the
PTPER register, the local power conversion process
should remain operational even if the global
12.38 EXTERNAL TRIGGER BLANKING
Using the LEB<9:3> bits in the LEBCONx registers,
the PWM module has the capability to blank (ignore)
the external current and Fault inputs for a period of 0
to 1024 nsec. This feature is useful if power transistor
turn-on induced transients make current sensing
difficult at the start of a PWM cycle.
synchronization signal is not received.
12.37 CPU LOAD STAGGERING
The SMPS dsPIC DSC has the ability to stagger the
individual trigger comparison operations. This feature
helps to level the processor’s workload to minimize
situations where the processor is overloaded.
Assume a situation where there are four PWM chan-
nels controlling four independent voltage outputs.
Assume further that each PWM generator is operating
at 1000 kHz (1 µsec period) and each control loop is
operating at 125 kHz (8 µsec).
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 141
TABLE 12-4: POWER SUPPLY PWM REGISTER MAP
File Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PTCON
PTPER
MDC
0400
0402
0404
0406
PTEN
—
PTSIDL
SESTAT
SEIEN
EIPU
SYNCPOL SYNCOEN SYNCEN
SYNCSRC<2:0>
SEVTPS<3:0>
0000
FFF0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PTPER<15:3>
—
—
—
MDC<15:0>
MDCS
SEVTCMP
SEVTCMP<15:3>
—
—
—
XPRES
—
—
PWMCON1 0408 FLTSTAT CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
OVRENH
DTC<1:0>
OVRDAT<1:0>
CLMOD
—
—
—
IUE
IOCON1
FCLCON1
PDC1
040A
040C
040E
0410
0412
0414
0416
0418
041A
PENH
—
PENL
—
POLH
—
POLL
PMOD<1:0>
CLSRC<3:0>
OVRENL
CLPOL
FLTDAT<1:0>
FLTSRC<3:0>
CLDAT<1:0>
FLTPOL
OSYNC
FLTMOD<1:0>
PDC1<15:0>
PHASE1<15:2>
PHASE1
DTR1
—
—
—
—
—
—
—
—
—
—
—
—
DTR1<13:2>
ALTDTR1
TRIG1
ALTDTR1<13:2>
TRIG<15:3>
—
TRGSTRT<5:0>
—
TRGCON1
LEBCON1
TRGDIV<2:0>
PHF
—-
—-
FLTLEBEN CLLEBEN
CLIEN TRGIEN
PMOD<1:0>
CLSRC<3:0>
—-
—-
—-
—-
—-
PHR
PLR
PLF
LEB<9:3>
—
XPRES
—
—
PWMCON2 041C FLTSTAT CLSTAT TRGSTAT FLTIEN
ITB
MDCS
DTC<1:0>
OVRDAT<1:0>
CLMOD
—
—
—
—
IUE
IOCON2
FCLCON2
PDC2
041E
0420
0422
0424
0426
0428
042A
042C
042E
PENH
—
PENL
—
POLH
—
POLL
OVRENH
OVRENL
CLPOL
FLTDAT<1:0>
FLTSRC<3:0>
CLDAT<1:0>
OSYNC
FLTPOL
FLTMOD<1:0>
PDC2<15:0>
PHASE2<15:2>
PHASE2
DTR2
—
—
—
—
—
—
—
—
—
—
—
—
DTR2<13:2>
ALTDTR2
TRIG2
ALTDTR2<13:2>
TRIG<15:3>
—
TRGSTRT<5:0>
—
TRGCON2
LEBCON2
TRGDIV<2:0>
PHF
—-
—-
FLTLEBEN CLLEBEN
CLIEN TRGIEN
PMOD<1:0>
CLSRC<3:0>
—-
—-
—-
—-
—-
PHR
PLR
PLF
LEB<9:3>
—
XPRES
—
—
PWMCON3 0430 FLTSTAT CLSTAT TRGSTAT FLTIEN
ITB
MDCS
DTC<1:0>
OVRDAT<1:0>
CLMOD
—
—
—
—
IUE
IOCON3
FCLCON3
PDC3
0432
0434
0436
0438
043A
043C
043E
0440
0442
PENH
—
PENL
—
POLH
—
POLL
OVRENH
OVRENL
CLPOL
FLTDAT<1:0>
FLTSRC<3:0>
CLDAT<1:0>
OSYNC
FLTPOL
FLTMOD<1:0>
PDC3<15:0>
PHASE3<15:2>
PHASE3
DTR3
—
—
—
—
—
—
—
—
—
—
—
—
DTR3<13:2>
ALTDTR3
TRIG3
ALTDTR3<13:2>
TRIG<15:3>
—
TRGSTRT<5:0>
—
TRGCON3
LEBCON3
TRGDIV<2:0>
PHF
—-
—-
FLTLEBEN CLLEBEN
CLIEN TRGIEN
PMOD<1:0>
—-
—-
—-
—-
—-
PHR
PLR
PLF
LEB<9:3>
—
XPRES
—
—
PWMCON4 0444 FLTSTAT CLSTAT TRGSTAT FLTIEN
IOCON4 0446 PENH PENL POLH POLL
ITB
MDCS
DTC<1:0>
—
—
—
—
IUE
OVRENH
OVRENL
OVRDAT<1:0>
FLTDAT<1:0>
CLDAT<1:0>
OSYNC
TABLE 12-4: POWER SUPPLY PWM REGISTER MAP (CONTINUED)
File Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FCLCON4
PDC4
0448
044A
044C
044E
0450
0452
0454
0456
—
—
—
CLSRC<3:0>
CLPOL
CLMODE
FLTSRC<3:0>
FLTPOL
FLTMOD<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
PDC4<15:0>
PHASE4
DTR4
PHASE4<15:2>
DTR4<13:2>
—
—
—
—
—
—
—
—
—
—
—
—
ALTDTR4
TRIG4
ALTDTR4<13:2>
TRIG<15:3>
—
TRGCON4
LEBCON4
Reserved
TRGDIV<2:0>
—-
PLF
—
—-
—-
—-
—-
—
—-
—-
—
TRGSTRT<5:0>
—
PHR
—
PHF
—
PLR
—
FLTLEBEN CLLEBEN
LEB<9:3>
—
—
—
—
0458-
47F
—
—
—
—
—
—
—
—
dsPIC30F1010/202X
NOTES:
DS70178C-page 144
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
of the transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.
13.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note:
This data sheet summarizes the features
Note:
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register.
of this group of dsPIC30F1010/202X devices. It is not
intended to be a comprehensive reference source. To
complement the information in this data sheet, refer to
the “dsPIC30F Family Reference Manual” (DS70046).
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift regis-
ters, display drivers, ADC, etc. The SPI module is
compatible with SPI and SIOP from Motorola®.
To set up the SPI module for the Master mode of
operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSn
register.
Note: The dsPIC30F101/202X family has only
one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
b) Set the SPIxIE bit in the respective IECn
register.
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
The SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. Two control registers,
SPIxCON1 and SPIxCON2, configure the module. The
SPIxSR register is not accessible by user software. A sta-
tus register, SPIxSTAT, indicates various status
conditions.
2. Write the desired settings to the SPIxCON1
register with MSTEN (SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) start as
soon as data is written to the SPIxBUF register.
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock input
or output), and SSx (active-low slave select).
To set up the SPI module for the Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.
a) Clear the SPIxIF bit in the respective IFSn
register.
A series of eight (8) or sixteen (16) clock pulses shift out
bits from the SPIxSR to SDOx pin and simultaneously
shift in data from SDIx pin. An interrupt is generated
when the transfer is complete and the corresponding
interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt
can be disabled through an interrupt enable bit (SPI1IE
or SPI2IE).
b) Set the SPIxIE bit in the respective IECn
register.
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1 and
SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
The receive operation is double-buffered. When a com-
plete byte is received, it is transferred from SPIxSR to
SPIxBUF.
4. Clear the SMP bit (SPIxCON1<9>).
5. If the CKE (SPIxCON1<8>) bit is set, then the
SSEN bit (SPIxCON1<7>) must be set to enable
the SSx pin.
If the receive buffer is full when new data is being trans-
ferred from SPIxSR to SPIxBUF, the module sets the
SPIROV bit (SPIxSTAT<6>) to indicate an overflow con-
dition. The transfer of the data from SPIxSR to SPIxBUF
is not completed, and the new data is lost. The module
does not respond to transitions on the SCKx pin while
SPIROV (SPIxSTAT<6>) is ‘1’, effectively disabling the
module until SPIxBUF is read by user software.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
The SPI module generates an interrupt indicating com-
pletion of a byte or word transfer, as well as a separate
interrupt for all SPI error conditions.
Transmit writes are also double-buffered. The user soft-
ware writes to SPIxBUF. When the master or slave trans-
fer is completed, the contents of the shift register
(SPIxSR) are moved to the receive buffer. If any transmit
data has been written to the buffer register, the contents
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 145
dsPIC30F1010/202X
FIGURE 13-1:
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
Note:
The dsPIC30F1010/2020 devices do not contain the SS1 pin. Therefore, the Slave Select and Frame Sync
features cannot be used on these devices. These features are available on the dsPIC30F2023.
DS70178C-page 146
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 13-2:
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1 (SPI Master)
PROCESSOR 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer
(SPIxRXB)
Serial Receive Buffer
(SPIxRXB)
SDIx
SDOx
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)
LSb
MSb
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(SPIxTXB)
Serial Clock
SCKx
SCKx
SSx(1)
SPI Buffer
SPI Buffer
(SPIxBUF)(2)
(SPIxBUF)(2)
(MSTEN (SPIxCON1<5>) = 1)
(SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0)
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
FIGURE 13-3:
SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
dsPIC33F
PROCESSOR 2
(SPI Slave, Frame Slave)
SDIx
SDOx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
FIGURE 13-4:
SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
dsPIC33F
PROCESSOR 2
(SPI Master, Frame Slave)
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 147
dsPIC30F1010/202X
FIGURE 13-5:
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
dsPIC33F
PROCESSOR 2
(SPI Slave, Frame Slave)
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
FIGURE 13-6:
SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
dsPIC33F
PROCESSOR 2
(SPI Master, Frame Slave)
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
EQUATION 13-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED
FCY
FSCK =
Primary Prescaler * Secondary Prescaler
TABLE 13-1: SAMPLE SCKx FREQUENCIES
Secondary Prescaler Settings
FCY = 40 MHz
1:1
2:1
4:1
6:1
8:1
Primary Prescaler Settings
1:1
4:1
Invalid
7500
1875
469
Invalid
3750
7500
1875
469
5000
1250
312.5
78.1
3750
937.5
234.4
58.6
16:1
64:1
937.5
234.4
117
FCY = 5 MHz
Primary Prescaler Settings
1:1
4:1
5000
1250
313
78
2500
625
156
39
1250
313
78
833
208
52
625
156
39
16:1
64:1
20
13
10
Note: SCKx frequencies shown in kHz.
DS70178C-page 148
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 13-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register.
0= No overflow has occurred
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 149
dsPIC30F1010/202X
REGISTER 13-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSTEN
SPRE<2:0>
PPRE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled, pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
bit 4-2
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
SPRE<2:0>: Secondary Prescale bits (Master mode)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
...
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
DS70178C-page 150
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 13-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 151
TABLE 13-2: SPI1 REGISTER MAP
SFR
Name
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SPI1STAT
SPI1CON
0240
0242
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF SPIRBF
PPRE<1:0>
DISSCK DISSDO MODE16 SMP
SPI1CON2 0244 FRMEN SPIFSD FRMPOL
SPI1BUF 0246
—
—
—
—
—
—
—
FRMDLY
—
Transmit and Receive Buffer
Legend: u= uninitialized bit
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
2
14.1 Operating Function Description
14.0 I C™ MODULE
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
14.1.1
VARIOUS I2C MODES
The following types of I2C operation are supported:
• I2C Slave operation with 7 or 10-bit address
• I2C Master operation with 7 or 10-bit address
This module offers the following key features:
• I2C interface supporting both Master and Slave
operation.
• I2C Slave mode supports 7 and 10-bit address
• I2C Master mode supports 7 and 10-bit address
• I2C port allows bidirectional transfers between
master and slaves.
See the I2C programmer’s model in Figure 14-1.
14.1.2
PIN CONFIGURATION IN I2C MODE
I2C has a 2-pin interface; pin SCL is clock and pin SDA
is data.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports Multi-Master operation; detects bus
collision and will arbitrate accordingly.
FIGURE 14-1:
PROGRAMMER’S MODEL
I2CRCV (8 bits)
bit 0
bit 7
I2CTRN (8 bits)
bit 0
bit 7
bit 8
I2CBRG (9 bits)
bit 0
I2CCON (16 bits)
bit 0
bit 15
bit 15
I2CSTAT (16 bits)
bit 0
I2CADD (10 bits)
bit 0
bit 9
14.1.3
I2C REGISTERS
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator (BRG)
reload value.
I2CCON and I2CSTAT are Control and Status regis-
ters, respectively. The I2CCON register is readable and
writable. The lower 6 bits of I2CSTAT are read-only.
The remaining bits of the I2CSTAT are read/write.
In receive operations, I2CRSR and I2CRCV together
form
a double-buffered receiver. When I2CRSR
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are writ-
ten during a transmit operation, as shown in Figure 16-2.
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
Note:
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 153
dsPIC30F1010/202X
FIGURE 14-2:
I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CRCV
Read
Shift
Clock
SCL
SDA
I2CRSR
LSB
Addr_Match
Match Detect
I2CADD
Write
Read
Start and
Stop bit Detect
Write
Read
Start, Restart,
Stop bit Generate
Collision
Detect
Write
Read
Acknowledge
Generation
Clock
Stretching
Write
Read
I2CTRN
LSB
Shift
Clock
Reload
Control
Write
Read
I2CBRG
BRG Down
Counter
FCY
DS70178C-page 154
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
2
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
14.2 I C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 Least
Significant bits of the I2CADD register.
Note:
The I2CRCV will be loaded if the I2COV
bit = 1and the RBF flag = 0. In this case,
a read of the I2CRCV was performed, but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The acknowledgement is not
sent (ACK = 1) and the I2CRCV is
updated.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value ‘1 1 1 1 0 A9 A8’
(where A9, A8 are two Most Significant bits of
I2CADD). If that value matches, the next address will
be compared with the Least Significant 8 bits of
I2CADD, as specified in the 10-bit addressing protocol.
2
14.4 I C 10-bit Slave Mode Operation
2
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation, with two address bytes
following a Start bit.
14.3 I C 7-bit Slave Mode Operation
Once enabled (I2CEN = 1), the slave module will wait
for a Start bit to occur (i.e., the I2C module is ‘Idle’). Fol-
lowing the detection of a Start bit, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the
rising edge of SCL.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a
7-bit address. The address detection protocol for the
first byte of a message address is identical for 7-bit
and 10-bit messages, but the bits being compared are
different.
If an address match occurs, an acknowledgement will
be sent, and the slave event interrupt flag (SI2CIF) is
set on the falling edge of the ninth (ACK) bit. The
address match does not affect the contents of the
I2CRCV buffer or the RBF bit.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
14.3.1
SLAVE TRANSMISSION
If the R_W bit received is a ‘1’, then the serial port will
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to ‘0’ until the CPU responds by writ-
ing to I2CTRN. SCL is released by setting the SCLREL
bit, and 8 bits of data are shifted out. Data bits are
shifted out on the falling edge of SCL, such that SDA is
valid during SCL high (see timing diagram). The inter-
rupt pulse is sent on the falling edge of the ninth clock
pulse, regardless of the status of the ACK received
from the master.
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
14.3.2
SLAVE RECEPTION
14.4.1
10-BIT MODE SLAVE
TRANSMISSION
If the R_W bit received is a ‘0’ during an address
match, then Receive mode is initiated. Incoming bits
are sampled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
Once a slave is addressed in this fashion, with the full
10-bit address (we will refer to this state as
“PRIOR_ADDR_MATCH”), the master can begin send-
ing data bytes for a slave reception operation.
14.4.2
10-BIT MODE SLAVE RECEPTION
Once addressed, the master can generate a Repeated
Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave transmit operation.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 155
dsPIC30F1010/202X
14.5 Automatic Clock Stretch
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
stretching will not occur.
In the Slave modes, the module can synchronize buffer
reads and write to the master device by clock
stretching.
14.5.1
TRANSMIT CLOCK STRETCHING
2: The SCLREL bit can be set in software,
regardless of the state of the RBF bit. The
user should be careful to clear the RBF bit
in the ISR before the next receive
sequence in order to prevent an Overflow
condition.
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit.
14.5.4
CLOCK STRETCHING DURING
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock, and if the
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to ‘0’ will
assert the SCL line low. The user’s ISR must set the
SCLREL bit before transmission is allowed to con-
tinue. By holding the SCL line low, the user has time to
service the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit
sequence.
10-BIT ADDRESSING (STREN = 1)
Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
After the address phase is complete, clock stretching
will occur on each data receive or transmit sequence
as was described earlier.
14.6 Software Controlled Clock
Stretching (STREN = 1)
Note 1: If the user loads the contents of I2CTRN,
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not
be cleared and clock stretching will not
occur.
When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit will not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low. If the SCLREL bit is cleared by
the user while the SCL line has been sampled low, the
SCL output will be asserted (held low). The SCL out-
put will remain low until the SCLREL bit is set, and all
other devices on the I2C bus have deasserted SCL.
This ensures that a write to the SCLREL bit will not
violate the minimum high time requirement for SCL.
2: The SCLREL bit can be set in software,
regardless of the state of the TBF bit.
14.5.2
RECEIVE CLOCK STRETCHING
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at
the end of each data receive sequence.
14.5.3
CLOCK STRETCHING DURING
7-BIT ADDRESSING (STREN = 1)
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
When the STREN bit is set in Slave Receive mode,
the SCL line is held low when the buffer register is full.
The method for stretching the SCL output is the same
for both 7 and 10-bit Addressing modes.
14.7 Interrupts
The I2C module generates two interrupt flags, MI2CIF
(I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter-
rupt Flag). The MI2CIF interrupt flag is activated on
completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message
directed to the slave.
Clock stretching takes place following the ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the ACK sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing the
SCL output to be held low. The user’s ISR must set the
SCLREL bit before reception is allowed to continue. By
holding the SCL line low, the user has time to service
the ISR and read the contents of the I2CRCV before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring.
DS70178C-page 156
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
2
14.8 Slope Control
14.12 I C Master Operation
The I2C standard requires slope control on the SDA
and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate con-
trol, if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
14.9 IPMI Support
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic ‘0’. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK bit is received. Start and Stop con-
ditions are output to indicate the beginning and the end
of a serial transfer.
The control bit IPMIEN enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
14.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should,
in theory, respond with an acknowledgement.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device (7
bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic 1. Thus, the first byte trans-
mitted is a 7-bit slave address, followed by a ‘1’ to indi-
cate receive bit. Serial data is received via SDA, while
SCL outputs the serial clock. Serial data is received 8
bits at a time. After each byte is received, an ACK bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R_W = 0.
The general call address is recognized when the Gen-
eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).
Following a Start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.
14.12.1 I2C MASTER TRANSMISSION
If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set, and, on the falling edge of the ninth bit
(ACK bit), the master event interrupt flag (MI2CIF) is
set.
Transmission of a data byte, a 7-bit address, or the sec-
ond half of a 10-bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the Baud Rate Generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific, or a general call address.
2
14.11 I C Master Support
14.12.2 I2C MASTER RECEPTION
As a Master device, six operations are supported.
• Assert a Start condition on SDA and SCL.
• Assert a Restart condition on SDA and SCL.
Master mode reception is enabled by programming the
receive enable (RCEN) bit (I2CCON<3>). The I2C
module must be Idle before the RCEN bit is set, other-
wise the RCEN bit will be disregarded. The Baud Rate
Generator begins counting, and, on each rollover, the
state of the SCL pin toggles, and data is shifted in to the
I2CRSR on the rising edge of each clock.
• Write to the I2CTRN register initiating
transmission of data/address.
• Generate a Stop condition on SDA and SCL.
• Configure the I2C port to receive data.
• Generate an ACK condition at the end of a
received byte of data.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 157
dsPIC30F1010/202X
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are deasserted,
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus col-
lision Interrupt Service Routine, and if the I2C bus is
free, the user can resume communication by asserting
a Start condition.
14.12.3 BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
As per the I2C standard, FSCK may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
The Master will continue to monitor the SDA and SCL
pins and, if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
EQUATION 14-1: I2CBRG VALUE
Fcy
Fcy
⎛
⎝
⎞
⎠
---------- --------------------------
–
I2CBRG =
– 1
In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
Fscl 1, 111, 111
14.12.4 CLOCK ARBITRATION
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit or Restart/Stop condition. When the SCL pin is
allowed to float high, the Baud Rate Generator is
suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the
Baud Rate Generator is reloaded with the contents of
I2CBRG and begins counting. This ensures that the
SCL high time will always be at least one BRG rollover
count in the event that the clock is held low by an
external device.
2
14.13 I C Module Operation During CPU
Sleep and Idle Modes
14.13.1 I2C OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
14.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master operation support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
14.13.2 I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted, and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service
Routine, if the I2C bus is free (i.e., the P bit is set) the
user can resume communication by asserting a Start
condition.
DS70178C-page 158
Preliminary
© 2006 Microchip Technology Inc.
TABLE 14-1: I2C™ REGISTER MAP
SFR
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Name
I2CRCV
I2CTRN
I2CBRG
I2CCON
I2CSTAT
I2CADD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0001 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0200
0202
0204
0206
Receive Register
Transmit Register
Baud Rate Generator
GCEN STREN ACKDT ACKEN RCEN
GCSTAT ADD10 IWCOL I2COV D_A
Address Register
I2CEN
I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
PEN
R_W
RSEN
RBF
SEN
TBF
—
—
—
—
—
—
0208 ACKSTAT TRSTAT
BCL
P
S
—
—
—
020A
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
NOTES:
DS70178C-page 160
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
• Baud Rates Ranging from 1 Mbps to 15 bps at
16 MIPS
15.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
• 4-Deep First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC30F1010/202X device family.
The UART is a full-duplex asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN, RS-232 and RS-485 inter-
faces. The module also includes an IrDA encoder and
decoder.
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure 15-1. The UART module consists of these key
important hardware elements:
The primary features of the UART module are:
• Baud Rate Generator
• Full-Duplex 8 or 9-bit Data Transmission through
the U1TX and U1RX pins
• Asynchronous Transmitter
• Asynchronous Receiver
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Fully Integrated Baud Rate Generator with 16-bit
Prescaler
FIGURE 15-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
U1RX
U1TX
UART1 Receiver
UART1 Transmitter
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 161
dsPIC30F1010/202X
The maximum baud rate (BRGH = 0) possible is
FCY/16 (for U1BRG = 0), and the minimum baud rate
possible is FCY/(16 * 65536).
15.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated 16-bit Baud
Rate Generator. The U1BRG register controls the
period of a free-running 16-bit timer. Equation 15-1
shows the formula for computation of the baud rate
with BRGH = 0.
Equation 15-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 15-2: UART BAUD RATE WITH
BRGH = 1(1,2,3)
EQUATION 15-1: UART BAUD RATE WITH
BRGH = 0(1,2,3)
FCY
Baud Rate =
4 • (U1BRG + 1)
FCY
Baud Rate =
16 • (U1BRG + 1)
FCY
4 • Baud Rate
– 1
U1BRG =
FCY
16 • Baud Rate
– 1
U1BRG =
Note 1: FCY denotes the instruction cycle clock
frequency.
Note 1: FCY denotes the instruction cycle clock
frequency (FOSC/2).
2: Assuming external oscillator with fre-
quency of 15 MHz and PLL disabled,
FCY is 7.5 MHz.
2: Assuming external oscillator with fre-
quency of 15 MHz and PLL disabled,
FCY is 7.5 MHz.
3: Assuming external oscillator with fre-
quency of 15 MHz and PLL enabled,
FCY is 30 MHz.
3: Assuming external oscillator with fre-
quency of 15 MHz and PLL enabled,
FCY is 30 MHz.
The maximum baud rate (BRGH = 1) possible is FCY/4
(for U1BRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
Writing a new value to the U1BRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
• FCY = 7.5 MHz
• Desired Baud Rate = 9600
EXAMPLE 15-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate
=
Fcy/(16 (U1BRG + 1))
Solving for U1BRG value:
U1BRG
U1BRG
U1BRG
=
=
=
((FCY/Desired Baud Rate)/16) – 1
((7500000/9600)/16) – 1
48
Calculated Baud Rate
=
=
7500000/(16 (48 + 1))
9566
Error
=
(Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
=
=
(9566 – 9600)/9600
-0.35%
Note 1: Based on TCY = 2/FOSC, PLL are disabled.
DS70178C-page 162
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
15.2 Transmitting in 8-bit Data Mode
15.4 Break and Sync Transmit
Sequence
1. Set up the UART:
a) Write appropriate values for data, parity and
Stop bits.
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte.
b) Write appropriate baud rate value to the
U1BRG register.
1. Configure the UART for the desired mode.
c) Set up transmit and receive interrupt enable
and priority bits.
2. Set UTXEN and UTXBRK – sets up the Break
character,
2. Enable the UART.
3. Load the TXxREG with a dummy character to
initiate transmission (value is ignored).
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write data byte to lower byte of TXxREG word.
The value will be immediately transferred to the
Transmit Shift Register (TSR), and the serial bit
stream will start shifting out with next rising edge
of the baud clock.
4. Write ‘55h’ to TXxREG – loads Sync character
into the transmit FIFO.
5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
5. Alternately, the data byte may be transferred
while UTXEN = 0, and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
15.5 Receiving in 8-bit or 9-bit Data
Mode
1. Set up the UART (as described in Section 15.2
“Transmitting in 8-bit Data Mode”).
6. A transmit interrupt will be generated as per
interrupt control bit, UTXISELx.
2. Enable the UART.
3. A receive interrupt will be generated when one
or more data characters have been received as
per interrupt control bit, URXISELx.
15.3 Transmitting in 9-bit Data Mode
1. Set up the UART (as described in Section 15.2
“Transmitting in 8-bit Data Mode”).
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write TXxREG as a 16-bit value only.
5. Read RXxREG.
The act of reading the RXxREG character will move the
next character to the top of the receive FIFO, including
a new set of PERR and FERR values.
5. A word write to TXxREG triggers the transfer of
the 9-bit data to the TSR. Serial bit stream will
start shifting out with the first rising edge of the
baud clock.
15.6 Built-in IrDA Encoder and Decoder
6. A transmit interrupt will be generated as per the
setting of control bit, UTXISELx.
The UART has full implementation of the IrDA encoder
and decoder as part of the UART module. The built-in
IrDA encoder and decoder functionality is enabled
using the IREN bit U1MODE<12>. When enabled
(IREN = 1), the receive pin (U1RX) acts as the input
from the infrared receiver. The transmit pin (U1TX) acts
as the output to the infrared transmitter.
15.7 Alternate UART I/O Pins
An alternate set of I/O pins, U1ATX and U1ARX can be
used for communications. The alternate UART pins are
useful when the primary UART pins are shared by other
peripherals. The alternate I/O pins are enabled by set-
ting the ALTIO bit in the UxMODE register. If ALTIO =
1, the U1ATX and U1ARX pins are used by the UART
module, instead of the U1TX and U1RX pins. If ALTIO
= 0, the U1TX and U1RX pins are used by the UART
module.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 163
dsPIC30F1010/202X
REGISTER 15-1: U1MODE: UART1 MODE REGISTER
R/W-0
U-0
—
R/W-0
USIDL
R/W-0
IREN
U-0
—
R/W-0
ALTIO
U-0
—
U-0
—
UARTEN
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
RXINV
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HC = Hardware Cleared
‘0’ = Bit is cleared
HS = Hardware Select
x = Bit is unknown
bit 15
UARTEN: UART1 Enable bit
1
0
= UART1 enabled; all UART1 pins are controlled by UART1 as defined by UEN<1:0>
= UART1 disabled; all UART1 pins are controlled by PORT latches; UART1 power consumption minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
IREN: IrDA Encoder and Decoder Enable bit
1= IrDA encoder and decoder enabled
0= IrDA encoder and decoder disabled
Note:
This feature is only available for the 16x BRG mode (BRGH = 0).
bit 11
bit 10
Unimplemented: Read as ‘0’
ALTIO: UART Alternate I/O Selection bit
1= UART communicates using U1ATX and U1ARX I/O pins
0= UART communicates using U1TX and U1RX I/O pins.
bit 9-8
bit 7
Unimplemented: Read as ‘0’
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UART1 will continue to sample the U1RX pin; interrupt generated on falling edge, bit cleared in
hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UART1 Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0= Baud rate measurement disabled or completed
bit 4
bit 3
RXINV: Receive Polarity Inversion bit
1= U1RX Idle state is ‘0’
0= U1RX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)
DS70178C-page 164
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 15-1: U1MODE: UART1 MODE REGISTER (CONTINUED)
bit 2-1
PDSEL1:PDSEL0: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 165
dsPIC30F1010/202X
REGISTER 15-2: U1STA: UART1 STATUS AND CONTROL REGISTER
R/W-0
R/W-0
UTXINV(1)
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TRMT
UTXISEL1
UTXISEL0
UTXBRK
UTXEN
UTXBF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
RIDLE
R/W-0
PERR
R/W-0
FERR
R/W-0
OERR
R/W-0
URXISEL1
URXISEL0
ADDEN
URXDA
bit 7
bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS =Hardware Set
‘0’ = Bit is cleared
HC = Hardware Cleared
x = Bit is unknown
bit 15, 13
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits
11=Reserved; do not use
10=Interrupt when a character is transferred to the Transmit Shift Register and as a result, the
transmit buffer becomes empty
01=Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00=Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14
UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)
1= IrDA encoded U1TX idle state is ‘1’
0= IrDA encoded U1TX idle state is ‘0’
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is
enabled (IREN = 1).
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit
1= Transmit enabled, U1TX pin controlled by UART1
0= Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by
PORT.
bit 9
bit 8
UTXBF: Transmit Buffer Full Status bit (Read-Only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (Read-Only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has
completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
bit 5
URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits
11=Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10=Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x=Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
Receive buffer has one or more characters.
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode disabled
DS70178C-page 166
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 15-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED)
bit 4
bit 3
bit 2
RIDLE: Receiver Idle bit (Read-Only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (Read-Only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (Read-Only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (Read/Clear-Only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed (clearing a previously set OERR bit (1→ 0transition) will reset
the receiver buffer and the RSR to the empty state)
URXDA: Receive Buffer Data Available bit (Read-Only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 167
TABLE 15-1: UART1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
UARTEN
—
USIDL
IREN
—
—
ALTIO
—
—
WAKE
LPBACK
ABAUD
ADDEN
RXINV
RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN UTXBF
TRMT
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC30F1010/202X
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP based application.
16.0 10-BIT 2 MSPS ANALOG-TO-
DIGITAL CONVERTER (ADC)
MODULE
1. Result alignment options
2. Automated sampling
The dsPIC30F1010/202X devices provide high-speed
successive approximation analog to digital conversions
to support applications such as AC/DC and DC/DC
power converters.
3. External conversion start control
A block diagram of the ADC module is shown in
Figure 16-1.
16.1 Features
16.3 Module Functionality
• 10-bit resolution
The 10-bit 2 Msps ADC is designed to support power
conversion applications when used with the Power
Supply PWM module. The 10-bit 2 Msps ADC samples
up to N (N ≤ 12) inputs at a time and then converts two
sampled inputs at a time. The quantity of sample and
hold circuits is determined by a device’s requirements.
The10-Bit 2 Msps ADC produces two 10-bit conversion
results in 1 microsecond.
• Uni-polar Inputs
• Up to 12 input channels
• ±1 LSB accuracy
• Single supply operation
• 2000 ksps conversion rate at 5V
• 1000 ksps conversion rate at 3.0V
• Low power CMOS technology
The ADC module supports up to 12 analog inputs. The
sampled inputs are connected, via multiplexers, to the
converter.
16.2 Description
This ADC module is designed for applications that
require low latency between the request for conversion
and the resultant output data. Typical applications
include:
The analog reference voltage is defined as the device
supply voltage (AVDD / AVSS).
The ADC module uses these Control and Status regis-
ters:
• AC/DC power supplies
• DC/DC converters
• A/D Control Register (ADCON)
• A/D Status Register (ADSTAT)
• Power factor correction
• A/D Base Register (ADBASE)
This ADC works with the Power Supply PWM module
in power control applications that require high-fre-
quency control loops. This module can sample and
convert two analog inputs in one microsecond. The one
microsecond conversion delay reduces the “phase lag”
between measurement and control system response.
• A/D Port Configuration Register (ADPCFG)
• A/D Convert Pair Control Register #0 (ADCPC0)
• A/D Convert Pair Control Register #1 (ADCPC1)
• A/D Convert Pair Control Register #2 (ADCPC2)
The ADCON register controls the operation of the ADC
module. The ADSTAT register displays the status of the
conversion processes. The ADPCFG registers config-
ure the port pins as analog inputs or as digital I/O. The
CPC registers control the triggering of the ADC conver-
sions. (See Register 16-1 through Register 16-7 for
detailed bit configurations.)
Up to 4 inputs may be sampled at a time, and up to 12
inputs may request conversion at a time. If multiple
inputs request conversion, the ADC will convert them in
a sequential manner starting with the lowest order
input.
This ADC design provides each pair of analog inputs
(AN1,AN0), (AN3,AN2), ... , the ability to specify its own
trigger source out of a maximum of sixteen different
trigger sources. This capability allows this ADC to sam-
ple and convert analog inputs that are associated with
PWM generators operating on independent time
bases.
Note: A unique feature of the ADC module is its abil-
ity to sample inputs in an asynchronous manner.
Individual sample and hold circuits can be triggered
independently of each other.
There is no operation during Sleep mode. The user
applications typically require synchronization between
analog data sampling and PWM output to the applica-
tion circuit. The very high speed operation of this ADC
module allows “data on demand”.
Note: The PLL must be enabled for the ADC module
to function. This is achieved by using the
FNOSC<1:0> bits in the FOSCSEL Configuration
register.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 169
dsPIC30F1010/202X
FIGURE 16-1:
ADC BLOCK DIAGRAM
Dedicated Sample & Holds
AN0
AN2
AN4
AN6
12-word, 16-bit
Registers
10-Bit SAR
DAC
Conversion Logic
Comparator
AVSS
AVDD
MUX/Sample/Sequence
Control
AN8
Even numbered inputs
without dedicated
Sample and Hold
AN10
AN1
AN3
Common Sample and Hold
AN11
DS70178C-page 170
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 16-1: A/D CONTROL REGISTER (ADCON)
R/W-0
ADON
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
U-0
—
R/W-0
FORM
ADSIDL
GSWTRG
bit 15
bit 8
R/W-1
bit 0
R/W-0
EIE
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-1
ORDER
SEQSAMP
ADCS<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit
1= A/D converter module is operating
0= A/D converter is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
bit 10
Unimplemented: Read as ‘0’
GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e.,
this bit is not auto-clearing).
bit 9
bit 8
Unimplemented: Read as ‘0’
FORM: Data Output Format bit
1= Fractional (DOUT = dddd dddd dd00 0000)
0= Integer
(DOUT = 0000 00dd dddd dddd)
bit 7
bit 6
bit 5
EIE: Early Interrupt Enable bit
1= Interrupt is generated after first conversion is completed
0= Interrupt is generated after second conversion is completed
Note:
This control bit can only be changed while ADC is disabled (ADON = 0).
ORDER: Conversion Order bit
1= Odd numbered analog input is converted first, followed by conversion of even numbered input
0= Even numbered analog input is converted first, followed by conversion of odd numbered input
Note:
This control bit can only be changed while ADC is disabled (ADON = 0).
SEQSAMP: Sequential Sample Enable.
1= Shared S&H is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then
the shared S&H is sampled at the start of the first conversion.
0= Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle
bit 4-3
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
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REGISTER 16-1: A/D CONTROL REGISTER (ADCON) (CONTINUED)
bit 2-0
ADCS<2:0>: A/D Conversion Clock Divider Select bits
If PLL is enabled (assume 15 MHz external clock as clock source):
111= FADC/18 = 13.3 MHz @ 30 MIPS
110= FADC/16 = 15.0 MHz @ 30 MIPS
101= FADC/14 = 17.1 MHz @ 30 MIPS
100= FADC/12 = 20.0 MHz @ 30 MIPS
011= FADC/10 = 24.0 MHz @ 30 MIPS
010= FADC/8 = 30.0 MHz @ 30 MIPS
001= FADC/6 = Reserved, defaults to 30 MHz @ 30 MIPS
000= FADC/4 = Reserved, defaults to 30 MHz @ 30 MIPS
If PLL is disabled (assume 15 MHz external clock as clock source):
111= FADC/18 = 0.83 MHz @ 7.5 MIPS
110= FADC/16 = 0.93 MHz @ 7.5 MIPS
101= FADC/14 = 1.07 MHz @ 7.5 MIPS
100= FADC/12 = 1.25 MHz @ 7.5 MIPS
011= FADC/10 = 1.5 MHz @ 7.5 MIPS
010= FADC/8 = 1.87 MHz @ 7.5 MIPS
001= FADC/6 = 2.5 MHz @ 7.5 MIPS
000= FADC/4 = 3.75 MHz @ 7.5 MIPS
Note:
See Figure 18-2 for ADC clock derivation.
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REGISTER 16-2: A/D STATUS REGISTER (ADSTAT)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/C-0
H-S
R/C-0
H-S
R/C-0
H-S
R/C-0
H-S
R/C-0
H-S
R/C-0
H-S
P5RDY
P4RDY
P3RDY
P2RDY
P1RDY
P0RDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
C = Clear in software
H-S = Set by hardware
bit 15-6
bit 5
Unimplemented: Read as ‘0’
P5RDY: Conversion Data for Pair #5 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 4
bit 3
bit 2
bit 1
bit 0
P4RDY: Conversion Data for Pair #4 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P3RDY: Conversion Data for Pair #3 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P2RDY: Conversion Data for Pair #2 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P1RDY: Conversion Data for Pair #1 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
P0RDY: Conversion Data for Pair #0 Ready bit
Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
© 2006 Microchip Technology Inc.
Preliminary
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REGISTER 16-3: A/D BASE REGISTER (ADBASE)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
ADBASE<15:8>
R/W-0
R/W-0
R/W-0
U-0
—
ADBASE<7:1>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
ADC Base Register: This register contains the base address of the user’s ADC Interrupt Service Rou-
tine jump table. This register, when read, contains the sum of the ADBASE register contents and the
encoded value of the PxRDY Status bits.
The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the
highest priority, and P5RDY is lowest priority.
Note:
The encoding results are shifted left two bits so bits 1-0 of the result are always zero.
bit 0
Unimplemented: Read as ‘0’
Note:
As an alternative to using the ADBASE Register, the ADCP0-5 ADC Pair Conversion Complete Interrupts
(Interrupts 37-42) can be used to invoke A to D conversion completion routines for individual ADC input
pairs. Refer to Section 16.9 “Individual Pair Interrupts”.
REGISTER 16-4: A/D PORT CONFIGURATION REGISTER (ADPCFG)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
PCFG<11:0>: A/D Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, A/D samples pin voltage
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REGISTER 16-5: A/D CONVERT PAIR CONTROL REGISTER #0 (ADCPC0)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IRQEN1
PEND1
SWTRG1
TRGSRC1<4:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN0
PEND0
SWTRG0
TRGSRC0<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
IRQEN1: Interrupt Request Enable 1 bit
1= Enable IRQ generation when requested conversion of channels AN3 and AN2 is completed
0= IRQ is not generated
PEND1: Pending Conversion Status 1 bit
1= Conversion of channels AN3 and AN2 is pending. Set when selected trigger is asserted
0= Conversion is complete
SWTRG1: Software Trigger 1 bit
1= Start conversion of AN3 and AN2 (if selected in TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
bit 12-8
TRGSRC1<4:0>: Trigger 1 Source Selection bits
Selects trigger source for conversion of analog channels AN3 and AN2.
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
bit 7
IRQEN0: Interrupt Request Enable 0 bit
1= Enable IRQ generation when requested conversion of channels AN1 and AN0 is completed
0= IRQ is not generated
bit 6
bit 5
PEND0: Pending Conversion Status 0 bit
1= Conversion of channels AN1 and AN0 is pending. Set when selected trigger is asserted.
0= Conversion is complete
SWTRG0: Software Trigger 0 bit
1= Start conversion of AN1 and AN0 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set
© 2006 Microchip Technology Inc.
Preliminary
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REGISTER 16-5: A/D CONVERT PAIR CONTROL REGISTER #0 (ADCPC0) (CONTINUED)
bit 4-0
TRGSRC0<4:0>: Trigger 0 Source Selection bits
Selects trigger source for conversion of analog channels AN1 and AN0.
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
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REGISTER 16-6: A/D CONVERT PAIR CONTROL REGISTER #1 (ADCPC1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
IRQEN3
PEND3
SWTRG3
TRGSRC3<4:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN2
PEND2
SWTRG2
TRGSRC2<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
IRQEN3: Interrupt Request Enable 3 bit
1= Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed.
0= IRQ is not generated
bit 14
bit 13
PEND3: Pending Conversion Status 3 bit
1= Conversion of channels AN7 and AN6 is pending. Set when selected trigger is asserted.
0= Conversion is complete
SWTRG3: Software Trigger 3 bit
1= Start conversion of AN7 and AN6 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
bit 12-8
TRGSRC3<4:0>: Trigger 3 Source Selection bits
Selects trigger source for conversion of analog channels A7 and A6.
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
bit 7
bit 6
bit 5
IRQEN2: Interrupt Request Enable 2 bit
1= Enable IRQ generation when requested conversion of channels AN5 and AN4 is completed
0= IRQ is not generated
PEND2: Pending Conversion Status 2 bit
1= Conversion of channels AN5 and AN4 is pending. Set when selected trigger is asserted
0= Conversion is complete
SWTRG2: Software Trigger 2 bit
1= Start conversion of AN5 and AN4 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set
© 2006 Microchip Technology Inc.
Preliminary
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REGISTER 16-6: A/D CONVERT PAIR CONTROL REGISTER #1 (ADCPC1) (CONTINUED)
bit 4-0
TRGSRC2<4:0>: Trigger 2 Source Selection bits
Selects trigger source for conversion of analog channels: AN5 and AN4
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
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REGISTER 16-7: A/D CONVERT PAIR CONTROL REGISTER #2 (ADCPC2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
IRQEN5
PEND5
SWTRG5
TRGSRC5<4:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN4
PEND4
SWTRG4
TRGSRC4<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
.
bit 15
bit 14
bit 13
IRQEN5: Interrupt Request Enable 5 bit
1= Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0= IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1= Conversion of channels AN11 and AN10 is pending. Set when selected trigger is asserted
0= Conversion is complete
SWTRG5: Software Trigger 5 bit
1= Start conversion of AN11 and AN10 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
bit 12-8
TRGSRC5<4:0>: Trigger Source Selection 5 bits
Selects trigger source for conversion of analog channels A11 and A10.
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
bit 7
bit 6
bit 5
IRQEN4: Interrupt Request Enable 4 bit
1= Enable IRQ generation when requested conversion of channels AN9 and AN8 is completed
0= IRQ is not generated
PEND4: Pending Conversion Status 4 bit
1= Conversion of channels AN9 and AN8 is pending. Set when selected trigger is asserted.
0= Conversion is complete
SWTRG4: Software Trigger 4 bit
1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits). If other conversions are in
progress, then conversion will be performed when the conversion resources are available. This bit will
be reset when the PEND bit is set.
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Preliminary
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REGISTER 16-7: A/D CONVERT PAIR CONTROL REGISTER #2 (ADCPC2) (CONTINUED)
bit 4-0
TRGSRC4<4:0>: Trigger Source Selection 4 bits
Selects trigger source for conversion of analog channels: AN9 and AN8
00000= No conversion enabled
00001= Individual software trigger selected
00010= Global software trigger selected
00011= PWM Special Event Trigger selected
00100= PWM generator #1 trigger selected
00101= PWM generator #2 trigger selected
00110= PWM generator #3 trigger selected
00111= PWM generator #4 trigger selected
01100= Timer #1 period match
01101= Timer #2 period match
01110= PWM GEN #1 current-limit ADC trigger
01111= PWM GEN #2 current-limit ADC trigger
10000= PWM GEN #3 current-limit ADC trigger
10001= PWM GEN #4 current-limit ADC trigger
10110= PWM GEN #1 fault ADC trigger
10111= PWM GEN #2 fault ADC trigger
11000= PWM GEN #3 fault ADC trigger
11001= PWM GEN #4 fault ADC trigger
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16.4 ADC Result Buffer
16.5 Application Information
The ADC module contains up to 12 data output regis-
ters to store the A/D results called ADCBUF<11:0>.
The registers are 10 bits wide, but are read into differ-
ent format, 16-bit words. The buffers are read-only.
The ADC module implements a concept based on
“Conversion Pairs”. In power conversion applications,
there is a need to measure voltages and currents for
each PWM control loop. The ADC module enables the
sample and conversion process of each conversion
pair to be precisely timed relative to the PWM signals.
Each analog input has a corresponding data
output register.
In a user’s application circuit, the PWM signal enables
a transistor, which allows an inductor to charge up with
current to a desired value. The longer a PWM signal is
on, the longer the inductor is charging, and therefore
the inductor current is at its maximum at the end of the
PWM signal. Often, this is the point where the user
wants to take the current and voltage measurements.
This module DOES NOT include a circular data
buffer or FIFO. Because the conversion results may
be produced in any order, such schemes will not work
since there would be no means to determine which
data is in a specific location.
The SAR write to the buffers is synchronous to the
ADC clock. Reads from the buffers will always have
valid data assuming that the data-ready interrupt has
been processed.
Figure 16-2 shows a typical power conversion applica-
tion (a boost converter) where the current sensing of
the inductor is done by monitoring the voltage across a
resistor in series with the power transistor that
“charges” the inductor. The significant feature of this
figure is that if the sampling of the resistor voltage
occurs slightly later than the desired sample point, the
data read will be zero. This is not acceptable in most
applications. The ADC module always samples the
analog voltages at the appointed time regardless of
whether the ADC converter is busy or not.
If a buffer location has not been read by the software
and the SAR needs to overwrite that location, the
previous data is lost.
Reads from the result buffer pass through the data for-
matter. The 10 bits of the result data are formatted into
a 16-bit word.
The Power Supply PWM module supports 2-4 indepen-
dent PWM channels as well as 2-4 trigger signals (one
per PWM generator). The user can configure these
channels to initiate an ADC conversion of a selected
input pair at the proper time in the PWM cycle. The
Power Supply PWM module also provides an addi-
tional trigger signal (Special Event Trigger), which can
be programmed to occur at a specified time during the
primary time base count cycle.
FIGURE 16-2:
APPLICATION EXAMPLE: IMPORTANCE OF PRECISE SAMPLING
Critical Edge
Example Boost Converter
X
PWM
IL
IL
+VIN
VOUT
COUT
Desired sample point
L
X
PWM
IR
X
+
Late sample yields
zero data
IR
R
VISENSE
Measuring peak inductor current is very important
© 2006 Microchip Technology Inc.
Preliminary
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dsPIC30F1010/202X
16.6 Reverse Conversion Order
16.8 Group Interrupt Generation
The ORDER control bit in the ADCON register, when
set, reverses the order of the input pair conversion pro-
The ADC module provides a common or “Group” inter-
rupt request that is the OR of all of the enabled interrupt
sources within the module. Each CPC register has two
IRQENx bits, one for each analog input pair. If the
IRQEN bit is set, an interrupt request is made to the
interrupt controller when the requested conversion is
completed. When an interrupt is generated, an asso-
ciated PxRDY bit in the ADSTAT register is set. The
PxRDY bit is cleared by the user. The user’s software
can examine the ADSTAT register’s PxRDY bits to
determine if additional requested conversions have
been completed.
cess. Normally (ORDER
= 0), the even numbered
input of an input pair is converted first and then the odd
numbered input is converted. If ORDER = 1, the odd
numbered input pin of an input pair is converted first,
followed by the even numbered pin.
This feature is useful when using voltage control
modes and using the early interrupt capability
(EIE = 1). These features enable the user to minimize
the time period from actual acquisition of the feedback
(ADC) data to the update of the control output (PWM).
This time from input to output of the control system
determines the overall stability of the control system.
The group interrupt is useful for applications that use a
common software routine to process ADC interrupts for
multiple analog input pairs. This method is more
traditional in concept.
16.7 Simultaneous and Sequential
Sampling in a pair
Note:
The user must clear the IFS bit associated
with the ADC in the interrupt controller
before the PxRDY bit is cleared. Failure to
do so may cause interrupts to be lost. The
reason is that the ADC will possibly have
another interrupt pending. If the user
clears the PxRDY bit first, the ADC may
generate another interrupt request, but if
the user then clears the IFS bit, the
The inputs that have dedicated Sample and Hold
(S&H) circuits are sampled when their specified trigger
events occur. The inputs that share the common sam-
ple and hold circuit are sampled in the following
manner:
1. If the SEQSAMP bit = 0, and the common
(shared) sample and hold circuit is NOT busy,
then the shared S&H will sample their specified
input at the same time as the dedicated S&H.
This action provides “Simultaneous” sample and
hold functionality.
interrupt request will be erased.
2. If the SEQSAMP bit = 0, and the shared S&H is
currently busy with a conversion in progress,
then the shared S&H will sample as soon as
possible (at the start of the new conversion
process for the pair).
3. If the SEQSAMP bit = 1, then the shared S&H
will sample at the start of the conversion process
for that input. For example: If the ORDER bit = 0
the shared S&H will sample at the start of the
conversion of the second input. If ORDER = 1,
then the shared S&H will sample at the start of
the conversion for the first input.
The SEQSAMP bit is useful for some applica-
tions that want to minimize the time from a
sample event to the conversion of the sample.
When SEQSAMP = 0, the logic attempts to take
the samples for both inputs of a pair at the same
time if the resources are available. The user can
often ensure that the ADC will not be busy with
a prior conversion by controlling the timing of the
trigger signals that initiate the conversion
processes.
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16.9 Individual Pair Interrupts
16.11 Conflict Resolution
The ADC module also provides individual interrupts
outputs for each analog input pair. These interrupts are
always enabled within the module. The pair interrupts
can be individually enabled or disabled via the
If more than one conversion pair request is active at the
same time, the ADC control logic processes the
requests in a top-down manner, starting at analog pair
#0 (AN1/AN0) and ending at analog pair #5 (AN11/
AN10). This is not a “round-robin” process.
associated interrupt enable bits in the IEC registers.
Using the group interrupts may require the interrupt
service routine to determine which interrupt source
generated the interrupt. For applications that use sep-
arate software tasks to process ADC data, a common
interrupt vector can cause performance bottlenecks.
16.12 Deliberate Conflicts
If the user specifies the same conversion trigger source
for multiple “conversion pairs”, then the ADC module
functions like other dsPIC30F ADC modules; i.e., it pro-
cesses the requested conversions sequentially (in
pairs) until the sequence has been completed.
The use of the individual pair interrupts can save many
clock cycles compared to using the group interrupt to
process multiple interrupt sources. The individual pair
interrupts support the construction of application
software that is responsive and organized on a task
basis.
Note:
The ADC module will NOT repeatedly loop
once triggered. Each sequence of
conversions requires a trigger or multiple
triggers.
Regardless of whether an individual pair interrupt or the
global interrupt are used to respond to an interrupt
request from an ADC conversion, the PxRDY bits in the
ADSTAT register function in the same manner.
16.13 ADC Clock Selection
The ADCS<2:0> bits in the ADCON register specify the
clock divisor value for the ADC clock generation logic.
The input to the ADC clock divisor is the system clock
(240 MHz @ 30 MIPS) when the PLL is operating. This
high-frequency clock provides the needed timing reso-
lution to generate a 24 MHz ADC clock signal required
to process two ADC conversions in 1 microsecond.
The use of the individual pair interrupts also enables
the user to change the interrupt priority of individual
ADC channels (pairs) as compared to the fixed priority
structure of the group interrupt.
NOTE: The use of individual interrupts DOES NOT
affect the priority structure of the ADC with respect
to the order of input pair conversion.
16.14 ADC Base Register
The use of individual interrupts can reduce the problem
of accidently “losing” a pending interrupt while
processing and clearing a current interrupt
It is expected that the user application may have the
ADC module generate 500,000 interrupts per second.
To speed the evaluation of the PxRDY bits in the
ADSTAT register, the ADC module features the read/
write register: ADBASE. When read, the ADBASE reg-
ister provides a sum of the contents of the ADBASE
register plus an encoding of the PxRDY bits set in the
ADSTAT register.
16.10 Early Interrupt Generation
The EIE control bit in the ADCON register enables the
generation of the interrupts after completion of the first
conversion instead of waiting for the completion of both
inputs of an input pair. Even though the second input
will still be in the conversion process, the software can
be written to perform some of the computations using
the first data value while the second conversion is
completed.
The Least Significant bit of the ADBASE register is
forced to zero, which ensures that all (ADBASE +
PxRDY) results are on instruction boundaries.
The PxRDY bits are binary priority encoded; P0RDY is
the highest priority and P5RDY is the lowest priority.
The encoded priority result is shifted left two bit posi-
tions and added to the contents of the ADBASE regis-
ter. Thus the priority encoding yields addresses that
are on two instruction word boundaries.
The user software can be written to account for the 500
nsec conversion period of the second input before
using the second data, or the user can poll the PEND
bit in the ADCPCx register.
The PEND bit remains set until both conversions of a
pair have been completed. The PxRDY bit for the asso-
ciated interrupt is set in the ADSTAT register at the
completion of the first conversion, and remains set until
it is cleared by the user.
The user will typically load the ADBASE register with
the base address of a “Jump” table that contains either
the addresses of the appropriate ISRs or branches to
the appropriate ISR. The encoded PxRDY values are
set up to reserve two instruction words per entry in the
Jump table. It is expected that the user software will
use one instruction word to load an identifier into a W
register, and the other instruction will be a branch to
the appropriate ISR.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 183
dsPIC30F1010/202X
Example 16-1 shows a code sequence for using the
ADBASE register to implement ADC Input Pair Inter-
rupt Handling. When the ADBASE register is read, it
contains the sum of the base address of the jump table
and the encoded ADC channel pair number left shifted
by 2 bits.
For example, if ADBASE is initialized with a value of
0x0360, a channel pair 1 interrupt would cause an
ADBASE read value of 0x0364 (0x360
+
0b00000100). A channel pair 3 interrupt would cause
an ADBASE read value of 0x036C (0x360
0b00001100).
+
EXAMPLE 16-1:
ADC BASE REGISTER CODE
; Initialize and enable the ADC interrupt
MOV
#handle(JMP_TBL),W0
; Load the base address of the ISR Jump
MOVWO, ADBASE
; table in ADBASE.
BSET
BSET
BSET
IPC2,#12
IPC2,#13
IPC2,#14
; Set up the interrupt priority
BCLR
BCLR
IFS0,#11
ADSTAT
; Clear any pending interrupts
; Clear the ADC pair interrupts as well
BSET
IEC0,#11
; Enable the interrupt
; Code to Initialize the rest of the ADC registers
...
...
...
; ADC Interrupt Handler
__ADCInterrupt:
PUSH.S
; Save WO-W3 and SR registers
BCLR
MOV
GOTO
IFSO,#11
ADBASE, W0
W0
; Clear the interrupt
; ADBASE contains the encoded jump address
; within JMP_TBL
; Here's the Jump Table
; Note: It is important to clear the individual IRQ flags in the ADC AFTER the IRQ flags
in the interrupt controller. Failure to do so may cause interrupt requests to be lost
JMP_TBL:
BCLR
BRA
ADSTAT,#0
ADC_PAIR0_PROC
; Clear the IRQ flag in the ADC
; Actual Pair 0 Conversion Interrupt Handler
BCLR
BRA
ADSTAT,#1
ADC_PAIR1_PROC
; Clear the IRQ flag in the ADC
; Actual Pair 1 Conversion Interrupt Handler
BCLR
BRA
ADSTAT,#2
ADC_PAIR2_PROC
; Clear the IRQ flag in the ADC
; Actual Pair 2 Conversion Interrupt Handler
BCLR
BRA
ADSTAT,#3
ADC_PAIR3_PROC
; Clear the IRQ flag in the ADC
; Actual Pair 3 Conversion Interrupt Handler
BCLR
BRA
ADSTAT,#4
ADC_PAIR4_PROC
; Clear the IRQ flag in the ADC
; Actual Pair 4 Conversion Interrupt Handler
DS70178C-page 184
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
EXAMPLE 16-1:
ADC BASE REGISTER CODE (CONTINUED)
; The actual pair conversion interrupt handler
; Don't forget to pop the stack when done and return from interrupt
ADC_PAIR0_PROC:
...
POP.S
RETFIE
; The ADC pair 0 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
ADC_PAIR1_PROC:
...
POP.S
RETFIE
; The ADC pair 1 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
ADC_PAIR2_PROC:
...
POP.S
RETFIE
; The ADC pair 2 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
ADC_PAIR3_PROC:
...
POP.S
RETFIE
; The ADC pair 3 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
ADC_PAIR4_PROC:
...
POP.S
RETFIE
; The ADC pair 4 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
ADC_PAIR5_PROC:
...
POP.S
RETFIE
; The ADC pair 5 conversion complete handler
; Restore W0-W3 and SR registers
; Return from Interrupt
Each ADC pair specified in the ADCPCx registers ini-
16.15 Changing A/D Clock
tiates a sample operation when the selected trigger
event occurs. The conversion of the sampled analog
data occurs as resources become available.
In general, the ADC cannot accept changes to the ADC
clock divisor while ADON = 1. If the user makes A/D
clock changes while ADON = 1, the results will be
indeterminate.
If a new trigger event occurs for a specific channel
before a previous sample and convert request for that
channel has been processed, the newer request is
ignored. It is the user’s responsibility not to exceed the
conversion rate capability for the module.
16.16 Sample and Conversion
The ADC module always assigns two ADC clock peri-
ods for the sampling process. When operating at the
maximum conversion rate of 2 Msps per channel, the
sampling period is:
The actual conversion process requires 10 additional
ADC clocks. The conversion is processed serially, bit 9
first, then bit 8, down to bit 0. The result is stored when
the conversion is completed.
2 x 41.6 nsec = 83.3 nsec.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 185
dsPIC30F1010/202X
fied of a pending request, then the conversion is
performed as the conversion resources become
available.
16.17 A/D Sample and Convert Timing
The sample and hold circuits assigned to the input pins
have their own timing logic that is triggered when an
external sample and convert request (from PWM or
TMR) is made. The sample and hold circuits have a
fixed two clock data sample period. When the sample
has been acquired, then the ADC control logic is noti-
The ADC module always converts pairs of analog input
channels, so a typical conversion process requires 24
clock cycles.
FIGURE 16-3:
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 0, NOT BUSY
adc_clk
TAD
sample_even
sample_odd
connect_first
connect_second
convert_en
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
capture_first_data
capture_second_data
state counter
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21
0
1
2
DS70178C-page 186
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 16-4:
adc_clk
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 1
TAD
sample_even
(1)
sample_odd
(2)
sample_odd
connectx_en
connect_second
connect_common
convert_en
Dependent on S&H availability
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
capture_first_data
capture_second_data
state counter
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22
23
0
Note 1: For all analog input pairs that do not have dedicated sample and hold circuits, the common sample and hold circuit
samples the input at the start of the first and second conversions. Therefore, the samples are sequential, not
simultaneous.
2: For all analog input pairs that have dedicated sample and hold circuits, the common sample and hold circuit samples
the input at the start of the first conversion so that both samples (odd and even) are near simultaneous.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 187
dsPIC30F1010/202X
16.18 Module Power-Down Modes
16.20 Configuring Analog Port Pins
The module has two internal power modes.
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins.
When the ADON bit is ‘1’, the module is in Active mode
and is fully powered and functional.
The port pins that are desired as analog inputs should
have their corresponding TRIS bit set (input). If the
TRIS bit is cleared (output), the digital output level (VOH
or VOL) will be converted.
When ADON is ‘0’, the module is in Off mode. The state
machine for the module is reset, as are all of the
pending conversion requests.
Port pins that are desired as analog inputs must have
the corresponding ADPCFG bit clear. This will config-
ure the port to disable the digital input buffer. Analog
levels on pins where ADPCFG<n> = 1, may cause the
digital input buffer to consume excessive current.
To return to the Active mode from Off mode, the user
must wait for the bias generators to stabilize. The
stabilization time is specified in the electrical specs.
16.19 Effects of a Reset
If a pin is not configured as an analog input
ADPCFG<n> = 1, the analog input is forced to AVss,
and conversions of that input do not yield meaningful
results.
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and sampling sequence is aborted. The
value that is in the ADCBUFx register is not modified.
When reading the PORT register, all pins configured as
analog input ADPCFG<n> = 0will read ‘0’.
The ADCBUFx registers contain unknown data after a
Power-on Reset.
The A/D operation is independent of the state of the
input selection bits and the TRIS bits.
16.21 Output Formats
The A/D converts 10 bits. The data buffer RAM is 16
bits wide. The ADC data can be read in one of two dif-
ferent formats, as shown in Figure 16-5. The FORM bit
selects the format. Each of the output formats
translates to a 16-bit result on the data bus.
DS70178C-page 188
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 16-5:
A/D OUTPUT DATA FORMAT
RAM contents:
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Fractional
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0
0
0
0
0
0
Integer
0
0
0
0
0
0
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 189
TABLE 16-1: ADC REGISTER MAP
File Name
ADR
0300
0302
0304
0306
0308
030A
Bit 15
ADON
—
Bit 14
—
Bit 13
ADSIDL
—
Bit 12
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
Bit 3
—
Bit 2
Bit 1
Bit 0
All Resets
0009
ADCON
—
GSWTRG
—
FORM
EIE
ORDER SEQSAMP
ADCS<2:0>
ADPCFG
Reserved
ADSTAT
ADBASE
ADCPC0
ADCPC1
ADCPC2
Reserved
0000
—
—
PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6
PCFG5
—
PCFG4
—
PCFG3
—
PCFG2 PCFG1 PCFG0
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
P5RDY
P4RDY
P3RDY
P2RDY P1RDY P0RDY
—
0000
ADBASE<15:1>
0000
IRQEN1 PEND1 SWTRG1
TRGSRC1<4:0>
TRGSRC3<4:0>
TRGSRC5<4:0>
—
IRQEN0 PEND0 SWTRG0
IRQEN2 PEND2 SWTRG2
IRQEN4 PEND4 SWTRG4
TRGSRC0<4:0>
0000
030C IRQEN3 PEND3 SWTRG3
TRGSRC2<4:0>
TRGSRC4<4:0>
—
0000
030E
IRQEN5 PEND5 SWTRG5
0000
0310
–
—-
—
—
—
—
—
—
—
—
—
—
—
—
—
031E
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADCBUF4
ADCBUF5
ADCBUF6
ADCBUF7
ADCBUF8
ADCBUF9
ADCBUF10
ADCBUF11
Reserved
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0320
0322
0324
0326
0328
032A
032C
032E
0330
0332
0334
0336
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 8
ADC Data Buffer 9
ADC Data Buffer 10
ADC Data Buffer 11
0338
—
—
—
—
—
—
—
—
—
—
– 037E
dsPIC30F1010/202X
• Programmable output polarity
• Interrupt generation capability
• Selectable Input sources
17.0 SMPS COMPARATOR MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
• DAC has three ranges of operation:
- AVDD / 2
- Internal Reference 1.2V 1%
- External Reference < (AVDD - 1.6V)
• ADC sample and convert trigger capability
• Can be disabled to reduce power consumption
• Functional support for PWM Module:
- PWM Duty Cycle Control
The dsPIC30F SMPS Comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
17.1 Features Overview
- PWM Period Control
• 16 comparator inputs
- PWM Fault Detect
• 10-bit DAC provides reference
FIGURE 17-1:
COMPARATOR MODULE BLOCK DIAGRAM
INSEL<1:0>
CMP A*
x
CMP B*
Trigger to PWM
Status
x
M
U
X
CMP C*
x
CMP D*
x
0
1
CMP *
x
Glitch Filter
Pulse Generator
* x=1, 2, 3 & 4
RANGE
CMPPOL
AVDD/2
M
U
X
Interrupt Request
INTREF
DAC
10
AVSS
CMREF
EXTREF
• Disable the PWM outputs (Fault-latch)
17.2 Module Applications
The output of the Comparator module may be used in
multiple modes at the same time, such as: (1) gener-
ate an interrupt, (2) have the ADC take a sample and
convert it and (3) truncate the PWM output in
response to a voltage being detected beyond its
expected value.
This module provides a means for the SMPS dsPIC
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC pro-
cessor and/or peripherals without requiring the proces-
sor and ADC to constantly monitor voltages or currents
frees the dsPIC DSC to perform other tasks.
The Comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
The Comparator module has a high-speed comparator
and an associated 10-bit DAC that provides a pro-
grammable reference voltage to one input of the com-
parator. The polarity of the comparator output is user
programmable. The output of the module can be used
in the following modes:
• Generate an interrupt
• Trigger an ADC sample and convert process
• Truncate the PWM signal (current limit)
• Truncate the PWM period (current minimum)
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 191
dsPIC30F1010/202X
17.3 Module Description
17.7 Comparator Input Range
The Comparator module uses a 20 nsec comparator.
The comparator offset is ±5 mV typical. The negative
input of the comparator is always connected to the
DAC circuit. The positive input of the comparator is
connected to an analog multiplexer that selects the
desired source pin.
The comparator has a limitation for the input Common
Mode Range (CMR) of about 3.5 volts (AVDD – 1.5
volts). This means that both inputs should not exceed
this value, or the comparator’s output will become
indeterminate. As long as one of the inputs is within
the Common Mode Range, the comparator output will
be correct. An input excursion into the CMR region will
not corrupt the comparator output, but the comparator
input is saturated.
17.4 DAC
The range of the DAC is controlled via an analog mul-
tiplexer that selects either AVDD/2, internal 1.2V 1%
reference, or an external reference source EXTREF.
The full range of the DAC (AVDD/2) will typically be
used when the chosen input source pin is shared with
the ADC. The reduced range option (INTREF) will
likely be used when monitoring current levels via a
CLx pin using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V), therefore the option of using a reduced ref-
erence range for the comparator extends the available
DAC resolution in these applications. The use of an
external reference enables the user to connect to a
reference that better suits their application.
17.8 DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AVDD - 1.6) volts. An external refer-
ence voltage input should not exceed this value or the
reference DAC output will become indeterminate.
17.9 Comparator Registers
The Comparator module is controlled by the following
registers:
• Comparator Control Registerx (CMPCONx)
• Comparator DAC Control Registerx (CMPDACx)
17.5 Interaction with I/O Buffers
If the comparator module is enabled and a pin has
been selected as the source for the comparator, then
the chosen I/O pad must disable the digital input buffer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
17.6 Digital Logic
The CMPCONx register (see Register 17-1) provides
the control logic that configures the Comparator mod-
ule. The digital logic provides a glitch filter for the com-
parator output to mask transient signals less than two
TCY (66 nsec) in duration. In Sleep or Idle mode, the
glitch filter is bypassed to enable an asynchronous
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
processor from Sleep or Idle mode.
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple com-
parators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
The digital logic also provides a one TCY width pulse
generator for triggering the ADC and generating
interrupt requests.
The CMPDACx (see Register 17-2) register provides
the digital input value to the reference DAC.
If the module is disabled, the DAC and comparator are
disabled to reduce power consumption.
DS70178C-page 192
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 17-1: COMPARATOR CONTROL REGISTERX (CMPCONx)
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
CMPON
CMPSIDL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
INSEL<1:0>
EXTREF
CMPSTAT
CMPPOL
RANGE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMPON: A/D Operating Mode bit
1= Comparator module is enabled
0= Comparator module is disabled (reduces power consumption)
bit 14
bit 13
Unimplemented: Read as ‘0’
CMPSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode.
0= Continue module operation in Idle mode.
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in
Idle mode.
bit 12-8
bit 7-6
Reserved: Read as ‘0’
INSEL<1:0>: Input Source Select for Comparator bits
00= Select CMPxA input pin
01= Select CMPxB input pin
10= Select CMPxC input pin
11= Select CMPxD input pin
bit 5
EXTREF: Enable External Reference bit
1= External source provides reference to DAC
0= Internal reference sources provide source to DAC
bit 4
bit 3
bit 2
bit 1
Reserved: Read as ‘0’
CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit
Reserved: Read as ‘0’
CMPPOL: Comparator Output Polarity Control bit
1= Output is inverted
0= Output is non inverted
bit 0
RANGE: Selects DAC Output Voltage Range bit
1= High Range: Max DAC value = AVDD / 2, 2.5V @ 5 volt VDD
0= Low Range: Max DAC value = INTREF, 1.2V ±1%
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 193
dsPIC30F1010/202X
REGISTER 17-2: COMPARATOR DAC CONTROL REGISTERX (CMPDACx)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CMREF<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMREF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Reserved: Read as ‘0’
These bits are reserved for possible future expansion of the DAC from 10 bits to more bits.
CMREF<9:0>: Comparator Reference Voltage Select bits
1111111111= (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on Range bit
·····
0000000000= 0.0 volts
DS70178C-page 194
Preliminary
© 2006 Microchip Technology Inc.
TABLE 17-1: ANALOG COMPARATOR CONTROL REGISTER MAP
File Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CMPON
CMPSIDL
INSEL<1:0>
INSEL<1:0>
EXTREF
CMPSTAT
CMPPOL RANGE
CMPPOL RANGE
CMPCON1
CMPDAC1
CMPCON2
CMPDAC2
CMPCON3
CMPDAC3
CMPCON4
CMPDAC4
04C0
04C2
04C4
04C6
04C8
04CA
04CC
04CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
CMREF<9:0>
—
—
CMPON
CMPSIDL
EXTREF
CMPSTAT
CMPSTAT
CMPSTAT
—
—
—
—
—
—
—
—
—
—
CMREF<9:0>
—
—
CMPON
CMPSIDL
INSEL<1:0>
INSEL<1:0>
EXTREF
CMPPOL RANGE
CMPPOL RANGE
—
CMREF<9:0>
—
—
CMPON
CMPSIDL
EXTREF
—
CMREF<9:0>
—
—
dsPIC30F1010/202X
NOTES:
DS70178C-page 196
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
18.1 Oscillator System Overview
18.0 SYSTEM INTEGRATION
The dsPIC30F oscillator system has the following
modules and features:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
For more information on the device instruction set and pro-
gramming, refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to boost internal operating
frequency
• A clock switching mechanism between various
clock sources
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection:
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• Oscillator Selection
• Reset:
• Clock Control register OSCCON
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT)
• Power-Saving modes (Sleep and Idle)
• Code Protection
• Configuration bits for main oscillator selection
Configuration bits determine the clock source upon
Power-on Reset (POR). Thereafter, the clock source
can be changed between permissible clock sources.
The OSCCON register controls the clock switching and
reflects system clock related status bits.
• Unit ID Locations
Note: 32 kHz crystal operation is not enabled on
dsPIC30F1010/202X devices.
• In-Circuit Serial Programming (ICSP)
programming capability
A simplified diagram of the oscillator system is shown
in Figure 18-1.
dsPIC30F devices have a Watchdog Timer, which can
be permanently enabled via the Configuration bits or
can be software controlled. It runs off its own RC oscil-
lator for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a delay
on power-up only, designed to keep the part in Reset
mode while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
18.2 Oscillator Control Registers
The oscillators are controlled with these registers:
• OSCCON: Oscillator Control Register
• OSCTUN2: Oscillator Tuning Register 2
• LFSR: Linear Feedback Shift Register
• FOSCSEL: Oscillator Selection Configuration Bits
• FOSC: Oscillator Selection Configuration Bits
Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
mode through external Reset, Watchdog Timer Wake-
up or through an interrupt. Several oscillator options
are also made available to allow the part to fit a wide
variety of applications. In the Idle mode, the clock
sources are still active, but the CPU is shut off. The RC
oscillator option saves system cost, while the LP crystal
option saves power.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 197
dsPIC30F1010/202X
FIGURE 18-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
Oscillator Configuration Bits
FPWM
PWRSAVInstruction
Wake-up Request
FPLL
x32
x16
OSC1
OSC2
Primary
Oscillator
PLL
PLL Lock
COSC<2:0>
NOSC<2:0>
OSWEN
Primary Osc
TUN<3:0>
4
Primary
Oscillator
Clock
Stability Detector
Switching
and Control
Block
Internal Fast RC
Oscillator (FRC)
Oscillator
Start-up
Timer
POR Done
System Clock FCY
Clock Dither
Circuit
Internal
Low-Power RC
Oscillator (LPRC)
CF
Oscillator Trap
Fail-Safe Clock
Monitor (FSCM)
FCKSM<1:0>
2
DS70178C-page 198
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 18-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0
R-y
HS,HC
R-y
HS,HC
R-y
HS,HC
U-0
—
R/W-y
R/W-y
R/W-y
—
COSC<2:0>
NOSC<2:0>
bit 15
bit 8
R/W-0
U-0
—
R-0
HS,HC
R/W-0
R/C-0
HS,HC
R/W-0
U-0
—
R/W-0
HC
CLKLOCK
LOCK
PRCDEN
CF
TSEQEN
OSWEN
bit 7
bit 0
Legend:
x = Bit is unknown
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HC = Cleared by hardware
HS = Set by hardware
-y = Value set from Configuration bits on POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Group Selection bits (read-only)
000= Fast RC Oscillator (FRC)
001= Fast RC Oscillator (FRC) with PLL Module
010= Primary Oscillator (HS, EC)
011= Primary Oscillator (HS, EC) with PLL Module
100= Reserved
101= Reserved
110= Reserved
111= Reserved
This bit is Reset upon:
Set to FRC value (‘000’) on POR
Loaded with NOSC<2:0> at the completion of a successful clock switch
Set to FRC value (‘000’) when FSCM detects a failure and switches clock to FRC
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Group Selection bits
000= Fast RC Oscillator (FRC)
001= Fast RC Oscillator (FRC) with PLL Module
010= Primary Oscillator (HS, EC)
011= Primary Oscillator (HS, EC) with PLL Module
100= Reserved
101= Reserved
110= Reserved
111= Reserved
bit 7
bit 6
CLKLOCK: Clock Lock Enabled bit
1= If (FCKSM1 = 1), then clock and PLL configurations are locked
If (FCKSM1 = 0), then clock and PLL configurations may be modified
0= Clock and PLL selection are not locked, configurations may be modified
Note:
Once set, this bit can only be cleared via a Reset.
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 199
dsPIC30F1010/202X
REGISTER 18-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 5
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock
0= Indicates that PLL is out of lock (or disabled)
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when PLL lock is achieved after a PLL start
Reset when lock is lost
Read zero when PLL is not selected as a Group 1 system clock
bit 4
bit 3
PRCDEN: Pseudo Random Clock Dither Enable bit
1= Pseudo random clock dither is enabled
0= Pseudo random clock dither is disabled
CF: Clock Fail Detect bit (read/clearable by application)
1= FSCM has detected clock failure
0= FSCM has NOT detected clock failure
This bit is Reset upon:
Reset on POR
Reset when a valid clock switching sequence is initiated by the clock switch state machine
Set when clock fail detected
bit 2
TSEQEN: FRC Tune Sequencer Enable bit
1= The TUN<3:0>, TSEQ1<3:0>, ... , TSEQ7<3:0> bits in the OSCTUN and the OSCTUN2 regis-
ters sequentially tune the FRC oscillator. Each field being sequentially selected via the
ROLL<2:0> signals from the PWM module.
0= The TUN<3:0> bits in OSCTUN register tunes the FRC oscillator
bit 1
bit 0
Unimplemented: Read as ‘0’
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<1:0> bits
0= Oscillator switch is complete
This bit is Reset upon:
Reset on POR
Reset after a successful clock switch
Reset after a redundant clock switch
Reset after FSCM switches the oscillator to (Group 3) FRC
DS70178C-page 200
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 18-2: OSCTUN: OSCILLATOR TUNING REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
TSEQ3<3:0>
TSEQ2<3:0>
R/W-0
TSEQ1<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
TUN<3:0>
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
TSEQ3<3:0>: Tune Sequence Value #3 bits
When PWM ROLL<2:0> = 011, this field is used to tune the FRC instead of TUN<3:0>
TSEQ2<3:0>: Tune Sequence Value #2 bits
When PWM ROLL<2:0> = 010, this field is used to tune the FRC instead of TUN<3:0>
TSEQ1<3:0>: Tune Sequence Value #1 bits
When PWM ROLL<2:0> = 001, this field is used to tune the FRC instead of TUN<3:0>
bit 3-0
TUN<3:0>: Specifies the user tuning capability for the internal fast RC oscillator . If the TSEQEN bit
in the OSCCON register is set, this field, along with bits TSEQ1-TSEQ7, will sequentially tune the
FRC oscillator.
0111= Maximum frequency
0110=
0101=
0100=
0011=
0010=
0001=
0000= Center frequency, oscillator is running at calibrated frequency
1111=
1110=
1101=
1100=
1011=
1010=
1001=
1000= Minimum frequency
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 201
dsPIC30F1010/202X
REGISTER 18-3: OSCTUN2: OSCILLATOR TUNING REGISTER 2
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
TSEQ7<3:0>
TSEQ6<3:0>
R/W-0
TSEQ5<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
TSEQ4<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
TSEQ7<3:0>: Tune Sequence value #7 bits
When PWM ROLL<2:0> = 111, this field is used to tune the FRC instead of TUN<3:0>
TSEQ6<3:0>: Tune Sequence value #6 bits
When PWM ROLL<2:0> = 110, this field is used to tune the FRC instead of TUN<3:0>
TSEQ5<3:0>: Tune Sequence value #5 bits
When PWM ROLL<2:0> = 101, this field is used to tune the FRC instead of TUN<3:0>
TSEQ4<3:0>: Tune Sequence value #4 bits
bit 3-0
When PWM ROLL<2:0> = 100, this field is used to tune the FRC instead of TUN<3:0>
REGISTER 18-4: LFSR: LINEAR FEEDBACK SHIFT REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
LFSR<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
LFSR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
When PWM ROLL<2:0> = 111, this field is used to tune the FRC instead of TUN<3:0>
LFSR <14:8>: Most Significant 7 bits of the pseudo random FRC trim value bits
LFSR <7:0>: Least Significant 8 bits of the pseudo random FRC trim value bits
bit 14-8
bit 7-0
DS70178C-page 202
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 18-5: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION BITS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P
R/P
FNOSC1
FNOSC0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-2
bit 1-0
Unimplemented: Read as ‘0’
FNOSC<1:0>: Initial Oscillator Group Selection on POR bits
00= Fast RC Oscillator (FRC)
01= Fast RC Oscillator (FRC) divided by N, with PLL module
10= Primary Oscillator (HS,EC)
11= Primary Oscillator (HS,EC) with PLL module
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 203
dsPIC30F1010/202X
REGISTER 18-6: FOSC: OSCILLATOR SELECTION CONFIGURATION BITS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R/P
R/P
R/P
U-0
—
U-0
—
R/P
R/P
R/P
FCKSM<1:0>
FRANGE
OSCIOFNC
POSCMD<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-8
bit 7-6
Unimplemented: Read as ‘0’
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x= Clock switching is disabled, fail-safe clock monitor is disabled
01= Clock switching is enabled, fail-safe clock monitor is disabled
00= Clock switching is enabled, fail-safe clock monitor is enabled
bit 5
FRANGE: Frequency Range Select for FRC and PLL bit
Acts like a “Gear Shift” feature that enables the dsPIC DSC device to operate at reduced MIPS at a
reduced supply voltage (3.3V)
FRANGE
Bit Value
Temperature
Rating
FRC Frequency
(Nominal)
PLL VCO
(Nominal)
1= High Range
Industrial
Extended
14.55 MHz
9.7 MHz
466 MHz (480 MHz max.)
310 MHz (320 MHz max.)
0= Low Range
Industrial
Extended
9.7 MHz
6.4 MHz
310 MHz (320 MHz max.)
205 MHz (211 MHz max.)
bit 4-3
bit 3
Unimplemented: Read as ‘0’
OSCIOFNC: OSC2 Pin I/O Enable bit
1= CLKO output signal active on the OSCO pin
0= CLKO output disabled
bit 1-0
POSCMD<1:0>: Primary Oscillator Mode
11= Primary Oscillator Disabled
10= HS oscillator mode selected
01= Reserved
00= External clock mode selected
DS70178C-page 204
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Assuming the high-range FRC option is selected on an
industrial temperature rated part, the 480 MHz PLL
clock signal is divided by 2, providing a 240 MHz signal,
which drives the ADC Module. The same 480 MHz sig-
nal is also divided by 8 to produce the 60 MHz signal,
which is one of the inputs to the FCY multiplexer. The
other input to this multiplexer is the FOSC input clock
source (either the Primary Oscillator or the FRC)
divided by 2. When the PLL is enabled, FCY = FPLL/16.
When the PLL is disabled, FCY = FOSC/2.
18.2.1
ACCIDENTAL WRITE PROTECTION
Because the OSCCON register allows clock switching
and clock scaling, a write to OSCCON is intentionally
made difficult. To write to the OSCCON low byte, this
exact sequence must be executed without any other
instructions in between:
• Byte Write “46h” to OSCCON low
• Byte Write “57h” to OSCCON low
• Byte Write is allowed for one instruction cycle
mov.b W0,OSCCON
This method derives the 480 MHz clock:
To write to the OSCCON high byte, this exact
sequence must be executed without any other instruc-
tions in between:
• FRC Clock with high-range Option and TUN<3:0>
= 0111is = 15 MHz
• PLL enabled
• Byte Write “78h” to OSCCON high
• Byte Write “9Ah” to OSCCON high
• PWM clock = 15 x 32 = 480 MHz
• FCY = 480 MHz/16 = 30 MHz = 30 MIPS
• Byte Write is allowed for one instruction cycle
mov.b W0,OSCCON + 1
If the PLL is disabled,
• FRC Clock (with high-range Option and
TUN<3:0> = 0111) is = 15MHz
18.3 Oscillator Configurations
• FCY = 15 MHz/2 = 7.5 MHz = 7.5 MIPS
Figure 18-2 shows the derivation of the system clock
FCY. The PLL in Figure 18-1 outputs a maximum fre-
quency of 480MHz (high-range FRC option for
industrial temperature parts with PLL and TUN<3:0> =
0111 bit settings). This signal is used by the Power
Supply PWM module, and is 32 times the input PLL fre-
quency.
FIGURE 18-2:
SYSTEM CLOCK AND FADC DERIVATION
PLL Enable
96-240 MHZ
24-60 MHZ
Divide
By 2
1
FADC
0
Divide
By 8
PLL – 192-480 MHZ
1
Divide
FPLL
FCY
By 2
0
Primary Oscillator
FRC
FOSC
PLL Enable
Oscillator Configuration Bits
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 205
dsPIC30F1010/202X
18.3.1
INITIAL CLOCK SOURCE
SELECTION
While coming out of a Power-on Reset, the device
selects its clock source based on:
a) FNOSC<1:0> Configuration bits that select one
of three oscillator groups (HS, EC or FRC)
b) POSCMD1<1:0> Configuration bits that select
the Primary Oscillator Mode
c) OSCIOFNC selects if the OSC2 pin is an I/O or
clock output
The selection is as shown in Table 18-1.
TABLE 18-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
FNOSC<1:0> POSCMD<1:0>
Oscillator
Mode
Oscillator
Source
OSC2
Function
OSC1
Function
OSCIOFNC
Bit 1
Bit 0
Bit 1
Bit 0
HS w/PLL 32x
PLL
PLL
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
N/A
1
CLKO(1)
CLKO
I/O
CLKI
I/O
FRC w/PLL 32x
FRC w/PLL 32x
EC w/PLL 32x
EC w/PLL 32x
EC(2)
EC(2)
HS(2)
PLL
0
I/O
PLL
1
CLKO
I/O
CLKI
CLKI
CLKI
CLKI
CLKI
I/O
PLL
0
External
External
External
Internal RC
Internal RC
1
CLKO
I/O
CLKO(1)
0
N/A
0
FRC(2)
FRC(2)
I/O
1
CLKO
I/O
Note 1: CLKO is not recommended to drive external circuits.
2: This mode is not recommended for some applications; disabling 32x PLL will not allow operation of
high-speed ADC and PWM.
18.3.2
OSCILLATOR START-UP TIMER
(OST)
TABLE 18-2: PLL FREQUENCY RANGE
PLL
FIN
FOUT
Multiplier
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscillator clock to the rest of the system. The time-out
period is designated as TOST. The TOST time is involved
every time the oscillator has to restart (i.e., on POR and
wake-up from Sleep). The Oscillator Start-up Timer is
applied to the HS Oscillator mode (upon
6.4 MHz
x32
x32
x32
205 MHz
310 MHz
466 MHz
9.7 MHz
14.55 MHz
The PLL features a lock output, which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
wake-up from Sleep and POR) for the primary
oscillator.
18.3.3
PHASE LOCKED LOOP (PLL)
The PLL multiplies the clock, which is generated by the
primary oscillator. The PLL is selectable to have a gain
of x32 only. Input and output frequency ranges are
summarized in Table 18-2.
DS70178C-page 206
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
18.4
PRIMARY OSCILLATOR ON OSC1/
OSC2 PINS:
The primary oscillator uses is shown in Figure 18-3.
FIGURE 18-3: PRIMARY OSCILLATOR
OSC1/CLKI
To CLKGEN
C1
C2
XTAL
(2)
RF
OSC2/CLKO
Rs (1)
CLKO/RC15
Note 1: A series resistor, Rs, may be required for AT strip cut crystals.
2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
In the EC with IO mode (Figure 18-5), the OSC1 pin
18.5
EXTERNAL CLOCK INPUT
can be driven by CMOS drivers. In this mode, the
OSC1 pin is high-impedance and the OSC2 pin
becomes a general purpose I/O pin. The feedback
device between OSC1 and OSC2 is turned off to save
current.
Two of the primary Oscillator modes use an external
clock. These modes are EC and EC with IO.
In the EC mode (Figure 18-4), the OSC1 pin can be
driven by CMOS drivers. In this mode, the OSC1 pin is
high-impedance and the OSC2 pin is the clock output
(FOSC/2). This output clock is useful for testing or
synchronization purposes.
FIGURE 18-4:
FIGURE 18-5:
EXTERNAL CLOCK INPUT OPERATION (EC OSCILLATOR CONFIGURATION)
Clock from Ext System
OSC1
OSC2
dsPIC30F
FOSC/2
EXTERNAL CLOCK INPUT OPERATION (ECIO OSCILLATOR CONFIGURATION)
Clock from Ext System
OSC1
dsPIC30F
I/O (OSC2)
I/O
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 207
dsPIC30F1010/202X
18.6.4 CLOCK DITHERING LOGIC
18.6
INTERNAL FAST RC OSCILLATOR
(FRC)
In power conversion applications, the primary electri-
cal noise emission that the designers want to reduce is
caused by the power transistors switching at the PWM
frequency. By changing the system clock frequency of
the SMPS dsPIC DSC, the resultant PWM frequency
will change and the peak EMI will be reduced at the
noise is spread over a wider frequency range.
Typically, the range of frequency variation is few
percent. The dsPIC30F1010/202X can provide two
ways to vary system clock frequency on a PWM cycle
basis. These are Frequency Sequencing mode and
Pseudo Random Clock Dithering mode. Table 18-8
shows the implementation details of both these
methods.
FRC is a fast, precise frequency internal RC oscillator.
The FRC oscillator is designed to run at a frequency of
6.4/9.7/14.55 MHz (<±2% accuracy). The FRC oscilla-
tor option is intended to be accurate enough to provide
the clock frequency necessary to maintain baud rate
tolerance for serial data transmissions. The user has
the ability to tune the FRC frequency by +-3%.
The FRC oscillator is powered:
a) Any time the EC or HS Oscillator modes are
NOT selected.
b) When the fail-safe clock monitor is enabled and
a clock fail is detected, forcing a switch to FRC.
18.6.1 FREQUENCY RANGE SELECTION
18.6.5
FREQUENCY SEQUENCING MODE
The Frequency Sequencing mode enables the PWM
module to select a sequence of eight different FRC
TUN values to vary the system frequency with each
rollover of the primary PWM time base. The OSCTUN
and the OSCTUN2 registers allow the user to specify
eight sequential tune values if the TSEQEN bit is set in
the OSCCON register. If the TSEQEN bit is zero, then
only the TUN bits affect the FRC frequency.
The FRC module has a “Gear Shift” control signal that
selects low range (9.7 MHz for industrial temperature
rated parts and 6.4 MHz for extended temperature
rated parts) or high range (14.55 MHz for industrial
temperture rated parts and 9.7 MHz for extended tem-
perature rated parts) frequency of operation. This fea-
ture enables a dsPIC DSC device to operate up to a
maiximum speed of 20 MIPS at 3.3V or up to a maxi-
mum speed of 30 MIPS at 5.0V and remain with
system specifications.
A 4-bit wide multiplexer with eight sets of inputs
selects the tuning value from the TUN and the TSEQx
bit fields. The multiplexer is controlled by the
ROLL<5:3> counter in the PWM module. The
ROLL<5:3> counter increments every time the primary
time base rolls over after reaching the period value.
18.6.2 NOMINAL FREQUENCY VALUES
The FRC module is calibrated to a nominal 9.7 MHz
for industrial temperature rated parts and 6.4 MHz for
extended temperature rated parts in low range and
14.55 MHz for industrial temperture rated parts and
9.7 MHz for extended temperature rated parts in high
range This feature enables a user to “tune” the dsPIC
DSC device frequency of operation by +-3% and still
remain within system specifications.
18.6.6
PSEUDO RANDOM CLOCK
DITHERING MODE
The Pseudo Random Clock Dither (PRCD) logic is
implemented with a 15-bit LFSR (Linear Feedback
Shift Register), which is a shift register with a few
exclusive OR gates. The lower four bits of the LFSR
provides the FRC TUNE bits. The PRCD feature is
enabled by setting the PRCDEN bit in the OSCCON
register. The LSFR is “clocked” (enabled to clock)
once every time the ROLL<3> bit changes state,
which occurs once every 8 PWM cycles.
18.6.3 FRC FREQUENCY USER TUNING
The FRC is calibrated at the factory to give a nominal
6.4/9.7/14.55 MHz. The TUN<3:0> field in the OSC-
TUN register is available to the user for trimming the
FRC oscillator frequency in applications.
The 4-bit tuning control signals are supplied by the
OSCTUN or the OSCTUN2 registers depending on
the TSEQEN bit in the OSCCON register.
18.6.7
FAIL-SAFE CLOCK MONITOR
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM Configuration bits (Clock
Switch and Monitor Selection bits) in the FOSC
Configuration register.
The tuning range of the 14.55 MHz oscillator is
±0.45 MHz (±3%) nominal.
The base frequency can be tuned in the user's appli-
cation. This frequency tuning capability allows the user
to deviate from the factory calibrated frequency. The
user can tune the frequency by writing to the OSCTUN
register TUN<3:0> bits.
In the event of an oscillator failure, the FSCM will
generate a clock failure trap event and will switch the
system clock over to the FRC oscillator. The user will
then have the option to either attempt to restart the
oscillator or execute a controlled shutdown. The user
may decide to treat the trap as a warm Reset by sim-
DS70178C-page 208
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
ply loading the Reset address into the oscillator fail
trap vector. In this event, the CF (Clock Fail) status bit
(OSCCON<3>) is also set whenever a clock failure is
recognized.
18.7 Reset
The PIC18F1220/1320 differentiates between
various kinds of Reset:
a) Power-on Reset (POR)
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
If the oscillator has a very slow start-up time coming
out of POR or Sleep, it is possible that the PWRT timer
will expire before the oscillator has started. In such
cases, the FSCM will be activated and the FSCM will
initiate a clock failure trap, and the COSC<2:0> bits
are loaded with FRC oscillator selection. This will
effectively shut off the original oscillator that was trying
to start.
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) RESETInstruction
f) Reset cause by trap lock-up (TRAPR)
g) Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
The user may detect this situation and restart the
oscillator in the clock fail trap, ISR.
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up, since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 18-3. These bits are
used in software to determine the nature of the Reset.
Upon a clock failure detection, the FSCM module will
initiate a clock switch to the FRC oscillator as follows:
1. The COSC bits (OSCCON<14:12>) are loaded
with the FRC oscillator selection value
2. CF bit is set (OSCCON<3>)
A block diagram of the on-chip Reset circuit is shown in
Figure 18-7.
3. OSWEN control bit (OSCCON<0>) is cleared
For the purpose of clock switching, the clock sources
are sectioned into two groups:
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
1. Primary
Internally generated Resets do not drive MCLR pin low.
2. Internal FRC
The user can switch between these functional groups,
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FNOSC<1:0>
Configuration bits.
The OSCCON register holds the control and status bits
related to clock switching. If Configuration bits
FCKSM<1:0> = 1x, then the clock switching and Fail-
Safe Clock Monitor functions are disabled. This is the
default Configuration bit setting.
If clock switching is disabled, then the FNOSC<1:0>
and POSCMD<1:0> bits directly control the oscillator
selection and the COSC<2:0> bits do not control the
clock selection. However, these bits will reflect the
clock source selection.
Note:
The application should not attempt to
switch to a clock frequency lower than 100
KHz when the Fail-Safe Clock Monitor is
enabled. If clock switching is performed,
the device may generate an oscillator fail
trap and switch to the Fast RC oscillator.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 209
dsPIC30F1010/202X
FIGURE 18-6:
FRC TUNE DITHER LOGIC BLOCK DIAGRAM
PWM PS
ROLL Counter
ROLL<5:3>
ROLL<2:0>
3
Shift Enable for LFSR
ROLL<3>
TSEQEN in OSCCON
D
Q
15
12 11 OSCTUN 4 3
0
CLK
TSEQ3 TSEQ2 TSEQ1 TUN
0
1
2
3
4
5
PRCDEN in OSCCON
4
4
0
1
4
TUNE BIts to FRC
6
8
12 11
7
3
0
15
TSEQ7 TSEQ6 TSEQ5
TSEQ4
All Zero Detect
OSCTUN2
LFSR
4
15
D
D
Q0
Q
Q1
Q
D
Q2
Q
D
Q3
Q
D
Q4
D
Q5
Q
D
Q6
D
Q7
Q
D
Q8
Q
D
Q9
Q
D
Q10
D
Q11
D
Q12
D
Q13
D
Q14
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Q
Q
Q
Q
Q
Q
Q
FIGURE 18-7:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
POR
VDD Rise
Detect
S
VDD
R
Q
SYSRST
Trap Conflict
Illegal Opcode/
Uninitialized W Register
DS70178C-page 210
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected power-
up time-out (TPWRT) is applied. The TPWRT parameter
is based on Configuration bits and can be 0 ms (no
delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
18.7.1
POR: POWER-ON RESET
A power-on event will generate an internal POR pulse
when a VDD rise is detected. The Reset pulse will occur
at the POR circuit threshold voltage (VPOR), which is
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 18-8 through Figure 18-10.
FIGURE 18-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
TOST
OST Time-out
TPWRT
PWRT Time-out
Internal Reset
FIGURE 18-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
TOST
OST Time-out
TPWRT
PWRT Time-out
Internal Reset
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 211
dsPIC30F1010/202X
FIGURE 18-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
Internal POR
TOST
OST Time-out
TPWRT
PWRT Time-out
Internal Reset
18.7.1.1
POR with Long Crystal Start-up Time
(with FSCM Enabled)
FIGURE 18-11:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially low
frequency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the POR timer and the PWRT have
expired:
VDD
D
R
R1
MCLR
dsPIC30F
C
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has NOT expired (if
a crystal oscillator is used).
Note 1: External Power-on Reset circuit is
required only if the VDD power-up slope
is too slow. The diode D helps discharge
the capacitor quickly when VDD powers
down.
• The PLL has not achieved a LOCK (if PLL is
used).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap, ISR.
2: R should be suitably chosen so as to
make sure that the voltage drop across
R does not violate the device’s electrical
specification.
18.7.1.2
Operating without FSCM and PWRT
3: R1 should be suitably chosen so as to
limit any current flowing into MCLR from
external capacitor C, in the event of
MCLR/VPP pin breakdown due to Elec-
trostatic Discharge (ESD) or Electrical
Overstress (EOS).
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device will exit rap-
idly from Reset on power-up. If the clock source is FRC
or EC, it will be active immediately.
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
Note:
Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
DS70178C-page 212
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Table 18-3 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 18-3: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Program
Condition
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP
POR
Counter
Power-on Reset
0x000000
0x000000
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
MCLR Reset during normal
operation
Software Reset during
normal operation
0x000000
0
0
0
1
0
0
0
0
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
0x000000
0x000000
0x000000
PC + 2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
Interrupt Wake-up from
Sleep
PC + 2(1)
Clock Failure Trap
Trap Reset
0x000004
0x000000
0x000000
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Illegal Operation Trap
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 18-4 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 18-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Program
Condition
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP
POR
Counter
Power-on Reset
0x000000
0x000000
0
u
0
u
0
1
0
0
0
0
0
0
0
0
1
u
MCLR Reset during normal
operation
Software Reset during
normal operation
0x000000
u
u
0
1
0
0
0
u
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
0x000000
0x000000
0x000000
PC + 2
u
u
u
u
u
u
u
u
u
u
1
1
0
u
u
u
u
0
u
u
0
0
1
1
u
0
1
0
u
u
1
0
0
1
1
u
u
u
u
u
Interrupt Wake-up from
Sleep
PC + 2(1)
Clock Failure Trap
Trap Reset
0x000004
0x000000
0x000000
u
1
u
u
u
1
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Illegal Operation Reset
Legend: u= unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 213
dsPIC30F1010/202X
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
18.8
Watchdog Timer (WDT)
18.8.1
WATCHDOG TIMER OPERATION
• any interrupt that is individually enabled and
meets the required priority level
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer, which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
• any Reset (POR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry
into Sleep mode. When clock switching is enabled,
bits COSC<2:0> will determine the oscillator source
that will be used on wake-up. If clock switch is
disabled, then there is only one system clock.
18.8.2
ENABLING AND DISABLING THE
WDT
Note:
If a POR occurred, the selection of the
oscillator is based on the FOSC<2:0> and
FOSCSEL<1:0> Configuration bits.
The Watchdog Timer can be “enabled” or “disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register FWDT.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a sta-
ble oscillator). If PLL is used, the system clock is held
off until LOCK = 1 (indicating that the PLL is stable).
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip-erase, FWDTEN bit = 1. Any
device programmer capable of programming
dsPIC30F devices allows programming of this and
other Configuration bits.
Either way, TPOR, TLOCK and TPWRT delays are applied
.
If EC, FRC, oscillators are used, then a delay of TPOR
(~10 μs) is applied. This is the smallest delay possible
on wake-up from Sleep.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
Moreover, if LP oscillator was active during Sleep, and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to TPOR. PWRT delay and OST
timer delay are not applied. In order to have the small-
est possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
If a WDT times out during Sleep, the device will wake-
up. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. The proces-
sor will process the interrupt and branch to the ISR. The
Sleep status bit in the RCON register is set upon
18.9 Power-Saving Modes
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
wake-up
.
Note:
In spite of various delays applied (TPOR
,
These are: Sleep and Idle.
TLOCK and TPWRT), the crystal oscillator
The format of the PWRSAVinstruction is as follows:
(and PLL) may not be active at the end of
the time-out (e.g., for low frequency crys-
tals). In such cases, if FSCM is enabled, the
device will detect this as a clock failure and
process the clock failure trap, the FRC
oscillator will be enabled, and the user will
have to re-enable the crystal oscillator. If
FSCM is not enabled, then the device will
simply suspend execution of code until the
clock is stable, and will remain in Sleep until
the oscillator clock has started.
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
18.9.1
SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is
shutdown. If an on-chip oscillator is being used, it is
shutdown.
The Fail-Safe Clock Monitor is not functional during
Sleep, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
All Resets will wake-up the processor from Sleep
mode. Any Reset, other than POR, will set the Sleep
status bit. In a POR, the Sleep bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO status bits are both set.
DS70178C-page 214
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
18.9.2
IDLE MODE
18.10 Device Configuration Registers
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are six
Configuration registers available to the user:
Several peripherals have a control bit in each module
that allows them to operate during Idle.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
1. FBS (0xF80000): Boot Code Segment
Configuration Register
• on any interrupt that is individually enabled (IE bit
is ‘1’) and meets the required priority level
2. FGS (0xF80004): General Code Segment
Configuration Register
• on any Reset (POR, MCLR)
• on WDT time-out
3. FOSCEL (0xF80006): Oscillator Selection
Configuration Register
Upon wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction.
4. FOSC (0xF80008): Oscillator Configuration
Register
5. FWDT (0xF8000A): Watchdog Timer
Configuration Register
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle status bit in
RCON register is set upon wake-up.
6. FPOR (0xF8000C): Power-On Reset
Configuration Register
The placement of the Configuration bits is automati-
cally handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For addi-
tional information, please refer to the programming
specifications of the device.
Any Reset, other than POR, will set the Idle status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
Note:
If the code protection configuration fuse
bits (GSS<1:0> and GWRP in the FGS
register) have been programmed, an
erase of the entire code-protected device
is only possible at voltages VDD ≥ 4.5V.
Table 18-5 shows the bit descriptions of the FGS and
FBS registers for the dsPIC30F1010. Table 18-6
shows the bit descriptions of the FGS and FBS regis-
ters for dsPIC30F202x devices. Table 18-7 shows the
bit descriptions of FWDT and the FPOR registers for
dsPIC30F1010/202X devices.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 215
dsPIC30F1010/202X
TABLE 18-5: FGS AND FBS BIT DESCRIPTIONS FOR THE dsPIC30F1010
Bit Field
BWRP
Register
Description
FBS
Boot Segment Program Flash Write Protection
1= Boot segment may be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Boot Segment Program Flash Code Protection Size
x11= No boot program Flash segment
x00= No boot program Flash segment
x01= No boot program Flash segment
110= Standard security; small boot segment; boot program Flash seg-
ment starts at the end of the Interrupt Vector Segment and ends
at 0003FFH
010= High security; small boot segment; boot program Flash segment
starts at the end of the Interrupt Vector Segment and ends at
0003FFH
GRWP
FGS
FGS
General Segment Program Flash Write Protection
1= General segment may be written
0= General segment is write-protected
GSS<1:0>
General Segment Program Flash Code Protection
11= No Protection
10= Standard security; general program Flash segment starts at the
end of the boot segment and ends at the end of program Flash
0x= Reserved
TABLE 18-6: FGS AND FBS BIT DESCRIPTIONS FOR THE dsPIC30F202X
Bit Field
BWRP
Register
Description
FBS
Boot Segment Program Flash Write Protection
1= Boot segment may be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Boot Segment Program Flash Code Protection Size
x11= No boot program Flash segment
x00= No boot program Flash segment
110= Standard security; small boot segment; boot program Flash seg-
ment starts at the end of the Interrupt Vector Segment and ends
at 0003FFH
010= High security; small boot segment; boot program Flash segment
starts at the end of the Interrupt Vector Segment and ends at
0003FFH
101= Standard security; medium boot segment; boot program Flash
segment starts at the end of the Interrupt Vector Segment and
ends at 000FFFH
001= High security; medium boot segment; boot program Flash seg-
ment starts at the end of the Interrupt Vector Segment and ends
at 000FFFH
GWRP
FGS
FGS
General Segment Program Flash Write Protection
1= General segment may be written
0= General segment is write-protected
GSS<1:0>
General Segment Program Flash Code Protection
11= No Protection
10= Standard security; general program Flash segment starts at the
end of the Boot Segment and ends at the end of program Flash
0x= Reserved
DS70178C-page 216
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 18-7: FWDT AND FPOR BIT DESCRIPTIONS FOR dsPIC30F1010/202X
Bit Field
FWDTEN
Register
Description
FWDT
Watchdog Timer Enable bit
1= Watchdog Timer always enabled. (LPRC oscillator cannot be dis-
abled. Clearing the SWDTEN bit in the RCON register will have no
effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WWDTEN
FWDT
FWDT
FWDT
Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111= 1:32, 768
1110= 1:16, 384
.
.
.
0001= 1:2
0000= 1:1
FPWRT<2:0>
FPOR
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
18.11 In-Circuit Debugger
This gives rise to two possibilities:
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. When the device has this feature enabled,
some of the resources are not available for general
use. These resources include the first 80 bytes of data
RAM and two I/O pins.
1. If EMUD/EMUC is selected as the debug I/O pin
pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are multi-
plexed with the PGD and PGC pin functions in
all dsPIC30F devices.
2. If EMUD1/EMUC1 or EMUD2/EMUC2 is
selected as the debug I/O pin pair, then a 7-pin
interface is required, as the EMUDx/EMUCx pin
functions (x = 1 or 2) are not multiplexed with the
PGD and PGC pin functions.
One of four pairs of Debug I/O pins may be selected by
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1 and EMUD2/EMUC2.
In each case, the selected EMUD pin is the Emulation/
Debug Data line, and the EMUC pin is the Emulation/
Debug Clock line. These pins will interface to the
MPLAB ICD 2 module available from Microchip. The
selected pair of Debug I/O pins is used by
MPLAB ICD 2 to send commands and receive
responses, as well as to send and receive data. To use
the in-circuit debugging function of the device, the
design must implement ICSP connections to MCLR,
VDD, VSS, PGC, PGD and the selected
EMUDx/EMUCx pin pair.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 217
TABLE 18-8: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F202X
SFR
Name
Addr
.
Bit 15
Bit 14
Bit 13 Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
RCON
0740 TRAPR IOPUWR
—
—
—
—
—
—
—
EXTR
SWR SWDTEN
LOCK
WDTO
SLEEP
CF
IDLE
—
—
POR
Depends on type of Reset.
OSCCON
OSCTUN
0742
0748
—
COSC<2:0>
TSEQ3<3:0>
TSEQ7<3:0>
NOSC<2:0>
CLKLOCK
—
PRCDEN
TSEQEN
OSWEN Depends on Configuration bits.
0000 0000 0000 0000
TSEQ2<3:0>
TSEQ6<3:0>
TSEQ1<3:0>
TSEQ5<3:0>
TUN<3:0>
TSEQ4<3:0>
0000 0000 0000 0000
0000 0000 0000 0000
OSCTUN2 074A
LFSR
PMD1
PMD2
PMD3
Note:
074C
0770
0772
0774
—
—
—
—
LFSR<14:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
—
—
T3MD T2MD
T1MD
—
—
—
—
PWMMD
—
IC1MD
—
I2CMD
—
—
—
—
U1MD
—
—
—
—
SPI1MD
—
—
—
—
ADCMD
—
—
—
—
—
—
—
—
OC2MD OC1MD
—
—
—
—
CMP_PSMD
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
TABLE 18-9: DEVICE CONFIGURATION REGISTER MAP
File Name
Addr.
Bits 23-16
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FBS
F80000
F80004
F80006
F80008
F8000A
F8000C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BSS<2:0>
GSS1
—
BWRP
FGS
—
—
—
—
GSS0 GWRP
FNOSC<1:0>
FOSCSEL
FOSC
—
FRANGE
—
FCKSM<1:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
FWDT
FPOR
FWDTEN WWDTEN
WDTPRE
—
—
—
—
—
FPWRT<2:0>
Note:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
19.0 INSTRUCTION SET SUMMARY
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
• The W register (with or without an address modi-
fier) or file register (specified by the value of ‘Ws’
or ‘f’)
• The bit in the W register or file register
(specified by a literal value, or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
The dsPIC30F instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from PIC
MCU instruction sets.
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction.
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions may use some of the
following operands:
• DSP operations
• The accumulator (A or B) to be used (required
operand)
• Control operations
Table 19-1 shows the general symbols used in
describing the instructions.
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The dsPIC30F instruction set summary in Table 19-2
lists all the instructions along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication, and may include:
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The accumulator to be used (required)
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The amount of shift, specified by a W register
‘Wn’ or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands:
• A program memory address
• The file register specified by the value ‘f’
• The mode of the Table Read and Table Write
instructions
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
All instructions are a single word, except for certain
double word instructions, which were made double
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 219
dsPIC30F1010/202X
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all
Table Reads and Writes and RETURN/RETFIEinstruc-
tions, which are single-word instructions, but take two
or three cycles. Certain instructions that involve
skipping over the subsequent instruction, require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-
word or two-word instruction. Moreover, double word
moves require two cycles. The double word
instructions execute in two instruction cycles.
Note:
For more details on the instruction set,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
(text)
[text]
{
}
<n:m>
.b
Byte mode selection
.d
Double Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator write back destination address register ∈ {W13, [W13] + = 2}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
lit14
lit16
lit23
None
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’
Field does not require an entry, may be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
DS70178C-page 220
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wb
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wm*Wm
Dividend, Divisor working register pair (direct addressing)
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] – = 6, [W8] – = 4, [W8] – = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] – = 6, [W9] – = 4, [W9] – = 2,
[W9 + W12],none}
Wxd
Wy
X data space prefetch destination register for DSP instructions ∈ {W4..W7}
Y data space prefetch address register for DSP instructions
∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] – = 6, [W11] – = 4, [W11] – = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions ∈ {W4..W7}
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 221
dsPIC30F1010/202X
TABLE 19-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
# of
word
s
Assembly
Mnemonic
# of
cycles
Status Flags
Affected
Assembly Syntax
Description
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTSC
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
Wd = Wb + Ws
Wd = Wb + lit5
16-bit Signed Add to Accumulator
f = f + WREG + (C)
2
3
4
ADDC
AND
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
f = f .AND. WREG
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
N,Z
N,Z
Wd = Wb .AND. lit5
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
N,Z
5
6
BCLR
BRA
None
Bit Clear Ws
None
Branch if Carry
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
Branch if unsigned less than
Branch if Negative
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if accumulator A overflow
Branch if accumulator B overflow
Branch if Overflow
Branch if accumulator A saturated
Branch if accumulator B saturated
Branch Unconditionally
Branch if Zero
2
None
Z,Expr
1 (2) None
Wn
Computed Branch
2
1
1
1
1
1
1
None
None
None
None
None
None
None
None
7
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
Bit Set Ws
8
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
Ws,Wb
9
BTG
f,#bit4
Ws,#bit4
f,#bit4
Bit Toggle Ws
10
BTSC
Bit Test f, Skip if Clear
1
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
DS70178C-page 222
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
word
s
Assembly
Mnemonic
# of
cycles
Status Flags
Affected
Assembly Syntax
Description
Bit Test f, Skip if Set
11
12
BTSS
BTST
BTSS
BTSS
f,#bit4
1
1
None
None
(2 or 3)
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
C
Ws,Wb
Z
13
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ≠
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f –1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
WREG = f –1
1
DEC
Ws,Wd
Wd = Ws – 1
1
27
DEC2
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
f
f = f –2
1
f,WREG
WREG = f – 2
1
Ws,Wd
Wd = Ws – 2
1
28
29
DISI
DIV
#lit14
Disable Interrupts for k instruction cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit14 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
1
Wm,Wn
18
18
18
18
18
2
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
N,Z,C, OV
None
Wm,Wn
Wm,Wn
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
Wm * Wm,Acc,Wx,Wy,Wxd
DO
2
None
32
33
ED
ED
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm * Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 223
dsPIC30F1010/202X
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
word
s
Assembly
Mnemonic
# of
cycles
Status Flags
Affected
Assembly Syntax
Description
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
C
C
C
None
Wn
Go to indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link frame pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
f
f = Logical Right Shift f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Multiply and Accumulate
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm *
OA,OB,OAB,
SA,SB,SAB
Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
MAC
Wm *
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
Wm,Acc,Wx,Wxd,Wy,Wyd
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
None
None
None
None
N,Z
MOV.b
MOV
MOV
Wso,Wdo
WREG,f
Move Ws to Wd
MOV
Move WREG to f
MOV.D
MOV.D
MOVSAC
MPY
Wn,Acc,Wx,Wxd,Wy,Wyd
MPY Wm *
Wm,Acc,Wx,Wxd,Wy,Wyd
MPY.N Wm *
Wn,Acc,Wx,Wxd,Wy,Wyd
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Prefetch and store accumulator
Multiply Wm by Wn to Accumulator
None
None
None
Ws,Wnd
47
48
MOVSAC
MPY
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm *
OA,OB,OAB,
SA,SB,SAB
Square Wm to Accumulator
1
1
1
1
1
1
OA,OB,OAB,
SA,SB,SAB
49
50
MPY.N
MSC
-(Multiply Wm by Wn) to Accumulator
Multiply and Subtract from Accumulator
None
MSC
Wm *
OA,OB,OAB,
SA,SB,SAB
Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
f
W3:W2 = f * WREG
1
1
None
DS70178C-page 224
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
word
s
Assembly
Mnemonic
# of
cycles
Status Flags
Affected
Assembly Syntax
Acc
Description
Negate Accumulator
52
NEG
NEG
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
2
All
55
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
None
None
None
PUSH
Wso
Wns
PUSH.D
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
Push Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
None
56
57
PWRSAV
RCALL
#lit1
Go into Sleep or Idle mode
Relative Call
WDTO,Sleep
None
Expr
Wn
Computed Call
None
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
None
None
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
None
Return from interrupt
3 (2) None
3 (2) None
3 (2) None
#lit10,Wn
Return with literal in Wn
Return from Subroutine
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,N,Z
C,N,Z
C,N,Z
N,Z
RLC
f,WREG
RLC
Ws,Wd
64
65
66
67
RLNC
RRC
RLNC
RLNC
RLNC
RRC
f
f,WREG
N,Z
Ws,Wd
N,Z
f
C,N,Z
C,N,Z
C,N,Z
N,Z
RRC
f,WREG
RRC
Ws,Wd
RRNC
SAC
RRNC
RRNC
RRNC
SAC
f
f,WREG
N,Z
Ws,Wd
N,Z
Acc,#Slit4,Wdo
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = sign extended Ws
f = 0xFFFF
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
71
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
SL
SL
SL
SL
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
WREG = Left Shift f
Wd = Left Shift Ws
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
N,Z
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 225
dsPIC30F1010/202X
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
# of
word
s
Assembly
Mnemonic
# of
cycles
Status Flags
Affected
Assembly Syntax
Acc
Description
Subtract Accumulators
72
SUB
SUB
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
SUB
SUB
Wd = Wb – Ws
SUB
Wd = Wb – lit5
73
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
f = f – WREG – (C)
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
74
75
76
SUBR
SUBBR
SWAP
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
f = WREG – f – (C)
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
Wd = lit5 – Wb – (C)
Wn = nibble swap Wn
Wn = byte swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink frame pointer
f = f .XOR. WREG
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
Wn
None
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
None
XOR
f
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
Wnd = Zero-Extend Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
N,Z
83
ZE
ZE
C,Z,N
DS70178C-page 226
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
20.1 MPLAB Integrated Development
Environment Software
20.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 227
dsPIC30F1010/202X
20.2 MPASM Assembler
20.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
20.6 MPLAB SIM Software Simulator
20.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 family of microcontrollers and the
dsPIC30, dsPIC33 and PIC24 family of digital signal
controllers. These compilers provide powerful integra-
tion capabilities, superior code optimization and ease
of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
20.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS70178C-page 228
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
20.7 MPLAB ICE 2000
High-Performance
20.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
20.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
20.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 229
dsPIC30F1010/202X
20.11 PICSTART Plus Development
Programmer
20.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
20.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS70178C-page 230
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
21.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”
(DS70046).
Absolute maximum ratings for the device family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)(1)................................................ -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS(1) ......................................................................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................300 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 21-2.
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
21.1
DC Characteristics
TABLE 21-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
Temp Range
dsPIC30FXXX-30I
dsPIC30FXXX-20E
4.5-5.5V
4.5-5.5V
3.0-3.6V
3.0-3.6V
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
30
—
20
—
—
20
—
15
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 231
dsPIC30F1010/202X
TABLE 21-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
dsPIC30F1010/202X-30I
Operating Junction Temperature Range
Operating Ambient Temperature Range
dsPIC30F1010/202X-20E
TJ
TA
-40
-40
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
+150
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD × (IDD –
)
IOH
∑
PD
PINT + PI/O
(TJ - TA) / θJA
Max
W
W
I/O Pin power dissipation:
=
({ VDD – VOH} × IOH ) +
(
)
VOL × IOL
PI/O
∑
∑
Maximum Allowed Power Dissipation
PDMAX
TABLE 21-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Unit
Notes
Package Thermal Resistance, 28-pin SOIC (SO)
Package Thermal Resistance, 28-pin QFN
Package Thermal Resistance, 28-pin SPDIP (SP)
Package Thermal Resistance, 44-pin QFN
Package Thermal Resistance, 44-pin TQFP
θJA
θJA
θJA
θJA
θJA
48.3
33.7
42
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
1, 2
1, 2
28
39.3
Note 1: Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.
2: Depending on operating conditions, air flow may be required for improved thermal performance.
TABLE 21-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1) Max Units
Conditions
Operating Voltage(2)
DC10
DC11
DC12
DC16
VDD
VDD
VDR
VPOR
Supply Voltage
3.0
3.0
—
—
—
5.5
5.5
—
V
V
V
V
Industrial temperature
Extended temperature
Supply Voltage
RAM Data Retention Voltage(3)
1.5
VSS
VDD Start Voltage
to ensure internal
—
—
Power-on Reset signal
DC17
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms 0-5V in 0.1 sec
0-3.3V in 60 ms
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: This is the limit to which VDD can be lowered without losing RAM data.
DS70178C-page 232
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Operating Current (IDD)(2)
DC20a
DC20b
DC20c
DC20d
DC20e
DC20f
DC22a
DC22b
DC22c
DC22d
DC22e
DC22f
DC23a
DC23b
DC23c
DC23d
DC23e
DC23f
DC24a
DC24b
DC24c
DC24d
DC24e
DC24f
DC26a
DC26b
DC26d
DC26e
DC26f
DC27d
DC27e
13
14
16
16
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
14
17
FRC 3.2 MIPS, PLL disabled
22
26
22
26
22
27
19
22
19
23
3.3V
5V
19
23
FRC, 4.9 MIPS, PLL disabled
FRC, 7.3 MIPS, PLL disabled
FRC 13 MIPS, PLL enabled
30
36
30
37
31
37
27
33
28
33
3.3V
5V
28
34
44
53
45
53
45
54
66
79
67
80
3.3V
68
81
108
109
110
98
129
130
131
118
118
191
192
193
267
267
5V
3.3V
5V
99
159
160
161
222
223
FRC 20 MIPS, PLL enabled
FRC, 30 MIPS, PLL enabled
5V
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows:
- All I/O pins are configured as Outputs and pulled to VSS.
- MCLR = VDD, WDT and FSCM are disabled.
- CPU, SRAM, Program Memory and Data Memory are operational.
- No peripheral modules are operating.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 233
dsPIC30F1010/202X
TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Operating Current (IDD)(2)
DC28a
DC28b
DC28d
DC28e
DE28f
96
116
116
188
189
191
273
273
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
97
157
158
159
227
228
EC, 20 MIPS, PLL enabled
DC29d
DC29e
5V
EC, 30 MIPS, PLL enabled
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows:
- All I/O pins are configured as Outputs and pulled to VSS.
- MCLR = VDD, WDT and FSCM are disabled.
- CPU, SRAM, Program Memory and Data Memory are operational.
- No peripheral modules are operating.
DS70178C-page 234
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40a
DC40b
DC40c
DC40d
DC40e
DC40f
DC42a
DC42b
DC42c
DC42d
DC42e
DC42f
DC43a
DC43b
DC43c
DC43d
DC43e
DC43f
DC44a
DC44b
DC44c
DC44d
DC44e
DC44f
DC46a
DC46b
DC46d
DC46e
DC45f
DC47d
DC47e
8
8
9
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
8
10
15
15
16
12
13
13
20
21
21
18
18
18
29
29
30
53
54
55
87
88
89
79
80
129
131
132
182
183
FRC, 3.2 MIPS, PLL disabled
12
13
13
10
11
3.3V
5V
11
FRC, 4.9 MIPS, PLL disabled
FRC, 7.3 MIPS, PLL disabled
FRC, 13 MIPS, PLL enabled
17
17
18
15
15
15
24
24
25
44
45
46
72
73
74
66
67
108
109
110
152
153
3.3V
5V
3.3V
5V
3.3V
5V
FRC 20 MIPS, PLL enabled
FRC, 30 MIPS, PLL enabled
5V
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. All I/Os are configured
as inputs and pulled high. WDT, etc. are all switched off.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 235
dsPIC30F1010/202X
TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC48a
DC48b
DC48d
DC48e
DC48f
DC49d
DC49e
65
78
mA
mA
mA
mA
mA
mA
mA
25°C
85°C
25°C
85°C
125°C
25°C
85°C
3.3V
5V
66
79
105
107
108
155
156
127
128
130
186
187
EC, 20 MIPS, PLL enabled
5V
EC, 30 MIPS, PLL enabled
Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. All I/Os are configured
as inputs and pulled high. WDT, etc. are all switched off.
DS70178C-page 236
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Power-Down Current (IPD)
DC60a
DC60b
DC60c
DC60e
DC60f
DC60g
DC61a
DC61b
DC61c
DC61e
DC61f
DC61g
1.2
1.2
1.3
2.1
2.1
2.3
15
2.4
2.4
2.6
4.2
4.2
4.6
30
mA
mA
mA
mA
mA
mA
μA
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
25°C
85°C
125°C
3.3V
5V
Base Power-Down Current(2)
14
30
μA
μA
3.3V
5V
14
30
(3)
Watchdog Timer Current: ΔIWDT
30
60
μA
29
60
μA
μA
30
60
Note 1: Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Base IPD is measured with all peripherals and clocks shutdown. All I/Os are configured as inputs and
pulled high. WDT, etc. are all switched off.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 237
dsPIC30F1010/202X
TABLE 21-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
VIL
DI10
I/O pins:
with Schmitt Trigger buffer
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
DI15
DI16
DI18
DI19
MCLR
OSC1 (in HS mode)
SDA, SCL
SMbus disabled
SDA, SCL
SMbus enabled
VIH
Input High Voltage(2)
DI20
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.7 VDD
0.8 VDD
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
DI25
DI26
DI28
DI29
MCLR
OSC1 (in HS mode)
SDA, SCL
SMbus disabled
SMbus enabled
SDA, SCL
IIL
Input Leakage Current(2)(3)(4)
DI50
DI51
I/O ports
—
—
0.01
0.50
±1
—
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
Analog input pins
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55
DI56
MCLR
OSC1
—
—
0.05
0.05
±5
±5
μA
VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD, HS
Osc mode
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
4: Negative current is defined as current sourced by the pin.
DS70178C-page 238
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1) Max Units
Conditions
VOL
Output Low Voltage(2)
DO10
DO16
I/O ports
—
—
—
—
—
—
—
—
0.6
TBD
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 5V
IOL = 2.0 mA, VDD = 3.3V
IOL = 1.6 mA, VDD = 5V
IOL = 2.0 mA, VDD = 3.3V
OSC2/CLKO
(RC or EC Osc mode)
Output High Voltage(2)
I/O ports
TBD
VOH
DO20
DO26
VDD – 0.7
TBD
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 5V
IOH = -2.0 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 5V
IOH = -2.0 mA, VDD = 3.3V
OSC2/CLKO
VDD – 0.7
TBD
(RC or EC Osc mode)
Capacitive Loading Specs
on Output Pins(2)
DO50 COSC2
OSC2 pin
—
—
15
pF In HS mode when external
clock is used to drive OSC1.
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCL, SDA
—
—
—
—
50
pF RC or EC Osc mode
pF In I2C mode
400
Legend: TBD = To Be Determined
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
TABLE 21-10: DC CHARACTERISTICS: PROGRAM AND EEPROM
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min Typ(1)
Max
Units
Conditions
Program Flash Memory(2)
Cell Endurance
D130
D131
EP
10K
100K
—
—
E/W
V
VPR
VDD for Read
VMIN
5.5
VMIN = Minimum operating
voltage
D132
D133
D134
D135
VEB
VDD for Bulk Erase
4.5
3.0
—
—
—
5.5
5.5
—
V
V
VPEW
TPEW
TRETD
VDD for Erase/Write
Erase/Write Cycle Time
Characteristic Retention
2
ms
40
100
—
Year Provided no other specifications
are violated
D136
D137
D138
TEB
IPEW
IEB
ICSP Block Erase Time
IDD During Programming
IDD During Programming
—
—
—
4
—
30
30
ms
10
10
mA Row Erase
mA Bulk Erase
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
2: These parameters are characterized but not tested in manufacturing.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 239
dsPIC30F1010/202X
21.2 AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 21-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in DC Spec Section 21.0.
FIGURE 21-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS
5 pF for OSC2 output
FIGURE 21-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS30 OS30
OS31 OS31
OS25
OS40
OS41
DS70178C-page 240
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-12: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10 FIN
External CLKI Frequency(2)
(External clocks allowed only
in EC mode)
6
6
—
—
15.00
15.00
MHz
MHz
EC
EC with 32x PLL
Oscillator Frequency(2)
6
6
—
—
15.00
15.00
MHz
MHz
HS
FRC internal
(3)
OS20 TOSC
OS25 TCY
TOSC = 1/FOSC
16.5
33
—
—
—
DC
DC
—
ns
ns
ns
Instruction Cycle Time(2)(4)
External Clock(2) in (OSC1)
High or Low Time
OS30 TosL,
TosH
.45 x
TOSC
EC
EC
OS31 TosR,
TosF
External Clock(2) in (OSC1)
Rise or Fall Time
—
—
20
ns
OS40 TckR
OS41 TckF
CLKO Rise Time(2)(5)
CLKO Fall Time(2)(5)
—
—
6
6
10
10
ns
ns
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
3: The oscillator frequency (FOSC) is equal to FIN when the PLL is disabled. FOSC is equal to 4 x FIN when
the PLL is enabled.
4: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLK1 pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
5: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 241
dsPIC30F1010/202X
TABLE 21-13: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0 AND 5.0V )
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OS50
FPLLI
PLL Input Frequency Range(2)
6
—
15
MHz EC, HS modes with PLL
x32
OS51
FSYS
On-chip PLL Output(2)
192
—
480
MHz EC, HS modes with PLL
x32
OS52
OS53
TLOC
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
—
—
20
—
50
1
μs
%
Measured over 100 ms
period
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
TABLE 21-14: INTERNAL CLOCK TIMING EXAMPLES
Clock
MIPS(3)
w/o PLL
MIPS(4)
w/PLL x32
Oscillator
Mode
FIN (MHz)(1)
TCY (μsec)(2)
EC
10
15
10
15
0.2
0.133
0.2
5.0
7.5
5.0
7.5
20
30
20
30
HS
0.133
Note 1: Assumption: Oscillator Postscaler is divide by 1.
2: Instruction Execution Cycle Time: TCY = 1/MIPS.
3: Instruction Execution Frequency without PLL: MIPS = FIN/2 (since there are 2 Q clocks per instruction
cycle).
4: Instruction Execution Frequency with PLL: MIPS = (FIN * 2).
DS70178C-page 242
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.3V and 5.0V (± 10%)
(unless otherwise stated)
Operating temperature
AC CHARACTERISTICS
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Freq = 6.4 MHz(1)
FRC
-0.06
-0.06
-1
—
—
—
—
—
+0.06
+0.06
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
+25°C
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-1
+1
-1
+1
Internal FRC Accuracy @ FRC Freq = 9.7 MHz(1)
FRC
-0.06
-0.06
-1
—
—
—
—
—
+0.06
+0.06
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
+25°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-1
+1
-1
+1
Internal FRC Accuracy @ FRC Freq = 14.55 MHz(1)
FRC
-0.06
-0.06
-1
—
—
—
—
—
+0.06
+0.06
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
+25°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
-1
+1
-1
+1
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 243
dsPIC30F1010/202X
TABLE 21-16: AC CHARACTERISTICS: INTERNAL RC JITTER
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature
AC CHARACTERISTICS
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Jitter @ FRC Freq = 6.4 MHz(1)
FRC
-1
-1
-1
-1
-1
—
—
—
—
—
+1
+1
+1
+1
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
+25°C
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
Internal FRC Jitter @ FRC Freq = 9.7 MHz(1)
FRC
-1
-1
-1
-1
-1
—
—
—
—
—
+1
+1
+1
+1
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
+25°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
Internal FRC Jitter @ FRC Freq = 14.55 MHz(1)
FRC
-1
-1
-1
-1
-1
—
—
—
—
—
+1
+1
+1
+1
+1
%
%
%
%
%
+25°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
+25°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
Note 1: Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift.
DS70178C-page 244
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-17: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)(2)
Min
Typ(3)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port output rise time
—
—
10
10
—
—
25
25
—
—
ns
ns
ns
ns
—
—
—
—
Port output fall time
INTx pin high or low time (output)
CNx high or low time (input)
20
DI40
2 TCY
Note 1: These parameters are asynchronous events not related to any internal clock edges.
2: These parameters are characterized but not tested in manufacturing.
3: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 245
dsPIC30F1010/202X
FIGURE 21-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
SY30
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 21-1 for load conditions.
DS70178C-page 246
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-18: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TmcL
MCLR Pulse Width (low)
Power-up Timer Period
2
—
—
μs
ms
-40°C to +125°C
TPWRT
0.75
1.5
3
1
2
4
1.25
2.5
5
-40°C to +125°C
User programmable
6
8
10
12
24
48
96
16
32
64
128
20
40
80
160
SY12
SY13
TPOR
TIOZ
Power-On Reset Delay
3
10
30
μs
μs
-40°C to +125°C
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
0.8
1.0
SY20
TWDT1
TWDT2
Watchdog Timer Time-out Period
(No Prescaler)
1.4
1.4
2.1
2.1
2.8
2.8
ms
ms
VDD = 5V, -40°C to
+125°C
VDD = 3.3V, -40°C to
+125°C
SY30
SY35
TOST
Oscillation Start-up Timer Period
Fail-Safe Clock Monitor Delay
—
—
1024 TOSC
500
—
—
—
TOSC = OSC1 period
-40°C to +125°C
TFSCM
μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 247
dsPIC30F1010/202X
FIGURE 21-5:
BAND GAP START-UP TIME CHARACTERISTICS
VBGAP
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
TABLE 21-19: BAND GAP START-UP TIME REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Band Gap Start-up Time
Min Typ(2) Max Units
Conditions
SY40
TBGAP
—
40 65
µs Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON<13> status bit.
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
DS70178C-page 248
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-6:
TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRX
Note: “x” refers to Timer Type A or Timer Type B.
Refer to Figure 21-1 for load conditions.
TABLE 21-20: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 10
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale
value
(TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
20
—
—
—
ns
OS60
TA20
Ft1
SOSC1/T1CK oscillator input
DC
50
kHz
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5 TCY
—
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 249
dsPIC30F1010/202X
TABLE 21-21: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TtxH
TtxL
TtxP
TB10
TB11
TB15
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
—
—
—
—
ns Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
ns
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
ns Must also meet
parameter TB15
Synchronous,
with prescaler
10
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 10
ns N = prescale
value (1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
TABLE 21-22: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TtxH
TC10
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns Must also meet
parameter TC15
TC11
TtxL
0.5 TCY + 20
TCY + 10
—
—
ns Must also meet
parameter TC15
TC15 TtxP
TxCK Input Period Synchronous,
no prescaler
ns N = prescale
value (1, 8, 64,
256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40) /
N
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5
TCY
—
DS70178C-page 250
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICX
IC10
IC11
IC15
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-23: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
ICx Input Period
(2 TCY + 40) / N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 21-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 251
dsPIC30F1010/202X
FIGURE 21-9:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 21-25: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OC15 TFD
OC20 TFLT
Fault Input to PWM I/O
Change
—
—
25
TBD
50
ns
ns
ns
ns
VDD = 3.3V -40°C to +85°C
VDD = 5V
Fault Input Pulse Width
—
—
VDD = .33V -40°C to +85°C
VDD = 5V
TBD
Legend: TBD = To Be Determined
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70178C-page 252
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-10:
POWER SUPPLY PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA/B
PWMx
MP20
FIGURE 21-11:
POWER SUPPLY PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-26: POWER SUPPLY PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
VDD = 5V
VDD = 5V
MP10
MP11
MP12
MP13
TFPWM
TRPWM PWM Output Rise Time
TFPWM PWM Output Fall Time
TRPWM PWM Output Rise Time
PWM Output Fall Time
—
—
—
—
—
10
10
25
25
ns
ns
ns
ns
ns
ns
ns
ns
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 5V
TBD
TBD
—
TBD
TBD
TBD
25
TFD
Fault Input ↓ to PWM
I/O Change
MP20
MP30
TFH
Minimum Pulse Width
—
—
TBD
50
VDD = 3.3V
VDD = 5V
Legend: TBD = To Be Determined
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 253
dsPIC30F1010/202X
FIGURE 21-12:
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
BIT14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb IN
SP40
LSb IN
BIT14 - - - -1
SP41
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-27: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Para
m
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
No.
SP10 TscL
SP11 TscH
SP20 TscF
SP21 TscR
SP30 TdoF
SP31 TdoR
SCKX Output Low Time(3)
SCKX Output High Time(3)
SCKX Output Fall Time(4)
SCKX Output Rise Time(4)
SDOX Data Output Fall Time(4)
SDOX Data Output Rise Time(4)
TCY/2
TCY/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
—
See parameter D032
See parameter D031
See parameter D032
See parameter D031
—
—
—
—
SP35 TscH2doV, SDOX Data Output Valid after
TscL2doV SCKX Edge
—
SP40 TdiV2scH, Setup Time of SDIX Data Input
20
20
—
—
—
—
ns
ns
—
—
TdiV2scL
SP41 TscH2diL, Hold Time of SDIX Data Input
TscL2diL to SCKX Edge
Note 1: These parameters are characterized but not tested in manufacturing.
to SCKX Edge
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
DS70178C-page 254
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-13:
SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP20
BIT14 - - - - - -1
LSb
MSb
SP40
SDOX
SDIX
SP30,SP31
BIT14 - - - -1
MSb IN
SP41
LSb IN
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-28: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
SP11
SP20
SP21
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKX output low time(3)
SCKX output high time(3)
SCKX output fall time(4)
SCKX output rise time(4)
SDOX data output fall time(4)
SDOX data output rise time(4)
TCY / 2
TCY / 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
—
See parameter D032
See parameter D031
See parameter D032
See parameter D031
—
—
—
—
TscH2doV, SDOX data output valid after
TscL2doV SCKX edge
—
SP36
SP40
SP41
TdoV2sc, SDOX data output setup to
TdoV2scL first SCKX edge
30
20
20
—
—
—
—
—
—
ns
ns
ns
—
—
—
TdiV2scH, Setup time of SDIX data input
TdiV2scL
TscH2diL, Hold time of SDIX data input
TscL2diL to SCKX edge
Note 1: These parameters are characterized but not tested in manufacturing.
to SCKX edge
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 255
dsPIC30F1010/202X
FIGURE 21-14:
SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCK
(CKP =
X
0
)
)
SP71
SP70
SP72
SP73
SCK
(CKP =
X
1
SP73
LSb
SP72
SP35
MSb
BIT14 - - - - - -1
SDOX
SP51
SP30,SP31
BIT14 - - - -1
SDIX
MSb IN
SP41
LSb IN
Note: Refer to Figure 21-1 for load conditions.
SP40
TABLE 21-29: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKX Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKX Input High Time
—
SCKX Input Fall Time(3)
SCKX Input Rise Time(3)
SDOX Data Output Fall Time(3)
SDOX Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
TscH2doV SDOX Data Output Valid after
TscL2doV SCKX Edge
SP40
SP41
SP50
SP51
SP52
TdiV2scH, Setup Time of SDIX Data Input
TdiV2scL to SCKX Edge
20
20
—
—
—
—
—
—
—
—
50
—
ns
ns
ns
ns
ns
—
—
—
—
—
TscH2diL, Hold Time of SDIX Data Input
TscL2diL
to SCKX Edge
TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input
TssL2scL
120
10
TssH2doZ SSX↑ to SDOX Output
High-impedance(3)
TscH2ssH SSX after SCK Edge
TscL2ssH
1.5 TCY
+ 40
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: Assumes 50 pF load on all SPI pins.
DS70178C-page 256
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-15:
SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKX
(CKP = 1)
SP35
SP72
LSb
SP52
BIT14 - - - - - -1
MSb
SDOX
SDIX
SP30,SP31
BIT14 - - - -1
SP51
MSb IN
SP41
LSb IN
SP40
Note: Refer to Figure 21-1 for load conditions.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 257
dsPIC30F1010/202X
TABLE 21-30: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TscL
TscH
TscF
TscR
TdoF
TdoR
SP70
SP71
SP72
SP73
SP30
SP31
SP35
SCKX Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKX Input High Time
—
SCKX Input Fall Time(3)
SCKX Input Rise Time(3)
SDOX Data Output Fall Time(3)
SDOX Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
TscH2doV, SDOX Data Output Valid after
TscL2doV SCKX Edge
SP40
SP41
SP50
SP51
SP52
SP60
TdiV2scH, Setup Time of SDIX Data Input
TdiV2scL to SCKX Edge
20
20
—
—
—
—
—
—
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
TscH2diL, Hold Time of SDIX Data Input
TscL2diL
to SCKX Edge
TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input
TssL2scL
120
10
TssH2doZ SS↑ to SDOX Output
High-impedance(4)
TscH2ssH SSX↑ after SCKX Edge
TscL2ssH
1.5 TCY
+ 40
TssL2doV SDOX Data Output Valid after
SSX Edge
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
DS70178C-page 258
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-16:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
SDA
IM31
IM34
IM30
IM33
Stop
Condition
Start
Condition
Note: Refer to Figure 21-1 for load conditions.
FIGURE 21-17:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM33
IM25
SDA
In
IM45
IM40
IM40
SDA
Out
Note: Refer to Figure 21-1 for load conditions.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 259
dsPIC30F1010/202X
TABLE 21-31: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
TLO:SCL Clock Low Time 100 kHz mode TCY / 2 (BRG + 1)
400 kHz mode TCY / 2 (BRG + 1)
—
—
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
—
—
—
—
—
—
1 MHz mode(2) TCY / 2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY / 2 (BRG + 1)
—
400 kHz mode TCY / 2 (BRG + 1)
1 MHz mode(2) TCY / 2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
—
SDA and SCL
Rise Time
—
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
—
250
100
TBD
0
TSU:DAT Data Input
Setup Time
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
TBD
TSU:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1)
—
Only relevant for
repeated Start
condition
Setup Time
400 kHz mode TCY / 2 (BRG + 1)
—
1 MHz mode(2) TCY / 2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY / 2 (BRG + 1)
—
1 MHz mode(2) TCY / 2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY / 2 (BRG + 1)
—
1 MHz mode(2) TCY / 2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY / 2 (BRG + 1)
400 kHz mode TCY / 2 (BRG + 1)
1 MHz mode(2) TCY / 2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
TBD
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
Legend: TBD = To Be Determined
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ (I2C)”
section in the “dsPIC30F Family Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70178C-page 260
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-31: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min(1)
Max
Units
Conditions
IM50
CB
Bus Capacitive Loading
—
400
pF
Legend: TBD = To Be Determined
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ (I2C)”
section in the “dsPIC30F Family Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
FIGURE 21-18:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
SDA
IS34
IS31
IS30
IS33
Stop
Condition
Start
Condition
FIGURE 21-19:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS33
IS25
SDA
In
IS45
IS40
IS40
SDA
Out
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 261
dsPIC30F1010/202X
TABLE 21-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
—
μs
μs
Device must operate at a
minimum of 1.5 MHz
1.3
Device must operate at a
minimum of 10 MHz.
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
IS11
THI:SCL
Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
300
300
100
1000
300
300
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL
TR:SCL
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
—
SDA and SCL
Rise Time
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
250
100
100
0
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:STO Stop Condition
Hold Time
—
—
TAA:SCL
Output Valid From 100 kHz mode
3500
1000
350
—
Clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive
Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
DS70178C-page 262
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
Greater of
VDD – 0.3
or 2.7
Lesser of
VDD + 0.3
or 5.5
V
V
—
—
Vss – 0.3
Analog Input
VSS
VSS + 0.3
AD10
AD11
AD12
VINH-VINL Full-Scale Input Span
VDD
V
V
—
—
VIN
—
Absolute Input Voltage
Leakage Current
AVSS – 0.3
AVDD + 0.3
±0.244
—
—
—
±0.001
μA VINL = AVSS = 0V,
AVDD = 5V
Source Impedance = 1 kΩ
AD13
AD17
—
Leakage Current
±0.001
±0.244
1K
μA VINL = AVSS = 0V,
AVDD = 3.3V
Source Impedance = 1 kΩ
RIN
Recommended Impedance
Of Analog Voltage Source
Ω
—
DC Accuracy
10 data bits
±0.5
AD20 Nr
Resolution
bits
—
AD21 INL
Integral Nonlinearity
—
—
—
—
—
—
< ±1
< ±1
LSb VINL = AVSS = 0V
AVDD = 5V
AD21A INL
AD22 DNL
AD22A DNL
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Gain Error
±0.5
±0.5
LSb VINL = AVSS = 0V
AVDD = 3.3V
< ±1
LSb VINL = AVSS = 0V
AVDD = 5V
±0.5
< ±1
LSb VINL = AVSS = 0V
AVDD = 3.3V
AD23
GERR
±0.75
±0.75
<±4.0
<±3.0
LSb VINL = AVSS = 0V
AVDD = 5V
AD23A GERR
Gain Error
LSb VINL = AVSS = 0V
AVDD = 3.3V
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 263
dsPIC30F1010/202X
TABLE 21-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Offset Error
Min.
Typ
Max.
Units
Conditions
AD24
EOFF
—
±0.75
<±2.0
LSb VINL = AVSS = VSS = 0V,
AVDD = VDD = 5V
AD24A EOFF
AD25
Offset Error
—
—
±0.75
—
<±2.0
—
LSb VINL = AVSS = VSS = 0V,
AVDD = VDD = 3.3V
—
Monotonicity(2)
—
Guaranteed
Dynamic Performance
AD30 THD
Total Harmonic Distortion
-77
—
-73
58
-68
—
dB
dB
—
—
AD31 SINAD
Signal to Noise and
Distortion
AD32 SFDR
Spurious Free Dynamic
Range
—
-73
—
dB
—
AD33
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
—
0.5
—
MHz
bits
—
—
AD34 ENOB
9.4
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
FIGURE 21-20:
A/D CONVERSION TIMING PER INPUT
Tconv
Trigger Pulse
TAD
1
A/D Clock
A/D Data
9
0
2
0
Old Data
New Data
ADBUFxx
CONV
DS70178C-page 264
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-34: COMPARATOR OPERATING CONDITIONS
Symbol Characteristic
Min
3.0
4.5
-40
Typ
—
Max Units
Comments
Operating range of 3.0 V-3.6V
Operating range of 4.5 V-5.5 V
VDD
VDD
Voltage Range
3.6
5.5
105
V
V
Voltage Range
—
TEMP
Temperature Range
—
°C Note that junction temperature can
exceed 125°C under these ambient
conditions.
TABLE 21-35: COMPARATOR AC AND DC SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +105°C
Symbol Characteristic
Min
Typ
Max Units
Comments
VIOFF
VICM
Input offset voltage
±5
±15
mV
V
Input common mode
voltage range
0
VDD –
1.5
VGAIN Open loop gain
90
70
db
db
CMRR Common mode rejection
ratio
TRESP Large signal response
20
30
ns V+ input step of 100mv while V- input held
at AVDD/2. Delay measured from analog
input pin to PWM output pin.
TABLE 21-36: DAC DC SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +105°C
Symbol Characteristic
Min
Typ
Max
Units
Comments
CVRSRC Input reference voltage
0
AVDD –
1.6
V
CVRES
Resolution
10
Bits
Transfer Function Accuracy
Integral Non-Linearity Error
Differential Non-Linearity
Error
AVDD = 5 V,
DACREF = (AVDD/2) V
INL
DNL
—
—
—
—
—
—
—
—
±1
±0.8
±2
LSB
LSB
LSB
LSB
Offset Error
±2.0
Gain Error
Legend: TBD = To Be Determined
TABLE 21-37: DAC AC SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +125°C
Symbol Characteristic
Settling Time
Min
Typ
Max
Units
Comments
TSET
2.0
µs
Measured when range = 1 (High
Range), and cmref<9:0> transitions
from 0x1FF to 0x300.
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 265
dsPIC30F1010/202X
NOTES:
DS70178C-page 266
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
22.0 PACKAGE MARKING INFORMATION
28-Lead QFN-S
Example
dsPIC30F1010
XXXXXXX
XXXXXXX
-30I/MM
e
3
YYWWNNN
040700U
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
dsPIC30F202X-30I/SP
e
3
0348017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
dsPIC30F202X-30I/SO
e
0348017
3
YYWWNNN
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC30F202X
e
3
-I/PT
0510017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC30F202X
e
3
-I/ML
0510017
Legend: XX...X Customer-specific information
Y
e
Year code (last digit of calendar year)
3
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 267
dsPIC30F1010/202X
28-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body (QFN-S)
With 0.40 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
E2
E
b
2
1
2
1
K
N
N
L
NOTE 1
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MAX
MIN
28
Number of Pins
Pitch
N
e
0.65 BSC
0.90
0.80
0.00
Overall Height
Standoff
A
1.00
0.05
0.02
A1
A3
E
0.20 REF
6.00 BSC
3.70
Contact Thickness
Overall Width
3.65
Exposed Pad Width
Overall Length
E2
D
4.70
6.00 BSC
3.70
3.65
0.23
0.30
0.20
Exposed Pad Length
Contact Width
D2
b
4.70
0.43
0.50
—
0.38
0.40
Contact Length §
Contact-to-Exposed Pad §
L
—
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–124, Sept. 8, 2006
DS70178C-page 268
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
28
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.150
.130
.160
3.56
3.18
3.81
3.30
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.43
0.38
7.62
6.99
34.16
3.18
0.20
1.02
0.41
8.13
5
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
34.67
3.30
0.29
1.33
0.48
8.89
10
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
*
Controlling Parameter
§
Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 269
dsPIC30F1010/202X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
28
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
A
.093
.099
.091
.008
.407
.295
.704
.020
.033
4
.104
2.36
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
2.64
Molded Package Thickness
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
Standoff
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
c
Foot Angle Top
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS70178C-page 270
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45°
α
A
c
φ
β
A1
A2
L
F
Units
Dimension Limits
INCHES
NOM
44
MILLIMETERS
*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
n1
A
Overall Height
.039
.043
.039
.004
.024
.039 REF.
3.5
.047
1.00
1.10
1.20
Molded Package Thickness
Standoff
A2
A1
L
.037
.002
.018
.041
.006
.030
0.95
0.05
0.45
1.00
0.10
0.60
1.05
0.15
0.75
Foot Length
Footprint (Reference)
Foot Angle
F
φ
1.00 REF.
3.5
12.00
0
7
0
7
Overall Width
E
D
.463
.463
.390
.390
.004
.012
.025
.472
.472
.394
.394
.006
.015
.035
10
.482
.482
.398
.398
.008
.017
.045
11.75
11.75
9.90
9.90
0.09
0.30
0.64
12.25
12.25
10.10
10.10
0.20
Overall Length
12.00
10.00
10.00
0.15
0.38
0.89
10
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
B
CH
α
0.44
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
1.14
5
15
15
5
15
15
β
5
10
5
10
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MS-026
Revised 07-22-05
Drawing No. C04-076
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 271
dsPIC30F1010/202X
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body (QFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
E
E2
b
2
1
2
1
N
N
K
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
NOM
44
MAX
MIN
Number of Pins
Pitch
N
e
0.65 BSC
0.90
0.80
0.00
Overall Height
Standoff
A
1.00
0.05
0.02
A1
A3
E
0.20 REF
8.00 BSC
6.45
Contact Thickness
Overall Width
6.30
Exposed Pad Width
Overall Length
E2
D
6.80
8.00 BSC
6.45
6.30
0.25
0.30
0.20
Exposed Pad Length
Contact Width
D2
b
6.80
0.38
0.50
—
0.30
0.40
Contact Length §
Contact-to-Exposed Pad §
L
—
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–103, Sept. 8, 2006
DS70178C-page 272
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
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© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 273
dsPIC30F1010/202X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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dsPIC30F1010/202X
DS70178C
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70178C-page 274
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Revision C (November 2006)
APPENDIX A: REVISION HISTORY
This revision includes:
Revision A (June 2006)
• Initial release of this document.
Revision B (August 2006)
This revision includes:
Updated RC, EC and HS Crystal operating frequencies
for Industrial and Extended Temperatures.
Revised SPI section to reflect updated operating fre-
quencies (see Section 13.0 “Serial Peripheral Inter-
face (SPI)”).
Updated Section 5.0 “Interrupts” to include
INTTREG register.
Revised oscillator configurations (see Section 18.3
“Oscillator Configurations”).
Updated device configuration registers to include FBS
Boot Code Segment and FOSCEL Oscillator Selection
configuration registers (see Section 18.10 “Device
Configuration Registers”).
Updated Electrial Characteristics:
• Supply voltage parameter DC11 minimum value
changed to 3.0V (see Table 21-4)
Updated Electrical Characteristics:
• Operating current (IDD) (see Table 21-5)
• Idle current (IIDLE) (see Table 21-6)
• IIDLE Parameter DC43f Max Value revised to
87 ma (see Table 21-6)
• I/O Pin Input specifications (see Table 21-8)
• I/O Pin Output specifications (see Table 21-9)
Typographical corrections:
•
dsPIC30F1010/2020 Port Registers (see Table 6-1)
- TRISA SFR bit 9 corrected to “TRISA9”
• External Clock Timing (see Figure 21-2 and
Table 21-12)
• PLL Clock Timing (see Table 21-13)
• Internal RC Accuracy (see Table 21-15)
• Power-up Timer Period (see Table 21-18)
- TRISD SFR Reset State corrected to
“0000 0000 0000 0011”
• dsPIC30F2023 Port Registers (see Table 6-2)
- TRISA SFR bit 0 corrected to “unused”
- PORTA SFR bit 0 corrected to “unused”
- LATA SFR bit 0 corrected to “unused”
- TRISD SFR bit 0 corrected to “TRISD0”
- PORTD SFR bit 0 corrected to “RD0”
- LATD SFR bit 0 corrected to “LATD0”
- TRISD SFR reset state corrected to
“0000 0000 0000 0011”
• dsPIC30F1010/202X CNEN1 SFR reset state
corrected to “0000 0000 0000 0000“
(see Table 6-3)
• PWMCONx (see Register 12-5)
- Bit 13 description corrected to “TRGSTAT”
- Bit 10 description corrected to “TRGIEN”
• ALTDTRx (see Register 12-9)
- Bits 15-14 corrected to “unused”
• ADCPC1 (see Register 16-6)
- TRGSRC2<4:0> corrected to include bit 4
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 275
dsPIC30F1010/202X
NOTES:
DS70178C-page 276
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
INDEX
Comparator Control Register (CMPCONx)....................... 193
Comparator DAC Control Registerx (CMPDACx)............. 194
Configuring Analog Port Pins.............................................. 78
Control Registers................................................................ 82
NVMADR.................................................................... 82
NVMADRU ................................................................. 82
NVMCON.................................................................... 82
NVMKEY .................................................................... 82
Core Architecture
Overview..................................................................... 19
Core Register Map........................................................ 37, 38
Customer Change Notification Service............................. 273
Customer Notification Service .......................................... 273
Customer Support............................................................. 273
A
A/D.................................................................................... 169
Configuring Analog Port............................................ 188
A/D Control Register (ADCON)......................................... 171
A/D Convert Pair Control Register #0 (ADCPC0) ............. 175
A/D Convert Pair Control Register #1 (ADCPC1) ............. 177
A/D Convert Pair Control Register #2 (ADCPC2) ............. 179
A/D Port Configuration Register (ADPCFG) ..................... 174
A/D Status Register (ADSTAT)......................................... 173
AC Characteristics ............................................................ 240
Load Conditions........................................................ 240
AC Temperature and Voltage Specifications.................... 240
ADC Register Map ............................................................ 190
Address Generator Units .................................................... 41
Alternate Vector Table ........................................................ 51
Analog Comparator Control Register Map........................ 195
Assembler
D
Data Access from Program Memory Using
Program Space Visibility............................................. 32
Data Accumulators and Adder/Subtracter .......................... 25
Data Space Write Saturation...................................... 27
Overflow and Saturation............................................. 25
Round Logic ............................................................... 26
Write Back .................................................................. 26
Data Address Space........................................................... 33
Alignment.................................................................... 36
Alignment (Figure)...................................................... 36
MCU and DSP (MAC Class) Instructions ................... 35
Memory Map......................................................... 33, 34
Near Data Space........................................................ 37
Software Stack ........................................................... 37
Spaces........................................................................ 36
Width .......................................................................... 36
DC Characteristics
I/O Pin Input Specifications ...................................... 238
I/O Pin Output Specifications.................................... 239
Idle Current (IIDLE).................................................... 235
Operating Current (IDD) ............................................ 233
Power-Down Current (IPD)........................................ 237
Program and EEPROM ............................................ 239
Development Support....................................................... 227
Device Configuration Register Map.................................. 218
Device Configuration Registers ........................................ 215
Device Overview................................................................... 9
Divide Support .................................................................... 22
DSP Engine ........................................................................ 23
Multiplier ..................................................................... 25
dsPIC30F2020 Block Diagram ........................................... 13
Dual Output Compare Match Mode.................................. 102
Continuous Pulse Mode ........................................... 102
Single Pulse Mode.................................................... 102
MPASM Assembler................................................... 228
Automatic Clock Stretch.................................................... 156
During 10-bit Addressing (STREN = 1)..................... 156
During 7-bit Addressing (STREN = 1)....................... 156
Receive Mode........................................................... 156
Transmit Mode.......................................................... 156
B
Band Gap Start-up Time
Requirements............................................................ 248
Timing Characteristics .............................................. 248
Barrel Shifter ....................................................................... 27
Baud Rate Error Calculation (BRGH = 0) ......................... 162
Bit-Reversed Addressing .................................................... 45
Example...................................................................... 45
Implementation ........................................................... 45
Modifier Values (table)................................................ 46
Sequence Table (16-Entry)......................................... 46
Block Diagrams
16-bit Timer1 Module.................................................. 88
DSP Engine ................................................................ 24
dsPIC30F1010............................................................ 10
dsPIC30F2020............................................................ 13
dsPIC30F2023............................................................ 16
External Power-on Reset Circuit............................... 212
2
I C............................................................................. 154
Input Capture Mode .................................................... 97
Oscillator System...................................................... 198
Output Compare Mode ............................................. 101
Reset System............................................................ 210
Shared Port Structure ................................................. 77
SPI ............................................................................ 146
UART ........................................................................ 161
C
C Compilers
MPLAB C18 .............................................................. 228
MPLAB C30 .............................................................. 228
CLKO and I/O Timing
Characteristics .......................................................... 245
Requirements............................................................ 245
Code Examples
Erasing a Row of Program Memory............................ 83
Initiating a Programming Sequence............................ 84
Loading Write Latches ................................................ 84
Code Protection ................................................................ 197
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 277
dsPIC30F1010/202X
Pin Configuration ...................................................... 153
Programmer’s Model ................................................ 153
Registers .................................................................. 153
Slope Control............................................................ 157
Software Controlled Clock Stretching (STREN = 1) . 156
Various Modes.......................................................... 153
E
Electrical Characteristics...................................................231
AC .............................................................................240
Equations
2
I C.............................................................................158
Relationship Between Device and SPI
2
I C Register Map .............................................................. 159
Idle Current (IIDLE) ............................................................ 235
In-Circuit Debugger........................................................... 217
In-Circuit Serial Programming (ICSP)............................... 197
Initialization Condition for RCON Register Case 1 ........... 213
Initialization Condition for RCON Register Case 2 ........... 213
Input Capture (CAPX) Timing Characteristics .................. 251
Input Capture Interrupts...................................................... 99
Input Capture Module ......................................................... 97
Simple Capture Event Mode....................................... 98
Sleep and Idle Modes................................................. 99
Input Capture Register Map.............................................. 100
Input Capture Timing Requirements................................. 251
Input Change Notification ................................................... 78
Input Change Notification Register Map............................. 80
Instruction Addressing Modes ............................................ 41
File Register Instructions............................................ 41
Fundamental Modes Supported ................................. 41
MAC Instructions ........................................................ 42
MCU Instructions ........................................................ 42
Move and Accumulator Instructions............................ 42
Other Instructions ....................................................... 42
Instruction Set................................................................... 219
Instruction Set Overview................................................... 222
Clock Speed......................................................148
UART Baud Rate with BRGH = 0 .............................162
UART Baud Rate with BRGH = 1 .............................162
Errata ....................................................................................8
External Clock Input..........................................................207
External Clock Timing Characteristics
Type A, B and C Timer .............................................249
External Clock Timing Requirements................................241
Type A Timer ............................................................249
Type B Timer ............................................................250
Type C Timer ............................................................250
External Interrupt Requests ................................................51
F
Fast Context Saving............................................................51
Firmware Instructions........................................................219
Flash Program Memory.......................................................81
In-Circuit Serial Programming (ICSP).........................81
Run-Time Self-Programming (RTSP) .........................81
Table Instruction Operation Summary ........................81
I
I/O Pin Specifications
Input..........................................................................239
Output .......................................................................239
I/O Ports..............................................................................77
Parallel I/O (PIO).........................................................77
2
Inter-Integrated Circuit. See I C
Internal Clock Timing Examples ....................................... 242
Internet Address ............................................................... 273
Interrupt Control and Status Register (INTTREG).............. 74
Interrupt Control Register 1 (INTCON1) ............................. 52
Interrupt Control Register 2 (INTCON2) ............................. 54
Interrupt Controller Register Map ....................................... 75
Interrupt Enable Control Register 1 (IEC1)......................... 61
Interrupt Enable Control Register 2 (IEC2)......................... 62
Interrupt Flag Status Register 0 (IFS0)............................... 55
Interrupt Flag Status Register 1 (IFS1)............................... 57
Interrupt Flag Status Register 2 (IFS2)............................... 58
Interrupt Priority .................................................................. 48
Interrupt Priority Control Register 0 (IPC0)......................... 63
Interrupt Priority Control Register 1 (IPC1)......................... 64
Interrupt Priority Control Register 10 (IPC10)..................... 73
Interrupt Priority Control Register 2 (IPC2)......................... 65
Interrupt Priority Control Register 3 (IPC3)......................... 66
Interrupt Priority Control Register 4 (IPC4)......................... 67
Interrupt Priority Control Register 5 (IPC5)......................... 68
Interrupt Priority Control Register 6 (IPC6)......................... 69
Interrupt Priority Control Register 7 (IPC7)......................... 70
Interrupt Priority Control Register 8 (IPC8)......................... 71
Interrupt Priority Control Register 9 (IPC9)......................... 72
Interrupt Sequence ............................................................. 51
Interrupt Stack Frame................................................. 51
Interrupts............................................................................. 47
Traps .......................................................................... 49
2
I C.....................................................................................153
2
I C 10-bit Slave Mode Operation ......................................155
Reception..................................................................155
Transmission.............................................................155
I C 7-bit Slave Mode Operation ........................................155
2
Reception..................................................................155
Transmission.............................................................155
I C Master Mode
2
Baud Rate Generator................................................158
Clock Arbitration........................................................158
Multi-Master Communication, Bus Collision
and Bus Arbitration ...........................................158
Reception..................................................................157
Transmission.............................................................157
2
I C Module
Addresses.................................................................155
Bus Data Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
Bus Data Timing Requirements
Master Mode.....................................................260
Slave Mode.......................................................262
Bus Start/Stop Bits Timing Characteristics
Master Mode.....................................................259
Slave Mode.......................................................261
General Call Address Support ..................................157
Interrupts...................................................................156
IPMI Support.............................................................157
Master Operation ......................................................157
Master Support .........................................................157
Operating Function Description ................................153
Operation During CPU Sleep and Idle Modes ..........158
L
Leading Edge Blanking Control Register (LEBCONx)...... 120
Linear Feedback Register (LFSR).................................... 202
Load Conditions................................................................ 240
DS70178C-page 278
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Power-Saving Modes........................................................ 214
Idle............................................................................ 215
Sleep ........................................................................ 214
Power-Saving Modes (Sleep and Idle)............................. 197
Power-up Timer
Timing Characteristics.............................................. 246
Timing Requirements ............................................... 247
Primary Time Base Register (PTPER) ............................. 111
Product Identification System ........................................... 283
Program Address Space..................................................... 29
Construction ............................................................... 30
Data Access from Program Memory Using
M
Memory Organization.......................................................... 29
Microchip Internet Web Site.............................................. 273
Modulo Addressing ............................................................. 43
Applicability................................................................. 45
Operation Example ..................................................... 44
Start and End Address................................................ 43
W Address Register Selection .................................... 43
MPLAB ASM30 Assembler, Linker, Librarian ................... 228
MPLAB ICD 2 In-Circuit Debugger ................................... 229
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 229
MPLAB Integrated Development Environment Software .. 227
MPLAB PM3 Device Programmer .................................... 229
MPLAB REAL ICE In-Circuit Emulator System................. 229
MPLINK Object Linker/MPLIB Object Librarian ................ 228
Table Instructions ............................................... 31
Data Access from, Address Generation ..................... 30
Memory Map............................................................... 29
Table Instructions
TBLRDH ............................................................. 31
TBLRDL.............................................................. 31
TBLWTH............................................................. 31
TBLWTL ............................................................. 31
Program and EEPROM Characteristics............................ 239
Program Counter................................................................ 20
Program Data Table Access............................................... 32
Program Space Visibility
N
NVM Register Map.............................................................. 85
O
OC/PWM Module Timing Characteristics.......................... 252
Operating Current (IDD)..................................................... 233
Oscillator
Window into Program Space Operation ..................... 33
Programmer’s Model .......................................................... 20
Diagram...................................................................... 21
Programming Operations.................................................... 83
Algorithm for Program Flash....................................... 83
Erasing a Row of Program Memory ........................... 83
Initiating the Programming Sequence ........................ 84
Loading Write Latches................................................ 84
Programming, Device Instructions.................................... 219
PWM Alternate Dead-Time Register (ALTDTRx) ............. 115
PWM Control Register (PWMCONx)................................ 112
PWM Dead-Time Register (DTRx) ................................... 114
PWM Fault Current-Limit Control Register (FCLCONx) ... 117
PWM I/O Control Register (IOCONx) ............................... 116
PWM Master Duty Cycle Register (MDC)......................... 112
PWM Phase-Shift Register (PHASEx).............................. 114
PWM Time Base Control Register (PTCON).................... 110
PWM Trigger Compare Value Register (TRIGx) .............. 119
PWM Trigger Control Register (TRGCONx)..................... 115
System Overview...................................................... 197
Oscillator Configurations................................................... 205
Fail-Safe Clock Monitor............................................. 208
Initial Clock Source Selection ................................... 206
Phase Locked Loop (PLL) ........................................ 206
Start-up Timer (OST) ................................................ 206
Oscillator Control Register (OSCCON)............................. 199
Oscillator Selection ........................................................... 197
Oscillator Selection Configuration Bits (FOSC) ................ 204
Oscillator Selection Configuration Bits (FOSCSEL).......... 203
Oscillator Start-up Timer
Timing Characteristics .............................................. 246
Timing Requirements................................................ 247
Oscillator Tuning Register (OSCTUN) .............................. 201
Oscillator Tuning Register 2 (OSCTUN2)......................... 202
Output Compare Interrupts ............................................... 104
Output Compare Module................................................... 101
Timing Characteristics .............................................. 251
Timing Requirements................................................ 251
Output Compare Operation During CPU Idle Mode.......... 103
Output Compare Register Map ......................................... 105
Output Compare Sleep Mode Operation .......................... 103
R
Reader Response............................................................. 274
Register Map
P
ADC Register............................................................ 190
Analog Comparator Control Register ....................... 195
Core Registers............................................................ 38
Device Configuration Register.................................. 218
Packaging Information
Marking ..................................................................... 267
PICSTART Plus Development Programmer ..................... 230
Pinout Descriptions ................................................. 11, 14, 17
PLL Clock Timing Specifications....................................... 242
POR. See Power-on Reset
Port Register Map (dsPIC30F1010/2020)........................... 79
Port Register Map (dsPIC30F2023).................................... 80
Port Write/Read Example ................................................... 78
Power Supply PWM.......................................................... 107
Power Supply PWM Module
Timing Requirements................................................ 253
Power Supply PWM Register Map.................................... 142
Power-Down Current (IPD) ................................................ 237
Power-on Reset (POR)..................................................... 197
Oscillator Start-up Timer (OST) ................................ 197
Power-up Timer (PWRT) .......................................... 197
2
I C Register.............................................................. 159
Input Capture Registers............................................ 100
Input Change Notification Registers........................... 80
Interrupt Controller Registers ..................................... 75
NVM Registers ........................................................... 85
Output Compare Registers....................................... 105
Port Registers (dsPIC30F1010/2020) ........................ 79
Port Registers (dsPIC30F2023) ................................. 80
Power Supply PWM Registers ................................. 142
SPI1 Register ........................................................... 152
System Integration Register (dsPIC30F202X) ......... 218
Timer 1 Registers ....................................................... 90
Timer2/3 Registers ..................................................... 95
UART1 Register ....................................................... 168
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 279
dsPIC30F1010/202X
Registers
S
ADCON .....................................................................171
ADCPC@..................................................................179
ADCPC0 ...................................................................175
ADCPC1 ...................................................................177
ADPCFG...................................................................174
ADSTAT....................................................................173
ALTDTRx ..................................................................115
CMPCONx ................................................................193
CMPDACx.................................................................194
DTRx.........................................................................114
FCLCONx .................................................................117
FOSC ........................................................................204
FOSCSEL .................................................................203
IEC1............................................................................61
IEC2............................................................................62
IFS1 ............................................................................57
IFS2 ............................................................................58
IFSO............................................................................55
INTCON1 ....................................................................52
INTCON2 ....................................................................54
INTTREG ....................................................................74
IOCONx ....................................................................116
IPC0............................................................................63
IPC1............................................................................64
IPC10 ..........................................................................73
IPC2............................................................................65
IPC3............................................................................66
IPC4............................................................................67
IPC5............................................................................68
IPC6............................................................................69
IPC7............................................................................70
IPC8............................................................................71
IPC9............................................................................72
LEBCONx .................................................................120
LFSR.........................................................................202
MDC..........................................................................112
OSCCON ..................................................................199
OSCTUN...................................................................201
OSCTUN2.................................................................202
PHASEx....................................................................114
PTCON .....................................................................110
PTPER ......................................................................111
PWMCONx ...............................................................112
SEVTCMP.................................................................111
SPIxCON1 (SPIx Control 1)......................................150
SPIxCON2 (SPIx Control 2)......................................151
SPIxSTAT (SPIx Status and Control) .......................149
TRGCONx.................................................................115
TRIGx........................................................................119
U1MODE...................................................................164
U1STA ......................................................................166
Reset......................................................................... 197, 209
Reset Sequence..................................................................49
Reset Sources ............................................................49
Reset Timing Characteristics ............................................246
Reset Timing Requirements..............................................247
Resets
Sales and Support ............................................................ 282
Serial Peripheral Interface (SPI)....................................... 145
Simple Capture Event Mode
Capture Buffer Operation............................................ 98
Capture Prescaler....................................................... 98
Hall Sensor Mode ....................................................... 98
Input Capture in CPU Idle Mode................................. 99
Timer2 and Timer3 Selection Mode............................ 98
Simple OC/PWM Mode Timing Requirements ................. 252
Simple Output Compare Match Mode .............................. 102
Simple PWM Mode........................................................... 102
Period ....................................................................... 103
Software Simulator (MPLAB SIM) .................................... 228
Software Stack Pointer, Frame Pointer .............................. 20
CALL Stack Frame ..................................................... 37
Special Event Compare Register (SEVTCMP)................. 111
SPI
Master, Frame Master Connection ........................... 147
Master/Slave Connection.......................................... 147
Slave, Frame Master Connection ............................. 148
Slave, Frame Slave Connection ............................... 148
SPI Mode
SPI1 Register Map.................................................... 152
SPI Module
Timing Characteristics
Master Mode (CKE = 0).................................... 254
Master Mode (CKE = 1).................................... 255
Slave Mode (CKE = 1).............................. 256, 257
Timing Requirements
Master Mode (CKE = 0).................................... 254
Master Mode (CKE = 1).................................... 255
Slave Mode (CKE = 0)...................................... 256
Slave Mode (CKE = 1)...................................... 258
SPI1 Register Map............................................................ 152
STATUS Register ............................................................... 20
Symbols used in Opcode Descriptions............................. 220
System Integration............................................................ 197
System Integration Register Map (dsPIC30F202X).......... 218
T
Temperature and Voltage Specifications
AC............................................................................. 240
Timer1 Module.................................................................... 87
16-bit Asynchronous Counter Mode ........................... 87
16-bit Synchronous Counter Mode............................. 87
16-bit Timer Mode....................................................... 87
Gate Operation ........................................................... 88
Interrupt ...................................................................... 89
Operation During Sleep Mode .................................... 88
Prescaler .................................................................... 88
Timer1 Register Map .......................................................... 90
Timer2 and Timer3 Selection Mode.................................. 102
Timer2/3 Module................................................................. 91
16-bit Timer Mode....................................................... 91
32-bit Synchronous Counter Mode............................. 91
32-bit Timer Mode....................................................... 91
ADC Event Trigger...................................................... 94
Gate Operation ........................................................... 94
Interrupt ...................................................................... 94
Operation During Sleep Mode .................................... 94
Timer Prescaler .......................................................... 94
Timer2/3 Register Map ....................................................... 95
POR ..........................................................................211
POR with Long Crystal Start-up Time.......................212
POR, Operating without FSCM and PWRT ..............212
RTSP Operation..................................................................82
DS70178C-page 280
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
Timing Characteristics
A/D Conversion
U
UART
Baud Rate Generator (BRG) .................................... 162
10-Bit High-speed (CHPS = 01,
SIMSAM = 0, ASAM = 0, SSRC = 000).... 264
Band Gap Start-up Time........................................... 248
CLKO and I/O ........................................................... 245
External Clock........................................................... 240
Enabling and Setting Up UART................................ 162
IrDA
Built-in Encoder and Decoder........................... 163
Receiving
8-bit or 9-bit Data Mode.................................... 163
Transmitting
2
I C Bus Data
Master Mode..................................................... 259
Slave Mode....................................................... 261
I C Bus Start/Stop Bits
8-bit Data Mode................................................ 163
9-bit Data Mode................................................ 163
Break and Sync Sequence............................... 163
UART1 Mode Register (U1MODE)................................... 164
UART1 Register Map........................................................ 168
UART1 Status and Control Register (U1STA).................. 166
Unit ID Locations .............................................................. 197
Universal Asynchronous Receiver Transmitter. See UART
2
Master Mode..................................................... 259
Slave Mode....................................................... 261
Input Capture (CAPX)............................................... 251
Motor Control PWM Module...................................... 253
Motor Control PWM Module Falult............................ 253
OC/PWM Module...................................................... 252
Oscillator Start-up Timer........................................... 246
Output Compare Module........................................... 251
Power-up Timer ........................................................ 246
Reset......................................................................... 246
SPI Module
W
Wake-up from Sleep......................................................... 197
Wake-up from Sleep and Idle ............................................. 51
Watchdog Timer
Master Mode (CKE = 0).................................... 254
Master Mode (CKE = 1).................................... 255
Slave Mode (CKE = 0)...................................... 256
Slave Mode (CKE = 1)...................................... 257
Type A, B and C Timer External Clock ..................... 249
Watchdog Timer........................................................ 246
Timing Characteristics.............................................. 246
Timing Requirements ............................................... 247
Watchdog Timer (WDT)............................................ 197, 214
Enabling and Disabling............................................. 214
Operation.................................................................. 214
WWW Address ................................................................. 273
WWW, On-Line Support ....................................................... 8
Timing Diagrams
PWM Output ............................................................. 104
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 1 .................................. 211
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 2 .................................. 212
Time-out Sequence on Power-up (MCLR Tied
to VDD) .............................................................. 211
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 242
Timing Diagrams.See Timing Characteristics
Timing Requirements
Band Gap Start-up Time........................................... 248
Brown-out Reset ....................................................... 247
CLKO and I/O ........................................................... 245
External Clock........................................................... 241
2
I C Bus Data (Master Mode)..................................... 260
2
I C Bus Data (Slave Mode)....................................... 262
Input Capture ............................................................ 251
Motor Control PWM Module...................................... 253
Oscillator Start-up Timer........................................... 247
Output Compare Module........................................... 251
Power-up Timer ........................................................ 247
Reset......................................................................... 247
Simple OC/PWM Mode............................................. 252
SPI Module
Master Mode (CKE = 0).................................... 254
Master Mode (CKE = 1).................................... 255
Slave Mode (CKE = 0)...................................... 256
Slave Mode (CKE = 1)...................................... 258
Type A Timer External Clock .................................... 249
Type B Timer External Clock .................................... 250
Type C Timer External Clock.................................... 250
Watchdog Timer........................................................ 247
Timing Specifications
PLL Clock.................................................................. 242
Traps
Trap Sources .............................................................. 49
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 281
dsPIC30F1010/202X
NOTES:
DS70178C-page 282
Preliminary
© 2006 Microchip Technology Inc.
dsPIC30F1010/202X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC30F2020AT-30 I/ SO-ES
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
Package
MM = QFN
PT = TQFP
SP = SPDIP
SO = SOIC
Flash
Memory Size in Bytes
S
W
= Die (Waffle Pack)
= Die (Wafers)
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Temperature
I = Industrial -40°C to +85°C
E = Extended High Temp -40°C to +125°C
Speed
20 = 20 MIPS
Device ID
T = Tape and Reel
A,B,C… = Revision Level
Example:
dsPIC30F2020AT-30I/SO = 30 MIPS, Industrial temp., SOIC package, Rev. A
© 2006 Microchip Technology Inc.
Preliminary
DS70178C-page 283
WORLDWIDE SALES AND SERVICE
AMERICAS
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ASIA/PACIFIC
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Corporate Office
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Technical Support:
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Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
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Tel: 91-11-4160-8631
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Fax: 886-3-572-6459
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Fax: 86-755-8203-1760
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Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
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Taiwan - Taipei
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Santa Clara, CA
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China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
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Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
10/19/06
DS70178C-page 284
Preliminary
© 2006 Microchip Technology Inc.
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