DSPIC33FJ128MC708-I/PT [MICROCHIP]
16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, MS-026, TQFP-80;
| 型号： | DSPIC33FJ128MC708-I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, MS-026, TQFP-80 控制器 |
| 文件： | 总340页 (文件大小：5135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
dsPIC33FJXXXMCX06/X08/X10
Data Sheet
High-Performance,
16-Bit Digital Signal Controllers
© 2009 Microchip Technology Inc.
DS70287C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70287C-page ii
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
High-Performance, 16-Bit Digital Signal Controllers
Operating Range:
Digital I/O:
• Up to 40 MIPS operation (at 3.0-3.6V):
• Up to 85 programmable digital I/O pins
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
- Industrial temperature range
(-40°C to +85°C)
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
On-Chip Flash and SRAM:
• Flash program memory, up to 256 Kbytes
• 24-bit wide instructions
• Data SRAM, up to 30 Kbytes (includes 2 Kbytes
of DMA RAM)
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Two 40-bit accumulators:
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL
- With rounding and saturation options
• Flexible and powerful addressing modes:
- Indirect, Modulo and Bit-Reversed
• Software stack
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• Reset by multiple sources
Power Management:
• Up to ±16-bit shifts for up to 40-bit data
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Direct Memory Access (DMA):
• 8-channel hardware DMA
• 2 Kbytes dual ported DMA buffer area
(DMA RAM) to store data transferred via DMA:
Timers/Capture/Compare/PWM:
• Timer/Counters, up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)
- 1 timer runs as Real-Time Clock with external
32.768 kHz oscillator
• Most peripherals support DMA
- Programmable prescaler
Interrupt Controller:
• Input Capture (up to eight channels):
- Capture on up, down or both edges
- 16-bit capture input functions
• 5-cycle latency
• Up to 67 available interrupt sources
• Up to five external interrupts
• Seven programmable priority levels
• Five processor exceptions
- 4-deep FIFO on each capture
• Output Compare (up to eight channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
© 2009 Microchip Technology Inc.
DS70287C-page 1
dsPIC33FJXXXMCX06/X08/X10
Communication Modules:
Motor Control Peripherals:
• 3-wire SPI (up to two modules):
• Motor Control PWM (up to eight channels):
- Four duty cycle generators
- Framing supports I/O interface to simple
codecs
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™ (up to two modules):
- Manual output override control
- Up to two Fault inputs
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
• Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN™ (ECAN™ module) 2.0B active
(up to 2 modules):
Analog-to-Digital Converters (ADCs):
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
• Up to two ADC modules in a device
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two, four or eight simultaneous samples
- Up to 32 input channels with auto-scanning
- Wake-up on CAN message
- Conversion start can be manual or
synchronized with one of four trigger sources
- Automatic processing of Remote
Transmission Requests
- Conversion possible in Sleep mode
- ±1 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
- FIFO mode using DMA
- DeviceNet™ addressing support
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial temperature
• Low-power consumption
Packaging:
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 80-pin TQFP (12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
Note:
See the device variant tables for exact
peripheral features per device.
DS70287C-page 2
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
The device names, pin counts, memory sizes and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
dsPIC33F PRODUCT FAMILIES
The dsPIC33FJXXXMCX06/X08/X10 family of devices
supports a variety of motor control applications, such
as brushless DC motors, single and 3-phase induction
motors and switched reluctance motors. The dsPIC33F
Motor Control products are also well-suited for Uninter-
rupted Power Supply (UPS), inverters, switched mode
power supplies, power factor correction and also for
controlling the power management module in servers,
telecommunication equipment and other industrial
equipment.
dsPIC33FJXXXMCX06/X08/X10 Controller Families
Program
Flash
RAM
Device
Pins
Packages
Memory (Kbyte)(1)
(Kbyte)
dsPIC33FJ64MC506
dsPIC33FJ64MC508
dsPIC33FJ64MC510
dsPIC33FJ64MC706
dsPIC33FJ64MC710
dsPIC33FJ128MC506
64
80
64
64
8
8
9
9
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1 ADC,
16 ch
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
2
1
1
1
2
2
1
2
53
69
85
53
85
53
85
53
69
85
85
85
PT
PT
1 ADC,
18 ch
100
64
64
8
1 ADC,
24 ch
PF, PT
PT
64
16
16
8
2 ADC,
16 ch
100
64
64
2 ADC,
24 ch
PF, PT
PT
128
128
128
128
128
256
256
1 ADC,
16 ch
dsPIC33FJ128MC510 100
8
1 ADC,
24 ch
PF, PT
PT
dsPIC33FJ128MC706
dsPIC33FJ128MC708
64
80
16
16
16
16
30
2 ADC,
16 ch
2 ADC,
18 ch
PT
dsPIC33FJ128MC710 100
dsPIC33FJ256MC510 100
dsPIC33FJ256MC710 100
2 ADC,
24 ch
PF, PT
PF, PT
PF, PT
1 ADC,
24 ch
2 ADC,
24 ch
Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
© 2009 Microchip Technology Inc.
DS70287C-page 3
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams
64-Pin TQFP
= Pins are up to 5V tolerant
PWM3H/RE5
PWM4L/RE6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
1
2
3
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
4
IC4/INT4/RD11
5
IC3/INT3/RD10
6
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
7
dsPIC33FJ128MC506
dsPIC33FJ64MC506
dsPIC33FJ128MC706
dsPIC33FJ64MC706
8
VSS
SS2/CN11/RG9
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
9
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
DS70287C-page 4
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams (Continued)
80-Pin TQFP
= Pins are up to 5V tolerant
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
1
PWM3H/RE5
PWM4L/RE6
2
PWM4H/RE7
3
IC4/RD11
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
4
IC3/RD10
5
IC2/RD9
6
IC1/RD8
7
SDA2/INT4/RA3
SCL2/INT3/RA2
8
9
VSS
SS2/CN11/RG9
10
11
12
13
14
15
16
17
18
19
20
dsPIC33FJ64MC508
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
VDD
TMS/FLTA/INT1/RE8
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
TDO/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
© 2009 Microchip Technology Inc.
DS70287C-page 5
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams (Continued)
80-Pin TQFP
= Pins are up to 5V tolerant
60
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
1
PWM3H/RE5
PWM4L/RE6
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2
3
PWM4H/RE7
IC4/RD11
4
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
IC3/RD10
5
IC2/RD9
6
IC1/RD8
7
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SDA2/INT4/RA3
SCL2/INT3/RA2
8
9
VSS
SS2/CN11/RG9
10
11
12
dsPIC33FJ128MC708
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
VDD
TMS/FLTA/INT1/RE8
TDO/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
13
14
15
16
17
18
19
20
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
DS70287C-page 6
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
RG15
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64MC510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
© 2009 Microchip Technology Inc.
DS70287C-page 7
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
RG15
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ128MC510
dsPIC33FJ256MC510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
DS70287C-page 8
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
RG15
1
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64MC710
dsPIC33FJ128MC710
dsPIC33FJ256MC710
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
© 2009 Microchip Technology Inc.
DS70287C-page 9
dsPIC33FJXXXMCX06/X08/X10
Table of Contents
dsPIC33F Product Families ................................................................................................................................................................... 3
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 19
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization................................................................................................................................................................. 35
5.0 Flash Program Memory.............................................................................................................................................................. 73
6.0 Reset ......................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 85
8.0 Direct Memory Access (DMA).................................................................................................................................................. 133
9.0 Oscillator Configuration............................................................................................................................................................ 143
10.0 Power-Saving Features............................................................................................................................................................ 153
11.0 I/O Ports ................................................................................................................................................................................... 161
12.0 Timer1 ...................................................................................................................................................................................... 163
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 165
14.0 Input Capture............................................................................................................................................................................ 171
15.0 Output Compare....................................................................................................................................................................... 173
16.0 Motor Control PWM Module..................................................................................................................................................... 177
17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 191
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 195
19.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 201
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 209
21.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 215
22.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 241
23.0 Special Features ...................................................................................................................................................................... 253
24.0 Instruction Set Summary.......................................................................................................................................................... 261
25.0 Development Support............................................................................................................................................................... 269
26.0 Electrical Characteristics.......................................................................................................................................................... 273
27.0 Packaging Information.............................................................................................................................................................. 315
Appendix A: Revision History............................................................................................................................................................. 325
Index ................................................................................................................................................................................................. 331
The Microchip Web Site..................................................................................................................................................................... 335
Customer Change Notification Service .............................................................................................................................................. 335
Customer Support.............................................................................................................................................................................. 335
Reader Response .............................................................................................................................................................................. 336
Product Identification System............................................................................................................................................................. 337
DS70287C-page 10
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2009 Microchip Technology Inc.
DS70287C-page 11
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 12
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
These features make this family suitable for a wide vari-
ety of high-performance digital signal control applica-
1.0
DEVICE OVERVIEW
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the latest family
reference sections of the “dsPIC33F
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
tions. The devices are pin compatible with the PIC24H
family of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may be
necessitated by the specific functionality, computational
resource and system cost requirements of the
application.
The dsPIC33FJXXXMCX06/X08/X10 family of devices
employ a powerful 16-bit architecture that seamlessly
integrates the control features of a Microcontroller
(MCU) with the computational capabilities of a Digital
Signal Processor (DSP). The resulting functionality is
ideal for applications that rely on high-speed, repetitive
computations, as well as control.
This document contains device specific information for
the following devices:
• dsPIC33FJ64MC506
• dsPIC33FJ64MC508
• dsPIC33FJ64MC510
• dsPIC33FJ64MC706
• dsPIC33FJ64MC710
• dsPIC33FJ128MC506
• dsPIC33FJ128MC510
• dsPIC33FJ128MC706
• dsPIC33FJ128MC708
• dsPIC33FJ128MC710
• dsPIC33FJ256MC510
• dsPIC33FJ256MC710
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
a wide variety of data addressing modes, together,
provide the dsPIC33FJXXXMCX06/X08/X10 Central
Processing Unit (CPU) with extensive mathematical
processing capability. Flexible and deterministic
interrupt handling, coupled with a powerful array of
peripherals,
renders
the
dsPIC33FJXXXMCX06/X08/X10 devices suitable for
control applications. Further, Direct Memory Access
(DMA) enables overhead-free transfer of data between
several peripherals and a dedicated DMA RAM.
Reliable, field programmable Flash program memory
ensures scalability of applications that use
dsPIC33FJXXXMCX06/X08/X10 devices.
The dsPIC33FJXXXMCX06/X08/X10 includes devices
with a wide range of pin counts (64, 80 and 100), differ-
ent program memory sizes (64 Kbytes, 128 Kbytes and
256 Kbytes) and different RAM sizes (8 Kbytes, 16
Kbytes and 30 Kbytes).
© 2009 Microchip Technology Inc.
DS70287C-page 13
dsPIC33FJXXXMCX06/X08/X10
FIGURE 1-1:
dsPIC33FJXXXMCX06/X08/X10 GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
16
DMA
RAM
Data Latch
Data Latch
X RAM
23
PCH PCL
Program Counter
Y RAM
PCU
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
DMA
16
Controller
23
16
16
PORTC
PORTD
PORTE
PORTF
PORTG
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
Power-up
Timer
Timing
Generation
OSC2/CLKO
OSC1/CLKI
16 x 16
W Register Array
Oscillator
Start-up Timer
Divide Support
FRC/LPRC
Oscillators
16
Power-on
Reset
Precision
Band Gap
Reference
Watchdog
Timer
16-bit ALU
Brown-out
Reset
Voltage
Regulator
16
VCAP/VDDCORE
VDD, VSS
MCLR
Timers
1-9
ADC1,2
I2C1,2
PWM
ECAN1,2
UART1,2
QEI
OC/
IC1-8
CN1-23
SPI1,2
PWM1-8
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70287C-page 14
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin
Buffer
Type
Description
Type
AN0-AN31
AVDD
I
Analog Analog input channels.
P
P
P
P
Positive supply for analog modules. This pin must be connected at all times.
Ground reference for analog modules.
AVSS
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
O
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External
Clock/Gate input in Timer mode.
QEB
I
ST
Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External
Clock/Gate input in Timer mode.
UPDN
O
CMOS Position Up/Down Counter Direction State.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
FLTA
FLTB
I
I
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM 1 low output.
PWM 1 high output.
PWM 2 low output.
PWM 2 high output.
PWM 3 low output.
PWM 3 high output.
PWM 4 low output.
PWM 4 high output.
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
O
O
O
O
O
O
O
O
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
OSC2
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
O = Output
P = Power
I = Input
ST = Schmitt Trigger input with CMOS levels
© 2009 Microchip Technology Inc.
DS70287C-page 15
dsPIC33FJXXXMCX06/X08/X10
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Description
Type
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
RD0-RD15
RE0-RE9
I/O
I/O
I/O
ST
ST
ST
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RF0-RF8
RF12-RF13
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
ST
ST
—
ST
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
O
I/O
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
ST
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
32.768 kHz low-power oscillator crystal output.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
TDO
O
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
U1TX
UART1 transmit.
U2CTS
U2RTS
U2RX
UART2 clear to send.
UART2 ready to send.
UART2 receive.
U2TX
UART2 transmit.
VDD
P
P
—
—
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
VCAP/VDDCORE
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
O = Output
P = Power
I = Input
ST = Schmitt Trigger input with CMOS levels
DS70287C-page 16
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Description
Type
VSS
P
I
—
Ground reference for logic and I/O pins.
VREF+
VREF-
Analog Analog voltage reference (high) input.
Analog Analog voltage reference (low) input.
I
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
O = Output
P = Power
I = Input
ST = Schmitt Trigger input with CMOS levels
© 2009 Microchip Technology Inc.
DS70287C-page 17
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 18
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
CONTROLLERS
Consider the following criteria when using decoupling
capacitors:
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, which is available
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
from
the
Microchip
website
(www.microchip.com).
2.1
Basic Connection Requirements
Getting
started
with
the
dsPIC33FJXXXMCX06/X08/X10 family of 16-bit Digital
Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2009 Microchip Technology Inc.
DS70287C-page 19
dsPIC33FJXXXMCX06/X08/X10
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
• Device Reset
VDD
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
R
R1
MCLR
C
dsPIC33F
VDD
VSS
VDD
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
0.1 µF
Ceramic
Ceramic
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
10 Ω
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
VDD
R
R1
MCLR
dsPIC33F
JP
C
2.3
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
Note 1: R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the
MCLR pin VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
voltage regulator output voltage. The VCAP/VDDCORE
pin must not be connected to VDD, and must have a
capacitor between 4.7 µF and 10 µF, 16V connected to
ground. The type can be ceramic or tantalum. Refer to
Section 26.0 “Electrical Characteristics” for
additional information.
2: R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP/VDDCORE. It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
Section 23.2 “On-Chip Voltage Regulator” for
details.
DS70287C-page 20
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
2.5
ICSP Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3 In-Circuit Debugger”
Main Oscillator
Guard Ring
13
14
15
16
17
18
19
20
Guard Trace
Secondary
Oscillator
(poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
© 2009 Microchip Technology Inc.
DS70287C-page 21
dsPIC33FJXXXMCX06/X08/X10
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3 or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor to VSS on
unused pins and drive the output to logic low.
DS70287C-page 22
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
3.1
Data Addressing Overview
3.0
CPU
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com).
The dsPIC33FJXXXMCX06/X08/X10 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A sin-
gle-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable exe-
cution. All instructions execute in a single cycle, with
the exception of instructions that change the program
flow, the double word move (MOV.D) instruction and the
table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software bound-
ary checking overhead for DSP algorithms. Further-
more, the X AGU circular addressing can be used with
any of the MCU class of instructions. The X AGU also
supports Bit-Reversed Addressing to greatly simplify
input or output data reordering for radix-2 FFT algo-
rithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit Pro-
gram Space Visibility Page (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
The dsPIC33FJXXXMCX06/X08/X10 devices have
sixteen 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th work-
ing register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers but may
be used as general purpose RAM.
3.2
DSP Engine Overview
The dsPIC33FJXXXMCX06/X08/X10 instruction set
has two classes of instructions: MCU and DSP. These
two instruction classes are seamlessly integrated into a
single CPU. The instruction set includes many
addressing modes and is designed for optimum C com-
piler efficiency. For most instructions, the
dsPIC33FJXXXMCX06/X08/X10 is capable of execut-
ing a data (or program data) memory read, a working
register (data) read, a data memory write and a pro-
gram (instruction) memory read per instruction cycle.
As a result, three parameter instructions can be sup-
ported, allowing A + B = C operations to be executed in
a single cycle.
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumu-
lators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left in a single cycle. The DSP instructions oper-
ate seamlessly with all other instructions and have
been designed for optimal real-time performance. The
MAC instruction and other associated instructions can
concurrently fetch two data operands from memory
while multiplying two W registers and accumulating and
optionally saturating the result in the same cycle. This
instruction functionality requires that the RAM memory
data space be split for these instructions and linear for
all others. Data space partitioning is achieved in a
transparent and flexible manner through dedicating
certain working registers to each address space.
A block diagram of the CPU is shown in Figure 3-1, and
the
programmer’s
model
for
shown
the
in
dsPIC33FJXXXMCX06/X08/X10
Figure 3-2.
is
© 2009 Microchip Technology Inc.
DS70287C-page 23
dsPIC33FJXXXMCX06/X08/X10
The dsPIC33FJXXXMCX06/X08/X10 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEATloop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without a loss of data.
3.3
Special MCU Features
The dsPIC33FJXXXMCX06/X08/X10 features a 17-bit
by 17-bit, single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for spe-
cial operations, such as (-1.0) x (-1.0).
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJXXXMCX06/X08/X10 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
Data Latch
16
16
8
16
Data Latch
Y RAM
DMA
RAM
23
16
PCH PCL
Program Counter
PCU
X RAM
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
16 x 16
W Register Array
Divide Support
16
16-bit ALU
16
To Peripheral Modules
DS70287C-page 24
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 3-2:
dsPIC33FJXXXMCX06/X08/X10 PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD15
AD39
AccA
AD31
AD0
DSP
Accumulators
AccB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
DOLoop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV
Z
C
IPL2 IPL1
STATUS Register
SRL
© 2009 Microchip Technology Inc.
DS70287C-page 25
dsPIC33FJXXXMCX06/X08/X10
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA(1)
R/C-0
SB(1)
R-0
R/C-0
SAB
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(2)
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
OA: Accumulator A Overflow Status bit
1= Accumulator A overflowed
0= Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B overflowed
0= Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulators A or B have overflowed
0= Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1= Accumulators A or B are saturated or have been saturated at some time in the past
0= Neither Accumulator A or B are saturated
Note:
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
bit 8
DA: DOLoop Active bit
1= DOloop in progress
0= DOloop not in progress
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
Note 1: This bit may be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
DS70287C-page 26
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation which affects the Z bit has set it at some time in the past
0= The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: This bit may be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
© 2009 Microchip Technology Inc.
DS70287C-page 27
dsPIC33FJXXXMCX06/X08/X10
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
bit 12
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1= DSP engine multiplies are unsigned
0= DSP engine multiplies are signed
bit 11
EDT: Early DOLoop Termination Control bit(1)
1= Terminate executing DOloop at end of current loop iteration
0= No effect
bit 10-8
DL<2:0>: DOLoop Nesting Level Status bits
111= 7 DOloops active
•
•
•
001= 1 DOloop active
000= 0 DOloops active
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SATA: AccA Saturation Enable bit
1= Accumulator A saturation enabled
0= Accumulator A saturation disabled
SATB: AccB Saturation Enable bit
1= Accumulator B saturation enabled
0= Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data space write saturation enabled
0= Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1= Program space visible in data space
0= Program space not visible in data space
RND: Rounding Mode Select bit
1= Biased (conventional) rounding enabled
0= Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode enabled for DSP multiply ops
0= Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70287C-page 28
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The dsPIC33FJXXXMCX06/X08/X10 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N), Over-
flow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow
and Digit Borrow bits, respectively, for subtraction oper-
ations.
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, barrel shifter and 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
a
a
The dsPIC33FJXXXMCX06/X08/X10 is a single-cycle,
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources may be used concurrently by the
same instruction (e.g., ED, EDAC).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUBand NEG.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
1. Fractional or integer DSP multiply (IF)
2. Signed or unsigned DSP multiply (US)
3. Conventional or convergent rounding (RND)
4. Automatic saturation on/off for AccA (SATA)
5. Automatic saturation on/off for AccB (SATB)
6. Automatic saturation on/off for writes to data
memory (SATDW)
The
dsPIC33FJXXXMCX06/X08/X10
CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor
division.
7. Accumulator Saturation mode selection (ACCSAT)
3.5.1
MULTIPLIER
Table 3-1 provides a summary of DSP instructions. A
block diagram of the DSP engine is shown in
Figure 3-3.
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
TABLE 3-1:
DSP INSTRUCTIONS
SUMMARY
1. 16-bit x 16-bit signed
2. 16-bit x 16-bit unsigned
Algebraic
Operation
ACC Write
Instruction
3. 16-bit signed x 5-bit (literal) unsigned
4. 16-bit unsigned x 16-bit unsigned
5. 16-bit unsigned x 5-bit (literal) unsigned
6. 16-bit unsigned x 16-bit signed
7. 8-bit unsigned x 8-bit unsigned
Back
CLR
A = 0
Yes
No
ED
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
EDAC
MAC
No
Yes
No
3.5.2
DIVIDER
MAC
MOVSAC
MPY
No change in A
A = x * y
Yes
No
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
MPY
A = x 2
No
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
MPY.N
MSC
A = – x * y
No
A = A – x * y
Yes
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIVinstructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algo-
rithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
© 2009 Microchip Technology Inc.
DS70287C-page 29
dsPIC33FJXXXMCX06/X08/X10
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
S
a
40
40-bit Accumulator A
40-bit Accumulator B
t
16
40
Round
Logic
u
r
a
t
Carry/Borrow Out
Saturate
e
Adder
Carry/Borrow In
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70287C-page 30
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
3.6.1
MULTIPLIER
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true, or complement
data into the other input. In the case of addition, the
Carry/Borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the Carry/Borrow input is active-low and
the other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS
register:
multiplier/scaler is
a
33-bit value which is
sign-extended to 40 bits. Integer data is inherently rep-
resented as a signed two’s complement value, where
the MSb is defined as a sign bit. Generally speaking,
the range of an N-bit two’s complement integer is -2N-1
to 2N-1 – 1. For a 16-bit integer, the data range is
-32768 (0x8000) to 32767 (0x7FFF) including 0. For a
32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSb is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX
format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1 – 21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF) including 0 and has
a precision of 3.01518x10-5. In Fractional mode, the 16
x 16 multiply operation generates a 1.31 product which
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above and the SAT<A:B> (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
has a precision of 4.65661 x 10-10
.
1. OA:
The same multiplier is used to support the MCU multi-
ply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.
AccA overflowed into guard bits
2. OB:
AccB overflowed into guard bits
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3. SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
4. SB:
AccB saturated (bit 31 overflow and saturation)
or
The data accumulator consists of
a
40-bit
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation desti-
nation. For the ADDand LACinstructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter prior to accumulation.
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when they and the correspond-
ing Overflow Trap Flag Enable bits (OVATE, OVBTE)
in the INTCON1 register (refer to Section 7.0 “Inter-
rupt Controller”) are set. This allows the user to take
immediate action, for example, to correct system gain.
© 2009 Microchip Technology Inc.
DS70287C-page 31
dsPIC33FJXXXMCX06/X08/X10
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When
saturation is not enabled, SA and SB default to bit 39
overflow and, thus, indicate that a catastrophic over-
flow has occurred. If the COVTE bit in the INTCON1
register is set, SA and SB bits will generate an
3.6.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as
1.15 fraction.
arithmetic warning trap when saturation is disabled.
a
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic, which typically uses
both the accumulators.
2. [W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accu-
mulator are written into the address pointed to
by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
3.6.2.3
The round logic is a combinational block which
performs conventional (biased) or convergent
(unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a
16-bit, 1.15 data value which is passed to the data
space write saturation logic. If rounding is not indicated
by the instruction, a truncated 1.15 data value is stored
and the least significant word is simply discarded.
Round Logic
The device supports three Saturation and Overflow
modes:
a
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data or unexpected algorithm problems
(e.g., gain calculations).
Conventional rounding zero-extends bit 15 of the accu-
mulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator). If the ACCxL word (bits 0
through 15 of the accumulator) is between 0x8000 and
0xFFFF (0x8000 included), ACCxH is incremented. If
ACCxL is between 0x0000 and 0x7FFF, ACCxH is left
unchanged. A consequence of this algorithm is that
over a succession of random rounding operations, the
value tends to be biased slightly positive.
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally posi-
tive 1.31 value (0x007FFFFFFF) or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least Signifi-
cant bit (bit 16 of the accumulator) of ACCxH is
examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is
effectively random in nature, this scheme removes any
rounding bias that may accumulate.
3. Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the
X
bus, subject to data saturation (see
Section 3.6.2.4 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator
write-back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
DS70287C-page 32
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
3.6.2.4
Data Space Write Saturation
3.6.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated – but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the max-
imum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The Most
Significant bit of the source (bit 39) is used to determine
the sign of the operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is pre-
sented to the barrel shifter between bit positions 16 to
31 for right shifts and between bit positions 0 to 16 for
left shifts.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
© 2009 Microchip Technology Inc.
DS70287C-page 33
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 34
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
4.1
Program Address Space
4.0
MEMORY ORGANIZATION
The program address memory space of the
dsPIC33FJXXXMCX06/X08/X10 devices is 4M instruc-
tions. The space is addressable by a 24-bit value
derived from either the 23-bit Program Counter (PC)
during program execution, or from table operation or
data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 3. “Data
Memory” (DS70202) and Section 4.
“Program Memory” (DS70203) in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space. Memory usage for the
dsPIC33FJXXXMCX06/X08/X10 family of devices is
shown in Figure 4-1.
The dsPIC33FJXXXMCX06/X08/X10 architecture fea-
tures separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
FIGURE 4-1:
PROGRAM MEMORY MAP FOR dsPIC33FJXXXMCX06/X08/X10 DEVICES
dsPIC33FJ64MCXXX
dsPIC33FJ128MCXXX
dsPIC33FJ256MCXXX
0x000000
0x000002
0x000004
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
User Program
Flash Memory
(22K instructions)
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
Unimplemented
(Read ‘0’s)
0x02ABFE
0x02AC00
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
0xF7FFFE
0xF80000
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
0xF80017
0xF80010
Reserved
DEVID (2)
Reserved
DEVID (2)
Reserved
0xFEFFFE
0xFF0000
DEVID (2)
0xFFFFFE
Note:
Memory areas are not shown to scale.
© 2009 Microchip Technology Inc.
DS70287C-page 35
dsPIC33FJXXXMCX06/X08/X10
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
INTERRUPT AND TRAP VECTORS
All dsPIC33FJXXXMCX06/X08/X10 devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTOinstruction is programmed
by the user at 0x000000, with the actual address for the
start of code at 0x000002.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
dsPIC33FJXXXMCX06/X08/X10 devices also have
two interrupt vector tables located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vec-
tor tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70287C-page 36
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
4.2
Data Address Space
The dsPIC33FJXXXMCX06/X08/X10 CPU has a sepa-
rate 16-bit wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. Data memory
maps of devices with different RAM sizes are shown in
Figure 4-3 through Figure 4-5.
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSb of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
dsPIC33FJXXXMCX06/X08/X10 devices implement a
total of up to 30 Kbytes of data memory. Should an EA
point to a location outside of this area, an all-zero word
or byte will be returned.
4.2.3
SFR SPACE
4.2.1
DATA SPACE WIDTH
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJXXXMCX06/X08/X10 core and peripheral
modules for controlling the operation of the device.
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® micro-
controllers and improve data space memory usage
Note:
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
efficiency,
the
dsPIC33FJXXXMCX06/X08/X10
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all effective
address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws +
1 for byte operations and Ws + 2 for word operations.
4.2.4
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Data byte reads will read the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSb of the data path. That is, data memory and reg-
isters are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
© 2009 Microchip Technology Inc.
DS70287C-page 37
dsPIC33FJXXXMCX06/X08/X10
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06/X08/X10 DEVICES WITH 8 KBS
RAM
MSB
Address
LSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
X Data RAM (X)
Space
8 Kbyte
0x17FF
0x1801
0x17FE
0x1800
SRAM Space
Y Data RAM (Y)
DMA RAM
0x1FFF
0x2001
0x1FFE
0x2000
0x27FF
0x2801
0x27FE
0x2800
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
DS70287C-page 38
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 4-4:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06/X08/X10 DEVICES WITH 16 KB
RAM
LSB
Address
MSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
8 Kbyte
Near
Data
0x07FE
0x0800
0x07FF
0x0801
Space
X Data RAM (X)
0x1FFF
0x1FFE
0x27FF
0x2801
16 Kbyte
SRAM Space
0x27FE
0x2800
Y Data RAM (Y)
DMA RAM
0x3FFF
0x4001
0x3FFE
0x4000
0x47FF
0x4801
0x47FE
0x4800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
© 2009 Microchip Technology Inc.
DS70287C-page 39
dsPIC33FJXXXMCX06/X08/X10
FIGURE 4-5:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06/X08/X10 DEVICES WITH 30 KB
RAM
MSB
LSB
Address
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
8 Kbyte
Near
Data
0x07FE
0x0800
0x07FF
0x0801
Space
X Data RAM (X)
30 Kbyte
SRAM Space
0x47FF
0x4801
0x47FE
0x4800
Y Data RAM (Y)
DMA RAM
0x77FE
0x7800
0x77FF
0x7800
0x7FFE
0x8000
0x7FFF
0x8001
Optionally
Mapped
into Program
Memory
X Data
Unimplemented (X)
0xFFFF
0xFFFE
DS70287C-page 40
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
4.2.5
X AND Y DATA SPACES
4.2.6
DMA RAM
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions) or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
Every dsPIC33FJXXXMCX06/X08/X10 device contains
2 Kbytes of dual ported DMA RAM located at the end of
Y data space. Memory locations is part of Y data RAM
and is in the DMA RAM space are accessible
simultaneously by the CPU and the DMA controller
module. DMA RAM is utilized by the DMA controller to
store data to be transferred to various peripherals using
DMA, as well as data transferred from various
peripherals using DMA. The DMA RAM can be
accessed by the DMA controller without having to steal
cycles from the CPU.
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses for X data space. The X read
data bus is the read data path for all instructions that
view data space as combined X and Y address space.
It is also the X data prefetch path for the dual operand
DSP instructions (MACclass).
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.Nand MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
© 2009 Microchip Technology Inc.
DS70287C-page 41
TABLE 4-1:
CPU CORE REGISTERS MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032
0034
0036
0038
003A
003C
003E
0040
0042
0044
0046
0048
004A
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
00xx
xxxx
00xx
0000
0020
0000
xxxx
xxxx
Stack Pointer Limit Register
ACCAL
Accumulator A Low Word Register
Accumulator A High Word Register
Accumulator A Upper Word Register
Accumulator B Low Word Register
Accumulator B High Word Register
Accumulator B Upper Word Register
Program Counter Low Word Register
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter High Byte Register
Table Page Address Pointer Register
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
DOSTARTH
DOENDL
DOENDH
SR
Program Memory Visibility Page Address Pointer Register
Repeat Loop Counter Register
DCOUNT<15:0>
DOSTARTL<15:1>
0
0
—
—
—
—
—
—
—
—
DOENDL<15:1>
—
—
—
DOSTARTH<5:0>
DOENDH
—
OA
—
—
OB
—
—
SA
—
—
SB
US
—
—
—
—
—
—
OAB
EDT
SAB
DA
DC
IPL2
SATA
IPL1
SATB
IPL0
RA
N
OV
Z
C
CORCON
MODCON
XMODSRT
XMODEND
DL<2:0>
SATDW ACCSAT
IPL3
PSV
RND
IF
XMODEN YMODEN
—
BWM<3:0>
YWM<3:0>
XWM<3:0>
XS<15:1>
XE<15:1>
0
1
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1:
CPU CORE REGISTERS MAP(CONTINUED)
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
YMODSRT
YMODEND
XBREV
004C
004E
0050
0052
0750
0752
YS<15:1>
YE<15:1>
0
1
xxxx
xxxx
xxxx
xxxx
0000
0000
BREN
—
XB<14:0>
DISICNT
BSRAM
—
—
—
Disable Interrupts Counter Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR IR_BSR RL_BSR
IW_SSR IR_SSR RL_SSR
SSRAM
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX10 DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
—
—
—
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX08 DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
—
CN6IE
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
—
—
—
—
—
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX06 DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
—
CN6IE
—
CN5IE
CN4IE
CN3IE
—
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN21IE
CN20IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
CN21PUE CN20PUE
—
—
—
—
—
—
—
—
—
—
—
CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
—
0000
INTCON2 0082 ALTIVT
DISI
—
AD1IF
—
U1TXIF
T5IF
OC8IF
—
—
U1RXIF
T4IF
OC7IF
—
—
—
—
—
T2IF
IC8IF
IC5IF
C2RXIF
C2TXIF
T2IE
IC8IE
IC5IE
C2RXIE
C2TXIE
—
—
—
INT4EP
DMA0IF
INT1IF
DMA3IF
T9IF
INT3EP
T1IF
CNIF
C1IF
T8IF
—
INT2EP
OC1IF
—
INT1EP INT0EP 0000
IC1IF INT0IF 0000
IFS0
0084
—
DMA1IF
SPI1IF SPI1EIF
T3IF
OC2IF
IC7IF
IC2IF
IFS1
0086 U2TXIF U2RXIF
INT2IF
OC4IF OC3IF DMA2IF
AD2IF
MI2C1IF SI2C1IF 0000
SPI2IF SPI2EIF 0000
IFS2
0088
T6IF
DMA4IF
—
—
OC6IF OC5IF
QEIIF PWMIF
IC6IF
C2IF
—
IC4IF
IC3IF
C1RXIF
IFS3
008A FLTAIF
DMA5IF
—
INT4IF
C1TXIF
OC2IE
IC7IE
INT3IF
MI2C2IF SI2C2IF
T7IF
0000
0000
0000
IFS4
008C
0094
—
—
—
—
—
—
—
DMA7IF
DMA6IF
DMA0IE
INT1IE
DMA3IE
T9IE
U2EIF
OC1IE
—
U1EIF
IC1IE
FLTBIF
INT0IE
IEC0
IEC1
IEC2
IEC3
IEC4
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
IPC12
IPC13
IPC14
IPC15
IPC16
IPC17
DMA1IE
AD1IE
U1TXIE
T5IE
OC8IE
—
U1RXIE
T4IE
OC7IE
—
SPI1IE SPI1EIE
T3IE
IC2IE
T1IE
CNIE
C1IE
T8IE
—
0096 U2TXIE U2RXIE
INT2IE
OC4IE OC3IE DMA2IE
AD2IE
MI2C1IE SI2C1IE 0000
SPI2IE SPI2EIE 0000
0098
T6IE
DMA4IE
—
OC6IE OC5IE
QEIIE PWMIE
IC6IE
C2IE
—
IC4IE
IC3IE
C1RXIE
009A FLTAIE
—
—
DMA5IE
—
INT4IE
C1TXIE
INT3IE
MI2C2IE SI2C2IE
T7IE
0000
0000
4444
4444
4444
0444
4044
4444
4444
4444
4444
4444
4444
4404
4444
4444
0444
4040
0444
4444
0000
009C
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00B8
00BA
00BC
00BE
00C0
00C2
00C4
00C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA7IE
DMA6IE
U2EIE
U1EIE
INT0IP<2:0>
DMA0IP<2:0>
T3IP<2:0>
FLTBIE
T1IP<2:0>
T2IP<2:0>
U1RXIP<2:0>
—
—
OC1IP<2:0>
OC2IP<2:0>
SPI1IP<2:0>
DMA1IP<2:0>
—
IC1IP<2:0>
IC2IP<2:0>
SPI1EIP<2:0>
AD1IP<2:0>
MI2C1IP<2:0>
AD2IP<2:0>
OC3IP<2:0>
INT2IP<2:0>
SPI2IP<2:0>
IC3IP<2:0>
OC5IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
U1TXIP<2:0>
SI2C1IP<2:0>
INT1IP<2:0>
DMA2IP<2:0>
T5IP<2:0>
CNIP<2:0>
IC8IP<2:0>
T4IP<2:0>
U2TXIP<2:0>
C1IP<2:0>
IC5IP<2:0>
OC7IP<2:0>
T6IP<2:0>
T8IP<2:0>
C2RXIP<2:0>
—
—
—
—
—
—
—
IC7IP<2:0>
OC4IP<2:0>
U2RXIP<2:0>
C1RXIP<2:0>
IC4IP<2:0>
OC6IP<2:0>
DMA4IP<2:0>
MI2C2IP<2:0>
INT4IP<2:0>
QEIIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
SPI2EIP<2:0>
DMA3IP<2:0>
IC6IP<2:0>
OC8IP<2:0>
T7IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
SI2C2IP<2:0>
INT3IP<2:0>
PWMIP<2:0>
DMA5IP<2:0>
U1EIP<2:0>
DMA7IP<2:0>
—
—
—
—
T9IP<2:0>
—
—
—
—
—
—
—
—
—
C2IP<2:0>
FLTAIP<2:0>
—
—
—
—
—
—
—
—
—
—
U2EIP<2:0>
C1TXIP<2:0>
—
—
FLTBIP<2:0>
DMA6IP<2:0>
C2TXIP<2:0>
—
—
—
—
INTTREG 00E0
Legend:
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
TIMER REGISTER MAP
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
PR1
0100
0102
0104
0106
Timer1 Register
Period Register 1
xxxx
FFFF
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
T1CON
TMR2
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
—
TSYNC
TCS
—
Timer2 Register
TMR3HLD 0108
Timer3 Holding Register (for 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
0114
Period Register 2
PR3
Period Register 3
T2CON
T3CON
TMR4
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer4 Register
TMR5HLD 0116
Timer5 Holding Register (for 32-bit operations only)
Timer5 Register
TMR5
PR4
0118
011A
011C
011E
0120
0122
Period Register 4
PR5
Period Register 5
T4CON
T5CON
TMR6
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer6 Register
TMR7HLD 0124
Timer7 Holding Register (for 32-bit operations only)
Timer7 Register
TMR7
PR6
0126
0128
012A
012C
012E
0130
Period Register 6
PR7
Period Register 7
T6CON
T7CON
TMR8
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer8 Register
TMR9HLD 0132
Timer9 Holding Register (for 32-bit operations only)
Timer9 Register
TMR9
PR8
0134
0136
0138
013A
013C
Period Register 8
PR9
Period Register 9
T8CON
T9CON
Legend:
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1BUF
IC1CON
IC2BUF
IC2CON
IC3BUF
IC3CON
IC4BUF
IC4CON
IC5BUF
IC5CON
IC6BUF
IC6CON
IC7BUF
IC7CON
IC8BUF
IC8CON
Legend:
0140
0142
0144
0146
0148
014A
014C
014E
0150
0152
0154
0156
0158
015A
015C
015E
Input 1 Capture Register
ICTMR
Input 2 Capture Register
ICTMR
Input 3 Capture Register
ICTMR
Input 4 Capture Register
ICTMR
Input 5 Capture Register
ICTMR
Input 6 Capture Register
ICTMR
Input 7 Capture Register
ICTMR
Input 8 Capture Register
ICTMR
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICI<1:0>
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
—
—
—
—
—
—
TABLE 4-8:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
0198
019A
019C
019E
01A0
01A2
01A4
01A6
01A8
01AA
01AC
01AE
Output Compare 1 Secondary Register
Output Compare 1 Register
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
OC1CON
OC2RS
OC2R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Output Compare 2 Secondary Register
Output Compare 2 Register
OC2CON
OC3RS
OC3R
—
—
—
Output Compare 3 Secondary Register
Output Compare 3 Register
OC3CON
OC4RS
OC4R
—
—
—
Output Compare 4 Secondary Register
Output Compare 4 Register
OC4CON
OC5RS
OC5R
—
—
—
Output Compare 5 Secondary Register
Output Compare 5 Register
OC5CON
OC6RS
OC6R
—
—
—
Output Compare 6 Secondary Register
Output Compare 6 Register
OC6CON
OC7RS
OC7R
—
—
—
Output Compare 7 Secondary Register
Output Compare 7 Register
OC7CON
OC8RS
OC8R
—
—
—
Output Compare 8 Secondary Register
Output Compare 8 Register
OC8CON
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
8-OUTPUT PWM REGISTER MAP
SFR Name Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
P1TCON
P1TMR
01C0
01C2 PTDIR
01C4
01C6 SEVTDIR
PTEN
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PWM Timer Count Value Register
PWM Time Base Period Register
P1TPER
P1SECMP
—
PWM Special Event Compare Register
PMOD4 PMOD3 PMOD2 PMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L
PWM1CON1 01C8
PWM1CON2 01CA
P1DTCON1 01CC
P1DTCON2 01CE
—
—
—
—
—
—
—
—
SEVOPS<3:0>
DTB<5:0>
—
—
—
—
—
IUE
OSYNC
UDIS
DTBPS<1:0>
DTAPS<1:0>
DTS4A DTS4I
DTA<5:0>
—
—
—
—
—
—
—
—
DTS3A
—
DTS3I
—
DTS2A
DTS2I
DTS1A
DTS1I
P1FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM
P1FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM
—
FAEN4 FAEN3 FAEN2 FAEN1
FBEN4 FBEN3 FBEN2 FBEN1
—
—
—
P1OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000
P1DC1
P1DC2
P1DC3
P1DC4
01D6
01D8
01DA
01DC
PWM Duty Cycle #1 Register
PWM Duty Cycle #2 Register
PWM Duty Cycle #3 Register
PWM Duty Cycle #4 Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Legend: u= uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-10: QEI REGISTER MAP
SFR
Name
Addr
.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
QEI1CON
01E0 CNTERR
—
—
QEISIDL INDX UPDN
QEIM<2:0>
IMV<1:0>
SWPAB PCDOUT TQGATE
TQCKPS<1:0>
—
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
DFLT1CON 01E2
POS1CNT 01E4
MAX1CNT 01E6
—
—
—
—
CEID QEOUT
Position Counter<15:0>
Maximum Count<15:0>
QECK<2:0>
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
Legend: u= uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-11: I2C1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
0200
0202
0204
0206
0208
020A
020C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
ADD10
IWCOL
I2COV
—
—
—
—
Address Register
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12: I2C2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
0210
0212
0214
0216
0218
021A
021C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
ADD10
IWCOL
—
—
—
—
Address Register
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: UART1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD URXINV
ADDEN RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14: UART2 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U2MODE
U2STA
0230
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD URXINV
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
0232 UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN
URXISEL<1:0>
ADDEN
RIDLE
FERR
OERR
URXDA
U2TXREG
U2RXREG
U2BRG
0234
0236
0238
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: SPI1 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240
0242
0244
0248
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: SPI2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
0260
0262
0264
0268
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI2 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17: ADC1 REGISTER MAP
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
0300
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
0320 ADON
0322
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
0324 ADRC
—
—
—
—
SAMC<4:0>
AD1CHS123 0326
—
—
—
—
—
CH123NB<1:0>
CH0SB<4:0>
CH123SB
—
—
—
—
—
—
—
CH123NA<1:0>
CH123SA 0000
AD1CHS0
0328 CH0NB
CH0NA
CH0SA<4:0>
0000
(1)
AD1PCFGH
AD1PCFGL
032A PCFG31 PCFG30 PCFG29
032C PCFG15 PCFG14 PCFG13
PCFG28
PCFG12
CSS28
CSS12
—
PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16
0000
0000
0000
0000
0000
PCFG11 PCFG10 PCFG9
PCFG8
CSS24
CSS8
—
PCFG7
CSS23
CSS7
—
PCFG6
CSS22
CSS6
—
PCFG5
CSS21
CSS5
—
PCFG4
CSS20
CSS4
—
PCFG3 PCFG2
PCFG1
CSS17
PCFG0
CSS16
CSS0
(1)
AD1CSSH
AD1CSSL
AD1CON4
032E CSS31 CSS30
0330 CSS15 CSS14
CSS29
CSS13
—
CSS27
CSS11
—
CSS26
CSS10
—
CSS25
CSS9
—
CSS19
CSS3
—
CSS18
CSS2
CSS1
0332
—
—
DMABL<2:0>
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
Not all ANx inputs are available on all devices. Refer to the device pin diagrams for available ANx inputs.
TABLE 4-18: ADC2 REGISTER MAP
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC2BUF0 0340
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
AD2CON1
AD2CON2
AD2CON3
0360 ADON
0362
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
0364 ADRC
—
—
—
—
—
SAMC<4:0>
AD2CHS123 0366
—
—
—
—
—
—
—
—
CH123NB<1:0>
CH0SB<3:0>
CH123SB
—
CH0NA
—
—
—
—
—
—
—
—
—
CH123NA<1:0>
CH0SA<3:0>
CH123SA
AD2CHS0
Reserved
0368 CH0NB
036A
—
—
—
—
—
—
—
PCFG8
—
—
PCFG3
—
—
—
—
PCFG0
—
AD2PCFGL 036C PCFG15 PCFG14 PCFG13
PCFG12
—
PCFG11 PCFG10 PCFG9
PCFG7 PCFG6 PCFG5
PCFG4
—
PCFG2 PCFG1
Reserved
AD2CSSL
AD2CON4
Legend:
036E
0370 CSS15
0372
—
—
CSS14
—
—
CSS13
—
—
CSS11
—
—
CSS10
—
—
CSS9
—
—
CSS7
—
—
CSS6
—
—
CSS5
—
—
—
CSS12
—
CSS8
—
CSS4
—
CSS3
—
CSS2
CSS1
CSS0
—
DMABL<2:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: DMA REGISTER MAP
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA0CON 0380 CHEN
DMA0REQ 0382 FORCE
DMA0STA 0384
SIZE
—
DIR
—
HALF
—
NULLW
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA0STB 0386
DMA0PAD 0388
DMA0CNT 038A
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA1CON 038C CHEN
DMA1REQ 038E FORCE
DMA1STA 0390
—
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
—
—
—
—
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA1STB 0392
DMA1PAD 0394
DMA1CNT 0396
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA2CON 0398 CHEN
DMA2REQ 039A FORCE
DMA2STA 039C
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA2STB 039E
DMA2PAD 03A0
DMA2CNT 03A2
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA3CON 03A4 CHEN
DMA3REQ 03A6 FORCE
DMA3STA 03A8
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA3STB 03AA
DMA3PAD 03AC
DMA3CNT 03AE
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA4CON 03B0 CHEN
DMA4REQ 03B2 FORCE
DMA4STA 03B4
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA4STB 03B6
DMA4PAD 03B8
DMA4CNT 03BA
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA5CON 03BC CHEN
DMA5REQ 03BE FORCE
DMA5STA 03C0
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
DMA5STB 03C2
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: DMA REGISTER MAP(CONTINUED)
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA5PAD 03C4
PAD<15:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
DMA5CNT 03C6
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA6CON 03C8 CHEN
DMA6REQ 03CA FORCE
DMA6STA 03CC
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA6STB 03CE
DMA6PAD 03D0
DMA6CNT 03D2
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA7CON 03D4 CHEN
DMA7REQ 03D6 FORCE
DMA7STA 03D8
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA7STB 03DA
DMA7PAD 03DC
DMA7CNT 03DE
—
—
—
—
—
—
CNT<9:0>
DMACS0
DMACS1
DSADR
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000
03E2
03E4
—
—
—
—
LSTCH<3:0>
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0000
0000
DSADR<15:0>
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0OR 1
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1CTRL1
0400
0402
0404
0406
0408
040A
040C
040E
0410
0412
—
—
—
—
CSIDL
—
ABAT
—
—
—
REQOP<2:0>
—
OPMODE<2:0>
—
—
CANCAP
—
—
WIN
0480
0000
0000
0000
0000
0000
0000
0000
0000
0000
FFFF
0000
0000
C1CTRL2
C1VEC
—
—
—
—
—
—
—
—
DNCNT<4:0>
ICODE<6:0>
FSA<4:0>
FNRB<5:0>
FIFOIF RBOVIF
FIFOIE RBOVIE
—
—
FILHIT<4:0>
—
C1FCTRL
C1FIFO
C1INTF
C1INTE
C1EC
DMABS<2:0>
—
—
—
—
—
—
—
—
—
—
—
FBP<5:0>
—
—
TXBO
—
TXBP
—
RXBP
—
TXWAR RXWAR EWARN
IVRIF
IVRIE
WAKIF
WAKIE
ERRIF
ERRIE
—
—
RBIF
RBIE
TBIF
TBIE
—
—
—
TERRCNT<7:0>
RERRCNT<7:0>
BRP<5:0>
C1CFG1
C1CFG2
C1FEN1
—
—
—
—
—
—
—
—
—
—
—
—
SJW<1:0>
WAKFIL
SEG2PH<2:0>
SEG2PHTS
FLTEN7
SAM
FLTEN6 FLTEN5 FLTEN4
SEG1PH<2:0>
FLTEN3
F1MSK<1:0>
F9MSK<1:0>
PRSEG<2:0>
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
FLTEN2 FLTEN1 FLTEN0
C1FMSKSEL1 0418
C1FMSKSEL2 041A
F7MSK<1:0>
F15MSK<1:0>
F6MSK<1:0>
F14MSK<1:0>
F5MSK<1:0>
F13MSK<1:0>
F4MSK<1:0>
F12MSK<1:0>
F3MSK<1:0>
F11MSK<1:0>
F2MSK<1:0>
F10MSK<1:0>
F0MSK<1:0>
F8MSK<1:0>
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-21: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
See definition when WIN = x
C1RXFUL1
C1RXFUL2
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C1TR01CON 0430
C1TR23CON 0432
C1TR45CON 0434
C1TR67CON 0436
TXEN1
TXEN3
TXEN5
TXEN7
TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1
TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3
TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5
TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7
TX1PRI<1:0>
TX3PRI<1:0>
TX5PRI<1:0>
TX7PRI<1:0>
TXEN0
TXEN2
TXEN4
TXEN6
TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0
TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2
TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4
TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6
TX0PRI<1:0>
TX2PRI<1:0>
TX4PRI<1:0>
TX6PRI<1:0>
0000
0000
0000
xxxx
xxxx
xxxx
C1RXD
C1TXD
Legend:
0440
0442
Received Data Word
Transmit Data Word
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See definition when WIN = x
F1BP<3:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
C1BUFPNT1
C1BUFPNT2
C1BUFPNT3
C1BUFPNT4
C1RXM0SID
C1RXM0EID
C1RXM1SID
C1RXM1EID
C1RXM2SID
C1RXM2EID
C1RXF0SID
C1RXF0EID
C1RXF1SID
C1RXF1EID
C1RXF2SID
C1RXF2EID
C1RXF3SID
C1RXF3EID
C1RXF4SID
C1RXF4EID
C1RXF5SID
C1RXF5EID
C1RXF6SID
C1RXF6EID
C1RXF7SID
C1RXF7EID
C1RXF8SID
C1RXF8EID
C1RXF9SID
C1RXF9EID
C1RXF10SID
C1RXF10EID
Legend:
0420
0422
0424
0426
0430
0432
0434
0436
0438
043A
0440
0442
0444
0446
0448
044A
044C
044E
0450
0452
0454
0456
0458
045A
045C
045E
0460
0462
0464
0466
0468
046A
F3BP<3:0>
F2BP<3:0>
F6BP<3:0>
F10BP<3:0>
F14BP<3:0>
F0BP<3:0>
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
F7BP<3:0>
F11BP<3:0>
F15BP<3:0>
F5BP<3:0>
F9BP<3:0>
F13BP<3:0>
F4BP<3:0>
F8BP<3:0>
F12BP<3:0>
SID<10:3>
SID<2:0>
—
MIDE
MIDE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EID<17:16>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EID<17:16>
EID<7:0>
—
MIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1RXF11SID
C1RXF11EID
C1RXF12SID
C1RXF12EID
C1RXF13SID
C1RXF13EID
C1RXF14SID
C1RXF14EID
C1RXF15SID
C1RXF15EID
Legend:
046C
046E
0470
0472
0474
0476
0478
047A
047C
047E
SID<10:3>
SID<2:0>
—
EXIDE
—
EID<17:16>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EXIDE
—
—
—
—
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0OR 1 FOR dsPIC33FJXXXMC708/710 DEVICES
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2CTRL1
C2CTRL2
C2VEC
0500
0502
0504
0506
0508
050A
050C
050E
0510
0512
—
—
—
—
CSIDL
—
ABAT
—
—
—
REQOP<2:0>
—
OPMODE<2:0>
—
—
CANCAP
—
—
WIN
0480
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
—
—
—
—
DNCNT<4:0>
ICODE<6:0>
FSA<4:0>
FNRB<5:0>
—
—
FILHIT<4:0>
—
C2FCTRL
C2FIFO
C2INTF
C2INTE
C2EC
DMABS<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
FBP<5:0>
—
TXBO
—
TXBP
—
RXBP
—
TXWAR RXWAR EWARN
IVRIF
IVRIE
WAKIF ERRIF
WAKIE ERRIE
—
—
FIFOIF RBOVIF
FIFOIE RBOVIE
RBIF
RBIE
TBIF
TBIE
—
—
—
TERRCNT<7:0>
RERRCNT<7:0>
BRP<5:0>
C2CFG1
C2CFG2
C2FEN1
—
—
—
—
—
—
—
—
—
—
—
SJW<1:0>
SEG2PHTS SAM
FLTEN7
F3MSK<1:0>
F11MSK<1:0>
WAKFIL
—
SEG2PH<2:0>
SEG1PH<2:0>
PRSEG<2:0>
0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF
C2FMSKSEL1 0518
C2FMSKSEL2 051A
F7MSK<1:0>
F15MSK<1:0>
F6MSK<1:0>
F14MSK<1:0>
F5MSK<1:0>
F13MSK<1:0>
F4MSK<1:0>
F12MSK<1:0>
F2MSK<1:0>
F10MSK<1:0>
F1MSK<1:0>
F9MSK<1:0>
F0MSK<1:0>
F8MSK<1:0>
0000
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 FOR dsPIC33FJXXXMC708/710 DEVICES
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0500-
051E
See definition when WIN = x
C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000
C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C2TR01CON 0530
C2TR23CON 0532
C2TR45CON 0534
C2TR67CON 0536
TXEN1
TXEN3
TXEN5
TXEN7
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
RTREN3
RTREN5
RTREN7
TX1PRI<1:0>
TX3PRI<1:0>
TX5PRI<1:0>
TX7PRI<1:0>
TXEN0
TXEN2
TXEN4
TXEN6
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
RTREN2
RTREN4
RTREN6
TX0PRI<1:0>
TX2PRI<1:0>
TX4PRI<1:0>
TX6PRI<1:0>
0000
0000
0000
xxxx
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
TX
TX
TX
TX
TX
TX
TX
TX
ABAT7
LARB7
ERR7
REQ7
ABAT6
LARB6
ERR6
REQ6
C2RXD
C2TXD
Legend:
0540
0542
Recieved Data Word
Transmit Data Word
xxxx
xxxx
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXMC708/710 DEVICES
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0500-
051E
See definition when WIN = x
C2BUFPNT1 0520
C2BUFPNT2 0522
C2BUFPNT3 0524
C2BUFPNT4 0526
C2RXM0SID 0530
C2RXM0EID 0532
C2RXM1SID 0534
C2RXM1EID 0536
C2RXM2SID 0538
C2RXM2EID 053A
F3BP<3:0>
F2BP<3:0>
F1BP<3:0>
F0BP<3:0>
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
F7BP<3:0>
F11BP<3:0>
F15BP<3:0>
F6BP<3:0>
F10BP<3:0>
F14BP<3:0>
F5BP<3:0>
F9BP<3:0>
F13BP<3:0>
F4BP<3:0>
F8BP<3:0>
F12BP<3:0>
SID<10:3>
SID<2:0>
—
MIDE
MIDE
—
EID<17:16>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
MIDE
EID<7:0>
C2RXF0SID
C2RXF0EID
C2RXF1SID
C2RXF1EID
C2RXF2SID
C2RXF2EID
C2RXF3SID
C2RXF3EID
C2RXF4SID
C2RXF4EID
C2RXF5SID
C2RXF5EID
C2RXF6SID
C2RXF6EID
C2RXF7SID
C2RXF7EID
C2RXF8SID
C2RXF8EID
C2RXF9SID
C2RXF9EID
0540
0542
0544
0546
0548
054A
054C
054E
0550
0552
0554
0556
0558
055A
055C
055E
0560
0562
0564
0566
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
C2RXF10SID 0568
C2RXF10EID 056A
—
EXIDE
EID<7:0>
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXMC708/710 DEVICES(CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2RXF11SID 056C
C2RXF11EID 056E
C2RXF12SID 0570
C2RXF12EID 0572
C2RXF13SID 0574
C2RXF13EID 0576
C2RXF14SID 0578
C2RXF14EID 057A
C2RXF15SID 057C
C2RXF15EID 057E
SID<10:3>
SID<2:0>
—
EXIDE
—
EID<17:16>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
—
EXIDE
—
—
—
—
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
(1)
TABLE 4-26: PORTA REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
06C0
TRISA15
RA15
TRISA14
RA14
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10
RA10
LATA10
—
TRISA9
RA9
—
—
—
—
TRISA7
RA7
TRISA6
RA6
TRISA5
RA5
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
C6FF
xxxx
xxxx
0000
LATA15
ODCA15
LATA14
ODCA14
LATA9
—
LATA7
—
LATA6
—
LATA5
ODCA5
LATA4
ODCA4
LATA3
ODCA3
LATA2
ODCA2
LATA1
ODCA1
LATA0
ODCA0
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-27: PORTB REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C6
02C8
02CA
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9
TRISB8
RB8
TRISB7
RB7
TRISB6
RB6
TRISB5
RB5
TRISB4
RB4
TRISB3
RB3
TRISB2
RB2
TRISB1 TRISB0
FFFF
xxxx
xxxx
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB1
RB0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-28: PORTC REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISC
PORTC
LATC
02CC TRISC15 TRISC14 TRISC13 TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4
RC4
TRISC3
RC3
TRISC2
RC2
TRISC1
RC1
—
—
—
F01E
xxxx
xxxx
02CE
02D0
RC15
RC14
RC13
RC12
LATC15
LATC14
LATC13
LATC12
LATC4
LATC3
LATC2
LATC1
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-29: PORTD REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISD
PORTD
LATD
02D2
02D4
02D6
06D2
TRISD15
RD15
TRISD14
RD14
TRISD13
RD13
TRISD12
RD12
TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
FFFF
xxxx
xxxx
0000
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD15
ODCD15
LATD14
ODCD14
LATD13
ODCD13
LATD12
ODCD12
LATD11
ODCD11
LATD10
ODCD10
LATD9
ODCD9
LATD8
ODCD8
LATD7
ODCD7
LATD6
ODCD6
LATD5
ODCD5
LATD4
ODCD4
LATD3
ODCD3
LATD2
ODCD2
LATD1
ODCD1
LATD0
ODCD0
ODCD
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-30: PORTE REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISE
PORTE
LATE
02D8
02DA
02DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
RE9
TRISE8
RE8
TRISE7
RE7
TRISE6
RE6
TRISE5
RE5
TRISE4
RE4
TRISE3
RE3
TRISE2
RE2
TRISE1
RE1
TRISE0
RE0
01FF
xxxx
xxxx
LATE9
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-31: PORTF REGISTER MAP
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISF
PORTF
LATF
02DE
02E0
02E2
06DE
—
—
—
—
—
—
—
—
TRISF13
RF13
TRISF12
RF12
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
RF8
TRISF7
RF7
TRISF6
RF6
TRISF5
RF5
TRISF4
RF4
TRISF3
RF3
TRISF2
RF2
TRISF1
RF1
TRISF0
RF0
31FF
xxxx
xxxx
0000
LATF13
ODCF13
LATF12
ODCF12
LATF8
ODCF8
LATF7
ODCF7
LATF6
ODCF6
LATF5
ODCF5
LATF4
ODCF4
LATF3
ODCF3
LATF2
ODCF2
LATF1
ODCF1
LATF0
ODCF0
ODCF
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-32: PORTG REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISG
PORTG
LATG
02E4
02E6
02E8
06E4
TRISG15
RG15
TRISG14
RG14
TRISG13
RG13
TRISG12
RG12
—
—
—
—
—
—
—
—
TRISG9
RG9
TRISG8
RG8
TRISG7
RG7
TRISG6
RG6
—
—
—
—
—
—
—
—
TRISG3
RG3
TRISG2
RG2
TRISG1
RG1
TRISG0
RG0
F3CF
xxxx
xxxx
0000
LATG15
ODCG15
LATG14
ODCG14
LATG13
ODCG13
LATG12
ODCG12
LATG9
ODCG9
LATG8
ODCG8
LATG7
ODCG7
LATG6
ODCG6
LATG3
ODCG3
LATG2
ODCG2
LATG1
ODCG1
LATG0
ODCG0
ODCG
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-33: SYSTEM CONTROL REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
RCON
0740
0742
0744
0746
0748
TRAPR IOPUWR
—
COSC<2:0>
DOZE<2:0>
—
—
—
—
—
—
NOSC<2:0>
FRCDIV<2:0>
—
VREGS
EXTR
SWR
—
SWDTEN WDTO
SLEEP
CF
IDLE
—
BOR
POR
xxxx
0300
3040
0030
0000
(2)
OSCCON
CLKDIV
PLLFBD
OSCTUN
—
CLKLOCK
LOCK
—
—
LPOSCEN OSWEN
ROI
DOZEN
—
PLLPOST<1:0>
PLLPRE<4:0>
—
—
—
—
—
—
—
—
PLLDIV<8:0>
—
—
—
—
—
—
TUN<5:0>
Legend:
Note 1:
2:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and type of Reset.
TABLE 4-34: NVM REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ERASE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
NVMCON
NVMKEY
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMOP<3:0>
0000
NVMKEY<7:0>
0000
Legend:
Note 1:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-35: PMD REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
PMD2
PMD3
Legend:
0770
0772
0774
T5MD
IC8MD
T9MD
T4MD
IC7MD
T8MD
T3MD
IC6MD
T7MD
T2MD
IC5MD
T6MD
T1MD
IC4MD
—
QEIMD
IC3MD
—
PWMMD
IC2MD
—
—
IC1MD
—
I2C1MD
OC8MD
—
U2MD
OC7MD
—
U1MD
OC6MD
—
SPI2MD SPI1MD
C2MD
C1MD
OC2MD
I2C2MD
AD1MD
OC1MD
AD2MD
0000
0000
0000
OC5MD OC4MD OC3MD
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
dsPIC33FJXXXMCX06/X08/X10
4.2.7
SOFTWARE STACK
4.2.8
DATA RAM PROTECTION FEATURE
The dsPIC33FJXXXMCX06/X08/X10 devices supports
Data RAM protection features which enable segments
of RAM to be protected when used in conjunction with
Boot and Secure Code Segment Security. BSRAM
(Secure RAM segment for BS) is accessible only from
the Boot Segment Flash code when enabled. SSRAM
(Secure RAM segment for RAM) is accessible only
from the Secure Segment Flash code when enabled.
See Table 4-1 for an overview of the BSRAM and
SSRAM SFRs.
In addition to its use as a working register, the W15
register in the dsPIC33FJXXXMCX06/X08/X10
devices is also used as a software Stack Pointer. The
Stack Pointer always points to the first available free
word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-6. For a PC push
during any CALL instruction, the MSb of the PC is
zero-extended before the push, ensuring that the MSb
is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
4.3
Instruction Addressing Modes
The addressing modes in Table 4-36 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
4.3.2
MCU INSTRUCTIONS
The 3-operand MCU instructions are of the following
form:
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be register direct) which is
referred to as Wb. Operand 2 can be a W register
fetched from data memory or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
FIGURE 4-6:
CALLSTACK FRAME
0x0000
15
0
• Register Direct
PC<15:0>
000000000
W15 (before CALL)
• Register Indirect
PC<22:16>
<Free Word>
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
© 2009 Microchip Technology Inc.
DS70287C-page 63
dsPIC33FJXXXMCX06/X08/X10
TABLE 4-36: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
The 2-source operand prefetch registers must be
4.3.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU
and W10 and W11 will always be directed to the Y
AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
Register Indirect with Register Offset
Addressing mode is only available for W9
(in X space) and W11 (in Y space).
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by the MACclass of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
In summary, the following Addressing modes are
supported by move and accumulator instructions:
• Register Direct
4.3.5
OTHER INSTRUCTIONS
• Register Indirect
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA(branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISIinstruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
4.4
Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
4.3.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also referred
to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
DS70287C-page 64
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
can operate on any W register pointer. However, it is not
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
advisable to use W14 or W15 for Modulo Addressing,
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for incre-
menting buffers) or end address (for decrementing buf-
fers), based upon the direction of the buffer.
4.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select which registers will
operate with Modulo Addressing. If XWM = 15, X RAGU
and X WAGU Modulo Addressing is disabled. Similarly, if
YWM = 15, Y AGU Modulo Addressing is disabled.
The only exception to the usage restrictions is for
buffers which have a power-of-2 length. As these
buffers satisfy the start and end address criteria, they
may operate in a bidirectional mode (i.e., address
boundary checks will be performed on both the lower
and upper address boundaries).
The X Address Space Pointer W register (XWM) to
which Modulo Addressing is to be applied is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
4.4.1
START AND END ADDRESS
The Modulo Addressing scheme requires that a starting
and ending address be specified and loaded into the
16-bit Modulo Buffer Address registers: XMODSRT,
XMODEND, YMODSRT and YMODEND (see
Table 4-1).
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
Note:
Y space Modulo Addressing EA calcula-
tions assume word sized data (LSb of
every EA is always clear).
FIGURE 4-7:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x1100
MOV
MOV
#0x0000, W0
#0x1110, W1
DO
MOV
AGAIN, #0x31
W0, [W1++]
;fill the 50 buffer locations
;fill the next location
AGAIN: INC W0, W0
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
© 2009 Microchip Technology Inc.
DS70287C-page 65
dsPIC33FJXXXMCX06/X08/X10
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
The modulo corrected effective address is
written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the effective
address. When an address offset (e.g.,
[W7+W2]) is used, Modulo Address cor-
rection is performed but the contents of
the register remain unchanged.
When enabled, Bit-Reversed Addressing is only exe-
cuted for Register Indirect with Pre-Increment or
Post-Increment Addressing and word sized data
writes. It will not function for any other addressing
mode or for byte sized data; normal addresses are gen-
erated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word sized data is a requirement, the LSb
of the EA is ignored (and always clear).
4.5
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user attempts
to do so, Bit-Reversed Addressing will
assume priority for the X WAGU, and X
WAGU Modulo Addressing will be dis-
abled. However, Modulo Addressing will
continue to function in the X RAGU.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when the
following conditions exist:
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
1. The BWM bits (W register selection) in the
MODCON register are any value other than ‘15’
(the stack cannot be accessed using
Bit-Reversed Addressing).
2. The BREN bit is set in the XBREV register.
3. The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
DS70287C-page 66
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 4-8:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b2 b3 b4
0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-37: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
© 2009 Microchip Technology Inc.
DS70287C-page 67
dsPIC33FJXXXMCX06/X08/X10
4.6.1
ADDRESSING PROGRAM SPACE
4.6
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJXXXMCX06/X08/X10 architecture
uses a 24-bit wide program space and a 16-bit wide
data space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside
from
normal
execution,
the
dsPIC33FJXXXMCX06/X08/X10 architecture provides
two methods by which program space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The
remapping method allows an application to access a
large block of data on a read-only basis, which is ideal
for look ups from a large table of static data. It can only
access the least significant word of the program word.
Table 4-38 and Figure 4-9 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
TABLE 4-38: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xxx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
0
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
DS70287C-page 68
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 4-9:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
© 2009 Microchip Technology Inc.
DS70287C-page 69
dsPIC33FJXXXMCX06/X08/X10
2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDHand TBLWTHaccess the space
which contains the upper data byte.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-10:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B(Wn<0> = 0)
TBLRDL.B(Wn<0> = 1)
TBLRDL.B(Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
DS70287C-page 70
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access of stored
constant data from the data space without the need to
use special instructions (i.e., TBLRDL/H).
Note:
PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV and are executed inside a
REPEATloop, there will be some instances that require
two instruction cycles in addition to the specified exe-
cution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Any other iteration of the REPEAT loop will allow the
instruction accessing data using PSV to execute in a
single cycle.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
FIGURE 4-11:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
...whilethelower15bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
© 2009 Microchip Technology Inc.
DS70287C-page 71
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 72
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
then program the digital signal controller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
5.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 5. “Flash
Programming” (DS70191) in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
can write program memory data by blocks (or ‘rows’) of
64 instructions (192 bytes) at a time or by single pro-
gram memory word; and the user can erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
5.1
Table Instructions and Flash
Programming
The dsPIC33FJXXXMCX06/X08/X10 devices contain
internal Flash program memory for storing and execut-
ing application code. The memory is readable, writable
and erasable during normal operation over the entire
VDD range.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
Flash memory can be programmed in two ways:
1. In-Circuit Serial Programming™ (ICSP™)
programming capability
2. Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJXXXMCX06/X08/X10 device
to be serially programmed while in the end application
circuit. This is simply done with two lines for
programming clock and programming data (one of the
alternate programming pin pairs: PGECx/PGEDx), and
three other lines for power (VDD), ground (VSS) and
Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices and
The TBLRDLand TBLWTLinstructions are used to read
or write to bits <15:0> of program memory. TBLRDLand
TBLWTL can access program memory in both Word
and Byte modes.
The TBLRDHand TBLWTHinstructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
© 2009 Microchip Technology Inc.
DS70287C-page 73
dsPIC33FJXXXMCX06/X08/X10
5.2
RTSP Operation
5.3
Programming Operations
The dsPIC33FJXXXMCX06/X08/X10 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user to erase a page of
memory at a time, which consists of eight rows (512
instructions), and to program one row or one word at a
time. Table 26-12 shows typical erase and program-
ming times. The 8-row erase pages and single-row
write rows are edge-aligned, from the beginning of pro-
gram memory, on boundaries of 1536 bytes and 192
bytes, respectively.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 26-12).
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
EQUATION 5-1:
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------
7.37 MHz × (FRC Accuracy)% × (FRC Tuning)%
For example, if the device is operating at +85°C, the
FRC accuracy will be ±2%. If the TUN<5:0> bits (see
Register 9-4) are set to ‘b111111, the Minimum
Row Write Time is:
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
11064 Cycles
----------------------------------------------------------------------------------------------
TRW
=
= 1.48ms
7.37 MHz × (1 + 0.02) × (1 – 0.00375)
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
and, the Maximum Row Write Time is:
written.
programming each row.
A
programming cycle is required for
11064 Cycles
7.37 MHz × (1 – 0.02) × (1 – 0.00375)
---------------------------------------------------------------------------------------------
=
TRW
= 1.54ms
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
DS70287C-page 74
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0(1)
bit 0
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
Legend:
SO = Settable-only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(2)
If ERASE = 1:
1111= Memory bulk erase operation
1110= Reserved
1101= Erase General Segment
1100= Erase Secure Segment
1011= Reserved
0011= No operation
0010= Memory page erase operation
0001= No operation
0000= Erase a single Configuration register byte
If ERASE = 0:
1111= No operation
1110= Reserved
1101= No operation
1100= No operation
1011= Reserved
0011= Memory word program operation
0010= No operation
0001= Memory row program operation
0000= Program a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2009 Microchip Technology Inc.
DS70287C-page 75
dsPIC33FJXXXMCX06/X08/X10
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is as follows:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
1. Read eight rows of program memory
(512 instructions) and store it in data RAM.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
6. Repeat steps 4 and 5 using the next available 64
instructions from the block in data RAM by incre-
menting the value in TBLPAG until all
512 instructions are written back to Flash memory.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
DS70287C-page 76
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
© 2009 Microchip Technology Inc.
DS70287C-page 77
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 78
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
6.0
RESET
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 8.
“Reset” (DS70192) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1). A POR will clear all bits except for
the POR bit (RCON<0>), which is set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
• WDT: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
• IOPUWR: Illegal Opcode and Uninitialized W
Register Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
© 2009 Microchip Technology Inc.
DS70287C-page 79
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 6-1:
RCON: RESET CONTROL REGISTER
R/W-0
TRAPR
bit 15
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IOPUWR
VREGS
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-9
bit 8
Unimplemented: Read as ‘0’
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70287C-page 80
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 6-1:
RCON: RESET CONTROL REGISTER (CONTINUED)
bit 1
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
© 2009 Microchip Technology Inc.
DS70287C-page 81
dsPIC33FJXXXMCX06/X08/X10
TABLE 6-1:
RESET FLAG BIT OPERATION
Flag Bit Setting Event
Trap conflict event
Clearing Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
POR, BOR
POR, BOR
Illegal opcode or uninitialized
W register access
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
MCLR Reset
POR
RESETinstruction
WDT time-out
POR, BOR
PWRSAVinstruction, POR, BOR
PWRSAV #SLEEPinstruction
PWRSAV #IDLEinstruction
BOR, POR
POR, BOR
POR, BOR
—
—
POR
Note: All Reset flag bits may be set or cleared by the user software.
6.1
Clock Source Selection at Reset
6.2
Device Reset Times
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
The Reset times for various types of device Reset are
summarized in Table 6-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
TABLE 6-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Reset Type
Clock Source Determinant
POR
BOR
Oscillator Configuration bits
(FNOSC<2:0>)
MCLR
WDTR
SWR
COSC Control bits
(OSCCON<14:12>)
DS70287C-page 82
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 6-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
FSCM
Delay
Clock Source
SYSRST Delay
Notes
1, 2, 3
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TRST
—
—
TFSCM
TFSCM
TFSCM
—
TLOCK
1, 2, 3, 5, 6
TOST
1, 2, 3, 4, 6
TOST + TLOCK
1, 2, 3, 4, 5, 6
BOR
—
3
TLOCK
TFSCM
TFSCM
TFSCM
—
3, 5, 6
TOST
3, 4, 6
TOST + TLOCK
3, 4, 5, 6
MCLR
—
—
—
—
—
—
3
3
3
3
3
3
WDT
Any Clock
TRST
—
Software
Any Clock
TRST
—
Illegal Opcode
Uninitialized W
Trap Conflict
Any Clock
TRST
—
Any Clock
TRST
—
Any Clock
TRST
—
Note 1: TPOR = Power-on Reset delay (10 μs nominal).
2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down
states, including waking from Sleep mode, if the regulator is enabled.
3: TRST = Internal state Reset time (20 μs nominal).
4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: TLOCK = PLL lock time (20 μs nominal).
6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).
6.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
6.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released:
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available at this time, the device
automatically switches to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
Trap Service Routine.
• The oscillator circuit has not begun to oscillate.
6.2.2.1
FSCM Delay for Crystal and PLL
Clock Sources
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, TFSCM, is
automatically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
© 2009 Microchip Technology Inc.
DS70287C-page 83
dsPIC33FJXXXMCX06/X08/X10
6.3
Special Function Register Reset
States
Most of the Special Function Registers (SFRs)
associated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function, and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of two registers. The
Reset value for the Reset Control register, RCON,
depends on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, depends
on the type of Reset and the programmed values of the
oscillator Configuration bits in the FOSC Configuration
register.
DS70287C-page 84
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
7.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 6.
“Interrupts” (DS70184) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and
a
support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
The interrupt controller for the dsPIC33FJXXXMCX06/
X08/X10 family of devices reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the dsPIC33FJXXXMCX06/X08/X10
CPU. It has the following features:
• Up to eight processor exceptions and software
traps
7.2
Reset Sequence
• Seven user-selectable priority levels
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJXXXMCX06/X08/X10 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins pro-
gram execution at location 0x000000. The user pro-
grams a GOTOinstruction at the Reset address, which
redirects program execution to the appropriate start-up
routine.
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
The dsPIC33FJXXXMCX06/X08/X10 family of
devices implement up to 67 unique interrupts and five
nonmaskable traps. These are summarized in
Table 7-1 and Table 7-2.
© 2009 Microchip Technology Inc.
DS70287C-page 85
dsPIC33FJXXXMCX06/X08/X10
FIGURE 7-1:
dsPIC33FJXXXMCX06/X08/X10 INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
DS70287C-page 86
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 7-1:
INTERRUPT VECTORS
Interrupt
Request(IRQ)
Number
Vector
Number
IVT Address
AIVT Address
Interrupt Source
INT0 – External Interrupt 0
8
0
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
9
1
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
2
3
4
DMA0 – DMA Channel 0
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
5
6
7
8
T3 – Timer3
9
SPI1E – SPI1 Error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – ADC 1
DMA1 – DMA Channel 1
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
Reserved
Change Notification Interrupt
INT1 – External Interrupt 1
ADC2 – ADC 2
IC7 – Input Capture 7
IC8 – Input Capture 8
DMA2 – DMA Channel 2
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
SPI2E – SPI2 Error
SPI1 – SPI1 Transfer Done
C1RX – ECAN1 Receive Data Ready
C1 – ECAN1 Event
DMA3 – DMA Channel 3
IC3 – Input Capture 3
IC4 – Input Capture 4
IC5 – Input Capture 5
IC6 – Input Capture 6
OC5 – Output Compare 5
OC6 – Output Compare 6
OC7 – Output Compare 7
OC8 – Output Compare 8
Reserved
© 2009 Microchip Technology Inc.
DS70287C-page 87
dsPIC33FJXXXMCX06/X08/X10
TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
DMA4 – DMA Channel 4
54
55
46
47
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008E
0x000090
0x000092
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018E
0x000190
0x000192
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
T6 – Timer6
56
48
T7 – Timer7
57
49
SI2C2 – I2C2 Slave Events
MI2C2 – I2C2 Master Events
T8 – Timer8
58
50
59
51
60
52
T9 – Timer9
61
53
INT3 – External Interrupt 3
INT4 – External Interrupt 4
C2RX – ECAN2 Receive Data Ready
C2 – ECAN2 Event
62
54
63
55
64
56
65
57
PWM – PWM Period Match
QEI – Position Counter Compare
DMA5 – DMA Channel 5
Reserved
66
58
69
61
70
62
71
63
FLTA – MCPWM Fault A
FLTB – MCPWM Fault B
U1E – UART1 Error
72
64
73
65
74
66
U2E – UART2 Error
75
67
Reserved
76
68
DMA6 – DMA Channel 6
DMA7 – DMA Channel 7
C1TX – ECAN1 Transmit Data Request
C2TX – ECAN2 Transmit Data Request
Reserved
77
69
78
70
79
71
80-125
72-117
0x0000A4-
0x0000FE
0x0001A4-
0x0001FE
TABLE 7-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
Reserved
0
1
2
3
4
5
6
7
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000104
0x000106
0x000108
0x00010A
0x00010C
0x00010E
0x000110
0x000112
Oscillator Failure
Address Error
Stack Error
Math Error
DMA Error Trap
Reserved
Reserved
DS70287C-page 88
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3
Interrupt Control and Status
Registers
dsPIC33FJXXXMCX06/X08/X10 devices implement a
total of 30 registers for the interrupt controller:
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt prior-
ity level is the priority of the pending interrupt.
• INTCON1
• INTCON2
• IFS0 through IFS4
• IEC0 through IEC4
• IPC0 through IPC17
• INTTREG
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality. The CPU
STATUS register, SR, contains the IPL<2:0> bits
(SR<7:5>). These bits indicate the current CPU
interrupt priority level. The user can change the current
CPU priority level by writing to the IPL bits.
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a Status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The CORCON register contains the IPL3 bit which,
together with IPL<2:0>, also indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
All Interrupt registers are described in Register 7-1
through Register 7-32 in the following pages.
© 2009 Microchip Technology Inc.
DS70287C-page 89
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 7-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
R/C-0
SAB
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1: “SR: CPU STATUS REGISTER”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
(1)
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 3-2: “CORCON: CORE CONTROL REGISTER”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70287C-page 90
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR
OVBERR
COVAERR COVBERR
OVATE
OVBTE
COVTE
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
DMACERR MATHERR ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B enabled
0= Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divide by zero
0= Math error trap was not caused by a divide by zero
bit 5
DMACERR: DMA Controller Error Status bit
1= DMA controller error trap has occurred
0= DMA controller error trap has not occurred
bit 4
MATHERR: Arithmetic Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
© 2009 Microchip Technology Inc.
DS70287C-page 91
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
DS70287C-page 92
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
ALTIVT
bit 15
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DISI
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
© 2009 Microchip Technology Inc.
DS70287C-page 93
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
DMA1IF
U1TXIF
U1RXIF
SPI1EIF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
R/W-0
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
DMA01IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
DMA01IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70287C-page 94
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
DS70287C-page 95
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
U2TXIF
bit 15
R/W-0
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
R/W-0
OC4IF
R/W-0
OC3IF
R/W-0
U2RXIF
DMA21IF
bit 8
R/W-0
IC8IF
R/W-0
IC7IF
R/W-0
AD2IF
R/W-0
INT1IF
R/W-0
CNIF
U-0
—
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
DMA21IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70287C-page 96
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
DS70287C-page 97
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
R/W-0
T6IF
R/W-0
U-0
—
R/W-0
OC8IF
R/W-0
OC7IF
R/W-0
OC6IF
R/W-0
OC5IF
R/W-0
IC6IF
DMA4IF
bit 15
bit 8
R/W-0
IC5IF
R/W-0
IC4IF
R/W-0
IC3IF
R/W-0
R/W-0
C1IF
R/W-0
R/W-0
SPI2IF
R/W-0
DMA3IF
C1RXIF
SPI2EIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
T6IF: Timer6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
Unimplemented: Read as ‘0’
OC8IF: Output Compare Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
OC7IF: Output Compare Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC6IF: Output Compare Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC6IF: Input Capture Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C1IF: ECAN1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70287C-page 98
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED)
bit 2
bit 1
bit 0
C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2IF: SPI2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2EIF: SPI2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
DS70287C-page 99
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0
FLTAIF
bit 15
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
QEIIF
R/W-0
R/W-0
C2IF
DMA5IF
PWMIF
bit 8
R/W-0
C2RXIF
bit 7
R/W-0
INT4IF
R/W-0
INT3IF
R/W-0
T9IF
R/W-0
T8IF
R/W-0
R/W-0
R/W-0
T7IF
MI2C2IF
SI2C2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FLTAIF: PWM Fault A Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 14
bit 13
Unimplemented: Read as ‘0’
DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-11
bit 10
Unimplemented: Read as ‘0’
QEIIF: QEI Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PWMIF: PWM Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C2IF: ECAN2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT4IF: External Interrupt 4 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT3IF: External Interrupt 3 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T9IF: Timer9 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T8IF: Timer8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C2IF: I2C2 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70287C-page 100
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3 (CONTINUED)
bit 1
SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
T7IF: Timer7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
DS70287C-page 101
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
C2TXIF
bit 7
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U2EIF
R/W-0
U1EIF
R/W-0
C1TXIF
DMA7IF
DMA6IF
FLTBIF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
bit 5
bit 4
C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
bit 2
Unimplemented: Read as ‘0’
U2EIF: UART2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 1
bit 0
U1EIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
FLTBIF: PWM Fault B Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70287C-page 102
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
DMA1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
R/W-0
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
DMA0IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1EIE: SPI1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
DS70287C-page 103
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70287C-page 104
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
T5IE
R/W-0
T4IE
R/W-0
OC4IE
R/W-0
OC3IE
R/W-0
U2TXIE
U2RXIE
INT2IE
DMA2IE
bit 15
bit 8
R/W-0
IC8IE
R/W-0
IC7IE
R/W-0
AD2IE
R/W-0
R/W-0
CNIE
U-0
—
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
AD2IE: ADC2 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
DS70287C-page 105
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70287C-page 106
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
R/W-0
T6IE
R/W-0
U-0
—
R/W-0
OC8IE
R/W-0
OC7IE
R/W-0
OC6IE
R/W-0
OC5IE
R/W-0
IC6IE
DMA4IE
bit 15
bit 8
R/W-0
IC5IE
R/W-0
IC4IE
R/W-0
IC3IE
R/W-0
R/W-0
C1IE
R/W-0
R/W-0
R/W-0
DMA3IE
C1RXIE
SPI2IE
SPI2EIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
T6IE: Timer6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
Unimplemented: Read as ‘0’
OC8IE: Output Compare Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C1IE: ECAN1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
DS70287C-page 107
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED)
bit 2
bit 1
bit 0
C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2IE: SPI2 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2EIE: SPI2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70287C-page 108
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
QEIIE
R/W-0
R/W-0
C2IE
FLTAIE
DMA5IE
PWMIE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
T9IE
R/W-0
T8IE
R/W-0
R/W-0
R/W-0
T7IE
C2RXIE
INT4IE
INT3IE
MI2C2IE
SI2C2IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FLTAIE: PWM Fault A Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 14
bit 13
Unimplemented: Read as ‘0’
DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12-11
bit 10
Unimplemented: Read as ‘0’
QEIIE: QEI Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PWMIE: PWM Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C2IE: ECAN2 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT4IE: External Interrupt 4 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT3IE: External Interrupt 3 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T9IE: Timer9 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T8IE: Timer8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
MI2C2IE: I2C2 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
DS70287C-page 109
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED)
bit 1
SI2C2IE: I2C2 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
T7IE: Timer7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70287C-page 110
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U2EIE
R/W-0
U1EIE
R/W-0
C2TXIE
C1TXIE
DMA7IE
DMA6IE
FLTBIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
bit 5
bit 4
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
bit 2
Unimplemented: Read as ‘0’
U2EIE: UART2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 1
bit 0
U1EIE: UART1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
FLTBIE: PWM Fault B Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
DS70287C-page 111
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC1IP<2:0>
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 112
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T2IP<2:0>
OC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC2IP<2:0>
DMA0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 113
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U1RXIP<2:0>
SPI1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI1EIP<2:0>
T3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 114
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DMA1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD1IP<2:0>
U1TXIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 115
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CNIP<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 116
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IC8IP<2:0>
IC7IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD2IP<2:0>
INT1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 117
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T4IP<2:0>
OC4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
OC3IP<2:0>
DMA2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T4IP<2:0>: Timer4 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 118
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U2TXIP<2:0>
U2RXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
INT2IP<2:0>
T5IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 119
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C1IP<2:0>
C1RXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI2IP<2:0>
SPI2EIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C1IP<2:0>: ECAN1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 120
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IC5IP<2:0>
IC4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC3IP<2:0>
DMA3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 121
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
OC7IP<2:0>
OC6IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
OC5IP<2:0>
IC6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 122
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T6IP<2:0>
DMA4IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
OC8IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T6IP<2:0>: Timer6 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 123
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T8IP<2:0>
MI2C2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SI2C2IP<2:0>
T7IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T8IP<2:0>: Timer8 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T7IP<2:0>: Timer7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 124
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C2RXIP<2:0>
INT4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
INT3IP<2:0>
T9IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
INT4IP<2:0>: External Interrupt 4 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT3IP<2:0>: External Interrupt 3 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T9IP<2:0>: Timer9 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 125
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-29: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
QEIIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
PWMIP<2:0>
C2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
QEIIP<2:0>: QEI Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWMIP<2:0>: PWM Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
C2IP<2:0>: ECAN2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 126
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
FLTAIP<2:0>
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
DMA5IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
FLTAIP<2:0>: PWM Fault A Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
DS70287C-page 127
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U2EIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
U1EIP<2:0>
FLTBIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
U2EIP<2:0>: UART2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
FLTBIP<2:0>: PWM Fault B Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70287C-page 128
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-32: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C2TXIP<2:0>
C1TXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
DMA7IP<2:0>
DMA6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 129
dsPIC33FJXXXMCX06/X08/X10
REGISTER 7-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
DS70287C-page 130
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
7.4.3
TRAP SERVICE ROUTINE
7.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.1
INITIALIZATION
To configure an interrupt source, do the following:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
7.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
All user interrupts can be disabled using the following
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POPinstruction may be
Note: At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to priority level 4.
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-level 15)
cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISIinstruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI instruction.
4. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., C or assembler) and
the language development tool suite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of interrupt that the ISR handles. Otherwise, the
ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
© 2009 Microchip Technology Inc.
DS70287C-page 131
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 132
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
The DMA controller features eight identical data
8.0
DIRECT MEMORY ACCESS
(DMA)
transfer channels. Each channel has its own set of
control and status registers. Each DMA channel can be
configured to copy data either from buffers stored in
dual port DMA RAM to peripheral SFRs or from
peripheral SFRs to buffers in DMA RAM.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 22.
“Direct Memory Access (DMA)”
(DS70182) in the “dsPIC33F Family
Reference Manual”, which is available
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral.
• Indirect Addressing of DMA RAM locations with or
without automatic post-increment.
from
the
Microchip
web
site
(www.microchip.com).
• Peripheral Indirect Addressing – In some
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral.
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., the UART Receive register and Input Capture 1
buffer) and buffers or variables stored in RAM, with
minimal CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and, therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
• One-Shot Block Transfers – Terminating DMA
transfer after one block transfer.
• Continuous Block Transfers – Reloading DMA
RAM buffer start address after every block
transfer is complete.
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
• Automatic or manual initiation of block transfers.
• Each channel can select from 20 possible
sources of data sources or destinations.
For each DMA channel, a DMA interrupt request is
The dsPIC33FJXXXMCX06/X08/X10 peripherals that
can utilize DMA are listed in Table 8-1 along with their
associated Interrupt Request (IRQ) numbers.
generated when
a
block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
TABLE 8-1:
PERIPHERALS WITH DMA
SUPPORT
Peripheral
IRQ Number
INT0
0
1
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
5
2
6
7
Timer3
8
SPI1
10
33
11
12
30
31
13
21
34
70
55
71
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
ECAN1 Reception
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
© 2009 Microchip Technology Inc.
DS70287C-page 133
dsPIC33FJXXXMCX06/X08/X10
FIGURE 8-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA
Ready
Peripheral 3
DMA
Channels
DMA RAM
SRAM
PORT 1 PORT 2
CPU DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU DMA
DMA
Ready
CPU DMA
Non-DMA
Ready
DMA
Ready
Peripheral 2
CPU
Peripheral
Peripheral 1
Note: For clarity, CPU and DMA address buses are not shown.
8.1
DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
(DMAxCON)
• A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
• A 16-bit DMA RAM Primary Start Address Offset
register (DMAxSTA)
• A 16-bit DMA RAM Secondary Start Address
Offset register (DMAxSTB)
• A 16-bit DMA Peripheral Address register
(DMAxPAD)
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DS70287C-page 134
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
CHEN
R/W-0
SIZE
R/W-0
DIR
R/W-0
HALF
R/W-0
U-0
—
U-0
—
U-0
—
NULLW
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
AMODE<1:0>
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
CHEN: Channel Enable bit
1= Channel enabled
0= Channel disabled
SIZE: Data Transfer Size bit
1= Byte
0= Word
DIR: Transfer Direction bit (source/destination bus select)
1= Read from DMA RAM address; write to peripheral address
0= Read from peripheral address; write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1= Initiate block transfer complete interrupt when half of the data has been moved
0= Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0= Normal operation
bit 10-6
bit 5-4
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11= Reserved
10= Peripheral Indirect Addressing mode
01= Register Indirect without Post-Increment mode
00= Register Indirect with Post-Increment mode
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10= Continuous, Ping-Pong modes enabled
01= One-Shot, Ping-Pong modes disabled
00= Continuous, Ping-Pong modes disabled
© 2009 Microchip Technology Inc.
DS70287C-page 135
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0
FORCE(1)
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL6(2) IRQSEL5(2) IRQSEL4(2) IRQSEL3(2) IRQSEL2(2)
IRQSEL1(2) IRQSEL0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit(1)
1= Force a single DMA transfer (Manual mode)
0= Automatic DMA transfer initiation by DMA request
bit 14-7
bit 6-0
Unimplemented: Read as ‘0’
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)
0000000-1111111= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ
Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
2: See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources.
DS70287C-page 136
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-3:
DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
STA<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STA<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
REGISTER 8-4:
DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
STB<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STB<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
© 2009 Microchip Technology Inc.
DS70287C-page 137
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 8-5:
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PAD<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
PAD<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PAD<15:0>: Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
(1)
REGISTER 8-6:
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CNT<9:8>(2)
bit 15
bit 8
R/W-0
bit 0
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: Number of DMA transfers = CNT<9:0> + 1.
DS70287C-page 138
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0
R/C-0
PWCOL7
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
PWCOL6
PWCOL5
PWCOL4
PWCOL3
PWCOL2
PWCOL1
PWCOL0
bit 8
R/C-0
XWCOL7
bit 7
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
XWCOL6
XWCOL5
XWCOL4
XWCOL3
XWCOL2
XWCOL1
XWCOL0
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 8
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 7
XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 6
XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 5
XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 4
XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
© 2009 Microchip Technology Inc.
DS70287C-page 139
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
XWCOL3: Channel 3 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL2: Channel 2 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL1: Channel 1 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
DS70287C-page 140
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-8:
DMACS1: DMA CONTROLLER STATUS REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R-1
R-1
R-1
LSTCH<3:0>
bit 15
bit 8
R-0
PPST7
bit 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
LSTCH<3:0>: Last DMA Channel Active bits
1111= No DMA transfer has occurred since system Reset
1110-1000= Reserved
0111= Last data transfer was by DMA Channel 7
0110= Last data transfer was by DMA Channel 6
0101= Last data transfer was by DMA Channel 5
0100= Last data transfer was by DMA Channel 4
0011= Last data transfer was by DMA Channel 3
0010= Last data transfer was by DMA Channel 2
0001= Last data transfer was by DMA Channel 1
0000= Last data transfer was by DMA Channel 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PPST7: Channel 7 Ping-Pong Mode Status Flag bit
1= DMA7STB register selected
0= DMA7STA register selected
PPST6: Channel 6 Ping-Pong Mode Status Flag bit
1= DMA6STB register selected
0= DMA6STA register selected
PPST5: Channel 5 Ping-Pong Mode Status Flag bit
1= DMA5STB register selected
0= DMA5STA register selected
PPST4: Channel 4 Ping-Pong Mode Status Flag bit
1= DMA4STB register selected
0= DMA4STA register selected
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1= DMA3STB register selected
0= DMA3STA register selected
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1= DMA2STB register selected
0= DMA2STA register selected
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1= DMA1STB register selected
0= DMA1STA register selected
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1= DMA0STB register selected
0= DMA0STA register selected
© 2009 Microchip Technology Inc.
DS70287C-page 141
dsPIC33FJXXXMCX06/X08/X10
REGISTER 8-9:
DSADR: MOST RECENT DMA RAM ADDRESS
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
DSADR<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits
DS70287C-page 142
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
9.0
OSCILLATOR
CONFIGURATION
• The internal FRC oscillator can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 7.
“Oscillator” (DS70186) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
The dsPIC33FJXXXMCX06/X08/X10 oscillator system
provides the following:
A simplified diagram of the oscillator system is shown
in Figure 9-1.
• Various external and internal oscillator options as
clock sources
FIGURE 9-1:
dsPIC33FJXXXMCX06/X08/X10 OSCILLATOR SYSTEM DIAGRAM
dsPIC33F
Primary Oscillator
POSCMD<1:0>
OSC1
DOZE<2:0>
XT, HS, EC
S2
(2)
R
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
S1
FCY
(1)
S1/S3
PLL
OSC2
FP
÷ 2
FRC
Oscillator
FRCDIVN
FOSC
S7
FRCDIV<2:0>
TUN<5:0>
FRCDIV16
FRC
S6
S0
÷ 16
LPRC
SOSC
LPRC
Oscillator
S5
Secondary Oscillator
S4
LPOSCEN
SOSCO
SOSCI
Clock Switch
Reset
Clock Fail
S7
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note 1: See Figure 9-2 for PLL details.
2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.
© 2009 Microchip Technology Inc.
DS70287C-page 143
dsPIC33FJXXXMCX06/X08/X10
POSCMD<1:0> (FOSC<1:0>), select the oscillator
source that is used at a Power-on Reset. The FRC pri-
mary oscillator is the default (unprogrammed) selection.
9.1
CPU Clocking System
There are seven system clock options provided by the
dsPIC33FJXXXMCX06/X08/X10:
The Configuration bits allow users to choose between
twelve different clock modes, shown in Table 9-1.
• FRC Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• LPRC Oscillator
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected), FOSC, is divided by 2
to generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJXXXMCX06/
X08/X10 architecture.
• FRC Oscillator with postscaler
9.1.1
SYSTEM CLOCK SOURCES
Instruction execution speed or device operating
frequency, FCY, is given by the following equation:
The FRC (Fast RC) internal oscillator runs at a nominal
frequency of 7.37 MHz. The user software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
EQUATION 9-1:
DEVICE OPERATING
FREQUENCY
FOSC
2
-------------
FCY =
The primary oscillator can use one of the following as
its clock source:
9.1.3
PLL CONFIGURATION
1. XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides a significant amount of
flexibility in selecting the device operating speed. A
block diagram of the PLL is shown in Figure 9-2.
2. HS (High-Speed Crystal): Crystals in the range
of 10 MHz to 40 MHz. The crystal is connected
to the OSC1 and OSC2 pins.
3. EC (External Clock): External clock signal is
directly applied to the OSC1 pin.
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected to be in the range of 0.8 MHz to 8 MHz.
Since the minimum prescale factor is 2, this implies that
FIN must be chosen to be in the range of 1.6 MHz to 16
MHz. The prescale factor, ‘N1’, is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
The LPRC (Low-Power RC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The PLL Feedback Divisor, selected using the
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 9.1.3 “PLL
Configuration”.
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor,
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
The FRC frequency depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4).
9.1.2
SYSTEM CLOCK SELECTION
For a primary oscillator or FRC oscillator output, ‘FIN’,
the PLL output, ‘FOSC’, is given by the following
equation:
The oscillator source that is used at a device Power-on
Reset event is selected using Configuration bit settings.
The oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 23.1 “Configuration Bits” for further details.)
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary
EQUATION 9-2:
FOSC CALCULATION
M
N1 ⋅ N2
⎛
⎝
⎞
⎠
------------------
FOSC = FIN ⋅
Oscillator
Mode
Select
Configuration
bits,
DS70287C-page 144
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
For example, suppose a 10 MHz crystal is being used
with “XT with PLL” as the selected oscillator mode. If
PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO
input of 10/2 = 5 MHz, which is within the acceptable
range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then
M = 32. This yields a VCO output of 5 * 32 = 160 MHz,
which is within the 100-200 MHz ranged needed.
EQUATION 9-3:
XT WITH PLL MODE
EXAMPLE
FOSC
1 10000000 ⋅ 32
⎛
-- ---------------------------------
⎞
⎠
-------------
FCY =
=
= 40 MIPS
⎝
2
2
2 ⋅ 2
If PLLPOST<1:0> = 0, then N2 = 2. This provides a
Fosc of 160/2 = 80 MHz. The resultant device operating
speed is 80/2 = 40 MIPS.
FIGURE 9-2:
dsPIC33FJXXXMCX06/X08/X10 PLL BLOCK DIAGRAM
FVCO
0.8-8.0 MHz
100-200 MHz
Here(1)
12.5-80 MHz
Here(1)
Here(1)
Source (Crystal, External Clock
or Internal RC)
FOSC
PLLPRE
VCO
PLLPOST
X
PLLDIV
N1
Divide by
2-33
N2
Divide by
2, 4, 8
M
Divide by
2-513
Note 1: This frequency range must be satisfied at all times.
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
1, 2
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Internal
xx
111
Internal
xx
110
1
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Low-Power RC Oscillator (LPRC)
Internal
Secondary
Primary
xx
xx
10
101
100
011
1
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL
(HSPLL)
—
Primary Oscillator (XT) with PLL
(XTPLL)
Primary
Primary
01
00
011
011
—
1
Primary Oscillator (EC) with PLL
(ECPLL)
Primary Oscillator (HS)
Primary
Primary
Primary
Internal
Internal
10
01
00
xx
xx
010
010
010
001
000
—
—
1
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
1
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
© 2009 Microchip Technology Inc.
DS70287C-page 145
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
NOSC<2:0>(2)
R/W-y
bit 8
COSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
U-0
—
R-0
U-0
—
R/C-0
CF
U-0
—
R/W-0
R/W-0
LOCK
LPOSCEN
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 7
CLKLOCK: Clock Lock Enable bit
1= If (FCKSM0 = 1), then clock and PLL configurations are locked
If (FCKSM0 = 0), then clock and PLL configurations may be modified
0= Clock and PLL selections are not locked; configurations may be modified
bit 6
bit 5
Unimplemented: Read as ‘0’
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
bit 2
Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
DS70287C-page 146
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
(1)
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
© 2009 Microchip Technology Inc.
DS70287C-page 147
dsPIC33FJXXXMCX06/X08/X10
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
000= FCY/1
001= FCY/2
010= FCY/4
011= FCY/8 (default)
100= FCY/16
101= FCY/32
110= FCY/64
111= FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000= FRC divide by 1 (default)
001= FRC divide by 2
010= FRC divide by 4
011= FRC divide by 8
100= FRC divide by 16
101= FRC divide by 32
110= FRC divide by 64
111= FRC divide by 256
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
00= Output/2
01= Output/4 (default)
10= Reserved
11= Output/8
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000= Input/2 (default)
00001= Input/3
•
•
•
11111= Input/33
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
DS70287C-page 148
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0(1)
PLLDIV<8>
bit 8
bit 15
R/W-0
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000= 2
000000001= 3
000000010= 4
•
•
•
000110000= 50 (default)
•
•
•
111111111= 513
© 2009 Microchip Technology Inc.
DS70287C-page 149
dsPIC33FJXXXMCX06/X08/X10
REGISTER 9-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Center frequency + 11.625% (8.23 MHz)
011110= Center frequency + 11.25% (8.20 MHz)
•
•
•
000001= Center frequency + 0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency – 0.375% (7.345 MHz)
•
•
•
100001= Center frequency – 11.625% (6.52 MHz)
100000= Center frequency – 12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
DS70287C-page 150
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
2. If a valid clock switch has been initiated, the
9.2
Clock Switching Operation
LOCK
(OSCCON<5>)
and
the
CF
Applications are free to switch between any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects that could result from this flexibility,
dsPIC33FJXXXMCX06/X08/X10 devices have a safe-
guard lock built into the switch process.
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC) which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
9.2.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 23.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing sensitive code should not be
executed during this time.
2: Direct clock switches between any primary
oscillator mode with PLL and FRCPLL
mode are not permitted. This applies to
clock switches in either direction. In these
instances, the application must switch to
FRC mode as a transition clock source
between the two PLL modes.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
3: Refer to 7. “Oscillator” (DS70186) in the
“dsPIC33F Family Reference Manual” for
details.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
9.2.2
OSCILLATOR SWITCHING SEQUENCE
9.3
Fail-Safe Clock Monitor (FSCM)
At a minimum, performing a clock switch requires the
following basic sequence:
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
1. If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
© 2009 Microchip Technology Inc.
DS70287C-page 151
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 152
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
10.2 Instruction-Based Power-Saving
Modes
10.0 POWER-SAVING FEATURES
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 9.
“Watchdog Timer and Power-Saving
Modes” (DS70196) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
dsPIC33FJXXXMCX06/X08/X10 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code execu-
tion. Idle mode halts the CPU and code execution, but
allows peripheral modules to continue operation. The
assembly syntax of the PWRSAVinstruction is shown in
Example 10-1.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
The dsPIC33FJXXXMCX06/X08/X10 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower con-
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
sumed
power.
dsPIC33FJXXXMCX06/X08/X10
10.2.1
SLEEP MODE
devices can manage power consumption in four differ-
ent ways:
Sleep mode has the following features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
10.1 Clock Frequency and Clock
Switching
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports
and peripherals that use an external clock input.
Any peripheral that requires the system clock
source for its operation is disabled in Sleep mode.
dsPIC33FJXXXMCX06/X08/X10 devices allow a wide
range of clock frequencies to be selected under appli-
cation control. If the system clock configuration is not
locked, users can choose low-power or high-precision
oscillators by simply changing the NOSC bits (OSC-
CON<10:8>). The process of changing a system clock
during operation, as well as limitations to the process,
are discussed in more detail in Section 9.0 “Oscillator
Configuration”.
The device will wake-up from Sleep mode on any of
the following events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
EXAMPLE 10-1:
PWRSAVINSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
© 2009 Microchip Technology Inc.
DS70287C-page 153
dsPIC33FJXXXMCX06/X08/X10
Doze mode is enabled by setting the DOZEN bit (CLK-
DIV<11>). The ratio between peripheral and core clock
speed is determined by the DOZE<2:0> bits (CLK-
DIV<14:12>). There are eight possible configurations,
from 1:1 to 1:128, with 1:1 being the default setting.
10.2.2
IDLE MODE
Idle mode has the following features:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
It is also possible to use Doze mode to selectively
reduce power consumption in event-driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of the fol-
lowing events:
• Any interrupt that is individually enabled
• Any device Reset
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
• A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAVinstruction or
the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
10.4 Peripheral Module Disable
Any interrupt that coincides with the execution of a
PWRSAVinstruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled via the appropriate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
10.3 Doze Mode
Generally, changing clock speed and invoking one of the
power-saving modes are the preferred strategies for
reducing power consumption. There may be cir-
cumstances, however, where this is not practical. For
example, it may be necessary for an application to main-
tain uninterrupted synchronous communication, even
while it is doing nothing else. Reducing system clock
speed may introduce communication errors, while using
a power-saving mode may stop communications
completely.
A peripheral module is only enabled if both the associ-
ated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC® DSC variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70287C-page 154
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
T5MD
R/W-0
T4MD
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
R/W-0
R/W-0
U-0
—
QEI1MD
PWMMD
bit 15
bit 8
R/W-0
R/W-0
U2MD
R/W-0
U1MD
R/W-0
R/W-0
R/W-0
C2MD
R/W-0
C1MD
R/W-0
I2C1MD
SPI2MD
SPI1MD
AD1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
T5MD: Timer5 Module Disable bit
1= Timer5 module is disabled
0= Timer5 module is enabled
T4MD: Timer4 Module Disable bit
1= Timer4 module is disabled
0= Timer4 module is enabled
T3MD: Timer3 Module Disable bit
1= Timer3 module is disabled
0= Timer3 module is enabled
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
QEI1MD: QEI1 Module Disable bit
1= QEI1 module is disabled
0= QEI1 module is enabled
PWMMD: PWM Module Disable bit
1= PWM module is disabled
0= PWM module is enabled
bit 8
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
bit 6
bit 5
bit 4
bit 3
U2MD: UART2 Module Disable bit
1= UART2 module is disabled
0= UART2 module is enabled
U1MD: UART1 Module Disable bit
1= UART1 module is disabled
0= UART1 module is enabled
SPI2MD: SPI2 Module Disable bit
1= SPI2 module is disabled
0= SPI2 module is enabled
SPI1MD: SPI1 Module Disable bit
1= SPI1 module is disabled
0= SPI1 module is enabled
© 2009 Microchip Technology Inc.
DS70287C-page 155
dsPIC33FJXXXMCX06/X08/X10
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
C2MD: ECAN2 Module Disable bit
1= ECAN2 module is disabled
0= ECAN2 module is enabled
C1MD: ECAN1 Module Disable bit
1= ECAN1 module is disabled
0= ECAN1 module is enabled
AD1MD: ADC1 Module Disable bit
1= ADC1 module is disabled
0= ADC1 module is enabled
DS70287C-page 156
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
IC8MD: Input Capture 8 Module Disable bit
1= Input Capture 8 module is disabled
0= Input Capture 8 module is enabled
IC7MD: Input Capture 7 Module Disable bit
1= Input Capture 7 module is disabled
0= Input Capture 7 module is enabled
IC6MD: Input Capture 6 Module Disable bit
1= Input Capture 6 module is disabled
0= Input Capture 6 module is enabled
IC5MD: Input Capture 5 Module Disable bit
1= Input Capture 5 module is disabled
0= Input Capture 5 module is enabled
IC4MD: Input Capture 4 Module Disable bit
1= Input Capture 4 module is disabled
0= Input Capture 4 module is enabled
IC3MD: Input Capture 3 Module Disable bit
1= Input Capture 3 module is disabled
0= Input Capture 3 module is enabled
IC2MD: Input Capture 2 Module Disable bit
1= Input Capture 2 module is disabled
0= Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7
OC8MD: Output Compare 8 Module Disable bit
1= Output Compare 8 module is disabled
0= Output Compare 8 module is enabled
bit 6
OC7MD: Output Compare 4 Module Disable bit
1= Output Compare 7 module is disabled
0= Output Compare 7 module is enabled
bit 5
OC6MD: Output Compare 6 Module Disable bit
1= Output Compare 6 module is disabled
0= Output Compare 6 module is enabled
bit 4
OC5MD: Output Compare 5 Module Disable bit
1= Output Compare 5 module is disabled
0= Output Compare 5 module is enabled
© 2009 Microchip Technology Inc.
DS70287C-page 157
dsPIC33FJXXXMCX06/X08/X10
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
OC4MD: Output Compare 4 Module Disable bit
1= Output Compare 4 module is disabled
0= Output Compare 4 module is enabled
OC3MD: Output Compare 3 Module Disable bit
1= Output Compare 3 module is disabled
0= Output Compare 3 module is enabled
OC2MD: Output Compare 2 Module Disable bit
1= Output Compare 2 module is disabled
0= Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
DS70287C-page 158
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
R/W-0
T9MD
R/W-0
T8MD
R/W-0
T7MD
R/W-0
T6MD
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
I2C2MD
AD2MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
T9MD: Timer9 Module Disable bit
1= Timer9 module is disabled
0= Timer9 module is enabled
T8MD: Timer8 Module Disable bit
1= Timer8 module is disabled
0= Timer8 module is enabled
T7MD: Timer7 Module Disable bit
1= Timer7 module is disabled
0= Timer7 module is enabled
T6MD: Timer6 Module Disable bit
1= Timer6 module is disabled
0= Timer6 module is enabled
bit 11-2
bit 1
Unimplemented: Read as ‘0’
I2C2MD: I2C2 Module Disable bit
1= I2C2 module is disabled
0= I2C2 module is enabled
bit 0
AD2MD: AD2 Module Disable bit
1= AD2 module is disabled
0= AD2 module is enabled
© 2009 Microchip Technology Inc.
DS70287C-page 159
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 160
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
When a peripheral is enabled and actively driving an
associated pin, the use of the pin as a general purpose
11.0 I/O PORTS
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If
a peripheral is enabled but the peripheral is not actively
driving a pin, that pin may be driven by a port.
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 10. “I/O
Ports” (DS70193) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch. Reads from the port
(PORTx), read the port pins, while writes to the port
pins, write the latch.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKIN) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device will be disabled.
That means the corresponding LATx and TRISx
registers and the port pins will read as zeros.
11.1 Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The periph-
eral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
Note:
The voltage on a digital input pin can be
between -0.3V to 5.6V.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
Output Enable
0
1
0
PIO Module
Output Data
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR PORT
CK
Data Latch
Read LAT
Read Port
Input Data
© 2009 Microchip Technology Inc.
DS70287C-page 161
dsPIC33FJXXXMCX06/X08/X10
11.2 Open-Drain Configuration
11.4 I/O Port Write/Read Timing
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.5 Input Change Notification
The input change notification function of the I/O ports
allows the dsPIC33FJXXXMCX06/X08/X10 devices to
generate interrupt requests to the processor in
response to a change-of-state on selected input pins.
This feature is capable of detecting input
change-of-states even in Sleep mode, when the clocks
are disabled. Depending on the device pin count, there
are up to 24 external signals (CN0 through CN23) that
can be selected (enabled) for generating an interrupt
request on a change-of-state.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired
digital-only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See “Pin Diagrams” for the available pins and their
functionality.
11.3 Configuring Analog Port Pins
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
CN interrupt enable (CNxIE) control bits for each of the
CN input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
The ADxPCFGH, ADxPCFGL and TRIS registers con-
trol the operation of the ADC port pins. The port pins
that are desired as analog inputs must have their cor-
responding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL) is
converted.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the weak pull-up
enable (CNxPUE) bits for each of the CN pins. Setting
any of the control bits enables the weak pull-ups for the
corresponding pins.
Clearing any bit in the ADxPCFGH or ADxPCFGL reg-
ister configures the corresponding bit to be an analog
pin. This is also the Reset state of any I/O pin that has
an analog (ANx) function associated with it.
Note:
In devices with two ADC modules, if the
corresponding PCFG bit in either
AD1PCFGH(L) and AD2PCFGH(L) is
cleared, the pin is configured as an analog
input.
Note:
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
Note:
The voltage on an analog input pin can be
between -0.3V to (VDD + 0.3 V).
EXAMPLE 11-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
btss
0xFF00, W0
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
W0, TRISBB
PORTB, #13
; Next Instruction
DS70287C-page 162
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Timer1 also supports the following features:
12.0 TIMER1
• Timer gate operation
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 11.
“Timers” (DS70205) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
Figure 12-1 presents a block diagram of the 16-bit
timer module.
To configure Timer1 for operation, do the following:
1. Set the TON bit (= 1) in the T1CON register.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock or operate as
a free-running interval timer/counter. Timer1 can oper-
ate in three modes:
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
3. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
• 16-bit Timer
4. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
TON
2
SOSCO/
1x
01
00
T1CK
Prescaler
1, 8, 64, 256
Gate
Sync
SOSCEN
SOSCI
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T1IF
CK
0
Reset
Equal
TMR1
1
Sync
TSYNC
Comparator
PR1
© 2009 Microchip Technology Inc.
DS70287C-page 163
dsPIC33FJXXXMCX06/X08/X10
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When T1CS = 1:
This bit is ignored.
When T1CS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin T1CK (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
DS70287C-page 164
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
13.0 TIMER2/3, TIMER4/5, TIMER6/7
AND TIMER8/9
Note:
For 32-bit operation, T3CON, T5CON,
T7CON and T9CON control bits are
ignored. Only T2CON, T4CON, T6CON
and T8CON control bits are used for setup
and control. Timer2, Timer4, Timer6 and
Timer8 clock and gate inputs are utilized
for the 32-bit timer modules, but an inter-
rupt is generated with the Timer3, Timer5,
Ttimer7 and Timer9 interrupt flags.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 11.
“Timers” (DS70205) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9
for 32-bit operation, do the following:
1. Set the corresponding T32 control bit.
The Timer2/3, Timer4/5, Timer6/7 and Timer8/9
modules are 32-bit timers that can also be configured
as four independent 16-bit timers with selectable
operating modes.
2. Select the prescaler ratio for Timer2, Timer4,
Timer6 or Timer8 using the TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and
Timer8/9 operate in three modes:
4. Load the timer period value. PR3, PR5, PR7 or
PR9 contains the most significant word of the
value, while PR2, PR4, PR6 or PR8 contains the
least significant word.
• Two Independent 16-bit Timers (e.g., Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
5. If interrupts are required, set the interrupt enable
bit, T3IE, T5IE, T7IE or T9IE. Use the priority
bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or
T9IP<2:0>, to set the interrupt priority. While
Timer2, Timer4, Timer6 or Timer8 control the
timer, the interrupt appears as a Timer3, Timer5,
Timer7 or Timer9 interrupt.
• Single 32-bit Timer
• Single 32-bit Synchronous Counter
They also support the following features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-bit Period Register Match
6. Set the corresponding TON bit.
The timer value at any point is stored in the register
pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or
TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always
contain the most significant word of the count, while
TMR2, TMR4, TMR6 or TMR8 contain the least
significant word.
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
• ADC1 Event Trigger (Timer2/3 only)
• ADC2 Event Trigger (Timer4/5 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger; this
is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON,
T5CON, T6CON, T7CON, T8CON and T9CON regis-
ters. T2CON, T4CON, T6CON and T8CON are shown
in generic form in Register 13-1. T3CON, T5CON,
T7CON and T9CON are shown in Register 13-2.
To configure any of the timers for individual 16-bit
operation, do the following:
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
For 32-bit timer/counter operation, Timer2, Timer4,
Timer6 or Timer8 is the least significant word; Timer3,
Timer5, Timer7 or Timer9 is the most significant word
of the 32-bit timers.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
A block diagram for a 32-bit timer pair (Timer4/5)
example is shown in Figure 13-1, and a timer (Timer4)
operating in 16-bit mode example is shown in
Figure 13-2.
Note:
Only Timer2 and Timer3 can trigger a
DMA data transfer.
© 2009 Microchip Technology Inc.
DS70287C-page 165
dsPIC33FJXXXMCX06/X08/X10
(1)
FIGURE 13-1:
TIMER2/3 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
1x
01
00
T2CK
Gate
Sync
Prescaler
1, 8, 64, 256
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T3IF
CK
PR2
PR3
ADC Event Trigger(2)
Equal
Reset
Comparator
MSb
LSb
TMR3
TMR2
Sync
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
2: The ADC event trigger is available only on Timer2/3.
DS70287C-page 166
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 13-2:
TIMER2 (16-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TGATE
TCS
TGATE
TCY
1
0
Q
D
Set T2IF
Q
CK
Reset
Equal
Sync
TMR2
Comparator
PR2
© 2009 Microchip Technology Inc.
DS70287C-page 167
dsPIC33FJXXXMCX06/X08/X10
REGISTER 13-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32
U-0
—
R/W-0
TCS(1)
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timerx On bit
When T32 = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When T32 = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-bit Timer Mode Select bit
1= Timerx and Timery form a single 32-bit timer
0= Timerx and Timery act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(1)
1= External clock from pin TxCK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
DS70287C-page 168
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS<1:0>(1)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(1,3)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(1)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(2)
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(1,3)
1= External clock from pin TyCK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through T2CON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
© 2009 Microchip Technology Inc.
DS70287C-page 169
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 170
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
2. Capture timer value on every edge (rising and
falling) of input at ICx pin
14.0 INPUT CAPTURE
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
3. Prescaler Capture Event modes
-Capture timer value on every 4th rising edge
of input at ICx pin
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 12.
“Input Capture” (DS70198) in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
-Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include the following:
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJXXXMCX06/X08/X10 devices support
up to eight input capture channels.
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
1. Simple Capture Event modes
-Capture timer value on every falling edge of
input at ICx pin
Note:
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00).
-Capture timer value on every rising edge of
input at ICx pin
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMRy TMRz
16
16
ICTMR
(ICxCON<7>)
1
0
Edge Detection Logic
and
Clock Synchronizer
FIFO
R/W
Logic
Prescaler
Counter
(1, 4, 16)
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICxI<1:0>
Interrupt
Logic
ICxCON
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2009 Microchip Technology Inc.
DS70287C-page 171
dsPIC33FJXXXMCX06/X08/X10
14.1 Input Capture Registers
REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
bit 0
R/W-0
ICTMR(1)
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
ICI<1:0>
ICM<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module will halt in CPU Idle mode
0= Input capture module will continue to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits(1)
1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty; at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000= Input capture module turned off
Note 1: Timer selections may vary. Refer to the device data sheet for details.
DS70287C-page 172
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
The state of the output pin changes when the timer
value matches the Compare register value. The output
compare module generates either a single output
pulse, or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The output compare module can also generate
interrupts on compare match events.
15.0 OUTPUT COMPARE
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 13. “Output
Compare” (DS70209), which is available
The output compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
on
the
Microchip
web
site
(www.microchip.com).
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without Fault Protection
• PWM mode with Fault Protection
The output compare module can select either Timer2 or
Timer3 for its time base. The module compares the
value of the timer with the value of one or two Compare
registers depending on the operating mode selected.
FIGURE 15-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
OCxR(1)
Output
Logic
S
R
Q
OCx(1)
Output Enable
3
OCM<2:0>
Mode Select
OCFA
or
Comparator
OCFB(2)
0
0
OCTSEL
1
1
16
16
TMR2
Rollover
TMR3
Rollover
TMR3
TMR2
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.
2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8.
© 2009 Microchip Technology Inc.
DS70287C-page 173
dsPIC33FJXXXMCX06/X08/X10
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
15.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
Note:
See Section 13. “Output Compare” in
the “dsPIC33F Family Reference Manual”
(DS70209) for OCxR and OCxRS register
restrictions.
TABLE 15-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
Module Disabled
OCx Pin Initial State
OCx Interrupt Generation
000
001
010
011
100
101
110
Controlled by GPIO register
—
Active-Low One-Shot
Active-High One-Shot
Toggle
0
1
OCx rising edge
OCx falling edge
Current output is maintained OCx rising and falling edge
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
0
0
OCx falling edge
OCx falling edge
No interrupt
‘0’, if OCxR is zero
‘1’, if OCxR is non-zero
111
PWM with Fault Protection
‘0’, if OCxR is zero
OCFA falling edge for OC1 to OC4
‘1’, if OCxR is non-zero
FIGURE 15-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode Enabled
Timer is Reset on
Period Match
OCxRS
OCxR
TMRy
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse
(OCM = 101)
PWM
(OCM = 110or 111)
DS70287C-page 174
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2)
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R-0, HC
OCFLT
R/W-0
R/W-0
R/W-0
OCTSEL
OCM<2:0>
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare x halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low
001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled
© 2009 Microchip Technology Inc.
DS70287C-page 175
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 176
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
• ‘On-the-fly’ PWM frequency changes
16.0 MOTOR CONTROL PWM
• Edge and Center-Aligned Output modes
• Single Pulse Generation mode
MODULE
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 14.
“Motor Control PWM” (DS70187) in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
• Interrupt support for asymmetrical updates in
Center-Aligned mode
• Output override control for Electrically
Commutative Motor (ECM) operation
• ‘Special Event’ comparator for scheduling other
peripheral events
• Fault pins to optionally drive each of the PWM
output pins to a defined state
• Duty cycle updates are configurable to be
immediate or synchronized to the PWM time base
This module simplifies the task of generating multiple,
synchronized Pulse-Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
This module contains four duty cycle generators,
numbered 1 through 4. The module has eight PWM
output pins, numbered PWM1H/PWM1L through
PWM4H/PWM4L. The eight I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
• 3-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• Uninterruptible Power Supply (UPS)
The PWM module allows several modes of operation
which are beneficial for specific power control
applications.
The PWM module has the following features:
• Eight PWM I/O pins with four duty cycle generators
• Up to 16-bit resolution
© 2009 Microchip Technology Inc.
DS70287C-page 177
dsPIC33FJXXXMCX06/X08/X10
FIGURE 16-1:
PWM MODULE BLOCK DIAGRAM
PWMxCON1
PWM Enable and Mode SFRs
Dead-Time Control SFRs
Fault Pin Control SFRs
PWMxCON2
PxDTCON1
PxDTCON2
PxFLTACON
PxFLTBCON
PxOVDCON
PWM Manual
Control SFR
PWM Generator 4
PxDC4 Buffer
PxDC4
PWM4H
PWM4L
Comparator
Channel 4 Dead-Time
Generator and
Override Logic
PWM
Generator 3
PWM3H
PWM3L
PxTMR
Comparator
PxTPER
Channel 3 Dead-Time
Generator and
Output
Driver
Block
Override Logic
PWM
Generator 2
PWM2H
PWM2L
Channel 2 Dead-Time
Generator and
Override Logic
PWM
Generator 1
PWM1H
PWM1L
Channel 1 Dead-Time
Generator and
Override Logic
PxTPER Buffer
PxTCON
FLTA
FLTB
Special Event
Postscaler
Comparator
PxSECMP
Special Event Trigger
SEVTDIR
PTDIR
PWM Time Base
Note:
For clarity, details of PWM Generator 1, 2 and 3 are not shown.
DS70287C-page 178
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-1: PxTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PTSIDL
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTEN: PWM Time Base Timer Enable bit
1= PWM time base is on
0= PWM time base is off
bit 14
bit 13
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1= PWM time base halts in CPU Idle mode
0= PWM time base runs in CPU Idle mode
bit 12-8
bit 7-4
Unimplemented: Read as ‘0’
PTOPS<3:0>: PWM Time Base Output Postscale Select bits
1111= 1:16 postscale
•
•
•
0001= 1:2 postscale
0000= 1:1 postscale
bit 3-2
bit 1-0
PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits
11= PWM time base input clock period is 64 TCY (1:64 prescale)
10= PWM time base input clock period is 16 TCY (1:16 prescale)
01= PWM time base input clock period is 4 TCY (1:4 prescale)
00= PWM time base input clock period is TCY (1:1 prescale)
PTMOD<1:0>: PWM Time Base Mode Select bits
11= PWM time base operates in a Continuous Up/Down Count mode with interrupts for double
PWM updates
10= PWM time base operates in a Continuous Up/Down Count mode
01= PWM time base operates in Single Pulse mode
00= PWM time base operates in a Free-Running mode
© 2009 Microchip Technology Inc.
DS70287C-page 179
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-2: PxTMR: PWM TIMER COUNT VALUE REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PTDIR
PTMR<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTMR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTDIR: PWM Time Base Count Direction Status bit (read-only)
1= PWM time base is counting down
0= PWM time base is counting up
bit 14-0
PTMR <14:0>: PWM Time Base Register Count Value bits
REGISTER 16-3: PxTPER: PWM TIME BASE PERIOD REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PTPER<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTPER<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
PTPER<14:0>: PWM Time Base Period Value bits
bit 14-0
DS70287C-page 180
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER
R/W-0
SEVTDIR(1)
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<14:8>(2)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
SEVTCMP<7:0>(2)
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SEVTDIR: Special Event Trigger Time Base Direction bit(1)
1= A Special Event Trigger will occur when the PWM time base is counting downwards
0= A Special Event Trigger will occur when the PWM time base is counting upwards
bit 14-0
SEVTCMP<14:0>: Special Event Compare Value bits(2)
Note 1: SEVTDIR is compared with PTDIR (PTMR<15>) to generate the Special Event Trigger.
2: SEVTCMP<14:0> is compared with PTMR<14:0> to generate the Special Event Trigger.
© 2009 Microchip Technology Inc.
DS70287C-page 181
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-5: PWMxCON1: PWM CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PMOD4
PMOD3
PMOD2
PMOD1
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PEN4H(1)
PEN3H(1)
PEN2H(1)
PEN1H(1)
PEN4L(1)
PEN3L(1)
PEN2L(1)
PEN1L(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
PMOD<4:1>: PWM I/O Pair Mode bits
1= PWM I/O pin pair is in the Independent PWM Output mode
0= PWM I/O pin pair is in the Complementary Output mode
bit 7-4
bit 3-0
PEN4H:PEN1H: PWMxH I/O Enable bits(1)
1= PWMxH pin is enabled for PWM output
0= PWMxH pin is disabled; I/O pin becomes general purpose I/O
PEN4L:PEN1L: PWMxL I/O Enable bits(1)
1= PWMxL pin is enabled for PWM output
0= PWMxL pin is disabled; I/O pin becomes general purpose I/O
Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in
the FPOR Configuration register.
DS70287C-page 182
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-6: PWMxCON2: PWM CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
SEVOPS<3:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IUE
R/W-0
R/W-0
UDIS
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111= 1:16 postscale
•
•
•
0001= 1:2 postscale
0000= 1:1 postscale
bit 7-3
bit 2
Unimplemented: Read as ‘0’
IUE: Immediate Update Enable bit
1= Updates to the active PDC registers are immediate
0= Updates to the active PDC registers are synchronized to the PWM time base
bit 1
bit 0
OSYNC: Output Override Synchronization bit
1= Output overrides via the OVDCON register are synchronized to the PWM time base
0= Output overrides via the OVDCON register occur on next TCY boundary
UDIS: PWM Update Disable bit
1= Updates from Duty Cycle and Period Buffer registers are disabled
0= Updates from Duty Cycle and Period Buffer registers are enabled
© 2009 Microchip Technology Inc.
DS70287C-page 183
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-7: PxDTCON1: DEAD-TIME CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTB<5:0>
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DTBPS<1:0>
bit 15
R/W-0
DTAPS<1:0>
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
DTA<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
DTBPS<1:0>: Dead-Time Unit B Prescale Select bits
11= Clock period for Dead-Time Unit B is 8 TCY
10= Clock period for Dead-Time Unit B is 4 TCY
01= Clock period for Dead-Time Unit B is 2 TCY
00= Clock period for Dead-Time Unit B is TCY
bit 13-8
bit 7-6
DTB<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit B bits
DTAPS<1:0>: Dead-Time Unit A Prescale Select bits
11= Clock period for Dead-Time Unit A is 8 TCY
10= Clock period for Dead-Time Unit A is 4 TCY
01= Clock period for Dead-Time Unit A is 2 TCY
00= Clock period for Dead-Time Unit A is TCY
bit 5-0
DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits
DS70287C-page 184
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
DTS4I
R/W-0
R/W-0
DTS3I
R/W-0
R/W-0
DTS2I
R/W-0
R/W-0
DTS1I
DTS4A
DTS3A
DTS2A
DTS1A
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
DTS4A: Dead-Time Select for PWM4 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DTS4I: Dead-Time Select for PWM4 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS3A: Dead-Time Select for PWM3 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS2A: Dead-Time Select for PWM2 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS1A: Dead-Time Select for PWM1 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
© 2009 Microchip Technology Inc.
DS70287C-page 185
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-9: PxFLTACON: FAULT A CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FAOV4H
FAOV4L
FAOV3H
FAOV3L
FAOV2H
FAOV2L
FAOV1H
FAOV1L
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
FLTAM
FAEN4
FAEN3
FAEN2
FAEN1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
FAOVxH<4:1>:FAOVxL<4:1>: Fault Input A PWM Override Value bits
1= The PWM output pin is driven active on an external Fault input event
0= The PWM output pin is driven inactive on an external Fault input event
FLTAM: Fault A Mode bit
1= The Fault A input pin functions in the Cycle-by-Cycle mode
0= The Fault A input pin latches all control pins to the states programmed in FLTACON<15:8>
bit 6-4
bit 3
Unimplemented: Read as ‘0’
FAEN4: Fault Input A Enable bit
1= PWM4H/PWM4L pin pair is controlled by Fault Input A
0= PWM4H/PWM4L pin pair is not controlled by Fault Input A
bit 2
bit 1
bit 0
FAEN3: Fault Input A Enable bit
1= PWM3H/PWM3L pin pair is controlled by Fault Input A
0= PWM3H/PWM3L pin pair is not controlled by Fault Input A
FAEN2: Fault Input A Enable bit
1= PWM2H/PWM2L pin pair is controlled by Fault Input A
0= PWM2H/PWM2L pin pair is not controlled by Fault Input A
FAEN1: Fault Input A Enable bit
1= PWM1H/PWM1L pin pair is controlled by Fault Input A
0= PWM1H/PWM1L pin pair is not controlled by Fault Input A
DS70287C-page 186
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-10: PxFLTBCON: FAULT B CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FBOV4H
FBOV4L
FBOV3H
FBOV3L
FBOV2H
FBOV2L
FBOV1H
FBOV1L
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
FBEN4(1)
R/W-0
FBEN3(1)
R/W-0
FBEN2(1)
R/W-0
FBEN1(1)
FLTBM
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
FBOVxH<4:1>:FBOVxL<4:1>: Fault Input B PWM Override Value bits
1= The PWM output pin is driven active on an external Fault input event
0= The PWM output pin is driven inactive on an external Fault input event
FLTBM: Fault B Mode bit
1= The Fault B input pin functions in the Cycle-by-Cycle mode
0= The Fault B input pin latches all control pins to the states programmed in FLTBCON<15:8>
bit 6-4
bit 3
Unimplemented: Read as ‘0’
FBEN4: Fault Input B Enable bit(1)
1= PWM4H/PWM4L pin pair is controlled by Fault Input B
0= PWM4H/PWM4L pin pair is not controlled by Fault Input B
bit 2
bit 1
bit 0
FBEN3: Fault Input B Enable bit(1)
1= PWM3H/PWM3L pin pair is controlled by Fault Input B
0= PWM3H/PWM3L pin pair is not controlled by Fault Input B
FBEN2: Fault Input B Enable bit(1)
1= PWM2H/PWM2L pin pair is controlled by Fault Input B
0= PWM2H/PWM2L pin pair is not controlled by Fault Input B
FBEN1: Fault Input B Enable bit(1)
1= PWM1H/PWM1L pin pair is controlled by Fault Input B
0= PWM1H/PWM1L pin pair is not controlled by Fault Input B
Note 1: Fault A pin has priority over Fault B pin, if enabled.
© 2009 Microchip Technology Inc.
DS70287C-page 187
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-11: PxOVDCON: OVERRIDE CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD4H
POVD4L
POVD3H
POVD3L
POVD2H
POVD2L
POVD1H
POVD1L
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POUT4H
POUT4L
POUT3H
POUT3L
POUT2H
POUT2L
POUT1H
POUT1L
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
POVDxH<4:1>:POVDxL<4:1>: PWM Output Override bits
1= Output on PWMx I/O pin is controlled by the PWM generator
0= Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit
POUTxH<4:1>:POUTxL<4:1>: PWM Manual Output bits
1= PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared
0= PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared
DS70287C-page 188
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-12: PxDC1: PWM DUTY CYCLE REGISTER 1
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC1<15:8>
R/W-0
R/W-0
R/W-0
PDC1<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC1<15:0>: PWM Duty Cycle #1 Value bits
REGISTER 16-13: PxDC2: PWM DUTY CYCLE REGISTER 2
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC2<15:8>
R/W-0
R/W-0
R/W-0
PDC2<7:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC2<15:0>: PWM Duty Cycle #2 Value bits
© 2009 Microchip Technology Inc.
DS70287C-page 189
dsPIC33FJXXXMCX06/X08/X10
REGISTER 16-14: PxDC3: PWM DUTY CYCLE REGISTER 3
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC3<15:8>
R/W-0
R/W-0
R/W-0
PDC3<7:0>
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC3<15:0>: PWM Duty Cycle #3 Value bits
REGISTER 16-15: PxDC4: PWM DUTY CYCLE REGISTER 4
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC4<15:8>
R/W-0
R/W-0
R/W-0
PDC4<7:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC4<15:0>: PWM Duty Cycle #4 Value bits
DS70287C-page 190
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
The operational features of the QEI include the follow-
ing:
17.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
• Three input channels for two phase signals and
an index pulse
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 15.
“Quadrature Encoder Interface (QEI)”
(DS70208) in the “dsPIC33F Family Ref-
erence Manual”, which is available from
the Microchip web site (www.micro-
chip.com).
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
The QEI module’s operating mode is determined by
setting
the
appropriate
bits,
QEIM<2:0>
(QEICON<10:8>). Figure 17-1 depicts the Quadrature
Encoder Interface block diagram.
This section describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
FIGURE 17-1:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
Sleep Input
TQCS
2
TCY
0
1
Synchronize
Det
Prescaler
1, 8, 64, 256
1
0
QEIM<2:0>
QExIF
Event
Flag
D
Q
Q
TQGATE
CK
16-bit Up/Down Counter
(POSCNT)
2
Programmable
Digital Filter
QEAx
Reset
Equal
Quadrature
Encoder
Interface Logic
UPDN_SRC
Comparator/
Zero Detect
QEIxCON<11>
0
1
3
QEIM<2:0>
Mode Select
Max Count Register
(MAXCNT)
Programmable
Digital Filter
QEBx
Programmable
Digital Filter
INDXx
3
PCDOUT
Existing Pin Logic
0
UPDNx
Up/Down
1
© 2009 Microchip Technology Inc.
DS70287C-page 191
dsPIC33FJXXXMCX06/X08/X10
REGISTER 17-1: QEIxCON: QEI CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R-0
R/W-0
UPDN
R/W-0
R/W-0
R/W-0
bit 8
CNTERR
QEISIDL
INDEX
QEIM<2:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TQCS
R/W-0
UPDN_SRC
bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS<1:0>
POSRES
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
(CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’)
bit 14
bit 13
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
INDEX: Index Pin State Status bit (Read-Only)
1= Index pin is High
0= Index pin is Low
UPDN: Position Counter Direction Status bit
1= Position Counter direction is positive (+)
0= Position Counter direction is negative (-)
(Read-only bit when QEIM<2:0> = ‘1XX’)
(Read/Write bit when QEIM<2:0> = ‘001’)
bit 10-8
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111= Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match (MAXCNT)
110= Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101= Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match (MAXCNT)
100= Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011= Unused (Module disabled)
010= Unused (Module disabled)
001= Starts 16-bit Timer
000= Quadrature Encoder Interface/Timer off
bit 7
bit 6
bit 5
SWPAB: Phase A and Phase B Input Swap Select bit
1= Phase A and Phase B inputs swapped
0= Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1= Position Counter direction status output enable (QEI logic controls state of I/O pin)
0= Position Counter direction status output disabled (normal I/O pin operation)
TQGATE: Timer Gated Time Accumulation Enable bit
1= Timer gated time accumulation enabled
0= Timer gated time accumulation disabled
DS70287C-page 192
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 17-1: QEIxCON: QEI CONTROL REGISTER (CONTINUED)
bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
(Prescaler utilized for 16-bit timer mode only)
POSRES: Position Counter Reset Enable bit
1= Index Pulse resets Position Counter
0= Index Pulse does not reset Position Counter
(Bit only applies when QEIM<2:0> = 100or 110)
TQCS: Timer Clock Source Select bit
1= External clock from pin QEA (on the rising edge)
0= Internal clock TCY)
bit 2
bit 1
bit 0
UPDN_SRC: Position Counter Direction Selection Control bit
1= QEB pin state defines Position Counter direction
0= Control/status bit UPDN (QEICON<11>) defines Position Counter (POSCNT) direction
Note:
When configured for QEI mode, control bit is a ‘don’t care’.
© 2009 Microchip Technology Inc.
DS70287C-page 193
dsPIC33FJXXXMCX06/X08/X10
REGISTER 17-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CEID
IMV<1:0>
bit 15
bit 8
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
QEOUT
QECK<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits – These bits allow the user to specify the state of the QEAx and
QEBx input pins during an index pulse when the POSxCNT register is to be reset
In 4X Quadrature Count Mode:
IMV1 = Required state of Phase B input signal for match on index pulse
IMV0 = Required state of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1 = Selects phase input signal for index state match (0= Phase A, 1= Phase B)
IMV0 = Required state of the selected Phase input signal for match on index pulse
bit 8
CEID: Count Error Interrupt Disable bit
1= Interrupts due to count errors are disabled
0= Interrupts due to count errors are enabled
bit 7
QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit
1= Digital filter outputs enabled
0= Digital filter outputs disabled (normal pin operation)
bit 6-4
QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits
111= 1:256 Clock Divide
110= 1:128 Clock Divide
101= 1:64 Clock Divide
100= 1:32 Clock Divide
011= 1:16 Clock Divide
010= 1:4 Clock Divide
001= 1:2 Clock Divide
000= 1:1 Clock Divide
bit 3-0
Unimplemented: Read as ‘0’
DS70287C-page 194
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
18.0 SERIAL PERIPHERAL
Note: In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 and SPI2. Special Function Reg-
isters will follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1 or SPI2 module.
INTERFACE (SPI)
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 18.
“Serial Peripheral Interface (SPI)”
(DS70206) in the “dsPIC33F Family
Reference Manual”, which is available
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions.
from
the
Microchip
web
site
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock input
or output) and SSx (active-low slave select).
(www.microchip.com).
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift regis-
ters, display drivers, ADC, etc. The SPI module is
compatible with SPI and SIOP from Motorola®.
In Master mode operation, SCK is a clock output, but in
Slave mode, it is a clock input.
FIGURE 18-1:
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
© 2009 Microchip Technology Inc.
DS70287C-page 195
dsPIC33FJXXXMCX06/X08/X10
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register
0= No overflow has occurred
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started; SPIxTXB is full
0= Transmit started; SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete; SPIxRXB is full
0= Receive is not complete; SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
DS70287C-page 196
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN(3)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
SPRE<2:0>(2)
R/W-0
R/W-0
R/W-0
MSTEN
PPRE<1:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled; pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)(3)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
2: Do not set both the Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
© 2009 Microchip Technology Inc.
DS70287C-page 197
dsPIC33FJXXXMCX06/X08/X10
REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
•
•
•
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
2: Do not set both the Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
DS70287C-page 198
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application
© 2009 Microchip Technology Inc.
DS70287C-page 199
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 200
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
19.1 Operating Modes
19.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 19.
“Inter-Integrated Circuit™ (I2C™)”
(DS70195) in the “dsPIC33F Family
Reference Manual”, which is available
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7 or 10-bit address
from
the
Microchip
web
site
For details about the communication sequence in each
of these modes, please refer to the “dsPIC30F Family
Reference Manual”.
(www.microchip.com).
The Inter-Integrated Circuit (I2C) module, with its 16-bit
interface, provides complete hardware support for both
Slave and Multi-Master modes of the I2C serial commu-
nication standard.
19.2 I2C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
The dsPIC33FJXXXMCX06/X08/X10 devices have up
to two I2C interface modules, denoted as I2C1 and
I2C2. Each I2C module has a 2-pin interface: the SCLx
pin is clock and the SDAx pin is data.
Each I2C module ‘x’ (x = 1 or 2) offers the following key
features:
• I2C interface supports both master and slave
operation.
• I2C Slave mode supports 7- and 10-bit addresses.
• I2C Master mode supports 7- and 10-bit
addresses.
• I2C Port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control).
• I2C supports multi-master operation; it detects
bus collision and will arbitrate accordingly.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
© 2009 Microchip Technology Inc.
DS70287C-page 201
dsPIC33FJXXXMCX06/X08/X10
2
FIGURE 19-1:
I C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSb
Address Match
Match Detect
Write
Read
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
DS70287C-page 202
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1 HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0 HC
ACKEN
R/W-0 HC
RCEN
R/W-0 HC
PEN
R/W-0 HC
RSEN
R/W-0 HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HC = Cleared in hardware
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module. All I2C pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters an Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode disabled
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enable I/O pin thresholds compliant with SMBus specification
0= Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
© 2009 Microchip Technology Inc.
DS70287C-page 203
dsPIC33FJXXXMCX06/X08/X10
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0= Start condition not in progress
DS70287C-page 204
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0 HS
BCL
R-0 HSC
GCSTAT
R-0 HSC
ADD10
ACKSTAT
bit 15
bit 8
R/C-0 HS
IWCOL
R/C-0 HS
I2COV
R-0 HSC
D_A
R/C-0 HSC R/C-0 HSC
R-0 HSC
R_W
R-0 HSC
RBF
R-0 HSC
TBF
P
S
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HSC = Hardware set/cleared
x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
© 2009 Microchip Technology Inc.
DS70287C-page 205
dsPIC33FJXXXMCX06/X08/X10
REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete; I2CxRCV is full
0= Receive not complete; I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70287C-page 206
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSKx: Mask for Address bit x Select bit
1= Enable masking for bit x of incoming message address; bit match not required in this position
0= Disable masking for bit x; bit match required in this position
© 2009 Microchip Technology Inc.
DS70287C-page 207
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 208
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
• Hardware Flow Control Option with UxCTS and
UxRTS pins
20.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Fully Integrated Baud Rate Generator with 16-bit
Prescaler
• Baud rates ranging from 1 Mbps to 15 bps at 16x
mode at 40 MIPS
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 17.
“UART” (DS70188) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
• Baud rates ranging from 4 Mbps to 61 bps at 4x mode
at 40 MIPS
• 4-deep First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the dsPIC33FJXXXMCX06/X08/X10 device
family. The UART is a full-duplex asynchronous system
that can communicate with peripheral devices, such as
personal computers, LIN, RS-232 and RS-485 inter-
faces. The module also supports a hardware flow con-
trol option with the UxCTS and UxRTS pins and also
includes an IrDA® encoder and decoder.
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART is shown in
Figure 20-1. The UART module consists of the key
important hardware elements:
The primary features of the UART module are:
• Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
• Baud Rate Generator
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 20-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UxTX
UART Transmitter
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e.,
UTXISEL<1:0> = 00and URXISEL<1:0> = 00).
© 2009 Microchip Technology Inc.
DS70287C-page 209
dsPIC33FJXXXMCX06/X08/X10
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
R/W-0
RTSMD
UEN<1:0>
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL<1:0>
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA® encoder and decoder enabled
0= IrDA® encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin in Simplex mode
0= UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00= UxTX and UxRX pins are enabled and used; and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (0x55)
before other data; cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70287C-page 210
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
© 2009 Microchip Technology Inc.
DS70287C-page 211
dsPIC33FJXXXMCX06/X08/X10
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
UTXEN(1)
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IREN = 1:
1= IrDA® encoded UxTX Idle state is ‘1’
0= IrDA® encoded UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1= Transmit enabled, UxTX pin controlled by UARTx
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
enabling the UART module for transmit operation.
DS70287C-page 212
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0= Address Detect mode disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0transition) will reset
the receiver buffer and the UxRSR to the empty state
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on
enabling the UART module for transmit operation.
© 2009 Microchip Technology Inc.
DS70287C-page 213
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 214
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
• Programmable link to input capture module (IC2
for both CAN1 and CAN2) for time-stamping and
network synchronization
21.0 ENHANCED CAN (ECAN™)
MODULE
• Low-power Sleep and Idle mode
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 21.
“Enhanced Controller Area Network
(ECAN™)” (DS70185) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
21.1 Overview
21.2 Frame Types
The Enhanced Controller Area Network (ECAN™)
module is a serial interface, useful for communicating
with other CAN modules or microcontroller devices.
This interface/protocol was designed to allow commu-
The CAN module transmits various types of frames
which include data messages, or remote transmission
requests initiated by the user, as other frames that are
automatically generated for control purposes. The
following frame types are supported:
nications
within
noisy
environments.
The
dsPIC33FJXXXMCX06/X08/X10 devices contain up to
two ECAN modules.
• Standard Data Frame:
A standard data frame is generated by a node
when the node wishes to transmit data. It includes
an 11-bit Standard Identifier (SID), but not an
18-bit Extended Identifier (EID).
The CAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module will support CAN 1.2,
CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active
versions of the protocol. The module implementation is
a full CAN system. The CAN specification is not covered
within this data sheet. The reader may refer to the
BOSCH CAN specification for further details.
• Extended Data Frame:
An extended data frame is similar to a standard
data frame, but includes an extended identifier as
well.
• Remote Frame:
The module features are as follows:
It is possible for a destination node to request the
data from the source. For this purpose, the
destination node sends a remote frame with an
identifier that matches the identifier of the required
data frame. The appropriate data source node will
then send a data frame as a response to this
remote request.
• Implementation of the CAN protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Automatic response to remote transmission
requests
• Error Frame:
• Up to eight transmit buffers with application speci-
fied prioritization and abort capability (each buffer
may contain up to 8 bytes of data)
An error frame is generated by any node that
detects a bus error. An error frame consists of two
fields: an error flag field and an error delimiter field.
• Up to 32 receive buffers (each buffer may contain
up to 8 bytes of data)
• Overload Frame:
An overload frame can be generated by a node as
a result of two conditions. First, the node detects a
dominant bit during interframe space which is an
illegal condition. Second, due to internal condi-
tions, the node is not yet able to start reception of
the next message. A node may generate a maxi-
mum of 2 sequential overload frames to delay the
start of the next message.
• Up to 16 full (standard/extended identifier)
acceptance filters
• Three full acceptance filter masks
• DeviceNet™ addressing support
• Programmable wake-up functionality with
integrated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Interframe Space:
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
Interframe space separates a proceeding frame
(of whatever type) from a following data or remote
frame.
• Programmable clock source
© 2009 Microchip Technology Inc.
DS70287C-page 215
dsPIC33FJXXXMCX06/X08/X10
FIGURE 21-1:
ECAN™ MODULE BLOCK DIAGRAM
RXF15 Filter
RXF14 Filter
RXF13 Filter
RXF12 Filter
RXF11 Filter
RXF10 Filter
RXF9 Filter
RXF8 Filter
RXF7 Filter
RXF6 Filter
RXF5 Filter
RXF4 Filter
RXF3 Filter
RXF2 Filter
RXF1 Filter
RXF0 Filter
DMA Controller
TRB7 TX/RX Buffer Control Register
TRB6 TX/RX Buffer Control Register
TRB5 TX/RX Buffer Control Register
TRB4 TX/RX Buffer Control Register
TRB3 TX/RX Buffer Control Register
TRB2 TX/RX Buffer Control Register
TRB1 TX/RX Buffer Control Register
TRB0 TX/RX Buffer Control Register
RXM2 Mask
RXM1 Mask
RXM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
Control
Configuration
Logic
CPU
Bus
CAN Protocol
Engine
Interrupts
CiTX(1) CiRX(1)
Note 1: i = 1 or 2 refers to a particular ECAN™ module (ECAN1 or ECAN2).
DS70287C-page 216
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
21.3 Modes of Operation
Note:
Typically, if the CAN module is allowed to
transmit in a particular mode of operation
and a transmission is requested immedi-
ately after the CAN module has been
placed in that mode of operation, the mod-
ule waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
The CAN module can operate in one of several operation
modes selected by the user. These modes include:
• Initialization Mode
• Disable Mode
• Normal Operation Mode
• Listen Only Mode
• Listen All Messages Mode
• Loopback Mode
Modes are requested by setting the REQOP<2:0> bits
(CiCTRL1<10:8>). Entry into a mode is Acknowledged
21.3.3
NORMAL OPERATION MODE
by
monitoring
the
OPMODE<2:0>
bits
Normal Operation mode is selected when
REQOP<2:0> = 000. In this mode, the module is
activated and the I/O pins will assume the CAN bus
functions. The module will transmit and receive CAN
bus messages via the CiTX and CiRX pins.
(CiCTRL1<7:5>). The module will not change the mode
and the OPMODE bits until a change in mode is
acceptable, generally during bus Idle time, which is
defined as at least 11 consecutive recessive bits.
21.3.1
INITIALIZATION MODE
21.3.4
LISTEN ONLY MODE
In the Initialization mode, the module will not transmit or
receive. The error counters are cleared and the inter-
rupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes. The module will protect the
user from accidentally violating the CAN protocol
through programming errors. All registers which control
the configuration of the module can not be modified
while the module is on-line. The CAN module will not
be allowed to enter the Configuration mode while a
transmission is taking place. The Configuration mode
serves as a lock to protect the following registers:
If the Listen Only mode is activated, the module on the
CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is neces-
sary that there are at least two further nodes that
communicate with each other.
21.3.5
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive
any message. The Listen All Messages mode is acti-
vated by setting REQOP<2:0> = ‘111’. In this mode,
the data which is in the message assembly buffer, until
the time an error occurred, is copied in the receive
buffer and can be read via the CPU interface.
• All Module Control Registers
• Baud Rate and Interrupt Configuration Registers
• Bus Timing Registers
• Identifier Acceptance Filter Registers
• Identifier Acceptance Mask Registers
21.3.2
DISABLE MODE
21.3.6
LOOPBACK MODE
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
If the Loopback mode is activated, the module will con-
nect the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the
module will enter the Module Disable mode. If the module
is active, the module will wait for 11 recessive bits on the
CAN bus, detect that condition as an Idle bus, then
accept the module disable command. When the
OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indi-
cates whether the module successfully went into Module
Disable mode. The I/O pins will revert to normal I/O
function when the module is in the Module Disable mode.
The module can be programmed to apply a low-pass
filter function to the CiRX input line while the module or
the CPU is in Sleep mode. The WAKFIL bit
(CiCFG2<14>) enables or disables the filter.
© 2009 Microchip Technology Inc.
DS70287C-page 217
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-1: CiCTRL1: ECAN™ CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
CSIDL
R/W-0
ABAT
r-0
—
R/W-1
R/W-0
R/W-0
bit 8
REQOP<2:0>
bit 15
R-1
R-0
R-0
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
WIN
OPMODE<2:0>
CANCAP
bit 7
Legend:
bit 0
r = Bit is Reserved
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions
are aborted
bit 11
Reserved: Do no use
bit 10-8
REQOP<2:0>: Request Operation Mode bits
000= Set Normal Operation mode
001= Set Disable mode
010= Set Loopback mode
011= Set Listen Only Mode
100= Set Configuration mode
101= Reserved – do not use
110= Reserved – do not use
111= Set Listen All Messages mode
bit 7-5
OPMODE<2:0>: Operation Mode bits
000= Module is in Normal Operation mode
001= Module is in Disable mode
010= Module is in Loopback mode
011= Module is in Listen Only mode
100= Module is in Configuration mode
101= Reserved
110= Reserved
111= Module is in Listen All Messages mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CANCAP: CAN Message Receive Timer Capture Event Enable bit
1= Enable input capture based on CAN message receive
0= Disable CAN capture
bit 2-1
bit 0
Unimplemented: Read as ‘0’
WIN: SFR Map Window Select bit
1= Use filter window
0= Use buffer window
DS70287C-page 218
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-2: CiCTRL2: ECAN™ CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
DNCNT<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111= Invalid selection
10001= Compare up to data byte 3, bit 6 with EID<17>
....
00001= Compare up to data byte 1, bit 7 with EID<0>
00000= Do not compare data bytes
© 2009 Microchip Technology Inc.
DS70287C-page 219
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FILHIT<4:0>
bit 15
bit 8
bit 0
U-0
—
R-1
R-0
R-0
R-0
R-0
ICODE<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Number bits
10000-11111= Reserved
01111= Filter 15
....
00001= Filter 1
00000= Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111= Reserved
1000100= FIFO almost full interrupt
1000011= Receiver overflow interrupt
1000010= Wake-up interrupt
1000001= Error interrupt
1000000= No interrupt
0010000-0111111= Reserved
0001111= RB15 buffer Interrupt
....
0001001= RB9 buffer interrupt
0001000= RB8 buffer interrupt
0000111= TRB7 buffer interrupt
0000110= TRB6 buffer interrupt
0000101= TRB5 buffer interrupt
0000100= TRB4 buffer interrupt
0000011= TRB3 buffer interrupt
0000010= TRB2 buffer interrupt
0000001= TRB1 buffer interrupt
0000000= TRB0 Buffer interrupt
DS70287C-page 220
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMABS<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
FSA<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
DMABS<2:0>: DMA Buffer Size bits
111= Reserved
110= 32 buffers in DMA RAM
101= 24 buffers in DMA RAM
100= 16 buffers in DMA RAM
011= 12 buffers in DMA RAM
010= 8 buffers in DMA RAM
001= 6 buffers in DMA RAM
000= 4 buffers in DMA RAM
bit 12-5
bit 4-0
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Area Starts with Buffer bits
11111= RB31 buffer
11110= RB30 buffer
....
00001= TRB1 buffer
00000= TRB0 buffer
© 2009 Microchip Technology Inc.
DS70287C-page 221
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-5: CiFIFO: ECAN™ FIFO STATUS REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FBP<5:0>
R-0
R-0
R-0
R-0
bit 15
bit 8
bit 0
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FNRB<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FBP<5:0>: FIFO Write Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
....
000001= TRB1 buffer
000000= TRB0 buffer
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
....
000001= TRB1 buffer
000000= TRB0 buffer
DS70287C-page 222
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
bit 15
bit 8
R/C-0
IVRIF
R/C-0
R/C-0
U-0
—
R/C-0
R/C-0
R/C-0
RBIF
R/C-0
TBIF
WAKIF
ERRIF
FIFOIF
RBOVIF
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
Unimplemented: Read as ‘0’
TXBO: Transmitter in Error State Bus Off bit
TXBP: Transmitter in Error State Bus Passive bit
RXBP: Receiver in Error State Bus Passive bit
TXWAR: Transmitter in Error State Warning bit
RXWAR: Receiver in Error State Warning bit
EWARN: Transmitter or Receiver in Error State Warning bit
IVRIF: Invalid Message Received Interrupt Flag bit
WAKIF: Bus Wake-up Activity Interrupt Flag bit
ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)
Unimplemented: Read as ‘0’
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
FIFOIF: FIFO Almost Full Interrupt Flag bit
RBOVIF: RX Buffer Overflow Interrupt Flag bit
RBIF: RX Buffer Interrupt Flag bit
bit 2
bit 1
bit 0
TBIF: TX Buffer Interrupt Flag bit
© 2009 Microchip Technology Inc.
DS70287C-page 223
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IVRIE
R/W-0
R/W-0
ERRIE
U-0
—
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
TBIE
WAKIE
FIFOIE
RBOVIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Received Interrupt Enable bit
WAKIE: Bus Wake-up Activity Interrupt Flag bit
ERRIE: Error Interrupt Enable bit
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
RBOVIE: RX Buffer Overflow Interrupt Enable bit
RBIE: RX Buffer Interrupt Enable bit
TBIE: TX Buffer Interrupt Enable bit
DS70287C-page 224
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-8: CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT<7:0>
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RERRCNT<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
TERRCNT<7:0>: Transmit Error Count bits
RERRCNT<7:0>: Receive Error Count bits
© 2009 Microchip Technology Inc.
DS70287C-page 225
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW<1:0>
BRP<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
SJW<1:0>: Synchronization Jump Width bits
11= Length is 4 x TQ
10= Length is 3 x TQ
01= Length is 2 x TQ
00= Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
11 1111= TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010= TQ = 2 x 3 x 1/FCAN
00 0001= TQ = 2 x 2 x 1/FCAN
00 0000= TQ = 2 x 1 x 1/FCAN
DS70287C-page 226
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2
U-0
—
R/W-x
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
WAKFIL
SEG2PH<2:0>
bit 15
R/W-x
R/W-x
SAM
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SEG1PH<2:0>
PRSEG<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
WAKFIL: Select CAN bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 13-11
bit 10-8
Unimplemented: Read as ‘0’
SEG2PH<2:0>: Phase Buffer Segment 2 bits
111= Length is 8 x TQ
000= Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1= Bus line is sampled three times at the sample point
0= Bus line is sampled once at the sample point
bit 5-3
bit 2-0
SEG1PH<2:0>: Phase Buffer Segment 1 bits
111= Length is 8 x TQ
000= Length is 1 x TQ
PRSEG<2:0>: Propagation Time Segment bits
111= Length is 8 x TQ
000= Length is 1 x TQ
© 2009 Microchip Technology Inc.
DS70287C-page 227
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10
FLTEN9
FLTEN8
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN7
FLTEN6
FLTEN5
FLTEN4
FLTEN3
FLTEN2
FLTEN1
FLTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
FLTENn: Enable Filter n to Accept Messages bits
1= Enable Filter n
0= Disable Filter n
REGISTER 21-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F3BP<3:0>
F2BP<3:0>
R/W-0
F1BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F0BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits
F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits
F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits
F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits
bit 3-0
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
....
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
DS70287C-page 228
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F7BP<3:0>
F6BP<3:0>
R/W-0
F5BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F4BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits
F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits
F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits
F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits
bit 3-0
REGISTER 21-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F11BP<3:0>
F10BP<3:0>
R/W-0
F9BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F8BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits
F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits
F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits
F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits
bit 3-0
© 2009 Microchip Technology Inc.
DS70287C-page 229
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F15BP<3:0>
F14BP<3:0>
R/W-0
F13BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F12BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits
F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits
F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits
F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits
bit 3-0
DS70287C-page 230
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1,
...,15)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Message address bit SIDx must be ‘1’ to match filter
0= Message address bit SIDx must be ‘0’ to match filter
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDE: Extended Identifier Enable bit
If MIDE = 1then:
1= Match only messages with extended identifier addresses
0= Match only messages with standard identifier addresses
If MIDE = 0then:
Ignore EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
REGISTER 21-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER n EXTENDED IDENTIFIER (n = 0, 1, ...,
15)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
© 2009 Microchip Technology Inc.
DS70287C-page 231
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK<1:0>
F6MSK<1:0>
F5MSK<1:0>
F4MSK<1:0>
bit 15
bit 8
R/W-0 R/W-0
F3MSK<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F2MSK<1:0>
F1MSK<1:0>
F0MSK<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
bit 11-10
bit 9-8
F7MSK<1:0>: Mask Source for Filter 7 bit
F6MSK<1:0>: Mask Source for Filter 6 bit
F5MSK<1:0>: Mask Source for Filter 5 bit
F4MSK<1:0>: Mask Source for Filter 4 bit
F3MSK<1:0>: Mask Source for Filter 3 bit
F2MSK<1:0>: Mask Source for Filter 2 bit
F1MSK<1:0>: Mask Source for Filter 1 bit
F0MSK<1:0>: Mask Source for Filter 0 bit
11= Reserved
bit 7-6
bit 5-4
bit 3-2
bit 1-0
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
DS70287C-page 232
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK<1:0>
F14MSK<1:0>
F13MSK<1:0>
F12MSK<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK<1:0>
F10MSK<1:0>
F9MSK<1:0>
F8MSK<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
F15MSK<1:0>: Mask Source for Filter 15 bit
11= Reserved
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14)
F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14)
F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14)
F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14)
F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14)
F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14)
F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
© 2009 Microchip Technology Inc.
DS70287C-page 233
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
MIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Include bit SIDx in filter comparison
0= Bit SIDx is don’t care in filter comparison
bit 4
bit 3
Unimplemented: Read as ‘0’
MIDE: Identifier Receive Mode bit
1= Match only message types (standard or extended address) that correspond to EXIDE bit in filter
0= Match either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
REGISTER 21-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
DS70287C-page 234
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL15
RXFUL14
RXFUL13
RXFUL12
RXFUL11
RXFUL10
RXFUL9
RXFUL8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL7
RXFUL6
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
RXFUL0
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<15:0>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (clear by application software)
REGISTER 21-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL31
RXFUL30
RXFUL29
RXFUL28
RXFUL27
RXFUL26
RXFUL25
RXFUL24
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL23
RXFUL22
RXFUL21
RXFUL20
RXFUL19
RXFUL18
RXFUL17
RXFUL16
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<31:16>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (clear by application software)
© 2009 Microchip Technology Inc.
DS70287C-page 235
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<15:0>: Receive Buffer n Overflow bits
1= Module pointed a write to a full buffer (set by module)
0= Overflow is cleared (clear by application software)
REGISTER 21-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
RXOVF26
RXOVF25
RXOVF24
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
RXOVF18
RXOVF17
RXOVF16
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<31:16>: Receive Buffer n Overflow bits
1= Module pointed a write to a full buffer (set by module)
0= Overflow is cleared (clear by application software)
DS70287C-page 236
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n =
1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI<1:0>
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm
RTRENm
TXmPRI<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1= Buffer TRBn is a transmit buffer
0= Buffer TRBn is a receive buffer
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXABTm: Message Aborted bit(1)
1= Message was aborted
0= Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit(1)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit(1)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message
is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.
RTRENm: Auto-Remote Transmit Enable bit
1= When a remote transmit is received, TXREQ will be set
0= When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11= Highest message priority
10= High intermediate message priority
01= Low intermediate message priority
00= Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
© 2009 Microchip Technology Inc.
DS70287C-page 237
dsPIC33FJXXXMCX06/X08/X10
Note:
The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.
REGISTER 21-27: CiTRBnSID: ECAN™ BUFFER n STANDARD IDENTIFIER (n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
bit 15
bit 8
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
IDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SID<10:0>: Standard Identifier bits
SRR: Substitute Remote Request bit
1= Message will request remote transmission
0= Normal message
bit 0
IDE: Extended Identifier bit
1= Message will transmit extended identifier
0= Message will transmit standard identifier
REGISTER 21-28: CiTRBnEID: ECAN™ BUFFER n EXTENDED IDENTIFIER (n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
EID17
R/W-x
EID16
R/W-x
EID15
R/W-x
EID14
bit 15
bit 8
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
R/W-x
EID7
R/W-x
EID6
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
EID<17:6>: Extended Identifier bits
DS70287C-page 238
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-29: CiTRBnDLC: ECAN™ BUFFER n DATA LENGTH CONTROL (n = 0, 1, ..., 31)
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
R/W-x
RTR
R/W-x
RB1
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
1= Message will request remote transmission
0= Normal message
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
bit 7-5
bit 4
RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
bit 3-0
REGISTER 21-30: CiTRBnDm: ECAN
™ BUFFER n DATA FIELD BYTE m (n = 0, 1, ..., 31; m = 0, 1, ...,
(1)
7)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TRBnDm7
TRBnDm6
TRBnDm5
TRBnDm4 TRBnDm3
TRBnDm2
TRBnDm1
TRBnDm0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
Note 1: The Most Significant Byte contains byte (m + 1) of the buffer.
TRBnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits
© 2009 Microchip Technology Inc.
DS70287C-page 239
dsPIC33FJXXXMCX06/X08/X10
REGISTER 21-31: CiTRBnSTAT: ECAN™ RECEIVE BUFFER n STATUS (n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers)
Encodes number of filter that resulted in writing this buffer.
Unimplemented: Read as ‘0’
bit 7-0
DS70287C-page 240
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
log input pins. The actual number of analog input pins
and external voltage reference input configuration will
depend on the specific device. Refer to the device data
sheet for further details.
22.0 10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
A block diagram of the ADC is shown in Figure 22-1.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 16.
“Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F Family
Reference Manual”, which is available
22.2 ADC Initialization
The following configuration steps should be performed.
1. Configure the ADC module:
a) Select port pins as analog inputs
(ADxPCFGH<15:0> or ADxPCFGL<15:0>)
b) Select voltage reference source to match
expected range on analog inputs
(ADxCON2<15:13>)
from
the
Microchip
web
site
(www.microchip.com).
The dsPIC33FJXXXMCX06/X08/X10 devices have up
to 32 ADC input channels. These devices also have up
to 2 ADC modules (ADCx, where ‘x’ = 1 or 2), each with
its own set of Special Function Registers.
c) Select the analog conversion clock to
match desired data rate with processor
clock (ADxCON3<7:0>)
d) Determine how many S/H channels will be
used
(ADxCON2<9:8>
and
The AD12B bit (ADxCON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
ADxPCFGH<15:0> or ADxPCFGL<15:0>)
e) Select the appropriate sample/conversion
sequence
(ADxCON1<7:5>
and
ADxCON3<12:8>)
Note:
The ADC module needs to be disabled
before modifying the AD12B bit.
f) Select how conversion results are
presented in the buffer (ADxCON1<9:8>)
g) Turn on ADC module (ADxCON1<15>)
2. Configure ADC interrupt (if required):
a) Clear the ADxIF bit
22.1 Key Features
The 10-bit ADC configuration has the following key
features:
b) Select ADC interrupt priority
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
22.3 ADC and DMA
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. Both ADC1 and ADC2 can trigger a DMA data
transfer. If ADC1 or ADC2 is selected as the DMA IRQ
source, a DMA transfer occurs when the AD1IF or
AD2IF bit gets set as a result of an ADC1 or ADC2
sample conversion sequence.
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
The SMPI<3:0> bits (ADxCON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
The ADDMABM bit (ADxCON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module will
provide an address to the DMA channel that is the
same as the address used for the non-DMA
stand-alone buffer. If the ADDMABM bit is cleared, then
DMA buffers are written in Scatter/Gather mode. The
module will provide a scatter/gather address to the
DMA channel, based on the index of the analog input
and the size of the DMA buffer.
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only 1 sample/hold amplifier in the 12-bit
configuration, so simultaneous sampling of
multiple channels is not supported.
Depending on the particular device pinout, the ADC
can have up to 32 analog input pins, designated AN0
through AN31. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs may be shared with other ana-
© 2009 Microchip Technology Inc.
DS70287C-page 241
dsPIC33FJXXXMCX06/X08/X10
FIGURE 22-1:
ADC1 MODULE BLOCK DIAGRAM
AN0
(3)
ANy
CHANNEL
S/H0
+
SCAN
CH0SB<4:0>
-
CH0SA<4:0>
CH0
CSCNA
AN1
VREF-
CH0NB
CH0NA
(1)
(1)
VREF+
AVDD
VREF-
AVSS
AN0
AN3
S/H1
+
-
CH123SA
CH123SB
(2)
CH1
AN6
AN9
VREF-
VREFH
VREFL
CH123NB
CH123NA
ADC1BUF0
SAR ADC
AN1
AN4
S/H2
+
-
CH123SA
CH123SB
(2)
CH2
AN7
AN10
VREF-
CH123NA
CH123NB
AN2
AN5
S/H3
+
-
CH123SA CH123SB
AN8
(2)
CH3
AN11
VREF-
CH123NA
CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: For 64-pin devices, y = 15; for 80-pin devices, y = 17; for 100-pin devices, y = 23; for ADC2, y = 15.
DS70287C-page 242
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADxCON3<15>
ADC Internal
RC Clock(2)
0
1
TAD
ADxCON3<5:0>
6
ADC Conversion
Clock Multiplier
TCY
(1)
X2
TOSC
1, 2, 3, 4, 5,..., 64
Note 1: Refer to Figure 9-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source
frequency. TOSC = 1/FOSC.
2: See the ADC electrical specifications for the exact RC clock value.
© 2009 Microchip Technology Inc.
DS70287C-page 243
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2)
R/W-0
ADON
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
ADDMABM
AD12B
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
ASAM
R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0>
SIMSAM
SAMP
DONE
bit 7
Legend:
bit 0
HC = Cleared by hardware
W = Writable bit
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ADDMABM: DMA Buffer Build Mode bit
1= DMA buffers are written in the order of conversion. The module will provide an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0= DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address
to the DMA channel, based on the index of the analog input and the size of the DMA buffer
bit 11
bit 10
Unimplemented: Read as ‘0’
AD12B: 10-Bit or 12-Bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11= Signed fractional (DOUT = sddd dddd dd00 0000, where s= .NOT.d<9>)
10= Fractional (DOUT = dddd dddd dd00 0000)
01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11= Signed fractional (DOUT = sddd dddd dddd 0000, where s= .NOT.d<11>)
10= Fractional (DOUT = dddd dddd dddd 0000)
01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto-convert)
110= Reserved
101= Reserved
100= Reserved
011= MPWM interval ends sampling and starts conversion
010= GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
Unimplemented: Read as ‘0’
DS70287C-page 244
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) (continued)
bit 3
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
bit 2
bit 1
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set
0= Sampling begins when SAMP bit is set
SAMP: ADC Sample Enable bit
1= ADC sample/hold amplifiers are sampling
0= ADC sample/hold amplifiers are holding
If ASAM = 0, software may write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software may write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed
0= ADC conversion not started or in progress
Automatically set by hardware when ADC conversion is complete. Software may write ‘0’ to clear
DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
© 2009 Microchip Technology Inc.
DS70287C-page 245
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-2: ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2)
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VCFG<2:0>
CSCNA
CHPS<1:0>
bit 15
bit 8
R-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
R/W-0
ALTS
BUFS
SMPI<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
VCFG<2:0>: Converter Voltage Reference Configuration bits
VREF+
VREF-
000
001
010
011
1xx
AVDD
External VREF+
AVDD
Avss
Avss
External VREF-
External VREF-
Avss
External VREF+
AVDD
bit 12-11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Selects Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x= Converts CH0, CH1, CH2 and CH3
01= Converts CH0 and CH1
00= Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1= ADC is currently filling second half of buffer, user should access data in the first half
0= ADC is currently filling first half of buffer, user should access data in the second half
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion
operations per interrupt
1111= Increments the DMA address or generates interrupt after completion of every 16th
sample/conversion operation
1110= Increments the DMA address or generates interrupt after completion of every 15th
sample/conversion operation
•
•
•
0001= Increments the DMA address or generates interrupt after completion of every 2nd
sample/conversion operation
0000= Increments the DMA address or generates interrupt after completion of every
sample/conversion operation
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0= Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
DS70287C-page 246
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-3: ADxCON3: ADCx CONTROL REGISTER 3
R/W-0
ADRC
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
R/W-0
R/W-0
bit 8
R/W-0
bit 0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADRC: ADC Conversion Clock Source bit
1= ADC internal RC clock
0= Clock derived from system clock
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits(1)
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111= Reserved
•
•
•
01000000= Reserved
00111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD
•
•
•
00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
Note 1: This bit only used if ADxCON1<SSRC> = 1.
2: This bit is not used if ADxCON3<ADRC> = 1.
© 2009 Microchip Technology Inc.
DS70287C-page 247
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-4: ADxCON4: ADCx CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
DMABL<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111= Allocates 128 words of buffer to each analog input
110= Allocates 64 words of buffer to each analog input
101= Allocates 32 words of buffer to each analog input
100= Allocates 16 words of buffer to each analog input
011= Allocates 8 words of buffer to each analog input
010= Allocates 4 words of buffer to each analog input
001= Allocates 2 words of buffer to each analog input
000= Allocates 1 word of buffer to each analog input
DS70287C-page 248
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NB<1:0>
CH123SB
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NA<1:0>
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x= CH1, CH2, CH3 negative input is VREF-
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
When AD12B = 1, CHxSB is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
bit 2-1
Unimplemented: Read as ‘0’
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x= CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
© 2009 Microchip Technology Inc.
DS70287C-page 249
dsPIC33FJXXXMCX06/X08/X10
REGISTER 22-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
CH0NB
CH0SB<4:0>
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH0NA
CH0SA<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
Same definition as bit<4:0>.
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 6-5
bit 4-0
Unimplemented: Read as ‘0’
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
11111= Channel 0 positive input is AN31
11110= Channel 0 positive input is AN30
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
Note:
ADC2 can only select AN0-AN15 as positive inputs.
DS70287C-page 250
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
(1,2)
REGISTER 22-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS<31:16>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 32 analog inputs, all ADxCSSH bits may be selected by user. However, inputs selected
for scan without a corresponding input on device will convert VREFL.
2: CSSx = ANx, where x = 16 through 31.
(1,2)
REGISTER 22-8: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS9
R/W-0
CSS8
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
bit 15
bit 8
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS<15:0>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs selected
for scan without a corresponding input on device will convert VREFL.
2: CSSx = ANx, where x = 0 through 15.
© 2009 Microchip Technology Inc.
DS70287C-page 251
dsPIC33FJXXXMCX06/X08/X10
(1,2,3)
REGISTER 22-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG31
PCFG30
PCFG29
PCFG28
PCFG27
PCFG26
PCFG25
PCFG24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19
PCFG18
PCFG17
PCFG16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PCFG<31:16>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 port Configuration register exists.
3: PCFGx = ANx, where x = 16 through 31.
(1,2,3)
REGISTER 22-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PCFG<15:0>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: On devices with two analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the
configuration of port pins multiplexed with AN0-AN15.
3: PCFGx = ANx, where x = 0 through 15.
DS70287C-page 252
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
23.1 Configuration Bits
23.0 SPECIAL FEATURES
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 23.
“CodeGuard™ Security” (DS70199),
The device Configuration register map is shown in
Table 23-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
Section
24.
“Programming
and
Diagnostics” (DS70207), and Section
25. “Device Configuration” (DS70194)
in the “dsPIC33F Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
dsPIC33FJXXXMCX06/X08/X10 devices include sev-
eral features intended to maximize application flexibility
and reliability, and minimize cost through elimination of
external components. These are:
The upper byte of all device Configuration registers
should always be ‘1111 1111’. This makes them
appear to be NOPinstructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
TABLE 23-1: DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
RBS<1:0>
RSS<1:0>
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000 FBS
—
—
—
BSS<2:0>
SSS<2:0>
GSS1
BWRP
SWRP
0xF80002 FSS
—
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
—
—
—
—
—
—
—
GSS0 GWRP
FNOSC<2:0>
IESO
Reserved(2)
—
—
FCKSM<1:0>
—
—
WDTPRE
—
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
FWDTEN
WINDIS
—
PWMPIN
HPOL
LPOL
JTAGEN
—
—
FPWRT<2:0>
Reserved(1)
—
—
ICS<1:0>
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Note 1: When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.
2: When read, this bit returns the current programmed value.
© 2009 Microchip Technology Inc.
DS70287C-page 253
dsPIC33FJXXXMCX06/X08/X10
TABLE 23-2: dsPIC33FJXXXMCX06/X08/X10 CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
BWRP
FBS
Boot Segment Program Flash Write Protection
1= Boot segment may be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 1K IW less VS
110= Standard security; boot program Flash segment starts at End of
VS, ends at 0007FEh
010= High security; boot program Flash segment starts at End of VS,
ends at 0007FEh
Boot space is 4K IW less VS
101= Standard security; boot program Flash segment starts at End of
VS, ends at 001FFEh
001= High security; boot program Flash segment starts at End of VS,
ends at 001FFEh
Boot space is 8K IW less VS
100= Standard security; boot program Flash segment starts at End of
VS, ends at 003FFEh
000= High security; boot program Flash segment starts at End of VS,
ends at 003FFEh
RBS<1:0>
SWRP
FBS
FSS
Boot Segment RAM Code Protection
11= No Boot RAM defined
10= Boot RAM is 128 Bytes
01= Boot RAM is 256 Bytes
00= Boot RAM is 1024 Bytes
Secure Segment Program Flash Write Protection
1= Secure segment may be written
0= Secure segment is write-protected
DS70287C-page 254
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 23-2: dsPIC33FJXXXMCX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
SSS<2:0>
FSS
Secure Segment Program Flash Code Protection Size
(FOR 128K and 256K DEVICES)
X11= No Secure program Flash segment
Secure space is 8K IW less BS
110= Standard security; secure program Flash segment starts at End
of BS, ends at 0x003FFE
010= High security; secure program Flash segment starts at End of
BS, ends at 0x003FFE
Secure space is 16K IW less BS
101= Standard security; secure program Flash segment starts at End
of BS, ends at 0x007FFE
001= High security; secure program Flash segment starts at End of
BS, ends at 0x007FFE
Secure space is 32K IW less BS
100= Standard security; secure program Flash segment starts at End
of BS, ends at 0x00FFFE
000= High security; secure program Flash segment starts at End of
BS, ends at 0x00FFFE
(FOR 64K DEVICES)
X11= No Secure program Flash segment
Secure space is 4K IW less BS
110= Standard security; secure program Flash segment starts at End
of BS, ends at 0x001FFE
010= High security; secure program Flash segment starts at End of
BS, ends at 0x001FFE
Secure space is 8K IW less BS
101= Standard security; secure program Flash segment starts at End
of BS, ends at 0x003FFE
001= High security; secure program Flash segment starts at End of
BS, ends at 0x003FFE
Secure space is 16K IW less BS
100= Standard security; secure program Flash segment starts at End
of BS, ends at 007FFEh
000= High security; secure program Flash segment starts at End of
BS, ends at 0x007FFE
RSS<1:0>
GSS<1:0>
FSS
FGS
Secure Segment RAM Code Protection
11= No Secure RAM defined
10= Secure RAM is 256 Bytes less BS RAM
01= Secure RAM is 2048 Bytes less BS RAM
00= Secure RAM is 4096 Bytes less BS RAM
General Segment Code-Protect bit
11= User program memory is not code-protected
10= Standard security; general program Flash segment starts at End
of SS, ends at EOM
0x= High security; general program Flash segment starts at End of SS,
ends at EOM
© 2009 Microchip Technology Inc.
DS70287C-page 255
dsPIC33FJXXXMCX06/X08/X10
TABLE 23-2: dsPIC33FJXXXMCX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
GWRP
FGS
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
IESO
FOSCSEL
FOSCSEL
Two-speed Oscillator Start-up Enable bit
1= Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start-up device with user-selected oscillator source
FNOSC<2:0>
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator with postscaler
110= Internal Fast RC (FRC) oscillator with divide-by-16
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= FRC oscillator
FCKSM<1:0>
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFNC
FOSC
FOSC
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
FWDTEN
FWDT
Watchdog Timer Enable bit
1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
WDTPRE
WDTPOST
FWDT
FWDT
FWDT
Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
.
.
.
0001= 1:2
0000= 1:1
PWMPIN
FPOR
Motor Control PWM Module Pin Mode bit
1= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
DS70287C-page 256
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 23-2: dsPIC33FJXXXMCX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
HPOL
FPOR
Motor Control PWM High Side Polarity bit
1= PWM module high side output pins have active-high output polarity
0= PWM module high side output pins have active-low output polarity
LPOL
FPOR
FPOR
Motor Control PWM Low Side Polarity bit
1= PWM module low side output pins have active-high output polarity
0= PWM module low side output pins have active-low output polarity
FPWRT<2:0>
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
JTAGEN
ICS<1:0>
FICD
FICD
JTAG Enable bits
1= JTAG enabled
0= JTAG disabled
ICD Communication Channel Select bits
11= Communicate on PGEC1 and PGED1
10= Communicate on PGEC2 and PGED2
01= Communicate on PGEC3 and PGED3
00= Reserved
© 2009 Microchip Technology Inc.
DS70287C-page 257
dsPIC33FJXXXMCX06/X08/X10
23.2 On-Chip Voltage Regulator
23.3 BOR: Brown-Out Reset
All of the dsPIC33FJXXXMCX06/X08/X10 devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify system design, all devices in the
dsPIC33FJXXXMCX06/X08/X10 family incorporate an
on-chip regulator that allows the device to run its core
logic from VDD.
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the
regulated supply voltage VCAP/VDDCORE. The main
purpose of the BOR module is to generate a device
Reset when a brown-out condition occurs. Brown-out
conditions are generally caused by glitches on the AC
mains (i.e., missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
The regulator provides power to the core from the other
VDD pins. The regulator requires that a low-ESR (less
than 5 ohms) capacitor (such as tantalum or ceramic)
be connected to the VCAP/VDDCORE pin (Figure 23-1).
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Table 26-13 of Section 26.1 “DC Characteristics”.
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If TPWRT
= 0 and a crystal oscillator is being used, then a
nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold
voltage.
FIGURE 23-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
(1)
3.3V
dsPIC33F
VDD
VCAP/VDDCORE
VSS
CEFC
Note 1: These are typical operating voltages. Refer to
TABLE 26-13: “Internal Voltage Regulator
Specifications” located in Section 26.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP/VDDCORE.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
DS70287C-page 258
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
If the WDT is enabled, it will continue to run during Sleep
23.4 Watchdog Timer (WDT)
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will con-
tinue from where the PWRSAVinstruction was executed.
The corresponding SLEEP or IDLE bits (RCON<3,2>) will
need to be cleared in software after the device wakes up.
For dsPIC33FJXXXMCX06/X08/X10 devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>) which allow the selec-
tion of a total of 16 settings, from 1:1 to 1:32,768. Using
the prescaler and postscaler, time-out periods ranging
from 1 ms to 131 seconds can be achieved.
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN con-
trol bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for crit-
ical code segments and disable the WDT during
non-critical segments for maximum power savings.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
Note:
If the WINDIS bit (FWDT<6>) is cleared, the
CLRWDTinstruction should be executed by
the application software only during the last
1/4 of the WDT period. This CLRWDT win-
dow can be determined by using a timer. If
a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
FIGURE 23-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPRE
Prescaler
WDTPOST<3:0>
SWDTEN
FWDTEN
WDT
Wake-up
1
0
RS
RS
Postscaler
WDT
Reset
(divide by N1)
(divide by N2)
LPRC Clock
WDT Window Select
WINDIS
CLRWDTInstruction
© 2009 Microchip Technology Inc.
DS70287C-page 259
dsPIC33FJXXXMCX06/X08/X10
23.5 JTAG Interface
23.8 In-Circuit Debugger
dsPIC33FJXXXMCX06/X08/X10 devices implement a
JTAG interface, which supports boundary scan device
testing, as well as in-circuit programming. Detailed
information on the interface will be provided in future
revisions of the document.
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
23.6 Code Protection and
CodeGuard™ Security
Any one out of three pairs of debugging clock/data pins
may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
The dsPIC33FJXXXMCX06/X08/X10 devices offer the
advanced implementation of CodeGuard™ Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
designs.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IP are resident on the single
chip. The code protection features vary depending on
the actual device implemented. The following sections
provide an overview of these features.
The code protection features are controlled by the
Configuration registers: FBS, FSS and FGS.
Note:
Refer to Section 23. “CodeGuard™
Security” (DS70199) in the “dsPIC33F
Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.
23.7
In-Circuit Serial Programming
dsPIC33FJXXXMCX06/X08/X10 family digital signal
controllers can be serially programmed while in the end
application circuit. This is simply done with two lines for
clock and data and three other lines for power, ground
and the programming sequence. This allows
customers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware, to be
programmed. Please refer to the “dsPIC33F/PIC24H
Flash
Programming
Specification”
(DS70152)
document for details about ICSP.
Any one out of three pairs of programming clock/data
pins may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS70287C-page 260
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
24.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the related section
in the “dsPIC33F Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The first source operand which is a register ‘Wb’
without any address modifier
• The second source operand which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories:
• The destination of the result (only if not the same
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions may use some of the
following operands:
• DSP operations
• The accumulator (A or B) to be used (required
operand)
• Control operations
Table 24-1 shows the general symbols used in
describing the instructions.
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The dsPIC33F instruction set summary in Table 24-2
lists all the instructions, along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication and may include:
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is typically a
register ‘Ws’ with or without an address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
The control instructions may use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands:
• A program memory address
• The mode of the table read and table write
instructions
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
© 2009 Microchip Technology Inc.
DS70287C-page 261
dsPIC33FJXXXMCX06/X08/X10
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all the required infor-
mation is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
Note:
For more details on the instruction set,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double-Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator write back destination address register ∈ {W13, [W13]+ = 2}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
C, DC, N, OV, Z
Expr
f
lit1
1-bit unsigned literal ∈ {0,1}
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
lit14
lit16
16-bit unsigned literal ∈ {0...65535}
lit23
23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’
Field does not require an entry, may be blank
DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
Program Counter
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
Wb
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Dividend, Divisor working register pair (direct addressing)
Wdo
Wm,Wn
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
DS70287C-page 262
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0...W15}
One of 16 source working registers ∈ {W0...W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
∈ {[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2,
[W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2,
[W9 + W12], none}
Wxd
Wy
X data space prefetch destination register for DSP instructions ∈ {W4...W7}
Y data space prefetch address register for DSP instructions
∈ {[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2,
[W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions ∈ {W4...W7}
© 2009 Microchip Technology Inc.
DS70287C-page 263
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
16-bit Signed Add to Accumulator
f = f + WREG + (C)
1
2
3
4
ADDC
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
AND
f = f .AND. WREG
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
1
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
Wd = Wb .AND. Ws
1
N,Z
Wd = Wb .AND. lit5
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N,Z
5
6
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
None
None
None
None
None
None
None
Branch if unsigned less than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Accumulator A overflow
Branch if Accumulator B overflow
Branch if Overflow
None
None
None
Branch if Accumulator A saturated
Branch if Accumulator B saturated
Branch Unconditionally
Branch if Zero
None
None
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
7
8
9
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
1
None
Bit Toggle Ws
1
None
DS70287C-page 264
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
10
BTSC
BTSS
BTST
BTSC
BTSC
BTSS
BTSS
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test f, Skip if Clear
1
1
1
1
1
None
None
None
None
(2 or 3)
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
(2 or 3)
11
12
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
C
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Ws,Wb
Z
13
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ≠
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
DEC
Wd = Ws – 1
27
28
DEC2
DISI
DEC2
DEC2
DEC2
DISI
f = f – 2
f,WREG
Ws,Wd
#lit14
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k instruction cycles
© 2009 Microchip Technology Inc.
DS70287C-page 265
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
29
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
Wm,Wn
Signed 16/16-bit Integer Divide
1
1
1
1
1
2
2
1
18
18
18
18
18
2
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
Wm,Wn
Signed 32/16-bit Integer Divide
Wm,Wn
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit14 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
DO
2
None
32
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link Frame Pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f
f = Logical Right Shift f
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate
,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
None
None
None
None
N,Z
MOV.b
MOV
MOV
Wso,Wdo
Move Ws to Wd
MOV
WREG,f
Move WREG to f
MOV.D
MOV.D
MOVSAC
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Prefetch and store accumulator
None
None
None
Ws,Wnd
47
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
DS70287C-page 266
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
48
MPY
MPY
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
1
1
1
1
1
1
1
1
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
OA,OB,OAB,
SA,SB,SAB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
49
50
MPY.N
MSC
MPY.N
-(Multiply Wm by Wn) to Accumulator
None
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
,
AWB
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
52
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
All
None
None
None
None
WDTO,Sleep
None
None
None
None
None
None
None
None
C,N,Z
C,N,Z
C,N,Z
N,Z
55
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
1
PUSH
Wso
Wns
1
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
2
1
56
57
PWRSAV
RCALL
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
2
Computed Call
2
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
1
1
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
1
Return from interrupt
3 (2)
#lit10,Wn
Return with literal in Wn
3 (2)
Return from Subroutine
3 (2)
1
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
RLC
f,WREG
Ws,Wd
f
1
RLC
1
64
65
RLNC
RRC
RLNC
1
RLNC
f,WREG
Ws,Wd
f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
1
N,Z
RLNC
1
N,Z
RRC
1
C,N,Z
C,N,Z
C,N,Z
RRC
f,WREG
Ws,Wd
1
RRC
1
© 2009 Microchip Technology Inc.
DS70287C-page 267
dsPIC33FJXXXMCX06/X08/X10
TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
66
RRNC
RRNC
RRNC
RRNC
SAC
f
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
N,Z
f,WREG
Ws,Wd
N,Z
67
SAC
Acc,#Slit4,Wdo
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = sign-extended Ws
f = 0xFFFF
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
71
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
WREG = Left Shift f
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
72
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
SUB
SUB
Wd = Wb – Ws
SUB
Wd = Wb – lit5
73
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
f = f – WREG – (C)
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
74
75
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
Wd = lit5 – Wb – (C)
Wn = nibble swap Wn
Wn = byte swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
76
SWAP
Wn
None
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
None
XOR
f
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
Wnd = Zero-extend Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
N,Z
83
ZE
ZE
C,Z,N
DS70287C-page 268
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
25.1 MPLAB Integrated Development
Environment Software
25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2009 Microchip Technology Inc.
DS70287C-page 269
dsPIC33FJXXXMCX06/X08/X10
25.2 MPASM Assembler
25.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
25.6 MPLAB SIM Software Simulator
25.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
25.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS70287C-page 270
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
25.7 MPLAB ICE 2000
High-Performance
25.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
25.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2009 Microchip Technology Inc.
DS70287C-page 271
dsPIC33FJXXXMCX06/X08/X10
25.11 PICSTART Plus Development
Programmer
25.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
25.12 PICkit 2 Development Programmer
The PICkit 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70287C-page 272
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJXXXMCX06/X08/X10 electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJXXXMCX06/X08/X10 family are listed below. Exposure to these maximum
rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any
other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias...............................................................................................................-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V
Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx
and PGEDx pins, which are able to sink/source 12 mA.
© 2009 Microchip Technology Inc.
DS70287C-page 273
dsPIC33FJXXXMCX06/X08/X10
26.1 DC Characteristics
TABLE 26-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
Characteristic
dsPIC33FJXXXMCX06/X08/X10
DC5
3.0-3.6V
-40°C to +85°C
40
TABLE 26-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
dsPIC33FJXXXMCX06/X08/X10
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – Σ IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/θJA
TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 100-pin TQFP (14x14x1 mm)
Package Thermal Resistance, 100-pin TQFP (12x12x1 mm)
Package Thermal Resistance, 80-pin TQFP (12x12x1 mm)
Package Thermal Resistance, 64-pin TQFP (10x10x1 mm)
θJA
θJA
θJA
θJA
40
40
40
40
—
—
—
—
°C/W
°C/W
°C/W
°C/W
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
DS70287C-page 274
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
3.0
1.8
—
—
—
—
3.6
—
V
V
V
—
—
—
DC12
DC16
VDR
RAM Data Retention Voltage(2)
VDD Start Voltage(4)
VPOR
VSS
to ensure internal
Power-on Reset signal
DC17
DC18
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
VDD Core(3)
Internal regulator voltage
0.03
2.25
—
—
—
V/ms 0-3.0V in 0.1s
VCORE
2.75
V
Voltage is dependent on
load, temperature and VDD
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: This is the limit to which VDD can be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
4: VDD voltage must remain at VSS for a minimum of 200 µs to ensure POR.
© 2009 Microchip Technology Inc.
DS70287C-page 275
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Parameter
Typical(1)
No.
Max
Units
Conditions
Operating Current (IDD)(2)
DC20d
DC20a
DC20b
DC21d
DC21a
DC21b
DC22d
DC22a
DC22b
DC23d
DC23a
DC23b
DC24d
DC24a
DC24b
27
27
27
36
37
38
43
46
46
65
65
65
84
84
84
30
30
30
40
40
45
50
50
55
70
70
70
90
90
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
3.3V
3.3V
3.3V
3.3V
3.3V
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits
are all zeroed).
DS70287C-page 276
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Parameter
Typical(1)
No.
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
DC40a
DC40b
DC41d
DC41a
DC41b
DC42d
DC42a
DC42b
DC43a
DC43d
DC43b
DC44d
DC44a
DC44b
3
3
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+25°C
-40°C
+85°C
-40°C
+25°C
+85°C
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
3.3V
3.3V
3
4
5
6
8
9
3.3V
3.3V
3.3V
10
15
15
15
16
16
16
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
© 2009 Microchip Technology Inc.
DS70287C-page 277
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Parameter
Typical(1)
No.
Max
Units
Conditions
Power-Down Current (IPD)(2)
DC60d
DC60a
DC60b
DC61d
DC61a
DC61b
55
211
244
8
500
500
500
13
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
3.3V
3.3V
Base Power-Down Current(3,4)
(3)
10
15
Watchdog Timer Current: ΔIWDT
12
20
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
TABLE 26-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Parameter
Typical(1)
No.
Max
Doze Ratio
Units
Conditions
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
11
11
11
42
26
25
41
25
24
35
30
30
50
30
30
50
30
30
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
3.3V
40 MIPS
1:64
1:128
1:2
3.3V
3.3V
40 MIPS
40 MIPS
1:64
1:128
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
DS70287C-page 278
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage
I/O pins
DI10
DI15
DI16
DI18
DI19
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
MCLR
I/O Pins with OSC1 or SOSCI
I/O Pins with I2C
I/O Pins with I2C
Input High Voltage
SMbus disabled
SMbus enabled
VIH
DI20
I/O Pins Not 5V Tolerant(4)
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins 5V Tolerant(4)
2
2
—
—
VDD
5.5
V
V
VDD = 3.3V
VDD = 3.3V
DI26
DI28
DI29
I/O Pins with OSC1 or SOSCI 0.7 VDD
—
—
—
VDD
5.5
V
V
V
I/O Pins with I2C
0.7 VDD
0.8 VDD
SMbus disabled
SMbus enabled
I/O Pins with I2C
5.5
ICNPU
IIL
CNx Pull-up Current
DI30
50
250
400
μA VDD = 3.3V, VPIN = VSS
Input Leakage Current(2,3)
DI50
I/O Pins
—
—
—
—
—
—
—
—
—
—
±2
±2
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI51a
DI51b
DI51c
±2
μA Shared with external reference
pins
±3.5
±8
μA VSS ≤ VPIN ≤ VDD, Pin at
high-impedance
μA Analog pins shared with
external reference pins
DI55
DI56
MCLR
OSC1
—
—
—
—
±2
±2
μA
VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for a list of 5V tolerant pins.
© 2009 Microchip Technology Inc.
DS70287C-page 279
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
DO10
DO16
—
—
—
—
0.4
0.4
V
V
IOL = 2mA, VDD = 3.3V
IOL = 2mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
DO20
DO26
2.40
2.41
—
—
—
—
V
V
IOH = -2.3 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 3.3V
OSC2/CLKO
TABLE 26-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min(1) Typ Max(1) Units
Conditions
BO10
VBOR
BOR Event on VDD transition
high-to-low
2.40 2.55
—
V
—
BOR event is tied to VDD core voltage
decrease
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
DS70287C-page 280
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min Typ(1)
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130a EP
100
1000
—
—
E/W See Note 2
D131
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
—
—
—
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications
are violated
Supply Current during
Programming
—
—
mA
D136a TRW
D137a TPE
D138a TWW
Row Write Time
1.32
20.1
42.3
1.74
26.5
55.9
ms TRW = 11064 FRC cycles,
See Note 2
Page Erase Time
Word Write Cycle Time
ms TPE = 168517 FRC cycles,
See Note 2
µs TWW = 355 FRC cycles,
See Note 2
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111(for Min), TUN<5:0> = b'100000(for Max).
This parameter depends on the FRC accuracy (see Table 26-19) and the value of the FRC Oscillator Tun-
ing register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see
Section 5.3 “Programming Operations”.
TABLE 26-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
Comments
CEFC
External Filter Capacitor
Value
4.7
10
—
μF
Capacitor must be low
series resistance
(< 5 ohms)
© 2009 Microchip Technology Inc.
DS70287C-page 281
dsPIC33FJXXXMCX06/X08/X10
26.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
dsPIC33FJXXXMCX06/X08/X10 AC characteristics
and timing parameters.
TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Operating voltage VDD range as described in Section 26.0 “Electrical
Characteristics”.
FIGURE 26-1:
Load Condition 1 – for all pins except OSC2
VDD/2
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2
VSS
15 pF for OSC2 output
TABLE 26-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ
Max Units
Conditions
No.
DO50 COSC2
OSC2/SOSC2 pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
DS70287C-page 282
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS30 OS30
OS25
OS31 OS31
OS41
OS40
TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
No.
bol
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
—
—
10
40
33
MHz XT
MHz HS
kHz SOSC
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2)
12.5
25
—
—
—
DC
DC
ns
ns
TosL, External Clock in (OSC1)
TosH High or Low Time
0.375 x TOSC
0.625 x
TOSC
ns
EC
EC
OS31
TosR, External Clock in (OSC1)
TosF Rise or Fall Time
—
—
20
ns
OS40
OS41
OS42
TckR CLKO Rise Time(3)
—
—
14
5.2
5.2
16
—
—
18
ns
ns
—
—
TckF
GM
CLKO Fall Time(3)
External Oscillator
mA/V VDD = 3.3V
TA = +25ºC
Transconductance(4)
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
DS70287C-page 283
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range(2)
0.8
—
8.0
MHz ECPLL, HSPLL, XTPLL
modes
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
—
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
0.9
1.5
0.5
3.1
3.0
ms
%
—
-3.0
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
TABLE 26-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2)
FRC -2 +2
F20
—
%
-40°C ≤ TA ≤ +85°C
VDD = 3.0-3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
2: FRC set to initial frequency of 7.37 MHz (+1-2%) at 25° C FRC.
TABLE 26-19: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21
-20
±6
+20
%
-40°C ≤ TA ≤ +85°C
VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
DS70287C-page 284
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
20
2
10
10
—
—
25
25
—
—
ns
ns
—
—
—
—
Port Output Fall Time
INTx Pin High or Low Time (output)
CNx High or Low Time (input)
ns
DI40
TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2009 Microchip Technology Inc.
DS70287C-page 285
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
SY30
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 26-1 for load conditions.
DS70287C-page 286
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TMCL
MCLR Pulse-Width (low)
Power-up Timer Period
2
—
—
μs
-40°C to +85°C
TPWRT
—
—
—
—
—
—
—
2
4
8
16
32
64
128
—
—
—
—
—
—
—
ms
-40°C to +85°C
User programmable
SY12
SY13
TPOR
TIOZ
Power-on Reset Delay
3
10
30
μs
μs
-40°C to +85°C
—
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.68
0.72
1.2
SY20
TWDT1
Watchdog Timer Time-out
Period
—
—
—
—
See Section 23.4 “Watchdog
Timer (WDT)” and LPRC
specification F21 (Table 26-19)
SY30
SY35
TOST
Oscillator Start-up Timer
Period
—
—
1024 TOSC
500
—
—
TOSC = OSC1 period
-40°C to +85°C
TFSCM
Fail-Safe Clock Monitor
Delay
900
μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2009 Microchip Technology Inc.
DS70287C-page 287
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-5:
TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 26-1 for load conditions.
(1)
TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 40
—
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale
value
(TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
20
—
—
—
ns
—
—
OS60
TA20
Ft1
SOSC1/T1CK Oscillator Input
frequency Range (oscillator enabled
by setting bit TCS (T1CON<1>))
DC
50
kHz
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
—
Note 1: Timer1 is a Type A.
DS70287C-page 288
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-23: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
TB10
TB11
TB15
TtxH
TtxL
TtxP
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
Must also meet
parameter TB15
Synchronous,
with prescaler
10
TxCK Input
Period
Synchronous,
no prescaler
TCY + 40
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXT-
MRL
Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
—
TABLE 26-24: TIMER3, TIMER5, TIMER7 AND TIMER9 EXTERNAL CLOCK TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TC10
TC11
TC15
TtxH
TtxL
TtxP
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns
ns
ns
Must also meet
parameter TC15
0.5 TCY + 20
TCY + 40
—
—
Must also meet
parameter TC15
TxCK Input Period Synchronous,
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5
TCY
—
—
© 2009 Microchip Technology Inc.
DS70287C-page 289
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-6:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
—
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
ICx Input Period
(TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 26-7:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
DS70287C-page 290
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 26-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse-Width
50
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
© 2009 Microchip Technology Inc.
DS70287C-page 291
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-9:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA/B
PWMx
MP20
FIGURE 26-10:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
MP10
MP11
TFPWM
TRPWM
TFD
PWM Output Fall Time
PWM Output Rise Time
—
—
—
—
—
—
—
—
50
ns
ns
ns
See parameter D032
See parameter D031
—
Fault Input ↓ to PWM
I/O Change
MP20
MP30
TFH
Minimum Pulse-Width
50
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
DS70287C-page 292
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-11:
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEB
Internal
TABLE 26-29: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Typ(2)
Max
Units
Conditions
TQ30
TQ31
TQ35
TQ36
TQ40
TQUL
Quadrature Input Low Time
Quadrature Input High Time
Quadrature Input Period
Quadrature Phase Period
6 TCY
6 TCY
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
TQUH
TQUIN
TQUP
TQUFL
12 TCY
3 TCY
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
TQ41
TQUFH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. “Quadrature Encoder
Interface (QEI)” (DS70208) in the “dsPIC33F Family Reference Manual”.
© 2009 Microchip Technology Inc.
DS70287C-page 293
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-12:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position Coun-
ter Reset
TABLE 26-30: QEI INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
TQ50
TQ51
TQ55
TqIL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TqiH
Tqidxr
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
3 TCY
—
—
ns
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
Index Pulse Recognized to Position
Counter Reset (ungated index)
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on falling edge.
DS70287C-page 294
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-13:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 26-31: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10 TtQH
TQ11 TtQL
TQ15 TtQP
TQCK High Time Synchronous,
with prescaler
TCY + 20
—
—
ns
Must also meet
parameter TQ15
TQCK Low Time
Synchronous,
with prescaler
TCY + 20
—
—
—
—
—
ns
ns
—
Must also meet
parameter TQ15
TQCP Input
Period
Synchronous, 2 * TCY + 40
with prescaler
—
TQ20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5 TCY
—
Note 1: These parameters are characterized but not tested in manufacturing.
© 2009 Microchip Technology Inc.
DS70287C-page 295
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-14:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-32: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP11
SP20
TscL
TscH
TscF
SCKx Output Low Time
SCKx Output High Time
SCKx Output Fall Time
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
23
30
—
—
—
6
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter D032
and Note 4
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
—
—
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70287C-page 296
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-15:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP20
LSb
MSb
SP40
Bit 14 - - - - - -1
SDOX
SDIX
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-33: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
SP11
SP20
SP21
SP30
TscL
TscH
TscF
TscR
TdoF
SCKx Output Low Time(3)
SCKx Output High Time(3)
SCKx Output Fall Time(4)
SCKx Output Rise Time(4)
TCY/2
TCY/2
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
See parameter D032
See parameter D031
See parameter D032
—
SDOx Data Output Fall
Time(4)
—
SP31
SP35
SP36
SP40
SP41
TdoR
SDOx Data Output Rise
Time(4)
—
—
20
30
20
—
6
—
20
—
—
—
ns
ns
ns
ns
ns
See parameter D031
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2009 Microchip Technology Inc.
DS70287C-page 297
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-16:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP =
0
)
)
SP71
SP70
SP72
SP73
SP72
SCKX
(CKP =
1
SP73
LSb
SP35
MSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-34: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKx Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKx Input High Time
—
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP40
SP41
SP50
SP51
SP52
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
—
—
—
—
—
—
50
—
ns
ns
ns
ns
ns
—
—
—
—
—
TscH2diL, Hold Time of SDIx Data Input
20
120
TscL2diL
to SCKx Edge
TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input
TssL2scL
TssH2doZ SSx ↑ to SDOx Output
10
High-Impedance(3)
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized but not tested in manufacturing.
DS70287C-page 298
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-17:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
SP52
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 26-1 for load conditions.
© 2009 Microchip Technology Inc.
DS70287C-page 299
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-35: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TscL
TscH
TscF
TscR
TdoF
TdoR
SCKx Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKx Input High Time
—
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP40
SP41
SP50
SP51
SP52
SP60
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
—
—
—
—
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
20
TssL2scH, SSx ↓ to SCKx ↓ or SCKx ↑
TssL2scL Input
120
TssH2doZ SSx ↑ to SDOX Output
10
1.5 TCY + 40
—
High-Impedance(4)
TscH2ssH SSx ↑ after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70287C-page 300
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-18:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 26-1 for load conditions.
FIGURE 26-19:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 26-1 for load conditions.
© 2009 Microchip Technology Inc.
DS70287C-page 301
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
pF
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
250
100
40
0
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
CB
Bus Capacitive Loading
400
—
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™
(I2C™)” (DS70195) in the “dsPIC33F Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70287C-page 302
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-20:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 26-21:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
© 2009 Microchip Technology Inc.
DS70287C-page 303
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
1.3
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
IS11
THI:SCL
Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
—
300
300
100
1000
300
300
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode 20 + 0.1 CB
1 MHz mode(1)
—
—
SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode 20 + 0.1 CB
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
250
100
100
0
TSU:DAT Data Input
Setup Time
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:STO Stop Condition
Hold Time
—
—
TAA:SCL
Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70287C-page 304
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-22:
CAN MODULE I/O TIMING CHARACTERISTICS
CiTx Pin
(output)
New Value
Old Value
CA10 CA11
CA20
CiRx Pin
(input)
TABLE 26-38: ECAN™ MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
CA10
CA11
CA20
TioF
TioR
Tcwf
Port Output Fall Time
Port Output Rise Time
—
—
—
—
—
—
—
—
ns
ns
ns
See parameter D032
See parameter D031
—
Pulse-Width to Trigger
CAN Wake-up Filter
120
Note 1: These parameters are characterized but not tested in manufacturing.
© 2009 Microchip Technology Inc.
DS70287C-page 305
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-39: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 3.0
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
AD02
AVSS
Module VSS Supply
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.7
—
—
AVDD
3.6
V
V
See Note 1
AD05a
3.0
VREFH = AVDD
VREFL = AVSS = 0
AD06
VREFL
Reference Voltage Low
AVSS
0
—
—
AVDD – 2.7
0
V
V
See Note 1
AD06a
VREFH = AVDD
VREFL = AVSS = 0
AD07
AD08
VREF
IREF
Absolute Reference
Voltage
2.7
—
3.6
V
VREF = VREFH - VREFL
Current Drain
—
—
250
—
550
10
μA ADC operating, see Note 1
μA ADC off, see Note 1
AD08a IAD
Operating Current
—
—
7.0
2.7
9.0
3.2
mA 10-bit ADC mode, See Note 2
mA 12-bit ADC mode, See Note 2
Analog Input
AD12
AD13
VINH
Input Voltage Range VINH
Input Voltage Range VINL
VINL
—
VREFH
V
V
This voltage reflects Sample
and Hold Channels 0, 1, 2 and
3 (CH0-CH3), positive input
VINL
RIN
VREFL
—
AVSS + 1V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
AD17
Recommended Imped-
ance of Analog Voltage
Source
—
—
—
—
200
200
Ω
Ω
10-bit ADC
12-bit ADC
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized; but not tested in manufacturing
DS70287C-page 306
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-40: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-
AD20a Nr
AD21a INL
Resolution
12 data bits
—
bits
Integral Nonlinearity
-2
+2
<1
3
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
AD22a DNL
Differential Nonlinearity
Gain Error
>-1
1.25
1.25
—
—
1.5
1.52
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
Offset Error
2
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
Monotonicity
—
—
Guaranteed
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-
AD20b Nr
AD21b INL
AD22b DNL
Resolution
12 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
>-1
2
—
—
3
+2
<1
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
Offset Error
2
3
5
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (12-bit Mode)
AD30a THD
Total Harmonic Distortion
-77
59
-69
63
-61
64
dB
dB
—
—
AD31a SINAD
Signal to Noise and
Distortion
AD32a SFDR
Spurious Free Dynamic
Range
63
72
74
dB
—
AD33a
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
250
—
kHz
bits
—
—
AD34a ENOB
10.95
11.1
© 2009 Microchip Technology Inc.
DS70287C-page 307
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-41: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-
AD20c Nr
AD21c INL
Resolution
10 data bits
—
bits
Integral Nonlinearity
-1.5
>-1
1
+1.5
<1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22c DNL
Differential Nonlinearity
Gain Error
—
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23c
AD24c
AD25c
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
1
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
—
—
Guaranteed
ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-
AD20d Nr
AD21d INL
AD22d DNL
Resolution
10 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
>-1
1
—
—
5
+1
<1
6
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23d
AD24d
AD25d
GERR
EOFF
—
Offset Error
1
2
3
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (10-bit Mode)
AD30b THD
Total Harmonic Distortion
—
—
-64
57
-67
58
dB
dB
—
—
AD31b SINAD
Signal to Noise and
Distortion
AD32b SFDR
Spurious Free Dynamic
Range
—
60
62
dB
—
AD33b
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
550
9.8
kHz
bits
—
—
AD34b ENOB
9.1
9.7
DS70287C-page 308
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-23:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
TSAMP
AD55
CONV
ADxIF
Buffer(0)
1
2
3
4
5
6
7
8
9
– Software sets ADxCON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F Family Reference Manual”.
– Software clears ADxCON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 11.
3
4
5
6
7
8
9
– Convert bit 10.
– Convert bit 1.
– Convert bit 0.
– One TAD for end of conversion.
© 2009 Microchip Technology Inc.
DS70287C-page 309
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-42: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(1) Max.
Units
Conditions
Clock Parameters
AD50a TAD
AD51a tRC
ADC Clock Period
117.6
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator
Period
—
250
Conversion Rate
AD55a tCONV
AD56a FCNV
AD57a TSAMP
Conversion Time
Throughput Rate
Sample Time
—
—
14 TAD
—
ksps
—
—
—
—
—
—
500
—
3.0 TAD
Timing Parameters
AD60a tPCS
AD61a tPSS
AD62a tCSS
AD63a tDPU
Conversion Start from Sample
Trigger(2)
2.0 TAD
2.0 TAD
—
—
3.0 TAD
3.0 TAD
—
—
—
—
μs
—
—
—
—
Sample Start from Setting
Sample (SAMP) bit(2)
—
Conversion Completion to
0.5 TAD
—
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: tDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1).
During this time, the ADC result is indeterminate.
DS70287C-page 310
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-24:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
TSAMP
AD55
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F Family Reference Manual”.
– Software clears ADxCON. SAMP to start conversion.
3
4
5
6
7
8
– Sampling ends, conversion sequence starts.
– Convert bit 9.
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
© 2009 Microchip Technology Inc.
DS70287C-page 311
dsPIC33FJXXXMCX06/X08/X10
FIGURE 26-25:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> =
01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
TSAMP
AD55
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
– Software sets ADxCON. ADON to start AD operation.
– Convert bit 0.
1
2
5
6
7
8
– Sampling starts after discharge period. TSAMP is described in
Section 16. “Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F Family Reference Manual”.
– One TAD for end of conversion.
– Begin conversion of next channel.
– Sample for time specified by SAMC<4:0>.
– Convert bit 9.
– Convert bit 8.
3
4
DS70287C-page 312
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE 26-43: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C
Param
Symbol
No.
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters
AD50b TAD
AD51b tRC
ADC Clock Period
76
—
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator Period
250
Conversion Rate
AD55b tCONV
AD56b FCNV
Conversion Time
Throughput Rate
—
—
12 TAD
—
1.1
—
—
Msps
—
—
—
—
—
—
AD57b TSAMP Sample Time
2 TAD
Timing Parameters
AD60b tPCS
Conversion Start from Sample
2.0 TAD
—
3.0 TAD
—
Auto-Convert Trigger
(SSRC<2:0> = 111) not
selected
Trigger(2)
AD61b tPSS
AD62b tCSS
AD63b tDPU
Sample Start from Setting
Sample (SAMP) bit(2)
2.0 TAD
—
—
0.5 TAD
—
3.0 TAD
—
—
—
μs
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: tDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1).
During this time, the ADC result is indeterminate.
© 2009 Microchip Technology Inc.
DS70287C-page 313
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 314
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33FJ
256MC706
e
3
-I/PT
0510017
80-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC33FJ128
MC708-I/PT
0510017
e
3
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC33FJ256
MC710-I/PT
0510017
e
3
100-Lead TQFP (14x14x1mm)
100-Lead TQFP (14x14x1mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC33FJ256
MC710-I/PF
0510017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS70287C-page 315
dsPIC33FJXXXMCX06/X08/X10
27.2 Package Details
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
A1
β
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
0.50 BSC
–
1.00
–
MAX
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
N
e
A
A2
A1
L
–
1.20
1.05
0.15
0.75
0.95
0.05
0.45
Foot Length
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
E
D
E1
D1
c
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
0.09
0.17
11°
0.20
0.27
13°
b
α
0.22
12°
12°
Mold Draft Angle Top
Mold Draft Angle Bottom
β
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B
DS70287C-page 316
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
DS70287C-page 317
dsPIC33FJXXXMCX06/X08/X10
80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
12 3
α
NOTE 2
A
c
φ
A2
β
A1
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
80
0.50 BSC
–
1.00
–
MAX
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Foot Length
N
e
A
A2
A1
L
–
1.20
1.05
0.15
0.75
0.95
0.05
0.45
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
b
α
β
14.00 BSC
14.00 BSC
12.00 BSC
12.00 BSC
–
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-092B
DS70287C-page 318
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
)ꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
DS70287C-page 319
dsPIC33FJXXXMCX06/X08/X10
100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E
E1
N
b
123
NOTE 2
NOTE 1
c
α
A
φ
L
A1
β
A2
L1
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Leads
Lead Pitch
Overall Height
N
e
A
100
0.40 BSC
–
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
Foot Length
A2
A1
L
0.95
0.05
0.45
1.00
–
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
E
D
E1
D1
c
b
α
β
14.00 BSC
14.00 BSC
12.00 BSC
12.00 BSC
–
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
0.09
0.13
11°
0.20
0.23
13°
0.18
12°
12°
Mold Draft Angle Top
Mold Draft Angle Bottom
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-100B
DS70287C-page 320
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
DS70287C-page 321
dsPIC33FJXXXMCX06/X08/X10
100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
NOTE 2
A
φ
c
A2
A1
β
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
100
0.50 BSC
–
1.00
–
MAX
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Foot Length
N
e
A
A2
A1
L
–
1.20
1.05
0.15
0.75
0.95
0.05
0.45
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
b
α
β
16.00 BSC
16.00 BSC
14.00 BSC
14.00 BSC
–
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-110B
DS70287C-page 322
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢓꢗꢇMꢇꢘꢁꢚꢘꢁꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
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© 2009 Microchip Technology Inc.
DS70287C-page 323
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 324
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
APPENDIX A: REVISION HISTORY
Revision A (June 2007)
Initial release of this document.
Revision B (March 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
Section 3.0 “Memory Organization”
Updated Change Notification Register Map table title to reflect
application with dsPIC33FJXXXMCX10 devices (Table 3-2).
Added Change Notification Register Map tables (Table 3-3 and
Table 3-4) for dsPIC33FJXXXMCX08 and dsPIC33FJXXXMCX06
devices, respectively.
Updated SFR names in 8-Output PWM Register Map (Table 3-9).
Updated SFR names in QEI Register Map (Table 3-10).
Updated the bit range for AD1CON3 (ADCS<7:0>) in the ADC1
Register Map and added Note 1 (Table 3-17).
Updated the bit range for AD2CON3 (ADCS<7:0>) in the ADC2
Register Map (Table 3-18).
Updated the Reset value for C1FEN1 (FFFF) in the ECAN1 Register
Map When C1CTRL1.WIN = 0or 1(Table 3-20).
Updated the Reset value for C2FEN1 (FFFF) in the ECAN2 Register
Map When C2CTRL1.WIN = 0or 1and updated the title to reflect
application for dsPIC33FJXXXMC708/710 devices (Table 3-23).
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 0to reflect application toward dsPIC33FJXXXMC708/710 devices
(Table 3-24).
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 1to reflect application with dsPIC33FJXXXMC708/710 devices
(Table 3-25).
Updated Reset value for TRISA (C6FF) and changed the bit 12 and
bit 13 values for all File Names to unimplemented in the PORTA
Register Map (Table 3-26).
Added PMD Register Map (Table 4-35).
Section 5.0 “Reset”
Added POR and BOR references in Reset Flag Bit Operation
(Table 5-1).
Section 7.0 “Direct Memory Access (DMA)” Updated the table cross-reference in Note 2 in the DMAxREQ
register (Register 7-2).
© 2009 Microchip Technology Inc.
DS70287C-page 325
dsPIC33FJXXXMCX06/X08/X10
TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 8.0 “Oscillator Configuration”
Updated the third clock source item (External Clock) in
Section 8.1.1 “System Clock Sources”.
Added the center frequency in the OSCTUN register for the FRC
Tuning bits (TUN<5:0>) value 011111and updated the center
frequency for bits value 011110(Register 8-4).
Section 15.0 “Motor Control PWM Module” Removed sections 15.1 through 15.16 (redundant information,
which is now available in the related section in the “dsPIC33F
Family Reference Manual”).
Updated SFR names in the PWM Module Block Diagram (Figure 15-
1).
Updated all register names (Register 16-1 through Register 15-15).
Section 16.0 “Quadrature Encoder
Interface (QEI) Module”
Removed sections 16.1 through 16.9 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated names in Quadrature Encoder Interface Block Diagram
(Figure 16-1).
Updated register names (Register 16-1 and Register 16-2).
Section 17.0 “Serial Peripheral Interface
(SPI)”
Removed redundant information, which is now available in the
related section in the “dsPIC33F Family Reference Manual”.
Section 18.0 “Inter-Integrated Circuit™
(I2C™)”
Removed sections 18.3 through 18.14, while retaining the I2C Block
Diagram (Figure 18-1) (redundant information, which is now
available in the related section in the “dsPIC33F Family Reference
Manual”).
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Removed sections 19.1 through 19.7 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Section 20.0 “Enhanced CAN (ECAN™)
Module”
Removed sections 20.4 through 20.6 (redundant information, which
is now available in the related section in the “dsPIC33F Family
Reference Manual”).
Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1
register (Register 20-9).
Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15
(FLTEN6-FLTEN15) in the CiFEN1 register (Register 20-11).
Section 21.0 “10-Bit/12-Bit Analog-to-
Digital Converter (ADC)”
Removed Equation 21-1 (ADC Conversion Clock Period) and Figure
21-3 (ADC Transfer Function (10-Bit Example) in Section 21.0 “10-
bit/12-bit Analog-to-Digital Converter (ADC)”
Updated AN14 and AN15 ADC values in the ADC2 Module Block
Diagram (Figure 21-2).
Added Note 2 to ADC Conversion Clock Period Block Diagram
(Figure 21-3).
Added Note to ADxCHS0 register (Register 21-6).
Updated ADC Conversion Clock Select bits in the ADxCON3
register from ADCS<5:0> to ADCS<7:0>. Any references to these
bits have also been updated throughout this data sheet
(Register 21-3).
DS70287C-page 326
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE A-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 22.0 “Special Features”
Added a Note after the second paragraph in Section 22.2 “On-Chip
Voltage Regulator”.
Updated address 0xF8000E in the Device Configuration Register
Map (Table 22-1).
Added FICD register content (BKBUG, COE, JTAGEN and
ICS<1:0>) to the dsPIC33F Configuration Bits Description and
removed the last two rows (Table 22-2).
© 2009 Microchip Technology Inc.
DS70287C-page 327
dsPIC33FJXXXMCX06/X08/X10
Revision C (March 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of VDDCORE and VDDCORE/
VCAP to VCAP/VDDCORE
The other changes are referenced by their respective
section in the following table.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit Digital
Signal Controllers”
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to VSS.
Section 1.0 “Device Overview”
Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).
Section 2.0 “Guidelines for Getting
Started with 16-Bit Digital Signal
Controllers”
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Microcontrollers.
Section 4.0 “Memory Organization”
Add Accumulator A and B SFRs (ACCAL, ACCAH, ACCAU, ACCBL,
ACCBH and ACCBU) and updated the Reset value for CORCON in the
CPU Core Register Map (see Table 4-1).
Updated Reset values for IPC3, IPC4, IPC11 and IPC13-IPC15 in the
Interrupt Controller Register Map (see Table 4-5).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-33).
Section 5.0 “Flash Program Memory” Updated Section 5.3 “Programming Operations” with programming
time formula.
Section 9.0 “Oscillator Configuration” Added Note 2 to the Oscillator System Diagram (see Figure 9-1).
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock Sources”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
Section 10.0 “Power-Saving
Features”
Added the following registers:
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
Section 11.0 “I/O Ports”
Added reference to pin diagrams for I/O pin availability and functionality
(see Section 11.2 “Open-Drain Configuration”).
Section 18.0 “Serial Peripheral
Interface (SPI)”
Added Note 2 to the SPIxCON1 register (see Register 18-2).
Section 20.0 “Universal
Updated the UTXINV bit settings in the UxSTA register (see
Asynchronous Receiver Transmitter Register 20-2).
(UART)”
DS70287C-page 328
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
TABLE A-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 21.0 “Enhanced CAN
(ECAN™) Module”
Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved
(see Register 21-1).
Added the ECAN Filter 15-8 Mask Selection (CiFMSKSEL2) register (see
Register 21-19).
Section 22.0 “10-Bit/12-Bit Analog-to- Replaced the ADC Module Block Diagram (see Figure 22-1) and removed
Digital Converter (ADC)”
Figure 21-2.
Section 23.0 “Special Features”
Added Note 2 to the Device Configuration Register Map (see Table 23-1).
Section 26.0 “Electrical
Characteristics”
Updated Typical values for Thermal Packaging Characteristics (see
Table 26-3).
Updated Min and Max values for parameter DC12 (RAM Data Retention
Voltage) and added Note 4 (see Table 26-4).
Updated Power-Down Current Max values for parameters DC60b and
DC60c (see Table 26-7).
Updated Characteristics for I/O Pin Input Specifications (see Table 26-9).
Updated Program Memory values for parameters 136, 137 and 138
(renamed to 136a, 137a and 138a), added parameters 136b, 137b and
138b, and added Note 2 (see Table 26-12).
Added parameter OS42 (GM) to the External Clock Timing Requirements
(see Table 26-16).
Updated Watchdog Timer Time-out Period parameter SY20 (see
Table 26-21).
© 2009 Microchip Technology Inc.
DS70287C-page 329
dsPIC33FJXXXMCX06/X08/X10
NOTES:
DS70287C-page 330
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
INDEX
CPU Clocking System ...................................................... 144
Options ..................................................................... 144
Selection................................................................... 144
Customer Change Notification Service............................. 335
Customer Notification Service .......................................... 335
Customer Support............................................................. 335
A
A/D Converter ................................................................... 241
DMA.......................................................................... 241
Initialization ............................................................... 241
Key Features............................................................. 241
AC Characteristics ............................................................ 282
Internal RC Accuracy................................................ 284
Load Conditions........................................................ 282
ADC Module
ADC11 Register Map.................................................. 52
ADC2 Register Map.................................................... 52
Alternate Interrupt Vector Table (AIVT) .............................. 85
Arithmetic Logic Unit (ALU)................................................. 29
Assembler
D
Data Accumulators and Adder/Subtractor .......................... 31
Data Space Write Saturation...................................... 33
Overflow and Saturation............................................. 31
Round Logic ............................................................... 32
Write Back .................................................................. 32
Data Address Space........................................................... 37
Alignment.................................................................... 37
Memory Map for dsPIC33FJXXXMCX06/X08/X10 De-
vices with 16 KB RAM........................................ 39
Memory Map for dsPIC33FJXXXMCX06/X08/X10 De-
vices with 30 KB RAM........................................ 40
Memory Map for dsPIC33FJXXXMCX06/X08/X10 De-
vices with 8 KB RAM.......................................... 38
Near Data Space........................................................ 37
Software Stack ........................................................... 63
Width .......................................................................... 37
DC Characteristics............................................................ 274
I/O Pin Input Specifications ...................................... 279
I/O Pin Output Specifications.................................... 280
Idle Current (IIDLE).................................................... 277
Operating Current (IDD) ............................................ 276
Power-Down Current (IPD)........................................ 278
Program Memory...................................................... 281
Temperature and Voltage Specifications.................. 275
Development Support....................................................... 269
DMA Module
MPASM Assembler................................................... 270
B
Barrel Shifter....................................................................... 33
Bit-Reversed Addressing .................................................... 66
Example...................................................................... 67
Implementation ........................................................... 66
Sequence Table (16-Entry)......................................... 67
Block Diagrams
16-bit Timer1 Module................................................ 163
A/D Module ............................................................... 242
Connections for On-Chip Voltage Regulator............. 258
Device Clock..................................................... 143, 145
DSP Engine ................................................................ 30
dsPIC33F.................................................................... 14
dsPIC33F CPU Core................................................... 24
ECAN Module ........................................................... 216
Input Capture ............................................................ 171
Output Compare ....................................................... 173
PLL............................................................................ 145
PWM Module ............................................................ 178
Quadrature Encoder Interface .................................. 191
Reset System.............................................................. 79
Shared Port Structure ............................................... 161
SPI ............................................................................ 195
Timer2 (16-bit) .......................................................... 167
Timer2/3 (32-bit) ....................................................... 166
UART ........................................................................ 209
Watchdog Timer (WDT)............................................ 259
DMA Register Map ..................................................... 53
DMAC Registers............................................................... 134
DMAxCNT ................................................................ 134
DMAxCON................................................................ 134
DMAxPAD ................................................................ 134
DMAxREQ................................................................ 134
DMAxSTA................................................................. 134
DMAxSTB................................................................. 134
DSP Engine........................................................................ 29
Multiplier ..................................................................... 31
C
E
C Compilers
ECAN Module
MPLAB C18 .............................................................. 270
MPLAB C30 .............................................................. 270
Clock Switching................................................................. 151
Enabling.................................................................... 151
Sequence.................................................................. 151
Code Examples
Erasing a Program Memory Page............................... 76
Initiating a Programming Sequence............................ 77
Loading Write Buffers ................................................. 77
Port Write/Read ........................................................ 162
PWRSAV Instruction Syntax..................................... 153
Code Protection ........................................................ 253, 260
Configuration Bits.............................................................. 253
Configuration Register Map .............................................. 253
Configuring Analog Port Pins............................................ 162
CPU
CiFMSKSEL2 register .............................................. 233
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1)......... 55
ECAN1 Register Map (C1CTRL1.WIN = 0)................ 55
ECAN1 Register Map (C1CTRL1.WIN = 1)................ 56
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1)......... 58
ECAN2 Register Map (C2CTRL1.WIN = 0).......... 58, 59
Frame Types ............................................................ 215
Modes of Operation.................................................. 217
Overview................................................................... 215
ECAN Registers
Filter 15-8 Mask Selection Register (CiFMSKSEL2) 233
Electrical Characteristics .................................................. 273
AC............................................................................. 282
Enhanced CAN Module .................................................... 215
Equations
Device Operating Frequency.................................... 144
Errata.................................................................................. 11
Control Register.......................................................... 26
© 2009 Microchip Technology Inc.
DS70287C-page 331
dsPIC33FJXXXMCX06/X08/X10
Modes of Operation
F
Disable...................................................................... 217
Flash Program Memory.......................................................73
Control Registers ........................................................74
Operations ..................................................................74
Programming Algorithm ..............................................76
RTSP Operation..........................................................74
Table Instructions........................................................73
Flexible Configuration .......................................................253
FSCM
Initialization............................................................... 217
Listen All Messages.................................................. 217
Listen Only................................................................ 217
Loopback .................................................................. 217
Normal Operation ..................................................... 217
Modulo Addressing............................................................. 64
Applicability................................................................. 66
Operation Example..................................................... 65
Start and End Address ............................................... 65
W Address Register Selection.................................... 65
Motor Control PWM .......................................................... 177
Motor Control PWM Module
8-Output Register Map ............................................... 49
MPLAB ASM30 Assembler, Linker, Librarian................... 270
MPLAB ICD 2 In-Circuit Debugger ................................... 271
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
ulator......................................................................... 271
MPLAB Integrated Development Environment Software.. 269
MPLAB PM3 Device Programmer .................................... 271
MPLAB REAL ICE In-Circuit Emulator System ................ 271
MPLINK Object Linker/MPLIB Object Librarian................ 270
Delay for Crystal and PLL Clock Sources...................83
Device Resets.............................................................83
I
I/O Ports............................................................................161
Parallel I/O (PIO).......................................................161
Write/Read Timing ....................................................162
I2C
Addresses.................................................................202
Operating Modes ......................................................201
Registers...................................................................201
I2C Module
I2C1 Register Map......................................................50
I2C2 Register Map......................................................50
In-Circuit Debugger...........................................................260
In-Circuit Emulation...........................................................253
In-Circuit Serial Programming (ICSP) .......................253, 260
Input Capture
N
NVM Module
Register Map .............................................................. 62
Registers...................................................................172
Input Change Notification Module.....................................162
Instruction Addressing Modes.............................................63
File Register Instructions ............................................63
Fundamental Modes Supported..................................64
MAC Instructions.........................................................64
MCU Instructions ........................................................63
Move and Accumulator Instructions............................64
Other Instructions........................................................64
Instruction Set
Overview...................................................................264
Summary...................................................................261
Instruction-Based Power-Saving Modes...........................153
Idle ............................................................................154
Sleep.........................................................................153
Internal RC Oscillator
Use with WDT...........................................................259
Internet Address................................................................335
Interrupt Control and Status Registers................................89
IECx ............................................................................89
IFSx.............................................................................89
INTCON1 ....................................................................89
INTCON2 ....................................................................89
IPCx ............................................................................89
Interrupt Setup Procedures...............................................131
Initialization ...............................................................131
Interrupt Disable........................................................131
Interrupt Service Routine ..........................................131
Trap Service Routine ................................................131
Interrupt Vector Table (IVT) ................................................85
Interrupts Coincident with Power Save Instructions..........154
O
Open-Drain Configuration................................................. 162
Output Compare ............................................................... 173
P
Packaging......................................................................... 315
Details....................................................................... 316
Marking..................................................................... 315
Peripheral Module Disable (PMD) .................................... 154
PICSTART Plus Development Programmer..................... 272
Pinout I/O Descriptions (table)............................................ 15
PMD Module
Register Map .............................................................. 62
POR and Long Oscillator Start-up Times ........................... 83
PORTA
Register Map .............................................................. 60
PORTB
Register Map .............................................................. 60
PORTC
Register Map .............................................................. 61
PORTD
Register Map .............................................................. 61
PORTE
Register Map .............................................................. 61
PORTF
Register Map .............................................................. 61
PORTG
Register Map .............................................................. 62
Power-Saving Features .................................................... 153
Clock Frequency and Switching ............................... 153
Program Address Space..................................................... 35
Construction ............................................................... 68
Data Access from Program Memory Using Program
Space Visibility ................................................... 71
Data Access from Program Memory Using Table Instruc-
tions.................................................................... 70
Data Access from, Address Generation ..................... 69
Memory Map............................................................... 35
J
JTAG Boundary Scan Interface ........................................253
M
Memory Organization..........................................................35
Microchip Internet Web Site..............................................335
DS70287C-page 332
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
Table Read Instructions
DMACS1 (DMA Controller Status 1) ........................ 141
TBLRDH ............................................................. 70
TBLRDL.............................................................. 70
Visibility Operation ...................................................... 71
DMAxCNT (DMA Channel x Transfer Count)........... 138
DMAxCON (DMA Channel x Control)....................... 135
DMAxPAD (DMA Channel x Peripheral Address) .... 138
DMAxREQ (DMA Channel x IRQ Select)................. 136
DMAxSTA (DMA Channel x RAM Start Address A). 137
DMAxSTB (DMA Channel x RAM Start Address B). 137
DSADR (Most Recent DMA RAM Address) ............. 142
DTCON1 (Dead-Time Control 1).............................. 184
DTCON2 (Dead-Time Control 2).............................. 185
FLTACON (Fault A Control) ..................................... 186
FLTBCON (Fault B Control) ..................................... 187
I2CxCON (I2Cx Control)........................................... 203
I2CxMSK (I2Cx Slave Mode Address Mask)............ 207
I2CxSTAT (I2Cx Status)........................................... 205
ICxCON (Input Capture x Control)............................ 172
IEC0 (Interrupt Enable Control 0)............................. 103
IEC1 (Interrupt Enable Control 1)............................. 105
IEC2 (Interrupt Enable Control 2)............................. 107
IEC3 (Interrupt Enable Control 3)............................. 109
IEC4 (Interrupt Enable Control 4)............................. 111
IFS0 (Interrupt Flag Status 0)..................................... 94
IFS1 (Interrupt Flag Status 1)..................................... 96
IFS2 (Interrupt Flag Status 2)..................................... 98
IFS3 (Interrupt Flag Status 3)................................... 100
IFS4 (Interrupt Flag Status 4)................................... 102
INTCON1 (Interrupt Control 1) ................................... 91
INTCON2 (Interrupt Control 2) ................................... 93
INTTREG Interrupt Control and Status Register ...... 130
IPC0 (Interrupt Priority Control 0)............................. 112
IPC1 (Interrupt Priority Control 1)............................. 113
IPC10 (Interrupt Priority Control 10)......................... 122
IPC11 (Interrupt Priority Control 11)......................... 123
IPC12 (Interrupt Priority Control 12)......................... 124
IPC13 (Interrupt Priority Control 13)......................... 125
IPC14 (Interrupt Priority Control 14)......................... 126
IPC15 (Interrupt Priority Control 15)......................... 127
IPC16 (Interrupt Priority Control 16)......................... 128
IPC17 (Interrupt Priority Control 17)......................... 129
IPC2 (Interrupt Priority Control 2)............................. 114
IPC3 (Interrupt Priority Control 3)............................. 115
IPC4 (Interrupt Priority Control 4)............................. 116
IPC5 (Interrupt Priority Control 5)............................. 117
IPC6 (Interrupt Priority Control 6)............................. 118
IPC7 (Interrupt Priority Control 7)............................. 119
IPC8 (Interrupt Priority Control 8)............................. 120
IPC9 (Interrupt Priority Control 9)............................. 121
NVMCOM (Flash Memory Control) ............................ 75
OCxCON (Output Compare x Control)..................... 175
OSCCON (Oscillator Control)................................... 146
OSCTUN (FRC Oscillator Tuning)............................ 150
OVDCON (Override Control).................................... 188
PDC1 (PWM Duty Cycle 1) ...................................... 189
PDC2 (PWM Duty Cycle 2) ...................................... 189
PDC3 (PWM Duty Cycle 3) ...................................... 190
PDC4 (PWM Duty Cycle 4) ...................................... 190
PLLFBD (PLL Feedback Divisor) ............................. 149
PMD1 (Peripheral Module Disable Control Register 1)..
155
Program Memory
Interrupt Vector ........................................................... 36
Organization................................................................ 36
Reset Vector ............................................................... 36
Q
Quadrature Encoder Interface (QEI)................................. 191
Quadrature Encoder Interface (QEI) Module
Register Map............................................................... 50
R
Reader Response............................................................. 336
Registers
ADxCHS0 (ADCx Input Channel 0 Select................. 250
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 249
ADxCON1 (ADCx Control 1)..................................... 244
ADxCON2 (ADCx Control 2)..................................... 246
ADxCON3 (ADCx Control 3)..................................... 247
ADxCON4 (ADCx Control 4)..................................... 248
ADxCSSH (ADCx Input Scan Select High)............... 251
ADxCSSL (ADCx Input Scan Select Low) ................ 251
ADxPCFGH (ADCx Port Configuration High) ........... 252
ADxPCFGL (ADCx Port Configuration Low)............. 252
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 228
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 229
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 229
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 230
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 226
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 227
CiCTRL1 (ECAN Control 1) ...................................... 218
CiCTRL2 (ECAN Control 2) ...................................... 219
CiEC (ECAN Transmit/Receive Error Count)............ 225
CiFCTRL (ECAN FIFO Control)................................ 221
CiFEN1 (ECAN Acceptance Filter Enable)............... 228
CiFIFO (ECAN FIFO Status)..................................... 222
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 232,
233
CiINTE (ECAN Interrupt Enable) .............................. 224
CiINTF (ECAN Interrupt Flag)................................... 223
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
fier).................................................................... 231
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
fier).................................................................... 231
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 235
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 235
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
Identifier)........................................................... 234
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
Identifier)........................................................... 234
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 236
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 236
CiTRBnDLC (ECAN Buffer n Data Length Control).. 239
CiTRBnDm (ECAN Buffer n Data Field Byte m) ....... 239
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 238
CiTRBnSID (ECAN Buffer n Standard Identifier)...... 238
CiTRBnSTAT (ECAN Receive Buffer n Status)........ 240
CiTRmnCON (ECAN TX/RX Buffer m Control)......... 237
CiVEC (ECAN Interrupt Code).................................. 220
CLKDIV (Clock Divisor)............................................. 148
CORCON (Core Control) ...................................... 28, 90
DFLTCON (QEI Control)........................................... 194
DMACS0 (DMA Controller Status 0)......................... 139
PMD2 (Peripheral Module Disable Control Register 2)..
157
PMD3 (Peripheral Module Disable Control Register 3)..
159
PTCON (PWM Time Base Control).......................... 179
PTMR (PWM Timer Count Value) ............................ 180
© 2009 Microchip Technology Inc.
DS70287C-page 333
dsPIC33FJXXXMCX06/X08/X10
PTPER (PWM Time Base Period) ............................180
PWMCON1 (PWM Control 1) ...................................182
PWMCON2 (PWM Control 2) ...................................183
QEICON (QEI Control)..............................................192
RCON (Reset Control)................................................80
SEVTCMP (Special Event Compare) .......................181
SPIxCON1 (SPIx Control 1)......................................197
SPIxCON2 (SPIx Control 2)......................................199
SPIxSTAT (SPIx Status and Control) .......................196
SR (CPU Status)...................................................26, 90
T1CON (Timer1 Control)...........................................164
TxCON (T2CON, T4CON, T6CON or T8CON Control) ..
168
SPIx Master Mode (CKE = 1) ................................... 297
SPIx Slave Mode (CKE = 0) ..................................... 298
SPIx Slave Mode (CKE = 1) ..................................... 299
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 288
TimerQ (QEI Module) External Clock ....................... 295
Timing Requirements
CLKO and I/O ........................................................... 285
External Clock........................................................... 283
Input Capture............................................................ 290
Timing Specifications
10-bit A/D Conversion Requirements ....................... 313
12-bit A/D Conversion Requirements ....................... 310
CAN I/O Requirements............................................. 305
I2Cx Bus Data Requirements (Master Mode)........... 302
I2Cx Bus Data Requirements (Slave Mode)............. 304
Motor Control PWM Requirements........................... 292
Output Compare Requirements................................ 290
PLL Clock ................................................................. 284
QEI External Clock Requirements............................ 295
QEI Index Pulse Requirements ................................ 294
Quadrature Decoder Requirements.......................... 293
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
er-up Timer and Brown-out Reset Requirements...
287
Simple OC/PWM Mode Requirements ..................... 291
SPIx Master Mode (CKE = 0) Requirements............ 296
SPIx Master Mode (CKE = 1) Requirements............ 297
SPIx Slave Mode (CKE = 0) Requirements.............. 298
SPIx Slave Mode (CKE = 1) Requirements.............. 300
Timer1 External Clock Requirements....................... 288
Timer2, Timer4, Timer6 and Timer8 External Clock Re-
quirements........................................................ 289
Timer3, Timer5, Timer7 and Timer9 External Clock Re-
quirements........................................................ 289
TyCON (T3CON, T5CON, T7CON or T9CON Control) ..
169
UxMODE (UARTx Mode)..........................................210
UxSTA (UARTx Status and Control).........................212
Reset
Clock Source Selection...............................................82
Special Function Register Reset States .....................84
Times ..........................................................................82
Reset Sequence..................................................................85
Resets.................................................................................79
S
Serial Peripheral Interface (SPI) .......................................195
Software Simulator (MPLAB SIM).....................................270
Software Stack Pointer, Frame Pointer
CALLL Stack Frame....................................................63
Special Features of the CPU.............................................253
SPI Module
SPI1 Register Map......................................................51
SPI2 Register Map......................................................51
Symbols Used in Opcode Descriptions.............................262
System Control
U
Register Map...............................................................62
UART Module
T
UART1 Register Map.................................................. 51
UART2 Register Map.................................................. 51
Temperature and Voltage Specifications
AC.............................................................................282
Timer1...............................................................................163
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 .....................165
Timing Characteristics
CLKO and I/O ...........................................................285
Timing Diagrams
V
Voltage Regulator (On-Chip) ............................................ 258
W
Watchdog Timer (WDT)............................................ 253, 259
Programming Considerations ................................... 259
WWW Address ................................................................. 335
WWW, On-Line Support ..................................................... 11
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 0, SSRC = 000)..............................................311
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 1, SSRC = 111, SAMC = 00001)...................312
12-bit A/D Conversion (ASAM = 0, SSRC = 000).....309
CAN I/O.....................................................................305
External Clock...........................................................283
I2Cx Bus Data (Master Mode) ..................................301
I2Cx Bus Data (Slave Mode) ....................................303
I2Cx Bus Start/Stop Bits (Master Mode) ...................301
I2Cx Bus Start/Stop Bits (Slave Mode).....................303
Input Capture (CAPx)................................................290
Motor Control PWM ..................................................292
Motor Control PWM Fault .........................................292
OC/PWM...................................................................291
Output Compare (OCx).............................................290
QEA/QEB Input.........................................................293
QEI Module Index Pulse ...........................................294
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................286
SPIx Master Mode (CKE = 0)....................................296
DS70287C-page 334
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dsPIC33FJXXXMCX06/X08/X10
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Literature Number: DS70287C
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DS70287C-page 336
© 2009 Microchip Technology Inc.
dsPIC33FJXXXMCX06/X08/X10
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
dsPIC 33 FJ 256 MC7 10 T I / PT - XXX
a)
dsPIC33FJ64MC706I/PT:
Motor Control dsPIC33, 64 KB program
memory, 64-pin, Industrial temp.,
TQFP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
=
16-bit Digital Signal Controller
Flash program memory, 3.3V
Flash Memory Family: FJ
Product Group:
Pin Count:
MC5
=
=
Motor Control family
Motor Control family
MC7
06
08
10
=
=
=
64-pin
80-pin
100-pin
Temperature Range:
Package:
I
=
-40°C to +85°C (Industrial)
PT
PF
=
=
10x10 or 12x12 mm TQFP (Thin Quad Flat-
pack)
14x14 mm TQFP (Thin Quad Flatpack)
Pattern
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2009 Microchip Technology Inc.
DS70287C-page 337
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
02/04/09
DS70287C-page 338
© 2009 Microchip Technology Inc.
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