DSPIC33FJ256MC708IPT [MICROCHIP]
dsPIC DSC High-Performance 16-Bit Digital Signal Controllers; 的dsPIC DSC的高性能16位数字信号控制器型号: | DSPIC33FJ256MC708IPT |
厂家: | MICROCHIP |
描述: | dsPIC DSC High-Performance 16-Bit Digital Signal Controllers |
文件: | 总90页 (文件大小:2849K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
dsPIC33F
Product Overview
dsPIC® DSC High-Performance 16-Bit
Digital Signal Controllers
© 2005 Microchip Technology Inc.
Preliminary
DS70155C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70155C-page ii
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
dsPIC33F High-Performance 16-Bit
Digital Signal Controller Product Overview
Operating Range
Interrupt Controller
• DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40° to +85°C)
• Industrial temperature range (-40° to +85°C)
• 5-cycle latency
• 117 interrupt vectors
• Up to 67 available interrupt sources, up to
5 external interrupts
High-Performance DSC CPU
• 7 programmable priority levels
• 5 processor exceptions
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
Digital I/O
• 24-bit wide instructions
• Up to 85 programmable digital I/O pins
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 84 base instructions: mostly 1 word/1 cycle
• Sixteen 16-bit general purpose registers
• Two 40-bit accumulators:
• 4 mA sink and source on all I/O pins
On-Chip Flash and SRAM
- With rounding and saturation options
• Flexible and powerful addressing modes:
- Indirect, modulo and bit-reversed
• Software stack
• Flash program memory, up to 256 Kbytes
• Data SRAM (up to 30 Kbytes):
- Includes 2 KB of DMA RAM
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply-and-accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
System Management
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated PLL
- Extremely low jitter PLL
• Up to +/- 16-bit shifts, for up to 40-bit data
• Power-up timer
Direct Memory Access (DMA)
• Oscillator Start-up Timer/Stabilizer
• Watchdog timer with its own RC oscillator
• Fail-Safe Clock Monitor
• 8-channel hardware DMA
• Allows data transfer between RAM and a
peripheral while CPU is executing code (no cycle
stealing)
• Reset by multiple sources
Power Management
• 2 KB of dual-ported DMA buffer area (DMA RAM)
to store data transferred via DMA
• On-chip 2.5V voltage regulator
• Most peripherals support DMA
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 1
dsPIC33F
Timers/Capture/Compare/PWM
Motor Control Peripherals
• Timer/Counters: up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
• Motor Control PWM (up to 8 channels):
- 4 duty cycle generators
- 1 timer runs as Real-Time Clock with external
32 kHz oscillator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge or center-aligned
- Programmable prescaler
• Input Capture (up to 8 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to 8 channels):
- Single or Dual 16-Bit Compare mode
- 16-Bit Glitchless PWM mode
- Manual output override control
- Up to 2 Fault inputs
- Trigger for A/D conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
Communication Modules
• Quadrature Encoder Interface module:
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
• 3-wire SPI™ (up to 2 modules):
- Framing supports I/O interface to simple
codecs
- Count direction status
- Supports 8-bit and 16-bit data
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Supports all serial clock formats and
sampling modes
- 8-word FIFO buffers
• I2C™ (up to 2 modules):
- Interrupt on position counter rollover/
underflow
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Address masking
Analog-to-Digital Converters
• Up to two 10-bit or 12-bit A/D modules in a device
• 10-bit 2.2 Msps or 12-bit 1 Msps conversion:
- 2 or 4 simultaneous samples
• UART (up to 2 modules):
- Up to 32 input channels with auto-scanning
- 16-deep result buffer
- Interrupt-on-address bit detect
- Wake-up-on-Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- IrDA® encoding and decoding in hardware
-
-
1 LSB max integral nonlinearity
1 LSB max differential nonlinearity
- High-Speed Baud mode
• Data Conversion Interface (DCI) module:
- Codec interface
- Supports I2S and AC’97 protocols
CMOS Flash Technology
• Low-power, high-speed Flash technology
• Fully static design
- Up to 16-bit data words, up to 16 words per
frame
• 3.3V (+/- 10%) operating voltage
• Industrial temperature
- 4-word deep TX and RX buffers
• Enhanced CAN 2.0B active (up to 2 modules):
- Up to 8 transmit and up to 16 receive buffers
- 16 receive filters and 3 masks
• Low-power consumption
Packaging:
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 80-pin TQFP (12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
- Wake-up on CAN message
- FIFO mode using DMA
Note:
See Table 1-1 and Table 1-2 for exact
peripheral features per device.
DS70155C-page 2
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
1.0
1.1
dsPIC33F PRODUCT FAMILIES
General Purpose Family
The dsPIC33F General Purpose Family (Table 1-1)
is ideal for a wide variety of 16-bit MCU embedded
applications. The variants with codec interfaces are
well-suited for audio applications.
TABLE 1-1:
dsPIC33F GENERAL PURPOSE FAMILY VARIANTS
(1)
Program Flash RAM
Device
Pins
Packages
Memory (KB)
(KB)
33FJ64GP206
33FJ64GP306
33FJ64GP310
33FJ64GP706
33FJ64GP708
33FJ64GP710
33FJ128GP206
33FJ128GP306
64
64
64
64
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 A/D,
18 ch
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
1
2
2
2
2
2
2
2
2
0
0
0
2
2
2
0
0
0
2
2
2
1
1
2
53
53
85
53
69
85
53
53
85
53
69
85
53
85
85
PT
PT
16
16
16
16
16
8
1 A/D,
18 ch
100
64
64
1 A/D,
32 ch
PF, PT
PT
64
2 A/D,
18 ch
80
64
2 A/D,
24 ch
PT
100
64
64
2 A/D,
32 ch
PF, PT
PT
128
128
128
128
128
128
256
256
256
1 A/D,
18 ch
64
16
16
16
16
16
16
16
30
1 A/D,
18 ch
PT
33FJ128GP310 100
1 A/D,
32 ch
PF, PT
PT
33FJ128GP706
33FJ128GP708
64
80
2 A/D,
18 ch
2 A/D,
24 ch
PT
33FJ128GP710 100
33FJ256GP506 64
2 A/D,
32 ch
PF, PT
PT
1 A/D,
18 ch
33FJ256GP510 100
33FJ256GP710 100
1 A/D,
32 ch
PF, PT
PF, PT
2 A/D,
32 ch
Note 1: RAM size is inclusive of 2 KB DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 3
dsPIC33F
Supply (UPS), inverters, Switched mode power
supplies, power factor correction and also for
controlling the power management module in servers,
telecommunication equipment and other industrial
equipment.
1.2
Motor Control Family
This family of dsPIC33F controllers (Table 1-2)
supports a variety of motor control applications, such
as brushless DC motors, single and 3-phase induction
motors and switched reluctance motors. These
products are also well-suited for Uninterrupted Power
TABLE 1-2:
dsPIC33F MOTOR CONTROL AND POWER CONVERSION FAMILY VARIANTS
Program
Flash RAM
(1)
Device
Pins
Packages
Memory (KB)
(KB)
33FJ64MC506
33FJ64MC508
33FJ64MC510
33FJ64MC706
33FJ64MC710
64
80
64
64
8
8
9
9
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
8 ch
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1 A/D,
16 ch
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
2
1
1
1
1
2
1
2
53
69
85
53
85
53
85
53
69
85
85
85
PT
PT
1 A/D,
18 ch
100
64
64
8
1 A/D,
24 ch
PF, PT
PT
64
16
16
8
2 A/D,
16 ch
100
64
2 A/D,
24 ch
PF, PT
PT
33FJ128MC506 64
33FJ128MC510 100
33FJ128MC706 64
33FJ128MC708 80
33FJ128MC710 100
33FJ256MC510 100
33FJ256MC710 100
128
128
128
128
128
256
256
1 A/D,
16 ch
8
1 A/D,
24 ch
PF, PT
PT
16
16
16
16
30
2 A/D,
16 ch
2 A/D,
18 ch
PT
2 A/D,
24 ch
PF, PT
PF, PT
PF, PT
1 A/D,
24 ch
2 A/D,
24 ch
Note 1: RAM size is inclusive of 2 KB DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
DS70155C-page 4
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
PRODUCT IDENTIFICATION SYSTEM
Examples:
dsPIC 33 FJ 256 GP7 10 T I / PT - XXX
a)
dsPIC33FJ256GP710I/PT-PS:
General Purpose dsPIC33, 64 KB program
Microchip Trademark
Architecture
memory, 100-pin, Industrial temp.,
TQFP package, Prototype Sample.
Flash Memory Family
Program Memory Size (KB)
Product Group
b)
dsPIC33FJ64MC706I/PT-ES:
Motor Control dsPIC33, 64 KB program
memory, 64-pin, Industrial temp.,
TQFP package, Engineering Sample.
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture
33
=
=
16-bit Digital Signal Controller
Flash program memory, 3.3V
Flash Memory Family FJ
Product Group
GP2
=
=
=
=
=
=
General Purpose family
General Purpose family
General Purpose family
General Purpose family
Motor Control family
GP3
GP5
GP7
MC5
MC7
Motor Control family
Pin Count
06
08
10
=
=
=
64-pin
80-pin
100-pin
Temperature Range
I
=
-40°C to +85°C (Industrial)
Package
Pattern
PT
PF
=
=
10x10 or 12x12 mm TQFP (Thin Quad Flatpack)
14x14 mm TQFP (Thin Quad Flatpack)
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES
= Engineering Sample
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 5
dsPIC33F
a wide variety of data addressing modes, together
provide the dsPIC33F Central Processing Unit (CPU)
with extensive mathematical processing capability.
Flexible and deterministic interrupt handling, coupled
with a powerful array of peripherals, renders the
dsPIC33F devices suitable for control applications.
Further, Direct Memory Access (DMA) enables
overhead-free transfer of data between several
peripherals and a dedicated DMA RAM. Reliable, field
programmable Flash program memory ensures
scalability of applications that use dsPIC33F devices.
2.0
dsPIC33F DEVICE FAMILY
OVERVIEW
The dsPIC33F device family employs a powerful 16-bit
architecture that seamlessly integrates the control
features of
computational capabilities of a Digital Signal Processor
(DSP). The resulting functionality is ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
a
Microcontroller (MCU) with the
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
Figure 2-1 shows a sample device block diagram
typical of the dsPIC33F product family.
FIGURE 2-1:
dsPIC33F DEVICE BLOCK DIAGRAM
X-Data Bus <16-bit>
Y-Data Bus <16-bit>
Barrel Shifter
Y AGU
X AGU
Data SRAM
up to
28 Kbytes
17 x 17 Multiplier
I/O Ports
Program Flash
Memory Data
Access
W Register
Array
16 x 16
ACCA<40>
ACCB<40>
DSP Engine
Memory
Mapped
Flash
Program
Memory
up to
Peripherals
Program Counter
<23 bits>
23
24
Divide Control
Instruction
Prefetch & Decode
256 Kbytes
16-bit ALU
Legend:
Dual Port
RAM
2 Kbytes
Status Register
MCU/DSP X-Data Path
DSP Y-Data Path
Address Path
DMA
Controller
DS70155C-page 6
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
FIGURE 3-1:
PROGRAM SPACE
MEMORY MAP
3.0
3.1
CPU ARCHITECTURE
Overview
Reset – GOTOInstruction
Reset – Target Address
Reserved
000000
000002
000004
The dsPIC33F CPU module has a 16-bit (data)
modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented, as illustrated in Figure 3-1,
varies from one device to another. A single-cycle
instruction prefetch mechanism is used to help
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
Osc. Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Vector
Reserved Vector
Reserved Vector
000014
Interrupt Vector Table
0000FE
000100
000104
Reserved
Alternate Vector Table
0001FE
000200
User Flash
Program Memory
(87296 x 24-bit)
02ABFE
02AC00
The dsPIC33F devices have sixteen 16-bit working
registers in the programmer’s model. Each of the
working registers can serve as a data, address or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
Reserved
7FFFFE
800000
The dsPIC33F instruction set has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. These two instruction classes are
seamlessly integrated into
a single CPU. The
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency.
3.1.1
DATA MEMORY OVERVIEW
Reserved
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device specific.
F7FFFE
F80000
F80016
F80018
Device Configuration
Registers (12 x 8-bit)
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
Reserved
FEFFFE
FF0000
FF0002
FF0004
Device ID (2 x 16-bit)
Reserved
The data space includes 2 Kbytes of DMA RAM, which
is primarily used for DMA data transfers, but may be
used as general purpose RAM.
FFFFFE
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 7
dsPIC33F
The dsPIC33F supports 16/16 and 32/16 divide
operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those 19
cycles without loss of data.
3.1.2
ADDRESSING MODES OVERVIEW
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. The
modulo addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU circular addressing can be used with any of
the MCU class of instructions. The X AGU also
supports bit-reversed addressing to greatly simplify
input or output data reordering for radix-2 FFT
algorithms.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
The CPU supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct and Register
Indirect Addressing modes. Each instruction is
associated with a predefined addressing mode group
depending upon its functional requirements. As many
as 6 addressing modes are supported for each
instruction.
3.1.5
INTERRUPT OVERVIEW
The dsPIC33F has a vectored exception scheme with
up to 5 sources of non-maskable traps and 67 interrupt
sources. Each interrupt source can be assigned to one
of seven priority levels.
3.1.6
FEATURES TO ENHANCE
COMPILER EFFICIENCY
For most instructions, the dsPIC33F is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
In addition to extensive DSP capability, the CPU
architecture possesses several features that lead to a
more efficient (code size and speed) C compiler.
1. For most instructions, three-parameter instruc-
tions can be supported, allowing A + B = C
operations to be executed in a single cycle.
3.1.3
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, 40-bit ALU, two 40-bit saturating
DSP ENGINE OVERVIEW
2. Instruction addressing modes are extremely
flexible to meet compiler needs.
a
3. The working register array consists of 16 x 16-bit
registers, each of which can act as data,
address or offset registers. One working register
(W15) operates as the software Stack Pointer
for interrupts and calls.
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value,
up to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM memory data space
be split for these instructions and linear for all others.
Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space.
4. Linear indirect access of all data space is
possible, plus the memory direct address range
is up to 8 Kbytes. This capability, together with
the addition of 16-bit direct address MOV-based
instructions, has provided a contiguous linear
addressing space.
5. Linear indirect access of 32K word (64 Kbyte)
pages within program space is possible, using
any working register via new table read and
write instructions.
6. Part of data space can be mapped into program
space, allowing constant data to be accessed as
if it were in data space.
3.1.4
SPECIAL MCU FEATURES
The dsPIC33F features a 17-bit by 17-bit, single-cycle
multiplier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed-sign multiplication, it also
achieves accurate results for special operations such
as (-1.0) x (-1.0).
DS70155C-page 8
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
W15 is the dedicated software Stack Pointer (SP). It is
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
3.2
Programmer’s Model
The programmer’s model, shown in Figure 3-2,
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (ACCA and ACCB),
Status Register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 is the W register for all instructions that
perform file register addressing.
W14 has been dedicated as a Stack Frame Pointer, as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
(reads) and post-increments for stack pushes (writes).
Some of these registers have a shadow register
associated with them (see the legend in Figure 3-2).
The shadow register is used as a temporary holding
register and can transfer its contents to or from its host
register upon some event occurring in a single cycle.
None of the shadow registers are accessible directly.
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte-wide data memory space accesses.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 9
dsPIC33F
FIGURE 3-2:
PROGRAMMER’S MODEL
Legend:
15
0
W0/WREG
W1
PUSH.S Shadow
DO Shadow
DIV and MUL
Result Registers
W2
W3
W4
MAC Operand
Registers
W5
W6
W7
Working Registers
W8
W9
MAC Address
Registers
W10
W11
W12/MAC Offset
W13/MAC Write Back
W14/Frame Pointer
W15*/Stack Pointer
*W15 and SPLIM not shadowed
SPLIM*
Stack Pointer Limit Register
0
15
39
ACCA
31
DSP
Accumulators
ACCB
22
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEAT Loop Counter
DO Loop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DO Loop Start Address
DO Loop End Address
22
0
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV
Z
C
IPL2 IPL1
Status Register
SRL
DS70155C-page 10
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
3.3.3
DATA SPACE WIDTH
3.3
Data Address Space
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
Figure 3-3 depicts a sample data space memory map
for the dsPIC33F device with 33 Kbytes of RAM.
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
3.3.4
DATA ALIGNMENT
To help maintain backward compatibility with
PICmicro® devices and improve data space memory
usage efficiency, the dsPIC33F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the Least
Significant bit (LSb) of any EA to determine which byte
to select.
3.3.1
X AND Y DATA SPACES
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses for X data space. The X read
data bus is the read data path for all instructions that
view data space as combined X and Y address space.
It is also the X data prefetch path for the dual operand
DSP instructions (MACclass).
As a consequence of this byte accessibility, all effective
address calculations are internally scaled. For
example, the core would recognize that Post-Modified
Register Indirect Addressing mode, [Ws++], will result
in a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported.
Should a misaligned read or write be attempted, a trap
will then be executed, allowing the system and/or user
to examine the machine state prior to execution of the
address Fault.
Both the X and Y data spaces support Modulo
Addressing for all instructions, subject to addressing
mode restrictions. Bit-Reversed Addressing is only
supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent (an example is shown in Figure 3-3)
and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words, though the
implemented memory locations vary from one device to
another.
3.3.2
DMA RAM
Every dsPIC33F device contains 2 Kbytes of DMA RAM
located at the end of Y data space. Memory locations in
the DMA RAM space are accessible simultaneously by
the CPU and the DMA Controller module. DMA RAM is
utilized by the DMA Controller to store data to be
transferred to various peripherals using DMA, as well as
data transferred from various peripherals using DMA.
When the CPU and the DMA Controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 11
dsPIC33F
FIGURE 3-3:
SAMPLE DATA SPACE MEMORY MAP
Most Significant Byte
Address
Least Significant Byte
Address
16 Bits
MSB
LSB
0x0000
0x0001
SFR Space
2-Kbyte
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8-Kbyte
X Data RAM (X)
Data Space
0x3FFF
0x4001
0x3FFE
0x4000
Y Data RAM (Y)
DMA RAM
0x77FF
0x7801
0x77FE
0x7800
0x7FFF
0x8001
0x7FFE
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
Note:
This data memory map is for the largest memory dsPIC33F device. Data memory maps for other
devices may vary.
DS70155C-page 12
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
3.4.3
SATURATION AND OVERFLOW
3.4
DSP Engine
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above and the user-configured control bits to
determine when to saturate and to what value to
saturate (a 40-bit or a 32-bit value).
The DSP engine consists of a high-speed, single-
cycle, 17-bit x 17-bit multiplier, a barrel shifter and a
40-bit adder/subtractor with two target accumulators,
round and saturation logic, all of which enable efficient
execution of computationally intensive DSP
algorithms. The 17-bit x 17-bit multiplier is also utilized
for MCU-based multiply instructions.
In addition to adder/subtractor saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG. This feature greatly simplifies basic
arithmetic operations on 32-bit or 40-bit data.
The rounding logic performs a conventional (biased) or
convergent (unbiased) data rounding function during
an accumulator write (store). The Round mode is user-
selectable. Rounding generates a 16-bit, 1.15 data
value, which is passed to the data space write
saturation logic. Data space write saturation ensures
that the data in the accumulator is written back
accurately even when rounding is performed. If
rounding is not indicated by the instruction, a truncated
1.15 data value is stored and the least significant word
is simply discarded.
A block diagram of the DSP engine is shown in
Figure 3-4.
3.4.1
17 x 17-BIT MULTIPLIER
The 17 x 17-bit multiplier is capable of signed or
unsigned operation. It can suitably scale its output to
support either 1.31 fractional (Q31) or 32-bit integer
results, thereby diminishing the need to manually
post-process multiplication results for fractional data.
3.4.2
40-BIT ACCUMULATORS
The data accumulators have a 40-bit adder/subtractor
with automatic sign extension logic. It can select one of
two accumulators (A or B) as its pre-accumulation
source and post-accumulation destination. For the ADD
and LAC instructions, the data to be accumulated or
loaded can be optionally scaled via the barrel shifter
prior to accumulation.
The adder/subtractor generates overflow status bits,
SA/SB and OA/OB, which are latched and reflected in
the Status register and can also optionally generate an
arithmetic error trap:
• Overflow from bit 39. This is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39. This is a
recoverable overflow. This bit (OA/OB) is set
whenever all the guard bits are not identical to
each other.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 13
dsPIC33F
FIGURE 3-4:
DSP ENGINE BLOCK DIAGRAM
S
a
40
40-bit Accumulator A
40-bit Accumulator B
t
u
r
40
16
Round
Logic
a
t
Saturate
Adder
e
Enable
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
Operand Latches
16
16
To/From W Array
DS70155C-page 14
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
• Indirect addressing of DMA RAM locations with or
without automatic post-increment
4.0
DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer)
and buffers or variables stored in RAM with minimal
CPU intervention. The DMA Controller can
automatically copy entire blocks of data, without the
user software having to read or write peripheral Special
Function Registers (SFRs) every time a peripheral
interrupt occurs. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM space.
• Peripheral Indirect Addressing – In some
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral
• One-Shot Block Transfers – Terminating DMA
transfer after one block transfer
• Continuous Block Transfers – Reloading DMA
RAM buffer start address after every block
transfer is complete
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately
The DMA Controller features eight identical data
transfer channels, each with its own set of control and
status registers. The UART, SPI, DCI, Input Capture,
Output Compare, ECAN™ and A/D modules can utilize
DMA. Each DMA channel can be configured to copy
data either from buffers stored in DMA RAM to
peripheral SFRs or from peripheral SFRs to buffers in
DMA RAM.
• Automatic or manual initiation of block transfers
• Each channel can select from 32 possible
sources of data sources or destinations
For each DMA channel, a DMA interrupt request is
generated when
a
block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled. Additionally, a DMA error trap
is generated in either of the following Fault conditions:
Each channel supports the following features:
• Word or byte-sized data transfers
• DMA RAM data write collision between the CPU
and a peripheral
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral
• Peripheral SFR data write collision between the
CPU and the DMA Controller
FIGURE 4-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA
Ready
Peripheral 3
DMA
Channels
DMA RAM
SRAM
PORT 1 PORT 2
CPU
DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU
DMA
CPU
DMA
Non-DMA
Ready
Peripheral
DMA
Ready
Peripheral 2
DMA
Ready
Peripheral 1
CPU
Note: CPU and DMA address buses are not shown for clarity.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 15
dsPIC33F
Each individual interrupt source has its own vector
address and can be individually enabled and prioritized
in user software. Each interrupt source also has its own
status flag. This independent control and monitoring of
the interrupt eliminates the need to poll various status
flags to determine the interrupt source
5.0
EXCEPTION PROCESSING
The dsPIC33F has four processor exceptions (traps)
and up to 67 sources of interrupts, which must be
arbitrated based on a priority scheme.
The processor core is responsible for reading the
Interrupt Vector Table (IVT) and transferring the
address contained in the interrupt vector to the
program counter.
Table 5-1 contains information about the interrupt
vector.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, interrupt-
on-change, etc. Control of these features remains within
the peripheral module, which generates the interrupt.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004) for ease of debugging.
The interrupt controller hardware pre-processes the
interrupts before they are presented to the CPU.
The interrupts and traps are enabled, prioritized and
controlled using centralized Special Function Registers.
The special DISI instruction can be used to disable
the processing of interrupts of priorities 6 and lower for
a certain number of instruction cycles, during which
the DISI bit remains set.
TABLE 5-1:
INTERRUPT VECTORS
Vector
Number
IVT Address
AIVT Address
Interrupt Source
8
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
INT0 – External Interrupt 0
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DMA0 – DMA Channel 0
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1E – SPI1 Error
SPI1D – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – A/D Converter 1
DMA1 – DMA Channel 1
Reserved
I2C1D – I2C1 Transfer Done
I2C1E – I2C1 Bus Collision Error
Reserved
Change Notification Interrupt
INT1 – External Interrupt 1
ADC2 – A/D Converter 2
IC7 – Input Capture 7
IC8 – Input Capture 8
DMA2 – DMA Channel 2
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
DS70155C-page 16
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 5-1:
INTERRUPT VECTORS (CONTINUED)
Vector
Number
IVT Address
AIVT Address
Interrupt Source
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
0x000192
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
SPI2E – SPI2 Error
SPI1D – SPI1 Transfer Done
C1RX – ECAN1 Receive Data Ready
C1 – CAN1 Event
DMA3 – DMA Channel 3
IC3 – Input Capture 3
IC4 – Input Capture 4
IC5 – Input Capture 5
IC6 – Input Capture 6
OC5 – Output Compare 5
OC6 – Output Compare 6
OC7 – Output Compare 7
OC8 – Output Compare 8
Reserved
DMA4 – DMA Channel 4
T6 – Timer6
T7 – Timer7
I2C2D – I2C2 Transfer Done
I2C2E – I2C2 Bus Collision Error
T8 – Timer8
T9 – Timer9
INT3 – External Interrupt 3
INT4 – External Interrupt 4
C2RX – ECAN2 Receive Data Ready
C2 – CAN2 Event
PWM – PWM Period Match
QEI – Position Counter Compare
DCIE – DCI Error
DCID – DCI Transfer Done
DMA5 – DMA Channel 5
RTC – Real-Time Clock
FLTA – MCPWM Fault A
FLTB – MCPWM Fault B
U1E – UART1 Error
U2E – UART2 Error
Reserved
DMA6 – DMA Channel 6
DMA7 – DMA Channel 7
C1TX – ECAN1 Transmit Data Request
Reserved (for devices marked “PS”)
C2TX – ECAN2 Transmit Data Request
Reserved (for devices marked “PS”)
Reserved
79
0x0000A2
0x0001A2
80-125
0x0000A4-
0x0000FE
0x0001A4-
0x0001FE
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 17
dsPIC33F
5.1
Interrupt Priority
5.3
Traps
Each interrupt source can be user-assigned to one of
8 priority levels, 0 through 7. Levels 7 and 1 represent
the highest and lowest maskable priorities,
respectively. A priority level of 0 disables the interrupt.
Traps can be considered as non-maskable, nestable
interrupts that adhere to a fixed priority structure.
Traps are intended to provide the user a means to
correct erroneous operation during debug and when
operating within the application. If the user does not
intend to take corrective action in the event of a trap
error condition, these vectors must be loaded with the
address of a software routine that will reset the device.
Otherwise, the trap vector is programmed with the
address of a service routine that will correct the trap
condition.
Since more than one interrupt request source may be
assigned to a user-specified priority level, a means is
provided to assign priority within a given level. This
method is called “Natural Order Priority”.
The Natural Order Priority of an interrupt is numerically
identical to its vector number. The Natural Order
Priority scheme has 0 as the highest priority and 74 as
the lowest priority.
The dsPIC33F has four implemented sources of
non-maskable traps:
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low Natural Order Priority, thereby providing much
flexibility in designing applications that use a large
number of peripherals.
• Oscillator Failure Trap
• Address Error Trap
• Stack Error Trap
• Math Error Trap
• DMA Trap
Many of these trap conditions can only be detected
when they happen. Consequently, the instruction that
caused the trap is allowed to complete before
exception processing begins. Therefore, the user may
have to correct the action of the instruction that
caused the trap.
5.2
Interrupt Nesting
Interrupts, by default, are nestable. Any ISR that is in
progress may be interrupted by another source of
interrupt with a higher user-assigned priority level.
Interrupt nesting may be optionally disabled by
setting the NSTDIS control bit (INTCON1<15>).
When the NSTDIS control bit is set, all interrupts in
progress will force the CPU priority to level 7 by
setting IPL<2:0> = 111. This action will effectively
mask all other sources of interrupt until a RETFIE
instruction is executed. When interrupt nesting is
disabled, the user-assigned interrupt priority levels
will have no effect, except to resolve conflicts
between simultaneous pending interrupts.
Each trap source has a fixed priority as defined by its
position in the IVT. An oscillator failure trap has the
highest priority, while an arithmetic error trap has the
lowest priority.
Table 5-2 contains information about the trap vector.
5.4
Generating a Software Interrupt
Any available interrupt can be manually generated by
user software (even if the corresponding peripheral is
disabled), simply by enabling the interrupt and then
setting the interrupt flag bit when required.
The IPL<2:0> bits become read-only when interrupt
nesting is disabled. This prevents the user software
from setting IPL<2:0> to a lower value, which would
effectively re-enable interrupt nesting.
TABLE 5-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
Reserved
0
1
2
3
4
5
6
7
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
Oscillator Failure
Address Error
Stack Error
Math Error
DMA Error Trap
Reserved
Reserved
DS70155C-page 18
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. The input to
the PLL can be in the range of 1.6 MHz to 16 MHz, and
the PLL Phase Detector Input Divider, PLL Multiplier
Ratio and PLL Voltage Controlled Oscillator (VCO) can
be individually configured by user software to generate
output frequencies in the range of 25 MHz to 160 MHz.
6.0
SYSTEM INTEGRATION
System management services provided by the
dsPIC33F device family include:
• Control of clock options and oscillators
• Power-on Reset
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with RC oscillator
• Fail-Safe Clock Monitor
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) is divided by 4 to
generate the device instruction clock (FCY). FCY
defines the operating speed of the device, and speeds
up to 40 MHz are supported by the dsPIC33F
architecture.
• Reset by multiple sources
6.1
Clock Options and Oscillators
There are 7 clock options provided by the dsPIC33F:
• FRC Oscillator
The dsPIC33F oscillator system provides:
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• LPRC Oscillator
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
• The internal FRC oscillator can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
The FRC (Fast RC) internal oscillator runs at a nominal
frequency of 7.37 MHz. The user software can tune the
FRC frequency. User software can specify a factor by
which this clock frequency is scaled.
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
The primary oscillator can use one of the following as
its clock source:
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
1. XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
• A Clock Control register (OSCCON)
• Nonvolatile configuration bits for main oscillator
selection.
2. HS (High-Speed Crystal): Crystals in the range
of 10 MHz to 40 MHz. The crystal is connected
to the OSC1 and OSC2 pins.
A simplified block diagram of the oscillator system is
shown in Figure 6-1.
3. EC (External Clock): External clock signal in the
range of 0.8 MHz to 64 MHz. The external clock
signal is directly applied to the OSC1 pin.
The secondary (LP) oscillator is designed for low power
and uses a 32 kHz crystal or ceramic resonator. The LP
oscillator uses the SOSCI and SOSCO pins.
The LPRC (Low-Power RC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. Another scaled
reference clock is used by the Watchdog Timer (WDT)
and Fail-Safe Clock Monitor (FSCM).
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 19
dsPIC33F
FIGURE 6-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
OSC1
OSC2
PLL
Primary
Oscillator
Module
Primary Osc
Internal Fast
RC (FRC)
Oscillator
Clock
Switching
and
Control
Block
FCY
FOSC
Secondary Osc
Divide by 4
Secondary
Oscillator
32 kHz
SOSCO
SOSCI
Internal Low-Power
RC (LPRC)
Oscillator
To Timer1
6.2
Power-on Reset
6.4
Watchdog Timer (WDT)
When a supply voltage is applied to the device, a
Power-on Reset is generated. A new Power-on Reset
event is generated if the supply voltage falls below the
device threshold voltage (VPOR). An internal POR
pulse is generated when the rising supply voltage
crosses the POR circuit threshold voltage.
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off the on-chip LPRC oscillator, requiring no external
component. The WDT continues to operate even if the
main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled”
either through a configuration bit (FWDTEN) in the
Configuration register, or through an SFR bit
(SWDTEN).
6.3
Oscillator Start-up Timer/Stabilizer
(OST)
An Oscillator Start-up Timer (OST) is included to
ensure that a crystal oscillator (or ceramic resonator)
has started and stabilized. The OST is a simple, 10-bit
counter that counts 1024 TOSC cycles before releasing
the oscillator clock to the rest of the system. The time-
out period is designated as TOST. The TOST time is
involved every time the oscillator has to restart (i.e., on
Power-on Reset (POR) and wake-up from Sleep). The
Oscillator Start-up Timer is applied to the LP oscillator,
XT and HS modes (upon wake-up from Sleep, POR
and BOR) for the primary oscillator.
Any device programmer capable of programming
dsPIC® DSC devices (such as Microchip’s MPLAB®
PM3 Programmer) allows programming of this and
other configuration bits to the desired state. If enabled,
the WDT increments until it overflows or “times out”. A
WDT time-out forces a device Reset (except during
Sleep).
DS70155C-page 20
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
6.5
Fail-Safe Clock Monitor (FSCM)
6.6
Reset System
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
The Reset system combines all Reset sources and
controls the device Master Reset signal.
Device Reset sources include:
• POR: Power-on Reset
• BOR: Brown-out Reset
• SWR: RESETInstruction
• EXTR: MCLR Reset
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The application
program then can either attempt to restart the oscillator,
or execute a controlled shutdown. The trap can be
treated as a warm Reset by simply loading the Reset
address into the oscillator fail trap vector.
• WDTR: Watchdog Timer Time-out Reset
• TRAPR: Trap Conflict
• IOPUWR: Attempted execution of an Illegal
Opcode, or Indirect Addressing, using an
Uninitialized W register
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 21
dsPIC33F
The processor exits (wakes up) from Sleep on one of
these events:
7.0
DEVICE POWER MANAGEMENT
Power management services provided by the
dsPIC33F devices include:
• Any interrupt source that is individually enabled
• Any form of device Reset
• Real-Time Clock Source Switching
• Power-Saving Modes
• A WDT time-out
7.2.2
IDLE MODE
7.1
Real-Time Clock Source Switching
When the device enters Idle mode:
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register
controls the clock switching and reflects system clock
related status bits. To reduce power consumption, the
user can switch to a slower clock source.
• CPU stops executing instructions
• WDT is automatically cleared
• System clock source remains active
• Peripheral modules, by default, continue to
operate normally from the system clock source
• Peripherals, optionally, can be shut down in Idle
mode using their ‘stop-in-idle’ control bit.
• If the WDT or FSCM is enabled, the LPRC also
remains active
7.2
Power-Saving Modes
The dsPIC33F devices have two reduced power
modes that can be entered through execution of the
PWRSAVinstruction.
The processor wakes from Idle mode on these events:
• Any interrupt that is individually enabled
• Any source of device Reset
• A WDT time-out
• Sleep Mode: The CPU, system clock source and
any peripherals that operate on the system clock
source are disabled. This is the lowest power
mode of the device.
Upon wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately
starting with the instruction following the PWRSAV
instruction, or the first instruction in the Interrupt
Service Routine (ISR).
• Idle Mode: The CPU is disabled but the system
clock source continues to operate. Peripherals
continue to operate but can optionally be disabled.
• Doze Mode: The CPU clock is temporarily slowed
down relative to the peripheral clock by a
user-selectable factor.
7.2.3
DOZE MODE
The Doze mode provides the user software the ability
to temporarily reduce the processor instruction cycle
frequency relative to the peripheral frequency. Clock
frequency ratios of 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64
and 1:128 are supported.
These modes provide an effective way to reduce power
consumption during periods when the CPU is not in use.
7.2.1
SLEEP MODE
When the device enters Sleep mode:
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps bit rate based on this device operating speed.
If the device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module will continue to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
• System clock source is shut down. If an on-chip
oscillator is used, it is turned off.
• Device current consumption is at minimum
provided that no I/O pin is sourcing current.
• Fail-Safe Clock Monitor (FSCM) does not operate
during Sleep mode because the system clock
source is disabled.
This feature further reduces the power consumption
during periods where relatively less CPU activity is
required.
• LPRC clock continues to run in Sleep mode if the
WDT is enabled.
• BOR circuit, if enabled, remains operative during
Sleep mode
When the device is operating in Doze mode, the
hardware ensures that there is no loss of
synchronization between peripheral events and SFR
accesses by the CPU.
• WDT, if enabled, is automatically cleared prior to
entering Sleep mode.
• Some peripherals may continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, or
peripherals that use an external clock input. Any
peripheral that is operating on the system clock
source is disabled in Sleep mode.
DS70155C-page 22
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
•
1 LSB max Integral Nonlinearity (INL)
(3.3V 10%)
8.0
dsPIC33F PERIPHERALS
The Digital Signal Controller (DSC) family of 16-bit
DSC devices provides the integrated functionality of
many peripherals. Specific peripheral functions
include:
• Up to 4 on-chip sample and hold amplifiers in
each A/D
- Enables simultaneous sampling of 2, 4 or
8 analog inputs
• Analog-to-Digital Converters
- 10-bit High-Speed A/D Converter
- 12-bit High-Resolution A/D Converter
• General Purpose 16-Bit Timers
• Motor Control PWM module
• Quadrature Encoder Interface module
• Input Capture module
• Automated channel scanning
• Single-supply operation: 3.0-3.6V
• 2.2 Msps or 1 Msps sampling rate at 3.0V
• Ability to convert during CPU Sleep and Idle
modes
• Conversion start can be manual or synchronized
with 1 of 4 trigger sources (automatic, Timer3,
external interrupt, PWM period match)
• Output Compare/PWM module
• Data Converter Interface
• A/D can use DMA for buffer storage
• Lower and upper half of buffer can be filled on
alternate conversions
• Serial Peripheral Interface (SPI™) module
• UART module
• I2C™ module
8.2
General Purpose Timer Modules
• Controller Area Network (CAN) module
• I/O pins
The General Purpose (GP) timer modules provide the
time base elements for input capture and output
compare/PWM. They can be configured for Real-Time
Clock operation as well as various timer/counter
modes. The timer modes count pulses of the internal
time base, whereas counter modes count external
pulses that appear on the timer clock pin.
8.1
Analog-to-Digital Converters
The Analog-to-Digital (A/D) Converters provide up to
32 analog inputs with both single-ended and differential
inputs. These modules offer on-board sample and hold
circuitry.
The dsPIC33F device supports up to nine 16-bit timers
(Timer1 through Timer9). Eight of the 16-bit timers can
be configured as four 32-bit timers (Timer2/3, Timer4/5,
Timer6/7 and Timer8/9). Each timer has several
selectable operating modes.
To minimize control loop errors due to finite update
times (conversion plus computations), a high-speed
low-latency ADC is required.
In addition, several hardware features have been
included in the peripheral interface to improve real-time
performance in a typical DSP-based application.
8.2.1
TIMER1
The Timer1 module (Figure 8-1) is a 16-bit timer that can
serve as the time counter for an asynchronous Real-
Time Clock, or operate as a free-running interval timer/
counter. The 16-bit timer has the following modes:
• Result alignment options
• Automated sampling
• Automated channel scanning
• Dual port data buffer
• 16-Bit Timer
• External conversion start control
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
The A/D Converter is available in either of the following
configurations:
Further, the following operational characteristics are
supported:
• 10-bit, 1.1 Msps A/D module:
- 2.2 Msps A/D conversion using 2 channels
• 12-bit, 500 ksps A/D module:
• Timer gated by external pulse
• Selectable prescaler settings
- 1 Msps A/D conversion using 2 channels
• Timer operation during CPU Idle and Sleep modes
Key features of the A/D module include:
• Interrupt on 16-Bit Period register match or falling
edge of external gate signal
• 10-bit or 12-bit resolution
• Unipolar differential sample/hold amplifiers
• Up to 32 input channels
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:
• Selectable voltage reference sources
- External VREF+ and VREF- pins available
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
•
1 LSB max Differential Nonlinearity (DNL)
(3.3V 10%)
• Real-Time Clock interrupts
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 23
dsPIC33F
FIGURE 8-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
PR1
Comparator x 16
TMR1
Equal
Reset
TSYNC
1
Sync
0
0
1
T1IF
Event Flag
Q
Q
D
TGATE
CK
TGATE
TCKPS<1:0>
2
TON
SOSCO/
T1CK
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
LPOSCEN
SOSCI
TCY
8.2.2
TIMER2/3
8.2.3
TIMER4/5, TIMER6/7, TIMER8/9
The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable
operating modes. These timers are used by other
peripheral modules, such as:
The Timer4/5, Timer6/7 and Timer8/9 modules are
similar in operation to the Timer2/3 module. Differences
include:
• These modules do not support the ADC event
trigger feature
• Input Capture
• Output Compare/Simple PWM
• These modules can not be used by other
peripheral modules, such as input capture and
output compare
Timer2/3 has the following modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with Timer and Synchronous Counter
modes
8.3
Motor Control PWM Module
The Motor Control PWM (MCPWM) module simplifies
the task of generating multiple, synchronized pulse-
width modulated outputs. In particular, the following
power and motion control applications are supported:
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
Further, the following operational characteristics are
supported:
• Three-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• ADC conversion start trigger
• 32-bit timer gated by external pulse
• Selectable prescaler settings
• Uninterrupted Power Supply (UPS)
• Timer counter operation during Idle and Sleep
modes
• Interrupt on a 32-Bit Period register match
• Timer2/3 can use DMA for buffer storage
DS70155C-page 24
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
The PWM module has the following features:
8.3.1
PWM TIME BASE
• Dedicated time base supports TCY/2 PWM edge
resolution
The PWM time base is provided by a 15-bit timer with
a prescaler and postscaler. The PWM time base can be
configured for four different modes of operation:
• Two output pins (pair) for each PWM generator
• Complementary or independent operation for
each output pin pair
• Free-Running mode
• Single-Shot mode
• Hardware dead-time generators for
Complementary mode
• Continuous Up/Down Count mode
• Continuous Up/Down Count mode with interrupts
for double updates
• Output pin polarity defined by nonvolatile device
configuration bits
The Up/Down Counting modes support center-aligned
PWM generation. The Single-Shot mode allows the
PWM module to support pulse control of certain
Electronically Commutated Motors (ECMs).
• Multiple output modes:
- Edge-Aligned mode
- Center-Aligned mode
- Center-Aligned mode with double updates
- Single Event mode
Table 8-1 lists the frequencies and resolutions that can
be attained as a function of the dsPIC33F device
instruction cycle frequency.
• Manual override register for PWM output pins
• Hardware Fault input pins with programmable
function
• Trigger for synchronizing A/D samples and
conversions to PWM timing
• Each output pin associated with the PWM can be
individually enabled
TABLE 8-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS, 1:1 PRESCALER
TCY (FCY)
PTPER Value
PWM Resolution
PWM Frequency*
25 ns (40 MHz)
25 ns (40 MHz)
50 ns (20 MHz)
50 ns (20 MHz)
100 ns (10 MHz)
100 ns (10 MHz)
200 ns (5 MHz)
200 ns (5 MHz)
0x7FFF
0x03FF
0x7FFF
0x01FF
0x7FFF
0x00FF
0x7FFF
0x007F
16 bits
11 bits
16 bits
10 bits
16 bits
9 bits
1220 Hz
39.1 kHz
610 Hz
39.1 kHz
305 Hz
39.1 kHz
153 Hz
16 bits
8 bits
39.1 kHz
* PWM frequencies will be 1/2 the value indicated for center-aligned operation.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 25
dsPIC33F
FIGURE 8-2:
8-OUTPUT PWM MODULE BLOCK DIAGRAM
PWMCON1
PWMCON2
PWM Enable and Mode SFRs
Dead-Time Control SFRs
DTCON1
DTCON2
FLTACON
FLTBCON
OVDCON
Fault Pin Control SFRs
PWM Manual
Control SFR
PWM Generator #4
PDC4 Buffer
PDC4
Comparator
PWM4H
PWM4L
Channel 4 Dead-Time
Generator and
Override Logic
PWM Generator
#3
PWM3H
PWM3L
PTMR
Channel 3 Dead-Time
Generator and
Override Logic
Output
Driver
Block
Comparator
PWM Generator
#2
PWM2H
PWM2L
Channel 2 Dead-Time
Generator and
PTPER
Override Logic
PWM Generator
#1
Channel 1 Dead-Time
Generator and
PWM1H
PWM1L
Override Logic
PTPER Buffer
PTCON
FLTA
FLTB
Special Event
Postscaler
Comparator
SEVTCMP
Special Event Trigger
SEVTDIR
PTDIR
PWM Time Base
Note:
Details of PWM Generator #1, #2 and #3 are not shown for clarity.
DS70155C-page 26
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
increment when the shaft is rotating one direction and
decrement when the shaft is rotating in the other
direction.
8.4
Quadrature Encoder Interface
(QEI) Module
Quadrature encoders (also referred to as incremental
encoders or optical encoders) are used in position and
speed detection of rotating motion systems.
Quadrature encoders enable closed-loop control of
many motor control applications, such as Switched
Reluctance (SR) Motor and AC Induction Motor
(ACIM).
The QEI module (Figure 8-3) includes:
• Three input pins for two phase signals and index
pulse
• Programmable digital noise filters on inputs
• Quadrature decoder providing counter pulses and
count direction
Typically, three outputs termed, Phase A, Phase B and
INDEX, provide information that can be decoded to
provide information on the movement of the motor
shaft, including distance and direction.
• 16-bit up/down position counter
• Count direction status
• x2 and x4 count resolution
• Two modes of Position Counter Reset
• General Purpose16-Bit Timer/Counter mode
• Interrupts generated by QEI or counter events
A quadrature decoder captures the phase signals and
index pulse and converts the information into a numeric
count of the position pulses. Generally, the count will
FIGURE 8-3:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
2
Sleep Input
TQCS
TCY
0
1
Synchronize
Det
Prescaler
1, 8, 64, 256
1
0
QEIM<2:0>
QEIIF
Event
Flag
D
Q
Q
TQGATE
CK
16-Bit Up/Down Counter
(POSCNT)
Programmable
Digital Filter
2
QEA
Reset
Quadrature
Encoder
Interface Logic
UPDN_SRC
Comparator/
Zero Detect
Equal
QEICON<11>
0
3
QEIM<2:0>
Mode Select
1
Max Count Register
(MAXCNT)
Programmable
Digital Filter
QEB
Programmable
Digital Filter
INDX
3
PCDOUT
Existing Pin Logic
0
1
UPDN
Up/Down
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 27
dsPIC33F
The dsPIC33F device may have up to eight output
compare channels, designated OC1 through OC8.
Refer to the specific device data sheet for the number
of channels available in a particular device. All output
compare channels are functionally identical.
8.5
Input Capture Module
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33F devices support up to eight input
capture channels.
Each output compare channel can use one of two
selectable time bases. The time base is selected using
the OCTSEL bit (OCxCON<3>). An ‘x’ in the pin,
register or bit name denotes the specific output
compare channel. Refer to the device data sheet for the
specific timers that can be used with each output
compare channel number.
The input capture module captures the 16-bit value of
the selected time base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1. Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
Each output compare module has the following modes
of operation:
- Capture timer value on every rising edge of
input at ICx pin
• Single Compare Match mode
• Dual Compare Match mode generating
- Single Output Pulse
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes
- Continuous Output Pulses
- Capture timer value on every 4th rising
edge of input at ICx pin
• Simple Pulse-Width Modulation mode
- With Fault Protection Input
- Capture timer value on every 16th rising
edge of input at ICx pin
- Without Fault Protection Input
Output compare channels, OC1 and OC2, support
DMA data transfers.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or an
external clock.
8.7
Data Converter Interface Module
Other operational features include:
The dsPIC33F Data Converter Interface (DCI) module
allows simple interfacing to devices such as audio
coder/decoders (codecs), A/D Converters and D/A
Converters.
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
The following interfaces are supported:
• 4-word FIFO buffer for capture values
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Inter-IC Sound (I2S) Interface
• Input capture can also be used to provide
additional sources of external interrupts.
• AC-Link (AC’97) Compliant mode
Input capture channels IC1 and IC2 support DMA data
transfers.
Many codecs intended for use in audio applications
support sampling rates between 8 kHz and 48 kHz and
use one of the interface protocols listed above. The
DCI automatically handles the interface timing
associated with these codecs. No overhead from the
CPU is required until the requested amount of data has
been transmitted and/or received by the DCI. Up to four
data words can be transferred between CPU interrupts.
8.6
Output Compare/PWM Module
The output compare module features are quite useful
in applications that require controlled timing pulses or
PWM modulated pulse streams.
The output compare module has the ability to compare
the value of a selected time base with the value of one
or two compare registers (depending on the operation
mode selected). Furthermore, it has the ability to
generate a single output pulse, or a repetitive
sequence of output pulses, on a compare match event.
Like most dsPIC33F peripherals, it also has the ability
to generate interrupts on compare match events.
The data word length for the DCI is programmable up
to 16 bits to match the data size of the dsPIC33F CPU.
However, many codecs have data word sizes greater
than 16 bits. Long data word lengths can be supported
by the DCI. The DCI is configured to transmit/receive
the long word in multiple 16-bit time slots. This
operation is transparent to the user and the long data
word is stored in consecutive register locations.
DS70155C-page 28
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Figure 8-4 is a block diagram of the DCI module. The
DCI can support up to 16 time slots in a data frame for
a maximum frame size of 256 bits. There are control
bits for each time slot in the data frame that determine
whether the DCI will transmit/receive during the time
slot. The DCI module supports DMA data transfers.
FIGURE 8-4:
DCI MODULE BLOCK DIAGRAM
BCG Control Bits
CSCKD
COFSD
Sample Rate
Generator
CSCK
COFS
FOSC/4
Word Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
Frame
Synchronization
Generator
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
0
Transmit Buffer
Registers w/Shadow
DCI Shift Register
CSDI
CSDO
A series of 8 or 16 clock pulses (depending on mode)
shift out the 8 or 16 bits (depending on whether a byte
or word is being transferred) and simultaneously shift in
8 or 16 bits of data from the SDI pin. An interrupt is
generated when the transfer is complete.
8.8
SPI™ Module
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface for communicating with
other peripheral or microcontroller devices such as
serial EEPROMs, shift registers, display drivers, A/D
Converters, etc. It is compatible with Motorola® SPI and
SIOP interfaces.
Slave select synchronization allows selective enabling
of SPI slave devices, which is particularly useful when
a single master is connected to multiple slaves.
This SPI module includes all SPI modes. A Frame
Synchronization mode is also included for support of
voice band codecs.
The SPI1 and SPI2 modules support DMA data
transfers.
Four pins make up the serial interface: SDI, Serial Data
Input; SDO, Serial Data Output; SCK, Shift Clock Input
or Output; SS, Active-Low Slave Select, which also
serves as the FSYNC (Frame Synchronization Pulse).
A device set up as an SPI master provides the serial
communication clock signal on its SCK pin.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 29
dsPIC33F
In I2C mode, pin SCL is clock and pin SDA is data. The
module will override the data direction bits for these pins.
8.9
UART Module
The UART is a full-duplex asynchronous system that
can communicate with peripheral devices, such as
personal computers, RS-232 and RS-485 interfaces.
8.11 Controller Area Network (CAN)
Module
The dsPIC33F devices have one or more UARTs.
The key features of the UART module are:
The Controller Area Network (CAN) module is a serial
interface useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy environments.
• Full-duplex operation with 8 or 9-bit data
• Even, odd or no parity options (for 8-bit data)
• One or two Stop bits
• Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
The CAN module is a communication controller
implementing the CAN 2.0 A/B protocol, as defined in
the BOSCH specification. The module supports
CAN 1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B
Active versions of the protocol. Details of these protocols
can be found in the BOSCH CAN specification.
• Baud rates range from up to 10 Mbps and down to
38 Hz at 40 MIPS
• 4-character deep transmit data buffer
• 4-character deep receive data buffer
The CAN module features:
• Parity, framing and buffer overrun error detection
• Full IrDA® support, including hardware encoding
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
and decoding of IrDA® messages
• Standard and extended data frames
• Data lengths of 0-8 bytes
• LIN bus support
- Auto wake-up from Sleep or Idle mode on
Start bit detect
• Programmable bit rate up to 1 Mbit/sec
• Automatic response to remote frames
• Up to 16 receive buffers in DMA RAM
• FIFO Buffer mode (up to 64 messages deep)
- Auto-baud detection
- Break character support
• Support for interrupt on address detect (9th bit = 1)
• Separate transmit and receive interrupts
- On transmission of 1 or 4 characters
- On reception of 1, 3 and 4 characters
• Loopback mode for diagnostics
• 16 full (standard/extended identifier) acceptance
filters
• 3 full acceptance filter masks
• Up to 8 transmit buffers in DMA RAM
• DMA can be used for transmission and reception
The UART1 and UART2 modules support DMA data
transfers.
• Programmable wake-up functionality with
integrated low-pass filter
2
• Programmable Loopback mode supports self-test
operation
8.10 I C™ Module
The I2C module is a synchronous serial interface, useful
for communicating with other peripheral or
microcontroller devices. These peripheral devices may
be serial EEPROMs, shift registers, display drivers, A/D
Converters, etc.
The Inter-Integrated Circuit (I2C) module offers full
hardware support for both slave and multi-master
operations.
The key features of the I2C module are:
• I2C slave operation supports 7 and 10-bit address
• I2C master operation supports 7 and 10-bit address
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (serial clock stretching)
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization
• Low-power Sleep and Idle mode
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
• I2C supports multi-master operation; detects bus
collision and will arbitrate accordingly
• Slew rate control for 100 kHz and 400 kHz bus speeds
DS70155C-page 30
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
The I/O pins have the following features:
8.12 I/O Pins
• Schmitt Trigger input
• CMOS output drivers
• Weak internal pull-up
Some pins for the I/O pin functions are multiplexed with
an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
All I/O pins configured as digital inputs can accept 5V
signals. This provides a degree of compatibility with
external signals of different voltage levels. However, all
digital outputs and analog pins can only generate
voltage levels up to 3.6V.
All I/O port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register determines whether the pin is an input or an
output. The Port Data Latch register provides latched
output data for the I/O pins. The Port register provides
visibility of the logic state of the I/O pins. Reading the
Port register provides the I/O pin logic state, while
writes to the Port register write the data to the Port Data
Latch register.
The input change notification module gives dsPIC33F
devices the ability to generate interrupt requests to the
processor in response to a change of state on selected
input pins. This module is capable of detecting input
changes of state, even in Sleep mode, when the clocks
are disabled. There are up to 24 external signals (CN0
through CN23) that can be selected (enabled) for
generating an interrupt request on a change of state.
Each of the CN pins also has an optional weak pull-up
feature.
I/O port pins have latch bits (Port Data Latch register).
This register, when read, yields the contents of the I/O
latch and when written, modifies the contents of the I/O
latch, thus modifying the value driven out on a pin if the
corresponding Data Direction register bit is configured
for output. This can be used in read-modify-write
instructions that allow the user to modify the contents
of the Port Data Latch register, regardless of the status
of the corresponding pins.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 31
dsPIC33F
9.2.1
MULTI-CYCLE INSTRUCTIONS
9.0
dsPIC33F INSTRUCTION SET
As the instruction summary tables show, most
instructions execute in a single cycle with the following
exceptions:
9.1
Introduction
The dsPIC33F instruction set provides a broad suite of
instructions which supports traditional microcontroller
applications, and a class of instructions which supports
math-intensive applications. Since almost all of the
functionality of the PICmicro® MCU instruction set has
been maintained, this hybrid instruction set allows a
friendly DSP migration path for users already familiar
with the PICmicro microcontroller.
• Instructions DO, MOV.D, POP.D, PUSH.D,
TBLRDH, TBLRDL, TBLWTHand TBLWTL
require 2 cycles to execute.
• Instructions DIVF, DIV.S, DIV.U are single-
cycle instructions, which should be executed
18 consecutive times as the target REPEAT
instruction.
• Instructions that change the program counter also
require 2 cycles to execute, with the extra cycle
executed as a NOP. Skip instructions, which skip
over a 2-word instruction, require 3 instruction
cycles to execute with 2 cycles executed as a
NOP.
9.2
Instruction Set Overview
The dsPIC33F instruction set contains 84 instructions
which can be grouped into the ten functional categories
shown in Table 9-1. Table 9-2 defines the symbols
used in the instruction summary tables, Table 9-3
through Table 9-12. These tables define the syntax,
description, storage and execution requirements
for each instruction. Storage requirements are repre-
sented in 24-bit instruction words and execution
requirements are represented in instruction cycles.
Most instructions have several different addressing
modes and execution flows which require different
instruction variants. For instance, there are six unique
ADD instructions and each instruction variant has its
own instruction encoding.
• The RETFIE, RETLW and RETURN are special
cases of instructions that change the program
counter. These execute in 3 cycles unless an
exception is pending, and then they execute in
2 cycles.
Note:
Instructions that access program memory
as data, using Program Space Visibility,
incur some cycle count overhead.
9.2.2
MULTI-WORD INSTRUCTIONS
As the instruction summary tables show, almost all
instructions consume one instruction word (24 bits),
with the exception of the CALL, DO and GOTO
instructions, which are flow instructions listed in
Table 9-9. These instructions require two words of
memory because their opcodes embed large literal
operands.
TABLE 9-1:
dsPIC33F INSTRUCTION
GROUPS
Functional Group
Summary Table
Move Instructions
Table 9-3
Table 9-4
Table 9-5
Table 9-6
Table 9-7
Table 9-8
Table 9-9
Table 9-10
Table 9-11
Table 9-12
Math Instructions
Logic Instructions
Rotate/Shift Instructions
Bit Instructions
Compare/Skip Instructions
Program Flow Instructions
Shadow/Stack Instructions
Control Instructions
DSP Instructions
DS70155C-page 32
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 9-2:
Symbol
SYMBOLS USED IN SUMMARY TABLES
Description
#
Literal operand designation
Acc
Accumulator A or Accumulator B
AWB
Accumulator Write Back
bit4
Expr
f
4-bit wide bit position (0:15)
Absolute address, label or expression (resolved by the linker)
File register address
lit1
lit4
lit5
lit8
lit10
lit14
lit16
lit23
Slit4
Slit6
Slit10
Slit16
TOS
1-bit literal (0:1)
4-bit literal (0:15)
5-bit literal (0:31)
8-bit literal (0:255)
10-bit literal (0:255 for Byte mode, 0:1023 for Word mode)
14-bit literal (0:16383)
16-bit literal (0:65535)
23-bit literal (0:8388607)
Signed 4-bit literal (-8:7)
Signed 6-bit literal (-16:16)
Signed 10-bit literal (-512:511)
Signed 16-bit literal (-32768:32767)
Top-of-Stack
Wb
Base working register
Wd
Destination working register (direct and indirect addressing)
Working register divide pair (dividend, divisor)
Working register multiplier pair (same source register)
Working register multiplier pair (different source registers)
Both source and destination working register (direct addressing)
Destination working register (direct addressing)
Source working register (direct addressing)
Default working register
Wm, Wn
Wm*Wm
Wm*Wn
Wn
Wnd
Wns
WREG
Ws
Source working register (direct and indirect addressing)
Source addressing mode and working register for X data bus prefetch
Destination working register for X data bus prefetch
Source addressing mode and working register for Y data bus prefetch
Destination working register for Y data bus prefetch
Wx
Wxd
Wy
Wyd
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 33
dsPIC33F
TABLE 9-3:
Assembly
MOVE INSTRUCTIONS
Syntax
Description
Swap Wns and Wnd
Words
Cycles
EXCH
MOV
Wns,Wnd
f {,WREG}
WREG,f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
2
2
Move f to destination
MOV
Move WREG to f
MOV
f,Wnd
Move f to Wnd
MOV
Wns,f
Move Wns to f
MOV.b
MOV
#lit8,Wnd
#lit16,Wnd
[Ws+Slit10],Wnd
Wns,[Wd+Slit10]
Ws,Wd
Move 8-bit literal to Wnd
Move 16-bit literal to Wnd
Move [Ws + signed 10-bit offset] to Wnd
Move Wns to [Wd + signed 10-bit offset]
Move Ws to Wd
MOV
MOV
MOV
MOV.D
MOV.D
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
Ws,Wnd
Move double Ws to Wnd:Wnd + 1
Move double Wns:Wns + 1 to Wd
Wn = byte or nibble swap Wn
Read high program word to Wd
Read low program word to Wd
Write Ws to high program word
Write Ws to low program word
Wns,Wd
Wn
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
Note:
Table 9-3 through Table 9-12 present the base instruction syntax for the dsPIC33F. These instructions do not
include all of the available addressing modes. For example, some instructions show the Byte Addressing
mode and others do not.
DS70155C-page 34
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 9-4:
MATH INSTRUCTIONS
Assembly Syntax
Description
Destination = f + WREG
Words
Cycles
ADD
f {,WREG}
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADD
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
Wn
Wn = lit10 + Wn
ADD
Wd = Wb + lit5
1
ADD
Wd = Wb + Ws
1
ADDC
ADDC
ADDC
ADDC
DAW.B
DEC
Destination = f + WREG + (C)
Wn = lit10 + Wn + (C)
1
1
Wd = Wb + lit5 + (C)
1
Wd = Wb + Ws + (C)
1
Wn = decimal adjust Wn
Destination = f – 1
1
f {,WREG}
Ws,Wd
1
DEC
Wd = Ws – 1
1
DEC2
DEC2
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
INC
f {,WREG}
Ws,Wd
Destination = f – 2
1
Wd = Ws – 2
1
Wm,Wn
Signed 16/16-bit integer divide*
Signed 32/16-bit integer divide*
Unsigned 16/16-bit integer divide*
Unsigned 32/16-bit integer divide*
Signed 16/16-bit fractional divide*
Destination = f + 1
18
18
18
18
18
1
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
f {,WREG}
Ws,Wd
INC
Wd = Ws + 1
1
INC2
INC2
MUL
f {,WREG}
Ws,Wd
Destination = f + 2
1
Wd = Ws + 2
1
f
W3:W2 = f * WREG
1
MUL.SS
MUL.SU
MUL.SU
MUL.US
MUL.UU
MUL.UU
SE
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,Ws,Wnd
Ws,Wnd
{Wnd + 1,Wnd} = sign(Wb) * sign(Ws)
{Wnd + 1,Wnd} = sign(Wb) * unsign(lit5)
{Wnd + 1,Wnd} = sign(Wb) * unsign(Ws)
{Wnd + 1,Wnd} = unsign(Wb) * sign(Ws)
{Wnd + 1,Wnd} = unsign(Wb) * unsign(lit5)
{Wnd + 1,Wnd} = unsign(Wb) * unsign(Ws)
Wnd = sign-extended Ws
Destination = f – WREG
Wn = Wn – lit10
1
1
1
1
1
1
1
SUB
f {,WREG}
#lit10, Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
#lit10, Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Wb,#lit5,Wd
Wb,Ws,Wd
Ws,Wnd
1
SUB
1
SUB
Wd = Wb – lit5
1
SUB
Wd = Wb – Ws
1
SUBB
SUBB
SUBB
SUBB
SUBBR
SUBBR
SUBBR
SUBR
SUBR
SUBR
ZE
Destination = f – WREG – (C)
Wn = Wn – lit10 – (C)
1
1
Wd = Wb – lit5 – (C)
1
Wd = Wb – Ws – (C)
1
Destination = WREG – f – (C)
Wd = lit5 – Wb – (C)
1
1
Wd = Ws – Wb – (C)
1
Destination = WREG – f
Wd = lit5 – Wb
1
1
Wd = Ws – Wb
1
Wnd = zero-extended Ws
1
* Divide instructions are interruptible on a cycle-by-cycle basis. Also, divide instructions must be accompanied by a
REPEATinstruction, which adds 1 extra cycle.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 35
dsPIC33F
TABLE 9-5:
Assembly
LOGIC INSTRUCTIONS
Syntax
Description
Destination = f .AND. WREG
Words
Cycles
AND
AND
AND
AND
CLR
CLR
CLR
COM
COM
IOR
IOR
IOR
IOR
NEG
NEG
SETM
SETM
SETM
XOR
XOR
XOR
XOR
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Wn = lit10 .AND. Wn
Wd = Wb .AND. lit5
Wd = Wb .AND. Ws
f = 0x0000
WREG
WREG = 0x0000
Wd = 0x0000
Wd
f {,WREG}
Ws,Wd
Destination = f
Wd = Ws
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Ws,Wd
Destination = f .IOR. WREG
Wn = lit10 .IOR. Wn
Wd = Wb .IOR. lit5
Wd = Wb .IOR. Ws
Destination = f + 1
Wd = Ws + 1
f
f = 0xFFFF
WREG
WREG = 0xFFFF
Wd = 0xFFFF
Wd
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
Destination = f .XOR. WREG
Wn = lit10 .XOR. Wn
Wd = Wb .XOR. lit5
Wd = Wb .XOR. Ws
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
DS70155C-page 36
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 9-6:
Assembly
ROTATE/SHIFT INSTRUCTIONS
Syntax
Description
Words
Cycles
ASR
ASR
ASR
ASR
LSR
LSR
LSR
LSR
RLC
RLC
RLNC
RLNC
RRC
RRC
RRNC
RRNC
SL
f {,WREG}
Ws,Wd
Destination = arithmetic right shift f
Wd = arithmetic right shift Ws
Wnd = arithmetic right shift Wb by lit4
Wnd = arithmetic right shift Wb by Wns
Destination = logical right shift f
Wd = logical right shift Ws
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
Wnd = logical right shift Wb by lit4
Wnd = logical right shift Wb by Wns
Destination = rotate left through Carry f
Wd = rotate left through Carry Ws
Destination = rotate left (no Carry) f
Wd = rotate left (no Carry) Ws
Destination = rotate right through Carry f
Wd = rotate right through Carry Ws
Destination = rotate right (no Carry) f
Wd = rotate right (no Carry) Ws
Destination = left shift f
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
SL
Wd = left shift Ws
SL
Wb,#lit4,Wnd
Wb,Wns,Wnd
Wnd = left shift Wb by lit4
SL
Wnd = left shift Wb by Wns
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
TABLE 9-7:
Assembly
BIT INSTRUCTIONS
Syntax
Description
Words
Cycles
BCLR
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,Wb
Bit clear f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BCLR
Bit clear Ws
Bit set f
BSET
BSET
Bit set Ws
BSW.C
BSW.Z
BTG
Write C bit to Ws<Wb>
Write SZ bit to Ws<Wb>
Bit toggle f
Ws,Wb
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
BTG
Bit toggle Ws
BTST
Bit test f
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
BTSTS.C
BTSTS.Z
FBCL
Bit test Ws to C
Bit test Ws to SZ
Bit test Ws<Wb> to C
Bit test Ws<Wb> to SZ
Bit test f then set f
Ws,Wb
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wnd
Bit test Ws to C then set Ws
Bit test Ws to SZ then set Ws
Find bit change from left (MSb) side
Find first one from left (MSb) side
Find first one from right (LSb) side
FF1L
Ws,Wnd
FF1R
Ws,Wnd
Note:
Bit positions are specified by bit4 (0:15) for word operations.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 37
dsPIC33F
TABLE 9-8:
COMPARE/SKIP INSTRUCTIONS
Assembly Syntax
Description
Words
Cycles
BTSC
BTSC
BTSS
BTSS
CP
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
f
Bit test f, skip if clear
Bit test Ws, skip if clear
Bit test f, skip if set
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
Bit test Ws, skip if set
Compare (f – WREG)
Compare (Wb – lit5)
Compare (Wb – Ws)
Compare (f – 0x0000)
Compare (Ws – 0x0000)
1 (2 or 3)
1
CP
Wb,#lit5
Wb,Ws
f
1
CP
1
CP0
1
CP0
Ws
1
1
CPB
f
Compare with Borrow (f – WREG – C)
CPB
Wb,#lit5
Wb,Ws
Wb,Wn
Wb,Wn
Wb,Wn
Wb,Wn
Compare with Borrow (Wb – lit5 – C)
1
CPB
Compare with Borrow (Wb – Ws – C)
1
CPSEQ
CPSGT
CPSLT
CPSNE
Compare Wb with Wn, Skip if Equal (Wb = Wn)
Signed Compare Wb with Wn, Skip if Greater Than (Wb > Wn)
Signed Compare Wb with Wn, Skip if Less Than (Wb < Wn)
Signed Compare Wb with Wn, Skip if Not Equal (Wb ≠ Wn)
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
Note 1: Bit positions are specified by bit4 (0:15) for word operations.
2: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over a
one-word instruction and 3 cycles if the skip is taken over a two-word instruction.
DS70155C-page 38
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 9-9:
Assembly
PROGRAM FLOW INSTRUCTIONS
Syntax
Description
Words
Cycles
BRA
Expr
Branch unconditionally
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
2
1
1
1
1
1
1
1
1
2
BRA
Wn
Computed branch
2
BRA
C,Expr
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Z,Expr
Expr
Branch if Carry (no Borrow)
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
BRA
BRA
BRA
BRA
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
BRA
BRA
BRA
BRA
Branch if unsigned less than
Branch if Negative
BRA
BRA
Branch if not Carry (Borrow)
Branch if not Negative
BRA
BRA
Branch if not Overflow
BRA
Branch if not Zero
BRA
Branch if Accumulator A Overflow
Branch if Accumulator B Overflow
Branch if Overflow
BRA
BRA
BRA
Branch if Accumulator A Saturate
Branch if Accumulator B Saturate
Branch if Zero
BRA
BRA
CALL
CALL
DO
Call subroutine
Wn
Call indirect subroutine
2
#lit14,Expr
Wn,Expr
Expr
Do code through PC + Expr, (lit14 + 1) times
Do code through PC + Expr, (Wn + 1) times
Go to address
2
DO
2
GOTO
GOTO
RCALL
RCALL
REPEAT
REPEAT
RETFIE
RETLW
RETURN
2
Wn
Go to address indirectly
2
Expr
Relative call
2
Wn
Computed call
2
#lit14
Wn
Repeat next instruction (lit14 + 1) times
Repeat next instruction (Wn + 1) times
Return from interrupt enable
Return with lit10 in Wn
1
1
3 (2)
3 (2)
3 (2)
#lit10,Wn
Return from subroutine
Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken, or 2 cycles if the branch is
taken.
2: RETURNnormally executes in 3 cycles; however, it executes in 2 cycles if an interrupt is pending.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 39
dsPIC33F
TABLE 9-10: SHADOW/STACK INSTRUCTIONS
Assembly Syntax
Description
Words Cycles
LNK
#lit14
f
Link Frame Pointer
Pop TOS to f
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
POP
POP
Wd
Pop TOS to Wd
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
ULNK
Wnd
Double pop from TOS to Wnd:Wnd + 1
Pop shadow registers
f
Push f to TOS
Ws
Wns
Push Ws to TOS
Push double Wns:Wns + 1 to TOS
Push shadow registers
Unlink Frame Pointer
TABLE 9-11: CONTROL INSTRUCTIONS
Assembly Syntax
Description
Words Cycles
CLRWDT
DISI
Clear Watchdog Timer
1
1
1
1
1
1
1
1
1
1
1
1
#lit14
#lit1
Disable interrupts for (lit14 + 1) instruction cycles
No operation
NOP
NOPR
No operation
PWRSAV
RESET
Enter Power-Saving mode lit1
Software device Reset
TABLE 9-12: DSP INSTRUCTIONS
Assembly
Syntax
Description
Add accumulators
Words Cycles
ADD
Acc
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADD
Ws,#Slit4,Acc
16-bit signed add to Acc
Clear Acc
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wy,Wxd
Wm*Wm,Acc,Wx,Wy,Wxd
Ws,#Slit4,Acc
ED
Euclidean distance (no accumulate)
Euclidean distance
EDAC
LAC
Load Acc
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Acc
Multiply and accumulate
Square and accumulate
Move Wx to Wxd and Wy to Wyd
Multiply Wn by Wm to Acc
Square to Acc
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
-(Multiply Wn by Wm) to Acc
Multiply and subtract from Acc
Negate Acc
NEG
SAC
Acc,#Slit4,Wd
Store Acc
SAC.R
SFTAC
SFTAC
SUB
Acc,#Slit4,Wd
Store rounded Acc
Acc,#Slit6
Arithmetic shift Acc by Slit6
Arithmetic shift Acc by (Wn)
Subtract accumulators
Acc,Wn
Acc
DS70155C-page 40
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
10.0 MICROCHIP DEVELOPMENT
TOOL SUPPORT
Microchip offers comprehensive development tools
and libraries to support the dsPIC33F architecture. In
addition, the company is partnering with many third
party tools manufacturers for additional dsPIC33F
device support. Table 10-1 lists development tools that
support the dsPIC33F family. The paragraphs that
follow describe each of the tools in more detail.
TABLE 10-1: dsPIC33F DEVELOPMENT TOOLS
Development Tool
Description
Part #
From
MPLAB® IDE
Integrated Development Environment
SW007002 Microchip
(see Section 10.1 MPLAB Inte-
grated Development Environment
Software)
MPLAB ASM30
(see Section 10.2 MPLAB ASM30
Assembler/Linker/Librarian)
Assembler (included in MPLAB IDE)
SW007002 Microchip
SW007002 Microchip
SW007002 Microchip
SW006012 Microchip
DV164005 Microchip
DV007004 Microchip
MPLAB SIM
(see Section 10.3 MPLAB SIM
Software Simulator)
Software Simulator (Included in MPLAB IDE)
MPLAB VDI
(see Section 10.4 MPLAB Visual
Device Initializer)
Visual Device Initializer for dsPIC33F
(included in MPLAB IDE)
MPLAB C30
(see Section 10.5 MPLAB C30 C
Compiler/Linker/Librarian)
ANSI C Compiler, Assembler, Linker and Librarian
In-Circuit Debugger and Device Programmer
MPLAB ICD 2
(see Section 10.6 MPLAB ICD 2
In-Circuit Debugger)
Full-Featured Device Programmer, Base Unit
MPLAB PM3
(see Section 10.7 MPLAB PM3
Universal Device Programmer)
Socket Module for 100L TQFP Devices (14 mm x 14 mm)
Socket Module for 80L TQFP Devices (12 mm x 12 mm)
Socket Module for 64L TQFP Devices (10 mm x 10 mm)
TBD
TBD
TBD
Microchip
Microchip
Microchip
Legend:
TBD = To Be Determined
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 41
dsPIC33F
• Context sensitive, interactive on-line help
• Integrated MPLAB SIM instruction simulator
• User interface for MPLAB PM3 and PICSTART®
Plus device programmers (sold separately)
10.1 MPLAB Integrated Development
Environment Software
The MPLAB Integrated Development Environment
(IDE) is available at no cost. The MPLAB IDE lets the
user edit, compile and emulate from a single user
interface, as depicted in Figure 10-1. Code can be
designed and developed for the dsPIC® DSC devices
in the same design environment as the PICmicro
microcontrollers. The MPLAB IDE is a 32-bit Windows®
operating system-based application that provides
many advanced features for the demanding engineer in
• User interface for MPLAB ICD 2 In-Circuit
Debugger (sold separately)
The MPLAB IDE allows:
• Editing of source files in either assembly or ‘C’
• One-touch compiling and downloading to dsPIC
DSC emulator or simulator
• Debugging using:
a
modern, easy-to-use interface. MPLAB IDE
integrates:
- Source files
- Machine code
• Full-featured, color coded text editor
• Easy to use project manager with visual display
• Source level debugging
- Mixed mode source and machine code
The ability to use the MPLAB IDE with multiple
development and debugging targets provides easy
transition from the cost-effective simulator to MPLAB
ICD 2, or to a full-featured emulator with minimal
retraining.
• Enhanced source level debugging for ‘C’
(structures, automatic variables, etc.)
• Customizable toolbar and key mapping
• Dynamic status bar displays processor condition
FIGURE 10-1:
MPLAB® IDE DESKTOP
Set break/trace points with
a click of the mouse
Powerful Project Manager handles
multiple projects and all file types
Simply move your mouse over a
variable to view or modify
Color keyed editor makes
source code debug easier
Fullycustomizable watch windows
to view and modify registers and
memory locations
Status bar updates on
single step or run
DS70155C-page 42
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
10.2 MPLAB ASM30 Assembler/Linker/
Librarian
10.4 MPLAB Visual Device Initializer
The MPLAB Visual Device Initializer (VDI) simplifies
the task of configuring the dsPIC33F. MPLAB VDI
software allows you to configure the entire processor
graphically (see Figure 10-2). And when you’re done, a
mouse click generates your code in assembly or
‘C’ code. MPLAB VDI performs extensive error
checking on assignments and conflicts on pins,
memories and interrupts, as well as selection of
operating conditions. Generated code files are
integrated seamlessly with the rest of our application
code through MPLAB Project.
MPLAB ASM30 is a full-featured macro assembler.
User-defined macros, conditional assembly and a
variety of assembler directives make the MPLAB
ASM30 a powerful code generation tool.
The accompanying MPLAB LINK30 Linker and MPLAB
LIB30 Librarian modules allow efficient linking, library
creation and maintenance.
Notable features of the assembler include:
• Support for the entire dsPIC DSC instruction set
• Support for fixed-point and floating-point data
• Available for Windows operating system
• Command Line Interface
Detailed resource assignment and configuration
reports simplify project documentation. Key features of
MPLAB VDI include:
• Drag-and-drop feature selection
• One click configuration
• Rich Directive Set
• Flexible Macro Language
• Extensive error checking
• MPLAB IDE compatibility
• Generates initialization code in the form of a
‘C’ callable assembly function
Notable features of the linker include:
• Automatic or user-defined stack allocation
• Integrates seamlessly in MPLAB Project
• Supports dsPIC DSC Program Space Visibility
(PSV) window
• Printed reports ease project documentation
requirements
• Available for Windows operating systems
• Command Line Interface
• MPLAB Visual Device Initializer is an MPLAB
plug-in and can be installed independently of
MPLAB IDE
• Linker scripts for all dsPIC DSC devices
• MPLAB IDE compatibility
FIGURE 10-2:
MPLAB® VDI DISPLAY
10.3 MPLAB SIM Software Simulator
The MPLAB SIM software simulator provides code
development for the dsPIC33F family in a PC-hosted
environment by simulating the dsPIC33F device on an
instruction level. On any instruction, you can examine
or modify the data areas and apply stimuli to any of the
pins from a file or by pressing a user-defined key.
The execution can be performed in Single-Step,
Execute-Until-Break or Trace mode. The MPLAB SIM
software simulator fully supports symbolic debugging
using the MPLAB C30 C compiler and assembler. The
software simulator gives you the flexibility to develop
and debug code outside of the laboratory environment,
making it an excellent multi-project software
development tool. Complex stimuli can be injected from
files, synchronous clocks or user-defined keys. Output
files log register activity for sophisticated post analysis.
Besides modeling the behavior of the CPU, MPLAB
SIM also supports the following peripherals:
• Timers
• Motor Control PWM
• UART
• Input Capture
• 12-Bit ADC
• 10-Bit ADC
• I/O Ports
• Program Flash
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 43
dsPIC33F
The MPLAB C30 has these characteristics:
• 16-bit native data types
10.5 MPLAB C30 C Compiler/Linker/
Librarian
• Efficient use of register-based, 3-operand
instructions
The Microchip Technology MPLAB C30 C Compiler
provides ‘C’ language support for the dsPIC33F family.
This C compiler is a fully ANSI-compliant product with
standard libraries. It is highly optimized for the
dsPIC33F family and takes advantage of many
dsPIC33F architecture-specific features to help you
generate very efficient software code. Figure 10-3
illustrates the code size efficiency relative to several
competitors.
• Complex addressing modes
• Efficient multi-bit shift operations
• Efficient signed/unsigned comparisons
MPLAB C30 comes complete with its own assembler,
linker and librarian. These allow Mixed mode ‘C’ and
assembly programs and link the resulting object files
into a single executable file. The compiler is sold
separately. The assembler, linker and librarian are
available for free with MPLAB C30.
MPLAB C30 also provides extensions that allow for
excellent support of the hardware, such as interrupts
and peripherals. It is fully integrated with MPLAB IDE
for high-level source debugging.
MPLAB C30 also includes the Math Library, Peripheral
Library, DSP Library and standard ‘C’ libraries.
FIGURE 10-3:
RELATIVE CODE SIZE (IN BYTES)
DS70155C-page 44
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
The MPLAB PM3 programmer is designed with
40 programmable socket pins and therefore, each
socket module can be configured to support many
different devices. As a result, fewer socket modules are
required to support the entire line of Microchip parts.
The socket modules use multi-pin connectors for high
reliability and quick interchange.
10.6 MPLAB ICD 2 In-Circuit Debugger
The MPLAB ICD 2 In-Circuit Debugger is a powerful,
low-cost, run-time development tool that uses in-circuit
debugging capability built into the dsPIC33F Flash
devices. This feature, along with Microchip’s In-Circuit
Serial Programming™ protocol, gives you cost-effective,
in-circuit debugging from the graphical user interface of
MPLAB IDE. It lets you develop and debug source code
by watching variables, single-stepping and setting
breakpoints, as well as running at full speed to test
hardware in real time.
When connected to a PC host system, the MPLAB
PM3 programmer is seamlessly integrated with the
MPLAB Integrated Development Environment (IDE),
providing a user-friendly programming interface.
Key features of the MPLAB PM3 Programmer include:
• RS-232 or USB interface
The MPLAB ICD 2 has these features:
• Full-speed operation to the range of the device
• Serial or USB PC connector
• Integrated In-Circuit Serial Programming™
(ICSP™) interface
• USB-powered from PC interface
• Fast programming time
• Three operating modes:
- PC Host mode for full control
- Safe mode for secure data
• Low noise power (VPP and VDD) for use with
analog and other noise sensitive applications
• Operation down to 2.0V
• Can be used as debugger and inexpensive serial
programmer
- Stand-Alone mode for programming without
a PC
• Some device resources required (80 bytes of
RAM and 2 pins)
• Complete line of interchangeable socket modules
to support all Microchip devices and package
options (sold separately)
• SQTPSM serialization for programming unique
serial numbers while in PC Host mode.
FIGURE 10-4:
MPLAB® ICD 2 IN-CIRCUIT
DEBUGGER
• An alternate DOS command line interface for
batch control
• Large easy-to-read display
• Field upgradeable firmware allows quick new
device support
• Secure Digital (SD) and Multimedia Card (MMC)
external memory support
• Buzzer notification for noisy environments
FIGURE 10-5:
MPLAB® PM3 DEVICE
PROGRAMMER
10.7 MPLAB PM3 Universal Device
Programmer
The MPLAB PM3 Universal Device Programmer is easy
to use with a PC, or as a stand-alone unit, to program
Microchip’s entire line of PICmicro devices as well as the
latest dsPIC33F DSC devices. The MPLAB PM3
features a large and bright LCD unit (128 x 64 pixels) to
display easy menus, programming statistics and status
information.
The MPLAB PM3 programmer has exceptional
programming speed for high production throughput,
especially important for large memory devices. It also
includes a Secure Digital/Multimedia Card slot for easy
and secure data storage and transfer.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 45
dsPIC33F
Table 11-1 summarizes available and planned
dsPIC33F software tools and libraries. Microchip also
provides value added services, such as skilled/certified
technical application contacts, reference designs and
hardware and software developers. (Contact Microchip
DSCD Marketing for availability.)
11.0 dsPIC33F DEVELOPMENT TOOLS
AND APPLICATION LIBRARIES
Microchip offers a comprehensive set of tools and
libraries to help with rapid development of dsPIC33F
device-based application(s).
TABLE 11-1: MICROCHIP SOFTWARE DEVELOPMENT TOOLS AND APPLICATION LIBRARIES
Development Tool
Description
Part #
Math Library (see Section 11.1 Math
Library)
Double Precision and Floating-Point Library
(ASM, C Wrapper)
SW300020
Peripheral Library (see Section 11.2
Peripheral Driver Library)
Peripheral Initialization, Control and Utility Routines (C)
SW300021
SW300022
SW300023
DSP Library (see Section 11.3 DSP
Algorithm Library)
Essential DSP Algorithm Suite (Filters, FFT)
dsPICworks™ Tool (see Section 11.4
dsPICworks™ Data Analysis and DSP
Software)
Graphical Data Analysis and Conversion Tool for DSP Algorithms
Digital Filter Design (see Section 11.5 Digital Graphical IIR and FIR Filter Design Package for dsPIC33F
Filter Design Software Utility)
SW300001
SW300024
TCP/IP Library (see Section 11.6 Microchip TCP/IP Connectivity and Protocol Support
TCP/IP Stack)
Soft Modem Library (see Section 11.7 Soft V.22bis/V.22 Soft Modem Library
SW300002
Modem Library)
V.32bis Soft Modem Library up to 5K units
SW300003-5K
V.32bis Soft Modem Library up to 25K units
V.32bis Soft Modem Library up to 100K units
Evaluation Copy of V.32bis Soft Modem Library
SW300003-25K
SW300003-100K
SW300003-EVAL
SW300010-5K
Speech Recognition Library (see
Speech Recognition Library up to 5K units
Section 11.8 Speech Recognition Library)
Speech Recognition Library up to 25K units
SW300010-25K
SW300010-100K
SW300010-EVAL
SW300040-5K
Speech Recognition Library up to 100K units
Evaluation Copy of Speech Recognition Library
Noise Suppression Library up to 5K units
Noise Suppression Library (see
Section 11.9 Noise Suppression Library)
Noise Suppression Library up to 25K units
SW300040-25K
SW300040-100K
SW300040-EVAL
SW300060-5K
Noise Suppression Library up to 100K units
Evaluation Copy of Noise Suppression Library
Acoustic Echo Cancellation Library up to 5K units
Acoustic Echo Cancellation Library up to 25K units
Acoustic Echo Cancellation Library up to 100K units
Evaluation Copy of Acoustic Echo Cancellation Library
Symmetric Key Embedded Encryption Library up to 5K units
Symmetric Key Embedded Encryption Library up to 25K units
Symmetric Key Embedded Encryption Library up to 100K units
Acoustic Echo Cancellation Library (see
Section 11.10 Acoustic Echo Cancellation
Library)
SW300060-25K
SW300060-100K
SW300060-EVAL
SW300050-5K
Symmetric Key Embedded Encryption
Library (see Section 11.11 Symmetric Key
Embedded Encryption Library)
SW300050-25K
SW300050-100K
Evaluation Copy of Symmetric Key Embedded Encryption Library SW300050-EVAL
Asymmetric Key Embedded Encryption
Library (see Section 11.12 Asymmetric Key
Embedded Encryption Library)
Asymmetric Key Embedded Encryption Library up to 5K units
Asymmetric Key Embedded Encryption Library up to 25K units
SW300055-5K
SW300055-25K
Asymmetric Key Embedded Encryption Library up to 100K units SW300055-100K
Evaluation Copy of Asymmetric Key Embedded Encryption
Library
SW300055-EVAL
Speech Encoding/Decoding Library (see
Section 11.13 Speech Encoding/Decoding
Library)
Speech Encoding/Decoding Library up to 5K units
Speech Encoding/Decoding Library up to 25K units
Speech Encoding/Decoding Library up to 100K units
Evaluation Copy of Speech Encoding/Decoding Library
SW300070-5K
SW300070-25K
SW300070-100K
SW300070-EVAL
DS70155C-page 46
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 11-2: MEMORY USAGE AND
11.1 Math Library
PERFORMANCE
Memory Usage (bytes)(1,2)
The dsPIC33F Math Library is the compiled version of
the math library that is distributed with the highly
optimized, ANSI-compliant dsPIC33F MPLAB C30 C
Compiler (SW006012). It contains advanced single and
Code size
Data size
5250
4
double-precision
floating-point
arithmetic
and
Performance (cycles)(1,3)
trigonometric functions from the standard ‘C’ header
file (math.h). The library delivers small program code
size and data size, reduced cycles and high accuracy.
add
sub
mul
div
122
124
109
361
385
492
Features
• The math library is callable from either MPLAB
C30 or dsPIC33F assembly language.
Rem
Sqrt
• The functions are IEEE-754 compliant, with
signed zero, signed infinity, NaN (Not a Number)
and denormal support and operated in the “Round
to Nearest” mode.
Note 1: Results are based on using dsPIC33F
MPLAB C30 C Compiler (SW006012),
version 1.20.
• Compatible with MPLAB ASM30 and MPLAB
LINK30, which are available at no charge from
Microchip’s web site.
2: Maximum “Memory Usage” when all
functions in the library are loaded. Most
applications will use less.
Table 11-2 shows the memory usage and performance
of the Math Library. Table 11-3 lists the math functions
that are included.
3: Average 32-bit floating-point performance
results.
TABLE 11-3: MATH FUNCTIONS
Single and Double-Precision Floating-Point Functions
Arithmetic Functions
add, subtract, multiply, divide, remainder
Root and Power Functions
Trigonometric and Hyperbolic Functions
Logarithmic and Exponential Functions
Rounding Functions
pow, sqrt
acos, asin, atan, atan2, cos, cosh, sin, sinh, tan, tanh
exp, log, log10, frexp, ldexp
ceil, floor
Absolute Value Functions
fabs
Modular Arithmetic Functions
Comparison and Conversions
fmod, modf
comparison, integer and floating-point conversions
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 47
dsPIC33F
11.2 Peripheral Driver Library
11.3 DSP Algorithm Library
The free DSP library supports multiple filtering,
convolution, vector and matrix functions. Among the
supported functions are:
Microchip offers a free peripheral driver library that
supports the setup and control of dsPIC33F hardware
peripherals, including, but not limited to:
• Cascaded Infinite Impulse Response (IIR) Filters
• Correlation
• Analog-to-Digital Converter
• Motor Control PWM
• Quadrature Encoder Interface
• UART
• Convolution
• Finite Impulse Response (FIR) Filters
• Windowing Functions
• FFTs
• SPI™
• Data Converter Interface
• I2C™
• LMS Filter
• Vector Addition and Subtraction
• Vector Dot Product
• General Purpose Timers
• Input Capture
• Vector Power
• Output Compare/Simple PWM
• CAN
• Matrix Addition and Subtraction
• Matrix Multiplication
• I/O Ports and External Interrupts
• Reset
Some DSP functions use double-precision and
floating-point arithmetic. All DSP routines are
developed and optimized in dsPIC33F assembly
language and are callable from both assembly and ‘C’
language. The Microchip MPLAB C30 and IAR C
Compilers are supported.
In addition to the hardware peripherals, the library
supports software generated peripherals, such as
standard LCD drivers, which support an Hitachi style
controller.
The peripheral library consist of more than 270
functions, as well as several macros for simple tasks
such as enabling and disabling interrupts. All peripheral
driver routines are developed and optimized using the
MPLAB C30 C Compiler. Electronic documentation
accompanies the peripheral library to help you become
familiar with and implement the library functions.
Key features of the DSP Algorithm Library include:
• 49 total functions
• Full compliance with the Microchip dsPIC33F C30
C Compiler, Assembler and Linker
• Simple user interface – just one library file and
one header file
Key features of the dsPIC33F Peripheral Library
include:
• Functions are both ‘C’ and assembly callable
• FIR filtering functions include support for Lattice,
Decimating, Interpolating and LMS filters
• A library file for each individual device from the
dsPIC33F family, including functions
corresponding to peripherals present in that
particular device.
• IIR filtering functions include support for Canonic,
Transposed Canonic and Lattice filters
• FIR and IIR functions may be used with the filter
files generated by the dsPIC33F Filter Design
program
• ‘C’ includefiles that let you take advantage of
predefined constants for passing parameters to
various library functions. There is an includefile
for each peripheral module.
• Transform functions include support for in-place
and out-of-place DCT, FFT and IFFT transforms
• Since the functions are in the form of precompiled
libraries, they can be called from a user
application program written in either MPLAB C30
C Compiler or dsPIC33F assembly language.
• Window functions include support for Bartlett,
Blackman, Hamming, Hanning and Kaiser
windows
• Support for Program Space Visibility
• Included ‘C’ source code allows you to customize
peripheral functions to suit your specific
application requirements.
• Complete function profile information including
register usage, cycle count and function size
information
• Predefined constants in the ‘C’ includefiles
eliminate the need to refer to the details and
structure of every Special Function Register while
initializing peripherals or checking status bits.
• Electronic documentation is included to help you
comprehend and use the library functions
DS70155C-page 48
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE 11-4: FUNCTION EXECUTION TIMES
Cycle Count
Number of
Cycles(2)
Execution Time @
40 MIPS
Function
Equation
Conditions(1)
Complex FFT(3)
Complex FFT(3)
Complex FFT(3)
Block FIR
—
—
N = 64
N = 128
3739
8485
19055
1205
7337
1188
2350
212
93.5 μs
212.1 μs
476.4 μs
30.1 μs
183.4 μs
29.7 μs
58.8 μs
5.3 μs
—
N = 256
53 + N(4 + M)
41 + N(4 + 7M)
36 + N(8 + 7S)
46 + N(16 + 7M)
20 + 3(C * R)
16 + C(6 + 3(R – 1))
17 + 3N
N = 32, M = 32
N = 32, M = 32
N = 32, S = 4
N = 32, M = 8
C = 8, R = 8
C = 8, R = 8
N = 32
Block FIR Lattice
Block IIR Canonic
Block IIR Lattice
Matrix Add
Matrix Transpose
Vector Dot Product
Vector Max
232
5.8 μs
113
2.8 μs
5.7 μs
19 + 7(N – 2)
17 + 4N
N = 32
229
Vector Multiply
Vector Power
N = 32
145
3.6 μs
16 + 2N
N = 32
80
2.0 μs
Note 1: C = # columns, N = # samples, M = # taps, S = # sections, R = # rows.
2: 1 cycle = 25 nanoseconds @ 40 MIPS.
3: Complex FFT routine inherently prevents overflow.
FIGURE 11-1:
dsPICworks™ DATA
ANALYSIS AND DSP
SOFTWARE
11.4 dsPICworks™ Data Analysis and
DSP Software
The dsPICworks tool is a free data analysis and signal
processing package for use with Microsoft®
Windows® 9x, Windows NT®, Windows 2000 and
Windows XP platforms. It provides an extensive
number of functions encompassing:
• Wide variety of Signal Generators – Sine, Square,
Triangular, Window Functions, Noise
• Extensive DSP Functions – FFT, DCT, Filtering,
Convolution, Interpolation
• Extensive Arithmetic Functions – Algebraic
Expressions, Data Scaling, Clipping, etc.
• 1-D, 2-D and 3-D Displays
• Multiple Data Quantization and Saturation
Options
• Multi-Channel Data Support
• Automatic “Script File”-based Execution Options
available for any user-defined sequence of
dsPICworks Tool Functions
• File Import/Export interoperable with MPLAB IDE
• Digital Filtering Options support Filters generated
by dsPIC DSC Filter Design
• ASM30 Assembler File Option to export Data
Tables into dsPIC33F RAM
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 49
dsPIC33F
11.4.1
SIGNAL GENERATION
11.4.4
FILE IMPORT/EXPORT – MPLAB
IDE AND MPLAB ASM30 SUPPORT
dsPICworks™ Data Analysis and DSP Software support
an extensive set of signal generators, including basic
sine, square and triangle wave generators, as well as
advanced generators for window functions, unit step,
unit sample, sine, exponential and noise functions.
Noise, with specified distribution, can be added to any
signal. Signals can be generated as 32-bit floating-point,
or as 16-bit fractional fixed-point values, for any desired
sampling rate. The length of the generated signal is
limited only by available disk space. Signals can be
imported or exported from or to MPLAB IDE file register
windows. Multi-channel data can be created by a set of
multiplexing functions.
dsPICworks Data Analysis and DSP Software allow
data to be imported from the external world in the form
of ASCII text or binary files. Conversely, it also allows
data to be exported out in the form of files. The
dsPICworks tool supports all file formats supported by
the MPLAB import/export table. This feature allows the
user to bring real-world data from MPLAB IDE into the
dsPICworks tool for analysis. The dsPICworks tool can
also create ASM30 assembler files that can be
included into the MPLAB workspace.
11.5 Digital Filter Design Software Utility
11.4.2
DIGITAL SIGNAL PROCESSING
(DSP) AND ARITHMETIC
OPERATIONS
The Digital Filter Design tool for the dsPIC33F 16-bit
digital signal controllers makes designing, analyzing and
implementing Finite Impulse Response (FIR) and Infinite
Impulse Response (IIR) digital filters easy through a
menu-driven, user-intuitive interface. This tool performs
complex mathematical computations for filter design,
provides superior graphical displays and generates
comprehensive design reports. Desired filter frequency
specifications are entered and the tool automatically
generates the filter code and coefficient files ready to
use in the MPLAB Integrated Development Environment
(IDE). System analysis of the filter transfer function is
supported with multiple generated graphs, such as
magnitude, phase, group delay, log magnitude, impulse
response and pole/zero locations.
dsPICworks Data Analysis and DSP Software have a
wide range of DSP and arithmetic functions that can be
applied to signals. Standard DSP functions include
transform operations: FFT and DCT, convolution and
correlation, signal decimation, signal interpolation
sample rate conversion and digital filtering. Digital
filtering is an important part of the dsPICworks tool. It
uses filters designed by the sister-application, dsPIC
DSC Filter Design, and applies them to synthesized or
imported signals. The dsPICworks tool also features
special operations, such as signal clipping, scaling and
quantization, all of which are vital in real practical
analysis of DSP algorithms.
FIGURE 11-2:
DIGITAL FILTER DESIGN
TOOL INTERFACE
11.4.3
DISPLAY AND MEASUREMENT
dsPICworks Data Analysis and DSP Software have a
wide variety of display and measurement options.
Frequency domain data may be plotted in the form of
2-dimensional ‘spectrogram’ and 3-dimensional
‘waterfall’ options. The signals can be measured
accurately by a simple mouse click. The log window
shows current cursor coordinates, as well as derived
values, such as the difference from last position and
signal frequency. Signal strength can be measured
over a particular range of frequencies. Special support
also exists for displaying multi-channel and multiplexed
data. Graphs allow zoom options. The user can choose
from a set of color scheme options to customize display
settings.
DS70155C-page 50
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Key features of the Digital Filter Design tool include:
Code Generation Features
• Generated files are compliant with the Microchip
dsPIC33F C30 C Compiler, Assembler and Linker
Finite Impulse Response Filter Design
• Design Method Selection
- FIR Windows Design
• Choice of placement of coefficients in Program
Space or Data Space
- FIR Equiripple Design (Parks-McClellan)
• ‘C’ Wrapper/Header Code Generation
• Low-Pass, High-Pass, Band-Pass and Band-Stop
Filters
Graphs
• FIR Filters can have up to 513 taps
• The following window functions are supported:
- Rectangular
• Magnitude Response vs. Frequency
• Log Magnitude vs. Frequency
• Phase Response vs. Frequency
• Group Delay vs. Frequency
- Hanning (Hann)
- Hamming
- Triangular
- Blackman
- Exact Blackman
• Impulse Response vs. Time (per sample)
• Step Response vs. Time (per sample)
• Pole and Zero Locations (IIR only)
- 3 Term Cosine
11.6 Microchip TCP/IP Stack
- 3 Term Cosine with Continuous 3rd Derivative
- Minimum 3 Term Cosine
- 4 Term Cosine
- 4 Term Cosine with continuous 5th Derivative
- Minimum 4 Term Cosine
- Good 4 Term Blackman Harris
- Harris Flat Top
The free Microchip TCP/IP Stack is a suite of programs
that can provide services to standard (HTTP Server,
Mail Client, etc.) or custom TCP/IP-based applications.
Users do not need to be an expert in TCP/IP
specifications to use it and only need specific
knowledge of TCP/IP in the accompanying HTTP
Server application.
- Kaiser
This stack is implemented in a modular fashion, with all
of its services creating highly abstracted layers, each
layer accessing services from one or more layers
directly below it. The stack is optimized for size and is
designed to run on the dsPIC33F using the
dsPICDEM.net™ Development Board; however, it can
be easily retargeted to any hardware equipped with a
dsPIC33F. HTML web pages generated by the
dsPIC33F can be viewed with a standard web browser
such as Microsoft Internet Explorer.
- Dolph-Tschebyscheff
- Taylor
- Gaussian
• Reports show design details, such as window
coefficients and impulse response prior to
multiplying by the window function
Infinite Impulse Response Filter Design
• Low-Pass, High-Pass, Band-Pass and Band-Stop
Filters
Key features of the Microchip TCP/IP Stack include:
• Filter Orders up to 10 for Low-Pass and
High-Pass Filters
• Out-of-box support for Microchip C30 C Compiler
• Implements complete TCP state machine
• Filter Orders up to 20 for Band-Pass and
Band-Stop Filters
• Multiple TCP and UDP sockets with simultaneous
connection/management
• Five Analog Prototype Filters are available:
- Butterworth
- Tschebyscheff
- Inverse Tschebyscheff
- Elliptic
• Includes modules supporting various standard
protocols: MAC, SLIP, ARP, IP, ICMP, TCP,
SNMP, UDP, DHCP, FTP, IP Gleaning, HTTP,
MPFS (Microchip File System)
- Bessel
• Can be used as a part of the HTTP Server
(included) or any custom TCP/IP-based
application
• Digital Transformations are performed by Bilinear
Transformation Method
• Reports show design details, such as all
transformations from normalized low-pass filter to
desired filter
• RTOS independent
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 51
dsPIC33F
11.7 Soft Modem Library
11.8 Speech Recognition Library
The Microchip data modem library is composed of
ITU-T compliant algorithms for V.21, V.22, V.22bis,
V.23, V.32 and V.32bis modem recommendations. Bell
standard 103 is also included in this library.
The dsPIC Speech Recognition Library provides voice
control of embedded applications that require an
alternative user interface. With a vocabulary of up to
100 words, the Speech Recognition Library allows
users to control their application using spoken
commands. The Speech Recognition Library is an ideal
front end for hands-free products, such as modem
appliances, security panels and cell phones. The
Speech Recognition Library has very modest memory
and processing requirements and is targeted for the
dsPIC30F5011, dsPIC30F5013, dsPIC30F6012 and
dsPIC30F6014 processors.
V.21, V.23 and Bell 103 are Frequency Shift Keying
(FSK) modems. V.32, V.32bis and V.22bis are
Quadrature Amplitude Modulation (QAM) modems. V.22
is a Quadrature Phase Shift Keying (QPSK) modem.
V.21, V.22, V.22bis, V.32 and V.32bis are all 2-wire, full-
duplex modems. V.23 is a full-duplex modem when it
operates with a 75 bps backwards channel.
V.22bis includes fallback to V.22, V.23 and V.21
standards. V.32bis optionally falls back to V.22bis, V.22
and V.21 standards.
Key features of the dsPIC DSC Speech Recognition
Library include:
• US English language support
The dsPIC DSC Soft Modem is well-suited for small
transaction oriented applications, such as, but not
limited to:
• Speaker independent recognition of isolated
words
• No speaker training is required
• POS Terminals
• Hidden Markov Modem-based recognition system
• Recognition time < 500 msec
• Set Top Boxes
• Drop Boxes
• Master library of 100 common words (listed in the
“dsPIC30F Speech Recognition Library User’s
Guide”)
• Fire Panels
• Internet Enabled Home Security Systems
• Internet Connected Power, Gas and Water Meters
• Internet Connected Vending Machines
• Smart Appliances
• Windows operating system-based utility allows
the user to create a custom word library from the
master library
• Industrial Monitoring
• Additional words can be added to the master
library (fee based)
Functions supporting ITU-T Recommendation V.42 are
provided with each library. V.42 contains a High-Level
Data Link Control (HDLC) protocol, referred to as Link
Access Procedure for Modems (LAPM) and defines
error correcting protocols for modems.
• Data tables can be stored in external memory
• Optional keyword activation and silence detection
• Optional system self-test using a predefined
keyword
All data pump modulation and demodulation functions
are written in ASM30 assembly code yielding optimal
code size and execution time. The AT, V.42 and data
pump APIs are written in C30 C Compiler language.
• Flexible API
• Full compliance with Microchip MPLAB C30 C
Compiler Language Tools
• “dsPIC30F Speech Recognition Library User’s
Guide” and “dsPIC30F Word Library Builder
User’s Guide”
Electronic documentation accompanies the modem
library to help you become familiar with and implement
the library functions. A comprehensive “dsPIC30F Soft
Modem Library User’s Guide” describes the required
APIs for the AT, V.42 and data pump layers.
• Designed to run on dsPICDEM™ 1.1 General
Purpose Development Board (DM300014)
11.8.1
RESOURCE REQUIREMENTS
• Sampling Interface: Si-3000 Audio Codec
operating at 12.0 kHz
• System Operating Frequency: 12.288, 18.432 or
24.576 MHz
• Computational Power: 8 MIPS
• Program Flash Memory: 18 KB + 1.5 KB for each
library word
• RAM: < 3.0 KB
DS70155C-page 52
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
11.9 Noise Suppression Library
11.10 Acoustic Echo Cancellation Library
The dsPIC DSC Noise Suppression Library provides a
function to suppress the effect of noise interfering with
a speech signal. This function is useful for microphone-
based applications which have a potential for incoming
speech getting corrupted by ambient noise captured by
a microphone. It is especially suitable for systems in
which an acoustically isolated noise reference is not
available, such as:
The Acoustic Echo Cancellation (AEC) Library
provides a function to eliminate echo generated in the
acoustic path between a speaker and a microphone.
This function is useful for speech and telephony
applications in which a speaker and a microphone are
located in close proximity to each other and therefore,
susceptible to signals propagating from the speaker to
the microphone resulting in
a perceptible and
distracting echo effect at the far end. It is especially
suitable for these applications:
• Hands-Free Cell Phone Kits
• Speakerphones
• Hands-Free Cell Phone Kits
• Speakerphones
• Intercoms
• Teleconferencing Systems
• Headsets
• Intercoms
• Teleconferencing Systems
• As a front end to a Speech Recognition or Speech
Encoding system
For hands-free phones intended to be used in compact
environments, such as a car cabin, this library is fully
compliant with the G.167 standard for Acoustic Echo
Cancellation.
• Any microphone-based application that needs to
eliminate undesired noise
• Any application that needs to eliminate noise
interference from signals received over a
communication channel
Like the Noise Suppression Library, the Acoustic Echo
Cancellation Library also includes sample rate
conversion functions.
The Noise Suppression Library uses an 8 kHz sampling
rate. However, the library includes sample rate
conversion functions that ensure interoperability with
libraries and speech sampling peripherals configured for
higher sampling rates (9.6 kHz, 11.025 kHz or 12 kHz).
Key features of the AEC Library include:
• All functions can be called from either a ‘C’ or
assembly application program
• Full compliance with the Microchip C30
C Compiler, Assembler and Linker
Key features of the Noise Suppression Library include:
• All functions can be called from either a ‘C’ or
assembly application program
• Precompiled library archive files
• Highly optimized assembly code, utilizing DSP
instructions and advanced addressing modes
• Full compliance with the Microchip C30
C Compiler, Assembler and Linker
• Echo cancellation for 16, 32 or 64 ms echo delay
or ‘tail length’ (configurable)
• Precompiled library archive files
• Highly optimized assembly code, utilizing DSP
instructions and advanced addressing modes
• Fully tested for compliance with G.167
specifications for in-car applications
• Audio Bandwidth: 0-4 kHz at 8 kHz sampling rate
• Audio Bandwidth: 0-4 kHz at 8 kHz sampling rate
• 10-20 dB noise reduction depending on type of
noise
• Convergence Rate: up to 43 dB/sec.,
typically > 30 dB/sec.
• “dsPIC30F Noise Suppression Library User’s Guide”
• Demo application source code is provided
• Echo Cancellation: Up to 50 dB, typically > 40 dB
• “dsPIC30F Acoustic Echo Cancellation Library
User’s Guide”
• Accessory Kit available for purchase includes:
audio cable, headset, oscillators, microphone,
speaker, DB9 M/F RS-232 cable, DB9M-DB9M
null modem adapter and can be used for library
evaluation
• Demo application source code is provided
• Accessory Kit available for purchase
TABLE 11-6: RESOURCE REQUIREMENTS
Algorithm
MIPS Flash
RAM
TABLE 11-5: RESOURCE REQUIREMENTS
AEC – 64 ms Echo Tail
AEC – 32 ms Echo Tail
AEC – 16 ms Echo Tail
Sample Rate Conversion
16.5
10.5
7.5
6 KB 5.7 KB
6 KB 3.4 KB
6 KB 2.6 KB
2.6 KB 0.5 KB
Algorithm
MIPS Flash
RAM
Noise Suppression
3.3
1.0
7 KB
1 KB
Sample Rate Conversion
2.6 KB 0.5 KB
1.0
Note:
The user application might require an
additional 1 KB-1.5 KB for data buffering
(application-dependent).
Note:
The user application might require an
additional 2 KB-2.5 KB for data buffering
(application-dependent).
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 53
dsPIC33F
11.11 Symmetric Key Embedded
Encryption Library
11.12 Asymmetric Key Embedded
Encryption Library
Microchip offers
a
reliable security solution for
Microchip offers a reliable security solution for
embedded applications built on the dsPIC33F platform.
This solution is provided by means of two libraries –
Symmetric Key and Asymmetric Key Embedded
Encryption Libraries. The Symmetric Key Library
includes the following:
embedded applications built on the dsPIC33F platform.
This solution is provided by means of two libraries –
Symmetric Key and Asymmetric Key Embedded
Encryption Libraries. The Asymmetric Key Library
includes the following:
• Hash functions
• Public Key Encryption/Decryption functions
- RSA (1024 and 2048-bit)
• Key Agreement Protocol
- Diffie-Hellman (1024 and 2048-bit)
• Signing and Verification
- DSA (1024-bit)
- SHA-1 Secure Hash Standard
- MD5 Message Digest
• Symmetric Key Encryption/Decryption functions
- Advanced Encryption Standard (AES)
- Triple Data Encryption Standard (Triple-DES)
• Random Number Generator functions
- RSA (1024 and 2048-bit)
• Hash functions
- Deterministic Random Bit Generator
ANSI X9.82
- SHA-1 Secure Hash Standard
- MD5 Message Digest
Some typical applications for this library include:
• Random Number Generator functions
- ANSI X9.82
• Mobile and Wireless Devices, PDAs
• Secure Banking
• Secure Web Transactions
Some typical applications for this library include:
- Secure Socket Layer (SSL)
- Transport Layer Security (TLS)
- Secure Multipurpose Mail Extensions (S/MIME)
• Mobile and Wireless Devices, PDAs
• Secure Banking
• Secure Web Transactions
- Secure Socket Layer (SSL)
- Transport Layer Security (TLS)
• ZigBee™ Technology and other Monitoring and
Control Applications
• Smart Card Readers/Trusted Card Readers
• Friend/Foe Identification
- Secure Multipurpose Mail Extensions
(S/MIME)
• Secure devices and peripherals interoperating
with TCG (Trusted Computing Group) and
NGSCB (Microsoft Next Generation Secure
Computing Base) personal computers
• ZigBee Technology and other Monitoring and
Control Applications
• Smart Card Readers/Trusted Card Readers
• Friend/Foe Identification
Key features of the Symmetric Key Embedded
Encryption Library include:
• Secure devices and peripherals interoperating
with TCG (Trusted Computing Group) and
NGSCB (Microsoft Next Generation Secure
Computing Base) personal computers
• C-callable library functions developed in MPLAB
ASM30 assembly language
• Optimized for speed, code size and RAM usage
- RAM usage below 60 bytes
Key features of the Asymmetric Key Embedded
Encryption Library include:
• Library functions extensively tested for adherence
to applicable standards
• C-callable library functions developed in MPLAB
ASM30 assembly language
• Symmetric Key Encryption/Decryption functions
support multiple modes of operation:
• Optimized for speed, code size and RAM usage
- RAM usage below 100 bytes
- Electronic Code Book (ECB) mode
• Library functions extensively tested for adherence
to applicable standards
- Cipher Block Chaining with Message
Authentication (CBC-MAC) mode
• “dsPIC30F Embedded Encryption Libraries User’s
Guide”
- Counter (CTR) mode
- Combined CBC-MAC and CTR (CCM) mode
• Several examples of use are provided for each
library function
• “dsPIC30F Embedded Encryption Libraries User’s
Guide”
• Several examples of use are provided for each
library function
DS70155C-page 54
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Key features of the Speech Encoding/Decoding Library
include:
11.13 Speech Encoding/Decoding
Library
• PESQ-based Mean Opinion Score: 3.7-4.2
(out of 5.0)
The Speech Encoding/Decoding Library performs toll-
quality voice compression and voice decompression.
The library is based on a modified version of the Speex
speech encoder/decoder source code and features a
16:1 compression ratio. It samples speech at 8 kHz and
compresses it to a data rate of 8 kbps. Storing
• Code Excited Linear Prediction (CELP) based
coding
• 2 Analog Input Interfaces – codec or on-chip ADC
• 2 Analog Output Interfaces – codec or
on-chip PWM
compressed
speech
for
playback
requires
approximately 1 KB of memory for each second of
speech. The library is especially suitable for the
following voice-based applications:
• Optional Voice Activity Detection
• Storing compressed speech requires 1 KB of
memory per second of speech
• Answering Machines
• Building and Home Safety Systems
• Intercoms
• Royalty-free (only one-time license fee)
• Full compliance with Microchip MPLAB C30
C Compiler Language Tools
• Smart Appliances
• “dsPIC30F Speech Encoding/Decoding Library
User’s Guide”
• Voice Recorders
• Designed to run on dsPICDEM 1.1 General
Purpose Development Board (DM300014)
• Walkie-Talkies
• Any Application using Message Playback
A PC-based speech encoder utility program allows you
to create your own encoded speech files for playback.
Encoded speech files are made from either a PC
microphone or existing WAV file. Once you create the
encoded speech files, they are added to your MPLAB
C30 project, just like a regular source file, and built into
your application. The speech encoder utility allows you to
select four target memory areas to store your speech file:
program Flash memory, RAM and external Flash
memory. External Flash memory allows you to store
many minutes of speech (1 minute of speech requires
60 KB) and it is supported through a general purpose I/O
port.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 55
dsPIC33F
12.0 THIRD PARTY DEVELOPMENT
TOOLS AND APPLICATION
LIBRARIES
Besides providing development tools and application
libraries for dsPIC33F products, Microchip also
partners with key third party tool manufacturers to
develop quality hardware and software tools in support
of the dsPIC33F product family. Details of various third
party development tools will be provided shortly.
DS70155C-page 56
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
MPLAB In-Circuit Debugger (ICD 2) tool for cost-
effective debugging and programming of the dsPIC33F
devices. These two boards are shown in Table 13-1.
13.0 dsPIC33F HARDWARE
DEVELOPMENT BOARDS
Microchip initially offers two hardware development
boards that help you quickly prototype and validate key
aspects of your design. Each board features various
dsPIC33F peripherals and supports Microchip’s
Microchip plans to offer additional hardware
development boards to support the dsPIC33F product
family. Contact Microchip DSCD Marketing for
additional information.
TABLE 13-1: HARDWARE DEVELOPMENT BOARDS
Development Tool
Description
Part #
From
General Purpose
Development Board
dsPICDEM™ 80-Pin Starter Development Board
Explorer 16 Development Board
DM300019
DM240001
Microchip
Microchip
Plug-in Sample
(see Section 13.3
Plug-in Modules)
PC board with 80-pin dsPIC30F6014A general purpose
MCU sample; use with DM300019 development board.
MA300014
MA330011
MA330012
AC300030
Microchip
Microchip
Microchip
Microchip
PC board with 100-pin dsPIC33F MCU sample; use with
DM240001 development board.
PC board with 100-pin dsPIC33F MCU sample; use with
DM300019 development board.
Acoustic Accessory
Kit
(see Section 13.3
Plug-in Modules)
Accessory Kit includes: audio cable, headset, oscillators,
microphone, speaker, DB9 M/F RS-232 cable,
DB9M-DB9M Null Modem Adapter and can be used for
library evaluation.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 57
dsPIC33F
13.1 dsPICDEM™ 80-Pin Starter
Development Board
13.2 Explorer 16 Development Board
This development board offers a very economical way
to evaluate both the dsPIC33F General Purpose and
Motor Control Family devices, as well as the PIC24F
devices. This board is an ideal prototyping tool to help
you quickly develop and validate key design
requirements.
This development board offers a very economical way
to evaluate both the dsPIC30F and dsPIC33F General
Purpose and Motor Control Family devices. This board
is an ideal prototyping tool to help you quickly develop
and validate key design requirements.
Some key features and attributes of the Explorer 16
Development Board include:
Some key features and attributes of the dsPICDEM
80-Pin Starter Development Board include:
• Includes a 100-pin dsPIC33F plug-in module
(MA330011)
• Includes an 80-pin dsPIC30F6014A plug-in
module (MA300014)
• Includes a 100-pin PIC24 plug-in module
(part # TBD)
• Power input from 9V supply
• Selectable voltage regulator outputs of 5V
and 3.3V
• Power input from 9V supply
• Modular design for plug-in demonstration boards,
expansion header
• LEDs, switches, potentiometer, UART interface
• A/D input filter circuit for speech band signal input
• On-board DAC and filter for speech band signal output
• Circuit prototyping area
• ICD 2 and JTAG connection for reprogramming
• USB and protocol translation support through
PIC18F4450
• Assembly language demonstration program and
tutorial
• RS-232 connection with firmware and driver
support
• Can accommodate 80-pin dsPIC30F6010 plug-in
module (MA300013)
• LED bank for general indication
• Serial EEPROM
• Can accommodate 100 to 80-pin adapter
dsPIC33F plug-in module (MA330012)
• 16 x 2 alphanumeric LCD
• Temperature sensor
FIGURE 13-1:
dsPICDEM™ 80-PIN
STARTER DEVELOPMENT
BOARD
• Terminal interface program and menu programs
FIGURE 13-2:
EXPLORER 16
DEVELOPMENT BOARD
DS70155C-page 58
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
13.3 Plug-in Modules
13.4 Acoustic Accessory Kit
The various dsPIC33F development boards may use
the plug-in modules for the dsPIC33F silicon devices.
Since the boards contain device header pins on the
PCB, they also are used to provide flexibility for the
replacement of the dsPIC33F silicon. Three different
plug-in sample types will be provided, supporting the
64-pin, 80-pin and 100-pin TQFP package types for
General Purpose and Motor Control Family device
samples. The use of plug-in samples is considered to
be an interim development board mechanization.
The Acoustic Accessory Kit includes the following
accessories targeted towards acoustics-oriented
library (NS, AEC, etc.) evaluation and application
development support:
• 6 ft. Stereo Audio Cable
• Stereo Headset
• Two 14.7456 MHz Oscillators
• Clip-on Microphone
• Fold-up Speaker
• 6 ft. DB9 M/F RS-232 Cable
• DB9M-DB9M Null Modem Adapter
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 59
dsPIC33F
Table A-1 provides a brief description of device I/O
pinouts and functions that can be multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
APPENDIX A: DEVICE I/O PINOUTS
AND FUNCTIONS
FOR GENERAL
PURPOSE FAMILY
TABLE A-1:
PINOUT I/O DESCRIPTIONS FOR GENERAL PURPOSE FAMILY
Pin
Type
Input Buffer
Type
Pin Name
Description
AN0-AN23
AVDD
I
Analog
Analog input channels.
P
P
I
P
P
Positive supply for analog module.
Ground reference for analog module.
AVSS
CLKI
ST/CMOS
External clock source input. Always associated with OSC1 pin
function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs. Can be software programmed for
internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
I/O
I/O
I
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CSDO
O
C1RX
C1TX
C2RX
C2TX
I
O
I
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
O
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
I/O
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is
an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
ST/CMOS
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
OSC2
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
DS70155C-page 60
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE A-1:
PINOUT I/O DESCRIPTIONS FOR GENERAL PURPOSE FAMILY (CONTINUED)
Pin
Type
Input Buffer
Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
RD0-RD15
RE0-RE9
I/O
I/O
ST
ST
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
I/O
ST
ST
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
ST
ST
—
ST
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
I
O
I
I/O
I
O
I
SPI2 data out.
SPI2 slave synchronization.
ST
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
SOSCO
I
O
ST/CMOS
—
32 kHz low-power oscillator crystal input; CMOS otherwise.
32 kHz low-power oscillator crystal output.
TMS
TCK
TDI
I
I/O
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input/output pin.
JTAG test data input pin.
TDO
O
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
U1TX
UART1 transmit.
U2CTS
U2RTS
U2RX
UART2 clear to send.
UART2 ready to send.
UART2 receive.
U2TX
UART2 transmit.
VDD
P
P
P
I
—
—
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Analog voltage reference (high) input.
Analog voltage reference (low) input.
VDDCORE
VSS
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 61
dsPIC33F
TABLE A-2:
dsPIC33F GENERAL PURPOSE FAMILY VARIANTS (DEVICES MARKED “PS”)
Program Flash
Memory (KB)
RAM
(KB)
Device
Pins
Packages
(1)
33FJ128GP706
33FJ128GP708
64
80
128
128
256
17
17
33
9
9
9
8
8
8
8
8
8
1
1
1
2 A/D,
18 ch
2
2
2
2
2
2
2
2
2
2
2
2
53
69
86
PT
PT
PF
2 A/D,
24 ch
33FJ256GP710 100
2 A/D,
32 ch
Note 1: RAM size is inclusive of 1 KB DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
Note:
Prototype samples are intended for dsPIC33F early adopters and are based on early revision silicon. Devices
are marked with “PS” suffix. Major differences are noted in this data sheet. For additional information, please
refer to the “dsPIC33F Data Sheet”.
DS70155C-page 62
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams
64-Pin TQFP
COFS/RG15
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EMUC1/SOSCO/T1CK/CN0/RC14
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
dsPIC33FJ128GP706*
9
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
/
*Device is marked with ‘PS’ designator.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 63
dsPIC33F
Pin Diagrams (Continued)
80-Pin TQFP
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
COFS/RG15
AN16/T2CK/T7CK/RC1
2
3
EMUC2/OC1/RD0
IC4/RD11
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
4
IC3/RD10
5
IC2/RD9
6
IC1/RD8
SDI2/CN9/RG7
7
SDA2/INT4/RA15
SCL2/INT3/RA14
VSS
SDO2/CN10/RG8
MCLR
8
9
SS2/CN11/RG9
VSS
10
11
12
dsPIC33FJ128GP708*
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
13
14
15
16
17
18
19
20
SCL1/RG2
SDA1/RG3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
EMUD3/U1TX/RF3
*Device is marked with ‘PS’ designator.
DS70155C-page 64
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
EMUC1/SOSCO/T1CK/CN0/RC14
VDD
2
3
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
AN29/RE5
AN30/RE6
AN31/RE7
4
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ256GP710*
VDD
SS2/CN11/RG9
RA5
RA4
VSS
VDD
RA0
SDA2/RA3
SCL2/RA2
AN20/INT1/RA12
AN21/INT2/RA13
SCL1/RG2
AN5/CN7/RB5
SDA1/RG3
AN4/CN6/RB4
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
EMUD3/U1TX/RF3
*Device is marked with ‘PS’ designator.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 65
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
dsPIC33FJ64GP206
dsPIC33FJ128GP206
9
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
DS70155C-page 66
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
dsPIC33FJ64GP306
dsPIC33FJ128GP306
9
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 67
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
1
2
3
4
5
6
7
8
dsPIC33FJ256GP506
9
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
DS70155C-page 68
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/T5CK/CN11/RG9
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
dsPIC33FJ64GP706
dsPIC33FJ128GP706
9
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 69
dsPIC33F
Pin Diagrams (Continued)
80-Pin TQFP
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
2
3
4
5
IC4/RD11
IC3/RD10
IC2/RD9
6
7
IC1/RD8
SDI2/CN9/RG7
SDA2/INT4/RA15
SCL2/INT3/RA14
SDO2/CN10/RG8
MCLR
8
9
VSS
10
11
12
13
14
SS2/CN11/RG9
dsPIC33FJ64GP708
dsPIC33FJ128GP708
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
TMS/AN20/INT1/RE8
TDO/AN21/INT2/RE9
AN5/CN7/RB5
VDD
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
15
16
17
18
19
20
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70155C-page 70
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
COFS/RG15
1
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
AN29/RE5
AN30/RE6
3
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
SDO2/CN10/RG8
MCLR
dsPIC33FJ64GP310
dsPIC33FJ128GP310
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RE8
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RE9
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 71
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
3
AN29/RE5
AN30/RE6
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ256GP510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RE8
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RE9
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70155C-page 72
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
AN29/RE5
AN30/RE6
3
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
AN31/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
VSS
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64GP710
dsPIC33FJ128GP710
dsPIC33FJ256GP710
13
14
15
16
17
18
19
20
21
22
23
24
25
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RE8
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RE9
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 73
dsPIC33F
Table B-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
APPENDIX B: DEVICE I/O PINOUTS
AND FUNCTIONS
FOR MOTOR
CONTROL FAMILY
TABLE B-1:
PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY
Pin
Type
Buffer
Type
Pin Name
Description
AN0-AN23
I
Analog
Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs, respectively.
AVDD
AVSS
P
P
P
P
Positive supply for analog module.
Ground reference for analog module.
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
I/O
I/O
I
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CSDO
O
C1RX
C1TX
C2RX
C2TX
I
O
I
ST
—
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin.
O
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
I/O
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
QEB
I
ST
UPDN
O
CMOS
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
FLTA
FLTB
I
I
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM 1 low output.
PWM 1 high output.
PWM 2 low output.
PWM 2 high output.
PWM 3 low output.
PWM 3 high output.
PWM 4 low output.
PWM 4 high output.
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
O
O
O
O
O
O
O
O
Legend: CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
DS70155C-page 74
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
TABLE B-1:
PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY (CONTINUED)
Pin
Type
Buffer
Type
Pin Name
Description
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an active-low
Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
OSC2
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Optionally functions as CLKO in RC and EC modes.
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
RD0-RD15
RE0-RE9
I/O
I/O
I/O
ST
ST
ST
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RF0-RF8
RF12-RF13
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
ST
ST
—
ST
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
I
O
I
I/O
I
O
I
SPI2 data out.
SPI2 slave synchronization.
ST
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
I
ST/CMOS 32 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
32 kHz low-power oscillator crystal output.
TMS
TCK
TDI
I
I/O
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input/output pin.
JTAG test data input pin.
TDO
O
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
Legend: CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 75
dsPIC33F
TABLE B-1:
PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY (CONTINUED)
Pin
Type
Buffer
Type
Pin Name
Description
U1CTS
U1RTS
U1RX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
U1TX
UART1 transmit.
U2CTS
U2RTS
U2RX
U2TX
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
VDD
P
P
P
I
—
—
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Analog voltage reference (high) input.
Analog voltage reference (low) input.
VDDCORE
VSS
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output; Analog = Analog input
ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power
TABLE B-2:
dsPIC33F MOTOR CONTROL FAMILY VARIANTS (DEVICES MARKED “PS”)
Program
Flash
Memory (KB)
(KB)
RAM
Device
Pins
Packages
(1)
33FJ128MC706 64
33FJ128MC708 80
33FJ256MC710 100
128
128
256
17
17
33
9
9
9
8
8
8
8
8
8
8 ch
8 ch
8 ch
1
1
1
0
0
0
2 A/D,
16 ch
2
2
2
2
2
2
2
2
2
1
1
2
53
69
86
PT
PT
PF
2 A/D,
18 ch
2 A/D,
24 ch
Note 1: RAM size is inclusive of 1 KB DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
Note:
Prototype samples are intended for dsPIC33F early adopters and are based on early revision silicon. Devices
are marked with “PS” suffix. Major differences are noted in this data sheet. For additional information, please
refer to the “dsPIC33F Data Sheet”.
DS70155C-page 76
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams
64-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EMUC1/SOSCO/T1CK/CN0/RC14
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
1
2
3
4
5
6
7
8
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
IC4/INT4/RD11
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
IC3/INT3/RD10
IC2/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
SS2/T5CK/CN11/RG9
VSS
dsPIC33FJ128MC706*
9
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
/
*Device is marked with ‘PS’ designator.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 77
dsPIC33F
Pin Diagrams (Continued)
80-Pin TQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
1
PWM3H/RE5
PWM4L/RE6
2
PWM4H/RE7
3
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
4
IC3/RD10
5
IC2/RD9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
6
IC1/RD8
7
SDA2/INT4/RA15
SCL2/INT3/RA14
8
9
VSS
SS2/CN11/RG9
10
11
12
13
14
15
16
17
18
19
20
dsPIC33FJ128MC708*
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
VDD
FLTA/INT1/RE8
FLTB/INT2/RE9
SCL1/RG2
AN5/QEB/CN7/RB5
SDA1/RG3
AN4/QEA/CN6/RB4
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
SDO1/RF8
U1RX/RF2
PGD/EMUD/AN0/CN2/RB0
EMUD3/U1TX/RF3
*Device is marked with ‘PS’ designator.
DS70155C-page 78
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
VDD
2
PWM3H/RE5
PWM4L/RE6
3
4
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
SS
SDI2/CN9/RG7
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
SDO2/CN10/RG8
MCLR
dsPIC33FJ256MC710*
VDD
SS2/CN11/RG9
VSS
RA5
VDD
RA4
RA0
AN20/FLTA/INT1/RA12
AN21/FLTB/INT2/RA13
AN5/QEB/CN7/RB5
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
EMUD3/U1TX/RF3
*Device is marked with ‘PS’ designator.
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 79
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
1
2
3
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
5
6
7
8
9
SS2/T5CK/CN11/RG9
dsPIC33FJ64MC506
VSS
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
DS70155C-page 80
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
64-Pin TQFP
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
1
2
3
4
5
6
7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
dsPIC33FJ128MC506
dsPIC33FJ64MC506
dsPIC33FJ128MC706
8
9
VSS
SS2/T5CK/CN11/RG9
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
/
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 81
dsPIC33F
Pin Diagrams (Continued)
80-Pin TQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
1
PWM3H/RE5
PWM4L/RE6
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
2
PWM4H/RE7
3
IC4/RD11
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
4
IC3/RD10
5
IC2/RD9
6
IC1/RD8
7
INT4/RA15
8
INT3/RA14
9
VSS
SS2/CN11/RG9
10
11
12
13
14
15
16
17
18
19
20
dsPIC33FJ64MC508
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
VDD
TMS/FLTA/INT1/RE8
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
TDO/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
DS70155C-page 82
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
80-Pin TQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
1
PWM3H/RE5
PWM4L/RE6
2
PWM4H/RE7
3
IC4/RD11
4
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
IC3/RD10
5
IC2/RD9
6
IC1/RD8
7
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SDA2/INT4/RA15
SCL2/INT3/RA14
8
9
VSS
SS2/CN11/RG9
10
11
12
13
14
15
16
17
18
19
20
dsPIC33FJ128MC708
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VSS
VDD
VDD
TMS/FLTA/INT1/RE8
TDO/FLTB/INT2/RE9
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGD3/EMUD3/AN0/CN2/RB0
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 83
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64MC510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
TDI/RA4
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
RA3
RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
DS70155C-page 84
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
SDI2/CN9/RG7
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
SDO2/CN10/RG8
MCLR
dsPIC33FJ128MC510
dsPIC33FJ256MC510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 85
dsPIC33F
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
COFS/RG15
1
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
PWM3H/RE5
PWM4L/RE6
3
4
IC4/RD11
PWM4H/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64MC710
dsPIC33FJ128MC710
dsPIC33FJ256MC710
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70155C-page 86
Preliminary
© 2005 Microchip Technology Inc.
dsPIC33F
NOTES:
© 2005 Microchip Technology Inc.
Preliminary
DS70155C-page 87
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Fax: 905-673-6509
08/24/05
DS70155C-page 88
Preliminary
© 2005 Microchip Technology Inc.
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