HCS412-/P [MICROCHIP]
暂无描述;
| 型号： | HCS412-/P |
| 厂家： | 
MICROCHIP |
| 描述： | 暂无描述 存储 |
| 文件： | 总28页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCSXXX
HCSXXX Memory Programming Specification
This document includes the
programming specifications for the
following devices:
1.2
Program/Verify Mode
The Program/Verify mode for the KEELOQ devices
allows programming for all memory locations within the
device being programmed. With the exception of the
decoders, these pins are also used to verify the memory
arrays.
• HCS200
• HCS201
• HCS300
• HCS301
• HCS320
• HCS360
• HCS361
• HCS362
• HCS410
• HCS412
• HCS500
• HCS512
• HCS515
1.0
PROGRAMMING THE HCSXXX
®
All of the KEELOQ devices are programmed using a
serial method. This Serial mode allows KEELOQ
devices to be programmed while in users' systems,
which increases the flexibility of designing
cryptographic encoders, decoders and transponders
into electronic systems. While some of the devices are
capable of being programmed through wireless
communications, the subject of this document is
focused on wired programmers that make contact with
the KEELOQ products while the components are in-
circuit or in a programmer socket. Additionally, this
programming specification only applies to all KEELOQ
devices listed above in all packages.
Note:
For the purpose of this document,
“KEELOQ devices” and “KEELOQ products”
refers to all of the components listed
above.
1.1
Programming Algorithm
Requirements
Depending on the device being programmed, the
method for entering Programming mode can be
achieved through the use of a combination of logic level
signals applied to the programming pins. One or two
pins are capable of accepting clock signals, while
another pin is dedicated to bidirectional data. These
pins are detailed in Table 1-1.
Additionally, the programming voltage range for VDD is
+5V ± 10% for all the KEELOQ devices. There is not a
requirement to apply high voltages to any of the pins
beyond the level of VDD in order to enter the
Programming mode. For more details about pin
configurations during programming, refer to Table 1-1.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 1
HCSXXX
Pin Diagrams
PDIP, SOIC
8
7
6
5
8
7
6
5
VDD
NC
VDD
S0
S1
S0
S1
1
2
3
4
1
2
3
4
STEP
DATA
VSS
PWM
VSS
S2
S2
NC
VDDB
8
8
VDD
LED
PWM
VSS
VDD
LED
PWM
VSS
S0
S1
S0
S1
1
1
7
6
5
7
6
5
2
3
4
2
3
4
S2
S3
S2
SHIFT
8
7
6
5
8
7
6
5
VDD
VDD
S0
S1
S0
S1
1
2
3
4
1
2
3
4
LED/SHIFT
DATA
LED
DATA
VSS
S2
S2
S3
VSS
S3/RFEN
8
7
6
5
8
VDD
VDD
S0
S1
S0
1
2
3
4
1
LC0
7
6
5
LED
DATA
GND
2
3
4
S1
PWM
GND
S2/LED
LC1
S2/RFEN/LC1
LC0
8
7
6
5
VSS
VDD
1
2
3
4
RFIN
EE_CLK
S_CLK
S_DAT
EE_DAT
MCLR
DS41256A-page 2
Preliminary
2004 Microchip Technology Inc.
HCSXXX
Pin Diagrams (Continued)
PDIP, SOIC
LRNIN
LRNOUT
NC
1
2
3
4
5
6
7
8
9
18 RFIN
17 NC
14
13
12
NC
NC
NC
NC
VSS
1
2
3
16 OSCIN
15 OSCOUT
14 VDD
MCLR
GND
S0
VDD
S1
S0
4
5
11
10
RF_IN
S_CLK
13 DATA
12 CLK
S1
6
7
9
8
MCLR
NC
S_DAT
NC
S2
11 SLEEP
10 VLOW
S3
TSSOP
8
8
S1
S1
S2/LED
S2
1
1
2
3
4
7
6
5
S0
7
6
5
S0
2
3
4
LC1
GND
PWM
S3/RFEN
VSS
HCS410
HCS362
VDD
LC0
VDD
LED/SHIFT
DATA
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 3
HCSXXX
TABLE 1-1:
Device
PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Number
Clock
Comments
Power Supply
Ground
Data
Other
HCS200
HCS201
HCS300
HCS301
HCS320
HCS360
HCS361
HCS362
HCS410
HCS412
HCS500
HCS512
HCS515
8
8
5
5
3
3
6
6
—
—
—
—
—
2
(Notes 1)
8
5
3, 4
3, 4
3
6
(Notes 2)
(Notes 2)
(Notes 2)
(Notes 2)
(Notes 2)
(Notes 2)
8
5
6
8
5
6
8
5
3, 4
3, 4
3, 4
3
6
8
5
6
2
8
5
6
—
—
—
—
4
8
5
6
8
5
3
6
(Note 1)
1
8
6
5
(Notes 2, 3, 4, 7, 8)
(Notes 5, 6, 8, 9)
(Notes 7, 8)
14
3
5
12
10
13
9
12
—
Note 1: Sends calibration pulse during ACK periods.
2: VDD pin must be driven low after a Program/Verify cycle.
3: In-circuit programming recommended.
4: Used in conjunction with a Microchip Technology 24LC02B device.
5: MCLR, pin 4, is used to enter Program mode.
6: Must apply external clock source to OSCIN while programming.
7: Requires command byte preceding data packet.
8: Verify function not available.
9: Uses checksum in data packet.
DS41256A-page 4
Preliminary
2004 Microchip Technology Inc.
HCSXXX
2.0
MEMORY MAPPING
The program memory maps for KEELOQ products begin
at 0x000 and extend as shown in the tables that follow.
As a device is being programmed, the address counter
automatically increments to the next word location after
receiving a data word. The memory maps for all
KEELOQ encoders and transponders were designed so
that each word is 16 bits wide. Decoder memory maps
are 8 bits wide.
2.1
Encoder Memory Maps
TABLE 2-1:
Word Address
0x00
HCS200 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
KEY_0
KEY_1
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value
Set to 0x0000
KEY_2
KEY_3
SYNC
Reserved
SER_0
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Set to 0x0000
SER_1
SEED_0
SEED_1
Reserved
CONFIG
Configuration Word
TABLE 2-2:
HCS201 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
KEY_0
KEY_1
KEY_2
KEY_3
SYNC
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value
Set to 0x0000
Reserved
SER_0
SER_1
SEED_0
SEED_1
DISC
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Discrimination Word
CONFIG
Configuration Word
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 5
HCSXXX
TABLE 2-3:
HCS300 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
KEY_0
KEY_1
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value
Set to 0x0000
KEY_2
KEY_3
SYNC
Reserved
SER_0
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Set to 0x0000
SER_1(1)
SEED_0
SEED_1
Reserved
CONFIG
Configuration Word
Note 1: MSb of this word is used for auto-shutoff timer.
TABLE 2-4:
HCS301 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
KEY_0
KEY_1
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value
Set to 0x0000
KEY_2
KEY_3
SYNC
Reserved
SER_0
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Set to 0x0000
SER_1(1)
SEED_0
SEED_1
Reserved
CONFIG
Configuration Word
Note 1: MSb of this word is used for auto-shutoff timer.
TABLE 2-5:
HCS320 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
KEY_0
KEY_1
KEY_2
KEY_3
SYNC
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value
Set to 0x0000
Reserved
SER_0
SER_1(1)
—
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Not used
—
Not used
Reserved
CONFIG
Set to 0x0000
Configuration Word
Note 1: MSb of this word is used for auto-shutoff timer.
DS41256A-page 6
Preliminary
2004 Microchip Technology Inc.
HCSXXX
TABLE 2-6:
Word Address
0x00
HCS360 12 X 16-BIT EEPROM MEMORY MAP
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
KEY_0
KEY_1
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
Word 1 of 64-bit crypt key
KEY_2
Word 2 of 64-bit crypt key
KEY_3
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value A
SYNC_A
SYNC_B
Reserved
SEED_0
SEED_1
SER_0
16-bit synchronization value B or Seed Value (Word 2)
Set to 0x0000
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Configuration Word
SER_1
CONFIG
TABLE 2-7:
HCS361 12 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
KEY_0
KEY_1
Word 1 of 64-bit crypt key
KEY_2
Word 2 of 64-bit crypt key
KEY_3
Word 3 (MSb's) of 64-bit crypt key
16-bit synchronization value A
16-bit synchronization value B or Seed Value (Word 2)
Set to 0x0000
SYNC_A
SYNC_B/SEED_2
Reserved
SEED_0
SEED_1
SER_0
Word 0 (LSb's) of 32-bit seed value
Word 1 (MSb's) of 32-bit seed value
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Configuration Word
SER_1
CONFIG
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 7
HCSXXX
TABLE 2-8:
HCS362 18 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
KEY1_0
KEY1_1
KEY1_2
KEY1_3
KEY2_0
KEY2_1
KEY2_2
KEY2_3
SEED_0
SEED_1
SEED_2
SEED_3
CONFIG_0
CONFIG_1
SERIAL_0
SERIAL_0
SYNC
Word 0 (LSb's) of 64-bit crypt key 1
Word 1 of 64-bit crypt key 1
Word 2 of 64-bit crypt key 1
Word 3 (MSb's) of 64-bit crypt key 1
Word 0 (LSb's) of 64-bit crypt key 2
Word 1 of 64-bit crypt key 2
Word 2 of 64-bit crypt key 2
Word 3 (MSb's) of 64-bit crypt key 2
Word 0 (LSb's) of 64-bit seed value
Word 1 of 64-bit seed value
Word 2 of 64-bit seed value
Word 3 (MSb's) of 64-bit seed value
Configuration Word (LSb's)
Configuration Word (MSb's)
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
16-bit synchronization value
Set to 0x0000
Reserved
TABLE 2-9:
HCS500 9 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
CONFIG
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
Configuration Word
Byte 0 (LSb’s) of 64-bit manufacturer key
Byte 1 of 64-bit manufacturer key
Byte 2 of 64-bit manufacturer key
Byte 3 of 64-bit manufacturer key
Byte 4 of 64-bit manufacturer key
Byte 5 of 64-bit manufacturer key
Byte 6 of 64-bit manufacturer key
Byte 7 (MSb’s) of 64-bit manufacturer key
TABLE 2-10: HCS512 10 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
KEY0
KEY1
Byte 0 (LSb’s) of 64-bit manufacturer key
Byte 1 of 64-bit manufacturer key
Byte 2 of 64-bit manufacturer key
Byte 3 of 64-bit manufacturer key
Byte 4 of 64-bit manufacturer key
Byte 5 of 64-bit manufacturer key
Byte 6 of 64-bit manufacturer key
Byte 7 (MSb’s) of 64-bit manufacturer key
Configuration byte
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
CONFIG
Checksum
Checksum byte
DS41256A-page 8
Preliminary
2004 Microchip Technology Inc.
HCSXXX
TABLE 2-11: HCS515 9 X 8-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
CONFIG
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
Configuration byte
Byte 0 (LSb’s) of 64-bit manufacturer key
Byte 1 of 64-bit manufacturer key
Byte 2 of 64-bit manufacturer key
Byte 3 of 64-bit manufacturer key
Byte 4 of 64-bit manufacturer key
Byte 5 of 64-bit manufacturer key
Byte 6 of 64-bit manufacturer key
Byte 7 (MSb’s) of 64-bit manufacturer key
2.2
Transponder Memory Maps
TABLE 2-12: HCS410 16 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
Word 0 (LSb's) of 64-bit crypt key
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
KEY_0
KEY_1
KEY_2
KEY_3
DISC
Word 1 of 64-bit crypt key
Word 2 of 64-bit crypt key
Word 3 (MSb's) of 64-bit crypt key
Ext. Config. Word/10-bit Discriminator
16-bit Configuration Word
CONFIG
SER_0
SER_1
SEED_0
SEED_1
SEED_2
SEED_3
USR_0
USR_1
USR_2
USR_3
Word 0 (LSb's) of 32-bit serial number
Word 1 (MSb's) of 32-bit serial number
Word 0 (LSb's) of 64-bit seed value
Word 1 of 64-bit seed value
Word 2 of 64-bit seed value
Word 3 (MSb's) of 64-bit seed value
Word 0 (LSb's) of 64-bit user area
Word 1 of 64-bit user area
Word 2 of 64-bit user area
Word 3 (MSb's) of 64-bit user area SYNC
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 9
HCSXXX
TABLE 2-13: HCS412 18 X 16-BIT EEPROM MEMORY MAP
Word Address
Mnemonic
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
KEY0
KEY1
Word 0 (LSb’s) of 64-bit crypt key 1
Word 1 of 64-bit crypt key 1
KEY2
Word 2 of 64-bit crypt key 1
KEY3
Word 3 (MSb’s) of 64-bit crypt key 1
Word 0 (LSb’s) of 60-bit seed value
Word 1 of 60-bit seed value
SEED0
SEED1
SEED2
CFG/SEED3
CONFIG1
CONFIG2
SER0
Word 2 of 60-bit seed value
Word 3 of 60-bit seed value/Configuration in top nibble
Configuration Word 1 (security options)
Configuration Word 2
Word 0 (LSb’s) of 32-bit serial number
Word 1 (MSb’s) of 32-bit serial number
Word 0 (LSb’s) of 64-bit user area
Word 1 of 64-bit user area
SER1
USR0
USR1
USR2
Word 2 of 64-bit user area
USR3
Word 3 (MSb’s) of 64-bit user area
The HCS512 is another device that does not conform to
the 2-wire protocol described above. For this device, the
MCLR pin is driven high while data is held low. After the
minimum setup time has been realized, the clock pin is
driven high and then low for a minimum amount of time
in order to send the HCS512 a Start condition and
complete the Entry mode for the next programming
sequence. The associated waveform is detailed in
Section 5.0 “Program/Verify Mode Electrical
Characteristics”. The HCS512 is also the only device
that requires a checksum be sent to the target device
while it is being programmed. See the Checksum
2.3
Entering Program Mode
Entering the Program/Verify mode will be dependent
upon the type of device in use. Most KEELOQ devices
use a serial clock and bidirectional data line to access
the chips' memory maps. In order to enter the
Programming mode, a Start condition is sent to the
target device, where the clock and data lines must be
held high and low for specified periods of time. That is,
all lines are held low while the clock line is driven high.
After a short delay, the data line is driven high. At this
point, both lines must remain high for another delay
period prior to dropping back to ground. After dropping
both lines low and providing another delay, the state
machine for the KEELOQ device will enter the
Programming mode and begin to wait for data, or
depending on the component, a bulk erase is
performed on the memory array.
®
Section in the HCS512 Data Sheet, “KEELOQ Code
Hopping Decoder“ (DS40151), for details on calculating
the checksum.
Note:
The HCS512 requires an external clock
signal for the OSCIN pin. This signal is
necessary throughout the Programming
mode.
For the HCS360 and HCS361 devices, the Programming
mode is entered by providing a clock source on the clock
line and a Start pulse on the data line, as described in the
previous paragraph. However, the difference is with
driving the S1 pin, as shown in Figure 5-5. Bit 0 of the
data packet must be driven on the S1 pin and kept at that
level throughout the programming cycles and through
verification.
DS41256A-page 10
Preliminary
2004 Microchip Technology Inc.
HCSXXX
2.4
Bulk Write Device
2.7
Polling Write Cycle
All transponders and encoders are bulk erased and
programmed with zeros following the Start condition.
The bulk erase/write time frame is specified as TPBW,
which is minimally 4.0 ms. After the bulk function is
complete, the programming state machine continues
into the Program mode where it begins to wait for data
and clock signals.
2.7.1
HCS201 AND HCS412
Once the 16th clock cycle for the data word has been
generated and the next minimum low time for the clock
passes, the clock pin can be driven high to poll the
completion of the write cycle. Before the write cycle is
complete, the data pin for the target KEELOQ device will
be low. After the write cycle is complete, the data pin on
the HCS201 and the HCS412 will begin to provide
pulses to the programmer in order to signal the
completion of the write cycle. As a result, the
programmer data pin should be set to high-impedance
(input) so that it can read the pulses. After reading the
pulses on the data pin, the programmer should drive
the clock pin low and make the data pin an output so
that data can continue to be driven into the target
device. These pulses can be used for calibration
sequences for the HCS201 and the HCS412. For
information relating to oscillator calibration refer to
Section 5.0 “Program/Verify Mode Electrical
Characteristics”, which discusses oscillator tuning. If
the programmer polls the target device for the end of a
write cycle, these two devices will continue to emit
calibration pulses until their clock lines are driven low.
In order to measure the calibration pulses, the clock pin
must be driven high prior to the end of the write cycle,
otherwise the calibration pulses will not appear.
2.5
Serial Program/Verify Operation
For all of the encoders and transponders, the memory
maps have been designed to be in 16-bit format, which
means that each address location contains 16 bits of
information including “don't care” bits that are read as
zeros. Details relating to the designated pins for clock
and data signals are outlined in Table 1-1. The
decoders, on the other hand, were designed with
memory maps in 8-bit format, so they are discussed
separately in the next couple of paragraphs.
For specific information relating to the size of the
memory maps for a given family of devices, be sure to
review the tables in Section 2.1 “Encoder Memory
Maps”.
The following paragraphs were written with the
assumption that the target device has been placed into
the Programming mode and is now waiting for data or
a command byte to continue programming the memory
array.
2.7.2
ALL OTHER KEELOQ DEVICES
Once the 16th clock cycle for the data word has been
generated for any of the encoders or transponders or
the last clock cycle for a decoder data packet is
generated, the clock pin can be driven high to poll for
the completion of the write cycle. Before the write cycle
is complete, the data pin for the target KEELOQ device
will be low. As a result, the programmer data pin should
be set to high-impedance (input) so that it can sense
the rising edge of data. After the write cycle is
complete, the data pin will be driven high until the clock
line is driven low again.
2.5.1
ENCODERS/TRANSPONDERS
To input data to the target KEELOQ encoder or
transponder, 16 clock cycles are applied to the clock pin
of the target device while data is driven into the data pin.
Data is clocked into the target device on the falling edge
of the clock signal. Also, the minimum high time and low
time for the clock signals are 50 µs. During verification,
data must be sampled on the rising edge of the clock.
2.5.2
DECODERS
To input data to the target KEELOQ decoder, 8 clock
cycles are applied to the clock pin of the target device
while data is driven into the data pin. Data is clocked
into the target device on the falling edge of the clock
signals. Also, the minimum high time and minimum low
time for the clock signals are 50 µs. For the decoder
family, there are no verification functions.
2.6
Begin Programming
Write cycles are performed a bit-at-a-time throughout
the entire programming sequence for KEELOQ
products. The total write cycle, which includes internal
processing and programming time, is specified to take
a minimum of 50 ms. As a result, programmers can
include a delay for the minimum write cycle time or they
can poll the target device as discussed in Section 2.7
“Polling Write Cycle”.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 11
HCSXXX
2.8
Verify Mode
4.0
OSCILLATOR TUNING
In terms of verify operations, all KEELOQ encoders and
transponders incorporate a security feature that only
allows one verify operation to be completed, and it
must be completed at the end of the programming
sequence before exiting the Programming mode.
Calibrating the oscillator of select devices can be
completed a number of ways. For the purpose of this
document, calibration will be completed using the Two-
Point Calibration Algorithm, which is described in
®
Application Note AN824, “KEELOQ
Encoders
Oscillator Calibration” (DS00824). The algorithm is as
follows:
When implementing polling routines to sense the end
of the last write cycle and after driving the clock line low,
the programmer can begin to read data by continuing
to provide clock cycles to the target device. Note that
there is not an Acknowledge bit from KEELOQ devices
during the Verify mode.
• OSCCAL = -8
• Program target device
• Measure oscillator frequency FHIGH
• OSCCAL = +7
In the case where the programmer provides a time delay
to allow for write cycle completion, the programmer can
provide clock cycles after the delay to begin reading
data.
• Program target device
• Measure oscillator frequency FLOW
• Interpolate:
- OSCCAL = 16*(FIDEAL - FLOW)/(FHIGH - FLOW)
• Program target device
Note:
Decoders do not incorporate a verify
function.
For a better understanding of how to implement this
algorithm, the following flow charts are being provided:
3.0
CONFIGURATION WORD
For detailed descriptions of bit functions for the
configuration words of the KEELOQ devices, be sure to
download the latest Data Sheet for the respective device
from
the
Microchip
Technology
web
site
(www.microchip.com). Configuration word architectures
are also shown earlier in Section 2.0 “Memory
Mapping”.
DS41256A-page 12
Preliminary
2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-1:
HCS201 AND HCS412 OSCILLATOR TUNING
Preload Datastream
with 0x7 for OSCCAL(1)
Store Average Value
as FLOW
Interpolate
OSCCAL
Preload Datastream
with 400 µs Time Element
Measure Calibration Pulses
as Time Elements
Reset Target(2)
Preload Datastream
with Interpolated OSCCAL
Poll Target for End
of Write Cycle
Program Target
Reset Target(2)
Program First Word
of Target
Preload Desired
Baud Rate
Preload Datastream
with 0x8 for OSCCAL(1)
Reset Target(2)
Program Target
Preload Datastream
with 400 µs Time Element
Program Remaining
Target
Program First Word
of Target
Store Average Value
as FHIGH
Poll Target for End
of Write Cycle
Measure Calibration Pulses
as Time Elements
Note 1: -8d = 0x7, and +7d = 0x8
2: Cycle Power
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 13
HCSXXX
FIGURE 4-2:
HCS362 AND HCS410 OSCILLATOR TUNING
Preload Datastream
with 0x7 for OSCCAL(1)
Store Average Value
as FLOW
Interpolate
OSCCAL
Preload Datastream
with 400 µs Time Element
Measure Preamble
Time Elements
Preload Datastream
with Interpolated OSCCAL
Activate Button
Input on Target
Program Target
Device
Preload Desired
Baud Rate
Reset Target(2)
Reset Target(2)
Program Target
Activate Button
Input on Target
Program Target
Device
Measure Preamble
Time Elements
Preload Datastream
With 400 µs Time Element
Store Average
Value as FHIGH
Preload Datastream
With 0x8 for OSCCAL
Reset Target(2)
Note 1: -8d = 0x7, and +7d = 0x8
2: Cycle Power
DS41256A-page 14
Preliminary
2004 Microchip Technology Inc.
HCSXXX
KEELOQ devices that are capable of oscillator tuning
include the HCS201, HCS362, HCS410 and the
HCS412. Though, only the HCS201 and HCS412
transmit calibration pulses when polling the chips at the
end of write cycles.
The HCS362 and the HCS410 oscillator tuning register
can also be tuned as shown in the algorithm above, but
with the caveat that after the device is programmed, the
programmer must activate the target device in order to
measure the time element in the communication
preamble. A typical preamble is shown in Figure 4-3.
The other two devices must be tuned according to the
preamble pulses that they transmit at the beginning of
a data packet. For the best accuracy, use multiple time
elements to achieve an average time element value.
Typically, a number that is a power of 2n is used in order
to simplify the resultant quotient (i.e., 4 or 8). In order to
obtain the most accurate time element measurement,
the widest possible baud rate should be chosen. For
simplifying the two flow diagrams below, a common
time element was chosen to the devices that share
algorithms.
FIGURE 4-3:
PWM CODE WORD TRANSMISSION TIMINGS
TE TE
TE TE TE
Preamble = 23 TE
bit 1
Header = 10 TE
bit 0
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 15
HCSXXX
4.1
Programming Flow Charts
FIGURE 4-4:
PROGRAMMING FLOW
CHART 1
FIGURE 4-5:
PROGRAMMING FLOW
CHART 2
Start
Start
Set VDD =
5.0V ± 10%
Set VDD =
5.0V ± 10%
Send Start
Sequence
Send Start
Sequence
If Data Bit 0 =
Then S1 =
Else S1 =
0
0
Device
Bulk Erase
1
Load 16 Bits
of Data
(LSb first)
Load 16-Bits
of Data
Load 16 Bits of
Complemented
Data
Wait TWC or
Poll Rising
Pulse
(LSb first)
Wait TWC or
Poll Calibration
Pulse
All Locations
Programmed?
No
Yes
All Locations
Programmed?
No
Begin Verify
Yes
Begin Verify
Read 16-Bits
of Data
Read 16-Bits
of Data
No
All Locations
Verified?
No
All Locations
Verified?
Yes
Program/Verify
Complete
Yes
Program/Verify
Complete
Note:
Applies to HCS200, HCS201, HCS300,
HCS301, HCS320, HCS362, HCS410
and HCS412 only.
Note:
Applies to HCS360 and HCS361 only.
DS41256A-page 16
Preliminary
2004 Microchip Technology Inc.
HCSXXX
FIGURE 4-6:
PROGRAMMING FLOW
CHART 3
FIGURE 4-7:
PROGRAMMING FLOW
CHART 4
Start
Start
Set VDD =
Set VDD =
5.0V ± 10%
5.0V ± 10%
Raise
NMCLR
Send Start
Sequence
Send Start
Sequence
Load 8-Bits
of Data
Load 8-Bits
of Data
All Locations
Loaded?
No
Yes
All Locations
Loaded?
No
Wait TWC or
Poll Rising
Pulse
Yes
Program
Complete
Load
Checksum
Wait TWC or
Poll Rising
Pulse
Note:
Applies to HCS500 and HCS515 only.
Program
Complete
Note:
Applies to HCS512 only.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 17
HCSXXX
5.0
5.1
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
Timing Requirements for Program/Verify Mode – Encoders
Standard Operating Conditions (unless otherwise
stated)
AC/DC CHARACTERISTICS
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
Sym
Characteristics
Min
Max
Units
Conditions/Comments
HCS200, HCS300, HCS301, HCS320 and HCS362
TCLKH
TCLKL
TDH
Clock high time
Clock low time
50
50
30
0
—
—
—
—
30
—
—
—
—
4.5
—
µs
µs
Data hold time
µs
TDS
Data setup time
Data out valid time
Bulk Write time
µs
TDV
—
µs
TPBW
TPH1
TPH2
TPROG
TPS
4.0
3.5
50
4.0
3.5
50
ms
ms
µs
Hold Time 1
Hold Time 2
Program delay time
Program mode setup time
Program cycle time
ms
ms
ms
TWC
HCS201
TACKH
TACKL
TCLKH
TCLKL
TDH
Data out valid time
Data hold time
Clock high time
Clock low time
Data hold time
Data setup time
Data out valid time
Bulk Write time
Hold Time 1
800
800
50
—
—
—
—
—
—
30
—
—
—
—
—
5.0
—
µs
µs
µs
µs
µs
µs
µs
ms
ms
µs
µs
ms
ms
ms
50
18
TDS
0
TDV
—
TPBW
TPH1
TPH2
4.0
4.0
50
Hold Time 2
TPHOLD Hold time
100
4.0
2.0
50
TPROG
TPS
Program delay time
Program mode setup time
Program cycle time
TWC
HCS360, HCS361
T1
Hold Time 1
9.0
0
—
4.0
—
—
—
—
30
—
ms
ms
µs
µs
µs
µs
µs
ms
T2
Program mode setup time
Clock high time
TCLKH
TCLKL
TDH
TDS
TDV
TWC
50
50
30
0
Clock low time
Data hold time
Data setup time
Data out valid time
Program cycle time
—
50
DS41256A-page 18
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.2 Timing Requirements for Program/Verify Mode – Transponders
Standard Operating Conditions (unless otherwise
stated)
AC/DC CHARACTERISTICS
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
Sym
Characteristics
Min
Max
Units
Conditions/Comments
HCS410, HCS412
TAS
ACK start time
100
50
50
20
20
—
—
—
—
—
—
20
—
—
—
5
µs
µs
µs
µs
µs
µs
ms
µs
ms
ms
ms
TCLKH
TCLKL
TDH
Clock high time
Clock low time
Data hold time
TDS
Data stable time
TDV
Data valid time
TPH1
TPH2
TPROG
TPS
Program Hold Time 1
Program Hold Time 2
Bulk write time
4
100
2.2
3
Program mode setup time
EEPROM write time
TWC
36
—
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 19
HCSXXX
5.3 Timing Requirements for Program/Verify Mode – Decoders
Standard Operating Conditions (unless otherwise
stated)
AC/DC CHARACTERISTICS
Operating Temperature +25°C ± 5°C
Operating Voltage
4.5V ≤ VDD ≤ 5.5V
Sugg.
Value
Sym
Characteristics
Min
Max Units Conditions/Comments
HCS500
FCLK
Clock frequency
—
—
—
—
—
—
—
—
—
—
—
500 25000 Hz
TACK
Decoder acknowledge time
Address validate time
Clock high time
30
10
µs
µs
µs
µs
µs
µs
µs
ms
ms
µs
TADDR
TCLKH
TCLKL
TCMD
TDATA
TDS
—
20
1000
1000
10
Clock low time
20
Command validate time
Command last bit to data first bit
Data hold time
—
—
10
14
—
TREQ
TRESP
TSTART
HCS512
TACK
Command request time
Acknowledge time
0.015
—
500
1
Command request to first command bit
20
1000
Acknowledge time
Acknowledge duration
Clock high time
—
—
—
—
—
—
—
—
1
80
—
ms FOSC = 4 MHZ
µs FOSC = 4 MHZ
µs FOSC = 4 MHZ
µs FOSC = 4 MHZ
ms FOSC = 4 MHZ
µs FOSC = 4 MHZ
ms FOSC = 4 MHZ
TACKH
TCLKH
TCLKL
TPH1
TPH2
TPS
0.05
0.05
8
320
320
128
320
64
Clock low time
Hold Time 1
Hold Time 2
0.05
1
Program mode setup time
HCS515
TACK
Command acknowledge time
Clock high time
*
30
20
240
1000
1000
1000
1000
500
ms
µs
µs
µs
µs
ms
µs
µs
µs
µs
TCLKH
TCLKL
TDATA
TDS
100
100
100
50
Clock low time
20
Command last bit to data first bit
Data hold time
10
14
TREQ
TRESP
TSTART
TWTH
TWTL
Command request time
Acknowledge time
*
0.005
10
100
100
100
100
1000
1000
1000
—
Command request to first command bit
Acknowledge respond time
Clock low to next command
Depends on decoder status.
20
20
10
*
DS41256A-page 20
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.4
Programming Waveforms (HCS200, HCS300, HCS301, HCS320, HCS362)
FIGURE 5-1:
PROGRAMMING WAVEFORMS
Enter Program
Mode
TPBW
TAS
TCLKH
TDS
S2
(Clock)
TWC
TDH
TPS
TPH1
TCLKL
PWM
(Data)
bit 0 bit 1 bit 2 bit 3
bit 14
bit 15
bit 16
bit 17
Data for Word 0 (KEY_0)
Data for Word 1 (KEY_1)
TPH2
Repeat for each word (12 times)
Ack
Pulse
Note 1: Unused button inputs to be held to ground during the entire programming sequence.
FIGURE 5-2:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
TWC
S2 (S3)
(Clock)
PWM
(Data)
bit 190 bit 191
bit 3
bit 14
bit 15
bit 16 bit 17
bit 1 bit 2
TDV
bit 190 bit 191
bit 0
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 21
HCSXXX
5.5
Programming Waveforms (HCS201)
FIGURE 5-3:
PROGRAMMING WAVEFORMS (HCS201)
Initiate Data
Polling Here
Enter Program
TCLKH
Mode
TPBW
TPHOLD
TCLKL
TDS
S2
(Clock)
T
ACKLTACKH
TPS TPH1
TWC
TDH
bit 0 bit 1 bit 2 bit 3
TCLKL
DATA
(Data)
Ack
Calibration Pulses
Ack
Ack
bit 14
bit 15
bit 17
bit 16
Data for Word 1
TPH2
Write Cycle
Complete Here
Repeat for each word (12 times)
S0 and S1 button inputs to be held to ground during the entire programming sequence.
Note:
FIGURE 5-4:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
DATA
Ack
bit 190 bit 191
bit 0 bit 1 bit 2 bit 3
TDV
bit 14
bit 15
bit 16 bit 17
bit 190bit 191
(Data)
TWC
S2
(Clock)
Note:
If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 22
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.6
Programming Waveforms (HCS360, HCS361)
PROGRAMMING WAVEFORMS
FIGURE 5-5:
Enter Program
Acknowledge Pulse
bit 16 bit 17
Mode
TWC
DATA
(Data)
bit 0 bit 1 bit 2 bit 3
bit 3
bit 14 bit 15
bit 14 bit 15 bit 0 bit 1 bit 2
TCLKH
T2
TCLKL
TDH
S2/S3
(Clock)
T1
TDS
bit 0 of Word 0
S1
Data for Word 1
Data for Word 0 (KEY_0)
Repeat for each word
Note 1: Unused button inputs to be held to ground during the entire programming sequence.
2: The VDD pin must be taken to ground after a Program/Verify cycle.
FIGURE 5-6:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word0
DATA
bit 2 bit 3
bit 1
bit 15
Ack
bit 0
bit 14
bit 16 bit 17
bit 190 bit 191
bit 190 bit 191
(Data)
TWC
TDV
S2/S3
(Clock)
S1
Note 1:
A Verify sequence is performed only once immediately after the Program cycle.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 23
HCSXXX
5.7
Programming Waveforms (HCS410, HCS412)
FIGURE 5-7:
PROGRAMMING WAVEFORMS
Enter Program
Mode
TPBW
TAS
TCLKH
TDS
S2
(Clock)
TWC
TDH
TPS
TPH1
TCLKL
PWM
(Data)
bit 0
bit 1 bit 2 bit 3
bit 14 bit 15
bit 16 bit 17
Data for Word 0 (KEY_0)
Data for Word 1 (KEY_1)
TPH2
Repeat for each word (18 times)
Ack
Pulse
Note 1:
2:
Unused button inputs to be held to ground during the entire programming sequence.
The VDD pin must be taken to ground after a Program/Verify cycle.
FIGURE 5-8:
VERIFY WAVEFORMS
End of Programming Cycle
Beginning of Verify Cycle
Data from Word 0
TWC
S2 (S3)
(Clock)
PWM
(Data)
bit 0
bit 206
bit 207
bit 2
bit 3
bit 14
bit 15
bit 16
bit 17
bit 1
bit 206
bit 207
TDV
Note: If a Verify operation is to be done, then it must immediately follow the Program cycle.
DS41256A-page 24
Preliminary
2004 Microchip Technology Inc.
HCSXXX
5.8
Programming Waveforms (HCS500)
FIGURE 5-9:
PROGRAMMING WAVEFORMS
TCLKL
TCMD
TADDR
TDATA
TDATA
TACK
TWT2
TPP3
TPP1
TCLKH
TDS
CLK
µC Data
LSb
MSb
LSb
MSb
MSb
MSb
LSb
TPP2
TPP4
TAW
Decoder
Data
Start Command
Command Byte
Configuration Byte Least Significant Byte
Most Significant Byte Acknowledge
G H
A
B
C
D
E
F
5.9
Programming Waveforms (HCS512)
FIGURE 5-10:
PROGRAMMING WAVEFORMS
MCLR
TCLKL
TACK
TACKH
TPS
TPH1
TPH2
TCLKH
CLK
(Clock)
DAT
bit 0
bit 1
bit 78 bit 79
Ack
(Data)
Acknowledge
pulse
Enter Program Mode
80-bit Data Package
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 25
HCSXXX
5.10 Programming Waveforms (HCS515)
FIGURE 5-11:
PROGRAMMING WAVEFORMS
TCLKL
TCLKH
TSTART
TDATA
TDATA
TDATA
TDATA
TACK
TREQ
CLK
TWTH
TDS
µC Data
LSb
LSb
MSb
LSb
MSb
MSb
LSb
MSb
TRESP
HCS515
TWTL
Data
Start Command
Acknowledge
Command Byte
Configuration Byte
LSb
MSb
D
E
G
H
A
B
C
F
Note:
The programming command consists of the following:
•
•
•
•
•
Command Request Sequence (A to B)
Command Byte (B to C)
Configuration Byte (C to D)
Manufacturer’s Code Eight Data Bytes (D to G)
Activation and Acknowledge Sequence (G to H)
DS41256A-page 26
Preliminary
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
Preliminary
DS41256A-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Korea - Seoul
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Boston
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Dallas
Addison, TX
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Tel: 972-818-7423
Fax: 972-818-2924
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shunde
Detroit
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS41256A-page 28
Preliminary
2004 Microchip Technology Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明