HV53011T-E/KVX [MICROCHIP]
16-Channel ±135V Push-Pull Driver with RTZ;
| 型号： | HV53011T-E/KVX |
| 厂家： | 
MICROCHIP |
| 描述： | 16-Channel ±135V Push-Pull Driver with RTZ |
| 文件： | 总32页 (文件大小：1575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV53011
16-Channel ±135V Push-Pull Driver with RTZ
Features
General Description
• 16-Channel Push-Pull Output
HV53011 is a high-voltage driver solution for surface
haptic applications. It consists of 16 push-pull drivers
capable of ±135V output swing with Return-To-Zero
(RTZ) function. Each output driver is capable of sourc-
ing and sinking at least 24 mA. Each high-voltage out-
put is capable of driving up to 250 pF capacitive load. A
global current sensor function is also integrated into
this device to monitor the charge and discharge cur-
rents. The measured current is mapped to a low volt-
age analog output with a scale factor of 3.1 V/V via a
current-sensing resistor.
• Return-To-Zero (RTZ) and High Impedance (Hi-Z)
Function
• Up to ±135V Output Voltage
• 24 mA Minimum Source Sink Output Current
• 250 pF Maximum Output Load
• Current Sensor Output
• SPI Interface with Quad-Latched 2-Bit per
Channel Architecture
• Power-On Reset Function
• Shutdown Function
An SPI interface is used to communicate between the
microcontroller/processor and the high-voltage drivers.
This interface accepts 3.3V logic I/O signals up to clock
speeds of 32 MHz. Five digital LATCH control signals
manage the data flow and the firing pattern. It estab-
• 59-Ball 8 x 8 mm TFBGA Package
Application
lishes the output to one of four possible states: VPP
VNN, 0V or high impedance.
,
• Surface Haptic Application
• MEMS Driver
A proper power on and off sequence is critical to
ensure the operation of the high-voltage driver. This
• Piezo Driver
driver requires four high-voltage power rails, VPP, VPF
,
VNN, VNF, and three low-voltage power rails, VCC, VSS
and VLL. A companion integrated driver IC, HV53001,
has a built-in power on/off sequence control circuits to
maintain the proper orders.
A shutdown function is available to disable the driver
and set it to consume minimum power when the driver
is not used.
The HV53011 device is packaged in a 8 x 8 mm
59-ball TFBGA package. All high-voltage I/Os are
assigned to have sufficient clearance for safety
purposes.
2021 Microchip Technology Inc.
DS20006519A-page 1
HV53011
Typical Application Diagram
SHDN
LATCHA,B,C,D
GPIOs
4
LATCHIN
32
32
32
32
32
32
32
32
Surface
Haptics
Element
4
2
2
HVOUT
0
1
SS
HVOUT
SCK
SPI
SDI
32
SDO
2
2
HVOUT14
HVOUT15
VPPSENSE
Analog
IPP and INN
Current Sensors
VNNSENSE
Inputs
HV53011
DS20006519A-page 2
2021 Microchip Technology Inc.
HV53011
Package Types (Top View)
HV53011
8 x 8 TFBGA*
9
1
2
3
4
5
6
7
8
10
11
A
HV
1
HV
5
6
HV
4
HV
3
HV
2
HV
OUT
0
OUT
A
B
OUT
OUT
OUT
OUT
B
VPP
SENSE
HV
OUT
LATCHD
SS
SHDN
V
V
FILP
C
D
E
LL
PPO
C
D
E
HVGND LATCHC
HVGND LATCHB
SDI
Reserved
V
CC
SDO
SCK
HVGND
V
V
V
HV
7
SS
PF
PP
OUT
VNN
LATCHA
SENSE
HVGND HVGND
F
F
NC
NC
LATCHIN HVGND HVGND HVGND
HVGND HVGND HVGND HVGND
V
V
G
NF
NN
HV
HV
HV
8
9
G
OUT
H
J
H
J
HVGND HVGND HVGND HVGND HVGND
V
FILN
OUT
NNO
K
L
K
L
HV
11
10
HV
12
HV
13
HV
14
HV
15
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
* see Table 2-1.
2021 Microchip Technology Inc.
DS20006519A-page 3
HV53011
Block Diagram
VPP
VPF
VNF
VNN
Logic voltage
supply
VPF VPP VNN VNNO VPPO
Sensor Circuit
FILN FILP
VLL
VNF
HV53011
VCC
VCC
VSS
VNNSENSE
VPPSENSE
VSS
POR
actuator
High Voltage Die
LATCHIN
LATCHA
LATCHB
LATCHC
LATCHD
LATCHIN
HVOUT
0
LATCHA
LATCHB
LATCHC
LATCHD
Control
Logic
HVOUT15
SPI
Interface
SDI SDO SCK SS
HVGND
SHDN
DATA FROM MCU
DS20006519A-page 4
2021 Microchip Technology Inc.
HV53011
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
High Positive Supply Voltage (VPP) .......................................................................................................... -0.3V to +140V
High Negative Supply Voltage (VNN)......................................................................................................... -140V to +0.3V
High Positive Floating Supply Voltage (VPF).......................................................................................... VPP - 14V to VPP
High Negative Floating Supply Voltage (VNF).......................................................................................VNN to VNN + 14V
Analog Low Positive Voltage Supply (VCC)................................................................................................ -0.3V to +8.0V
Analog Low Negative Voltage Supply (VSS) ............................................................................................. -8.0V to +0.3V
Logic Voltage Supply (VLL) ........................................................................................................................ -0.3V to +4.0V
Logic Input Levels (Hi-V Driver, SPI interface, LATCHx and SHDN) ...................................................-0.3V to VLL +0.3V
Maximum Junction Temperature (TJ(MAX))............................................................................................................ +125°C
Storage Temperature ..............................................................................................................................-65°C to +150°C
ESD Rating on Low Voltage Pins (Human Body Model)............................................................................................2 kV
ESD Rating on Low Voltage Pins (Charged Device Model).....................................................................................500 V
ESD Rating on High Voltage Pins (Human Body Model).........................................................................................500 V
ESD Rating on High Voltage Pins (Charged Device Model)....................................................................................500 V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1:
OPERATING SUPPLY VOLTAGES
Electrical Specifications: Unless otherwise specified: TA = TJ = +25°C. Boldface specifications apply over the
TA = TJ = range of -40°C to +125°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Note 1
V
V
High Positive Supply Voltage
High Negative Supply Voltage
VPP
VNN
48
135
-48
-135
Low Positive Supply Voltage
(High Voltage Driver)
V
V
V
VCC
VSS
VLL
6.0
-6.5
3.0
6.5
-6.0
3.3
7.0
-5.5
3.6
Low Negative Supply Voltage
(High Voltage Driver)
Logic Input Supply Voltage
(SPI Interface)
Negative Floating Supply Voltage
Positive Floating Supply Voltage
High-Level Input Logic Voltage
Low-Level Input Logic Voltage
VNN + 9V
VPP-13.2V
0.8 VLL
0
-
-
VNN+13.2V
VPP - 9V
V
V
V
V
VNF
VPF
VIH
VIL
0.2 VLL
Note 1: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006519A-page 5
HV53011
TABLE 1-2:
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA = TJ = -40°C to 125°C. Typical values are at +25°C.
VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise
specified.
Parameter
Sym.
Min.
Typ.
Max.
5.6
Units
Conditions
High Voltage Driver
Quiescent VPP Supply Current
(Sum of Current at VPP and
VPPO pins)
IPPQ
3.7
mA
mA
Quiescent VNN Supply Current
(Sum of Current at VNN and
VNNO pins)
INN
Q
-5.8
-5.2
-3.8
Quiescent VPF Supply Current
(Source)
IPF
Q
Q
-3.6
3.7
mA
mA
Quiescent VNF Supply Current
(Source)
INF
5.4
0.4
Quiescent High Voltage Positive
Supply Resultant Current,
I
PPRQ
mA
mA
IPPQ+ IPF
Q
Quiescent High Voltage
Negative Supply Resultant
INNR
Q
-0.4
-7.5
Current, INNQ+ INF
Q
VPP Supply Current
(Sum of current at VPP and
VPPO pins)
V
PP=+90V, VNN=-90V,
IPP
7.5
mA
mA
VPF=+78V, VNF=-78V,
fHVOUT = 20 kHz,CL=
250 pF, Running two
channels. Test pattern =
Figure 1-3 with 12.5 s
pulse width
VNN Supply Current
(Sum of current at VNN and
VNNO pins)
INN
V
PP=+90V, VNN=-90V,
High Voltage Positive Supply
Resultant Current, IPP + IPF
IPPR
INNR
IPF
2
mA
mA
mA
mA
VPF=+78V, VNF=-78V,
fHVOUT = 20 kHz,CL=
250 pF, Running two
channels. Test pattern =
Figure 1-3 with 12.5 s
pulse width
High Voltage Negative Supply
Resultant Current, INN + INF
-2
VPP = +90V, VNN= -90V,
VPF= + 78V, VNF= -78V,
fHVOUT = 20 kHz,
CL= 250 pF,
Running two channels.
Test pattern =
VPF Operating Supply Current
VNF Operating Supply Current
-5.5
INF
5.5
Figure 1-3 with 12.5 μs
pulse width
Note 1: Recommended operating conditions: VLL = +3.3V, VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V
all input pins = 0V unless noted. TJ = 25°.C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006519A-page 6
2021 Microchip Technology Inc.
HV53011
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA = TJ = -40°C to 125°C. Typical values are at +25°C.
VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise
specified.
Parameter
Sym.
Min.
-0.2
Typ.
Max.
0.2
Units
Conditions
V
PP=+90V, VNN=-90V,
VPF=+78V, VNF=-78V,
Test pattern =
Figure 1-3 with 12.5 s
pulse width
VCC Operating Supply Current
VSS Operating Supply Current
ICC
mA
ISS
mA
mA
VLL = +3.3V
SCK = 32 MHz,
SDI = 16 MHz pulse
train
VLL Operating Supply Current
ILL
25
VNF Negative Floating Supply
Voltage
VNN+9V
VNN+13.2V
VPP-9V
VNF
-
-
V
V
VPF Positive Floating Supply
Voltage
VPP-13.2V
VPF
VPP = +90V, VNN= -90V,
VPF = +78V, VNF= -78V,
CL= 250 pF,
Testpattern=Figure 1-3
with 12.5 μs pulse width
HVOUT Switching Frequency
fHVOUT
0
25
kHz
mA
VPP = +90V,
VNN = -90V,
VPF= +78V,
VNF = -78V
HVOUT Output Source and Sink
Current
IHVOUT
24
40
VPP = +90V,VNN = -90V,
VPF= +78V,VNF = -78V,
V/s VCC= +6.5V,VSS= -6.0V
Return-To-Zero Slew Rate
90% to 10%
(i) from VPP to 0V
(ii) from VNN to 0V
SR
100
200
CL = 250 pF
V
PP = +135 V,
Delay Time for Output to Start
Rise/Fall
(from LATCHA, B, C, D to
VNN = -135 V,
VCC= 6.5V, VSS = -6.0V
No load (Note 3)
td(ON/OFF)
100
40
ns
1V HVOUT
)
Variation of Delay Time
(Channel to Channel)
td
ns
V
Note 3
Shutdown Pin Input Enable
Voltage
VIH(SHDN)
2.5
VPPSENSE and VNNSENSE Current Sensor
Note 1: Recommended operating conditions: VLL = +3.3V, VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V
all input pins = 0V unless noted. TJ = 25°.C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006519A-page 7
HV53011
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA = TJ = -40°C to 125°C. Typical values are at +25°C.
VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise
specified.
Parameter
Sym.
Min.
0
Typ.
Max.
3.6
Units
Conditions
VPP = +135V,
VNN = -135V,
VCC = +6.5V,
VSS = -6.0V,
VPP - VPPO = 1.0V,
VNNO - VNN = 1.0V
Vout
VPPSENSE/VNNSENSE
Output Voltage
V
(VPPSENSE/
VNNSENSE)
VPP = +135V,
VNN = -135V,
VCC = +6.5V,
VSS = -6.0V,
VPP-VPPO and
VNNO-VNN: from 0.1 to
1.0V
Voltage Gain of Current Sensor
Sensing Amplifier Output Offset
AVSENSE
-14%
-280
3.1
+14%
+280
V/V
mV
VPP = +135V,
VNN = -135V,
VCC = +6.5V,
VSS = -6.0V,
VPP-VPPO and
VNNO-VNN: from 0.1 to
1.0V
VOS
(Note 3)
VPP = +90V,
VNN = -90V,
VCC = +6.5V,
300
ns
VSS = -6.0V, CL = 3 pF,
Test pulse: 1V, 1 μs
pulse width
1. VPP and VPPO
2. VNN and VNNO
Rise Time
(Time from 10% to 90% of
targeted value)
tR
VPP = +90V,
VNN = -90V,
VCC = +6.5V,
VSS = -6.0V, CL = 20 pF,
Test pulse: 1V, 1 μs
pulse width
740
ns
1. VPP and VPPO
2. VNN and VNNO
RLOAD
CLOAD
10
M
Note 2
Note 2
VPPSENSE/VNNSENSE
Output Load
3
pF
SPI Interface
Digital Input Clock Frequency
High-Level Input Logic Voltage
Low-Level Input Logic Voltage
Logic I/O Pin Rise and Fall Time
fCLK
VIH
32
MHz 3.3V logic input
0.8VLL
0
V
V
VIL
0.2VLL
tR, tF
5
ns
CL = 15 pF (Note 3)
Note 1: Recommended operating conditions: VLL = +3.3V, VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V
all input pins = 0V unless noted. TJ = 25°.C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006519A-page 8
2021 Microchip Technology Inc.
HV53011
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA = TJ = -40°C to 125°C. Typical values are at +25°C.
VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V, VLL = +3.3V unless otherwise
specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Note 2
Sourced by any standard I/O pin
Sunk by any standard I/O pin
Isource
Isink
10
10
mA
mA
Note 2
SPI Quiescent Current of Low
Voltage Supplies with Shut-
down asserted
In shutdown mode.
All logic input = 0V.
V(SHDN) = VLL
I
LLQ
100
1
A
SCK = 32 MHz and
SDI = 16 MHz pulse
train.
Time to Enter and Exit
Shutdown
tSHDN
ms
Time from Chip Select and SPI
data
Refer to Figure 1-1
(Note 2)
tWAIT
tPKT
20
4
50
-
-
-
-
ns
s
ns
Time to Transfer 128 Bits of
Data
Refer to Figure 1-1
(Note 2)
Time from Last Clock Pulse to
LATCHIN
Refer to Figure 1-1
(Note 2)
tH(LAT)
20
50
Digital Interface
Refer to Figure 1-2
(Note 2)
Time SPI Latch Held Low
tab
tac
tae
tak
tgk
tmn
trs
20
10
-
50
12
10
50
50
50
100
10
-
-
ns
s
ns
ns
ns
ns
ns
ns
Refer to Figure 1-2
(Note 2)
Time Between SPI Latches
Time from SPI Latch Assert to
Data Valid
Refer to Figure 1-2
(Note 2)
20
-
Time from SPI Latch to Data
Latch
Refer to Figure 1-2
(Note 2)
20
20
20
80
-
Refer to Figure 1-2
(Note 2)
Time Latch Signal Held High
Time Latch Signal Held Low
-
Refer to Figure 1-2
(Note 2)
-
Time Between Two Data Latch
Events
Refer to Figure 1-2
(Note 2)
-
Propagation Delay from Data
Register to Output Register
Refer to Figure 1-2
(Note 2)
tkv
20
Note 1: Recommended operating conditions: VLL = +3.3V, VCC = +6.5V, VSS = -6.0V, VPP = +135V, VNN = -135V
all input pins = 0V unless noted. TJ = 25°.C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006519A-page 9
HV53011
TEMPERATURE SPECIFICATIONS
Electrical Specifications: VPP = +135V, VNN = -135V, VPF = +123V, VNF = -123V, VCC = +6.5V, VSS = -6.0V,
VLL = +3.3V unless otherwise specified.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Junction Temperature Range
Storage Temperature Range
TJ
-40
-65
—
—
+125
+150
°C
°C
TA
Package Thermal Resistance
Thermal Resistance, 59B 8x8 TFBGA
JA
—
33.7
—
°C/W
DS20006519A-page 10
2021 Microchip Technology Inc.
HV53011
1.1
Timing Diagrams
SS
SCK
SDI
tWAIT
128 bits valid data
tPKT
tH(LAT)
LATCHIN
FIGURE 1-1:
SPI and LATCHIN Timing Diagram.
tac
tab
LATCHIN
Register D
Register C
Register B
Register A
LATCHA
c
a
b
SPI buffer bit 127:96
e
tae
SPI buffer bit 95:64
SPI buffer bit 63:32
SPI buffer bit 31:0
g
k
tak
tgk
tmn
LATCHB
m
n
LATCHC
s
trs
LATCHD
r
Output
v
Reg A
Reg D
Reg C
Reg B
Reg B
tkv
Register
w
HV Output
Reg A
Reg D
Reg C
tkw
FIGURE 1-2:
LATCHA, B, C, D and High Voltage Output Timing Diagram.
2021 Microchip Technology Inc.
DS20006519A-page 11
HV53011
FIGURE 1-3:
High Voltage Output Test Pattern.
DS20006519A-page 12
2021 Microchip Technology Inc.
HV53011
1.2
Typical Performance Curves
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-4:
Typical HV
Output
FIGURE 1-5:
Typical HV
from 0V to
OUT
OUT
Waveform V =135V, V =-135V,
135V, Load = 100 pF
PP
NN
Load = 100 pF.
FIGURE 1-6:
Typical HV
from 135V to
FIGURE 1-7:
Typical HV
from 0V to
OUT
OUT
0V, Load = 100 pF.
-135V, Load = 100 pF.
FIGURE 1-8:
Typical HV
from -135V
FIGURE 1-9:
Typ. HV
Rise Time
OUT
OUT
to 0V, Load = 100 pF.
Distribution, from 0V to 90V, Load = 250 pF.
2021 Microchip Technology Inc.
DS20006519A-page 13
HV53011
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-10:
Typ. HV
Fall Time
FIGURE 1-11:
Typ. HV
Fall Time
OUT
OUT
Distribution, from 90V to 0V, Load = 250 pF.
Distribution, from 0V to -90V, Load = 250 pF.
FIGURE 1-12:
Typ. HV
Rise Time
FIGURE 1-13:
Typical VNNSENSE
OUT
Distribution, from -90V to 0V, Load = 250 pF.
Buffered Output, V =135V, V =-135V,
PP
NN
Load=100pF, 6.04 ohm sense resistor, four
channels active.
FIGURE 1-14:
Typical VPPSENSE
buffered output, V = 135V, V = -135V,
Load=100 pF, 6.04 ohm sense resistor, four
channels active.
FIGURE 1-15:
Channel-to-Channel Delay.
Typical HV
OUT
PP
NN
DS20006519A-page 14
2021 Microchip Technology Inc.
HV53011
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-16:
Typical LATCHA to HV
FIGURE 1-17:
Typical LATCHB to HV
OUT
OUT
Propagation Delay
Propagation Delay
FIGURE 1-18:
Typical LATCHC to HV
FIGURE 1-19:
Typical LATCHD to HV
OUT
OUT
Propagation Delay
Propagation Delay
FIGURE 1-20:
Typical SDO output Rise
Time and Fall Time
2021 Microchip Technology Inc.
DS20006519A-page 15
HV53011
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin
PIN FUNCTION TABLE
Symbol
Description
E11
C9
G11
J9
VPP
VPPO
VNN
Positive High-Voltage Supply
Positive High-Voltage Current Sense
Negative High-Voltage Supply
Negative High-Voltage Current Sense
Positive Low-Voltage Supply
Negative Low-Voltage Supply
VLL Logic Voltage
VNNO
VCC
D7
E7
VSS
C7
VLL
J3-7, H4-7,G5-7,
F6-7, E6, D3, E3
HVGND
High-Voltage Ground
E9
G9
J11
C11
C3
F3
G3
H3
A11
A9
A7
A5
A3
A1
C1
E1
G1
J1
VPF
VNF
Positive floating voltage supply reference to VPP level
Negative floating voltage supply reference to VNN level
0.1 μF Capacitor across FILN and VNNO
FILN
FILP
0.1 μF Capacitor across FILP and VPPO
VPPSENSE Positive High-Voltage Sense Analog Output
VNNSENSE Negative High-Voltage Sense Analog Output
NC
No connection (Do not connect. Keep the pin floating.)
No connection (Do not connect. Keep the pin floating.)
High-Voltage Output 0
NC
HVOUT0
HVOUT1
HVOUT2
High-Voltage Output 1
High-Voltage Output 2
HVOUT
3
High-Voltage Output 3
HVOUT4
HVOUT5
High-Voltage Output 4
High-Voltage Output 5
HVOUT
6
High-Voltage Output 6
HVOUT7
HVOUT8
High-Voltage Output 7
High-Voltage Output 8
HVOUT
9
High-Voltage Output 9
L1
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
SS
High-Voltage Output 10
High-Voltage Output 11
High-Voltage Output 12
High-Voltage Output 13
High-Voltage Output 14
High-Voltage Output 15
SPI Chip Select
L3
L5
L7
L9
L11
C5
D5
E5
F5
G4
F4
E4
D4
C4
SDI
SPI Data In
SDO
SPI Data Out (for daisy chain)
SPI Clock
SCK
LATCHIN
LATCHA
LATCHB
LATCHC
LATCHD
Latch SPI Data (SPI -> Latch A, B, C, D)
Latch A -> Output Register
Latch B -> Output Register
Latch C -> Output Register
Latch D -> Output Register
DS20006519A-page 16
2021 Microchip Technology Inc.
HV53011
TABLE 2-1:
Pin
PIN FUNCTION TABLE (CONTINUED)
Symbol
Description
C6
D6
SHDN
Shutdown Mode
Reserved Pin. Connect to Ground.
Reserved
2021 Microchip Technology Inc.
DS20006519A-page 17
HV53011
microcontroller or host processor. The SDI and SDO
are the data input and data output pins of the SPI shift
register buffer.
3.0
3.1
DEVICE DESCRIPTION
Serial Peripheral Interface
The SDI and SDO can be used to cascade multiple
HV53011 or HV53011 drivers together if only a single
SPI port is available. This SPI interface is compatible
with 3.3V logic input voltage with a maximum clock fre-
quency of 32 MHz.
The SPI interface is used to transfer data of the channel
settings from the microcontroller to the high-voltage
driver. The HV53011 operates as an SPI slave device
and receives 128 bits of data from the master device
(microcontroller). The HV53011 SPI interface is
designed to be compatible with all Microchip 8-bit,
16-bit and 32-bit SPI data transmission formats. This
SPI interface has a 128-bit shift register buffer to store
128 bits of data.
The SPI shift register captures the data at the SDI input
in the rising edge of the SCK clock and pushes out the
data from the buffer to the SDO output in the falling
edge of the SCK clock. When the SPI bus is at idle sta-
tus, the SS pin stays in logic “1” and the SCK clock is
expected to stay at “0”.
The SS pin is a chip select function which is similar to
the enable function to guard the clock and data input
signal. The SCK contains the bus clock signal from the
SS
SCK
ReceiveꢀDataꢀtoꢀSPIꢀShiftꢀRegisterꢀBuffer
SDI
TransmitꢀDataꢀfromꢀSPIꢀShiftꢀRegisterꢀBuffer
SDO
FIGURE 3-1:
SPI Signal Diagram.
The bit order of the SDI data input is defined as follows.
The first and second data bits represent bit 1 and bit 0
of channel 15 in register D, respectively. The third and
fourth bits represent bit 1 and bit 0 of channel 14 in reg-
ister D. The similar pattern is extended all the way to
channel 0. Hence, there are 32 data bits to control
register D to cover all sixteen channels.
The next 32 data bits are arranged in the same fashion
for register C. Similarly, the exact pattern repeats itself
for register B and A. Since each register (A, B, C and
D) contains 32 bits of data, the SPI shift register buffer
is 128 bits long.
Bit 1 of channel 15 in register D is defined as the MSb
(Most Significant bit) and bit 0 of channel 0 in register
A as the LSb (Least Significant bit) in this SPI shift
register buffer definition.
MSb
LSb
FIGURE 3-2:
SPI Bit Pattern Diagram.
DS20006519A-page 18
2021 Microchip Technology Inc.
HV53011
The following table shows the summary of the SPI shift
register buffer.
TABLE 3-1:
Sym
REGISTER LEGEND
Description
Sym
Description
Cleared by Hardware only
R
W
U
P
Readable bit
Writable bit
HC
HS
1
Set by Hardware only
Bit is set at Reset
Unimplemented bit, read as ‘0’
Programmable bit
Settable bit
0
Bit is cleared at Reset
Bit is unknown at Reset
S
x
C
Clearable bit
Example: R/W - 0 indicates the bit is both readable or writable, and reads ‘0’ after a Reset.
TABLE 3-2: SPI_SR 128-BIT BUFFER SUMMARY
Register
Name
Bit Range
Bit
Bit
Bit
101
Bit
Bit
99
Bit
Bit
97
Bit
127/119/111/ 126/118/110/ 125/117/109/ 124/116/108/ 123/115/107/ 122/114/106/ 121/113/105/ 120/112/104/
103
102
100
98
96
LATCHD
<127:120>
<119:112>
<111:104>
<103:96>
Bit Range
CH15<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH14<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH13<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH12<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
95/87/79/71
Bit
Bit
93/85/77/69
Bit
Bit
91/83/75/67
Bit
Bit
89/81/73/65
Bit
94/86/78/70
92/84/76/68
90/82/74/66
88/80/72/64
LATCHC
<95:88>
<87:80>
<79:72>
<71:64>
Bit Range
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
63/55/47/39
Bit
Bit
61/53/45/37
Bit
Bit
59/51/43/35
Bit
Bit
57/49/41/33
Bit
62/54/46/38
60/52/44/36
58/50/42/34
56/48/40/32
LATCHB
<63:56>
<55:48>
<47:40>
<39:32>
Bit Range
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
31/23/15/7
Bit
Bit
29/21/13/5
Bit
Bit
27/19/11/3
Bit
Bit
25/17/9/1
Bit
30/22/14/6
28/20/12/4
26/18/10/2
24/16/8/0
LATCHA
<31:24>
<23:16>
<15:8>
<7:0>
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
“11” = Driven to Ground. Since there are 16 channels
on each HV53011 device, a 32-bit output control
register is required.
3.2
Quad-Latched Two-Bit per
Channel Architecture
In the Quad-Latched 2-bit per channel architecture,
each channel is controlled by a 2-bit encoding for each
of the four possible states: “00” = (Hi-Z) high imped-
Four separate latched arrays (A, B, C, & D) hold four
possible 32-bit output configurations. The data is
loaded from the arrays into the output control register
by four separate external control signals (LATCHA, B,
C, D). When the output control register is being
ance, “01” = Pull-down to VNN, “10” = Pull-up to VPP
,
2021 Microchip Technology Inc.
DS20006519A-page 19
HV53011
updated using one of the latch signals, the output will
LATCHB, LATCHC and LATCHD) are used to control
the data selection of the high-voltage output from the
four 32-bit registers. The SPI interface and latch
functions are two independent operation blocks.
go to
a not driven state temporarily to avoid
shoot-through.
The data in these four latched arrays can be updated
using the SPI shift register buffer. The 128 bits of data
is first transmitted from the host processor to this
device via the SPI interface. The data format has been
discussed in the previous section. After this 128 bits
transaction has completed, the data will stay in the SPI
shift register buffer. Then the user sends an activation
signal at the LATCHIN pin to initiate the transfer of the
data from the SPI shift register to the four 32-bit regis-
ters (A, B, C and D).
To achieve some power savings when idling for a
period of time, a shutdown pin is available to reduce the
quiescent current draw as much as possible.
TABLE 3-3:
2-BIT CONTROL AND
OUTPUT VOLTAGE LOGIC
TABLE
CONTROL BITS
HVOUT OUTPUT
Bit 1
Bit 0
When the application requires more output channels,
the user can cascade more driver devices in a daisy
chain configuration. The SDO pin is used to pass the
data from the SPI shift register buffer to the cascaded
driver IC.
0
0
1
1
0
1
0
1
High Impedance (Hi-Z)
Driven Low (VNN
)
Driven High (VPP
)
Driven to Ground (0V)
The SPI signal pins (SCK, SS, SDI and SDO) are used
to control the data flow of the SPI shift register buffer.
The five latch control signals (LATCHIN, LATCHA,
SS
SCK
Clock Control
SDO
SDI
SPI 128 bits shift register buffer
32
32
32
32
LATCHIN
32-bit LATCHA
32
32-bit LATCHB
32
32-bit LATCHC
32
32-bit LATCHD
32
LATCHA,B,C,D
SWITCHES
4
32-bit OUTPUT CONTROL REGISTER
SHDN
FIGURE 3-3:
Quad-Latched Two Bits per Channel Architecture.
DS20006519A-page 20
2021 Microchip Technology Inc.
HV53011
TABLE 3-4:
LATCHIN
↓
QUAD-LATCHED TWO-BIT LOGIC STATE TABLE
LATCHA
LATCHB
LATCHC
LATCHD
Description
X
X
X
X
SPI bit[127:96] into Latch Register D
SPI bit[95:64] into Latch Register C
SPI bit[63:32] into Latch Register B
SPI bit[31:0] into Latch Register A
X*
X*
X*
X*
↓
X
↓
X
X
↓
X
X
X
↓
Register A to output
Register B to output
Register C to output
Register D to output
X
X
X
X
X
X
Note:
* = Delay LATCHX appropriately if a register update from LATCHIN is still in progress.
↓ = Negative edge-triggered.
X = Don’t care.
The difference amplifier accepts maximum input volt-
3.3
Driver Shutdown Mode
age of 1V. The amplifier gain of 3.1 amplifies this input
and send the output to the VPPSENSE and VNN-
SENSE pins. These amplifiers are designed using
high-voltage and high value resistors to minimize its
power consumption. These amplifier outputs are high
impedance in nature, so an external high bandwidth
(200 MHz) unity gain buffer is recommended. The high
bandwidth is needed to capture the fast current pulse
during the transition.
When the shutdown (SHDN) pin is at logic “1”, any
unnecessary circuit in the line driver will be disabled to
minimize power consumption. It includes the level
translator, bias current, voltage reference, driver out-
put, SPI interface, and combinational logic. During
shutdown, the quiescent current will be less than
100 μA. The system response time is less than 1 ms to
switch between shutdown and active modes when a
new signal is asserted at the shutdown pin.
The user selects the value of the sensing resistor to fit
the system requirement. The speed of the difference
amplifier is its highest priority because the charge or
discharge current appear in a short period of time. The
amplifier output accuracy is less important. Both
VPPSENSE and VNNSENSE outputs have a tolerance
of ±14%.
3.4
Driver Power On Reset
The Power-on Reset function resets all high-voltage
HVOUT output to high impedance when the device is
initially powered on. It also resets and clears the SPI
buffer registers, registers A, B, C and D to logic “0”.
3.5
Driver Output Current Sensing
Sense
Resistor
+135V
Some system designs require a load sensing function
to determine the size or any change of the capacitive
load. One simple scheme is to place a series current
sensing resistor on the power supply rail and measure
the voltage drop across this resistor. This solution is
very effective as long as the voltage drop is small
enough not to affect the operation of the system.
VPPO
VPP
V+
V-
Av
HVOUT
HVOUT
0
1
Difference
Amplifier
x3.1
VPPSENSE
The HV53011 driver IC provides this function by which
users can monitor the supply current flowing through
both high-voltage positive and negative supplies. Two
external current sensing resistors are connected to VPP
and VNN supply rails, respectively, as high side current
sensing. The voltage drop across these resistors are
fed to two pin pairs, VPP-VPPO and VNN-VNNO. Since
this voltage drop is referenced to the VPP and VNN sup-
ply rails, it is not practical for any low-voltage ADC to
measure this voltage. Hence, two internal difference
amplifiers in the driver IC convert these voltage drops
to ground reference.
(Reference to GND)
HVOUT14
HVOUT15
FIGURE 3-4:
Current Sensing Topology.
2021 Microchip Technology Inc.
DS20006519A-page 21
HV53011
TABLE 3-5:
Steps
ACCEPTABLE POWER-ON SEQUENCES
Description
1
2
3
4
5
Connect ground.
Keep shutdown pin to low.
Set all driver inputs to low.
Power-on supplies in this sequence: VLL, VNN, VNF, VSS, VCC, VPF and then VPP
Set all inputs to a known state.
TABLE 3-6:
Steps
ACCEPTABLE POWER-OFF SEQUENCES
Description
1
2
3
Set all inputs and shutdown pin to low.
Power-off supplies in this sequence: VPP, VPF, VCC, VSS, VNF, VNN and then VLL
.
Disconnect ground
DS20006519A-page 22
2021 Microchip Technology Inc.
HV53011
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
59-Ball TFBGA (8x8x1.2 mm)
Example
HV53011
2008256
Legend: XX...X Product Code or Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
e8
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e8
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
2021 Microchip Technology Inc.
DS20006519A-page 23
HV53011
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DS20006519A-page 25
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DS20006519A-page 26
2021 Microchip Technology Inc.
HV53011
APPENDIX A: REVISION HISTORY
Revision A (March 2021)
• Original Release of this Document.
2021 Microchip Technology Inc.
DS20006519A-page 27
HV53011
NOTES:
DS20006519A-page 28
2021 Microchip Technology Inc.
HV53011
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X-
X
/XXX
Examples:
a)
HV53011-E/KVX: 16-Channel, ±135V Push-Pull
Driver with RTZ. Thin Fine Pitch
Media Type Temperature
Tape and Reel Range
Package
Ball Grid Array, 59-Ball TFBGA (8
x 8 x 1.2mm) Package, 260/Tray
b)
HV53011T-E/KVX:16-Channel, ±135V Push-Pull
Driver with RTZ. Thin Fine Pitch
Ball Grid Array, 59-Ball TFBGA (8x
8 x 1.2mm) Package, 1000/Reel
Device:
HV53011: 16-Channel, ±135V Push-Pull Driver with RTZ
Media Type:
blank = 260/Tray for KVX Package
T
= 1000/Reel for KVX Package
Temperature
Range:
E
=-40°C to +125°C (Extended) RoHS Compliant
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
KVX = Thin Fine Pitch Ball Grid Array
59-Ball TFBGA (8 x 8 x 1.2 mm)
2021 Microchip Technology Inc.
DS20006519A-page 29
HV53011
NOTES:
DS20006519A-page 30
2021 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole
purpose of designing with and using Microchip products. Infor-
mation regarding device applications and the like is provided
only for your convenience and may be superseded by updates.
It is your responsibility to ensure that your application meets
with your specifications.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON-
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
PARTICULAR PURPOSE OR WARRANTIES RELATED TO
ITS CONDITION, QUALITY, OR PERFORMANCE.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
WHATSOEVER RELATED TO THE INFORMATION OR ITS
USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES
ARE FORESEEABLE. TO THE FULLEST EXTENT
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP
FOR THE INFORMATION. Use of Microchip devices in life sup-
port and/or safety applications is entirely at the buyer's risk, and
the buyer agrees to defend, indemnify and hold harmless
Microchip from any and all damages, claims, suits, or expenses
resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, Espresso T1S,
EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-7930-7
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2021 Microchip Technology Inc.
DS20006519A-page 31
Worldwide Sales and Service
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DS20006519A-page 32
2021 Microchip Technology Inc.
02/28/20
相关型号：
HV5308DJ-B
AC Plasma Driver, 32-Segment, CMOS, CQCC44, 0.653 X 0.653 INCH, 0.190 INCH HEIGHT, 0.050 INCH PITCH, CERAMIC, MO-087AB, LCC-44
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